msm: pil-gss: Apply 8064v1.0 GSS QGIC bus workaround to secure PIL

On 8064v1.0 hardware, the secure PIL code will not release the A5
processor from reset as part of pas_auth_and_reset(). Instead,
Linux is expected to perform the GSS QGIC bus workaround after
pas_auth_and_reset() returns and then release the A5 reset itself
from non-secure context.

This is done to guarantee that the workaround is executed on Krait0,
while at the same time accommodating a secure-PIL implementation
under pas_auth_and_reset() that is shared with other high-level
operating systems.

Change-Id: Ibff9d85493cc190938ed829ed237982e8842e4c8
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>