msm_fb: display: change pixel sequence on lvds lanes

This is a s/w workaround to fix lvds phy h/w bug. On the rising edge
of lvds phy clk the phy transimits d0d1..d6 sequence, however, lvds
panel from the manufacture expects d6d5d0...d4. So s/w adjusts
the sequence on the phy side to meet panel spec.

CRs-fixed: 338715
Change-Id: If852ba29954b363911d04cd08d3784ce7d385c2f
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>