Commit 48aef6d5 authored by Pradeep Jilagam's avatar Pradeep Jilagam Committed by Bryan Huntsman
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msm_fb: display: Vote for AXI Clock for DSI on 7x27A 



Vote for a minimum rate of 65 MHz for AXI Clock while using
DSI interface on 7x27A

Signed-off-by: default avatarPradeep Jilagam <pjilagam@codeaurora.org>
parent 65ac922f
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