Commit 22e4b386 authored by Mayank Rana's avatar Mayank Rana
Browse files

msm_serial_hs_lite: set uart clock rate to zero after disabling clock 



Change-Id: Ib6413cae2ee32cd5e6c049f4a22ee24b808cb2fa
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
parent cf61df74
Show whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please to comment