HACK: drm/msm/mdp5: Set AXI clock to a high rate

On 8x96, we see underruns when trying to fetch 4K wide buffers
due to a low default AXI clock rate.
Increase AXI clock to 320 Mhz (only for 8x96) until we have
bus scaling sorted out on the platform.

Signed-off-by: Archit Taneja <architt@codeaurora.org>