Commit 472d090f authored by Mayank Chopra's avatar Mayank Chopra Committed by raghavendra ambadas
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msm_fb: display: Program TILE video frame size in dma ISR 



Since, video tile frame size register is single buffered, its
value takes effect as soon as it is programmed. Single buffered
registers like this should be configured very close to the vsync
to prevent issues like flicker or artifacts.
Program this register in dma ISR to prevent flickers and IOMMU
page faults.

Change-Id: Ifa770e4b4f29d6e4070e51388043422cc60e5872
Signed-off-by: default avatarMayank Chopra <makchopra@codeaurora.org>
parent b034891d
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