PCI: qcom: Fix pipe_clk_src reparenting

The hardware requires that pipe_clk_src is fed from TCXO when GDSC is
disabled. It can be fed from PHY's pipe_clk once GDSC is enabled (which
is what is done by the downstream driver).

Currently code does all clk_set_parent() calls after the
pm_runtime_get(), so the GDSC is already enabled.
Implement these requirements by moving pm_runtime_*() calls after
get_resources (so that get_resources() can ensure that the pipe clock
parent is TCXO).

Fixes: aa9c0df9 ("PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280")
Cc: Prasad Malisetty <pmaliset@codeaurora.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>