Commit a198e59d authored by Leonard Mosescu's avatar Leonard Mosescu
Browse files

Accurate VReg vs. VRegPair usage in the code IR

Dex bytecodes encode both single 32bit vreg fields and 64bit (wide) vreg pairs
the same way (for pairs the field contains the first vreg in the pair, ex. v4:v5 is
encoded simply as "v4"). The actual opcode (and not the instruction format!)
is implicitly interpreting the field as either 32bit or 64bit
(https://source.android.com/devices/tech/dalvik/dalvik-bytecode.html)

This is a bit problem if we want to track register usage so with this change we now
track the 32bit vregs vs. 64bit vreg pairs. For example, here's a bytecode sequence
dissasembled by dexdump:

    |0017: move-wide v2, v0
    |0018: neg-double v2, v2
    |0019: move-wide v0, v2
    |001a: return-wide v0

The same bytecode sequence dissasembled with dexter/slicer:

   23| move-wide v2:v3, v0:v1
   24| neg-double v2:v3, v2:v3
   25| move-wide v0:v1, v2:v3
   26| return-wide v0:v1

It's now clear that the first instruction writes to both v2 and v3 and not just v2
(and reads from v0 and v1, not just v0). This is needed to accurately track register
usage and interference.

Test: bazel test :dexter_tests

Change-Id: I7679849f45bfedb9d87ed1d8a2567b7e4b41e68c
parent 4beb6e36
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