Bug fix on shift that exceeds "lane width".

Rationale:
ARM is a bit less forgiving on shifting more than
the lane width of the SIMD instruction (rejecting
such cases is no loss, since it yields 0 anyway
and should be optimized differently).

Bug: 37776122
Test: test-art-target, test-art-host

(cherry picked from commit 65ffd8ef)

Change-Id: If65148eb0e8e705f48778549b7e31b8077cd233b