ART: Fix GenReduceVector and GenSetVector

For GenReduceVector:
We now correctly load non-wide values for non-wide destination registers,
and generate reg-reg and reg-mem forms of pextr correctly.

For GenSetVector:
We use the correct opcode from loading into an xmm from a 64-bit GPR

Change-Id: I0a01d1f0b12b32a0dee8f79a0139ffcf6d6cb4d5
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>