Commit 5192cbb1 authored by Yixin Shou's avatar Yixin Shou
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Load 64 bit constant into GPR by single instruction for 64bit mode 



This patch load 64 bit constant into a register by a single movabsq
instruction on 64 bit bit instead of previous mov, shift, add
instruction sequences.

Change-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c
Signed-off-by: default avatarYixin Shou <yixin.shou@intel.com>
parent 7a59a249
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