Commit 2e4fcc99 authored by Artem Serov's avatar Artem Serov Committed by Vladimir Marko
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ARM: Fix shifted register offset mem address mode for load signed. 

For example 'ldrsh r0, [sp, r1, LSL #2]' previously
was assembled as 'ldrh'.

Test: New test in assembler_thumb2_test.cc .
Change-Id: I1d30724f0c2745b131876bffefdc0a780d76f6a1
parent 4c489f48
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