- Aug 02, 2018
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Srinivas Ramana authored
Add cache, tlb and ram dump parsing support for steppe. Change-Id: I47f41ae0014340b284c60fd406f1ef8096521d46 Signed-off-by:Srinivas Ramana <sramana@codeaurora.org>
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- May 25, 2018
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Isaac J. Manjarres authored
Add TLB Dump Support for new target cores. Change-Id: Ic973a3d0a0e3e441bce1531af720ee1bad57e11c
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- Apr 06, 2018
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Shibin George authored
Add support for detecting SDM710 target and parsing the ramdumps. Change-Id: I8cf9e29e0019879da70c3d8c52813f09944ed176
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- Mar 01, 2018
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Kyle Yan authored
Add TLB dumps for L2 TLBs on Kryo3xx processors. Change-Id: Ic07df5bb7cac5a2799e01c5b271b34dfb1b240a4 Signed-off-by:Kyle Yan <kyan@codeaurora.org>
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- Oct 24, 2017
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Kaushal Kumar authored
Add support for detecting QCS605 target and parsing the ramdumps. Change-Id: I36197059621926f18a2649ea13e2537f5fe2081a
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- Sep 25, 2017
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Lingutla Chandrasekhar authored
Add board, cache and tlb dump parsing support for sdm670. Change-Id: I8d3299ff2ea31a492d6845d7bf192d358eb859c2 Signed-off-by:Lingutla Chandrasekhar <clingutla@codeaurora.org>
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- Mar 28, 2017
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Kyle Yan authored
Add TLB Dump Support for both KRYO3XX Gold and Silver Cores. Change-Id: I4e180f543bbbe743aa9c0143ffb1ca1d1117d120
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- Feb 08, 2017
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Runmin Wang authored
Add initial TLB dump support for msm8998 target. Change-Id: I6b1337a68241a6914eb05d5ab9d2844735f6a931
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