Correcting the A53 ICache dump format for parsing the instruction cache
dump.

Change-Id: Idc2d9dcba1a879461e4470fa9afdb162c50f251b

Add decoding information for LLC (System) cache.
Included LLC parse function.

Change-Id: Idd21a68eb6b8bf0cc63d79b640dc167fa78106a4

Add decoding information for L1 I/D caches for both Ananke
and Prometheus.

Change-Id: I0b6d0c6ad5171eef96f25d884db08780ae40cdad

Add Icache dump support for 8937,8917,8940 and 8920 targets.

Change-Id: I46dd4778ca973de870bf53a695485fe2b743d08a

Update the code name from msmfalcon/msmtriton to
sdm660/sdm630.

Change-Id: I5e0fcbb2399cac008b931eb5f641f6a1eadbd2ce

Describe the cache format used in msmfalcon.

Change-Id: I3e87b31fc4f67a6cbac3a362925a63d105664fcb

Update the target name according to the latest guidelines.

Change-Id: I6c8ae233213aed1a6b57fc1b4eaf8f7b7b81b98d
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>

Add support for detecting msm8940 and msm8920 target
and parsing the ramdumps and cachedumps.

Change-Id: I82ff0ffec41858937d08a3bc56fde4c50a642d8b

Update the correct cache dump table version to 0x14.

Change-Id: I909bd330c6a4c573a50ab10c549aea20374ee053

The board number is intended to be a human readable identification value.
Allowing this to be a string is more flexible.

CRs-Fixed: 1013327
Change-Id: If523acafc54f5026680d18c95e4899fb0436599d

Update the cache dump table version to be the supported version,
and Use the correct function to do ICache parsing.

CRs-Fixed: 1013312
Change-Id: I77f1e5edb106a2d906856f82295c6f9e4b573008

Describe the cache format used in msmcobalt.

CRs-Fixed: 983532
Change-Id: I4dc88fc7f29770e892a29a7e48e8a79d883c9b06

Describe the cache format used for 8937, 8953 and 8917.

Change-Id: Ie877173bc0fa6ea01e7daf1825720c5601a6f82a

Rename a variable to better describe its purpose.
Change the size of the L2 cache for 8992 to the correct value.
Update version information for 8994.

Change-Id: Ie0bf7e9ff257555cc40467918d258b05bf4c2ada

Describe the cache format used in 8992.

Change-Id: I40149802a68527b9b043a643f8d5c18b67916924

Decode the tag-ram according to the processor and cache type. Print
the decoded information alongside each cacheline in a table format.

Support A53 L1 Data Caches.
Support A57 L1 Instruction and Data Cache, L2 Cache.

Change-Id: I3e74affb69a91b1ca1399be604366e7f1fb0cd27