The stack and pointer sizes are different on arm64. Update
accordingly.

Change-Id: I262c79ea81671d97fd8bbc8343267cc3bc8c3d38
Acked-by: Kosuke Shitaba <kshibata@qti.qualcomm.com>

Consider the case of a nentries==8 and 3 cpus.
Numbers in parenthesis are the equivalent location in the circular buffer.
CPU:   Index0:  Index1: Index2: Index3:
0      0        3       6       9(1)
1      1        4       7       10(2)
2      2        5       8(0)

The current design is only appropriate for the case where
nentries % nrcpus == 0.

Fix this issue by incrementing the index by (nentries % nrcpus)
each time circular buffer wraps around.

CPU:   Index0:  Index1: Index2:
0      0        3       6+2==8(0)
1      1        4       7+2==9(1)
2      2        5       8+2==10(2)

Change-Id: I439fb540fc2c437c6b642d18aa9683603c270f36

The elf header file is different for arm64. Update it so that
the roareadiff feature can be used on 64bit targets.

Change-Id: Ica4424a6ea9d2e599e1a157353aa5f702a5e4bf8
Acked-by: Kosuke Shitaba <kshibata@qti.qualcomm.com>

The imem start address was missing for 9635. Add it.

Change-Id: Iea221df9f91e7d7ac54393f50ce0ea6b257e7a66

Add a parser which parses relevant thermal device information.

Change-Id: I4edde5a59ba5150cabc282716a42b7084dadda62

struct msm_dump_data contains the name of the entity who filled in the
data structure. Print out this information.

Change-Id: If490c0180bed22ba098d39e8e088170c9552da76

Describe the cache format used in 8992.

Change-Id: I40149802a68527b9b043a643f8d5c18b67916924

Add ipc_logging extraction script and documentation. This script is used
to extract IPC Logging data from memory dumps.

Change-Id: I5173ae394eea1d8f66592a73d61879fde4bb2e68

Handling few more error conditions while printing physical
addresses in RTB logs

Change-Id: Idfb75f4ed048d22dd3d8a6c69cd1e9187c9c94c2

Dump tv1 to tv5 timers for all the cores in the system.

Change-Id: I5df5b041e655fc28204a627a54dfd09e8d981c6e

Decode the tag-ram according to the processor and cache type. Print
the decoded information alongside each cacheline in a table format.

Support A53 L1 Data Caches.
Support A57 L1 Instruction and Data Cache, L2 Cache.

Change-Id: I3e74affb69a91b1ca1399be604366e7f1fb0cd27

prepare_count and count are 32-bit variables instead of 64-bit variables.

Change-Id: I7a0e81a5b7adc40d65ac9bec5be3763a10d23581

CPUMERRSR and L2MERRSR are CP15 registers so no need to set them in
core{X}_regs.cmm script.

Change-Id: I740ec7e96948b4fd887f1ae9095d663cc91601dd

Add support for detecting 9640 target and parsing the ramdumps

Change-Id: I085962bc75251b1f3e103546719119583d9baba5

Address the corner case where we end up in a continuous (almost
inifinite) loop when blk value equals rwpval. Change the
condition from blk < rwpval to blk <= rwpval to fix this.

Change-Id: I67923f3fa681e64eaff1821be7ae9805f66d47df

Add support for detecting 8992 target and parsing the ramdumps.

Change-Id: I06b88d67afdfea6a3c6867911c96ebe1317c2ce8

Add support for detecting 8908 target and parsing the ramdumps.

Change-Id: I9195e3ff47ed17ceffa2d634b3c827ea71d71559

Add a parser which parses relevant CPR regulator information
such as target quotient, enable flag and most recent voltage for
each registered cpr regulator.

Change-Id: I15432179a0cfd76575236be9c276f83a8ef7124e

Add support to parse PMIC register dump in debug image and
generate an XML file with PMIC registers information.

Change-Id: Ie0d85456711be48c8e8d5312e81712106868af4b