Correct the error.

Change-Id: Id466ba42d53789651acf13d45296329105c3117c

Add cache and tlb dump parsing support for Scuba.

Change-Id: I1b31fc0abe5d125187930feb9d868c0b2adf93d6

Add cache dump parsing support for Bengal.

Change-Id: Ida39a3ee5e6b4b0d3255bfef95601890afd80709

Add ramdump parser support for Atoll. Also, enable cachedump
and TLB dump parsing support.

Change-Id: Iff9b1e07d6befa384dbb70675d1e8fa083e52f55
Signed-off-by: Mayank Grover <groverm@codeaurora.org>

Add ramdump parser support for Lito. Also, enable cachedump
and TLB dump parsing support.

Change-Id: I4892ad3736f6d3f109f9eab1802faa77ecd550e5

Add cache and ram dump parsing support for
trinket.

Change-Id: I8269648a105eb575194c28b82bce6508bba0d0d8

Update target names, so that targets can be identified, and the
correct configurations are used when using the ramparser.

Change-Id: I254c65662943dd43f99fb12d22f1a17bc9f01283

Add cache, tlb and ram dump parsing support for
steppe.

Change-Id: I47f41ae0014340b284c60fd406f1ef8096521d46
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>

Add TLB Dump Support for new target cores.

Change-Id: Ic973a3d0a0e3e441bce1531af720ee1bad57e11c

Add support for detecting SDM710 target and parsing the ramdumps.

Change-Id: I8cf9e29e0019879da70c3d8c52813f09944ed176

Add TLB dumps for L2 TLBs on Kryo3xx processors.

Change-Id: Ic07df5bb7cac5a2799e01c5b271b34dfb1b240a4
Signed-off-by: Kyle Yan <kyan@codeaurora.org>

Add support for detecting QCS605 target and parsing the ramdumps.

Change-Id: I36197059621926f18a2649ea13e2537f5fe2081a

Add board, cache and tlb dump parsing support for sdm670.

Change-Id: I8d3299ff2ea31a492d6845d7bf192d358eb859c2
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>

Add TLB Dump Support for both KRYO3XX Gold and Silver Cores.

Change-Id: I4e180f543bbbe743aa9c0143ffb1ca1d1117d120

Add initial TLB dump support for msm8998 target.

Change-Id: I6b1337a68241a6914eb05d5ab9d2844735f6a931