Add cache dump parsing support for Bengal.

Change-Id: Ida39a3ee5e6b4b0d3255bfef95601890afd80709

Add ramdump parser support for Atoll. Also, enable cachedump
and TLB dump parsing support.

Change-Id: Iff9b1e07d6befa384dbb70675d1e8fa083e52f55
Signed-off-by: Mayank Grover <groverm@codeaurora.org>

Add System Cache slice dump parsing for Lito SoC.

Change-Id: I7796eb87001e9f52a34d9ae469369899184a6489

Add ramdump parser support for Lito. Also, enable cachedump
and TLB dump parsing support.

Change-Id: I4892ad3736f6d3f109f9eab1802faa77ecd550e5

Add cache and ram dump parsing support for
trinket.

Change-Id: I8269648a105eb575194c28b82bce6508bba0d0d8

Add cache, tlb and ram dump parsing support for
sdmmagpie in steppe target.

Change-Id: I0194e08c30f50839dbf06c7ce2d3e7906c1ba298
Signed-off-by: Prateek Sood <prsood@codeaurora.org>

Add correct cpu dump id for QCS405 and 403 to match with TZ SDI

Change-Id: Ia64fbd00a9cbf7fb886ca77020708acfd95acaa7
Signed-off-by: Archit Saxena <archsaxe@codeaurora.org>

Update target names, so that targets can be identified, and the
correct configurations are used when using the ramparser.

Change-Id: I254c65662943dd43f99fb12d22f1a17bc9f01283

Add cache, tlb and ram dump parsing support for
steppe.

Change-Id: I47f41ae0014340b284c60fd406f1ef8096521d46
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>

Add support for detecting QCS605 target and parsing the ramdumps.

Change-Id: I80e8e54340fe6fea0c6471570fbe45faf6920699
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>

Add support for detecting SDM429/SDA439/SDA429 target
and parsing the ramdumps.

Change-Id: I53168a87122b387d76452b0b9190a674122e3162
Signed-off-by: Jingbiao Lu <jingbiao@codeaurora.org>

Add decoding information for L1 I/D and L2 caches for
new target.

Change-Id: I6d947f8906797a2dcc247b4d5a8c38669ea87aa4

	board.py and cachedumplib file are modified to support sdm439 dump parsing

Change-Id: I15029ebf1b522903c000b82913362e466688ca42

Add support for detecting SDM710 target and parsing the ramdumps.

Change-Id: I8cf9e29e0019879da70c3d8c52813f09944ed176

Add support for detecting QCS605 target and parsing the ramdumps.

Change-Id: I36197059621926f18a2649ea13e2537f5fe2081a

Add board, cache and tlb dump parsing support for sdm670.

Change-Id: I8d3299ff2ea31a492d6845d7bf192d358eb859c2
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>

Changing the Last Level Cache (System Cache) dump
details according to their structures. Dumps have
been collected without structure padding

Change-Id: Ic34c4517df1399b16b16007a08932d5ffe6043b8

Updates LLCC client version number to 0x10

Change-Id: I4e80d912b0c959f39a31767c9a7002d87e2b6a7a

Change Client ID information for LLC (System) cache from 0x121 to 0x140.

Change-Id: Ieed438c7c1eb21e19e6d9d95ab14023ba6922f7c

Add support for detecting sdm450 target and parsing
the ramdumps and cachedumps.

Change-Id: I6d6626ff9827a7a85bbdbc4dbedab6974bdd7bb1

Initial commit of adding support for cache dump parsing in SDM845
contained syntax errors due to being unable to test on actual dumps.
Fix the cache parsing to deal with the errors.

Change-Id: I38dc3cebcd3ea7cfda1e6424fd4e19772b965570

Correcting the A53 ICache dump format for parsing the instruction cache
dump.

Change-Id: Idc2d9dcba1a879461e4470fa9afdb162c50f251b

Add decoding information for LLC (System) cache.
Included LLC parse function.

Change-Id: Idd21a68eb6b8bf0cc63d79b640dc167fa78106a4

Add decoding information for L1 I/D caches for both Ananke
and Prometheus.

Change-Id: I0b6d0c6ad5171eef96f25d884db08780ae40cdad

Add Icache dump support for 8937,8917,8940 and 8920 targets.

Change-Id: I46dd4778ca973de870bf53a695485fe2b743d08a

Update the code name from msmfalcon/msmtriton to
sdm660/sdm630.

Change-Id: I5e0fcbb2399cac008b931eb5f641f6a1eadbd2ce

Describe the cache format used in msmfalcon.

Change-Id: I3e87b31fc4f67a6cbac3a362925a63d105664fcb

Update the target name according to the latest guidelines.

Change-Id: I6c8ae233213aed1a6b57fc1b4eaf8f7b7b81b98d
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>

Add support for detecting msm8940 and msm8920 target
and parsing the ramdumps and cachedumps.

Change-Id: I82ff0ffec41858937d08a3bc56fde4c50a642d8b

Update the correct cache dump table version to 0x14.

Change-Id: I909bd330c6a4c573a50ab10c549aea20374ee053

The board number is intended to be a human readable identification value.
Allowing this to be a string is more flexible.

CRs-Fixed: 1013327
Change-Id: If523acafc54f5026680d18c95e4899fb0436599d

Update the cache dump table version to be the supported version,
and Use the correct function to do ICache parsing.

CRs-Fixed: 1013312
Change-Id: I77f1e5edb106a2d906856f82295c6f9e4b573008

Describe the cache format used in msmcobalt.

CRs-Fixed: 983532
Change-Id: I4dc88fc7f29770e892a29a7e48e8a79d883c9b06

Describe the cache format used for 8937, 8953 and 8917.

Change-Id: Ie877173bc0fa6ea01e7daf1825720c5601a6f82a

Rename a variable to better describe its purpose.
Change the size of the L2 cache for 8992 to the correct value.
Update version information for 8994.

Change-Id: Ie0bf7e9ff257555cc40467918d258b05bf4c2ada

Describe the cache format used in 8992.

Change-Id: I40149802a68527b9b043a643f8d5c18b67916924

Decode the tag-ram according to the processor and cache type. Print
the decoded information alongside each cacheline in a table format.

Support A53 L1 Data Caches.
Support A57 L1 Instruction and Data Cache, L2 Cache.

Change-Id: I3e74affb69a91b1ca1399be604366e7f1fb0cd27