lrdp_v2: clock info for kernel 4.4+

clock framework is changed in kernel 4.4.38+,
read clock vealue from different data structures based
on kernel version.

Change-Id: Ib40c41a1cee22795e924115090c4d90d2592cf56

linux-ramdump-parser-v2/parsers/clockdump.py

-# Copyright (c) 2015, The Linux Foundation. All rights reserved.
+# Copyright (c) 2015,2017 The Linux Foundation. All rights reserved.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License version 2 and
@@ -13,8 +13,9 @@ import linux_list
 from print_out import print_out_str
 from parser_util import register_parser, RamParser
 
+
 @register_parser('--clock-dump', 'Dump all the clocks in the system')
-class ClockDumps(RamParser) :
+class ClockDumps(RamParser):
 
     def __init__(self, *args):
         super(ClockDumps, self).__init__(*args)
@@ -118,14 +119,7 @@ class ClockDumps(RamParser) :
         clk_providers_walker = linux_list.ListWalker(self.ramdump, head, node_offset)
         clk_providers_walker.walk(head, self.clk_providers_walker)
 
-    def clk_providers_walker(self, node):
-        if node == self.head:
-            return
-
-        data_address = node + self.ramdump.field_offset('struct of_clk_provider', 'data')
-        node_address = node + self.ramdump.field_offset('struct of_clk_provider', 'node')
-        data = self.ramdump.read_word(data_address, True)
-        node = self.ramdump.read_word(node_address, True)
+    def print_clk_of_msm_provider_data(self, data):
         table_address = data + self.ramdump.field_offset('struct of_msm_provider_data', 'table')
         size_address = data + self.ramdump.field_offset('struct of_msm_provider_data', 'size')
         table = self.ramdump.read_word(table_address, True)
@@ -163,6 +157,73 @@ class ClockDumps(RamParser) :
             counter = counter + 1
             table = table + self.ramdump.sizeof('struct clk_lookup')
 
+    def print_clk_onecell_data(self, data):
+        offset_clk_onecell_data_clks = (
+                self.ramdump.field_offset('struct clk_onecell_data', 'clks'))
+        offset_clk_onecell_data_clknum = (
+                            self.ramdump.field_offset(
+                                'struct clk_onecell_data', 'clk_num'))
+        clks = self.ramdump.read_word(data + offset_clk_onecell_data_clks)
+        size = self.ramdump.read_int(data + offset_clk_onecell_data_clknum)
+        sizeof_clk_pointer = self.ramdump.sizeof('struct clk *')
+        offset_vdd_cur_level = self.ramdump.field_offset(
+                                    'struct clk_vdd_class', 'cur_level')
+        counter = 0
+
+        while counter < size:
+            clk = self.ramdump.read_word(clks + (sizeof_clk_pointer * counter))
+            if clk == 0 or clk is None:
+                counter = counter + 1
+                continue
+            clk_core = self.ramdump.read_structure_field(
+                                                    clk, 'struct clk', 'core')
+            if clk_core == 0 or clk_core is None:
+                counter = counter + 1
+                continue
+            clk_name_addr = self.ramdump.read_structure_field(
+                                        clk_core, 'struct clk_core', 'name')
+            clk_name = self.ramdump.read_cstring(clk_name_addr, 48)
+            clk_prepare_count = self.ramdump.read_structure_field(
+                                clk_core, 'struct clk_core', 'prepare_count')
+            clk_enable_count = self.ramdump.read_structure_field(
+                                clk_core, 'struct clk_core', 'enable_count')
+            clk_rate = self.ramdump.read_structure_field(
+                                    clk_core, 'struct clk_core', 'rate')
+            clk_vdd_class_addr = (
+                    self.ramdump.read_structure_field(
+                        clk_core, 'struct clk_core', 'vdd_class'))
+            vdd_class = self.ramdump.read_word(clk_vdd_class_addr)
+            cur_level = 0
+            if vdd_class != 0 and vdd_class is not None:
+                cur_level_address = (vdd_class + offset_vdd_cur_level)
+                cur_level = self.ramdump.read_word(cur_level_address, True)
+            formatStr  = "{0:40} {1:<2}/ {2:<17} {3:<25} {4:<10} v.v (struct clk_core *)0x{5:<20x}\n"
+            output = formatStr.format(
+                                    clk_name,
+                                    clk_enable_count,
+                                    clk_prepare_count,
+                                    clk_rate, cur_level,
+                                    clk_core)
+            if clk_enable_count > 0:
+                self.enabled_clocks.append(output)
+            elif clk_prepare_count > 0:
+                self.prepared_clocks.append(output)
+            else:
+                self.disabled_clocks.append(output)
+            counter = counter + 1
+
+    def clk_providers_walker(self, node):
+        if node == self.head:
+            return
+        data_address = node + self.ramdump.field_offset(
+                                    'struct of_clk_provider', 'data')
+        data = self.ramdump.read_word(data_address, True)
+
+        if (self.ramdump.kernel_version < (4, 4, 38)):
+            self.print_clk_of_msm_provider_data(data)
+        else:
+            self.print_clk_onecell_data(data)
+
     def parse(self):
         self.output_file = self.ramdump.open_file('ClockDumps.txt')