Enable +fp16 feature for ARM code generation on AArch64 device

Bug: http://b/27512382

On AArch64, 'asimd' feature in /proc/cpuinfo signals the presence of
hardware half-precision conversion instructions.  'asimd' in this
feature list is parsed and translated to the "neon" feature in LLVM's
getHostCPUFeatures.  Enable the "+fp16" feature if "neon" is in the
feature list, to signal the ARM backend that hardware fp16 support is
present.

Change-Id: If6a7db8f39b044fe262ac6953ab41535184973e4