Commit f0be3cc5 authored by Joel Sing's avatar Joel Sing
Browse files

runtime: unbreak linux/riscv64 following regabi merge

Unbreak the linux/riscv64 port by storing the zero value register to memory,
rather than the current code that is moving a zero intermediate to the stack
pointer register (ideally this should be caught by the assembler). This was
broken in CL#272568.

On riscv64 a zero immediate value cannot be moved directly to memory, rather
a register needs to be loaded with zero and then stored. Alternatively, the
the zero value register (aka X0) can be used directly.

Change-Id: Id57121541d50c9993cec5c2270b638b184ab9bc1
Reviewed-on: https://go-review.googlesource.com/c/go/+/292894


Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: default avatarMichael Knyszek <mknyszek@google.com>
Reviewed-by: default avatarCherry Zhang <cherryyz@google.com>
Run-TryBot: Michael Knyszek <mknyszek@google.com>
TryBot-Result: Go Bot <gobot@golang.org>
parent 07ef3135
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