mali_kbase: mem: Streamline coherency management

This change:

(1) Indicates to the kernel driver that all other HW blocks
    interacting with the GPU either write out directly to DRAM
    (i.e. use uncached accesses) or write out to caches that
    are snoopable by the GPU. This allows the kernel driver to
    set the region flags to indicate that SW cache maintenance
    is not needed when HW coherency is enabled. If HW coherency
    is not available, then SW cache maintenance is used as
    before.

(2) Removes the CONFIG_MALI_DMA_BUF_LEGACY_COMPAT flag as this
    is no longer necessary with the current GPU driver and kernel
    version.

These changes allow for HW coherency to be toggled via changes
to devicetree alone, without requiring modicfications to the
mali_kbase.ko binary.

Bug: 151952998
Bug: 168113578
Change-Id: Ib0ad42e273863a3f46e3997bf919b63fe68f6d9e
Signed-off-by: Sidath Senanayake <sidaths@google.com>