msm: idle-v7: clear ETM and Debug sticky bits for simple WFI on 8660

On 8660, SAW deasserts DBG_scCpu0/1CorePwrdUp when in clock gated
mode which causes the stickyPD bit to be set for both ETM PDSR and
Debug PRSR. Since 8660 processor has the ability to request clocks
be turned on in clock gated standby mode, it was not necessary to
deassert DBG_scCpu0/1CorePwrdUp but the SAW chose not to do that.

When the stickyPD bit is set, it prevents software accesses to etm
and debug registers in core power domain. Moreover, external debugger
accesses to these registers will also be prevented when in clock
gated wait state.

This issue is specific to 8660 and so prior chips and Krait based
chips are not affected. We now clear the stickyPD bit in ETM PDSR
and Debug PRSR when we come out of the simple clock gated WFI mode.

Change-Id: I2862adec7cc99413c73cf826029448e8a5987506
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>