mmc: msm_sdcc: Add delay after writing to MCI_CLEAR register

After writing to MCI_CLEAR register there is a synchronization
delay (3MCLK+2HCLK) for the write to take effect in MCI_STATUS
register. If we write to the same register without this delay
then these two writes can possibly negate each other and the
old status value is reflected in the STATUS register. This can
lead ISR handler to loop forever in do-while.

Now, since msmsdcc_delay is called in ISR handler it is better
to cache the values from delay computation when clk_rate
gets updated and use it afterwards.

CRs-Fixed: 309435
Signed-off-by: Sujith Reddy Thumma <sthumma@codeaurora.org>