mmc: msm_sdcc: fix issues related to DLL tuning

1. SDR50 mode operates at 96MHz MCLK and there are random failures
   (data timeouts or command CRC errors) seen if DLL is used in SDR50
   mode. It is found that DLL may have issues if used for
   clock <= 100MHz. According to SD3.01 Specification, Sampling clock
   tuning is optional for SDR50 mode and is only mandatory for SDR104
   (which requires clock > 100MHz). So this change removes the DLL
   tuning in SDR50 mode.

2. CDR_SELECT field in MCI_DLL_CONFIG register expect the phase value
   in gray coded binary format but currently driver was programming
   this field with normal binary numbers. This change maps the phase
   to gray coded binary numbers before programming CDR_SELECT field.

3. Find out the greatest range of consecuitive selected DLL clock
   output phases that can be used as sampling setting for SD3.0
   UHS-I card read operation (in SDR50/SDR104 timing mode) or
   for eMMC4.5 card read operation (in HS200 timing mode).
   Select the 3/4 of the range and configure the DLL with the
   selected DLL clock output phase.

4. Added few extra debug messages to be printed out when errors
   are seen while performing tuning.

CRs-fixed: 323399
Change-Id: Iadcb63930681b8f3a3d04252bc5b643c106baad7
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>