ASoC: fsl-sai: add default register map for regmap cache

FSL_SAI_TDR register is writable and not readable. According to
regmap_volatile() function, if FSL_SAI_TDR want to be volatile,
it should be readable. So we should remove FSL_SAI_TDR from volatile
register list.

If the flat cache don't have default register map, when do regcache_sync
operation, the non volatile and writable registers will be synchronised
to 0. FSL_SAI_TDR reigster will be written a 0 and cause channel swap.
So add default register map for flat cache, and such register will not
be written.

Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit b9b21722ff2e431c85d33bcc950327093cf9a991)