msm: Allow conditional L2 flush during power collapse

On existing targets, L2 is flushed every time any of the core executes a
power collapse. This adds latency into the enter path for idle power
collapse. This commit provides a API that would vote for a L2 flush
during power collapse.

Remove invalidating the L1/L2 cache during warmboot. On
Krait/Scorpion processors, the boot loaders code takes care of
invalidating the L1/L2 cache. On A5 processor, L1 is invalidated at reset.
And the L2 cache is invalidated later in the boot process using the L2
cache controller.

Change-Id: Ib63cfefafcc3aa887faa902a9856fbc5eb137075
Signed-off-by: Maheshkumar Sivasubramanian <msivasub@codeaurora.org>