MLK-11273-2 ARM: imx: update latency setting for imx6sx low power idle

Per design team, the RBC counter to hold interrupt needs at least
90us, so the counter value should be better set to 4, ~120us.

Also, right before WFI, ARM is running at 24MHz, the delay loop
value assumes ARM is at 1GHz which is incorrect, adjust it based
on 24MHz freq.

The latency of cpuidle exit should be adjusted accordingly.

Signed-off-by: Anson Huang <b20788@freescale.com>