MLK-10475-2 ARM: imx6q: Add PRE/PRG mux bits to GPR syscon definition

We've got the following mux options for PRE and PRG embedded in i.MX6Q R2.
 ------------------------------------------------------------------
|\     |          PRG0/IPU0          |           PRG1/IPU1         |
| mux  |-----------------------------------------------------------|
|    \ |ch0/ch23 |ch1/ch27 |ch2/ch28 |ch0/ch23 |ch1/ch27 |ch2/ch28 |
|------------------------------------------------------------------|
| PRE0 |  fixed  |   n/a   |   n/a   |   n/a   |   n/a   |   n/a   |
|------------------------------------------------------------------|
| PRE1 |   n/a   | A(2b'00)| A(2b'01)|   n/a   | A(2b'10)| A(2b'11)|
|------------------------------------------------------------------|
| PRE2 |   n/a   | B(2b'00)| B(2b'01)|   n/a   | B(2b'10)| B(2b'11)|
|------------------------------------------------------------------|
| PRE3 |   n/a   |   n/a   |   n/a   |  fixed  |   n/a   |   n/a   |
 ------------------------------------------------------------------
(Note - A: GPR5 bit12-13, B: GPR5 bit14-15)

This patch adds the PRE and PRG muxing bits and masks/shifts to GPR syscon
definition.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>