drm: xilinx: dp: Consider the max lanes for PHY status
The PHY status register changes the maximum number of lanes that the DP IP core supports. This patch adds to take the number of lanes into account when checking the PHY status. Signed-off-by:Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
Loading
Please sign in to comment