dmaengine: Add 16 byte bus width

Xilinx ZDMA controller supports 16 byte bus width and this bus width was
not defined. So, added to dma_slave_buswidths.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>