Commit 419937c8 authored by Zidan Wang's avatar Zidan Wang Committed by Nitin Garg
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MLK-10113: ASoC: fsl_sai: Bclk devision value must be a even number between 2-512 



According to the RM of sai, bclk DIV is 8 bit, and the devision value is
(DIV+1)*2. So bclk devision value must be a even number between 2-512.

When find the best clock source, stop judging the others.

Signed-off-by: default avatarZidan Wang <zidan.wang@freescale.com>
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