MLK-10782-3 ARM:imx6qdl: Initialize LDB_DI_CLK parent at boot

Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux
of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked
up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced
from ldb_di_clk.

To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the
switch. This patch ensures that correct steps are followed when ldb_di_clk parent is switched in
the beginning of boot. The glitchy muxes are then registered as read-only. The clock parent can be
selected by adding an entry shown below in the board device tree file:

	&clks {
		fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
		fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
	};

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>