Commit 08bb2fd9 authored by Soren Brinkmann's avatar Soren Brinkmann Committed by John Linn
Browse files

Xilinx: ARM: timer: Remove useless conditionals



When porting the timer to use the common clock framework
it was assumed it is possible to compile a Zynq kernel
w/ or w/o COMMON_CLK defined and conditional compilation had
been added accordingly.
Turns out this assumption was wrong and building for Zynq always
defines COMMON_CLK rendering the associated conditionals useless.

Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
parent 37db2186
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please to comment