msm: pil-gss: Apply workaround for QGIC bus access issue

On 8064 v1.0, QGIC registers are inaccessible from the GSS A5
processor unless a special sequence of register writes and reads
is first performed from the Krait0 CPU. This sequence affects the
initial state of an internal GSS bus, resolving the access issue.

CRs-Fixed: 334608
Change-Id: If0bf1f3f16e5e73399de4593b02ba92daf10e5b6
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>