From 8db5d1d3f7f9625bc3ef9ef065a142eafae07f2a Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 8 May 2022 12:33:06 +0530 Subject: [PATCH] Revert "New rr-cache entries from ci-merge" This reverts commit d2214412dba7e00b485f3a2e5970c5be6e57e288. --- .../preimage | 375 - .../preimage | 438 - .../preimage.1 | 438 - .../preimage.2 | 438 - .../preimage | 1079 --- .../preimage | 243 - .../postimage | 3811 --------- .../preimage | 3812 --------- .../preimage | 2381 ------ .../preimage.1 | 2381 ------ .../preimage | 391 - .../preimage | 141 - .../preimage | 625 -- .../preimage.1 | 625 -- .../preimage.2 | 625 -- .../preimage | 2553 ------ .../postimage | 551 -- .../preimage | 600 -- .../preimage | 1029 --- .../preimage | 634 -- .../preimage | 519 -- .../preimage | 579 -- .../preimage.1 | 579 -- .../preimage.2 | 579 -- .../preimage | 791 -- .../preimage.1 | 121 - .../preimage | 3865 --------- .../preimage.1 | 3865 --------- .../preimage.2 | 3865 --------- .../preimage | 6 - .../preimage | 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GPL-2.0 */ -/* - * Copyright (c) 2021, Linaro Ltd. - * - */ - -#ifndef _MHI_EP_INTERNAL_ -#define _MHI_EP_INTERNAL_ - -#include - -#include "../common.h" - -extern struct bus_type mhi_ep_bus_type; - -<<<<<<< -#define MHI_REG_OFFSET 0x100 -#define BHI_REG_OFFSET 0x200 - -/* MHI registers */ -#define MHIREGLEN (MHI_REG_OFFSET + REG_MHIREGLEN) -#define MHIVER (MHI_REG_OFFSET + REG_MHIVER) -#define MHICFG (MHI_REG_OFFSET + REG_MHICFG) -#define CHDBOFF (MHI_REG_OFFSET + REG_CHDBOFF) -#define ERDBOFF (MHI_REG_OFFSET + REG_ERDBOFF) -#define BHIOFF (MHI_REG_OFFSET + REG_BHIOFF) -#define BHIEOFF (MHI_REG_OFFSET + REG_BHIEOFF) -#define DEBUGOFF (MHI_REG_OFFSET + REG_DEBUGOFF) -#define MHICTRL (MHI_REG_OFFSET + REG_MHICTRL) -#define MHISTATUS (MHI_REG_OFFSET + REG_MHISTATUS) -#define CCABAP_LOWER (MHI_REG_OFFSET + REG_CCABAP_LOWER) -#define CCABAP_HIGHER (MHI_REG_OFFSET + REG_CCABAP_HIGHER) -#define ECABAP_LOWER (MHI_REG_OFFSET + REG_ECABAP_LOWER) -#define ECABAP_HIGHER (MHI_REG_OFFSET + REG_ECABAP_HIGHER) -#define CRCBAP_LOWER (MHI_REG_OFFSET + REG_CRCBAP_LOWER) -#define CRCBAP_HIGHER (MHI_REG_OFFSET + REG_CRCBAP_HIGHER) -#define CRDB_LOWER (MHI_REG_OFFSET + REG_CRDB_LOWER) -#define CRDB_HIGHER (MHI_REG_OFFSET + REG_CRDB_HIGHER) -#define MHICTRLBASE_LOWER (MHI_REG_OFFSET + REG_MHICTRLBASE_LOWER) -#define MHICTRLBASE_HIGHER (MHI_REG_OFFSET + REG_MHICTRLBASE_HIGHER) -#define MHICTRLLIMIT_LOWER (MHI_REG_OFFSET + REG_MHICTRLLIMIT_LOWER) -#define MHICTRLLIMIT_HIGHER (MHI_REG_OFFSET + REG_MHICTRLLIMIT_HIGHER) -#define MHIDATABASE_LOWER (MHI_REG_OFFSET + REG_MHIDATABASE_LOWER) -#define MHIDATABASE_HIGHER (MHI_REG_OFFSET + REG_MHIDATABASE_HIGHER) -#define MHIDATALIMIT_LOWER (MHI_REG_OFFSET + REG_MHIDATALIMIT_LOWER) -#define MHIDATALIMIT_HIGHER (MHI_REG_OFFSET + REG_MHIDATALIMIT_HIGHER) - -/* MHI BHI registers */ -#define BHI_IMGTXDB (BHI_REG_OFFSET + REG_BHI_IMGTXDB) -#define BHI_EXECENV (BHI_REG_OFFSET + REG_BHI_EXECENV) -#define BHI_INTVEC (BHI_REG_OFFSET + REG_BHI_INTVEC) - -/* MHI Doorbell registers */ -======= -/* MHI register definitions */ -#define MHIREGLEN 0x100 -#define MHIVER 0x108 -#define MHICFG 0x110 -#define CHDBOFF 0x118 -#define ERDBOFF 0x120 -#define BHIOFF 0x128 -#define DEBUGOFF 0x130 -#define MHICTRL 0x138 -#define MHISTATUS 0x148 -#define CCABAP_LOWER 0x158 -#define CCABAP_HIGHER 0x15c -#define ECABAP_LOWER 0x160 -#define ECABAP_HIGHER 0x164 -#define CRCBAP_LOWER 0x168 -#define CRCBAP_HIGHER 0x16c -#define CRDB_LOWER 0x170 -#define CRDB_HIGHER 0x174 -#define MHICTRLBASE_LOWER 0x180 -#define MHICTRLBASE_HIGHER 0x184 -#define MHICTRLLIMIT_LOWER 0x188 -#define MHICTRLLIMIT_HIGHER 0x18c -#define MHIDATABASE_LOWER 0x198 -#define MHIDATABASE_HIGHER 0x19c -#define MHIDATALIMIT_LOWER 0x1a0 -#define MHIDATALIMIT_HIGHER 0x1a4 ->>>>>>> -#define CHDB_LOWER_n(n) (0x400 + 0x8 * (n)) -#define CHDB_HIGHER_n(n) (0x404 + 0x8 * (n)) -#define ERDB_LOWER_n(n) (0x800 + 0x8 * (n)) -#define ERDB_HIGHER_n(n) (0x804 + 0x8 * (n)) -<<<<<<< -======= -#define BHI_INTVEC 0x220 -#define BHI_EXECENV 0x228 -#define BHI_IMGTXDB 0x218 ->>>>>>> - -#define MHI_CTRL_INT_STATUS_A7 0x4 -#define MHI_CTRL_INT_STATUS_A7_MSK BIT(0) -#define MHI_CTRL_INT_STATUS_CRDB_MSK BIT(1) -#define MHI_CHDB_INT_STATUS_A7_n(n) (0x28 + 0x4 * (n)) -#define MHI_ERDB_INT_STATUS_A7_n(n) (0x38 + 0x4 * (n)) - -#define MHI_CTRL_INT_CLEAR_A7 0x4c -#define MHI_CTRL_INT_MMIO_WR_CLEAR BIT(2) -#define MHI_CTRL_INT_CRDB_CLEAR BIT(1) -#define MHI_CTRL_INT_CRDB_MHICTRL_CLEAR BIT(0) - -#define MHI_CHDB_INT_CLEAR_A7_n(n) (0x70 + 0x4 * (n)) -#define MHI_CHDB_INT_CLEAR_A7_n_CLEAR_ALL GENMASK(31, 0) -#define MHI_ERDB_INT_CLEAR_A7_n(n) (0x80 + 0x4 * (n)) -#define MHI_ERDB_INT_CLEAR_A7_n_CLEAR_ALL GENMASK(31, 0) - -<<<<<<< -#define MHI_CTRL_INT_MASK_A7 0x94 -#define MHI_CTRL_INT_MASK_A7_MASK_MASK GENMASK(1, 0) -#define MHI_CTRL_MHICTRL_MASK BIT(0) -#define MHI_CTRL_MHICTRL_SHFT 0 -#define MHI_CTRL_CRDB_MASK BIT(1) -#define MHI_CTRL_CRDB_SHFT 1 -======= -/* - * Unlike the usual "masking" convention, writing "1" to a bit in this register - * enables the interrupt and writing "0" will disable it.. - */ -#define MHI_CTRL_INT_MASK_A7 0x94 -#define MHI_CTRL_INT_MASK_A7_MASK GENMASK(1, 0) -#define MHI_CTRL_MHICTRL_MASK BIT(0) -#define MHI_CTRL_CRDB_MASK BIT(1) ->>>>>>> - -#define MHI_CHDB_INT_MASK_A7_n(n) (0xb8 + 0x4 * (n)) -#define MHI_CHDB_INT_MASK_A7_n_EN_ALL GENMASK(31, 0) -#define MHI_ERDB_INT_MASK_A7_n(n) (0xc8 + 0x4 * (n)) -#define MHI_ERDB_INT_MASK_A7_n_EN_ALL GENMASK(31, 0) - -#define NR_OF_CMD_RINGS 1 -#define MHI_MASK_ROWS_CH_EV_DB 4 -#define MHI_MASK_CH_EV_LEN 32 - -/* Generic context */ -struct mhi_generic_ctx { - __u32 reserved0; - __u32 reserved1; - __u32 reserved2; - - __u64 rbase __packed __aligned(4); - __u64 rlen __packed __aligned(4); - __u64 rp __packed __aligned(4); - __u64 wp __packed __aligned(4); -}; - -<<<<<<< -======= -/** - * enum mhi_ep_execenv - MHI Endpoint Execution Environment - * @MHI_EP_SBL_EE: Secondary Bootloader - * @MHI_EP_AMSS_EE: Advanced Mode Subscriber Software - */ -enum mhi_ep_execenv { - MHI_EP_SBL_EE = 1, - MHI_EP_AMSS_EE = 2, - MHI_EP_UNRESERVED -}; - ->>>>>>> -/* Transfer Ring Element macros */ -#define MHI_EP_TRE_PTR(ptr) (ptr) -#define MHI_EP_TRE_DWORD0(len) (len & MHI_MAX_MTU) -#define MHI_EP_TRE_DWORD1(bei, ieot, ieob, chain) ((2 << 16) | (bei << 10) \ - | (ieot << 9) | (ieob << 8) | chain) -#define MHI_EP_TRE_GET_PTR(tre) ((tre)->ptr) -#define MHI_EP_TRE_GET_LEN(tre) ((tre)->dword[0] & 0xffff) -#define MHI_EP_TRE_GET_CHAIN(tre) FIELD_GET(BIT(0), (tre)->dword[1]) -#define MHI_EP_TRE_GET_IEOB(tre) FIELD_GET(BIT(8), (tre)->dword[1]) -#define MHI_EP_TRE_GET_IEOT(tre) FIELD_GET(BIT(9), (tre)->dword[1]) -#define MHI_EP_TRE_GET_BEI(tre) FIELD_GET(BIT(10), (tre)->dword[1]) - -<<<<<<< -======= -enum mhi_ep_ring_state { - RING_STATE_UINT = 0, - RING_STATE_IDLE, -}; - ->>>>>>> -enum mhi_ep_ring_type { - RING_TYPE_CMD = 0, - RING_TYPE_ER, - RING_TYPE_CH, -<<<<<<< - RING_TYPE_INVALID, -}; - -enum mhi_ep_execenv { - MHI_EP_SBL_EE = 1, - MHI_EP_AMSS_EE = 2, - MHI_EP_UNRESERVED -}; - -struct mhi_ep_ring_element { - u64 ptr; - u32 dword[2]; -}; - -/* Transfer ring element type */ -======= -}; - -struct mhi_ep_ring_element { - __le64 ptr; - __le32 dword[2]; -}; - -/* Ring element */ ->>>>>>> -union mhi_ep_ring_ctx { - struct mhi_cmd_ctxt cmd; - struct mhi_event_ctxt ev; - struct mhi_chan_ctxt ch; - struct mhi_generic_ctx generic; -}; - -<<<<<<< -struct mhi_ep_ring { - struct list_head list; -======= -struct mhi_ep_ring_item { - struct list_head node; - struct mhi_ep_ring *ring; -}; - -struct mhi_ep_ring { ->>>>>>> - struct mhi_ep_cntrl *mhi_cntrl; - int (*ring_cb)(struct mhi_ep_ring *ring, struct mhi_ep_ring_element *el); - union mhi_ep_ring_ctx *ring_ctx; - struct mhi_ep_ring_element *ring_cache; - enum mhi_ep_ring_type type; -<<<<<<< -======= - enum mhi_ep_ring_state state; ->>>>>>> - size_t rd_offset; - size_t wr_offset; - size_t ring_size; - u32 db_offset_h; - u32 db_offset_l; - u32 ch_id; -<<<<<<< -======= - u32 er_index; - u32 irq_vector; - bool started; ->>>>>>> -}; - -struct mhi_ep_cmd { - struct mhi_ep_ring ring; -}; - -struct mhi_ep_event { - struct mhi_ep_ring ring; -}; - -struct mhi_ep_state_transition { - struct list_head node; - enum mhi_state state; -}; - -struct mhi_ep_chan { - char *name; - struct mhi_ep_device *mhi_dev; - struct mhi_ep_ring ring; - struct mutex lock; - void (*xfer_cb)(struct mhi_ep_device *mhi_dev, struct mhi_result *result); - enum mhi_ch_state state; - enum dma_data_direction dir; - u64 tre_loc; - u32 tre_size; - u32 tre_bytes_left; - u32 chan; - bool skip_td; -}; - -/* MHI Ring related functions */ -<<<<<<< -int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ep_ring_element *el); -int mhi_ep_process_tre_ring(struct mhi_ep_ring *ring, struct mhi_ep_ring_element *el); -void mhi_ep_ring_init(struct mhi_ep_ring *ring, enum mhi_ep_ring_type type, u32 id); -void mhi_ep_ring_stop(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring); -size_t mhi_ep_ring_addr2offset(struct mhi_ep_ring *ring, u64 ptr); -int mhi_ep_ring_start(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring, - union mhi_ep_ring_ctx *ctx); -int mhi_ep_process_ring(struct mhi_ep_ring *ring); -int mhi_ep_ring_add_element(struct mhi_ep_ring *ring, struct mhi_ep_ring_element *element, - int evt_offset); -void mhi_ep_ring_inc_index(struct mhi_ep_ring *ring); - -/* MMIO related functions */ -void mhi_ep_mmio_read(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 *regval); -void mhi_ep_mmio_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 val); -void mhi_ep_mmio_masked_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, - u32 mask, u32 shift, u32 val); -int mhi_ep_mmio_masked_read(struct mhi_ep_cntrl *dev, u32 offset, - u32 mask, u32 shift, u32 *regval); -======= -void mhi_ep_ring_init(struct mhi_ep_ring *ring, enum mhi_ep_ring_type type, u32 id); -void mhi_ep_ring_reset(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring); -int mhi_ep_ring_start(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring, - union mhi_ep_ring_ctx *ctx); -size_t mhi_ep_ring_addr2offset(struct mhi_ep_ring *ring, u64 ptr); -int mhi_ep_process_ring(struct mhi_ep_ring *ring); -int mhi_ep_ring_add_element(struct mhi_ep_ring *ring, struct mhi_ep_ring_element *element); -void mhi_ep_ring_inc_index(struct mhi_ep_ring *ring); -int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ep_ring_element *el); -int mhi_ep_process_tre_ring(struct mhi_ep_ring *ring, struct mhi_ep_ring_element *el); -int mhi_ep_update_wr_offset(struct mhi_ep_ring *ring); - -/* MMIO related functions */ -u32 mhi_ep_mmio_read(struct mhi_ep_cntrl *mhi_cntrl, u32 offset); -void mhi_ep_mmio_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 val); -void mhi_ep_mmio_masked_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 mask, u32 val); -u32 mhi_ep_mmio_masked_read(struct mhi_ep_cntrl *dev, u32 offset, u32 mask); ->>>>>>> -void mhi_ep_mmio_enable_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_disable_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_enable_cmdb_interrupt(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_disable_cmdb_interrupt(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_enable_chdb_a7(struct mhi_ep_cntrl *mhi_cntrl, u32 chdb_id); -void mhi_ep_mmio_disable_chdb_a7(struct mhi_ep_cntrl *mhi_cntrl, u32 chdb_id); -void mhi_ep_mmio_enable_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_read_chdb_status_interrupts(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_mask_interrupts(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_get_chc_base(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_get_erc_base(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_get_crc_base(struct mhi_ep_cntrl *mhi_cntrl); -<<<<<<< -u64 mhi_ep_mmio_get_db(struct mhi_ep_ring *ring); -======= -void mhi_ep_mmio_get_ch_db(struct mhi_ep_ring *ring, u64 *wr_offset); -void mhi_ep_mmio_get_er_db(struct mhi_ep_ring *ring, u64 *wr_offset); -void mhi_ep_mmio_get_cmd_db(struct mhi_ep_ring *ring, u64 *wr_offset); ->>>>>>> -void mhi_ep_mmio_set_env(struct mhi_ep_cntrl *mhi_cntrl, u32 value); -void mhi_ep_mmio_clear_reset(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_reset(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_get_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state *state, - bool *mhi_reset); -void mhi_ep_mmio_init(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_mmio_update_ner(struct mhi_ep_cntrl *mhi_cntrl); - -/* MHI EP core functions */ -int mhi_ep_send_state_change_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state state); -int mhi_ep_send_ee_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_ep_execenv exec_env); -bool mhi_ep_check_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state cur_mhi_state, - enum mhi_state mhi_state); -int mhi_ep_set_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state mhi_state); -int mhi_ep_set_m0_state(struct mhi_ep_cntrl *mhi_cntrl); -int mhi_ep_set_m3_state(struct mhi_ep_cntrl *mhi_cntrl); -int mhi_ep_set_ready_state(struct mhi_ep_cntrl *mhi_cntrl); -<<<<<<< -void mhi_ep_handle_syserr(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_resume_channels(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_suspend_channels(struct mhi_ep_cntrl *mhi_cntrl); - -/* MHI EP memory management functions */ -int mhi_ep_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, size_t size, - phys_addr_t *phys_ptr, void __iomem **virt); -void mhi_ep_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, phys_addr_t phys, - void __iomem *virt, size_t size); -======= -void mhi_ep_resume_channels(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_suspend_channels(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_handle_syserr(struct mhi_ep_cntrl *mhi_cntrl); -int mhi_ep_suspend(struct mhi_ep_cntrl *mhi_cntrl); -int mhi_ep_resume(struct mhi_ep_cntrl *mhi_cntrl); ->>>>>>> - -#endif diff --git a/rr-cache/0bc32b624ddaf2249fb6c6594ecdbe205231941b/preimage b/rr-cache/0bc32b624ddaf2249fb6c6594ecdbe205231941b/preimage deleted file mode 100644 index 32944f5..0000000 --- a/rr-cache/0bc32b624ddaf2249fb6c6594ecdbe205231941b/preimage +++ /dev/null @@ -1,438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Red Hat - * Author: Rob Clark - */ - -#include -#include -#include - -#include "msm_kms.h" -#include "hdmi.h" - -static void msm_hdmi_phy_reset(struct hdmi *hdmi) -{ - unsigned int val; - - val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL); - - if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET); - } else { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET); - } - - if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET_PLL); - } else { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET_PLL); - } - - msleep(100); - - if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET); - } else { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET); - } - - if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET_PLL); - } else { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET_PLL); - } -} - -static int gpio_config(struct hdmi *hdmi, bool on) -{ - const struct hdmi_platform_config *config = hdmi->config; - int i; - - if (on) { - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - struct hdmi_gpio_data gpio = config->gpios[i]; - - if (gpio.gpiod) { - if (gpio.output) { - gpiod_direction_output(gpio.gpiod, - gpio.value); - } else { - gpiod_direction_input(gpio.gpiod); - gpiod_set_value_cansleep(gpio.gpiod, - gpio.value); - } - } - } - - DBG("gpio on"); - } else { - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - struct hdmi_gpio_data gpio = config->gpios[i]; - - if (!gpio.gpiod) - continue; - - if (gpio.output) { - int value = gpio.value ? 0 : 1; - - gpiod_set_value_cansleep(gpio.gpiod, value); - } - } - - DBG("gpio off"); - } - - return 0; -} - -static void enable_hpd_clocks(struct hdmi *hdmi, bool enable) -{ - const struct hdmi_platform_config *config = hdmi->config; - struct device *dev = &hdmi->pdev->dev; - int i, ret; - - if (enable) { - for (i = 0; i < config->hpd_clk_cnt; i++) { - if (config->hpd_freq && config->hpd_freq[i]) { - ret = clk_set_rate(hdmi->hpd_clks[i], - config->hpd_freq[i]); - if (ret) - dev_warn(dev, - "failed to set clk %s (%d)\n", - config->hpd_clk_names[i], ret); - } - - ret = clk_prepare_enable(hdmi->hpd_clks[i]); - if (ret) { - DRM_DEV_ERROR(dev, - "failed to enable hpd clk: %s (%d)\n", - config->hpd_clk_names[i], ret); - } - } - } else { - for (i = config->hpd_clk_cnt - 1; i >= 0; i--) - clk_disable_unprepare(hdmi->hpd_clks[i]); - } -} - -int msm_hdmi_hpd_enable(struct drm_bridge *bridge) -{ - struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); - struct hdmi *hdmi = hdmi_bridge->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct device *dev = &hdmi->pdev->dev; - uint32_t hpd_ctrl; - int ret; - unsigned long flags; - - ret = regulator_bulk_enable(config->hpd_reg_cnt, hdmi->hpd_regs); - if (ret) { - DRM_DEV_ERROR(dev, "failed to enable hpd regulators: %d\n", ret); - goto fail; - } - - ret = pinctrl_pm_select_default_state(dev); - if (ret) { - DRM_DEV_ERROR(dev, "pinctrl state chg failed: %d\n", ret); - goto fail; - } - - ret = gpio_config(hdmi, true); - if (ret) { - DRM_DEV_ERROR(dev, "failed to configure GPIOs: %d\n", ret); - goto fail; - } - - pm_runtime_get_sync(dev); - enable_hpd_clocks(hdmi, true); - - msm_hdmi_set_mode(hdmi, false); - msm_hdmi_phy_reset(hdmi); - msm_hdmi_set_mode(hdmi, true); - - hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b); - - /* enable HPD events: */ - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, - HDMI_HPD_INT_CTRL_INT_CONNECT | - HDMI_HPD_INT_CTRL_INT_EN); - - /* set timeout to 4.1ms (max) for hardware debounce */ - spin_lock_irqsave(&hdmi->reg_lock, flags); - hpd_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); - hpd_ctrl |= HDMI_HPD_CTRL_TIMEOUT(0x1fff); - - /* Toggle HPD circuit to trigger HPD sense */ - hdmi_write(hdmi, REG_HDMI_HPD_CTRL, - ~HDMI_HPD_CTRL_ENABLE & hpd_ctrl); - hdmi_write(hdmi, REG_HDMI_HPD_CTRL, - HDMI_HPD_CTRL_ENABLE | hpd_ctrl); - spin_unlock_irqrestore(&hdmi->reg_lock, flags); - - /* - * wait for a bit so that HPD is sensed if there is a cable already - * connected. Returning early will result in someone calling the - * connnector func's detect() callback too early - */ - msleep(15); - - return 0; - -fail: - return ret; -} - -void msm_hdmi_hpd_disable(struct hdmi_bridge *hdmi_bridge) -{ - struct hdmi *hdmi = hdmi_bridge->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct device *dev = &hdmi->pdev->dev; - int ret; - - /* Disable HPD interrupt */ - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, 0); - - msm_hdmi_set_mode(hdmi, false); - - enable_hpd_clocks(hdmi, false); - pm_runtime_put(dev); - - ret = gpio_config(hdmi, false); - if (ret) - dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret); - - ret = pinctrl_pm_select_sleep_state(dev); - if (ret) - dev_warn(dev, "pinctrl state chg failed: %d\n", ret); - - ret = regulator_bulk_disable(config->hpd_reg_cnt, hdmi->hpd_regs); - if (ret) - dev_warn(dev, "failed to disable hpd regulator: %d\n", ret); -} - -void msm_hdmi_hpd_irq(struct drm_bridge *bridge) -{ - struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); - struct hdmi *hdmi = hdmi_bridge->hdmi; - uint32_t hpd_int_status, hpd_int_ctrl; - - /* Process HPD: */ - hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); - hpd_int_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_INT_CTRL); - - if ((hpd_int_ctrl & HDMI_HPD_INT_CTRL_INT_EN) && - (hpd_int_status & HDMI_HPD_INT_STATUS_INT)) { - bool detected = !!(hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED); - - /* ack & disable (temporarily) HPD events: */ - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, - HDMI_HPD_INT_CTRL_INT_ACK); - - DBG("status=%04x, ctrl=%04x", hpd_int_status, hpd_int_ctrl); - - /* detect disconnect if we are connected or visa versa: */ - hpd_int_ctrl = HDMI_HPD_INT_CTRL_INT_EN; - if (!detected) - hpd_int_ctrl |= HDMI_HPD_INT_CTRL_INT_CONNECT; - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, hpd_int_ctrl); - - queue_work(hdmi->workq, &hdmi_bridge->hpd_work); - } -} - -static enum drm_connector_status detect_reg(struct hdmi *hdmi) -{ - uint32_t hpd_int_status; - - pm_runtime_get_sync(&hdmi->pdev->dev); - enable_hpd_clocks(hdmi, true); - - hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); - - enable_hpd_clocks(hdmi, false); - pm_runtime_put(&hdmi->pdev->dev); - - return (hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED) ? - connector_status_connected : connector_status_disconnected; -} - -#define HPD_GPIO_INDEX 2 -static enum drm_connector_status detect_gpio(struct hdmi *hdmi) -{ - const struct hdmi_platform_config *config = hdmi->config; - struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX]; - - return gpiod_get_value(hpd_gpio.gpiod) ? - connector_status_connected : - connector_status_disconnected; -} - -enum drm_connector_status msm_hdmi_bridge_detect( - struct drm_bridge *bridge) -{ - struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); - struct hdmi *hdmi = hdmi_bridge->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX]; - enum drm_connector_status stat_gpio, stat_reg; - int retry = 20; - - /* - * some platforms may not have hpd gpio. Rely only on the status - * provided by REG_HDMI_HPD_INT_STATUS in this case. - */ - if (!hpd_gpio.gpiod) - return detect_reg(hdmi); - - do { - stat_gpio = detect_gpio(hdmi); - stat_reg = detect_reg(hdmi); - - if (stat_gpio == stat_reg) - break; - - mdelay(10); - } while (--retry); - - /* the status we get from reading gpio seems to be more reliable, - * so trust that one the most if we didn't manage to get hdmi and - * gpio status to agree: - */ - if (stat_gpio != stat_reg) { - DBG("HDMI_HPD_INT_STATUS tells us: %d", stat_reg); - DBG("hpd gpio tells us: %d", stat_gpio); - } - - return stat_gpio; -} -<<<<<<< -======= - -static void hdmi_connector_destroy(struct drm_connector *connector) -{ - struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); - - hdp_disable(hdmi_connector); - - drm_connector_cleanup(connector); - - kfree(hdmi_connector); -} - -static int msm_hdmi_connector_get_modes(struct drm_connector *connector) -{ - struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); - struct hdmi *hdmi = hdmi_connector->hdmi; - struct edid *edid; - uint32_t hdmi_ctrl; - int ret = 0; - - hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); - hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE); - - edid = drm_get_edid(connector, hdmi->i2c); - - hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl); - - hdmi->hdmi_mode = drm_detect_hdmi_monitor(edid); - drm_connector_update_edid_property(connector, edid); - - if (edid) { - ret = drm_add_edid_modes(connector, edid); - kfree(edid); - } - - return ret; -} - -static int msm_hdmi_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); - struct hdmi *hdmi = hdmi_connector->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct msm_drm_private *priv = connector->dev->dev_private; - struct msm_kms *kms = priv->kms; - long actual, requested; - - requested = 1000 * mode->clock; - actual = kms->funcs->round_pixclk(kms, - requested, hdmi_connector->hdmi->encoder); - - /* for mdp5/apq8074, we manage our own pixel clk (as opposed to - * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder - * instead): - */ - if (config->pwr_clk_cnt > 0) - actual = clk_round_rate(hdmi->pwr_clks[0], actual); - - DBG("requested=%ld, actual=%ld", requested, actual); - - if (actual != requested) - return MODE_CLOCK_RANGE; - - return 0; -} - -static const struct drm_connector_funcs hdmi_connector_funcs = { - .detect = hdmi_connector_detect, - .fill_modes = drm_helper_probe_single_connector_modes, - .destroy = hdmi_connector_destroy, - .reset = drm_atomic_helper_connector_reset, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - -static const struct drm_connector_helper_funcs msm_hdmi_connector_helper_funcs = { - .get_modes = msm_hdmi_connector_get_modes, - .mode_valid = msm_hdmi_connector_mode_valid, -}; - -/* initialize connector */ -struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi) -{ - struct drm_connector *connector = NULL; - struct hdmi_connector *hdmi_connector; - - hdmi_connector = kzalloc(sizeof(*hdmi_connector), GFP_KERNEL); - if (!hdmi_connector) - return ERR_PTR(-ENOMEM); - - hdmi_connector->hdmi = hdmi; - INIT_WORK(&hdmi_connector->hpd_work, msm_hdmi_hotplug_work); - - connector = &hdmi_connector->base; - - drm_connector_init_with_ddc(hdmi->dev, connector, - &hdmi_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA, - hdmi->i2c); - drm_connector_helper_add(connector, &msm_hdmi_connector_helper_funcs); - - connector->polled = DRM_CONNECTOR_POLL_HPD; - - connector->interlace_allowed = 0; - connector->doublescan_allowed = 0; - - drm_connector_attach_encoder(connector, hdmi->encoder); - - return connector; -} ->>>>>>> diff --git a/rr-cache/0bc32b624ddaf2249fb6c6594ecdbe205231941b/preimage.1 b/rr-cache/0bc32b624ddaf2249fb6c6594ecdbe205231941b/preimage.1 deleted file mode 100644 index 32944f5..0000000 --- a/rr-cache/0bc32b624ddaf2249fb6c6594ecdbe205231941b/preimage.1 +++ /dev/null @@ -1,438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Red Hat - * Author: Rob Clark - */ - -#include -#include -#include - -#include "msm_kms.h" -#include "hdmi.h" - -static void msm_hdmi_phy_reset(struct hdmi *hdmi) -{ - unsigned int val; - - val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL); - - if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET); - } else { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET); - } - - if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET_PLL); - } else { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET_PLL); - } - - msleep(100); - - if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET); - } else { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET); - } - - if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET_PLL); - } else { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET_PLL); - } -} - -static int gpio_config(struct hdmi *hdmi, bool on) -{ - const struct hdmi_platform_config *config = hdmi->config; - int i; - - if (on) { - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - struct hdmi_gpio_data gpio = config->gpios[i]; - - if (gpio.gpiod) { - if (gpio.output) { - gpiod_direction_output(gpio.gpiod, - gpio.value); - } else { - gpiod_direction_input(gpio.gpiod); - gpiod_set_value_cansleep(gpio.gpiod, - gpio.value); - } - } - } - - DBG("gpio on"); - } else { - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - struct hdmi_gpio_data gpio = config->gpios[i]; - - if (!gpio.gpiod) - continue; - - if (gpio.output) { - int value = gpio.value ? 0 : 1; - - gpiod_set_value_cansleep(gpio.gpiod, value); - } - } - - DBG("gpio off"); - } - - return 0; -} - -static void enable_hpd_clocks(struct hdmi *hdmi, bool enable) -{ - const struct hdmi_platform_config *config = hdmi->config; - struct device *dev = &hdmi->pdev->dev; - int i, ret; - - if (enable) { - for (i = 0; i < config->hpd_clk_cnt; i++) { - if (config->hpd_freq && config->hpd_freq[i]) { - ret = clk_set_rate(hdmi->hpd_clks[i], - config->hpd_freq[i]); - if (ret) - dev_warn(dev, - "failed to set clk %s (%d)\n", - config->hpd_clk_names[i], ret); - } - - ret = clk_prepare_enable(hdmi->hpd_clks[i]); - if (ret) { - DRM_DEV_ERROR(dev, - "failed to enable hpd clk: %s (%d)\n", - config->hpd_clk_names[i], ret); - } - } - } else { - for (i = config->hpd_clk_cnt - 1; i >= 0; i--) - clk_disable_unprepare(hdmi->hpd_clks[i]); - } -} - -int msm_hdmi_hpd_enable(struct drm_bridge *bridge) -{ - struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); - struct hdmi *hdmi = hdmi_bridge->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct device *dev = &hdmi->pdev->dev; - uint32_t hpd_ctrl; - int ret; - unsigned long flags; - - ret = regulator_bulk_enable(config->hpd_reg_cnt, hdmi->hpd_regs); - if (ret) { - DRM_DEV_ERROR(dev, "failed to enable hpd regulators: %d\n", ret); - goto fail; - } - - ret = pinctrl_pm_select_default_state(dev); - if (ret) { - DRM_DEV_ERROR(dev, "pinctrl state chg failed: %d\n", ret); - goto fail; - } - - ret = gpio_config(hdmi, true); - if (ret) { - DRM_DEV_ERROR(dev, "failed to configure GPIOs: %d\n", ret); - goto fail; - } - - pm_runtime_get_sync(dev); - enable_hpd_clocks(hdmi, true); - - msm_hdmi_set_mode(hdmi, false); - msm_hdmi_phy_reset(hdmi); - msm_hdmi_set_mode(hdmi, true); - - hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b); - - /* enable HPD events: */ - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, - HDMI_HPD_INT_CTRL_INT_CONNECT | - HDMI_HPD_INT_CTRL_INT_EN); - - /* set timeout to 4.1ms (max) for hardware debounce */ - spin_lock_irqsave(&hdmi->reg_lock, flags); - hpd_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); - hpd_ctrl |= HDMI_HPD_CTRL_TIMEOUT(0x1fff); - - /* Toggle HPD circuit to trigger HPD sense */ - hdmi_write(hdmi, REG_HDMI_HPD_CTRL, - ~HDMI_HPD_CTRL_ENABLE & hpd_ctrl); - hdmi_write(hdmi, REG_HDMI_HPD_CTRL, - HDMI_HPD_CTRL_ENABLE | hpd_ctrl); - spin_unlock_irqrestore(&hdmi->reg_lock, flags); - - /* - * wait for a bit so that HPD is sensed if there is a cable already - * connected. Returning early will result in someone calling the - * connnector func's detect() callback too early - */ - msleep(15); - - return 0; - -fail: - return ret; -} - -void msm_hdmi_hpd_disable(struct hdmi_bridge *hdmi_bridge) -{ - struct hdmi *hdmi = hdmi_bridge->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct device *dev = &hdmi->pdev->dev; - int ret; - - /* Disable HPD interrupt */ - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, 0); - - msm_hdmi_set_mode(hdmi, false); - - enable_hpd_clocks(hdmi, false); - pm_runtime_put(dev); - - ret = gpio_config(hdmi, false); - if (ret) - dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret); - - ret = pinctrl_pm_select_sleep_state(dev); - if (ret) - dev_warn(dev, "pinctrl state chg failed: %d\n", ret); - - ret = regulator_bulk_disable(config->hpd_reg_cnt, hdmi->hpd_regs); - if (ret) - dev_warn(dev, "failed to disable hpd regulator: %d\n", ret); -} - -void msm_hdmi_hpd_irq(struct drm_bridge *bridge) -{ - struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); - struct hdmi *hdmi = hdmi_bridge->hdmi; - uint32_t hpd_int_status, hpd_int_ctrl; - - /* Process HPD: */ - hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); - hpd_int_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_INT_CTRL); - - if ((hpd_int_ctrl & HDMI_HPD_INT_CTRL_INT_EN) && - (hpd_int_status & HDMI_HPD_INT_STATUS_INT)) { - bool detected = !!(hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED); - - /* ack & disable (temporarily) HPD events: */ - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, - HDMI_HPD_INT_CTRL_INT_ACK); - - DBG("status=%04x, ctrl=%04x", hpd_int_status, hpd_int_ctrl); - - /* detect disconnect if we are connected or visa versa: */ - hpd_int_ctrl = HDMI_HPD_INT_CTRL_INT_EN; - if (!detected) - hpd_int_ctrl |= HDMI_HPD_INT_CTRL_INT_CONNECT; - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, hpd_int_ctrl); - - queue_work(hdmi->workq, &hdmi_bridge->hpd_work); - } -} - -static enum drm_connector_status detect_reg(struct hdmi *hdmi) -{ - uint32_t hpd_int_status; - - pm_runtime_get_sync(&hdmi->pdev->dev); - enable_hpd_clocks(hdmi, true); - - hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); - - enable_hpd_clocks(hdmi, false); - pm_runtime_put(&hdmi->pdev->dev); - - return (hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED) ? - connector_status_connected : connector_status_disconnected; -} - -#define HPD_GPIO_INDEX 2 -static enum drm_connector_status detect_gpio(struct hdmi *hdmi) -{ - const struct hdmi_platform_config *config = hdmi->config; - struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX]; - - return gpiod_get_value(hpd_gpio.gpiod) ? - connector_status_connected : - connector_status_disconnected; -} - -enum drm_connector_status msm_hdmi_bridge_detect( - struct drm_bridge *bridge) -{ - struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); - struct hdmi *hdmi = hdmi_bridge->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX]; - enum drm_connector_status stat_gpio, stat_reg; - int retry = 20; - - /* - * some platforms may not have hpd gpio. Rely only on the status - * provided by REG_HDMI_HPD_INT_STATUS in this case. - */ - if (!hpd_gpio.gpiod) - return detect_reg(hdmi); - - do { - stat_gpio = detect_gpio(hdmi); - stat_reg = detect_reg(hdmi); - - if (stat_gpio == stat_reg) - break; - - mdelay(10); - } while (--retry); - - /* the status we get from reading gpio seems to be more reliable, - * so trust that one the most if we didn't manage to get hdmi and - * gpio status to agree: - */ - if (stat_gpio != stat_reg) { - DBG("HDMI_HPD_INT_STATUS tells us: %d", stat_reg); - DBG("hpd gpio tells us: %d", stat_gpio); - } - - return stat_gpio; -} -<<<<<<< -======= - -static void hdmi_connector_destroy(struct drm_connector *connector) -{ - struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); - - hdp_disable(hdmi_connector); - - drm_connector_cleanup(connector); - - kfree(hdmi_connector); -} - -static int msm_hdmi_connector_get_modes(struct drm_connector *connector) -{ - struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); - struct hdmi *hdmi = hdmi_connector->hdmi; - struct edid *edid; - uint32_t hdmi_ctrl; - int ret = 0; - - hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); - hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE); - - edid = drm_get_edid(connector, hdmi->i2c); - - hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl); - - hdmi->hdmi_mode = drm_detect_hdmi_monitor(edid); - drm_connector_update_edid_property(connector, edid); - - if (edid) { - ret = drm_add_edid_modes(connector, edid); - kfree(edid); - } - - return ret; -} - -static int msm_hdmi_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); - struct hdmi *hdmi = hdmi_connector->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct msm_drm_private *priv = connector->dev->dev_private; - struct msm_kms *kms = priv->kms; - long actual, requested; - - requested = 1000 * mode->clock; - actual = kms->funcs->round_pixclk(kms, - requested, hdmi_connector->hdmi->encoder); - - /* for mdp5/apq8074, we manage our own pixel clk (as opposed to - * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder - * instead): - */ - if (config->pwr_clk_cnt > 0) - actual = clk_round_rate(hdmi->pwr_clks[0], actual); - - DBG("requested=%ld, actual=%ld", requested, actual); - - if (actual != requested) - return MODE_CLOCK_RANGE; - - return 0; -} - -static const struct drm_connector_funcs hdmi_connector_funcs = { - .detect = hdmi_connector_detect, - .fill_modes = drm_helper_probe_single_connector_modes, - .destroy = hdmi_connector_destroy, - .reset = drm_atomic_helper_connector_reset, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - -static const struct drm_connector_helper_funcs msm_hdmi_connector_helper_funcs = { - .get_modes = msm_hdmi_connector_get_modes, - .mode_valid = msm_hdmi_connector_mode_valid, -}; - -/* initialize connector */ -struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi) -{ - struct drm_connector *connector = NULL; - struct hdmi_connector *hdmi_connector; - - hdmi_connector = kzalloc(sizeof(*hdmi_connector), GFP_KERNEL); - if (!hdmi_connector) - return ERR_PTR(-ENOMEM); - - hdmi_connector->hdmi = hdmi; - INIT_WORK(&hdmi_connector->hpd_work, msm_hdmi_hotplug_work); - - connector = &hdmi_connector->base; - - drm_connector_init_with_ddc(hdmi->dev, connector, - &hdmi_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA, - hdmi->i2c); - drm_connector_helper_add(connector, &msm_hdmi_connector_helper_funcs); - - connector->polled = DRM_CONNECTOR_POLL_HPD; - - connector->interlace_allowed = 0; - connector->doublescan_allowed = 0; - - drm_connector_attach_encoder(connector, hdmi->encoder); - - return connector; -} ->>>>>>> diff --git a/rr-cache/0bc32b624ddaf2249fb6c6594ecdbe205231941b/preimage.2 b/rr-cache/0bc32b624ddaf2249fb6c6594ecdbe205231941b/preimage.2 deleted file mode 100644 index 32944f5..0000000 --- a/rr-cache/0bc32b624ddaf2249fb6c6594ecdbe205231941b/preimage.2 +++ /dev/null @@ -1,438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Red Hat - * Author: Rob Clark - */ - -#include -#include -#include - -#include "msm_kms.h" -#include "hdmi.h" - -static void msm_hdmi_phy_reset(struct hdmi *hdmi) -{ - unsigned int val; - - val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL); - - if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET); - } else { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET); - } - - if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET_PLL); - } else { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET_PLL); - } - - msleep(100); - - if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET); - } else { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET); - } - - if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { - /* pull high */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val | HDMI_PHY_CTRL_SW_RESET_PLL); - } else { - /* pull low */ - hdmi_write(hdmi, REG_HDMI_PHY_CTRL, - val & ~HDMI_PHY_CTRL_SW_RESET_PLL); - } -} - -static int gpio_config(struct hdmi *hdmi, bool on) -{ - const struct hdmi_platform_config *config = hdmi->config; - int i; - - if (on) { - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - struct hdmi_gpio_data gpio = config->gpios[i]; - - if (gpio.gpiod) { - if (gpio.output) { - gpiod_direction_output(gpio.gpiod, - gpio.value); - } else { - gpiod_direction_input(gpio.gpiod); - gpiod_set_value_cansleep(gpio.gpiod, - gpio.value); - } - } - } - - DBG("gpio on"); - } else { - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - struct hdmi_gpio_data gpio = config->gpios[i]; - - if (!gpio.gpiod) - continue; - - if (gpio.output) { - int value = gpio.value ? 0 : 1; - - gpiod_set_value_cansleep(gpio.gpiod, value); - } - } - - DBG("gpio off"); - } - - return 0; -} - -static void enable_hpd_clocks(struct hdmi *hdmi, bool enable) -{ - const struct hdmi_platform_config *config = hdmi->config; - struct device *dev = &hdmi->pdev->dev; - int i, ret; - - if (enable) { - for (i = 0; i < config->hpd_clk_cnt; i++) { - if (config->hpd_freq && config->hpd_freq[i]) { - ret = clk_set_rate(hdmi->hpd_clks[i], - config->hpd_freq[i]); - if (ret) - dev_warn(dev, - "failed to set clk %s (%d)\n", - config->hpd_clk_names[i], ret); - } - - ret = clk_prepare_enable(hdmi->hpd_clks[i]); - if (ret) { - DRM_DEV_ERROR(dev, - "failed to enable hpd clk: %s (%d)\n", - config->hpd_clk_names[i], ret); - } - } - } else { - for (i = config->hpd_clk_cnt - 1; i >= 0; i--) - clk_disable_unprepare(hdmi->hpd_clks[i]); - } -} - -int msm_hdmi_hpd_enable(struct drm_bridge *bridge) -{ - struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); - struct hdmi *hdmi = hdmi_bridge->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct device *dev = &hdmi->pdev->dev; - uint32_t hpd_ctrl; - int ret; - unsigned long flags; - - ret = regulator_bulk_enable(config->hpd_reg_cnt, hdmi->hpd_regs); - if (ret) { - DRM_DEV_ERROR(dev, "failed to enable hpd regulators: %d\n", ret); - goto fail; - } - - ret = pinctrl_pm_select_default_state(dev); - if (ret) { - DRM_DEV_ERROR(dev, "pinctrl state chg failed: %d\n", ret); - goto fail; - } - - ret = gpio_config(hdmi, true); - if (ret) { - DRM_DEV_ERROR(dev, "failed to configure GPIOs: %d\n", ret); - goto fail; - } - - pm_runtime_get_sync(dev); - enable_hpd_clocks(hdmi, true); - - msm_hdmi_set_mode(hdmi, false); - msm_hdmi_phy_reset(hdmi); - msm_hdmi_set_mode(hdmi, true); - - hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b); - - /* enable HPD events: */ - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, - HDMI_HPD_INT_CTRL_INT_CONNECT | - HDMI_HPD_INT_CTRL_INT_EN); - - /* set timeout to 4.1ms (max) for hardware debounce */ - spin_lock_irqsave(&hdmi->reg_lock, flags); - hpd_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); - hpd_ctrl |= HDMI_HPD_CTRL_TIMEOUT(0x1fff); - - /* Toggle HPD circuit to trigger HPD sense */ - hdmi_write(hdmi, REG_HDMI_HPD_CTRL, - ~HDMI_HPD_CTRL_ENABLE & hpd_ctrl); - hdmi_write(hdmi, REG_HDMI_HPD_CTRL, - HDMI_HPD_CTRL_ENABLE | hpd_ctrl); - spin_unlock_irqrestore(&hdmi->reg_lock, flags); - - /* - * wait for a bit so that HPD is sensed if there is a cable already - * connected. Returning early will result in someone calling the - * connnector func's detect() callback too early - */ - msleep(15); - - return 0; - -fail: - return ret; -} - -void msm_hdmi_hpd_disable(struct hdmi_bridge *hdmi_bridge) -{ - struct hdmi *hdmi = hdmi_bridge->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct device *dev = &hdmi->pdev->dev; - int ret; - - /* Disable HPD interrupt */ - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, 0); - - msm_hdmi_set_mode(hdmi, false); - - enable_hpd_clocks(hdmi, false); - pm_runtime_put(dev); - - ret = gpio_config(hdmi, false); - if (ret) - dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret); - - ret = pinctrl_pm_select_sleep_state(dev); - if (ret) - dev_warn(dev, "pinctrl state chg failed: %d\n", ret); - - ret = regulator_bulk_disable(config->hpd_reg_cnt, hdmi->hpd_regs); - if (ret) - dev_warn(dev, "failed to disable hpd regulator: %d\n", ret); -} - -void msm_hdmi_hpd_irq(struct drm_bridge *bridge) -{ - struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); - struct hdmi *hdmi = hdmi_bridge->hdmi; - uint32_t hpd_int_status, hpd_int_ctrl; - - /* Process HPD: */ - hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); - hpd_int_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_INT_CTRL); - - if ((hpd_int_ctrl & HDMI_HPD_INT_CTRL_INT_EN) && - (hpd_int_status & HDMI_HPD_INT_STATUS_INT)) { - bool detected = !!(hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED); - - /* ack & disable (temporarily) HPD events: */ - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, - HDMI_HPD_INT_CTRL_INT_ACK); - - DBG("status=%04x, ctrl=%04x", hpd_int_status, hpd_int_ctrl); - - /* detect disconnect if we are connected or visa versa: */ - hpd_int_ctrl = HDMI_HPD_INT_CTRL_INT_EN; - if (!detected) - hpd_int_ctrl |= HDMI_HPD_INT_CTRL_INT_CONNECT; - hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, hpd_int_ctrl); - - queue_work(hdmi->workq, &hdmi_bridge->hpd_work); - } -} - -static enum drm_connector_status detect_reg(struct hdmi *hdmi) -{ - uint32_t hpd_int_status; - - pm_runtime_get_sync(&hdmi->pdev->dev); - enable_hpd_clocks(hdmi, true); - - hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); - - enable_hpd_clocks(hdmi, false); - pm_runtime_put(&hdmi->pdev->dev); - - return (hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED) ? - connector_status_connected : connector_status_disconnected; -} - -#define HPD_GPIO_INDEX 2 -static enum drm_connector_status detect_gpio(struct hdmi *hdmi) -{ - const struct hdmi_platform_config *config = hdmi->config; - struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX]; - - return gpiod_get_value(hpd_gpio.gpiod) ? - connector_status_connected : - connector_status_disconnected; -} - -enum drm_connector_status msm_hdmi_bridge_detect( - struct drm_bridge *bridge) -{ - struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); - struct hdmi *hdmi = hdmi_bridge->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX]; - enum drm_connector_status stat_gpio, stat_reg; - int retry = 20; - - /* - * some platforms may not have hpd gpio. Rely only on the status - * provided by REG_HDMI_HPD_INT_STATUS in this case. - */ - if (!hpd_gpio.gpiod) - return detect_reg(hdmi); - - do { - stat_gpio = detect_gpio(hdmi); - stat_reg = detect_reg(hdmi); - - if (stat_gpio == stat_reg) - break; - - mdelay(10); - } while (--retry); - - /* the status we get from reading gpio seems to be more reliable, - * so trust that one the most if we didn't manage to get hdmi and - * gpio status to agree: - */ - if (stat_gpio != stat_reg) { - DBG("HDMI_HPD_INT_STATUS tells us: %d", stat_reg); - DBG("hpd gpio tells us: %d", stat_gpio); - } - - return stat_gpio; -} -<<<<<<< -======= - -static void hdmi_connector_destroy(struct drm_connector *connector) -{ - struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); - - hdp_disable(hdmi_connector); - - drm_connector_cleanup(connector); - - kfree(hdmi_connector); -} - -static int msm_hdmi_connector_get_modes(struct drm_connector *connector) -{ - struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); - struct hdmi *hdmi = hdmi_connector->hdmi; - struct edid *edid; - uint32_t hdmi_ctrl; - int ret = 0; - - hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); - hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE); - - edid = drm_get_edid(connector, hdmi->i2c); - - hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl); - - hdmi->hdmi_mode = drm_detect_hdmi_monitor(edid); - drm_connector_update_edid_property(connector, edid); - - if (edid) { - ret = drm_add_edid_modes(connector, edid); - kfree(edid); - } - - return ret; -} - -static int msm_hdmi_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); - struct hdmi *hdmi = hdmi_connector->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct msm_drm_private *priv = connector->dev->dev_private; - struct msm_kms *kms = priv->kms; - long actual, requested; - - requested = 1000 * mode->clock; - actual = kms->funcs->round_pixclk(kms, - requested, hdmi_connector->hdmi->encoder); - - /* for mdp5/apq8074, we manage our own pixel clk (as opposed to - * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder - * instead): - */ - if (config->pwr_clk_cnt > 0) - actual = clk_round_rate(hdmi->pwr_clks[0], actual); - - DBG("requested=%ld, actual=%ld", requested, actual); - - if (actual != requested) - return MODE_CLOCK_RANGE; - - return 0; -} - -static const struct drm_connector_funcs hdmi_connector_funcs = { - .detect = hdmi_connector_detect, - .fill_modes = drm_helper_probe_single_connector_modes, - .destroy = hdmi_connector_destroy, - .reset = drm_atomic_helper_connector_reset, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - -static const struct drm_connector_helper_funcs msm_hdmi_connector_helper_funcs = { - .get_modes = msm_hdmi_connector_get_modes, - .mode_valid = msm_hdmi_connector_mode_valid, -}; - -/* initialize connector */ -struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi) -{ - struct drm_connector *connector = NULL; - struct hdmi_connector *hdmi_connector; - - hdmi_connector = kzalloc(sizeof(*hdmi_connector), GFP_KERNEL); - if (!hdmi_connector) - return ERR_PTR(-ENOMEM); - - hdmi_connector->hdmi = hdmi; - INIT_WORK(&hdmi_connector->hpd_work, msm_hdmi_hotplug_work); - - connector = &hdmi_connector->base; - - drm_connector_init_with_ddc(hdmi->dev, connector, - &hdmi_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA, - hdmi->i2c); - drm_connector_helper_add(connector, &msm_hdmi_connector_helper_funcs); - - connector->polled = DRM_CONNECTOR_POLL_HPD; - - connector->interlace_allowed = 0; - connector->doublescan_allowed = 0; - - drm_connector_attach_encoder(connector, hdmi->encoder); - - return connector; -} ->>>>>>> diff --git a/rr-cache/117d6e0d01961082f5d745c3be1c8d93830351a2/preimage b/rr-cache/117d6e0d01961082f5d745c3be1c8d93830351a2/preimage deleted file mode 100644 index 98fd2d5..0000000 --- a/rr-cache/117d6e0d01961082f5d745c3be1c8d93830351a2/preimage +++ /dev/null @@ -1,1079 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Copyright (c) 2019-2020. Linaro Limited. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -#define EDID_BLOCK_SIZE 128 -#define EDID_NUM_BLOCKS 2 - -struct lt9611uxc { - struct device *dev; - struct drm_bridge bridge; - struct drm_connector connector; - - struct regmap *regmap; - /* Protects all accesses to registers by stopping the on-chip MCU */ - struct mutex ocm_lock; - - struct wait_queue_head wq; - struct work_struct work; - - struct device_node *dsi0_node; - struct device_node *dsi1_node; - struct mipi_dsi_device *dsi0; - struct mipi_dsi_device *dsi1; - struct platform_device *audio_pdev; - - struct gpio_desc *reset_gpio; - struct gpio_desc *enable_gpio; - - struct regulator_bulk_data supplies[2]; - - struct i2c_client *client; - - bool hpd_supported; - bool edid_read; - /* can be accessed from different threads, so protect this with ocm_lock */ - bool hdmi_connected; - uint8_t fw_version; -}; - -#define LT9611_PAGE_CONTROL 0xff - -static const struct regmap_range_cfg lt9611uxc_ranges[] = { - { - .name = "register_range", - .range_min = 0, - .range_max = 0xd0ff, - .selector_reg = LT9611_PAGE_CONTROL, - .selector_mask = 0xff, - .selector_shift = 0, - .window_start = 0, - .window_len = 0x100, - }, -}; - -static const struct regmap_config lt9611uxc_regmap_config = { - .reg_bits = 8, - .val_bits = 8, - .max_register = 0xffff, - .ranges = lt9611uxc_ranges, - .num_ranges = ARRAY_SIZE(lt9611uxc_ranges), -}; - -struct lt9611uxc_mode { - u16 hdisplay; - u16 vdisplay; - u8 vrefresh; - bool dual_dsi; -}; - -/* - * This chip supports only a fixed set of modes. - * Enumerate them here to check whether the mode is supported. - */ -static struct lt9611uxc_mode lt9611uxc_modes[] = { - { 3840, 2160, 60, true }, - { 3840, 2160, 30, true }, - { 1920, 1080, 60, false }, - { 1920, 1080, 30, false }, - { 1920, 1080, 25, false }, - { 1366, 768, 60, false }, - { 1360, 768, 60, false }, - { 1280, 1024, 60, false }, - { 1280, 800, 60, false }, - { 1280, 720, 60, false }, - { 1280, 720, 50, false }, - { 1280, 720, 30, false }, - { 1152, 864, 60, false }, - { 1024, 768, 60, false }, - { 800, 600, 60, false }, - { 720, 576, 50, false }, - { 720, 480, 60, false }, - { 640, 480, 60, false }, -}; - -static struct lt9611uxc *bridge_to_lt9611uxc(struct drm_bridge *bridge) -{ - return container_of(bridge, struct lt9611uxc, bridge); -} - -static struct lt9611uxc *connector_to_lt9611uxc(struct drm_connector *connector) -{ - return container_of(connector, struct lt9611uxc, connector); -} - -static void lt9611uxc_lock(struct lt9611uxc *lt9611uxc) -{ - mutex_lock(<9611uxc->ocm_lock); - regmap_write(lt9611uxc->regmap, 0x80ee, 0x01); -} - -static void lt9611uxc_unlock(struct lt9611uxc *lt9611uxc) -{ - regmap_write(lt9611uxc->regmap, 0x80ee, 0x00); - msleep(50); - mutex_unlock(<9611uxc->ocm_lock); -} - -static irqreturn_t lt9611uxc_irq_thread_handler(int irq, void *dev_id) -{ - struct lt9611uxc *lt9611uxc = dev_id; - unsigned int irq_status = 0; - unsigned int hpd_status = 0; - - lt9611uxc_lock(lt9611uxc); - - regmap_read(lt9611uxc->regmap, 0xb022, &irq_status); - regmap_read(lt9611uxc->regmap, 0xb023, &hpd_status); - if (irq_status) - regmap_write(lt9611uxc->regmap, 0xb022, 0); - - if (irq_status & BIT(0)) { - lt9611uxc->edid_read = !!(hpd_status & BIT(0)); - wake_up_all(<9611uxc->wq); - } - - if (irq_status & BIT(1)) { - lt9611uxc->hdmi_connected = hpd_status & BIT(1); - schedule_work(<9611uxc->work); - } - - lt9611uxc_unlock(lt9611uxc); - - return IRQ_HANDLED; -} - -static void lt9611uxc_hpd_work(struct work_struct *work) -{ - struct lt9611uxc *lt9611uxc = container_of(work, struct lt9611uxc, work); - bool connected; - - if (lt9611uxc->connector.dev) { - if (lt9611uxc->connector.dev->mode_config.funcs) - drm_kms_helper_hotplug_event(lt9611uxc->connector.dev); - } else { - - mutex_lock(<9611uxc->ocm_lock); - connected = lt9611uxc->hdmi_connected; - mutex_unlock(<9611uxc->ocm_lock); - - drm_bridge_hpd_notify(<9611uxc->bridge, - connected ? - connector_status_connected : - connector_status_disconnected); - } -} - -static void lt9611uxc_reset(struct lt9611uxc *lt9611uxc) -{ - gpiod_set_value_cansleep(lt9611uxc->reset_gpio, 1); - msleep(20); - - gpiod_set_value_cansleep(lt9611uxc->reset_gpio, 0); - msleep(20); - - gpiod_set_value_cansleep(lt9611uxc->reset_gpio, 1); - msleep(300); -} - -static void lt9611uxc_assert_5v(struct lt9611uxc *lt9611uxc) -{ - if (!lt9611uxc->enable_gpio) - return; - - gpiod_set_value_cansleep(lt9611uxc->enable_gpio, 1); - msleep(20); -} - -static int lt9611uxc_regulator_init(struct lt9611uxc *lt9611uxc) -{ - int ret; - - lt9611uxc->supplies[0].supply = "vdd"; - lt9611uxc->supplies[1].supply = "vcc"; - - ret = devm_regulator_bulk_get(lt9611uxc->dev, 2, lt9611uxc->supplies); - if (ret < 0) - return ret; - - return regulator_set_load(lt9611uxc->supplies[0].consumer, 200000); -} - -static int lt9611uxc_regulator_enable(struct lt9611uxc *lt9611uxc) -{ - int ret; - - ret = regulator_enable(lt9611uxc->supplies[0].consumer); - if (ret < 0) - return ret; - - usleep_range(1000, 10000); /* 50000 according to dtsi */ - - ret = regulator_enable(lt9611uxc->supplies[1].consumer); - if (ret < 0) { - regulator_disable(lt9611uxc->supplies[0].consumer); - return ret; - } - - return 0; -} - -static struct lt9611uxc_mode *lt9611uxc_find_mode(const struct drm_display_mode *mode) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(lt9611uxc_modes); i++) { - if (lt9611uxc_modes[i].hdisplay == mode->hdisplay && - lt9611uxc_modes[i].vdisplay == mode->vdisplay && - lt9611uxc_modes[i].vrefresh == drm_mode_vrefresh(mode)) { - return <9611uxc_modes[i]; - } - } - - return NULL; -} - -static struct mipi_dsi_device *lt9611uxc_attach_dsi(struct lt9611uxc *lt9611uxc, - struct device_node *dsi_node) -{ - const struct mipi_dsi_device_info info = { "lt9611uxc", 0, NULL }; - struct mipi_dsi_device *dsi; - struct mipi_dsi_host *host; - struct device *dev = lt9611uxc->dev; - int ret; - - host = of_find_mipi_dsi_host_by_node(dsi_node); - if (!host) { - dev_err(dev, "failed to find dsi host\n"); - return ERR_PTR(-EPROBE_DEFER); - } - - dsi = devm_mipi_dsi_device_register_full(dev, host, &info); - if (IS_ERR(dsi)) { - dev_err(dev, "failed to create dsi device\n"); - return dsi; - } - - dsi->lanes = 4; - dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_VIDEO_HSE; - - ret = devm_mipi_dsi_attach(dev, dsi); - if (ret < 0) { - dev_err(dev, "failed to attach dsi to host\n"); - return ERR_PTR(ret); - } - - return dsi; -} - -static int lt9611uxc_connector_get_modes(struct drm_connector *connector) -{ - struct lt9611uxc *lt9611uxc = connector_to_lt9611uxc(connector); - unsigned int count; - struct edid *edid; - - edid = lt9611uxc->bridge.funcs->get_edid(<9611uxc->bridge, connector); - drm_connector_update_edid_property(connector, edid); - count = drm_add_edid_modes(connector, edid); - kfree(edid); - - return count; -} - -static enum drm_connector_status lt9611uxc_connector_detect(struct drm_connector *connector, - bool force) -{ - struct lt9611uxc *lt9611uxc = connector_to_lt9611uxc(connector); - - return lt9611uxc->bridge.funcs->detect(<9611uxc->bridge); -} - -static enum drm_mode_status lt9611uxc_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - struct lt9611uxc_mode *lt9611uxc_mode = lt9611uxc_find_mode(mode); - struct lt9611uxc *lt9611uxc = connector_to_lt9611uxc(connector); - - if (!lt9611uxc_mode) - return MODE_BAD; - - if (lt9611uxc_mode->dual_dsi && (!lt9611uxc->dsi0 || !lt9611uxc->dsi1)) - return MODE_BAD; - - return MODE_OK; -} - -static const struct drm_connector_helper_funcs lt9611uxc_bridge_connector_helper_funcs = { - .get_modes = lt9611uxc_connector_get_modes, - .mode_valid = lt9611uxc_connector_mode_valid, -}; - -static const struct drm_connector_funcs lt9611uxc_bridge_connector_funcs = { - .fill_modes = drm_helper_probe_single_connector_modes, - .detect = lt9611uxc_connector_detect, - .destroy = drm_connector_cleanup, - .reset = drm_atomic_helper_connector_reset, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - -static int lt9611uxc_connector_init(struct drm_bridge *bridge, struct lt9611uxc *lt9611uxc) -{ - int ret; - - if (!bridge->encoder) { - DRM_ERROR("Parent encoder object not found"); - return -ENODEV; - } - - lt9611uxc->connector.polled = DRM_CONNECTOR_POLL_HPD; - - drm_connector_helper_add(<9611uxc->connector, - <9611uxc_bridge_connector_helper_funcs); - ret = drm_connector_init(bridge->dev, <9611uxc->connector, - <9611uxc_bridge_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA); - if (ret) { - DRM_ERROR("Failed to initialize connector with drm\n"); - return ret; - } - - return drm_connector_attach_encoder(<9611uxc->connector, bridge->encoder); -} - -static int lt9611uxc_bridge_attach(struct drm_bridge *bridge, - enum drm_bridge_attach_flags flags) -{ - struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); - int ret; - - if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { - ret = lt9611uxc_connector_init(bridge, lt9611uxc); - if (ret < 0) - return ret; - } - -<<<<<<< - /* Attach primary DSI */ - if (lt9611uxc->dsi0_node) { - lt9611uxc->dsi0 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi0_node); - if (IS_ERR(lt9611uxc->dsi0)) - return PTR_ERR(lt9611uxc->dsi0); - } - - /* Attach secondary DSI, if specified */ - if (lt9611uxc->dsi1_node) { - lt9611uxc->dsi1 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi1_node); - if (IS_ERR(lt9611uxc->dsi1)) { - ret = PTR_ERR(lt9611uxc->dsi1); - goto err_unregister_dsi0; - } - } - - return 0; - -err_unregister_dsi0: - if (lt9611uxc->dsi0) { - mipi_dsi_detach(lt9611uxc->dsi0); - mipi_dsi_device_unregister(lt9611uxc->dsi0); - } - - return ret; -======= - return 0; ->>>>>>> -} - -static enum drm_mode_status -lt9611uxc_bridge_mode_valid(struct drm_bridge *bridge, - const struct drm_display_info *info, - const struct drm_display_mode *mode) -{ - struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); - struct lt9611uxc_mode *lt9611uxc_mode = lt9611uxc_find_mode(mode); - - if (!lt9611uxc_mode) - return MODE_BAD; - - if (lt9611uxc_mode->dual_dsi && (!lt9611uxc->dsi0 || !lt9611uxc->dsi1)) - return MODE_BAD; - - return MODE_OK; -} - -static void lt9611uxc_video_setup(struct lt9611uxc *lt9611uxc, - const struct drm_display_mode *mode) -{ - u32 h_total, hactive, hsync_len, hfront_porch; - u32 v_total, vactive, vsync_len, vfront_porch; - - h_total = mode->htotal; - v_total = mode->vtotal; - - hactive = mode->hdisplay; - hsync_len = mode->hsync_end - mode->hsync_start; - hfront_porch = mode->hsync_start - mode->hdisplay; - - vactive = mode->vdisplay; - vsync_len = mode->vsync_end - mode->vsync_start; - vfront_porch = mode->vsync_start - mode->vdisplay; - - if (lt9611uxc->dsi0 && lt9611uxc->dsi1) - regmap_write(lt9611uxc->regmap, 0xb025, 0x03); - else if (lt9611uxc->dsi0) - regmap_write(lt9611uxc->regmap, 0xb025, 0x01); - else - regmap_write(lt9611uxc->regmap, 0xb025, 0x02); - - regmap_write(lt9611uxc->regmap, 0xd00d, (u8)(v_total / 256)); - regmap_write(lt9611uxc->regmap, 0xd00e, (u8)(v_total % 256)); - - regmap_write(lt9611uxc->regmap, 0xd00f, (u8)(vactive / 256)); - regmap_write(lt9611uxc->regmap, 0xd010, (u8)(vactive % 256)); - - regmap_write(lt9611uxc->regmap, 0xd011, (u8)(h_total / 256)); - regmap_write(lt9611uxc->regmap, 0xd012, (u8)(h_total % 256)); - - regmap_write(lt9611uxc->regmap, 0xd013, (u8)(hactive / 256)); - regmap_write(lt9611uxc->regmap, 0xd014, (u8)(hactive % 256)); - - regmap_write(lt9611uxc->regmap, 0xd015, (u8)(vsync_len % 256)); - - regmap_update_bits(lt9611uxc->regmap, 0xd016, 0xf, (u8)(hsync_len / 256)); - regmap_write(lt9611uxc->regmap, 0xd017, (u8)(hsync_len % 256)); - - regmap_update_bits(lt9611uxc->regmap, 0xd018, 0xf, (u8)(vfront_porch / 256)); - regmap_write(lt9611uxc->regmap, 0xd019, (u8)(vfront_porch % 256)); - - regmap_update_bits(lt9611uxc->regmap, 0xd01a, 0xf, (u8)(hfront_porch / 256)); - regmap_write(lt9611uxc->regmap, 0xd01b, (u8)(hfront_porch % 256)); -} - -static void lt9611uxc_bridge_mode_set(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adj_mode) -{ - struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); - - lt9611uxc_lock(lt9611uxc); - lt9611uxc_video_setup(lt9611uxc, mode); - lt9611uxc_unlock(lt9611uxc); -} - -static enum drm_connector_status lt9611uxc_bridge_detect(struct drm_bridge *bridge) -{ - struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); - unsigned int reg_val = 0; - int ret; - bool connected = true; - - lt9611uxc_lock(lt9611uxc); - - if (lt9611uxc->hpd_supported) { - ret = regmap_read(lt9611uxc->regmap, 0xb023, ®_val); - - if (ret) - dev_err(lt9611uxc->dev, "failed to read hpd status: %d\n", ret); - else - connected = reg_val & BIT(1); - } - lt9611uxc->hdmi_connected = connected; - - lt9611uxc_unlock(lt9611uxc); - - return connected ? connector_status_connected : - connector_status_disconnected; -} - -static int lt9611uxc_wait_for_edid(struct lt9611uxc *lt9611uxc) -{ - return wait_event_interruptible_timeout(lt9611uxc->wq, lt9611uxc->edid_read, - msecs_to_jiffies(500)); -} - -static int lt9611uxc_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) -{ - struct lt9611uxc *lt9611uxc = data; - int ret; - - if (len > EDID_BLOCK_SIZE) - return -EINVAL; - - if (block >= EDID_NUM_BLOCKS) - return -EINVAL; - - lt9611uxc_lock(lt9611uxc); - - regmap_write(lt9611uxc->regmap, 0xb00b, 0x10); - - regmap_write(lt9611uxc->regmap, 0xb00a, block * EDID_BLOCK_SIZE); - - ret = regmap_noinc_read(lt9611uxc->regmap, 0xb0b0, buf, len); - if (ret) - dev_err(lt9611uxc->dev, "edid read failed: %d\n", ret); - - lt9611uxc_unlock(lt9611uxc); - - return 0; -}; - -static struct edid *lt9611uxc_bridge_get_edid(struct drm_bridge *bridge, - struct drm_connector *connector) -{ - struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); - int ret; - - ret = lt9611uxc_wait_for_edid(lt9611uxc); - if (ret < 0) { - dev_err(lt9611uxc->dev, "wait for EDID failed: %d\n", ret); - return NULL; - } else if (ret == 0) { - dev_err(lt9611uxc->dev, "wait for EDID timeout\n"); - return NULL; - } - - return drm_do_get_edid(connector, lt9611uxc_get_edid_block, lt9611uxc); -} - -static const struct drm_bridge_funcs lt9611uxc_bridge_funcs = { - .attach = lt9611uxc_bridge_attach, - .mode_valid = lt9611uxc_bridge_mode_valid, - .mode_set = lt9611uxc_bridge_mode_set, - .detect = lt9611uxc_bridge_detect, - .get_edid = lt9611uxc_bridge_get_edid, -}; - -static int lt9611uxc_parse_dt(struct device *dev, - struct lt9611uxc *lt9611uxc) -{ - lt9611uxc->dsi0_node = of_graph_get_remote_node(dev->of_node, 0, -1); - lt9611uxc->dsi1_node = of_graph_get_remote_node(dev->of_node, 1, -1); - - if (!lt9611uxc->dsi0_node && !lt9611uxc->dsi1_node) { - dev_err(lt9611uxc->dev, "failed to get remote node for primary dsi\n"); - return -ENODEV; - } - -<<<<<<< -======= - ->>>>>>> - return 0; -} - -static int lt9611uxc_gpio_init(struct lt9611uxc *lt9611uxc) -{ - struct device *dev = lt9611uxc->dev; - - lt9611uxc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); - if (IS_ERR(lt9611uxc->reset_gpio)) { - dev_err(dev, "failed to acquire reset gpio\n"); - return PTR_ERR(lt9611uxc->reset_gpio); - } - - lt9611uxc->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); - if (IS_ERR(lt9611uxc->enable_gpio)) { - dev_err(dev, "failed to acquire enable gpio\n"); - return PTR_ERR(lt9611uxc->enable_gpio); - } - - return 0; -} - -static int lt9611uxc_read_device_rev(struct lt9611uxc *lt9611uxc) -{ - unsigned int rev0, rev1, rev2; - int ret; - - lt9611uxc_lock(lt9611uxc); - - ret = regmap_read(lt9611uxc->regmap, 0x8100, &rev0); - ret |= regmap_read(lt9611uxc->regmap, 0x8101, &rev1); - ret |= regmap_read(lt9611uxc->regmap, 0x8102, &rev2); - if (ret) - dev_err(lt9611uxc->dev, "failed to read revision: %d\n", ret); - else - dev_info(lt9611uxc->dev, "LT9611 revision: 0x%02x.%02x.%02x\n", rev0, rev1, rev2); - - lt9611uxc_unlock(lt9611uxc); - - return ret; -} - -static int lt9611uxc_read_version(struct lt9611uxc *lt9611uxc) -{ - unsigned int rev; - int ret; - - lt9611uxc_lock(lt9611uxc); - - ret = regmap_read(lt9611uxc->regmap, 0xb021, &rev); - if (ret) - dev_err(lt9611uxc->dev, "failed to read revision: %d\n", ret); - else - dev_info(lt9611uxc->dev, "LT9611 version: 0x%02x\n", rev); - - lt9611uxc_unlock(lt9611uxc); - - return ret < 0 ? ret : rev; -} - -static int lt9611uxc_hdmi_hw_params(struct device *dev, void *data, - struct hdmi_codec_daifmt *fmt, - struct hdmi_codec_params *hparms) -{ - /* - * LT9611UXC will automatically detect rate and sample size, so no need - * to setup anything here. - */ - return 0; -} - -static void lt9611uxc_audio_shutdown(struct device *dev, void *data) -{ -} - -static int lt9611uxc_hdmi_i2s_get_dai_id(struct snd_soc_component *component, - struct device_node *endpoint) -{ - struct of_endpoint of_ep; - int ret; - - ret = of_graph_parse_endpoint(endpoint, &of_ep); - if (ret < 0) - return ret; - - /* - * HDMI sound should be located as reg = <2> - * Then, it is sound port 0 - */ - if (of_ep.port == 2) - return 0; - - return -EINVAL; -} - -static const struct hdmi_codec_ops lt9611uxc_codec_ops = { - .hw_params = lt9611uxc_hdmi_hw_params, - .audio_shutdown = lt9611uxc_audio_shutdown, - .get_dai_id = lt9611uxc_hdmi_i2s_get_dai_id, -}; - -static int lt9611uxc_audio_init(struct device *dev, struct lt9611uxc *lt9611uxc) -{ - struct hdmi_codec_pdata codec_data = { - .ops = <9611uxc_codec_ops, - .max_i2s_channels = 2, - .i2s = 1, - .data = lt9611uxc, - }; - - lt9611uxc->audio_pdev = - platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, - PLATFORM_DEVID_AUTO, - &codec_data, sizeof(codec_data)); - - return PTR_ERR_OR_ZERO(lt9611uxc->audio_pdev); -} - -static void lt9611uxc_audio_exit(struct lt9611uxc *lt9611uxc) -{ - if (lt9611uxc->audio_pdev) { - platform_device_unregister(lt9611uxc->audio_pdev); - lt9611uxc->audio_pdev = NULL; - } -} - -#define LT9611UXC_FW_PAGE_SIZE 32 -static void lt9611uxc_firmware_write_page(struct lt9611uxc *lt9611uxc, u16 addr, const u8 *buf) -{ - struct reg_sequence seq_write_prepare[] = { - REG_SEQ0(0x805a, 0x04), - REG_SEQ0(0x805a, 0x00), - - REG_SEQ0(0x805e, 0xdf), - REG_SEQ0(0x805a, 0x20), - REG_SEQ0(0x805a, 0x00), - REG_SEQ0(0x8058, 0x21), - }; - - struct reg_sequence seq_write_addr[] = { - REG_SEQ0(0x805b, (addr >> 16) & 0xff), - REG_SEQ0(0x805c, (addr >> 8) & 0xff), - REG_SEQ0(0x805d, addr & 0xff), - REG_SEQ0(0x805a, 0x10), - REG_SEQ0(0x805a, 0x00), - }; - - regmap_write(lt9611uxc->regmap, 0x8108, 0xbf); - msleep(20); - regmap_write(lt9611uxc->regmap, 0x8108, 0xff); - msleep(20); - regmap_multi_reg_write(lt9611uxc->regmap, seq_write_prepare, ARRAY_SIZE(seq_write_prepare)); - regmap_noinc_write(lt9611uxc->regmap, 0x8059, buf, LT9611UXC_FW_PAGE_SIZE); - regmap_multi_reg_write(lt9611uxc->regmap, seq_write_addr, ARRAY_SIZE(seq_write_addr)); - msleep(20); -} - -static void lt9611uxc_firmware_read_page(struct lt9611uxc *lt9611uxc, u16 addr, char *buf) -{ - struct reg_sequence seq_read_page[] = { - REG_SEQ0(0x805a, 0xa0), - REG_SEQ0(0x805a, 0x80), - REG_SEQ0(0x805b, (addr >> 16) & 0xff), - REG_SEQ0(0x805c, (addr >> 8) & 0xff), - REG_SEQ0(0x805d, addr & 0xff), - REG_SEQ0(0x805a, 0x90), - REG_SEQ0(0x805a, 0x80), - REG_SEQ0(0x8058, 0x21), - }; - - regmap_multi_reg_write(lt9611uxc->regmap, seq_read_page, ARRAY_SIZE(seq_read_page)); - regmap_noinc_read(lt9611uxc->regmap, 0x805f, buf, LT9611UXC_FW_PAGE_SIZE); -} - -static char *lt9611uxc_firmware_read(struct lt9611uxc *lt9611uxc, size_t size) -{ - struct reg_sequence seq_read_setup[] = { - REG_SEQ0(0x805a, 0x84), - REG_SEQ0(0x805a, 0x80), - }; - - char *readbuf; - u16 offset; - - readbuf = kzalloc(ALIGN(size, 32), GFP_KERNEL); - if (!readbuf) - return NULL; - - regmap_multi_reg_write(lt9611uxc->regmap, seq_read_setup, ARRAY_SIZE(seq_read_setup)); - - for (offset = 0; - offset < size; - offset += LT9611UXC_FW_PAGE_SIZE) - lt9611uxc_firmware_read_page(lt9611uxc, offset, &readbuf[offset]); - - return readbuf; -} - -static int lt9611uxc_firmware_update(struct lt9611uxc *lt9611uxc) -{ - int ret; - u16 offset; - size_t remain; - char *readbuf; - const struct firmware *fw; - - struct reg_sequence seq_setup[] = { - REG_SEQ0(0x805e, 0xdf), - REG_SEQ0(0x8058, 0x00), - REG_SEQ0(0x8059, 0x50), - REG_SEQ0(0x805a, 0x10), - REG_SEQ0(0x805a, 0x00), - }; - - - struct reg_sequence seq_block_erase[] = { - REG_SEQ0(0x805a, 0x04), - REG_SEQ0(0x805a, 0x00), - REG_SEQ0(0x805b, 0x00), - REG_SEQ0(0x805c, 0x00), - REG_SEQ0(0x805d, 0x00), - REG_SEQ0(0x805a, 0x01), - REG_SEQ0(0x805a, 0x00), - }; - - ret = request_firmware(&fw, "lt9611uxc_fw.bin", lt9611uxc->dev); - if (ret < 0) - return ret; - - dev_info(lt9611uxc->dev, "Updating firmware\n"); - lt9611uxc_lock(lt9611uxc); - - regmap_multi_reg_write(lt9611uxc->regmap, seq_setup, ARRAY_SIZE(seq_setup)); - - /* - * Need erase block 2 timess here. Sometimes, block erase can fail. - * This is a workaroud. - */ - regmap_multi_reg_write(lt9611uxc->regmap, seq_block_erase, ARRAY_SIZE(seq_block_erase)); - msleep(3000); - regmap_multi_reg_write(lt9611uxc->regmap, seq_block_erase, ARRAY_SIZE(seq_block_erase)); - msleep(3000); - - for (offset = 0, remain = fw->size; - remain >= LT9611UXC_FW_PAGE_SIZE; - offset += LT9611UXC_FW_PAGE_SIZE, remain -= LT9611UXC_FW_PAGE_SIZE) - lt9611uxc_firmware_write_page(lt9611uxc, offset, fw->data + offset); - - if (remain > 0) { - char buf[LT9611UXC_FW_PAGE_SIZE]; - - memset(buf, 0xff, LT9611UXC_FW_PAGE_SIZE); - memcpy(buf, fw->data + offset, remain); - lt9611uxc_firmware_write_page(lt9611uxc, offset, buf); - } - msleep(20); - - readbuf = lt9611uxc_firmware_read(lt9611uxc, fw->size); - if (!readbuf) { - ret = -ENOMEM; - goto out; - } - - if (!memcmp(readbuf, fw->data, fw->size)) { - dev_err(lt9611uxc->dev, "Firmware update failed\n"); - print_hex_dump(KERN_ERR, "fw: ", DUMP_PREFIX_OFFSET, 16, 1, readbuf, fw->size, false); - ret = -EINVAL; - } else { - dev_info(lt9611uxc->dev, "Firmware updates successfully\n"); - ret = 0; - } - kfree(readbuf); - -out: - lt9611uxc_unlock(lt9611uxc); - lt9611uxc_reset(lt9611uxc); - release_firmware(fw); - - return ret; -} - -static ssize_t lt9611uxc_firmware_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) -{ - struct lt9611uxc *lt9611uxc = dev_get_drvdata(dev); - int ret; - - ret = lt9611uxc_firmware_update(lt9611uxc); - if (ret < 0) - return ret; - return len; -} - -static ssize_t lt9611uxc_firmware_show(struct device *dev, struct device_attribute *attr, char *buf) -{ - struct lt9611uxc *lt9611uxc = dev_get_drvdata(dev); - - return sysfs_emit(buf, "%02x\n", lt9611uxc->fw_version); -} - -static DEVICE_ATTR_RW(lt9611uxc_firmware); - -static struct attribute *lt9611uxc_attrs[] = { - &dev_attr_lt9611uxc_firmware.attr, - NULL, -}; - -static const struct attribute_group lt9611uxc_attr_group = { - .attrs = lt9611uxc_attrs, -}; - -static const struct attribute_group *lt9611uxc_attr_groups[] = { - <9611uxc_attr_group, - NULL, -}; - -static int lt9611uxc_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct lt9611uxc *lt9611uxc; - struct device *dev = &client->dev; - int ret; - bool fw_updated = false; - - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { - dev_err(dev, "device doesn't support I2C\n"); - return -ENODEV; - } - - lt9611uxc = devm_kzalloc(dev, sizeof(*lt9611uxc), GFP_KERNEL); - if (!lt9611uxc) - return -ENOMEM; - - lt9611uxc->dev = &client->dev; - lt9611uxc->client = client; - mutex_init(<9611uxc->ocm_lock); - - lt9611uxc->regmap = devm_regmap_init_i2c(client, <9611uxc_regmap_config); - if (IS_ERR(lt9611uxc->regmap)) { - dev_err(lt9611uxc->dev, "regmap i2c init failed\n"); - return PTR_ERR(lt9611uxc->regmap); - } - - ret = lt9611uxc_parse_dt(&client->dev, lt9611uxc); - if (ret) { - dev_err(dev, "failed to parse device tree\n"); - return ret; - } - - ret = lt9611uxc_gpio_init(lt9611uxc); - if (ret < 0) - goto err_of_put; - - ret = lt9611uxc_regulator_init(lt9611uxc); - if (ret < 0) - goto err_of_put; - - lt9611uxc_assert_5v(lt9611uxc); - - ret = lt9611uxc_regulator_enable(lt9611uxc); - if (ret) - goto err_of_put; - - lt9611uxc_reset(lt9611uxc); - - ret = lt9611uxc_read_device_rev(lt9611uxc); - if (ret) { - dev_err(dev, "failed to read chip rev\n"); - goto err_disable_regulators; - } - -retry: - ret = lt9611uxc_read_version(lt9611uxc); - if (ret < 0) { - dev_err(dev, "failed to read FW version\n"); - goto err_disable_regulators; - } else if (ret == 0) { - if (!fw_updated) { - fw_updated = true; - dev_err(dev, "FW version 0, enforcing firmware update\n"); - ret = lt9611uxc_firmware_update(lt9611uxc); - if (ret < 0) - goto err_disable_regulators; - else - goto retry; - } else { - dev_err(dev, "FW version 0, update failed\n"); - ret = -EOPNOTSUPP; - goto err_disable_regulators; - } - } else if (ret < 0x40) { - dev_info(dev, "FW version 0x%x, HPD not supported\n", ret); - } else { - lt9611uxc->hpd_supported = true; - } - lt9611uxc->fw_version = ret; - - init_waitqueue_head(<9611uxc->wq); - INIT_WORK(<9611uxc->work, lt9611uxc_hpd_work); - - ret = devm_request_threaded_irq(dev, client->irq, NULL, - lt9611uxc_irq_thread_handler, - IRQF_ONESHOT, "lt9611uxc", lt9611uxc); - if (ret) { - dev_err(dev, "failed to request irq\n"); - goto err_disable_regulators; - } - - i2c_set_clientdata(client, lt9611uxc); - - lt9611uxc->bridge.funcs = <9611uxc_bridge_funcs; - lt9611uxc->bridge.of_node = client->dev.of_node; - lt9611uxc->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID; - if (lt9611uxc->hpd_supported) - lt9611uxc->bridge.ops |= DRM_BRIDGE_OP_HPD; - lt9611uxc->bridge.type = DRM_MODE_CONNECTOR_HDMIA; - - drm_bridge_add(<9611uxc->bridge); - - /* Attach primary DSI, if specified */ - if (lt9611uxc->dsi0_node) { - lt9611uxc->dsi0 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi0_node); - if (IS_ERR(lt9611uxc->dsi0)) { - ret = PTR_ERR(lt9611uxc->dsi0); - goto err_remove_bridge; - } - } - - /* Attach secondary DSI, if specified */ - if (lt9611uxc->dsi1_node) { - lt9611uxc->dsi1 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi1_node); - if (IS_ERR(lt9611uxc->dsi1)) { - ret = PTR_ERR(lt9611uxc->dsi1); - goto err_remove_bridge; - } - } - - return lt9611uxc_audio_init(dev, lt9611uxc); - -err_remove_bridge: - drm_bridge_remove(<9611uxc->bridge); - -err_disable_regulators: - regulator_bulk_disable(ARRAY_SIZE(lt9611uxc->supplies), lt9611uxc->supplies); - -err_of_put: - of_node_put(lt9611uxc->dsi1_node); - of_node_put(lt9611uxc->dsi0_node); - - return ret; -} - -static int lt9611uxc_remove(struct i2c_client *client) -{ - struct lt9611uxc *lt9611uxc = i2c_get_clientdata(client); - - disable_irq(client->irq); - flush_scheduled_work(); - lt9611uxc_audio_exit(lt9611uxc); - drm_bridge_remove(<9611uxc->bridge); - - mutex_destroy(<9611uxc->ocm_lock); - - regulator_bulk_disable(ARRAY_SIZE(lt9611uxc->supplies), lt9611uxc->supplies); - - of_node_put(lt9611uxc->dsi1_node); - of_node_put(lt9611uxc->dsi0_node); - - return 0; -} - -static struct i2c_device_id lt9611uxc_id[] = { - { "lontium,lt9611uxc", 0 }, - { /* sentinel */ } -}; - -static const struct of_device_id lt9611uxc_match_table[] = { - { .compatible = "lontium,lt9611uxc" }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, lt9611uxc_match_table); - -static struct i2c_driver lt9611uxc_driver = { - .driver = { - .name = "lt9611uxc", - .of_match_table = lt9611uxc_match_table, - .dev_groups = lt9611uxc_attr_groups, - }, - .probe = lt9611uxc_probe, - .remove = lt9611uxc_remove, - .id_table = lt9611uxc_id, -}; -module_i2c_driver(lt9611uxc_driver); - -MODULE_AUTHOR("Dmitry Baryshkov "); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/160ccd05dcdf530f39d8e72ddd1cfdd8d2847c1a/preimage b/rr-cache/160ccd05dcdf530f39d8e72ddd1cfdd8d2847c1a/preimage deleted file mode 100644 index e8408e1..0000000 --- a/rr-cache/160ccd05dcdf530f39d8e72ddd1cfdd8d2847c1a/preimage +++ /dev/null @@ -1,243 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Linaro Ltd. - * Author: Manivannan Sadhasivam - */ - -#include -#include -#include -#include "internal.h" - -<<<<<<< -======= -const char * const mhi_state_str[MHI_STATE_MAX] = { - [MHI_STATE_RESET] = "RESET", - [MHI_STATE_READY] = "READY", - [MHI_STATE_M0] = "M0", - [MHI_STATE_M1] = "M1", - [MHI_STATE_M2] = "M2", - [MHI_STATE_M3] = "M3", - [MHI_STATE_M3_FAST] = "M3 FAST", - [MHI_STATE_BHI] = "BHI", - [MHI_STATE_SYS_ERR] = "SYS ERROR", -}; - ->>>>>>> -bool __must_check mhi_ep_check_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, - enum mhi_state cur_mhi_state, - enum mhi_state mhi_state) -{ - bool valid = false; - - switch (mhi_state) { - case MHI_STATE_READY: - valid = (cur_mhi_state == MHI_STATE_RESET); - break; - case MHI_STATE_M0: - valid = (cur_mhi_state == MHI_STATE_READY || - cur_mhi_state == MHI_STATE_M3); - break; - case MHI_STATE_M3: - valid = (cur_mhi_state == MHI_STATE_M0); - break; - case MHI_STATE_SYS_ERR: - /* Transition to SYS_ERR state is allowed all the time */ - valid = true; - break; - default: - break; - } - - return valid; -} - -int mhi_ep_set_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state mhi_state) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - - if (!mhi_ep_check_mhi_state(mhi_cntrl, mhi_cntrl->mhi_state, mhi_state)) { - dev_err(dev, "MHI state change to %s from %s is not allowed!\n", -<<<<<<< - TO_MHI_STATE_STR(mhi_state), - TO_MHI_STATE_STR(mhi_cntrl->mhi_state)); -======= - mhi_state_str(mhi_state), - mhi_state_str(mhi_cntrl->mhi_state)); ->>>>>>> - return -EACCES; - } - - switch (mhi_state) { - case MHI_STATE_READY: - mhi_ep_mmio_masked_write(mhi_cntrl, MHISTATUS, -<<<<<<< - MHISTATUS_READY_MASK, - MHISTATUS_READY_SHIFT, 1); - - mhi_ep_mmio_masked_write(mhi_cntrl, MHISTATUS, - MHISTATUS_MHISTATE_MASK, - MHISTATUS_MHISTATE_SHIFT, mhi_state); - break; - case MHI_STATE_SYS_ERR: - mhi_ep_mmio_masked_write(mhi_cntrl, MHISTATUS, - MHISTATUS_SYSERR_MASK, - MHISTATUS_SYSERR_SHIFT, 1); - - mhi_ep_mmio_masked_write(mhi_cntrl, MHISTATUS, - MHISTATUS_MHISTATE_MASK, - MHISTATUS_MHISTATE_SHIFT, mhi_state); - break; - case MHI_STATE_M1: - case MHI_STATE_M2: - dev_err(dev, "MHI state (%s) not supported\n", TO_MHI_STATE_STR(mhi_state)); -======= - MHISTATUS_READY_MASK, 1); - - mhi_ep_mmio_masked_write(mhi_cntrl, MHISTATUS, - MHISTATUS_MHISTATE_MASK, mhi_state); - break; - case MHI_STATE_SYS_ERR: - mhi_ep_mmio_masked_write(mhi_cntrl, MHISTATUS, - MHISTATUS_SYSERR_MASK, 1); - - mhi_ep_mmio_masked_write(mhi_cntrl, MHISTATUS, - MHISTATUS_MHISTATE_MASK, mhi_state); - break; - case MHI_STATE_M1: - case MHI_STATE_M2: - dev_err(dev, "MHI state (%s) not supported\n", mhi_state_str(mhi_state)); ->>>>>>> - return -EOPNOTSUPP; - case MHI_STATE_M0: - case MHI_STATE_M3: - mhi_ep_mmio_masked_write(mhi_cntrl, MHISTATUS, -<<<<<<< - MHISTATUS_MHISTATE_MASK, - MHISTATUS_MHISTATE_SHIFT, mhi_state); - break; - default: - dev_err(dev, "Invalid MHI state (%d)", mhi_state); -======= - MHISTATUS_MHISTATE_MASK, mhi_state); - break; - default: - dev_err(dev, "Invalid MHI state (%d)\n", mhi_state); ->>>>>>> - return -EINVAL; - } - - mhi_cntrl->mhi_state = mhi_state; - - return 0; -} - -int mhi_ep_set_m0_state(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - enum mhi_state old_state; - int ret; - - /* If MHI is in M3, resume suspended channels */ - spin_lock_bh(&mhi_cntrl->state_lock); - old_state = mhi_cntrl->mhi_state; - if (old_state == MHI_STATE_M3) - mhi_ep_resume_channels(mhi_cntrl); - - ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_M0); - if (ret) { - mhi_ep_handle_syserr(mhi_cntrl); - spin_unlock_bh(&mhi_cntrl->state_lock); - return ret; - } - - spin_unlock_bh(&mhi_cntrl->state_lock); - /* Signal host that the device moved to M0 */ - ret = mhi_ep_send_state_change_event(mhi_cntrl, MHI_STATE_M0); - if (ret) { -<<<<<<< - dev_err(dev, "Failed sending M0 state change event: %d\n", ret); -======= - dev_err(dev, "Failed sending M0 state change event\n"); ->>>>>>> - return ret; - } - - if (old_state == MHI_STATE_READY) { - /* Allow the host to process state change event */ - mdelay(1); - - /* Send AMSS EE event to host */ - ret = mhi_ep_send_ee_event(mhi_cntrl, MHI_EP_AMSS_EE); - if (ret) { -<<<<<<< - dev_err(dev, "Failed sending AMSS EE event: %d\n", ret); -======= - dev_err(dev, "Failed sending AMSS EE event\n"); ->>>>>>> - return ret; - } - } - - return 0; -} - -int mhi_ep_set_m3_state(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - int ret; - - spin_lock_bh(&mhi_cntrl->state_lock); - ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_M3); - if (ret) { - mhi_ep_handle_syserr(mhi_cntrl); - spin_unlock_bh(&mhi_cntrl->state_lock); - return ret; - } - - spin_unlock_bh(&mhi_cntrl->state_lock); - mhi_ep_suspend_channels(mhi_cntrl); - - /* Signal host that the device moved to M3 */ - ret = mhi_ep_send_state_change_event(mhi_cntrl, MHI_STATE_M3); - if (ret) { -<<<<<<< - dev_err(dev, "Failed sending M3 state change event: %d\n", ret); -======= - dev_err(dev, "Failed sending M3 state change event\n"); ->>>>>>> - return ret; - } - - return 0; -} - -int mhi_ep_set_ready_state(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - enum mhi_state mhi_state; - int ret, is_ready; - - spin_lock_bh(&mhi_cntrl->state_lock); - /* Ensure that the MHISTATUS is set to RESET by host */ -<<<<<<< - mhi_ep_mmio_masked_read(mhi_cntrl, MHISTATUS, MHISTATUS_MHISTATE_MASK, - MHISTATUS_MHISTATE_SHIFT, &mhi_state); - mhi_ep_mmio_masked_read(mhi_cntrl, MHISTATUS, MHISTATUS_READY_MASK, - MHISTATUS_READY_SHIFT, &is_ready); -======= - mhi_state = mhi_ep_mmio_masked_read(mhi_cntrl, MHISTATUS, MHISTATUS_MHISTATE_MASK); - is_ready = mhi_ep_mmio_masked_read(mhi_cntrl, MHISTATUS, MHISTATUS_READY_MASK); ->>>>>>> - - if (mhi_state != MHI_STATE_RESET || is_ready) { - dev_err(dev, "READY state transition failed. MHI host not in RESET state\n"); - spin_unlock_bh(&mhi_cntrl->state_lock); - return -EFAULT; - } - - ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_READY); - spin_unlock_bh(&mhi_cntrl->state_lock); - - return ret; -} diff --git a/rr-cache/1f448ef9b3a9eaf1fa37ea460f917006d348b78c/postimage b/rr-cache/1f448ef9b3a9eaf1fa37ea460f917006d348b78c/postimage deleted file mode 100644 index 5500c49..0000000 --- a/rr-cache/1f448ef9b3a9eaf1fa37ea460f917006d348b78c/postimage +++ /dev/null @@ -1,3811 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "reset.h" -#include "gdsc.h" - -enum { - P_BI_TCXO, - P_AUD_REF_CLK, - P_CORE_BI_PLL_TEST_SE, - P_GPLL0_OUT_EVEN, - P_GPLL0_OUT_MAIN, - P_GPLL7_OUT_MAIN, - P_GPLL9_OUT_MAIN, - P_SLEEP_CLK, -}; - -static struct clk_alpha_pll gpll0 = { - .offset = 0x0, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_trion_even[] = { - { 0x0, 1 }, - { 0x1, 2 }, - { 0x3, 4 }, - { 0x7, 8 }, - { } -}; - -static struct clk_alpha_pll_postdiv gpll0_out_even = { - .offset = 0x0, - .post_div_shift = 8, - .post_div_table = post_div_table_trion_even, - .num_post_div = ARRAY_SIZE(post_div_table_trion_even), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .width = 4, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll0_out_even", - .parent_hws = (const struct clk_hw*[]){ - &gpll0.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_postdiv_trion_ops, - }, -}; - -static struct clk_alpha_pll gpll7 = { - .offset = 0x1a000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gpll7", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll9 = { - .offset = 0x1c000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gpll9", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static const struct parent_map gcc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_0[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_SLEEP_CLK, 5 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_1[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "sleep_clk", .name = "sleep_clk" }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_SLEEP_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_2[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "sleep_clk", .name = "sleep_clk" }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_3[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_3[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se"}, -}; - -static const struct parent_map gcc_parent_map_4[] = { - { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_4[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_5[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL7_OUT_MAIN, 3 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_5[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll7.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_6[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL9_OUT_MAIN, 2 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_6[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll9.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_7[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_AUD_REF_CLK, 2 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_7[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { - .cmd_rcgr = 0x48014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), - F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_emac_ptp_clk_src = { - .cmd_rcgr = 0x6038, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_emac_ptp_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_emac_ptp_clk_src", - .parent_data = gcc_parents_5, - .num_parents = ARRAY_SIZE(gcc_parents_5), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { - F(2500000, P_BI_TCXO, 1, 25, 192), - F(5000000, P_BI_TCXO, 1, 25, 96), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), - F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_emac_rgmii_clk_src = { - .cmd_rcgr = 0x601c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_emac_rgmii_clk_src", - .parent_data = gcc_parents_5, - .num_parents = ARRAY_SIZE(gcc_parents_5), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_gp1_clk_src = { - .cmd_rcgr = 0x64004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp2_clk_src = { - .cmd_rcgr = 0x65004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp3_clk_src = { - .cmd_rcgr = 0x66004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { - .cmd_rcgr = 0x6b02c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { - .cmd_rcgr = 0x8d02c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { - .cmd_rcgr = 0x6f014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_phy_refgen_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pdm2_clk_src = { - .cmd_rcgr = 0x33010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pdm2_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_qspi_core_clk_src = { - .cmd_rcgr = 0x4b008, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qspi_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { - F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), - F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), - F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), - F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), - F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), - F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), - F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), - F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), - F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), - F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), - F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), - F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), - F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), - { } -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { - .cmd_rcgr = 0x17148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { - .cmd_rcgr = 0x17278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { - .cmd_rcgr = 0x173a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { - .cmd_rcgr = 0x174d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { - .cmd_rcgr = 0x17608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { - .cmd_rcgr = 0x17738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { - .cmd_rcgr = 0x17868, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s6_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { - .cmd_rcgr = 0x17998, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s7_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { - .cmd_rcgr = 0x18148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { - .cmd_rcgr = 0x18278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { - .cmd_rcgr = 0x183a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { - .cmd_rcgr = 0x184d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { - .cmd_rcgr = 0x18608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { - .cmd_rcgr = 0x18738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { - .cmd_rcgr = 0x1e148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { - .cmd_rcgr = 0x1e278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { - .cmd_rcgr = 0x1e3a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { - .cmd_rcgr = 0x1e4d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { - .cmd_rcgr = 0x1e608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { - .cmd_rcgr = 0x1e738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { - F(400000, P_BI_TCXO, 12, 1, 4), - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { - .cmd_rcgr = 0x1400c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_6, - .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk_src", - .parent_data = gcc_parents_6, - .num_parents = ARRAY_SIZE(gcc_parents_6), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_floor_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { - F(400000, P_BI_TCXO, 12, 1, 4), - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { - .cmd_rcgr = 0x1600c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_3, - .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_apps_clk_src", - .parent_data = gcc_parents_3, - .num_parents = ARRAY_SIZE(gcc_parents_3), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_floor_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { - F(105495, P_BI_TCXO, 2, 1, 91), - { } -}; - -static struct clk_rcg2 gcc_tsif_ref_clk_src = { - .cmd_rcgr = 0x36010, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_7, - .freq_tbl = ftbl_gcc_tsif_ref_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ref_clk_src", - .parent_data = gcc_parents_7, - .num_parents = ARRAY_SIZE(gcc_parents_7), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { - .cmd_rcgr = 0x75020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { - .cmd_rcgr = 0x75060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { - .cmd_rcgr = 0x75094, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_clk_src", - .parent_data = gcc_parents_4, - .num_parents = ARRAY_SIZE(gcc_parents_4), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { - .cmd_rcgr = 0x75078, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { - .cmd_rcgr = 0x77020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { - .cmd_rcgr = 0x77060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { - .cmd_rcgr = 0x77094, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk_src", - .parent_data = gcc_parents_4, - .num_parents = ARRAY_SIZE(gcc_parents_4), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { - .cmd_rcgr = 0x77078, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { - F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), - F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), - F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { - .cmd_rcgr = 0xf01c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), - F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { - .cmd_rcgr = 0xf034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { - .cmd_rcgr = 0x1001c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_master_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { - .cmd_rcgr = 0x10034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_mock_utmi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { - .cmd_rcgr = 0xf060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { - .cmd_rcgr = 0x10060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { - .halt_reg = 0x90018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x90018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_noc_pcie_tbu_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_card_axi_clk = { - .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x750c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x750c0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_card_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { - .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x750c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x750c0, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_aggre_ufs_card_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { - .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x770c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x770c0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x770c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x770c0, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_aggre_ufs_phy_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { - .halt_reg = 0xf07c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf07c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { - .halt_reg = 0x1007c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1007c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_usb3_sec_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_boot_rom_ahb_clk = { - .halt_reg = 0x38004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x38004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_boot_rom_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for camss boot - */ -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0xb008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_hf_axi_clk = { - .halt_reg = 0xb030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_sf_axi_clk = { - .halt_reg = 0xb034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_sf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to camss, so no need to poll */ -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0xb044, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb044, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { - .halt_reg = 0xf078, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { - .halt_reg = 0x10078, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_sec_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_ahb_clk = { - .halt_reg = 0x48000, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw }, - .num_parents = 1, - /* required for cpuss */ - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_dvm_bus_clk = { - .halt_reg = 0x48190, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48190, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_dvm_bus_clk", - /* required for cpuss */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_gnoc_clk = { - .halt_reg = 0x48004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x48004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_gnoc_clk", - /* required for cpuss */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_rbcpr_clk = { - .halt_reg = 0x48008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_rbcpr_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ddrss_gpu_axi_clk = { - .halt_reg = 0x71154, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x71154, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ddrss_gpu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for disp boot - */ -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0xb00c, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb00c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_hf_axi_clk = { - .halt_reg = 0xb038, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_sf_axi_clk = { - .halt_reg = 0xb03c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb03c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_sf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to disp, so no need to poll */ -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0xb048, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_axi_clk = { - .halt_reg = 0x6010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_ptp_clk = { - .halt_reg = 0x6034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_ptp_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_emac_ptp_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_rgmii_clk = { - .halt_reg = 0x6018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_rgmii_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_emac_rgmii_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_slv_ahb_clk = { - .halt_reg = 0x6014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x6014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x6014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_slv_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp1_clk = { - .halt_reg = 0x64000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x64000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp2_clk = { - .halt_reg = 0x65000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x65000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp3_clk = { - .halt_reg = 0x66000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x66000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x71004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x71004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x71004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - /* required for gpu */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0_out_even.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_iref_clk = { - .halt_reg = 0x8c010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_iref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_memnoc_gfx_clk = { - .halt_reg = 0x7100c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7100c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_memnoc_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { - .halt_reg = 0x71018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x71018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_snoc_dvm_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_at_clk = { - .halt_reg = 0x4d010, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_at_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_axi_clk = { - .halt_reg = 0x4d008, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_cfg_ahb_clk = { - .halt_reg = 0x4d004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x4d004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x4d004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_cfg_ahb_clk", - /* required for npu */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(18), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(19), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0_out_even.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_trig_clk = { - .halt_reg = 0x4d00c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_trig_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie0_phy_refgen_clk = { - .halt_reg = 0x6f02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie0_phy_refgen_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_phy_refgen_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie1_phy_refgen_clk = { - .halt_reg = 0x6f030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie1_phy_refgen_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_phy_refgen_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_aux_clk = { - .halt_reg = 0x6b020, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { - .halt_reg = 0x6b01c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x6b01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_clkref_clk = { - .halt_reg = 0x8c00c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_mstr_axi_clk = { - .halt_reg = 0x6b018, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_mstr_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ -static struct clk_branch gcc_pcie_0_pipe_clk = { - .halt_reg = 0x6b024, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_axi_clk = { - .halt_reg = 0x6b014, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x6b014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_slv_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { - .halt_reg = 0x6b010, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_slv_q2a_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_aux_clk = { - .halt_reg = 0x8d020, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(29), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_1_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { - .halt_reg = 0x8d01c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8d01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(28), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_clkref_clk = { - .halt_reg = 0x8c02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_mstr_axi_clk = { - .halt_reg = 0x8d018, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_mstr_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ -static struct clk_branch gcc_pcie_1_pipe_clk = { - .halt_reg = 0x8d024, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(30), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_axi_clk = { - .halt_reg = 0x8d014, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8d014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_slv_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { - .halt_reg = 0x8d010, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_slv_q2a_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_phy_aux_clk = { - .halt_reg = 0x6f004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm2_clk = { - .halt_reg = 0x3300c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3300c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pdm2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_ahb_clk = { - .halt_reg = 0x33004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x33004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x33004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_xo4_clk = { - .halt_reg = 0x33008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_xo4_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_prng_ahb_clk = { - .halt_reg = 0x34004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_prng_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { - .halt_reg = 0xb018, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb018, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_camera_nrt_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { - .halt_reg = 0xb01c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb01c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_camera_rt_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_disp_ahb_clk = { - .halt_reg = 0xb020, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb020, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb020, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_disp_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { - .halt_reg = 0xb010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_video_cvp_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { - .halt_reg = 0xb014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_video_vcodec_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { - .halt_reg = 0x4b000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4b000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_cnoc_periph_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_core_clk = { - .halt_reg = 0x4b004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4b004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qspi_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s0_clk = { - .halt_reg = 0x17144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s1_clk = { - .halt_reg = 0x17274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s2_clk = { - .halt_reg = 0x173a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s3_clk = { - .halt_reg = 0x174d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s4_clk = { - .halt_reg = 0x17604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(14), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s5_clk = { - .halt_reg = 0x17734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s6_clk = { - .halt_reg = 0x17864, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s6_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s6_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s7_clk = { - .halt_reg = 0x17994, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s7_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s7_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s0_clk = { - .halt_reg = 0x18144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s1_clk = { - .halt_reg = 0x18274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(23), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s2_clk = { - .halt_reg = 0x183a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(24), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s3_clk = { - .halt_reg = 0x184d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s4_clk = { - .halt_reg = 0x18604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s5_clk = { - .halt_reg = 0x18734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s0_clk = { - .halt_reg = 0x1e144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s1_clk = { - .halt_reg = 0x1e274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s2_clk = { - .halt_reg = 0x1e3a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s3_clk = { - .halt_reg = 0x1e4d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s4_clk = { - .halt_reg = 0x1e604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(8), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s5_clk = { - .halt_reg = 0x1e734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { - .halt_reg = 0x17004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { - .halt_reg = 0x18004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(20), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { - .halt_reg = 0x18008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x18008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { - .halt_reg = 0x1e004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_2_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { - .halt_reg = 0x1e008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x1e008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_2_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_ahb_clk = { - .halt_reg = 0x14008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_apps_clk = { - .halt_reg = 0x14004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_sdcc2_apps_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_ahb_clk = { - .halt_reg = 0x16008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_apps_clk = { - .halt_reg = 0x16004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_apps_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_sdcc4_apps_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x4819c, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw }, - .num_parents = 1, - /* required for cpuss */ - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_inactivity_timers_clk = { - .halt_reg = 0x3600c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3600c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_inactivity_timers_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ref_clk = { - .halt_reg = 0x36008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ref_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_tsif_ref_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ahb_clk = { - .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_axi_clk = { - .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { - .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_clkref_clk = { - .halt_reg = 0x8c004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ice_core_clk = { - .halt_reg = 0x7505c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7505c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7505c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_ice_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { - .halt_reg = 0x7505c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7505c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7505c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_ice_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_phy_aux_clk = { - .halt_reg = 0x75090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75090, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { - .halt_reg = 0x75090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75090, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_phy_aux_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x7501c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_rx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x750ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_rx_symbol_1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x75018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_tx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_unipro_core_clk = { - .halt_reg = 0x75058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_unipro_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { - .halt_reg = 0x75058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75058, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_unipro_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_mem_clkref_clk = { - .halt_reg = 0x8c000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_mem_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ahb_clk = { - .halt_reg = 0x77014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_clk = { - .halt_reg = 0x77010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x77010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77010, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_clk = { - .halt_reg = 0x7705c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7705c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7705c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_ice_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { - .halt_reg = 0x7705c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7705c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7705c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_ice_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_clk = { - .halt_reg = 0x77090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77090, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { - .halt_reg = 0x77090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77090, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_phy_aux_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x7701c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_rx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x770ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_rx_symbol_1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x77018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_tx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_clk = { - .halt_reg = 0x77058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_unipro_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { - .halt_reg = 0x77058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77058, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_unipro_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_master_clk = { - .halt_reg = 0xf010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { - .halt_reg = 0xf018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_sleep_clk = { - .halt_reg = 0xf014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_master_clk = { - .halt_reg = 0x10010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_master_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { - .halt_reg = 0x10018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_mock_utmi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_sleep_clk = { - .halt_reg = 0x10014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_clkref_clk = { - .halt_reg = 0x8c008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_aux_clk = { - .halt_reg = 0xf050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { - .halt_reg = 0xf054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0xf058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_clkref_clk = { - .halt_reg = 0x8c028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_aux_clk = { - .halt_reg = 0x10050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { - .halt_reg = 0x10054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_com_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x10058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for video boot - */ -static struct clk_branch gcc_video_ahb_clk = { - .halt_reg = 0xb004, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi0_clk = { - .halt_reg = 0xb024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axi0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi1_clk = { - .halt_reg = 0xb028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axi1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axic_clk = { - .halt_reg = 0xb02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axic_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to video, so no need to poll */ -static struct clk_branch gcc_video_xo_clk = { - .halt_reg = 0xb040, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct gdsc emac_gdsc = { - .gdscr = 0x6004, - .pd = { - .name = "emac_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_card_gdsc = { - .gdscr = 0x75004, - .pd = { - .name = "ufs_card_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_phy_gdsc = { - .gdscr = 0x77004, - .pd = { - .name = "ufs_phy_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_prim_gdsc = { - .gdscr = 0xf004, - .pd = { - .name = "usb30_prim_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_sec_gdsc = { - .gdscr = 0x10004, - .pd = { - .name = "usb30_sec_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct clk_regmap *gcc_sm8150_clocks[] = { - [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, - [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, - [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = - &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, - [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, - [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = - &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, - [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, - [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, - [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, - [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, - [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, - [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, - [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, - [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, - [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, - [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, - [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, - [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, - [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, - [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr, - [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr, - [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, - [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr, - [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr, - [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr, - [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, - [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, - [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, - [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, - [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, - [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, - [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, - [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, - [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, - [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, - [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, - [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr, - [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, - [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, - [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, - [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, - [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr, - [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, - [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, - [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, - [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, - [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, - [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, - [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, - [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, - [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, - [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, - [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, - [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, - [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, - [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, - [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, - [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, - [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, - [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, - [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, - [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, - [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, - [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, - [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, - [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, - [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, - [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, - [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, - [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, - [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, - [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, - [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, - [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, - [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, - [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, - [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, - [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, - [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, - [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, - [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, - [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, - [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, - [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, - [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, - [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, - [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, - [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, - [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, - [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, - [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, - [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, - [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, - [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, - [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, - [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, - [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, - [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, - [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, - [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, - [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, - [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, - [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, - [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, - [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, - [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, - [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, - [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, - [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, - [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, - [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, - [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, - [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, - [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, - [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, - [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, - [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, - [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, - [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, - [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, - [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, - [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, - [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, - [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, - [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, - [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, - [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, - [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, - [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, - [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, - [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, - [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, - [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = - &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, - [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, - [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = - &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, - [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, - [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = - &gcc_ufs_card_unipro_core_clk_src.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = - &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, - [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, - [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, - [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, - [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, - [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, - [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = - &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, - [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, - [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, - [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = - &gcc_ufs_phy_unipro_core_clk_src.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = - &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, - [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, - [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = - &gcc_usb30_prim_mock_utmi_clk_src.clkr, - [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, - [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, - [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, - [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, - [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = - &gcc_usb30_sec_mock_utmi_clk_src.clkr, - [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, - [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, - [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, - [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, - [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, - [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, - [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, - [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, - [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, - [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, - [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, - [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr, - [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, - [GPLL0] = &gpll0.clkr, - [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, - [GPLL7] = &gpll7.clkr, - [GPLL9] = &gpll9.clkr, -}; - -static const struct qcom_reset_map gcc_sm8150_resets[] = { - [GCC_EMAC_BCR] = { 0x6000 }, - [GCC_GPU_BCR] = { 0x71000 }, - [GCC_MMSS_BCR] = { 0xb000 }, - [GCC_NPU_BCR] = { 0x4d000 }, - [GCC_PCIE_0_BCR] = { 0x6b000 }, - [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, - [GCC_PCIE_1_BCR] = { 0x8d000 }, - [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, - [GCC_PCIE_PHY_BCR] = { 0x6f000 }, - [GCC_PDM_BCR] = { 0x33000 }, - [GCC_PRNG_BCR] = { 0x34000 }, - [GCC_QSPI_BCR] = { 0x24008 }, - [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, - [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, - [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, - [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, - [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, - [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, - [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, - [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, - [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, - [GCC_SDCC2_BCR] = { 0x14000 }, - [GCC_SDCC4_BCR] = { 0x16000 }, - [GCC_TSIF_BCR] = { 0x36000 }, - [GCC_UFS_CARD_BCR] = { 0x75000 }, - [GCC_UFS_PHY_BCR] = { 0x77000 }, - [GCC_USB30_PRIM_BCR] = { 0xf000 }, - [GCC_USB30_SEC_BCR] = { 0x10000 }, - [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, -}; - -static struct gdsc *gcc_sm8150_gdscs[] = { - [UFS_CARD_GDSC] = &ufs_card_gdsc, - [UFS_PHY_GDSC] = &ufs_phy_gdsc, - [USB30_PRIM_GDSC] = &usb30_prim_gdsc, - [USB30_SEC_GDSC] = &usb30_sec_gdsc, - [EMAC_GDSC] = &emac_gdsc, -}; - -static const struct regmap_config gcc_sm8150_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x9c040, - .fast_io = true, -}; - -static const struct qcom_cc_desc gcc_sm8150_desc = { - .config = &gcc_sm8150_regmap_config, - .clks = gcc_sm8150_clocks, - .num_clks = ARRAY_SIZE(gcc_sm8150_clocks), - .resets = gcc_sm8150_resets, - .num_resets = ARRAY_SIZE(gcc_sm8150_resets), - .gdscs = gcc_sm8150_gdscs, - .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs), -}; - -static const struct of_device_id gcc_sm8150_match_table[] = { - { .compatible = "qcom,gcc-sm8150" }, - { } -}; -MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table); - -static int gcc_sm8150_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - - regmap = qcom_cc_map(pdev, &gcc_sm8150_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ - regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); - regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - - return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap); -} - -static struct platform_driver gcc_sm8150_driver = { - .probe = gcc_sm8150_probe, - .driver = { - .name = "gcc-sm8150", - .of_match_table = gcc_sm8150_match_table, - }, -}; - -static int __init gcc_sm8150_init(void) -{ - return platform_driver_register(&gcc_sm8150_driver); -} -subsys_initcall(gcc_sm8150_init); - -static void __exit gcc_sm8150_exit(void) -{ - platform_driver_unregister(&gcc_sm8150_driver); -} -module_exit(gcc_sm8150_exit); - -MODULE_DESCRIPTION("QTI GCC SM8150 Driver"); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/1f448ef9b3a9eaf1fa37ea460f917006d348b78c/preimage b/rr-cache/1f448ef9b3a9eaf1fa37ea460f917006d348b78c/preimage deleted file mode 100644 index b657f0f..0000000 --- a/rr-cache/1f448ef9b3a9eaf1fa37ea460f917006d348b78c/preimage +++ /dev/null @@ -1,3812 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "reset.h" -#include "gdsc.h" - -enum { - P_BI_TCXO, - P_AUD_REF_CLK, - P_CORE_BI_PLL_TEST_SE, - P_GPLL0_OUT_EVEN, - P_GPLL0_OUT_MAIN, - P_GPLL7_OUT_MAIN, - P_GPLL9_OUT_MAIN, - P_SLEEP_CLK, -}; - -static struct clk_alpha_pll gpll0 = { - .offset = 0x0, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_trion_even[] = { - { 0x0, 1 }, - { 0x1, 2 }, - { 0x3, 4 }, - { 0x7, 8 }, - { } -}; - -static struct clk_alpha_pll_postdiv gpll0_out_even = { - .offset = 0x0, - .post_div_shift = 8, - .post_div_table = post_div_table_trion_even, - .num_post_div = ARRAY_SIZE(post_div_table_trion_even), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .width = 4, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll0_out_even", - .parent_hws = (const struct clk_hw*[]){ - &gpll0.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_postdiv_trion_ops, - }, -}; - -static struct clk_alpha_pll gpll7 = { - .offset = 0x1a000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gpll7", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll9 = { - .offset = 0x1c000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gpll9", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static const struct parent_map gcc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_0[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_SLEEP_CLK, 5 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_1[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "sleep_clk", .name = "sleep_clk" }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_SLEEP_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_2[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "sleep_clk", .name = "sleep_clk" }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_3[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_3[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se"}, -}; - -static const struct parent_map gcc_parent_map_4[] = { - { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_4[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_5[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL7_OUT_MAIN, 3 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_5[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll7.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_6[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL9_OUT_MAIN, 2 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_6[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll9.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_7[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_AUD_REF_CLK, 2 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_7[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { - .cmd_rcgr = 0x48014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), - F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_emac_ptp_clk_src = { - .cmd_rcgr = 0x6038, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_emac_ptp_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_emac_ptp_clk_src", - .parent_data = gcc_parents_5, - .num_parents = ARRAY_SIZE(gcc_parents_5), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { - F(2500000, P_BI_TCXO, 1, 25, 192), - F(5000000, P_BI_TCXO, 1, 25, 96), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), - F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_emac_rgmii_clk_src = { - .cmd_rcgr = 0x601c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_emac_rgmii_clk_src", - .parent_data = gcc_parents_5, - .num_parents = ARRAY_SIZE(gcc_parents_5), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_gp1_clk_src = { - .cmd_rcgr = 0x64004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp2_clk_src = { - .cmd_rcgr = 0x65004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp3_clk_src = { - .cmd_rcgr = 0x66004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { - .cmd_rcgr = 0x6b02c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { - .cmd_rcgr = 0x8d02c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { - .cmd_rcgr = 0x6f014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_phy_refgen_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pdm2_clk_src = { - .cmd_rcgr = 0x33010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pdm2_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_qspi_core_clk_src = { - .cmd_rcgr = 0x4b008, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qspi_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { - F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), - F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), - F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), - F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), - F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), - F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), - F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), - F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), - F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), - F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), - F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), - F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), - F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), - { } -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { - .cmd_rcgr = 0x17148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { - .cmd_rcgr = 0x17278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { - .cmd_rcgr = 0x173a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { - .cmd_rcgr = 0x174d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { - .cmd_rcgr = 0x17608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { - .cmd_rcgr = 0x17738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { - .cmd_rcgr = 0x17868, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s6_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { - .cmd_rcgr = 0x17998, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s7_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { - .cmd_rcgr = 0x18148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { - .cmd_rcgr = 0x18278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { - .cmd_rcgr = 0x183a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { - .cmd_rcgr = 0x184d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { - .cmd_rcgr = 0x18608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { - .cmd_rcgr = 0x18738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { - .cmd_rcgr = 0x1e148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { - .cmd_rcgr = 0x1e278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { - .cmd_rcgr = 0x1e3a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { - .cmd_rcgr = 0x1e4d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { - .cmd_rcgr = 0x1e608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { - .cmd_rcgr = 0x1e738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { - F(400000, P_BI_TCXO, 12, 1, 4), - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { - .cmd_rcgr = 0x1400c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_6, - .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk_src", - .parent_data = gcc_parents_6, - .num_parents = ARRAY_SIZE(gcc_parents_6), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_floor_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { - F(400000, P_BI_TCXO, 12, 1, 4), - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { - .cmd_rcgr = 0x1600c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_3, - .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_apps_clk_src", - .parent_data = gcc_parents_3, - .num_parents = ARRAY_SIZE(gcc_parents_3), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_floor_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { - F(105495, P_BI_TCXO, 2, 1, 91), - { } -}; - -static struct clk_rcg2 gcc_tsif_ref_clk_src = { - .cmd_rcgr = 0x36010, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_7, - .freq_tbl = ftbl_gcc_tsif_ref_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ref_clk_src", - .parent_data = gcc_parents_7, - .num_parents = ARRAY_SIZE(gcc_parents_7), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { - .cmd_rcgr = 0x75020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { - .cmd_rcgr = 0x75060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { - .cmd_rcgr = 0x75094, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_clk_src", - .parent_data = gcc_parents_4, - .num_parents = ARRAY_SIZE(gcc_parents_4), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { - .cmd_rcgr = 0x75078, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { - .cmd_rcgr = 0x77020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { - .cmd_rcgr = 0x77060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { - .cmd_rcgr = 0x77094, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk_src", - .parent_data = gcc_parents_4, - .num_parents = ARRAY_SIZE(gcc_parents_4), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { - .cmd_rcgr = 0x77078, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { - F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), - F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), - F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { - .cmd_rcgr = 0xf01c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), - F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { - .cmd_rcgr = 0xf034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { - .cmd_rcgr = 0x1001c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_master_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { - .cmd_rcgr = 0x10034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_mock_utmi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { - .cmd_rcgr = 0xf060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { - .cmd_rcgr = 0x10060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { - .halt_reg = 0x90018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x90018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_noc_pcie_tbu_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_card_axi_clk = { - .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x750c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x750c0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_card_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { - .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x750c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x750c0, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_aggre_ufs_card_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { - .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x770c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x770c0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x770c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x770c0, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_aggre_ufs_phy_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { - .halt_reg = 0xf07c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf07c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { - .halt_reg = 0x1007c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1007c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_usb3_sec_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_boot_rom_ahb_clk = { - .halt_reg = 0x38004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x38004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_boot_rom_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for camss boot - */ -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0xb008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_hf_axi_clk = { - .halt_reg = 0xb030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_sf_axi_clk = { - .halt_reg = 0xb034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_sf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to camss, so no need to poll */ -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0xb044, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb044, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { - .halt_reg = 0xf078, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { - .halt_reg = 0x10078, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_sec_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_ahb_clk = { - .halt_reg = 0x48000, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw }, - .num_parents = 1, - /* required for cpuss */ - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_dvm_bus_clk = { - .halt_reg = 0x48190, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48190, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_dvm_bus_clk", - /* required for cpuss */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_gnoc_clk = { - .halt_reg = 0x48004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x48004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_gnoc_clk", - /* required for cpuss */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_rbcpr_clk = { - .halt_reg = 0x48008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_rbcpr_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ddrss_gpu_axi_clk = { - .halt_reg = 0x71154, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x71154, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ddrss_gpu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for disp boot - */ -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0xb00c, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb00c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_hf_axi_clk = { - .halt_reg = 0xb038, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_sf_axi_clk = { - .halt_reg = 0xb03c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb03c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_sf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to disp, so no need to poll */ -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0xb048, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_axi_clk = { - .halt_reg = 0x6010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_ptp_clk = { - .halt_reg = 0x6034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_ptp_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_emac_ptp_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_rgmii_clk = { - .halt_reg = 0x6018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_rgmii_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_emac_rgmii_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_slv_ahb_clk = { - .halt_reg = 0x6014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x6014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x6014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_slv_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp1_clk = { - .halt_reg = 0x64000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x64000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp2_clk = { - .halt_reg = 0x65000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x65000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp3_clk = { - .halt_reg = 0x66000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x66000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x71004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x71004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x71004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - /* required for gpu */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0_out_even.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_iref_clk = { - .halt_reg = 0x8c010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_iref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_memnoc_gfx_clk = { - .halt_reg = 0x7100c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7100c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_memnoc_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { - .halt_reg = 0x71018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x71018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_snoc_dvm_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_at_clk = { - .halt_reg = 0x4d010, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_at_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_axi_clk = { - .halt_reg = 0x4d008, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_cfg_ahb_clk = { - .halt_reg = 0x4d004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x4d004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x4d004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_cfg_ahb_clk", - /* required for npu */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(18), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(19), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0_out_even.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_trig_clk = { - .halt_reg = 0x4d00c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_trig_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie0_phy_refgen_clk = { - .halt_reg = 0x6f02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie0_phy_refgen_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_phy_refgen_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie1_phy_refgen_clk = { - .halt_reg = 0x6f030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie1_phy_refgen_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_phy_refgen_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_aux_clk = { - .halt_reg = 0x6b020, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { - .halt_reg = 0x6b01c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x6b01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_clkref_clk = { - .halt_reg = 0x8c00c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_mstr_axi_clk = { - .halt_reg = 0x6b018, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_mstr_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ -static struct clk_branch gcc_pcie_0_pipe_clk = { - .halt_reg = 0x6b024, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_axi_clk = { - .halt_reg = 0x6b014, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x6b014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_slv_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { - .halt_reg = 0x6b010, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_slv_q2a_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_aux_clk = { - .halt_reg = 0x8d020, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(29), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_1_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { - .halt_reg = 0x8d01c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8d01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(28), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_clkref_clk = { - .halt_reg = 0x8c02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_mstr_axi_clk = { - .halt_reg = 0x8d018, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_mstr_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ -static struct clk_branch gcc_pcie_1_pipe_clk = { - .halt_reg = 0x8d024, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(30), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_axi_clk = { - .halt_reg = 0x8d014, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8d014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_slv_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { - .halt_reg = 0x8d010, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_slv_q2a_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_phy_aux_clk = { - .halt_reg = 0x6f004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm2_clk = { - .halt_reg = 0x3300c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3300c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pdm2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_ahb_clk = { - .halt_reg = 0x33004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x33004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x33004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_xo4_clk = { - .halt_reg = 0x33008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_xo4_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_prng_ahb_clk = { - .halt_reg = 0x34004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_prng_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { - .halt_reg = 0xb018, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb018, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_camera_nrt_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { - .halt_reg = 0xb01c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb01c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_camera_rt_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_disp_ahb_clk = { - .halt_reg = 0xb020, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb020, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb020, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_disp_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { - .halt_reg = 0xb010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_video_cvp_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { - .halt_reg = 0xb014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_video_vcodec_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { - .halt_reg = 0x4b000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4b000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_cnoc_periph_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_core_clk = { - .halt_reg = 0x4b004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4b004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qspi_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s0_clk = { - .halt_reg = 0x17144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s1_clk = { - .halt_reg = 0x17274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s2_clk = { - .halt_reg = 0x173a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s3_clk = { - .halt_reg = 0x174d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s4_clk = { - .halt_reg = 0x17604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(14), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s5_clk = { - .halt_reg = 0x17734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s6_clk = { - .halt_reg = 0x17864, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s6_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s6_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s7_clk = { - .halt_reg = 0x17994, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s7_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s7_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s0_clk = { - .halt_reg = 0x18144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s1_clk = { - .halt_reg = 0x18274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(23), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s2_clk = { - .halt_reg = 0x183a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(24), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s3_clk = { - .halt_reg = 0x184d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s4_clk = { - .halt_reg = 0x18604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s5_clk = { - .halt_reg = 0x18734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s0_clk = { - .halt_reg = 0x1e144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s1_clk = { - .halt_reg = 0x1e274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s2_clk = { - .halt_reg = 0x1e3a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s3_clk = { - .halt_reg = 0x1e4d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s4_clk = { - .halt_reg = 0x1e604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(8), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s5_clk = { - .halt_reg = 0x1e734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { - .halt_reg = 0x17004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { - .halt_reg = 0x18004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(20), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { - .halt_reg = 0x18008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x18008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { - .halt_reg = 0x1e004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_2_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { - .halt_reg = 0x1e008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x1e008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_2_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_ahb_clk = { - .halt_reg = 0x14008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_apps_clk = { - .halt_reg = 0x14004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_sdcc2_apps_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_ahb_clk = { - .halt_reg = 0x16008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_apps_clk = { - .halt_reg = 0x16004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_apps_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_sdcc4_apps_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x4819c, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw }, - .num_parents = 1, - /* required for cpuss */ - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_inactivity_timers_clk = { - .halt_reg = 0x3600c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3600c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_inactivity_timers_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ref_clk = { - .halt_reg = 0x36008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ref_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_tsif_ref_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ahb_clk = { - .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_axi_clk = { - .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { - .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_clkref_clk = { - .halt_reg = 0x8c004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ice_core_clk = { - .halt_reg = 0x7505c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7505c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7505c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_ice_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { - .halt_reg = 0x7505c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7505c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7505c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_ice_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_phy_aux_clk = { - .halt_reg = 0x75090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75090, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { - .halt_reg = 0x75090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75090, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_phy_aux_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x7501c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_rx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x750ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_rx_symbol_1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x75018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_tx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_unipro_core_clk = { - .halt_reg = 0x75058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_unipro_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { - .halt_reg = 0x75058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75058, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_unipro_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_mem_clkref_clk = { - .halt_reg = 0x8c000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_mem_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ahb_clk = { - .halt_reg = 0x77014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_clk = { - .halt_reg = 0x77010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x77010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77010, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_clk = { - .halt_reg = 0x7705c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7705c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7705c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_ice_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { - .halt_reg = 0x7705c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7705c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7705c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_ice_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_clk = { - .halt_reg = 0x77090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77090, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { - .halt_reg = 0x77090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77090, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_phy_aux_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x7701c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_rx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x770ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_rx_symbol_1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x77018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_tx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_clk = { - .halt_reg = 0x77058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_unipro_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { - .halt_reg = 0x77058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77058, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_unipro_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_master_clk = { - .halt_reg = 0xf010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { - .halt_reg = 0xf018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_sleep_clk = { - .halt_reg = 0xf014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_master_clk = { - .halt_reg = 0x10010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_master_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { - .halt_reg = 0x10018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_mock_utmi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_sleep_clk = { - .halt_reg = 0x10014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_clkref_clk = { - .halt_reg = 0x8c008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_aux_clk = { - .halt_reg = 0xf050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { - .halt_reg = 0xf054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0xf058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_clkref_clk = { - .halt_reg = 0x8c028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_aux_clk = { - .halt_reg = 0x10050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { - .halt_reg = 0x10054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_com_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x10058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for video boot - */ -static struct clk_branch gcc_video_ahb_clk = { - .halt_reg = 0xb004, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi0_clk = { - .halt_reg = 0xb024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axi0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi1_clk = { - .halt_reg = 0xb028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axi1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axic_clk = { - .halt_reg = 0xb02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axic_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to video, so no need to poll */ -static struct clk_branch gcc_video_xo_clk = { - .halt_reg = 0xb040, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -<<<<<<< -static struct gdsc emac_gdsc = { - .gdscr = 0x6004, - .pd = { - .name = "emac_gdsc", -======= -static struct gdsc ufs_card_gdsc = { - .gdscr = 0x75004, - .pd = { - .name = "ufs_card_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_phy_gdsc = { - .gdscr = 0x77004, - .pd = { - .name = "ufs_phy_gdsc", ->>>>>>> - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_prim_gdsc = { - .gdscr = 0xf004, - .pd = { - .name = "usb30_prim_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_sec_gdsc = { - .gdscr = 0x10004, - .pd = { - .name = "usb30_sec_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct clk_regmap *gcc_sm8150_clocks[] = { - [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, - [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, - [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = - &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, - [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, - [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = - &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, - [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, - [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, - [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, - [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, - [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, - [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, - [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, - [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, - [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, - [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, - [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, - [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, - [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, - [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr, - [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr, - [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, - [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr, - [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr, - [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr, - [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, - [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, - [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, - [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, - [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, - [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, - [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, - [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, - [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, - [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, - [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, - [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr, - [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, - [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, - [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, - [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, - [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr, - [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, - [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, - [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, - [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, - [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, - [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, - [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, - [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, - [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, - [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, - [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, - [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, - [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, - [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, - [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, - [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, - [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, - [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, - [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, - [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, - [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, - [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, - [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, - [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, - [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, - [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, - [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, - [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, - [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, - [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, - [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, - [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, - [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, - [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, - [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, - [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, - [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, - [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, - [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, - [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, - [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, - [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, - [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, - [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, - [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, - [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, - [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, - [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, - [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, - [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, - [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, - [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, - [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, - [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, - [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, - [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, - [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, - [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, - [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, - [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, - [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, - [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, - [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, - [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, - [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, - [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, - [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, - [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, - [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, - [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, - [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, - [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, - [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, - [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, - [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, - [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, - [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, - [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, - [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, - [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, - [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, - [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, - [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, - [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, - [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, - [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, - [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, - [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, - [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, - [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, - [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = - &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, - [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, - [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = - &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, - [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, - [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = - &gcc_ufs_card_unipro_core_clk_src.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = - &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, - [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, - [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, - [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, - [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, - [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, - [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = - &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, - [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, - [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, - [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = - &gcc_ufs_phy_unipro_core_clk_src.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = - &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, - [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, - [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = - &gcc_usb30_prim_mock_utmi_clk_src.clkr, - [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, - [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, - [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, - [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, - [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = - &gcc_usb30_sec_mock_utmi_clk_src.clkr, - [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, - [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, - [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, - [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, - [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, - [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, - [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, - [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, - [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, - [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, - [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, - [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr, - [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, - [GPLL0] = &gpll0.clkr, - [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, - [GPLL7] = &gpll7.clkr, - [GPLL9] = &gpll9.clkr, -}; - -static const struct qcom_reset_map gcc_sm8150_resets[] = { - [GCC_EMAC_BCR] = { 0x6000 }, - [GCC_GPU_BCR] = { 0x71000 }, - [GCC_MMSS_BCR] = { 0xb000 }, - [GCC_NPU_BCR] = { 0x4d000 }, - [GCC_PCIE_0_BCR] = { 0x6b000 }, - [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, - [GCC_PCIE_1_BCR] = { 0x8d000 }, - [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, - [GCC_PCIE_PHY_BCR] = { 0x6f000 }, - [GCC_PDM_BCR] = { 0x33000 }, - [GCC_PRNG_BCR] = { 0x34000 }, - [GCC_QSPI_BCR] = { 0x24008 }, - [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, - [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, - [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, - [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, - [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, - [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, - [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, - [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, - [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, - [GCC_SDCC2_BCR] = { 0x14000 }, - [GCC_SDCC4_BCR] = { 0x16000 }, - [GCC_TSIF_BCR] = { 0x36000 }, - [GCC_UFS_CARD_BCR] = { 0x75000 }, - [GCC_UFS_PHY_BCR] = { 0x77000 }, - [GCC_USB30_PRIM_BCR] = { 0xf000 }, - [GCC_USB30_SEC_BCR] = { 0x10000 }, - [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, -}; - -static struct gdsc *gcc_sm8150_gdscs[] = { -<<<<<<< - [EMAC_GDSC] = &emac_gdsc, -======= - [UFS_CARD_GDSC] = &ufs_card_gdsc, - [UFS_PHY_GDSC] = &ufs_phy_gdsc, ->>>>>>> - [USB30_PRIM_GDSC] = &usb30_prim_gdsc, - [USB30_SEC_GDSC] = &usb30_sec_gdsc, -}; - -static const struct regmap_config gcc_sm8150_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x9c040, - .fast_io = true, -}; - -static const struct qcom_cc_desc gcc_sm8150_desc = { - .config = &gcc_sm8150_regmap_config, - .clks = gcc_sm8150_clocks, - .num_clks = ARRAY_SIZE(gcc_sm8150_clocks), - .resets = gcc_sm8150_resets, - .num_resets = ARRAY_SIZE(gcc_sm8150_resets), - .gdscs = gcc_sm8150_gdscs, - .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs), -}; - -static const struct of_device_id gcc_sm8150_match_table[] = { - { .compatible = "qcom,gcc-sm8150" }, - { } -}; -MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table); - -static int gcc_sm8150_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - - regmap = qcom_cc_map(pdev, &gcc_sm8150_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ - regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); - regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - - return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap); -} - -static struct platform_driver gcc_sm8150_driver = { - .probe = gcc_sm8150_probe, - .driver = { - .name = "gcc-sm8150", - .of_match_table = gcc_sm8150_match_table, - }, -}; - -static int __init gcc_sm8150_init(void) -{ - return platform_driver_register(&gcc_sm8150_driver); -} -subsys_initcall(gcc_sm8150_init); - -static void __exit gcc_sm8150_exit(void) -{ - platform_driver_unregister(&gcc_sm8150_driver); -} -module_exit(gcc_sm8150_exit); - -MODULE_DESCRIPTION("QTI GCC SM8150 Driver"); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/281bed77ea93a7d45dea5729757bd3dd6bd0dd2d/preimage b/rr-cache/281bed77ea93a7d45dea5729757bd3dd6bd0dd2d/preimage deleted file mode 100644 index 0f48c02..0000000 --- a/rr-cache/281bed77ea93a7d45dea5729757bd3dd6bd0dd2d/preimage +++ /dev/null @@ -1,2381 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 2>; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8350", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_aop_mem: memory@80700000 { - no-map; - reg = <0x0 0x80700000 0x0 0x160000>; - }; - - cmd_db: memory@80860000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x80860000 0x0 0x20000>; - no-map; - }; - - reserved_xbl_uefi_log: memory@80880000 { - reg = <0x0 0x80880000 0x0 0x14000>; - no-map; - }; - - smem_mem: memory@80900000 { - reg = <0x0 0x80900000 0x0 0x200000>; - no-map; - }; - - cpucp_fw_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x100000>; - no-map; - }; - - cdsp_secure_heap: memory@80c00000 { - reg = <0x0 0x80c00000 0x0 0x4600000>; - no-map; - }; - - pil_camera_mem: mmeory@85200000 { - reg = <0x0 0x85200000 0x0 0x500000>; - no-map; - }; - - pil_video_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x500000>; - no-map; - }; - - pil_cvp_mem: memory@85c00000 { - reg = <0x0 0x85c00000 0x0 0x500000>; - no-map; - }; - - pil_adsp_mem: memory@86100000 { - reg = <0x0 0x86100000 0x0 0x2100000>; - no-map; - }; - - pil_slpi_mem: memory@88200000 { - reg = <0x0 0x88200000 0x0 0x1500000>; - no-map; - }; - - pil_cdsp_mem: memory@89700000 { - reg = <0x0 0x89700000 0x0 0x1e00000>; - no-map; - }; - - pil_ipa_fw_mem: memory@8b500000 { - reg = <0x0 0x8b500000 0x0 0x10000>; - no-map; - }; - - pil_ipa_gsi_mem: memory@8b510000 { - reg = <0x0 0x8b510000 0x0 0xa000>; - no-map; - }; - - pil_gpu_mem: memory@8b51a000 { - reg = <0x0 0x8b51a000 0x0 0x2000>; - no-map; - }; - - pil_spss_mem: memory@8b600000 { - reg = <0x0 0x8b600000 0x0 0x100000>; - no-map; - }; - - pil_modem_mem: memory@8b800000 { - reg = <0x0 0x8b800000 0x0 0x10000000>; - no-map; - }; - - rmtfs_mem: memory@9b800000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x9b800000 0x0 0x280000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - hyp_reserved_mem: memory@d0000000 { - reg = <0x0 0xd0000000 0x0 0x800000>; - no-map; - }; - - pil_trustedvm_mem: memory@d0800000 { - reg = <0x0 0xd0800000 0x0 0x76f7000>; - no-map; - }; - - qrtr_shbuf: memory@d7ef7000 { - reg = <0x0 0xd7ef7000 0x0 0x9000>; - no-map; - }; - - chan0_shbuf: memory@d7f00000 { - reg = <0x0 0xd7f00000 0x0 0x80000>; - no-map; - }; - - chan1_shbuf: memory@d7f80000 { - reg = <0x0 0xd7f80000 0x0 0x80000>; - no-map; - }; - - removed_mem: memory@d8800000 { - reg = <0x0 0xd8800000 0x0 0x6800000>; - no-map; - }; - }; - - smem: qcom,smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - smp2p_cdsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_cdsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - smp2p_modem_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_modem_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8350"; - reg = <0x0 0x00100000 0x0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "sleep_clk", - "pcie_0_pipe_clk", - "pcie_1_pipe_clk", - "ufs_card_rx_symbol_0_clk", - "ufs_card_rx_symbol_1_clk", - "ufs_card_tx_symbol_0_clk", - "ufs_phy_rx_symbol_0_clk", - "ufs_phy_rx_symbol_1_clk", - "ufs_phy_tx_symbol_0_clk", - "usb3_phy_wrapper_gcc_usb30_pipe_clk", - "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, - <0>, - <0>, - <0>, - <0>, - <0>, - <&ufs_phy_rx_symbol_0_clk>, - <&ufs_phy_rx_symbol_1_clk>, - <&ufs_phy_tx_symbol_0_clk>, - <0>, - <0>; - }; - - ipcc: mailbox@408000 { - compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; - reg = <0 0x00408000 0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - }; - - qupv3_id_0: geniqup@9c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x009c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - uart2: serial@98c000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x0098c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart3_default_state>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default_state>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8350-config-noc"; - reg = <0 0x01500000 0 0xa580>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@1580000 { - compatible = "qcom,sm8350-mc-virt"; - reg = <0 0x01580000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1680000 { - compatible = "qcom,sm8350-system-noc"; - reg = <0 0x01680000 0 0x1c200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8350-aggre1-noc"; - reg = <0 0x016e0000 0 0x1f180>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8350-aggre2-noc"; - reg = <0 0x01700000 0 0x33000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8350-mmss-noc"; - reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - lpass_ag_noc: interconnect@3c40000 { - compatible = "qcom,sm8350-lpass-ag-noc"; - reg = <0 0x03c40000 0 0xf080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - compute_noc: interconnect@a0c0000{ - compatible = "qcom,sm8350-compute-noc"; - reg = <0 0x0a0c0000 0 0xa180>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - ipa: ipa@1e40000 { - compatible = "qcom,sm8350-ipa"; - - iommus = <&apps_smmu 0x5c0 0x0>, - <&apps_smmu 0x5c2 0x0>; - reg = <0 0x1e40000 0 0x8000>, - <0 0x1e50000 0 0x4b20>, - <0 0x1e04000 0 0x23000>; - reg-names = "ipa-reg", - "ipa-shared", - "gsi"; - - interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, - <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ipa", - "gsi", - "ipa-clock-query", - "ipa-setup-ready"; - - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - - interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; - interconnect-names = "memory", - "config"; - - qcom,smem-states = <&ipa_smp2p_out 0>, - <&ipa_smp2p_out 1>; - qcom,smem-state-names = "ipa-clock-enabled-valid", - "ipa-clock-enabled"; - - status = "disabled"; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x01f40000 0x0 0x40000>; - #hwlock-cells = <1>; - }; - - mpss: remoteproc@4080000 { - compatible = "qcom,sm8350-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, - <&rpmhpd 0>, - <&rpmhpd 12>; - power-domain-names = "load_state", "cx", "mss"; - - interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; - - memory-region = <&pil_modem_mem>; - - qcom,smem-states = <&smp2p_modem_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - }; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8350-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; - qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, - <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, - <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, - <156 716 12>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x8>; /* SROT */ - #qcom,sensors = <15>; - interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x8>; /* SROT */ - #qcom,sensors = <14>; - interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8350-aoss-qmp"; - reg = <0 0x0c300000 0 0x100000>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - #power-domain-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0xc440000 0x0 0x1100>, - <0x0 0xc600000 0x0 0x2000000>, - <0x0 0xe600000 0x0 0x100000>, - <0x0 0xe700000 0x0 0xa0000>, - <0x0 0xc40a000 0x0 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8350-tlmm"; - reg = <0 0x0f100000 0 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 204>; - wakeup-parent = <&pdc>; - - qup_uart3_default_state: qup-uart3-default-state { - rx { - pins = "gpio18"; - function = "qup3"; - }; - tx { - pins = "gpio19"; - function = "qup3"; - }; - }; - - qup_i2c13_default_state: qup-i2c13-default-state { - mux { - pins = "gpio0", "gpio1"; - function = "qup13"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - rng: rng@10d3000 { - compatible = "qcom,prng-ee"; - reg = <0 0x010d3000 0 0x1000>; - clocks = <&rpmhcc RPMH_HWKM_CLK>; - clock-names = "core"; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; - - timer@17c20000 { - compatible = "arm,armv7-timer-mem"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17c21000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17c23000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17c25000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17c27000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17c29000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x17c2b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x17c2d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , , - , ; - - rpmhcc: clock-controller { - compatible = "qcom,sm8350-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8350-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - - cpufreq_hw: cpufreq@18591000 { - compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0 0x18591000 0 0x1000>, - <0 0x18592000 0 0x1000>, - <0 0x18593000 0 0x1000>; - reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8350-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0xe0 0x0>; - - clock-names = - "ref_clk", - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8350-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0xe10>; - #address-cells = <2>; - #size-cells = <2>; - #clock-cells = <1>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - #clock-cells = <0>; - }; - }; - - slpi: remoteproc@5c00000 { - compatible = "qcom,sm8350-slpi-pas"; - reg = <0 0x05c00000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, - <&rpmhpd 4>, - <&rpmhpd 5>; - power-domain-names = "load_state", "lcx", "lmx"; - - memory-region = <&pil_slpi_mem>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "slpi"; - qcom,remote-pid = <3>; - -<<<<<<< -======= - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0541 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0542 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0543 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; ->>>>>>> - }; - }; - - cdsp: remoteproc@98900000 { - compatible = "qcom,sm8350-cdsp-pas"; - reg = <0 0x098900000 0 0x1400000>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, - <&rpmhpd 0>, - <&rpmhpd 10>; - power-domain-names = "load_state", "cx", "mxc"; - - interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; - - memory-region = <&pil_cdsp_mem>; - - qcom,smem-states = <&smp2p_cdsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "cdsp"; - qcom,remote-pid = <5>; -<<<<<<< -======= - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x2161 0x0400>, - <&apps_smmu 0x1181 0x0420>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2162 0x0400>, - <&apps_smmu 0x1182 0x0420>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x2163 0x0400>, - <&apps_smmu 0x1183 0x0420>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x2164 0x0400>, - <&apps_smmu 0x1184 0x0420>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x2165 0x0400>, - <&apps_smmu 0x1185 0x0420>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x2166 0x0400>, - <&apps_smmu 0x1186 0x0420>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x2167 0x0400>, - <&apps_smmu 0x1187 0x0420>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x2168 0x0400>, - <&apps_smmu 0x1188 0x0420>; - }; - - /* note: secure cb9 in downstream */ - }; ->>>>>>> - }; - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8350-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_2_hsphy: phy@88e4000 { - compatible = "qcom,sm8250-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e4000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - }; - - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8350-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - reg-names = "reg-base", "dp_com"; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - usb_2_qmpphy: phy-wrapper@88eb000 { - compatible = "qcom,sm8350-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x200>; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_EN>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: phy@88ebe00 { - reg = <0 0x088ebe00 0 0x200>, - <0 0x088ec000 0 0x200>, - <0 0x088eb200 0 0x1100>; - #phy-cells = <0>; - #clock-cells = <1>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - dc_noc: interconnect@90c0000 { - compatible = "qcom,sm8350-dc-noc"; - reg = <0 0x090c0000 0 0x4200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9100000 { - compatible = "qcom,sm8350-gem-noc"; - reg = <0 0x09100000 0 0xb4000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, - <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_EN>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>, - <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x20 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - adsp: remoteproc@17300000 { - compatible = "qcom,sm8350-adsp-pas"; - reg = <0 0x17300000 0 0x100>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, - <&rpmhpd 4>, - <&rpmhpd 5>; - power-domain-names = "load_state", "lcx", "lmx"; - - memory-region = <&pil_adsp_mem>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <2>; -<<<<<<< -======= - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1803 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1804 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1805 0x0>; - }; - }; ->>>>>>> - }; - }; - }; - - thermal_zones: thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 14>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - }; - - nspss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - nspss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - }; - - nspss2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - nspss2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - }; - - nspss3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - nspss3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem1-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 8>; - - trips { - modem1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem2-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 9>; - - trips { - modem2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem3-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 10>; - - trips { - modem3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem4-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 11>; - - trips { - modem4_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 12>; - - trips { - camera1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cam-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 13>; - - trips { - camera2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; diff --git a/rr-cache/281bed77ea93a7d45dea5729757bd3dd6bd0dd2d/preimage.1 b/rr-cache/281bed77ea93a7d45dea5729757bd3dd6bd0dd2d/preimage.1 deleted file mode 100644 index 0f48c02..0000000 --- a/rr-cache/281bed77ea93a7d45dea5729757bd3dd6bd0dd2d/preimage.1 +++ /dev/null @@ -1,2381 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo685"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 2>; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8350", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_aop_mem: memory@80700000 { - no-map; - reg = <0x0 0x80700000 0x0 0x160000>; - }; - - cmd_db: memory@80860000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x80860000 0x0 0x20000>; - no-map; - }; - - reserved_xbl_uefi_log: memory@80880000 { - reg = <0x0 0x80880000 0x0 0x14000>; - no-map; - }; - - smem_mem: memory@80900000 { - reg = <0x0 0x80900000 0x0 0x200000>; - no-map; - }; - - cpucp_fw_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x100000>; - no-map; - }; - - cdsp_secure_heap: memory@80c00000 { - reg = <0x0 0x80c00000 0x0 0x4600000>; - no-map; - }; - - pil_camera_mem: mmeory@85200000 { - reg = <0x0 0x85200000 0x0 0x500000>; - no-map; - }; - - pil_video_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x500000>; - no-map; - }; - - pil_cvp_mem: memory@85c00000 { - reg = <0x0 0x85c00000 0x0 0x500000>; - no-map; - }; - - pil_adsp_mem: memory@86100000 { - reg = <0x0 0x86100000 0x0 0x2100000>; - no-map; - }; - - pil_slpi_mem: memory@88200000 { - reg = <0x0 0x88200000 0x0 0x1500000>; - no-map; - }; - - pil_cdsp_mem: memory@89700000 { - reg = <0x0 0x89700000 0x0 0x1e00000>; - no-map; - }; - - pil_ipa_fw_mem: memory@8b500000 { - reg = <0x0 0x8b500000 0x0 0x10000>; - no-map; - }; - - pil_ipa_gsi_mem: memory@8b510000 { - reg = <0x0 0x8b510000 0x0 0xa000>; - no-map; - }; - - pil_gpu_mem: memory@8b51a000 { - reg = <0x0 0x8b51a000 0x0 0x2000>; - no-map; - }; - - pil_spss_mem: memory@8b600000 { - reg = <0x0 0x8b600000 0x0 0x100000>; - no-map; - }; - - pil_modem_mem: memory@8b800000 { - reg = <0x0 0x8b800000 0x0 0x10000000>; - no-map; - }; - - rmtfs_mem: memory@9b800000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x9b800000 0x0 0x280000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - hyp_reserved_mem: memory@d0000000 { - reg = <0x0 0xd0000000 0x0 0x800000>; - no-map; - }; - - pil_trustedvm_mem: memory@d0800000 { - reg = <0x0 0xd0800000 0x0 0x76f7000>; - no-map; - }; - - qrtr_shbuf: memory@d7ef7000 { - reg = <0x0 0xd7ef7000 0x0 0x9000>; - no-map; - }; - - chan0_shbuf: memory@d7f00000 { - reg = <0x0 0xd7f00000 0x0 0x80000>; - no-map; - }; - - chan1_shbuf: memory@d7f80000 { - reg = <0x0 0xd7f80000 0x0 0x80000>; - no-map; - }; - - removed_mem: memory@d8800000 { - reg = <0x0 0xd8800000 0x0 0x6800000>; - no-map; - }; - }; - - smem: qcom,smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - smp2p_cdsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_cdsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - smp2p_modem_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_modem_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8350"; - reg = <0x0 0x00100000 0x0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "sleep_clk", - "pcie_0_pipe_clk", - "pcie_1_pipe_clk", - "ufs_card_rx_symbol_0_clk", - "ufs_card_rx_symbol_1_clk", - "ufs_card_tx_symbol_0_clk", - "ufs_phy_rx_symbol_0_clk", - "ufs_phy_rx_symbol_1_clk", - "ufs_phy_tx_symbol_0_clk", - "usb3_phy_wrapper_gcc_usb30_pipe_clk", - "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, - <0>, - <0>, - <0>, - <0>, - <0>, - <&ufs_phy_rx_symbol_0_clk>, - <&ufs_phy_rx_symbol_1_clk>, - <&ufs_phy_tx_symbol_0_clk>, - <0>, - <0>; - }; - - ipcc: mailbox@408000 { - compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; - reg = <0 0x00408000 0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - }; - - qupv3_id_0: geniqup@9c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x009c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - uart2: serial@98c000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x0098c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart3_default_state>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default_state>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8350-config-noc"; - reg = <0 0x01500000 0 0xa580>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@1580000 { - compatible = "qcom,sm8350-mc-virt"; - reg = <0 0x01580000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1680000 { - compatible = "qcom,sm8350-system-noc"; - reg = <0 0x01680000 0 0x1c200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8350-aggre1-noc"; - reg = <0 0x016e0000 0 0x1f180>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8350-aggre2-noc"; - reg = <0 0x01700000 0 0x33000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8350-mmss-noc"; - reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - lpass_ag_noc: interconnect@3c40000 { - compatible = "qcom,sm8350-lpass-ag-noc"; - reg = <0 0x03c40000 0 0xf080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - compute_noc: interconnect@a0c0000{ - compatible = "qcom,sm8350-compute-noc"; - reg = <0 0x0a0c0000 0 0xa180>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - ipa: ipa@1e40000 { - compatible = "qcom,sm8350-ipa"; - - iommus = <&apps_smmu 0x5c0 0x0>, - <&apps_smmu 0x5c2 0x0>; - reg = <0 0x1e40000 0 0x8000>, - <0 0x1e50000 0 0x4b20>, - <0 0x1e04000 0 0x23000>; - reg-names = "ipa-reg", - "ipa-shared", - "gsi"; - - interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, - <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ipa", - "gsi", - "ipa-clock-query", - "ipa-setup-ready"; - - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - - interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; - interconnect-names = "memory", - "config"; - - qcom,smem-states = <&ipa_smp2p_out 0>, - <&ipa_smp2p_out 1>; - qcom,smem-state-names = "ipa-clock-enabled-valid", - "ipa-clock-enabled"; - - status = "disabled"; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x01f40000 0x0 0x40000>; - #hwlock-cells = <1>; - }; - - mpss: remoteproc@4080000 { - compatible = "qcom,sm8350-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, - <&rpmhpd 0>, - <&rpmhpd 12>; - power-domain-names = "load_state", "cx", "mss"; - - interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; - - memory-region = <&pil_modem_mem>; - - qcom,smem-states = <&smp2p_modem_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - }; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8350-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; - qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, - <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, - <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, - <156 716 12>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x8>; /* SROT */ - #qcom,sensors = <15>; - interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x8>; /* SROT */ - #qcom,sensors = <14>; - interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8350-aoss-qmp"; - reg = <0 0x0c300000 0 0x100000>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - #power-domain-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0xc440000 0x0 0x1100>, - <0x0 0xc600000 0x0 0x2000000>, - <0x0 0xe600000 0x0 0x100000>, - <0x0 0xe700000 0x0 0xa0000>, - <0x0 0xc40a000 0x0 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8350-tlmm"; - reg = <0 0x0f100000 0 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 204>; - wakeup-parent = <&pdc>; - - qup_uart3_default_state: qup-uart3-default-state { - rx { - pins = "gpio18"; - function = "qup3"; - }; - tx { - pins = "gpio19"; - function = "qup3"; - }; - }; - - qup_i2c13_default_state: qup-i2c13-default-state { - mux { - pins = "gpio0", "gpio1"; - function = "qup13"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - rng: rng@10d3000 { - compatible = "qcom,prng-ee"; - reg = <0 0x010d3000 0 0x1000>; - clocks = <&rpmhcc RPMH_HWKM_CLK>; - clock-names = "core"; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; - - timer@17c20000 { - compatible = "arm,armv7-timer-mem"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17c21000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17c23000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17c25000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17c27000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17c29000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x17c2b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x17c2d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , , - , ; - - rpmhcc: clock-controller { - compatible = "qcom,sm8350-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8350-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - - cpufreq_hw: cpufreq@18591000 { - compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0 0x18591000 0 0x1000>, - <0 0x18592000 0 0x1000>, - <0 0x18593000 0 0x1000>; - reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8350-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0xe0 0x0>; - - clock-names = - "ref_clk", - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8350-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0xe10>; - #address-cells = <2>; - #size-cells = <2>; - #clock-cells = <1>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - #clock-cells = <0>; - }; - }; - - slpi: remoteproc@5c00000 { - compatible = "qcom,sm8350-slpi-pas"; - reg = <0 0x05c00000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, - <&rpmhpd 4>, - <&rpmhpd 5>; - power-domain-names = "load_state", "lcx", "lmx"; - - memory-region = <&pil_slpi_mem>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "slpi"; - qcom,remote-pid = <3>; - -<<<<<<< -======= - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0541 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0542 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0543 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; ->>>>>>> - }; - }; - - cdsp: remoteproc@98900000 { - compatible = "qcom,sm8350-cdsp-pas"; - reg = <0 0x098900000 0 0x1400000>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, - <&rpmhpd 0>, - <&rpmhpd 10>; - power-domain-names = "load_state", "cx", "mxc"; - - interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; - - memory-region = <&pil_cdsp_mem>; - - qcom,smem-states = <&smp2p_cdsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "cdsp"; - qcom,remote-pid = <5>; -<<<<<<< -======= - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x2161 0x0400>, - <&apps_smmu 0x1181 0x0420>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2162 0x0400>, - <&apps_smmu 0x1182 0x0420>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x2163 0x0400>, - <&apps_smmu 0x1183 0x0420>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x2164 0x0400>, - <&apps_smmu 0x1184 0x0420>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x2165 0x0400>, - <&apps_smmu 0x1185 0x0420>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x2166 0x0400>, - <&apps_smmu 0x1186 0x0420>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x2167 0x0400>, - <&apps_smmu 0x1187 0x0420>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x2168 0x0400>, - <&apps_smmu 0x1188 0x0420>; - }; - - /* note: secure cb9 in downstream */ - }; ->>>>>>> - }; - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8350-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_2_hsphy: phy@88e4000 { - compatible = "qcom,sm8250-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e4000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - }; - - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8350-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - reg-names = "reg-base", "dp_com"; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - usb_2_qmpphy: phy-wrapper@88eb000 { - compatible = "qcom,sm8350-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x200>; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_EN>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: phy@88ebe00 { - reg = <0 0x088ebe00 0 0x200>, - <0 0x088ec000 0 0x200>, - <0 0x088eb200 0 0x1100>; - #phy-cells = <0>; - #clock-cells = <1>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - dc_noc: interconnect@90c0000 { - compatible = "qcom,sm8350-dc-noc"; - reg = <0 0x090c0000 0 0x4200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9100000 { - compatible = "qcom,sm8350-gem-noc"; - reg = <0 0x09100000 0 0xb4000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, - <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_EN>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>, - <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x20 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - adsp: remoteproc@17300000 { - compatible = "qcom,sm8350-adsp-pas"; - reg = <0 0x17300000 0 0x100>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, - <&rpmhpd 4>, - <&rpmhpd 5>; - power-domain-names = "load_state", "lcx", "lmx"; - - memory-region = <&pil_adsp_mem>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <2>; -<<<<<<< -======= - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1803 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1804 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1805 0x0>; - }; - }; ->>>>>>> - }; - }; - }; - - thermal_zones: thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 14>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - }; - - nspss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - nspss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - }; - - nspss2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - nspss2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - }; - - nspss3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - nspss3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem1-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 8>; - - trips { - modem1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem2-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 9>; - - trips { - modem2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem3-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 10>; - - trips { - modem3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem4-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 11>; - - trips { - modem4_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 12>; - - trips { - camera1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cam-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 13>; - - trips { - camera2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; diff --git a/rr-cache/2afbefe9e83c97119ee25d550ef66161043a955a/preimage b/rr-cache/2afbefe9e83c97119ee25d550ef66161043a955a/preimage deleted file mode 100644 index 3b8f390..0000000 --- a/rr-cache/2afbefe9e83c97119ee25d550ef66161043a955a/preimage +++ /dev/null @@ -1,391 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/******************************************************************************* - Copyright (C) 2007-2009 STMicroelectronics Ltd - - - Author: Giuseppe Cavallaro -*******************************************************************************/ - -#ifndef __STMMAC_H__ -#define __STMMAC_H__ - -#define STMMAC_RESOURCE_NAME "stmmaceth" -#define DRV_MODULE_VERSION "Jan_2016" - -#include -#include -#include -#include -#include -#include -#include "common.h" -#include -#include -#include -#include - -struct stmmac_resources { - void __iomem *addr; - u8 mac[ETH_ALEN]; - int wol_irq; - int lpi_irq; - int irq; - int sfty_ce_irq; - int sfty_ue_irq; - int rx_irq[MTL_MAX_RX_QUEUES]; - int tx_irq[MTL_MAX_TX_QUEUES]; -}; - -enum stmmac_txbuf_type { - STMMAC_TXBUF_T_SKB, - STMMAC_TXBUF_T_XDP_TX, - STMMAC_TXBUF_T_XDP_NDO, - STMMAC_TXBUF_T_XSK_TX, -}; - -struct stmmac_tx_info { - dma_addr_t buf; - bool map_as_page; - unsigned len; - bool last_segment; - bool is_jumbo; - enum stmmac_txbuf_type buf_type; -}; - -#define STMMAC_TBS_AVAIL BIT(0) -#define STMMAC_TBS_EN BIT(1) - -/* Frequently used values are kept adjacent for cache effect */ -struct stmmac_tx_queue { - u32 tx_count_frames; - int tbs; - struct hrtimer txtimer; - u32 queue_index; - struct stmmac_priv *priv_data; - struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; - struct dma_edesc *dma_entx; - struct dma_desc *dma_tx; - union { - struct sk_buff **tx_skbuff; - struct xdp_frame **xdpf; - }; - struct stmmac_tx_info *tx_skbuff_dma; - struct xsk_buff_pool *xsk_pool; - u32 xsk_frames_done; - unsigned int cur_tx; - unsigned int dirty_tx; - dma_addr_t dma_tx_phy; - dma_addr_t tx_tail_addr; - u32 mss; -}; - -struct stmmac_rx_buffer { -<<<<<<< - struct page *page; - dma_addr_t addr; - __u32 page_offset; -======= - union { - struct { - struct page *page; - dma_addr_t addr; - __u32 page_offset; - }; - struct xdp_buff *xdp; - }; ->>>>>>> - struct page *sec_page; - dma_addr_t sec_addr; -}; - -struct stmmac_rx_queue { - u32 rx_count_frames; - u32 queue_index; - struct xdp_rxq_info xdp_rxq; - struct xsk_buff_pool *xsk_pool; - struct page_pool *page_pool; - struct stmmac_rx_buffer *buf_pool; - struct stmmac_priv *priv_data; - struct dma_extended_desc *dma_erx; - struct dma_desc *dma_rx ____cacheline_aligned_in_smp; - unsigned int cur_rx; - unsigned int dirty_rx; - unsigned int buf_alloc_num; - u32 rx_zeroc_thresh; - dma_addr_t dma_rx_phy; - u32 rx_tail_addr; - unsigned int state_saved; - struct { - struct sk_buff *skb; - unsigned int len; - unsigned int error; - } state; -}; - -struct stmmac_channel { - struct napi_struct rx_napi ____cacheline_aligned_in_smp; - struct napi_struct tx_napi ____cacheline_aligned_in_smp; - struct napi_struct rxtx_napi ____cacheline_aligned_in_smp; - struct stmmac_priv *priv_data; - spinlock_t lock; - u32 index; -}; - -struct stmmac_tc_entry { - bool in_use; - bool in_hw; - bool is_last; - bool is_frag; - void *frag_ptr; - unsigned int table_pos; - u32 handle; - u32 prio; - struct { - u32 match_data; - u32 match_en; - u8 af:1; - u8 rf:1; - u8 im:1; - u8 nc:1; - u8 res1:4; - u8 frame_offset; - u8 ok_index; - u8 dma_ch_no; - u32 res2; - } __packed val; -}; - -#define STMMAC_PPS_MAX 4 -struct stmmac_pps_cfg { - bool available; - struct timespec64 start; - struct timespec64 period; -}; - -struct stmmac_rss { - int enable; - u8 key[STMMAC_RSS_HASH_KEY_SIZE]; - u32 table[STMMAC_RSS_MAX_TABLE_SIZE]; -}; - -#define STMMAC_FLOW_ACTION_DROP BIT(0) -struct stmmac_flow_entry { - unsigned long cookie; - unsigned long action; - u8 ip_proto; - int in_use; - int idx; - int is_l4; -}; - -struct stmmac_priv { - /* Frequently used values are kept adjacent for cache effect */ - u32 tx_coal_frames[MTL_MAX_TX_QUEUES]; - u32 tx_coal_timer[MTL_MAX_TX_QUEUES]; - u32 rx_coal_frames[MTL_MAX_TX_QUEUES]; - - int tx_coalesce; - int hwts_tx_en; - bool tx_path_in_lpi_mode; - bool tso; - int sph; - int sph_cap; - u32 sarc_type; - - unsigned int dma_buf_sz; - unsigned int rx_copybreak; - u32 rx_riwt[MTL_MAX_TX_QUEUES]; - int hwts_rx_en; - - void __iomem *ioaddr; - struct net_device *dev; - struct device *device; - struct mac_device_info *hw; - int (*hwif_quirks)(struct stmmac_priv *priv); - struct mutex lock; - - /* RX Queue */ - struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; - unsigned int dma_rx_size; - - /* TX Queue */ - struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; - unsigned int dma_tx_size; - - /* Generic channel for NAPI */ - struct stmmac_channel channel[STMMAC_CH_MAX]; - - int speed; - unsigned int flow_ctrl; - unsigned int pause; - struct mii_bus *mii; - int mii_irq[PHY_MAX_ADDR]; - - struct phylink_config phylink_config; - struct phylink *phylink; - - struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; - struct stmmac_safety_stats sstats; - struct plat_stmmacenet_data *plat; - struct dma_features dma_cap; - struct stmmac_counters mmc; - int hw_cap_support; - int synopsys_id; - u32 msg_enable; - int wolopts; - int wol_irq; - int clk_csr; - struct timer_list eee_ctrl_timer; - int lpi_irq; - int eee_enabled; - int eee_active; - int tx_lpi_timer; - int tx_lpi_enabled; - int eee_tw_timer; - bool eee_sw_timer_en; - unsigned int mode; - unsigned int chain_mode; - int extend_desc; - struct hwtstamp_config tstamp_config; - struct ptp_clock *ptp_clock; - struct ptp_clock_info ptp_clock_ops; - unsigned int default_addend; - u32 sub_second_inc; - u32 systime_flags; - u32 adv_ts; - int use_riwt; - int irq_wake; - spinlock_t ptp_lock; - /* Protects auxiliary snapshot registers from concurrent access. */ - struct mutex aux_ts_lock; - - void __iomem *mmcaddr; - void __iomem *ptpaddr; - unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; - int sfty_ce_irq; - int sfty_ue_irq; - int rx_irq[MTL_MAX_RX_QUEUES]; - int tx_irq[MTL_MAX_TX_QUEUES]; - /*irq name */ - char int_name_mac[IFNAMSIZ + 9]; - char int_name_wol[IFNAMSIZ + 9]; - char int_name_lpi[IFNAMSIZ + 9]; - char int_name_sfty_ce[IFNAMSIZ + 10]; - char int_name_sfty_ue[IFNAMSIZ + 10]; - char int_name_rx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 14]; - char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18]; - -#ifdef CONFIG_DEBUG_FS - struct dentry *dbgfs_dir; -#endif - - unsigned long state; - struct workqueue_struct *wq; - struct work_struct service_task; - - /* Workqueue for handling FPE hand-shaking */ - unsigned long fpe_task_state; - struct workqueue_struct *fpe_wq; - struct work_struct fpe_task; - char wq_name[IFNAMSIZ + 4]; - - /* TC Handling */ - unsigned int tc_entries_max; - unsigned int tc_off_max; - struct stmmac_tc_entry *tc_entries; - unsigned int flow_entries_max; - struct stmmac_flow_entry *flow_entries; - - /* Pulse Per Second output */ - struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; - - /* Receive Side Scaling */ - struct stmmac_rss rss; - - /* XDP BPF Program */ -<<<<<<< -======= - unsigned long *af_xdp_zc_qps; ->>>>>>> - struct bpf_prog *xdp_prog; -}; - -enum stmmac_state { - STMMAC_DOWN, - STMMAC_RESET_REQUESTED, - STMMAC_RESETING, - STMMAC_SERVICE_SCHED, -}; - -int stmmac_mdio_unregister(struct net_device *ndev); -int stmmac_mdio_register(struct net_device *ndev); -int stmmac_mdio_reset(struct mii_bus *mii); -int stmmac_xpcs_setup(struct mii_bus *mii); -void stmmac_set_ethtool_ops(struct net_device *netdev); - -int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags); -void stmmac_ptp_register(struct stmmac_priv *priv); -void stmmac_ptp_unregister(struct stmmac_priv *priv); -int stmmac_open(struct net_device *dev); -int stmmac_release(struct net_device *dev); -int stmmac_resume(struct device *dev); -int stmmac_suspend(struct device *dev); -int stmmac_dvr_remove(struct device *dev); -int stmmac_dvr_probe(struct device *device, - struct plat_stmmacenet_data *plat_dat, - struct stmmac_resources *res); -void stmmac_disable_eee_mode(struct stmmac_priv *priv); -bool stmmac_eee_init(struct stmmac_priv *priv); -int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt); -int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size); -int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled); -void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable); - -static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv) -{ - return !!priv->xdp_prog; -} - -static inline unsigned int stmmac_rx_offset(struct stmmac_priv *priv) -{ - if (stmmac_xdp_is_enabled(priv)) - return XDP_PACKET_HEADROOM; - - return 0; -} - -<<<<<<< -======= -void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue); -void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue); -void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue); -void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue); -int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags); -struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time, - ktime_t current_time, - u64 cycle_time); - ->>>>>>> -#if IS_ENABLED(CONFIG_STMMAC_SELFTESTS) -void stmmac_selftest_run(struct net_device *dev, - struct ethtool_test *etest, u64 *buf); -void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data); -int stmmac_selftest_get_count(struct stmmac_priv *priv); -#else -static inline void stmmac_selftest_run(struct net_device *dev, - struct ethtool_test *etest, u64 *buf) -{ - /* Not enabled */ -} -static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv, - u8 *data) -{ - /* Not enabled */ -} -static inline int stmmac_selftest_get_count(struct stmmac_priv *priv) -{ - return -EOPNOTSUPP; -} -#endif /* CONFIG_STMMAC_SELFTESTS */ - -#endif /* __STMMAC_H__ */ diff --git a/rr-cache/2d6f4bb97d71426e793118a4ed9ac0bb38e8a746/preimage b/rr-cache/2d6f4bb97d71426e793118a4ed9ac0bb38e8a746/preimage deleted file mode 100644 index f1523f8..0000000 --- a/rr-cache/2d6f4bb97d71426e793118a4ed9ac0bb38e8a746/preimage +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2021, Intel Corporation. */ - -<<<<<<< -#include "stmmac.h" -#include "stmmac_xdp.h" - -======= -#include - -#include "stmmac.h" -#include "stmmac_xdp.h" - -static int stmmac_xdp_enable_pool(struct stmmac_priv *priv, - struct xsk_buff_pool *pool, u16 queue) -{ - struct stmmac_channel *ch = &priv->channel[queue]; - bool need_update; - u32 frame_size; - int err; - - if (queue >= priv->plat->rx_queues_to_use || - queue >= priv->plat->tx_queues_to_use) - return -EINVAL; - - frame_size = xsk_pool_get_rx_frame_size(pool); - /* XDP ZC does not span multiple frame, make sure XSK pool buffer - * size can at least store Q-in-Q frame. - */ - if (frame_size < ETH_FRAME_LEN + VLAN_HLEN * 2) - return -EOPNOTSUPP; - - err = xsk_pool_dma_map(pool, priv->device, STMMAC_RX_DMA_ATTR); - if (err) { - netdev_err(priv->dev, "Failed to map xsk pool\n"); - return err; - } - - need_update = netif_running(priv->dev) && stmmac_xdp_is_enabled(priv); - - if (need_update) { - napi_disable(&ch->rx_napi); - napi_disable(&ch->tx_napi); - stmmac_disable_rx_queue(priv, queue); - stmmac_disable_tx_queue(priv, queue); - } - - set_bit(queue, priv->af_xdp_zc_qps); - - if (need_update) { - stmmac_enable_rx_queue(priv, queue); - stmmac_enable_tx_queue(priv, queue); - napi_enable(&ch->rxtx_napi); - - err = stmmac_xsk_wakeup(priv->dev, queue, XDP_WAKEUP_RX); - if (err) - return err; - } - - return 0; -} - -static int stmmac_xdp_disable_pool(struct stmmac_priv *priv, u16 queue) -{ - struct stmmac_channel *ch = &priv->channel[queue]; - struct xsk_buff_pool *pool; - bool need_update; - - if (queue >= priv->plat->rx_queues_to_use || - queue >= priv->plat->tx_queues_to_use) - return -EINVAL; - - pool = xsk_get_pool_from_qid(priv->dev, queue); - if (!pool) - return -EINVAL; - - need_update = netif_running(priv->dev) && stmmac_xdp_is_enabled(priv); - - if (need_update) { - napi_disable(&ch->rxtx_napi); - stmmac_disable_rx_queue(priv, queue); - stmmac_disable_tx_queue(priv, queue); - synchronize_rcu(); - } - - xsk_pool_dma_unmap(pool, STMMAC_RX_DMA_ATTR); - - clear_bit(queue, priv->af_xdp_zc_qps); - - if (need_update) { - stmmac_enable_rx_queue(priv, queue); - stmmac_enable_tx_queue(priv, queue); - napi_enable(&ch->rx_napi); - napi_enable(&ch->tx_napi); - } - - return 0; -} - -int stmmac_xdp_setup_pool(struct stmmac_priv *priv, struct xsk_buff_pool *pool, - u16 queue) -{ - return pool ? stmmac_xdp_enable_pool(priv, pool, queue) : - stmmac_xdp_disable_pool(priv, queue); -} - ->>>>>>> -int stmmac_xdp_set_prog(struct stmmac_priv *priv, struct bpf_prog *prog, - struct netlink_ext_ack *extack) -{ - struct net_device *dev = priv->dev; - struct bpf_prog *old_prog; - bool need_update; - bool if_running; - - if_running = netif_running(dev); - - if (prog && dev->mtu > ETH_DATA_LEN) { - /* For now, the driver doesn't support XDP functionality with - * jumbo frames so we return error. - */ - NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported"); - return -EOPNOTSUPP; - } - - need_update = !!priv->xdp_prog != !!prog; - if (if_running && need_update) - stmmac_release(dev); - - old_prog = xchg(&priv->xdp_prog, prog); - if (old_prog) - bpf_prog_put(old_prog); - - /* Disable RX SPH for XDP operation */ - priv->sph = priv->sph_cap && !stmmac_xdp_is_enabled(priv); - - if (if_running && need_update) - stmmac_open(dev); - - return 0; -} diff --git a/rr-cache/2dcd3d9ba71b91a9f4fa6fbc51eb539743aee447/preimage b/rr-cache/2dcd3d9ba71b91a9f4fa6fbc51eb539743aee447/preimage deleted file mode 100644 index e7332b3..0000000 --- a/rr-cache/2dcd3d9ba71b91a9f4fa6fbc51eb539743aee447/preimage +++ /dev/null @@ -1,625 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018-19, Linaro Limited - -#include -#include -#include -#include -#include -#include "stmmac.h" -#include "stmmac_platform.h" - -#define RGMII_IO_MACRO_CONFIG 0x0 -#define SDCC_HC_REG_DLL_CONFIG 0x4 -#define SDCC_HC_REG_DDR_CONFIG 0xC -#define SDCC_HC_REG_DLL_CONFIG2 0x10 -#define SDC4_STATUS 0x14 -#define SDCC_USR_CTL 0x18 -#define RGMII_IO_MACRO_CONFIG2 0x1C -#define RGMII_IO_MACRO_DEBUG1 0x20 -#define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 - -/* RGMII_IO_MACRO_CONFIG fields */ -#define RGMII_CONFIG_FUNC_CLK_EN BIT(30) -#define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) -#define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) -#define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) -#define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) -#define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) -#define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) -#define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) -#define RGMII_CONFIG_LOOPBACK_EN BIT(2) -#define RGMII_CONFIG_PROG_SWAP BIT(1) -#define RGMII_CONFIG_DDR_MODE BIT(0) - -/* SDCC_HC_REG_DLL_CONFIG fields */ -#define SDCC_DLL_CONFIG_DLL_RST BIT(30) -#define SDCC_DLL_CONFIG_PDN BIT(29) -#define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) -#define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) -#define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) -#define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) -#define SDCC_DLL_CONFIG_CDR_EN BIT(17) -#define SDCC_DLL_CONFIG_DLL_EN BIT(16) -#define SDCC_DLL_MCLK_GATING_EN BIT(5) -#define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) - -/* SDCC_HC_REG_DDR_CONFIG fields */ -#define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) -#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) -#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) -#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) -#define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) - -/* SDCC_HC_REG_DLL_CONFIG2 fields */ -#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) -#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) -#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) -#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) -#define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) - -/* SDC4_STATUS bits */ -#define SDC4_STATUS_DLL_LOCK BIT(7) - -/* RGMII_IO_MACRO_CONFIG2 fields */ -#define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) -#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) -#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) -#define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) -#define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) -#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) -#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) - -struct ethqos_emac_por { - unsigned int offset; - unsigned int value; -}; - -struct ethqos_emac_driver_data { - const struct ethqos_emac_por *por; - unsigned int num_por; - bool rgmii_config_looback_en; -}; - -struct qcom_ethqos { - struct platform_device *pdev; - void __iomem *rgmii_base; - - unsigned int rgmii_clk_rate; - struct clk *rgmii_clk; - unsigned int speed; - - const struct ethqos_emac_por *por; - unsigned int num_por; - bool rgmii_config_looback_en; -}; - -static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) -{ - return readl(ethqos->rgmii_base + offset); -} - -static void rgmii_writel(struct qcom_ethqos *ethqos, - int value, unsigned int offset) -{ - writel(value, ethqos->rgmii_base + offset); -} - -static void rgmii_updatel(struct qcom_ethqos *ethqos, - int mask, int val, unsigned int offset) -{ - unsigned int temp; - - temp = rgmii_readl(ethqos, offset); - temp = (temp & ~(mask)) | val; - rgmii_writel(ethqos, temp, offset); -} - -static void rgmii_dump(void *priv) -{ - struct qcom_ethqos *ethqos = priv; - - dev_dbg(ðqos->pdev->dev, "Rgmii register dump\n"); - dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n", - rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); - dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", - rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); - dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", - rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); - dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", - rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); - dev_dbg(ðqos->pdev->dev, "SDC4_STATUS: %x\n", - rgmii_readl(ethqos, SDC4_STATUS)); - dev_dbg(ðqos->pdev->dev, "SDCC_USR_CTL: %x\n", - rgmii_readl(ethqos, SDCC_USR_CTL)); - dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n", - rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); - dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n", - rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); - dev_dbg(ðqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", - rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); -} - -/* Clock rates */ -#define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) -#define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) -#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) - -static void -ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed) -{ - switch (speed) { - case SPEED_1000: - ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ; - break; - - case SPEED_100: - ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; - break; - - case SPEED_10: - ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; - break; - } - - clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate); -} - -static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) -{ - rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, - RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); -} - -static const struct ethqos_emac_por emac_v2_3_0_por[] = { - { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, - { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, - { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, - { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, - { .offset = SDCC_USR_CTL, .value = 0x00010800 }, - { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, -}; - -static const struct ethqos_emac_driver_data emac_v2_3_0_data = { - .por = emac_v2_3_0_por, - .num_por = ARRAY_SIZE(emac_v2_3_0_por), - .rgmii_config_looback_en = true, -<<<<<<< -======= -}; - -static const struct ethqos_emac_por emac_v2_1_0_por[] = { - { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, - { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, - { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, - { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, - { .offset = SDCC_USR_CTL, .value = 0x00010800 }, - { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, -}; - -static const struct ethqos_emac_driver_data emac_v2_1_0_data = { - .por = emac_v2_1_0_por, - .num_por = ARRAY_SIZE(emac_v2_1_0_por), - .rgmii_config_looback_en = false, ->>>>>>> -}; - -static const struct ethqos_emac_por emac_v2_1_0_por[] = { - { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, - { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, - { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, - { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, - { .offset = SDCC_USR_CTL, .value = 0x00010800 }, - { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, -}; - -static const struct ethqos_emac_driver_data emac_v2_1_0_data = { - .por = emac_v2_1_0_por, - .num_por = ARRAY_SIZE(emac_v2_1_0_por), - .rgmii_config_looback_en = false, -}; - - -static int ethqos_dll_configure(struct qcom_ethqos *ethqos) -{ - unsigned int val; - int retry = 1000; - - /* Set CDR_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, - SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Set CDR_EXT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, - SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Clear CK_OUT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, - 0, SDCC_HC_REG_DLL_CONFIG); - - /* Set DLL_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, - SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); - - rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, - 0, SDCC_HC_REG_DLL_CONFIG); - - rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, - 0, SDCC_HC_REG_DLL_CONFIG); - - /* Wait for CK_OUT_EN clear */ - do { - val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); - val &= SDCC_DLL_CONFIG_CK_OUT_EN; - if (!val) - break; - mdelay(1); - retry--; - } while (retry > 0); - if (!retry) - dev_err(ðqos->pdev->dev, "Clear CK_OUT_EN timedout\n"); - - /* Set CK_OUT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, - SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Wait for CK_OUT_EN set */ - retry = 1000; - do { - val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); - val &= SDCC_DLL_CONFIG_CK_OUT_EN; - if (val) - break; - mdelay(1); - retry--; - } while (retry > 0); - if (!retry) - dev_err(ðqos->pdev->dev, "Set CK_OUT_EN timedout\n"); - - /* Set DDR_CAL_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, - SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, - 0, SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, - 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, - BIT(2), SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, - SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, - SDCC_HC_REG_DLL_CONFIG2); - - return 0; -} - -static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) -{ - /* Disable loopback mode */ - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, - 0, RGMII_IO_MACRO_CONFIG2); - - /* Select RGMII, write 0 to interface select */ - rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, - 0, RGMII_IO_MACRO_CONFIG); - - switch (ethqos->speed) { - case SPEED_1000: - rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, - RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, - RGMII_CONFIG_POS_NEG_DATA_SEL, - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, - RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, - RGMII_CONFIG2_RX_PROG_SWAP, - RGMII_IO_MACRO_CONFIG2); - - /* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */ - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, - 57, SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, - SDCC_DDR_CONFIG_PRG_DLY_EN, - SDCC_HC_REG_DDR_CONFIG); - if (ethqos->rgmii_config_looback_en) - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); - else - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - 0, RGMII_IO_MACRO_CONFIG); - break; - - case SPEED_100: - rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, - RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, - BIT(6), RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG2); - /* Write 0x5 to PRG_RCLK_DLY_CODE */ - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, - (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_HC_REG_DDR_CONFIG); - if (ethqos->rgmii_config_looback_en) - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); - else - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - 0, RGMII_IO_MACRO_CONFIG); - - break; - - case SPEED_10: - rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, - RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, - BIT(12) | GENMASK(9, 8), - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG2); - /* Write 0x5 to PRG_RCLK_DLY_CODE */ - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, - (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); - break; - default: - dev_err(ðqos->pdev->dev, - "Invalid speed %d\n", ethqos->speed); - return -EINVAL; - } - - return 0; -} - -static int ethqos_configure(struct qcom_ethqos *ethqos) -{ - volatile unsigned int dll_lock; - unsigned int i, retry = 1000; - - /* Reset to POR values and enable clk */ - for (i = 0; i < ethqos->num_por; i++) - rgmii_writel(ethqos, ethqos->por[i].value, - ethqos->por[i].offset); - ethqos_set_func_clk_en(ethqos); - - /* Initialize the DLL first */ - - /* Set DLL_RST */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, - SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); - - /* Set PDN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, - SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); - - /* Clear DLL_RST */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, - SDCC_HC_REG_DLL_CONFIG); - - /* Clear PDN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, - SDCC_HC_REG_DLL_CONFIG); - - if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { - /* Set DLL_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, - SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Set CK_OUT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, - SDCC_DLL_CONFIG_CK_OUT_EN, - SDCC_HC_REG_DLL_CONFIG); - - /* Set USR_CTL bit 26 with mask of 3 bits */ - rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL); - - /* wait for DLL LOCK */ - do { - mdelay(1); - dll_lock = rgmii_readl(ethqos, SDC4_STATUS); - if (dll_lock & SDC4_STATUS_DLL_LOCK) - break; - retry--; - } while (retry > 0); - if (!retry) - dev_err(ðqos->pdev->dev, - "Timeout while waiting for DLL lock\n"); - } - - if (ethqos->speed == SPEED_1000) - ethqos_dll_configure(ethqos); - - ethqos_rgmii_macro_init(ethqos); - - return 0; -} - -static void ethqos_fix_mac_speed(void *priv, unsigned int speed) -{ - struct qcom_ethqos *ethqos = priv; - - ethqos->speed = speed; - ethqos_update_rgmii_clk(ethqos, speed); - ethqos_configure(ethqos); -} - -static int ethqos_clks_config(void *priv, bool enabled) -{ - struct qcom_ethqos *ethqos = priv; - int ret = 0; - - if (enabled) { - ret = clk_prepare_enable(ethqos->rgmii_clk); - if (ret) { - dev_err(ðqos->pdev->dev, "rgmii_clk enable failed\n"); - return ret; - } - } else { - clk_disable_unprepare(ethqos->rgmii_clk); - } - - return ret; -} - -static int qcom_ethqos_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct plat_stmmacenet_data *plat_dat; - struct stmmac_resources stmmac_res; - const struct ethqos_emac_driver_data *data; - struct qcom_ethqos *ethqos; - int ret; - - ret = stmmac_get_platform_resources(pdev, &stmmac_res); - if (ret) - return ret; - - plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) { - dev_err(&pdev->dev, "dt configuration failed\n"); - return PTR_ERR(plat_dat); - } - - plat_dat->clks_config = ethqos_clks_config; - - ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL); - if (!ethqos) { - ret = -ENOMEM; - goto err_mem; - } - - ethqos->pdev = pdev; - ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); - if (IS_ERR(ethqos->rgmii_base)) { - ret = PTR_ERR(ethqos->rgmii_base); - goto err_mem; - } - - data = of_device_get_match_data(&pdev->dev); - ethqos->por = data->por; - ethqos->num_por = data->num_por; - ethqos->rgmii_config_looback_en = data->rgmii_config_looback_en; - - ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii"); - if (IS_ERR(ethqos->rgmii_clk)) { - ret = PTR_ERR(ethqos->rgmii_clk); - goto err_mem; - } - - ret = ethqos_clks_config(ethqos, true); - if (ret) - goto err_mem; - - ethqos->speed = SPEED_1000; - ethqos_update_rgmii_clk(ethqos, SPEED_1000); - ethqos_set_func_clk_en(ethqos); - - plat_dat->bsp_priv = ethqos; - plat_dat->fix_mac_speed = ethqos_fix_mac_speed; - plat_dat->dump_debug_regs = rgmii_dump; - plat_dat->has_gmac4 = 1; - plat_dat->pmt = 1; - plat_dat->tso_en = of_property_read_bool(np, "snps,tso"); - - ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); - if (ret) - goto err_clk; - - return ret; - -err_clk: - ethqos_clks_config(ethqos, false); - -err_mem: - stmmac_remove_config_dt(pdev, plat_dat); - - return ret; -} - -static int qcom_ethqos_remove(struct platform_device *pdev) -{ - struct qcom_ethqos *ethqos; - int ret; - - ethqos = get_stmmac_bsp_priv(&pdev->dev); - if (!ethqos) - return -ENODEV; - - ret = stmmac_pltfr_remove(pdev); - ethqos_clks_config(ethqos, false); - - return ret; -} - -static const struct of_device_id qcom_ethqos_match[] = { - { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, - { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, - { } -}; -MODULE_DEVICE_TABLE(of, qcom_ethqos_match); - -static struct platform_driver qcom_ethqos_driver = { - .probe = qcom_ethqos_probe, - .remove = qcom_ethqos_remove, - .driver = { - .name = "qcom-ethqos", - .pm = &stmmac_pltfr_pm_ops, - .of_match_table = of_match_ptr(qcom_ethqos_match), - }, -}; -module_platform_driver(qcom_ethqos_driver); - -MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/2dcd3d9ba71b91a9f4fa6fbc51eb539743aee447/preimage.1 b/rr-cache/2dcd3d9ba71b91a9f4fa6fbc51eb539743aee447/preimage.1 deleted file mode 100644 index e7332b3..0000000 --- a/rr-cache/2dcd3d9ba71b91a9f4fa6fbc51eb539743aee447/preimage.1 +++ /dev/null @@ -1,625 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018-19, Linaro Limited - -#include -#include -#include -#include -#include -#include "stmmac.h" -#include "stmmac_platform.h" - -#define RGMII_IO_MACRO_CONFIG 0x0 -#define SDCC_HC_REG_DLL_CONFIG 0x4 -#define SDCC_HC_REG_DDR_CONFIG 0xC -#define SDCC_HC_REG_DLL_CONFIG2 0x10 -#define SDC4_STATUS 0x14 -#define SDCC_USR_CTL 0x18 -#define RGMII_IO_MACRO_CONFIG2 0x1C -#define RGMII_IO_MACRO_DEBUG1 0x20 -#define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 - -/* RGMII_IO_MACRO_CONFIG fields */ -#define RGMII_CONFIG_FUNC_CLK_EN BIT(30) -#define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) -#define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) -#define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) -#define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) -#define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) -#define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) -#define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) -#define RGMII_CONFIG_LOOPBACK_EN BIT(2) -#define RGMII_CONFIG_PROG_SWAP BIT(1) -#define RGMII_CONFIG_DDR_MODE BIT(0) - -/* SDCC_HC_REG_DLL_CONFIG fields */ -#define SDCC_DLL_CONFIG_DLL_RST BIT(30) -#define SDCC_DLL_CONFIG_PDN BIT(29) -#define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) -#define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) -#define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) -#define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) -#define SDCC_DLL_CONFIG_CDR_EN BIT(17) -#define SDCC_DLL_CONFIG_DLL_EN BIT(16) -#define SDCC_DLL_MCLK_GATING_EN BIT(5) -#define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) - -/* SDCC_HC_REG_DDR_CONFIG fields */ -#define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) -#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) -#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) -#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) -#define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) - -/* SDCC_HC_REG_DLL_CONFIG2 fields */ -#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) -#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) -#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) -#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) -#define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) - -/* SDC4_STATUS bits */ -#define SDC4_STATUS_DLL_LOCK BIT(7) - -/* RGMII_IO_MACRO_CONFIG2 fields */ -#define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) -#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) -#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) -#define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) -#define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) -#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) -#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) - -struct ethqos_emac_por { - unsigned int offset; - unsigned int value; -}; - -struct ethqos_emac_driver_data { - const struct ethqos_emac_por *por; - unsigned int num_por; - bool rgmii_config_looback_en; -}; - -struct qcom_ethqos { - struct platform_device *pdev; - void __iomem *rgmii_base; - - unsigned int rgmii_clk_rate; - struct clk *rgmii_clk; - unsigned int speed; - - const struct ethqos_emac_por *por; - unsigned int num_por; - bool rgmii_config_looback_en; -}; - -static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) -{ - return readl(ethqos->rgmii_base + offset); -} - -static void rgmii_writel(struct qcom_ethqos *ethqos, - int value, unsigned int offset) -{ - writel(value, ethqos->rgmii_base + offset); -} - -static void rgmii_updatel(struct qcom_ethqos *ethqos, - int mask, int val, unsigned int offset) -{ - unsigned int temp; - - temp = rgmii_readl(ethqos, offset); - temp = (temp & ~(mask)) | val; - rgmii_writel(ethqos, temp, offset); -} - -static void rgmii_dump(void *priv) -{ - struct qcom_ethqos *ethqos = priv; - - dev_dbg(ðqos->pdev->dev, "Rgmii register dump\n"); - dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n", - rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); - dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", - rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); - dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", - rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); - dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", - rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); - dev_dbg(ðqos->pdev->dev, "SDC4_STATUS: %x\n", - rgmii_readl(ethqos, SDC4_STATUS)); - dev_dbg(ðqos->pdev->dev, "SDCC_USR_CTL: %x\n", - rgmii_readl(ethqos, SDCC_USR_CTL)); - dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n", - rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); - dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n", - rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); - dev_dbg(ðqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", - rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); -} - -/* Clock rates */ -#define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) -#define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) -#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) - -static void -ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed) -{ - switch (speed) { - case SPEED_1000: - ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ; - break; - - case SPEED_100: - ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; - break; - - case SPEED_10: - ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; - break; - } - - clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate); -} - -static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) -{ - rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, - RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); -} - -static const struct ethqos_emac_por emac_v2_3_0_por[] = { - { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, - { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, - { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, - { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, - { .offset = SDCC_USR_CTL, .value = 0x00010800 }, - { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, -}; - -static const struct ethqos_emac_driver_data emac_v2_3_0_data = { - .por = emac_v2_3_0_por, - .num_por = ARRAY_SIZE(emac_v2_3_0_por), - .rgmii_config_looback_en = true, -<<<<<<< -======= -}; - -static const struct ethqos_emac_por emac_v2_1_0_por[] = { - { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, - { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, - { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, - { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, - { .offset = SDCC_USR_CTL, .value = 0x00010800 }, - { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, -}; - -static const struct ethqos_emac_driver_data emac_v2_1_0_data = { - .por = emac_v2_1_0_por, - .num_por = ARRAY_SIZE(emac_v2_1_0_por), - .rgmii_config_looback_en = false, ->>>>>>> -}; - -static const struct ethqos_emac_por emac_v2_1_0_por[] = { - { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, - { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, - { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, - { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, - { .offset = SDCC_USR_CTL, .value = 0x00010800 }, - { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, -}; - -static const struct ethqos_emac_driver_data emac_v2_1_0_data = { - .por = emac_v2_1_0_por, - .num_por = ARRAY_SIZE(emac_v2_1_0_por), - .rgmii_config_looback_en = false, -}; - - -static int ethqos_dll_configure(struct qcom_ethqos *ethqos) -{ - unsigned int val; - int retry = 1000; - - /* Set CDR_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, - SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Set CDR_EXT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, - SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Clear CK_OUT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, - 0, SDCC_HC_REG_DLL_CONFIG); - - /* Set DLL_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, - SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); - - rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, - 0, SDCC_HC_REG_DLL_CONFIG); - - rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, - 0, SDCC_HC_REG_DLL_CONFIG); - - /* Wait for CK_OUT_EN clear */ - do { - val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); - val &= SDCC_DLL_CONFIG_CK_OUT_EN; - if (!val) - break; - mdelay(1); - retry--; - } while (retry > 0); - if (!retry) - dev_err(ðqos->pdev->dev, "Clear CK_OUT_EN timedout\n"); - - /* Set CK_OUT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, - SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Wait for CK_OUT_EN set */ - retry = 1000; - do { - val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); - val &= SDCC_DLL_CONFIG_CK_OUT_EN; - if (val) - break; - mdelay(1); - retry--; - } while (retry > 0); - if (!retry) - dev_err(ðqos->pdev->dev, "Set CK_OUT_EN timedout\n"); - - /* Set DDR_CAL_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, - SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, - 0, SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, - 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, - BIT(2), SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, - SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, - SDCC_HC_REG_DLL_CONFIG2); - - return 0; -} - -static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) -{ - /* Disable loopback mode */ - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, - 0, RGMII_IO_MACRO_CONFIG2); - - /* Select RGMII, write 0 to interface select */ - rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, - 0, RGMII_IO_MACRO_CONFIG); - - switch (ethqos->speed) { - case SPEED_1000: - rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, - RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, - RGMII_CONFIG_POS_NEG_DATA_SEL, - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, - RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, - RGMII_CONFIG2_RX_PROG_SWAP, - RGMII_IO_MACRO_CONFIG2); - - /* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */ - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, - 57, SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, - SDCC_DDR_CONFIG_PRG_DLY_EN, - SDCC_HC_REG_DDR_CONFIG); - if (ethqos->rgmii_config_looback_en) - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); - else - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - 0, RGMII_IO_MACRO_CONFIG); - break; - - case SPEED_100: - rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, - RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, - BIT(6), RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG2); - /* Write 0x5 to PRG_RCLK_DLY_CODE */ - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, - (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_HC_REG_DDR_CONFIG); - if (ethqos->rgmii_config_looback_en) - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); - else - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - 0, RGMII_IO_MACRO_CONFIG); - - break; - - case SPEED_10: - rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, - RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, - BIT(12) | GENMASK(9, 8), - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG2); - /* Write 0x5 to PRG_RCLK_DLY_CODE */ - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, - (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); - break; - default: - dev_err(ðqos->pdev->dev, - "Invalid speed %d\n", ethqos->speed); - return -EINVAL; - } - - return 0; -} - -static int ethqos_configure(struct qcom_ethqos *ethqos) -{ - volatile unsigned int dll_lock; - unsigned int i, retry = 1000; - - /* Reset to POR values and enable clk */ - for (i = 0; i < ethqos->num_por; i++) - rgmii_writel(ethqos, ethqos->por[i].value, - ethqos->por[i].offset); - ethqos_set_func_clk_en(ethqos); - - /* Initialize the DLL first */ - - /* Set DLL_RST */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, - SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); - - /* Set PDN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, - SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); - - /* Clear DLL_RST */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, - SDCC_HC_REG_DLL_CONFIG); - - /* Clear PDN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, - SDCC_HC_REG_DLL_CONFIG); - - if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { - /* Set DLL_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, - SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Set CK_OUT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, - SDCC_DLL_CONFIG_CK_OUT_EN, - SDCC_HC_REG_DLL_CONFIG); - - /* Set USR_CTL bit 26 with mask of 3 bits */ - rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL); - - /* wait for DLL LOCK */ - do { - mdelay(1); - dll_lock = rgmii_readl(ethqos, SDC4_STATUS); - if (dll_lock & SDC4_STATUS_DLL_LOCK) - break; - retry--; - } while (retry > 0); - if (!retry) - dev_err(ðqos->pdev->dev, - "Timeout while waiting for DLL lock\n"); - } - - if (ethqos->speed == SPEED_1000) - ethqos_dll_configure(ethqos); - - ethqos_rgmii_macro_init(ethqos); - - return 0; -} - -static void ethqos_fix_mac_speed(void *priv, unsigned int speed) -{ - struct qcom_ethqos *ethqos = priv; - - ethqos->speed = speed; - ethqos_update_rgmii_clk(ethqos, speed); - ethqos_configure(ethqos); -} - -static int ethqos_clks_config(void *priv, bool enabled) -{ - struct qcom_ethqos *ethqos = priv; - int ret = 0; - - if (enabled) { - ret = clk_prepare_enable(ethqos->rgmii_clk); - if (ret) { - dev_err(ðqos->pdev->dev, "rgmii_clk enable failed\n"); - return ret; - } - } else { - clk_disable_unprepare(ethqos->rgmii_clk); - } - - return ret; -} - -static int qcom_ethqos_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct plat_stmmacenet_data *plat_dat; - struct stmmac_resources stmmac_res; - const struct ethqos_emac_driver_data *data; - struct qcom_ethqos *ethqos; - int ret; - - ret = stmmac_get_platform_resources(pdev, &stmmac_res); - if (ret) - return ret; - - plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) { - dev_err(&pdev->dev, "dt configuration failed\n"); - return PTR_ERR(plat_dat); - } - - plat_dat->clks_config = ethqos_clks_config; - - ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL); - if (!ethqos) { - ret = -ENOMEM; - goto err_mem; - } - - ethqos->pdev = pdev; - ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); - if (IS_ERR(ethqos->rgmii_base)) { - ret = PTR_ERR(ethqos->rgmii_base); - goto err_mem; - } - - data = of_device_get_match_data(&pdev->dev); - ethqos->por = data->por; - ethqos->num_por = data->num_por; - ethqos->rgmii_config_looback_en = data->rgmii_config_looback_en; - - ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii"); - if (IS_ERR(ethqos->rgmii_clk)) { - ret = PTR_ERR(ethqos->rgmii_clk); - goto err_mem; - } - - ret = ethqos_clks_config(ethqos, true); - if (ret) - goto err_mem; - - ethqos->speed = SPEED_1000; - ethqos_update_rgmii_clk(ethqos, SPEED_1000); - ethqos_set_func_clk_en(ethqos); - - plat_dat->bsp_priv = ethqos; - plat_dat->fix_mac_speed = ethqos_fix_mac_speed; - plat_dat->dump_debug_regs = rgmii_dump; - plat_dat->has_gmac4 = 1; - plat_dat->pmt = 1; - plat_dat->tso_en = of_property_read_bool(np, "snps,tso"); - - ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); - if (ret) - goto err_clk; - - return ret; - -err_clk: - ethqos_clks_config(ethqos, false); - -err_mem: - stmmac_remove_config_dt(pdev, plat_dat); - - return ret; -} - -static int qcom_ethqos_remove(struct platform_device *pdev) -{ - struct qcom_ethqos *ethqos; - int ret; - - ethqos = get_stmmac_bsp_priv(&pdev->dev); - if (!ethqos) - return -ENODEV; - - ret = stmmac_pltfr_remove(pdev); - ethqos_clks_config(ethqos, false); - - return ret; -} - -static const struct of_device_id qcom_ethqos_match[] = { - { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, - { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, - { } -}; -MODULE_DEVICE_TABLE(of, qcom_ethqos_match); - -static struct platform_driver qcom_ethqos_driver = { - .probe = qcom_ethqos_probe, - .remove = qcom_ethqos_remove, - .driver = { - .name = "qcom-ethqos", - .pm = &stmmac_pltfr_pm_ops, - .of_match_table = of_match_ptr(qcom_ethqos_match), - }, -}; -module_platform_driver(qcom_ethqos_driver); - -MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/2dcd3d9ba71b91a9f4fa6fbc51eb539743aee447/preimage.2 b/rr-cache/2dcd3d9ba71b91a9f4fa6fbc51eb539743aee447/preimage.2 deleted file mode 100644 index e7332b3..0000000 --- a/rr-cache/2dcd3d9ba71b91a9f4fa6fbc51eb539743aee447/preimage.2 +++ /dev/null @@ -1,625 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018-19, Linaro Limited - -#include -#include -#include -#include -#include -#include "stmmac.h" -#include "stmmac_platform.h" - -#define RGMII_IO_MACRO_CONFIG 0x0 -#define SDCC_HC_REG_DLL_CONFIG 0x4 -#define SDCC_HC_REG_DDR_CONFIG 0xC -#define SDCC_HC_REG_DLL_CONFIG2 0x10 -#define SDC4_STATUS 0x14 -#define SDCC_USR_CTL 0x18 -#define RGMII_IO_MACRO_CONFIG2 0x1C -#define RGMII_IO_MACRO_DEBUG1 0x20 -#define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 - -/* RGMII_IO_MACRO_CONFIG fields */ -#define RGMII_CONFIG_FUNC_CLK_EN BIT(30) -#define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) -#define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) -#define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) -#define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) -#define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) -#define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) -#define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) -#define RGMII_CONFIG_LOOPBACK_EN BIT(2) -#define RGMII_CONFIG_PROG_SWAP BIT(1) -#define RGMII_CONFIG_DDR_MODE BIT(0) - -/* SDCC_HC_REG_DLL_CONFIG fields */ -#define SDCC_DLL_CONFIG_DLL_RST BIT(30) -#define SDCC_DLL_CONFIG_PDN BIT(29) -#define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) -#define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) -#define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) -#define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) -#define SDCC_DLL_CONFIG_CDR_EN BIT(17) -#define SDCC_DLL_CONFIG_DLL_EN BIT(16) -#define SDCC_DLL_MCLK_GATING_EN BIT(5) -#define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) - -/* SDCC_HC_REG_DDR_CONFIG fields */ -#define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) -#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) -#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) -#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) -#define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) - -/* SDCC_HC_REG_DLL_CONFIG2 fields */ -#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) -#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) -#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) -#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) -#define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) - -/* SDC4_STATUS bits */ -#define SDC4_STATUS_DLL_LOCK BIT(7) - -/* RGMII_IO_MACRO_CONFIG2 fields */ -#define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) -#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) -#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) -#define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) -#define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) -#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) -#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) - -struct ethqos_emac_por { - unsigned int offset; - unsigned int value; -}; - -struct ethqos_emac_driver_data { - const struct ethqos_emac_por *por; - unsigned int num_por; - bool rgmii_config_looback_en; -}; - -struct qcom_ethqos { - struct platform_device *pdev; - void __iomem *rgmii_base; - - unsigned int rgmii_clk_rate; - struct clk *rgmii_clk; - unsigned int speed; - - const struct ethqos_emac_por *por; - unsigned int num_por; - bool rgmii_config_looback_en; -}; - -static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) -{ - return readl(ethqos->rgmii_base + offset); -} - -static void rgmii_writel(struct qcom_ethqos *ethqos, - int value, unsigned int offset) -{ - writel(value, ethqos->rgmii_base + offset); -} - -static void rgmii_updatel(struct qcom_ethqos *ethqos, - int mask, int val, unsigned int offset) -{ - unsigned int temp; - - temp = rgmii_readl(ethqos, offset); - temp = (temp & ~(mask)) | val; - rgmii_writel(ethqos, temp, offset); -} - -static void rgmii_dump(void *priv) -{ - struct qcom_ethqos *ethqos = priv; - - dev_dbg(ðqos->pdev->dev, "Rgmii register dump\n"); - dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n", - rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); - dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", - rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); - dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", - rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); - dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", - rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); - dev_dbg(ðqos->pdev->dev, "SDC4_STATUS: %x\n", - rgmii_readl(ethqos, SDC4_STATUS)); - dev_dbg(ðqos->pdev->dev, "SDCC_USR_CTL: %x\n", - rgmii_readl(ethqos, SDCC_USR_CTL)); - dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n", - rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); - dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n", - rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); - dev_dbg(ðqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", - rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); -} - -/* Clock rates */ -#define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) -#define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) -#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) - -static void -ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed) -{ - switch (speed) { - case SPEED_1000: - ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ; - break; - - case SPEED_100: - ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; - break; - - case SPEED_10: - ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; - break; - } - - clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate); -} - -static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) -{ - rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, - RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); -} - -static const struct ethqos_emac_por emac_v2_3_0_por[] = { - { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, - { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, - { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, - { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, - { .offset = SDCC_USR_CTL, .value = 0x00010800 }, - { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, -}; - -static const struct ethqos_emac_driver_data emac_v2_3_0_data = { - .por = emac_v2_3_0_por, - .num_por = ARRAY_SIZE(emac_v2_3_0_por), - .rgmii_config_looback_en = true, -<<<<<<< -======= -}; - -static const struct ethqos_emac_por emac_v2_1_0_por[] = { - { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, - { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, - { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, - { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, - { .offset = SDCC_USR_CTL, .value = 0x00010800 }, - { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, -}; - -static const struct ethqos_emac_driver_data emac_v2_1_0_data = { - .por = emac_v2_1_0_por, - .num_por = ARRAY_SIZE(emac_v2_1_0_por), - .rgmii_config_looback_en = false, ->>>>>>> -}; - -static const struct ethqos_emac_por emac_v2_1_0_por[] = { - { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, - { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, - { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, - { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, - { .offset = SDCC_USR_CTL, .value = 0x00010800 }, - { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, -}; - -static const struct ethqos_emac_driver_data emac_v2_1_0_data = { - .por = emac_v2_1_0_por, - .num_por = ARRAY_SIZE(emac_v2_1_0_por), - .rgmii_config_looback_en = false, -}; - - -static int ethqos_dll_configure(struct qcom_ethqos *ethqos) -{ - unsigned int val; - int retry = 1000; - - /* Set CDR_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, - SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Set CDR_EXT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, - SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Clear CK_OUT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, - 0, SDCC_HC_REG_DLL_CONFIG); - - /* Set DLL_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, - SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); - - rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, - 0, SDCC_HC_REG_DLL_CONFIG); - - rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, - 0, SDCC_HC_REG_DLL_CONFIG); - - /* Wait for CK_OUT_EN clear */ - do { - val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); - val &= SDCC_DLL_CONFIG_CK_OUT_EN; - if (!val) - break; - mdelay(1); - retry--; - } while (retry > 0); - if (!retry) - dev_err(ðqos->pdev->dev, "Clear CK_OUT_EN timedout\n"); - - /* Set CK_OUT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, - SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Wait for CK_OUT_EN set */ - retry = 1000; - do { - val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); - val &= SDCC_DLL_CONFIG_CK_OUT_EN; - if (val) - break; - mdelay(1); - retry--; - } while (retry > 0); - if (!retry) - dev_err(ðqos->pdev->dev, "Set CK_OUT_EN timedout\n"); - - /* Set DDR_CAL_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, - SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, - 0, SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, - 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, - BIT(2), SDCC_HC_REG_DLL_CONFIG2); - - rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, - SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, - SDCC_HC_REG_DLL_CONFIG2); - - return 0; -} - -static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) -{ - /* Disable loopback mode */ - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, - 0, RGMII_IO_MACRO_CONFIG2); - - /* Select RGMII, write 0 to interface select */ - rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, - 0, RGMII_IO_MACRO_CONFIG); - - switch (ethqos->speed) { - case SPEED_1000: - rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, - RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, - RGMII_CONFIG_POS_NEG_DATA_SEL, - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, - RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, - RGMII_CONFIG2_RX_PROG_SWAP, - RGMII_IO_MACRO_CONFIG2); - - /* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */ - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, - 57, SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, - SDCC_DDR_CONFIG_PRG_DLY_EN, - SDCC_HC_REG_DDR_CONFIG); - if (ethqos->rgmii_config_looback_en) - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); - else - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - 0, RGMII_IO_MACRO_CONFIG); - break; - - case SPEED_100: - rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, - RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, - BIT(6), RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG2); - /* Write 0x5 to PRG_RCLK_DLY_CODE */ - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, - (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_HC_REG_DDR_CONFIG); - if (ethqos->rgmii_config_looback_en) - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); - else - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - 0, RGMII_IO_MACRO_CONFIG); - - break; - - case SPEED_10: - rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, - RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_CONFIG_BYPASS_TX_ID_EN, - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, - BIT(12) | GENMASK(9, 8), - RGMII_IO_MACRO_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, - 0, RGMII_IO_MACRO_CONFIG2); - rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, - 0, RGMII_IO_MACRO_CONFIG2); - /* Write 0x5 to PRG_RCLK_DLY_CODE */ - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, - (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, - SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, - SDCC_HC_REG_DDR_CONFIG); - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, - RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); - break; - default: - dev_err(ðqos->pdev->dev, - "Invalid speed %d\n", ethqos->speed); - return -EINVAL; - } - - return 0; -} - -static int ethqos_configure(struct qcom_ethqos *ethqos) -{ - volatile unsigned int dll_lock; - unsigned int i, retry = 1000; - - /* Reset to POR values and enable clk */ - for (i = 0; i < ethqos->num_por; i++) - rgmii_writel(ethqos, ethqos->por[i].value, - ethqos->por[i].offset); - ethqos_set_func_clk_en(ethqos); - - /* Initialize the DLL first */ - - /* Set DLL_RST */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, - SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); - - /* Set PDN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, - SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); - - /* Clear DLL_RST */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, - SDCC_HC_REG_DLL_CONFIG); - - /* Clear PDN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, - SDCC_HC_REG_DLL_CONFIG); - - if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { - /* Set DLL_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, - SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); - - /* Set CK_OUT_EN */ - rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, - SDCC_DLL_CONFIG_CK_OUT_EN, - SDCC_HC_REG_DLL_CONFIG); - - /* Set USR_CTL bit 26 with mask of 3 bits */ - rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL); - - /* wait for DLL LOCK */ - do { - mdelay(1); - dll_lock = rgmii_readl(ethqos, SDC4_STATUS); - if (dll_lock & SDC4_STATUS_DLL_LOCK) - break; - retry--; - } while (retry > 0); - if (!retry) - dev_err(ðqos->pdev->dev, - "Timeout while waiting for DLL lock\n"); - } - - if (ethqos->speed == SPEED_1000) - ethqos_dll_configure(ethqos); - - ethqos_rgmii_macro_init(ethqos); - - return 0; -} - -static void ethqos_fix_mac_speed(void *priv, unsigned int speed) -{ - struct qcom_ethqos *ethqos = priv; - - ethqos->speed = speed; - ethqos_update_rgmii_clk(ethqos, speed); - ethqos_configure(ethqos); -} - -static int ethqos_clks_config(void *priv, bool enabled) -{ - struct qcom_ethqos *ethqos = priv; - int ret = 0; - - if (enabled) { - ret = clk_prepare_enable(ethqos->rgmii_clk); - if (ret) { - dev_err(ðqos->pdev->dev, "rgmii_clk enable failed\n"); - return ret; - } - } else { - clk_disable_unprepare(ethqos->rgmii_clk); - } - - return ret; -} - -static int qcom_ethqos_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct plat_stmmacenet_data *plat_dat; - struct stmmac_resources stmmac_res; - const struct ethqos_emac_driver_data *data; - struct qcom_ethqos *ethqos; - int ret; - - ret = stmmac_get_platform_resources(pdev, &stmmac_res); - if (ret) - return ret; - - plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) { - dev_err(&pdev->dev, "dt configuration failed\n"); - return PTR_ERR(plat_dat); - } - - plat_dat->clks_config = ethqos_clks_config; - - ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL); - if (!ethqos) { - ret = -ENOMEM; - goto err_mem; - } - - ethqos->pdev = pdev; - ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); - if (IS_ERR(ethqos->rgmii_base)) { - ret = PTR_ERR(ethqos->rgmii_base); - goto err_mem; - } - - data = of_device_get_match_data(&pdev->dev); - ethqos->por = data->por; - ethqos->num_por = data->num_por; - ethqos->rgmii_config_looback_en = data->rgmii_config_looback_en; - - ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii"); - if (IS_ERR(ethqos->rgmii_clk)) { - ret = PTR_ERR(ethqos->rgmii_clk); - goto err_mem; - } - - ret = ethqos_clks_config(ethqos, true); - if (ret) - goto err_mem; - - ethqos->speed = SPEED_1000; - ethqos_update_rgmii_clk(ethqos, SPEED_1000); - ethqos_set_func_clk_en(ethqos); - - plat_dat->bsp_priv = ethqos; - plat_dat->fix_mac_speed = ethqos_fix_mac_speed; - plat_dat->dump_debug_regs = rgmii_dump; - plat_dat->has_gmac4 = 1; - plat_dat->pmt = 1; - plat_dat->tso_en = of_property_read_bool(np, "snps,tso"); - - ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); - if (ret) - goto err_clk; - - return ret; - -err_clk: - ethqos_clks_config(ethqos, false); - -err_mem: - stmmac_remove_config_dt(pdev, plat_dat); - - return ret; -} - -static int qcom_ethqos_remove(struct platform_device *pdev) -{ - struct qcom_ethqos *ethqos; - int ret; - - ethqos = get_stmmac_bsp_priv(&pdev->dev); - if (!ethqos) - return -ENODEV; - - ret = stmmac_pltfr_remove(pdev); - ethqos_clks_config(ethqos, false); - - return ret; -} - -static const struct of_device_id qcom_ethqos_match[] = { - { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, - { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, - { } -}; -MODULE_DEVICE_TABLE(of, qcom_ethqos_match); - -static struct platform_driver qcom_ethqos_driver = { - .probe = qcom_ethqos_probe, - .remove = qcom_ethqos_remove, - .driver = { - .name = "qcom-ethqos", - .pm = &stmmac_pltfr_pm_ops, - .of_match_table = of_match_ptr(qcom_ethqos_match), - }, -}; -module_platform_driver(qcom_ethqos_driver); - -MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/348efb6ac5d4f6ee40fbd7a04208727cd4bd073a/preimage b/rr-cache/348efb6ac5d4f6ee40fbd7a04208727cd4bd073a/preimage deleted file mode 100644 index ed907fa..0000000 --- a/rr-cache/348efb6ac5d4f6ee40fbd7a04208727cd4bd073a/preimage +++ /dev/null @@ -1,2553 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * MHI Bus Endpoint stack - * - * Copyright (C) 2021 Linaro Ltd. - * Author: Manivannan Sadhasivam - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "internal.h" - -#define MHI_SUSPEND_MIN 100 -#define MHI_SUSPEND_TIMEOUT 600 - -static DEFINE_IDA(mhi_ep_cntrl_ida); - -static int mhi_ep_create_device(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id); -static int mhi_ep_destroy_device(struct device *dev, void *data); - -<<<<<<< -int mhi_ep_send_event(struct mhi_ep_cntrl *mhi_cntrl, u32 event_ring, - struct mhi_ep_ring_element *el) -{ - struct mhi_ep_ring *ring = &mhi_cntrl->mhi_event[event_ring].ring; - struct device *dev = &mhi_cntrl->mhi_dev->dev; - union mhi_ep_ring_ctx *ctx; - int ret; - - mutex_lock(&mhi_cntrl->event_lock); - ctx = (union mhi_ep_ring_ctx *)&mhi_cntrl->ev_ctx_cache[event_ring]; - if (ring->state == RING_STATE_UINT) { - ret = mhi_ep_ring_start(mhi_cntrl, ring, ctx); - if (ret) { - dev_err(dev, "Error starting event ring (%d)\n", event_ring); -======= -static int mhi_ep_send_event(struct mhi_ep_cntrl *mhi_cntrl, u32 ring_idx, - struct mhi_ep_ring_element *el) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - union mhi_ep_ring_ctx *ctx; - struct mhi_ep_ring *ring; - int ret; - - mutex_lock(&mhi_cntrl->event_lock); - ring = &mhi_cntrl->mhi_event[ring_idx].ring; - ctx = (union mhi_ep_ring_ctx *)&mhi_cntrl->ev_ctx_cache[ring_idx]; - if (!ring->started) { - ret = mhi_ep_ring_start(mhi_cntrl, ring, ctx); - if (ret) { - dev_err(dev, "Error starting event ring (%d)\n", ring_idx); ->>>>>>> - goto err_unlock; - } - } - -<<<<<<< - /* Add element to the event ring */ - ret = mhi_ep_ring_add_element(ring, el); - if (ret) { - dev_err(dev, "Error adding element to event ring (%d)\n", ring_idx); -======= - /* Add element to the primary event ring (0) */ - ret = mhi_ep_ring_add_element(ring, el, 0); - if (ret) { - dev_err(dev, "Error adding element to event ring (%d)\n", event_ring); ->>>>>>> - goto err_unlock; - } - - /* Ensure that the ring pointer gets updated in host memory before triggering IRQ */ -<<<<<<< - smp_wmb(); -======= - wmb(); ->>>>>>> - - mutex_unlock(&mhi_cntrl->event_lock); - - /* - * Raise IRQ to host only if the BEI flag is not set in TRE. Host might - * set this flag for interrupt moderation as per MHI protocol. - */ - if (!MHI_EP_TRE_GET_BEI(el)) -<<<<<<< - mhi_cntrl->raise_irq(mhi_cntrl); -======= - mhi_cntrl->raise_irq(mhi_cntrl, ring->irq_vector); ->>>>>>> - - return 0; - -err_unlock: - mutex_unlock(&mhi_cntrl->event_lock); - - return ret; -} - -static int mhi_ep_send_completion_event(struct mhi_ep_cntrl *mhi_cntrl, -<<<<<<< - struct mhi_ep_ring *ring, u32 len, - enum mhi_ev_ccs code) -{ - struct mhi_ep_ring_element event = {}; - __le32 tmp; - - event.ptr = le64_to_cpu(ring->ring_ctx->generic.rbase) + -======= - struct mhi_ep_ring *ring, u32 len, - enum mhi_ev_ccs code) -{ - struct mhi_ep_ring_element event = {}; - u32 er_index, tmp; - - er_index = mhi_cntrl->ch_ctx_cache[ring->ch_id].erindex; - event.ptr = ring->ring_ctx->generic.rbase + ->>>>>>> - ring->rd_offset * sizeof(struct mhi_ep_ring_element); - - tmp = event.dword[0]; - tmp |= MHI_TRE_EV_DWORD0(code, len); - event.dword[0] = tmp; - - tmp = event.dword[1]; - tmp |= MHI_TRE_EV_DWORD1(ring->ch_id, MHI_PKT_TYPE_TX_EVENT); - event.dword[1] = tmp; - -<<<<<<< - return mhi_ep_send_event(mhi_cntrl, er_index, &event); -} - -int mhi_ep_send_state_change_event(struct mhi_ep_cntrl *mhi_cntrl, - enum mhi_state state) -{ - struct mhi_ep_ring_element event = {}; - u32 tmp; -======= - return mhi_ep_send_event(mhi_cntrl, ring->er_index, &event); -} - -int mhi_ep_send_state_change_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state state) -{ - struct mhi_ep_ring_element event = {}; - __le32 tmp; ->>>>>>> - - tmp = event.dword[0]; - tmp |= MHI_SC_EV_DWORD0(state); - event.dword[0] = tmp; - - tmp = event.dword[1]; - tmp |= MHI_SC_EV_DWORD1(MHI_PKT_TYPE_STATE_CHANGE_EVENT); - event.dword[1] = tmp; - - return mhi_ep_send_event(mhi_cntrl, 0, &event); -} - -int mhi_ep_send_ee_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_ep_execenv exec_env) -{ - struct mhi_ep_ring_element event = {}; -<<<<<<< - __le32 tmp; -======= - u32 tmp; ->>>>>>> - - tmp = event.dword[0]; - tmp |= MHI_EE_EV_DWORD0(exec_env); - event.dword[0] = tmp; - - tmp = event.dword[1]; - tmp |= MHI_SC_EV_DWORD1(MHI_PKT_TYPE_EE_EVENT); - event.dword[1] = tmp; - - return mhi_ep_send_event(mhi_cntrl, 0, &event); -} - -<<<<<<< -static int mhi_ep_send_cmd_comp_event(struct mhi_ep_cntrl *mhi_cntrl, - enum mhi_ev_ccs code) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - struct mhi_ep_ring_element event = {}; - u32 tmp; - - if (code > MHI_EV_CC_BAD_TRE) { - dev_err(dev, "Invalid command completion code: %d\n", code); - return -EINVAL; - } - - event.ptr = mhi_cntrl->cmd_ctx_cache->rbase -======= -static int mhi_ep_send_cmd_comp_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_ev_ccs code) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - struct mhi_ep_ring_element event = {}; - __le32 tmp; - - if (code > MHI_EV_CC_BAD_TRE) { - dev_err(dev, "Invalid command completion code (%d)\n", code); - return -EINVAL; - } - - event.ptr = le64_to_cpu(mhi_cntrl->cmd_ctx_cache->rbase) ->>>>>>> - + (mhi_cntrl->mhi_cmd->ring.rd_offset * - (sizeof(struct mhi_ep_ring_element))); - - tmp = event.dword[0]; - tmp |= MHI_CC_EV_DWORD0(code); - event.dword[0] = tmp; - - tmp = event.dword[1]; - tmp |= MHI_CC_EV_DWORD1(MHI_PKT_TYPE_CMD_COMPLETION_EVENT); - event.dword[1] = tmp; - - return mhi_ep_send_event(mhi_cntrl, 0, &event); -} - -<<<<<<< -/* - * We don't need to do anything special other than setting the MHI SYS_ERR - * state. The host issue will reset all contexts and issue MHI RESET so that we - * could also recover from error state. - */ -void mhi_ep_handle_syserr(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - int ret; - - /* If MHI EP is not enabled, nothing to do */ - if (!mhi_cntrl->is_enabled) - return; - - ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR); - if (ret) - return; - - /* Signal host that the device went to SYS_ERR state */ - ret = mhi_ep_send_state_change_event(mhi_cntrl, MHI_STATE_SYS_ERR); - if (ret) - dev_err(dev, "Failed sending SYS_ERR state change event: %d\n", ret); -} - -void mhi_ep_suspend_channels(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct mhi_ep_chan *mhi_chan; - u32 tmp; - int i; - - for (i = 0; i < mhi_cntrl->max_chan; i++) { - mhi_chan = &mhi_cntrl->mhi_chan[i]; - - if (!mhi_chan->mhi_dev) - continue; - - mutex_lock(&mhi_chan->lock); - /* Skip if the channel is not currently running */ - tmp = mhi_cntrl->ch_ctx_cache[i].chcfg; - if (FIELD_GET(CHAN_CTX_CHSTATE_MASK, tmp) != MHI_CH_STATE_RUNNING) { - mutex_unlock(&mhi_chan->lock); - continue; - } - - dev_dbg(&mhi_chan->mhi_dev->dev, "Suspending channel\n"); - /* Set channel state to SUSPENDED */ - tmp &= ~CHAN_CTX_CHSTATE_MASK; - tmp |= (MHI_CH_STATE_SUSPENDED << CHAN_CTX_CHSTATE_SHIFT); - mhi_cntrl->ch_ctx_cache[i].chcfg = tmp; - mutex_unlock(&mhi_chan->lock); - } -} - -void mhi_ep_resume_channels(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct mhi_ep_chan *mhi_chan; - u32 tmp; - int i; - - for (i = 0; i < mhi_cntrl->max_chan; i++) { - mhi_chan = &mhi_cntrl->mhi_chan[i]; - - if (!mhi_chan->mhi_dev) - continue; - - mutex_lock(&mhi_chan->lock); - /* Skip if the channel is not currently suspended */ - tmp = mhi_cntrl->ch_ctx_cache[i].chcfg; - if (FIELD_GET(CHAN_CTX_CHSTATE_MASK, tmp) != MHI_CH_STATE_SUSPENDED) { - mutex_unlock(&mhi_chan->lock); - continue; - } - - dev_dbg(&mhi_chan->mhi_dev->dev, "Resuming channel\n"); - /* Set channel state to RUNNING */ - tmp &= ~CHAN_CTX_CHSTATE_MASK; - tmp |= (MHI_CH_STATE_RUNNING << CHAN_CTX_CHSTATE_SHIFT); - mhi_cntrl->ch_ctx_cache[i].chcfg = tmp; - mutex_unlock(&mhi_chan->lock); - } -======= -int mhi_ep_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, size_t size, - phys_addr_t *phys_ptr, void __iomem **virt) -{ - size_t offset = pci_addr % 0x1000; - void __iomem *buf; - phys_addr_t phys; - int ret; - - size += offset; - - buf = mhi_cntrl->alloc_addr(mhi_cntrl, &phys, size); - if (!buf) - return -ENOMEM; - - ret = mhi_cntrl->map_addr(mhi_cntrl, phys, pci_addr - offset, size); - if (ret) { - mhi_cntrl->free_addr(mhi_cntrl, phys, buf, size); - return ret; - } - - *phys_ptr = phys + offset; - *virt = buf + offset; - - return 0; -} - -void mhi_ep_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, phys_addr_t phys, - void __iomem *virt, size_t size) -{ - size_t offset = pci_addr % 0x1000; - - size += offset; - - mhi_cntrl->unmap_addr(mhi_cntrl, phys - offset); - mhi_cntrl->free_addr(mhi_cntrl, phys - offset, virt - offset, size); ->>>>>>> -} - -int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ep_ring_element *el) -{ - struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl; - struct device *dev = &mhi_cntrl->mhi_dev->dev; -<<<<<<< - struct mhi_ep_ring *ch_ring, *event_ring; - union mhi_ep_ring_ctx *event_ctx; - struct mhi_result result = {}; - struct mhi_ep_chan *mhi_chan; - u32 event_ring_idx, tmp; - u32 ch_id; -======= - struct mhi_result result = {}; - struct mhi_ep_chan *mhi_chan; - struct mhi_ep_ring *ch_ring; - u32 tmp, ch_id; ->>>>>>> - int ret; - - ch_id = MHI_TRE_GET_CMD_CHID(el); - mhi_chan = &mhi_cntrl->mhi_chan[ch_id]; - ch_ring = &mhi_cntrl->mhi_chan[ch_id].ring; - - switch (MHI_TRE_GET_CMD_TYPE(el)) { - case MHI_PKT_TYPE_START_CHAN_CMD: - dev_dbg(dev, "Received START command for channel (%d)\n", ch_id); - - mutex_lock(&mhi_chan->lock); - /* Initialize and configure the corresponding channel ring */ -<<<<<<< - if (!ch_ring->started) { -======= - if (ch_ring->state == RING_STATE_UINT) { ->>>>>>> - ret = mhi_ep_ring_start(mhi_cntrl, ch_ring, - (union mhi_ep_ring_ctx *)&mhi_cntrl->ch_ctx_cache[ch_id]); - if (ret) { - dev_err(dev, "Failed to start ring for channel (%d)\n", ch_id); - ret = mhi_ep_send_cmd_comp_event(mhi_cntrl, - MHI_EV_CC_UNDEFINED_ERR); - if (ret) -<<<<<<< - dev_err(dev, "Error sending completion event (%d)\n", -======= - dev_err(dev, "Error sending completion event: %d\n", ->>>>>>> - MHI_EV_CC_UNDEFINED_ERR); - - goto err_unlock; - } - } - - /* Enable DB for the channel */ - mhi_ep_mmio_enable_chdb_a7(mhi_cntrl, ch_id); - -<<<<<<< - /* Set channel state to RUNNING */ - mhi_chan->state = MHI_CH_STATE_RUNNING; - tmp = le32_to_cpu(mhi_cntrl->ch_ctx_cache[ch_id].chcfg); - tmp &= ~CHAN_CTX_CHSTATE_MASK; - tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_RUNNING); - mhi_cntrl->ch_ctx_cache[ch_id].chcfg = cpu_to_le32(tmp); - - ret = mhi_ep_send_cmd_comp_event(mhi_cntrl, MHI_EV_CC_SUCCESS); - if (ret) { - dev_err(dev, "Error sending command completion event (%d)\n", -======= - mutex_lock(&mhi_cntrl->event_lock); - event_ring_idx = mhi_cntrl->ch_ctx_cache[ch_id].erindex; - event_ring = &mhi_cntrl->mhi_event[event_ring_idx].ring; - event_ctx = (union mhi_ep_ring_ctx *)&mhi_cntrl->ev_ctx_cache[event_ring_idx]; - if (event_ring->state == RING_STATE_UINT) { - ret = mhi_ep_ring_start(mhi_cntrl, event_ring, event_ctx); - if (ret) { - dev_err(dev, "Error starting event ring: %d\n", - mhi_cntrl->ch_ctx_cache[ch_id].erindex); - mutex_unlock(&mhi_cntrl->event_lock); - goto err_unlock; - } - } - - mutex_unlock(&mhi_cntrl->event_lock); - - /* Set channel state to RUNNING */ - mhi_chan->state = MHI_CH_STATE_RUNNING; - tmp = mhi_cntrl->ch_ctx_cache[ch_id].chcfg; - tmp &= ~CHAN_CTX_CHSTATE_MASK; - tmp |= (MHI_CH_STATE_RUNNING << CHAN_CTX_CHSTATE_SHIFT); - mhi_cntrl->ch_ctx_cache[ch_id].chcfg = tmp; - - ret = mhi_ep_send_cmd_comp_event(mhi_cntrl, MHI_EV_CC_SUCCESS); - if (ret) { - dev_err(dev, "Error sending command completion event: %d\n", ->>>>>>> - MHI_EV_CC_SUCCESS); - goto err_unlock; - } - - mutex_unlock(&mhi_chan->lock); - - /* - * Create MHI device only during UL channel start. Since the MHI - * channels operate in a pair, we'll associate both UL and DL - * channels to the same device. - * - * We also need to check for mhi_dev != NULL because, the host - * will issue START_CHAN command during resume and we don't - * destroy the device during suspend. - */ - if (!(ch_id % 2) && !mhi_chan->mhi_dev) { - ret = mhi_ep_create_device(mhi_cntrl, ch_id); - if (ret) { - dev_err(dev, "Error creating device for channel (%d)\n", ch_id); - return ret; - } - } - - break; - case MHI_PKT_TYPE_STOP_CHAN_CMD: - dev_dbg(dev, "Received STOP command for channel (%d)\n", ch_id); -<<<<<<< - if (!ch_ring->started) { -======= - if (ch_ring->state == RING_STATE_UINT) { ->>>>>>> - dev_err(dev, "Channel (%d) not opened\n", ch_id); - return -ENODEV; - } - - mutex_lock(&mhi_chan->lock); - /* Disable DB for the channel */ - mhi_ep_mmio_disable_chdb_a7(mhi_cntrl, ch_id); - -<<<<<<< -======= - /* Set the local value of the transfer ring read pointer to the channel context */ - ch_ring->rd_offset = mhi_ep_ring_addr2offset(ch_ring, - ch_ring->ring_ctx->generic.rp); - ->>>>>>> - /* Send channel disconnect status to client drivers */ - result.transaction_status = -ENOTCONN; - result.bytes_xferd = 0; - mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); - - /* Set channel state to STOP */ - mhi_chan->state = MHI_CH_STATE_STOP; -<<<<<<< - tmp = le32_to_cpu(mhi_cntrl->ch_ctx_cache[ch_id].chcfg); - tmp &= ~CHAN_CTX_CHSTATE_MASK; - tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_STOP); - mhi_cntrl->ch_ctx_cache[ch_id].chcfg = cpu_to_le32(tmp); - - ret = mhi_ep_send_cmd_comp_event(mhi_cntrl, MHI_EV_CC_SUCCESS); - if (ret) { - dev_err(dev, "Error sending command completion event (%d)\n", -======= - tmp = mhi_cntrl->ch_ctx_cache[ch_id].chcfg; - tmp &= ~CHAN_CTX_CHSTATE_MASK; - tmp |= (MHI_CH_STATE_STOP << CHAN_CTX_CHSTATE_SHIFT); - mhi_cntrl->ch_ctx_cache[ch_id].chcfg = tmp; - - ret = mhi_ep_send_cmd_comp_event(mhi_cntrl, MHI_EV_CC_SUCCESS); - if (ret) { - dev_err(dev, "Error sending command completion event: %d\n", ->>>>>>> - MHI_EV_CC_SUCCESS); - goto err_unlock; - } - - mutex_unlock(&mhi_chan->lock); - break; - case MHI_PKT_TYPE_RESET_CHAN_CMD: - dev_dbg(dev, "Received STOP command for channel (%d)\n", ch_id); -<<<<<<< - if (!ch_ring->started) { -======= - if (ch_ring->state == RING_STATE_UINT) { ->>>>>>> - dev_err(dev, "Channel (%d) not opened\n", ch_id); - return -ENODEV; - } - - mutex_lock(&mhi_chan->lock); - /* Stop and reset the transfer ring */ -<<<<<<< - mhi_ep_ring_reset(mhi_cntrl, ch_ring); -======= - mhi_ep_ring_stop(mhi_cntrl, ch_ring); ->>>>>>> - - /* Send channel disconnect status to client driver */ - result.transaction_status = -ENOTCONN; - result.bytes_xferd = 0; - mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); - - /* Set channel state to DISABLED */ - mhi_chan->state = MHI_CH_STATE_DISABLED; -<<<<<<< - tmp = le32_to_cpu(mhi_cntrl->ch_ctx_cache[ch_id].chcfg); - tmp &= ~CHAN_CTX_CHSTATE_MASK; - tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_DISABLED); - mhi_cntrl->ch_ctx_cache[ch_id].chcfg = cpu_to_le32(tmp); - - ret = mhi_ep_send_cmd_comp_event(mhi_cntrl, MHI_EV_CC_SUCCESS); - if (ret) { - dev_err(dev, "Error sending command completion event (%d)\n", - MHI_EV_CC_SUCCESS); - goto err_unlock; - } - - mutex_unlock(&mhi_chan->lock); - break; - default: - dev_err(dev, "Invalid command received: %d for channel (%d)\n", -======= - tmp = mhi_cntrl->ch_ctx_cache[ch_id].chcfg; - tmp &= ~CHAN_CTX_CHSTATE_MASK; - tmp |= (MHI_CH_STATE_DISABLED << CHAN_CTX_CHSTATE_SHIFT); - mhi_cntrl->ch_ctx_cache[ch_id].chcfg = tmp; - - ret = mhi_ep_send_cmd_comp_event(mhi_cntrl, MHI_EV_CC_SUCCESS); - if (ret) { - dev_err(dev, "Error sending command completion event: %d\n", - MHI_EV_CC_SUCCESS); - goto err_unlock; - } - mutex_unlock(&mhi_chan->lock); - break; - default: - dev_err(dev, "Invalid command received: %d for channel (%d)", ->>>>>>> - MHI_TRE_GET_CMD_TYPE(el), ch_id); - return -EINVAL; - } - - return 0; - -err_unlock: - mutex_unlock(&mhi_chan->lock); - - return ret; -} - -<<<<<<< -bool mhi_ep_queue_is_empty(struct mhi_ep_device *mhi_dev, enum dma_data_direction dir) -{ - struct mhi_ep_chan *mhi_chan = (dir == DMA_FROM_DEVICE) ? mhi_dev->dl_chan : - mhi_dev->ul_chan; - struct mhi_ep_cntrl *mhi_cntrl = mhi_dev->mhi_cntrl; - struct mhi_ep_ring *ring = &mhi_cntrl->mhi_chan[mhi_chan->chan].ring; - - return !!(ring->rd_offset == ring->wr_offset); -} -EXPORT_SYMBOL_GPL(mhi_ep_queue_is_empty); - -static int mhi_ep_read_channel(struct mhi_ep_cntrl *mhi_cntrl, - struct mhi_ep_ring *ring, - struct mhi_result *result, - u32 len) -{ - struct mhi_ep_chan *mhi_chan = &mhi_cntrl->mhi_chan[ring->ch_id]; - size_t bytes_to_read, read_offset, write_offset; - struct device *dev = &mhi_cntrl->mhi_dev->dev; - struct mhi_ep_ring_element *el; - bool td_done = false; - void *write_to_loc; - u64 read_from_loc; - u32 buf_remaining; -======= -static int mhi_ep_check_tre_bytes_left(struct mhi_ep_cntrl *mhi_cntrl, - struct mhi_ep_ring *ring, - struct mhi_ep_ring_element *el) -{ - struct mhi_ep_chan *mhi_chan = &mhi_cntrl->mhi_chan[ring->ch_id]; - bool td_done = 0; - - /* A full TRE worth of data was consumed. Check if we are at a TD boundary */ - if (mhi_chan->tre_bytes_left == 0) { - if (MHI_EP_TRE_GET_CHAIN(el)) { - if (MHI_EP_TRE_GET_IEOB(el)) - mhi_ep_send_completion_event(mhi_cntrl, - ring, MHI_EP_TRE_GET_LEN(el), MHI_EV_CC_EOB); - } else { - if (MHI_EP_TRE_GET_IEOT(el)) - mhi_ep_send_completion_event(mhi_cntrl, - ring, MHI_EP_TRE_GET_LEN(el), MHI_EV_CC_EOT); - td_done = 1; - } - - mhi_ep_ring_inc_index(ring); - mhi_chan->tre_bytes_left = 0; - mhi_chan->tre_loc = 0; - } - - return td_done; -} - -static int mhi_ep_read_channel(struct mhi_ep_cntrl *mhi_cntrl, - struct mhi_ep_ring *ring, - struct mhi_result *result, - u32 len) -{ - struct mhi_ep_chan *mhi_chan = &mhi_cntrl->mhi_chan[ring->ch_id]; - struct device *dev = &mhi_cntrl->mhi_dev->dev; - size_t bytes_to_read, addr_offset; - struct mhi_ep_ring_element *el; - ssize_t bytes_read = 0; - u32 buf_remaining; - void __iomem *tre_buf; - phys_addr_t tre_phys; - void *write_to_loc; - u64 read_from_loc; - bool td_done = 0; ->>>>>>> - int ret; - - buf_remaining = len; - - do { - /* Don't process the transfer ring if the channel is not in RUNNING state */ - if (mhi_chan->state != MHI_CH_STATE_RUNNING) - return -ENODEV; - - el = &ring->ring_cache[ring->rd_offset]; - -<<<<<<< - /* Check if there is data pending to be read from previous read operation */ - if (mhi_chan->tre_bytes_left) { - dev_dbg(dev, "TRE bytes remaining: %d\n", mhi_chan->tre_bytes_left); - bytes_to_read = min(buf_remaining, mhi_chan->tre_bytes_left); - } else { -======= - if (mhi_chan->tre_loc) { - bytes_to_read = min(buf_remaining, - mhi_chan->tre_bytes_left); - dev_dbg(dev, "TRE bytes remaining: %d", mhi_chan->tre_bytes_left); - } else { - if (mhi_ep_queue_is_empty(mhi_chan->mhi_dev, DMA_TO_DEVICE)) - /* Nothing to do */ - return 0; - ->>>>>>> - mhi_chan->tre_loc = MHI_EP_TRE_GET_PTR(el); - mhi_chan->tre_size = MHI_EP_TRE_GET_LEN(el); - mhi_chan->tre_bytes_left = mhi_chan->tre_size; - - bytes_to_read = min(buf_remaining, mhi_chan->tre_size); - } - -<<<<<<< - bytes_read += bytes_to_read; - addr_offset = mhi_chan->tre_size - mhi_chan->tre_bytes_left; - read_from_loc = mhi_chan->tre_loc + addr_offset; - write_to_loc = result->buf_addr + (len - buf_remaining); - mhi_chan->tre_bytes_left -= bytes_to_read; - - tre_buf = mhi_cntrl->alloc_addr(mhi_cntrl, &tre_phys, bytes_to_read); - if (!tre_buf) { - dev_err(dev, "Failed to allocate TRE buffer\n"); - return -ENOMEM; - } - - ret = mhi_cntrl->map_addr(mhi_cntrl, tre_phys, read_from_loc, bytes_to_read); - if (ret) { - dev_err(dev, "Failed to map TRE buffer\n"); - goto err_tre_free; - } - - dev_dbg(&mhi_chan->mhi_dev->dev, "Reading %d bytes", bytes_to_read); - memcpy_fromio(write_to_loc, tre_buf, bytes_to_read); - - mhi_cntrl->unmap_addr(mhi_cntrl, tre_phys); - mhi_cntrl->free_addr(mhi_cntrl, tre_phys, tre_buf, bytes_to_read); - - buf_remaining -= bytes_to_read; - td_done = mhi_ep_check_tre_bytes_left(mhi_cntrl, ring, el); - } while (buf_remaining && !td_done); - - result->bytes_xferd = bytes_read; - - return bytes_read; - -err_tre_free: - mhi_cntrl->free_addr(mhi_cntrl, tre_phys, tre_buf, bytes_to_read); - - return ret; -======= - read_offset = mhi_chan->tre_size - mhi_chan->tre_bytes_left; - write_offset = len - buf_remaining; - read_from_loc = mhi_chan->tre_loc + read_offset; - write_to_loc = result->buf_addr + write_offset; - - dev_dbg(dev, "Reading %zd bytes from channel (%d)\n", bytes_to_read, ring->ch_id); - ret = mhi_cntrl->read_from_host(mhi_cntrl, read_from_loc, write_to_loc, - bytes_to_read); - if (ret < 0) - return ret; - - buf_remaining -= bytes_to_read; - mhi_chan->tre_bytes_left -= bytes_to_read; - - /* - * Once the TRE (Transfer Ring Element) of a TD (Transfer Descriptor) has been - * read completely: - * - * 1. Send completion event to the host based on the flags set in TRE. - * 2. Increment the local read offset of the transfer ring. - */ - if (!mhi_chan->tre_bytes_left) { - /* - * The host will split the data packet into multiple TREs if it can't fit - * the packet in a single TRE. In that case, CHAIN flag will be set by the - * host for all TREs except the last one. - */ - if (MHI_EP_TRE_GET_CHAIN(el)) { - /* - * IEOB (Interrupt on End of Block) flag will be set by the host if - * it expects the completion event for all TREs of a TD. - */ - if (MHI_EP_TRE_GET_IEOB(el)) - mhi_ep_send_completion_event(mhi_cntrl, - ring, MHI_EP_TRE_GET_LEN(el), MHI_EV_CC_EOB); - } else { - /* - * IEOT (Interrupt on End of Transfer) flag will be set by the host - * for the last TRE of the TD and expects the completion event for - * the same. - */ - if (MHI_EP_TRE_GET_IEOT(el)) - mhi_ep_send_completion_event(mhi_cntrl, - ring, MHI_EP_TRE_GET_LEN(el), MHI_EV_CC_EOT); - td_done = true; - } - - mhi_ep_ring_inc_index(ring); - } - - result->bytes_xferd += bytes_to_read; - } while (buf_remaining && !td_done); - - return 0; ->>>>>>> -} - -int mhi_ep_process_tre_ring(struct mhi_ep_ring *ring, struct mhi_ep_ring_element *el) -{ - struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl; - struct mhi_result result = {}; - u32 len = MHI_EP_DEFAULT_MTU; - struct mhi_ep_chan *mhi_chan; -<<<<<<< - int ret = 0; -======= - int ret; ->>>>>>> - - mhi_chan = &mhi_cntrl->mhi_chan[ring->ch_id]; - - /* - * Bail out if transfer callback is not registered for the channel. - * This is most likely due to the client driver not loaded at this point. - */ - if (!mhi_chan->xfer_cb) { - dev_err(&mhi_chan->mhi_dev->dev, "Client driver not available\n"); - return -ENODEV; - } - -<<<<<<< -======= - dev_dbg(&mhi_chan->mhi_dev->dev, "Processing TRE ring\n"); - - mutex_lock(&mhi_chan->lock); ->>>>>>> - if (ring->ch_id % 2) { - /* DL channel */ - result.dir = mhi_chan->dir; - mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); - } else { - /* UL channel */ -<<<<<<< - do { - result.buf_addr = kzalloc(len, GFP_KERNEL); - if (!result.buf_addr) - return -ENOMEM; - - ret = mhi_ep_read_channel(mhi_cntrl, ring, &result, len); - if (ret < 0) { - dev_err(&mhi_chan->mhi_dev->dev, "Failed to read channel\n"); - kfree(result.buf_addr); - return ret; -======= - while (1) { - result.buf_addr = kzalloc(len, GFP_KERNEL); - if (!result.buf_addr) { - ret = -ENOMEM; - goto err_unlock; - } - - ret = mhi_ep_read_channel(mhi_cntrl, ring, &result, len); - if (ret < 0) { - dev_err(&mhi_chan->mhi_dev->dev, "Failed to read channel"); - kfree(result.buf_addr); - break; - } else if (ret == 0) { - /* No more data to read */ - kfree(result.buf_addr); - break; ->>>>>>> - } - - result.dir = mhi_chan->dir; - mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); - kfree(result.buf_addr); -<<<<<<< - result.bytes_xferd = 0; - - /* Read until the ring becomes empty */ - } while (!mhi_ep_queue_is_empty(mhi_chan->mhi_dev, DMA_TO_DEVICE)); - } - - return 0; -} - -int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, enum dma_data_direction dir, - struct sk_buff *skb, size_t len, enum mhi_flags mflags) -{ - struct mhi_ep_chan *mhi_chan = (dir == DMA_FROM_DEVICE) ? mhi_dev->dl_chan : - mhi_dev->ul_chan; - struct mhi_ep_cntrl *mhi_cntrl = mhi_dev->mhi_cntrl; - struct device *dev = &mhi_chan->mhi_dev->dev; - struct mhi_ep_ring_element *el; - struct mhi_ep_ring *ring; - size_t bytes_to_write; - enum mhi_ev_ccs code; - void *read_from_loc; - u32 buf_remaining; - u64 write_to_loc; - u32 tre_len; - int ret = 0; - - if (dir == DMA_TO_DEVICE) - return -EINVAL; - - buf_remaining = len; - ring = &mhi_cntrl->mhi_chan[mhi_chan->chan].ring; - - mutex_lock(&mhi_chan->lock); - - do { - /* Don't process the transfer ring if the channel is not in RUNNING state */ - if (mhi_chan->state != MHI_CH_STATE_RUNNING) { - dev_err(dev, "Channel not available\n"); - ret = -ENODEV; - goto err_exit; - } - - if (mhi_ep_queue_is_empty(mhi_dev, dir)) { - dev_err(dev, "TRE not available!\n"); - ret = -EINVAL; - goto err_exit; - } - - el = &ring->ring_cache[ring->rd_offset]; - tre_len = MHI_EP_TRE_GET_LEN(el); - if (skb->len > tre_len) { - dev_err(dev, "Buffer size (%d) is too large for TRE (%d)!\n", - skb->len, tre_len); - ret = -ENOMEM; - goto err_exit; - } - - bytes_to_write = min(buf_remaining, tre_len); - read_from_loc = skb->data; - write_to_loc = MHI_EP_TRE_GET_PTR(el); - - ret = mhi_cntrl->write_to_host(mhi_cntrl, read_from_loc, write_to_loc, - bytes_to_write); - if (ret < 0) - goto err_exit; - - buf_remaining -= bytes_to_write; - /* - * For all TREs queued by the host for DL channel, only the EOT flag will be set. - * If the packet doesn't fit into a single TRE, send the OVERFLOW event to - * the host so that the host can adjust the packet boundary to next TREs. Else send - * the EOT event to the host indicating the packet boundary. - */ - if (buf_remaining) - code = MHI_EV_CC_OVERFLOW; - else - code = MHI_EV_CC_EOT; - - ret = mhi_ep_send_completion_event(mhi_cntrl, ring, bytes_to_write, code); - if (ret) { - dev_err(dev, "Error sending completion event\n"); - goto err_exit; - } - - mhi_ep_ring_inc_index(ring); - } while (buf_remaining); - - /* - * During high network traffic, sometimes the DL doorbell interrupt from the host is missed - * by the endpoint. So manually check for the write pointer update here so that we don't run - * out of buffer due to missing interrupts. - */ - if (ring->rd_offset + 1 == ring->wr_offset) { - ret = mhi_ep_update_wr_offset(ring); - if (ret) { - dev_err(dev, "Error updating write pointer\n"); - goto err_exit; - } - } - - mutex_unlock(&mhi_chan->lock); - - return 0; - -err_exit: -======= - } - } - -err_unlock: ->>>>>>> - mutex_unlock(&mhi_chan->lock); - - return ret; -} -<<<<<<< -======= -EXPORT_SYMBOL_GPL(mhi_ep_queue_skb); ->>>>>>> - -static int mhi_ep_cache_host_cfg(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - int ret; - - /* Update the number of event rings (NER) programmed by the host */ - mhi_ep_mmio_update_ner(mhi_cntrl); - - dev_dbg(dev, "Number of Event rings: %d, HW Event rings: %d\n", - mhi_cntrl->event_rings, mhi_cntrl->hw_event_rings); - - mhi_cntrl->ch_ctx_host_size = sizeof(struct mhi_chan_ctxt) * - mhi_cntrl->max_chan; - mhi_cntrl->ev_ctx_host_size = sizeof(struct mhi_event_ctxt) * - mhi_cntrl->event_rings; - mhi_cntrl->cmd_ctx_host_size = sizeof(struct mhi_cmd_ctxt); - - /* Get the channel context base pointer from host */ - mhi_ep_mmio_get_chc_base(mhi_cntrl); - -<<<<<<< - /* Allocate and map memory for caching host channel context */ - ret = mhi_ep_alloc_map(mhi_cntrl, mhi_cntrl->ch_ctx_host_pa, mhi_cntrl->ch_ctx_host_size, - &mhi_cntrl->ch_ctx_cache_phys, - (void __iomem **)&mhi_cntrl->ch_ctx_cache); - if (ret) { - dev_err(dev, "Failed to allocate and map ch_ctx_cache\n"); - return ret; -======= - /* Allocate memory for caching host channel context */ - mhi_cntrl->ch_ctx_cache = mhi_cntrl->alloc_addr(mhi_cntrl, &mhi_cntrl->ch_ctx_cache_phys, - mhi_cntrl->ch_ctx_host_size); - if (!mhi_cntrl->ch_ctx_cache) { - dev_err(dev, "Failed to allocate ch_ctx_cache memory\n"); - return -ENOMEM; - } - - /* Map the host channel context */ - ret = mhi_cntrl->map_addr(mhi_cntrl, mhi_cntrl->ch_ctx_cache_phys, - mhi_cntrl->ch_ctx_host_pa, mhi_cntrl->ch_ctx_host_size); - if (ret) { - dev_err(dev, "Failed to map ch_ctx_cache\n"); - goto err_ch_ctx; ->>>>>>> - } - - /* Get the event context base pointer from host */ - mhi_ep_mmio_get_erc_base(mhi_cntrl); - -<<<<<<< - /* Allocate and map memory for caching host event context */ - ret = mhi_ep_alloc_map(mhi_cntrl, mhi_cntrl->ev_ctx_host_pa, mhi_cntrl->ev_ctx_host_size, - &mhi_cntrl->ev_ctx_cache_phys, - (void __iomem **)&mhi_cntrl->ev_ctx_cache); - if (ret) { - dev_err(dev, "Failed to allocate and map ev_ctx_cache\n"); - goto err_ch_ctx; -======= - /* Allocate memory for caching host event context */ - mhi_cntrl->ev_ctx_cache = mhi_cntrl->alloc_addr(mhi_cntrl, &mhi_cntrl->ev_ctx_cache_phys, - mhi_cntrl->ev_ctx_host_size); - if (!mhi_cntrl->ev_ctx_cache) { - dev_err(dev, "Failed to allocate ev_ctx_cache memory\n"); - ret = -ENOMEM; - goto err_ch_ctx_map; - } - - /* Map the host event context */ - ret = mhi_cntrl->map_addr(mhi_cntrl, mhi_cntrl->ev_ctx_cache_phys, - mhi_cntrl->ev_ctx_host_pa, mhi_cntrl->ev_ctx_host_size); - if (ret) { - dev_err(dev, "Failed to map ev_ctx_cache\n"); - goto err_ev_ctx; ->>>>>>> - } - - /* Get the command context base pointer from host */ - mhi_ep_mmio_get_crc_base(mhi_cntrl); - -<<<<<<< - /* Allocate and map memory for caching host command context */ - ret = mhi_ep_alloc_map(mhi_cntrl, mhi_cntrl->cmd_ctx_host_pa, mhi_cntrl->cmd_ctx_host_size, - &mhi_cntrl->cmd_ctx_cache_phys, - (void __iomem **)&mhi_cntrl->cmd_ctx_cache); - if (ret) { - dev_err(dev, "Failed to allocate and map cmd_ctx_cache\n"); - goto err_ev_ctx; -======= - /* Allocate memory for caching host command context */ - mhi_cntrl->cmd_ctx_cache = mhi_cntrl->alloc_addr(mhi_cntrl, &mhi_cntrl->cmd_ctx_cache_phys, - mhi_cntrl->cmd_ctx_host_size); - if (!mhi_cntrl->cmd_ctx_cache) { - dev_err(dev, "Failed to allocate cmd_ctx_cache memory\n"); - ret = -ENOMEM; - goto err_ev_ctx_map; - } - - /* Map the host command context */ - ret = mhi_cntrl->map_addr(mhi_cntrl, mhi_cntrl->cmd_ctx_cache_phys, - mhi_cntrl->cmd_ctx_host_pa, mhi_cntrl->cmd_ctx_host_size); - if (ret) { - dev_err(dev, "Failed to map cmd_ctx_cache\n"); - goto err_cmd_ctx; ->>>>>>> - } - - /* Initialize command ring */ - ret = mhi_ep_ring_start(mhi_cntrl, &mhi_cntrl->mhi_cmd->ring, - (union mhi_ep_ring_ctx *)mhi_cntrl->cmd_ctx_cache); - if (ret) { - dev_err(dev, "Failed to start the command ring\n"); -<<<<<<< - goto err_cmd_ctx; -======= - goto err_cmd_ctx_map; ->>>>>>> - } - - return ret; - -<<<<<<< -err_cmd_ctx: - mhi_ep_unmap_free(mhi_cntrl, mhi_cntrl->cmd_ctx_host_pa, mhi_cntrl->cmd_ctx_cache_phys, - mhi_cntrl->cmd_ctx_cache, mhi_cntrl->cmd_ctx_host_size); - -err_ev_ctx: - mhi_ep_unmap_free(mhi_cntrl, mhi_cntrl->ev_ctx_host_pa, mhi_cntrl->ev_ctx_cache_phys, - mhi_cntrl->ev_ctx_cache, mhi_cntrl->ev_ctx_host_size); - -err_ch_ctx: - mhi_ep_unmap_free(mhi_cntrl, mhi_cntrl->ch_ctx_host_pa, mhi_cntrl->ch_ctx_cache_phys, - mhi_cntrl->ch_ctx_cache, mhi_cntrl->ch_ctx_host_size); -======= -err_cmd_ctx_map: - mhi_cntrl->unmap_addr(mhi_cntrl, mhi_cntrl->cmd_ctx_cache_phys); - -err_cmd_ctx: - mhi_cntrl->free_addr(mhi_cntrl, mhi_cntrl->cmd_ctx_cache_phys, - mhi_cntrl->cmd_ctx_cache, mhi_cntrl->cmd_ctx_host_size); - -err_ev_ctx_map: - mhi_cntrl->unmap_addr(mhi_cntrl, mhi_cntrl->ev_ctx_cache_phys); - -err_ev_ctx: - mhi_cntrl->free_addr(mhi_cntrl, mhi_cntrl->ev_ctx_cache_phys, - mhi_cntrl->ev_ctx_cache, mhi_cntrl->ev_ctx_host_size); - -err_ch_ctx_map: - mhi_cntrl->unmap_addr(mhi_cntrl, mhi_cntrl->ch_ctx_cache_phys); - -err_ch_ctx: - mhi_cntrl->free_addr(mhi_cntrl, mhi_cntrl->ch_ctx_cache_phys, - mhi_cntrl->ch_ctx_cache, mhi_cntrl->ch_ctx_host_size); ->>>>>>> - - return ret; -} - -static void mhi_ep_free_host_cfg(struct mhi_ep_cntrl *mhi_cntrl) -{ -<<<<<<< - mhi_cntrl->unmap_addr(mhi_cntrl, mhi_cntrl->cmd_ctx_cache_phys); - mhi_cntrl->free_addr(mhi_cntrl, mhi_cntrl->cmd_ctx_cache_phys, - mhi_cntrl->cmd_ctx_cache, mhi_cntrl->cmd_ctx_host_size); - mhi_cntrl->unmap_addr(mhi_cntrl, mhi_cntrl->ev_ctx_cache_phys); - mhi_cntrl->free_addr(mhi_cntrl, mhi_cntrl->ev_ctx_cache_phys, - mhi_cntrl->ev_ctx_cache, mhi_cntrl->ev_ctx_host_size); - mhi_cntrl->unmap_addr(mhi_cntrl, mhi_cntrl->ch_ctx_cache_phys); - mhi_cntrl->free_addr(mhi_cntrl, mhi_cntrl->ch_ctx_cache_phys, - mhi_cntrl->ch_ctx_cache, mhi_cntrl->ch_ctx_host_size); -======= - mhi_ep_unmap_free(mhi_cntrl, mhi_cntrl->cmd_ctx_host_pa, mhi_cntrl->cmd_ctx_cache_phys, - mhi_cntrl->cmd_ctx_cache, mhi_cntrl->cmd_ctx_host_size); - mhi_ep_unmap_free(mhi_cntrl, mhi_cntrl->ev_ctx_host_pa, mhi_cntrl->ev_ctx_cache_phys, - mhi_cntrl->ev_ctx_cache, mhi_cntrl->ev_ctx_host_size); - mhi_ep_unmap_free(mhi_cntrl, mhi_cntrl->ch_ctx_host_pa, mhi_cntrl->ch_ctx_cache_phys, - mhi_cntrl->ch_ctx_cache, mhi_cntrl->ch_ctx_host_size); ->>>>>>> -} - -static void mhi_ep_enable_int(struct mhi_ep_cntrl *mhi_cntrl) -{ -<<<<<<< -======= - mhi_ep_mmio_enable_chdb_interrupts(mhi_cntrl); ->>>>>>> - mhi_ep_mmio_enable_ctrl_interrupt(mhi_cntrl); - mhi_ep_mmio_enable_cmdb_interrupt(mhi_cntrl); -} - -static int mhi_ep_enable(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - enum mhi_state state; - u32 max_cnt = 0; - bool mhi_reset; - int ret; - - /* Wait for Host to set the M0 state */ - do { - msleep(MHI_SUSPEND_MIN); - mhi_ep_mmio_get_mhi_state(mhi_cntrl, &state, &mhi_reset); - if (mhi_reset) { - /* Clear the MHI reset if host is in reset state */ - mhi_ep_mmio_clear_reset(mhi_cntrl); - dev_dbg(dev, "Host initiated reset while waiting for M0\n"); - } - max_cnt++; - } while (state != MHI_STATE_M0 && max_cnt < MHI_SUSPEND_TIMEOUT); - - if (state == MHI_STATE_M0) { - ret = mhi_ep_cache_host_cfg(mhi_cntrl); - if (ret) { - dev_err(dev, "Failed to cache host config\n"); - return ret; - } - - mhi_ep_mmio_set_env(mhi_cntrl, MHI_EP_AMSS_EE); - } else { - dev_err(dev, "Host failed to enter M0\n"); - return -ETIMEDOUT; - } - - /* Enable all interrupts now */ - mhi_ep_enable_int(mhi_cntrl); - - return 0; -} - -static void mhi_ep_ring_worker(struct work_struct *work) -{ - struct mhi_ep_cntrl *mhi_cntrl = container_of(work, - struct mhi_ep_cntrl, ring_work); - struct device *dev = &mhi_cntrl->mhi_dev->dev; -<<<<<<< - struct mhi_ep_ring *ring; - struct list_head *cp, *q; - unsigned long flags; - int ret = 0; -======= - struct mhi_ep_ring_item *itr, *tmp; - struct mhi_ep_ring *ring; - struct mhi_ep_chan *chan; - unsigned long flags; - LIST_HEAD(head); - int ret; ->>>>>>> - - /* Process the command ring first */ - ret = mhi_ep_process_ring(&mhi_cntrl->mhi_cmd->ring); - if (ret) { -<<<<<<< - dev_err(dev, "Error processing command ring: %d\n", ret); - return; - } - - spin_lock_irqsave(&mhi_cntrl->list_lock, flags); - list_splice_tail_init(&mhi_cntrl->ch_db_list, &head); - spin_unlock_irqrestore(&mhi_cntrl->list_lock, flags); - - /* Process the channel rings now */ - list_for_each_entry_safe(itr, tmp, &head, node) { - list_del(&itr->node); - ring = itr->ring; - chan = &mhi_cntrl->mhi_chan[ring->ch_id]; - mutex_lock(&chan->lock); - dev_dbg(dev, "Processing the ring for channel (%d)\n", ring->ch_id); - ret = mhi_ep_process_ring(ring); - if (ret) { - dev_err(dev, "Error processing ring for channel (%d): %d\n", - ring->ch_id, ret); - mutex_unlock(&chan->lock); - return; - } - mutex_unlock(&chan->lock); - kfree(itr); - } -======= - dev_err(dev, "Error processing command ring\n"); - goto err_unlock; - } - - spin_lock_irqsave(&mhi_cntrl->transition_lock, flags); - /* Process the channel rings now */ - list_for_each_safe(cp, q, &mhi_cntrl->ring_transition_list) { - ring = list_entry(cp, struct mhi_ep_ring, list); - list_del(cp); - ret = mhi_ep_process_ring(ring); - if (ret) { - dev_err(dev, "Error processing channel ring: %d\n", ring->ch_id); - goto err_unlock; - } - - /* Re-enable channel interrupt */ - mhi_ep_mmio_enable_chdb_a7(mhi_cntrl, ring->ch_id); - } - -err_unlock: - spin_unlock_irqrestore(&mhi_cntrl->transition_lock, flags); ->>>>>>> -} - -static void mhi_ep_queue_channel_db(struct mhi_ep_cntrl *mhi_cntrl, - unsigned long ch_int, u32 ch_idx) -{ -<<<<<<< -======= - struct device *dev = &mhi_cntrl->mhi_dev->dev; - struct mhi_ep_ring_item *item; ->>>>>>> - struct mhi_ep_ring *ring; - unsigned int i; - - for_each_set_bit(i, &ch_int, 32) { - /* Channel index varies for each register: 0, 32, 64, 96 */ - i += ch_idx; - ring = &mhi_cntrl->mhi_chan[i].ring; - -<<<<<<< - item = kmalloc(sizeof(*item), GFP_ATOMIC); - item->ring = ring; - - dev_dbg(dev, "Queuing doorbell interrupt for channel (%d)\n", i); - spin_lock(&mhi_cntrl->list_lock); - list_add_tail(&item->node, &mhi_cntrl->ch_db_list); - spin_unlock(&mhi_cntrl->list_lock); - -======= - spin_lock(&mhi_cntrl->transition_lock); - list_add(&ring->list, &mhi_cntrl->ring_transition_list); - spin_unlock(&mhi_cntrl->transition_lock); - /* - * Disable the channel interrupt here and enable it once - * the current interrupt got serviced - */ - mhi_ep_mmio_disable_chdb_a7(mhi_cntrl, i); ->>>>>>> - queue_work(mhi_cntrl->ring_wq, &mhi_cntrl->ring_work); - } -} - -/* - * Channel interrupt statuses are contained in 4 registers each of 32bit length. - * For checking all interrupts, we need to loop through each registers and then - * check for bits set. - */ -static void mhi_ep_check_channel_interrupt(struct mhi_ep_cntrl *mhi_cntrl) -{ -<<<<<<< -======= - struct device *dev = &mhi_cntrl->mhi_dev->dev; ->>>>>>> - u32 ch_int, ch_idx; - int i; - - mhi_ep_mmio_read_chdb_status_interrupts(mhi_cntrl); - - for (i = 0; i < MHI_MASK_ROWS_CH_EV_DB; i++) { - ch_idx = i * MHI_MASK_CH_EV_LEN; - - /* Only process channel interrupt if the mask is enabled */ - ch_int = (mhi_cntrl->chdb[i].status & mhi_cntrl->chdb[i].mask); - if (ch_int) { -<<<<<<< -======= - dev_dbg(dev, "Processing channel doorbell interrupt\n"); ->>>>>>> - mhi_ep_queue_channel_db(mhi_cntrl, ch_int, ch_idx); - mhi_ep_mmio_write(mhi_cntrl, MHI_CHDB_INT_CLEAR_A7_n(i), - mhi_cntrl->chdb[i].status); - } - } -} - -<<<<<<< -static void mhi_ep_state_worker(struct work_struct *work) -======= -void mhi_ep_state_worker(struct work_struct *work) ->>>>>>> -{ - struct mhi_ep_cntrl *mhi_cntrl = container_of(work, struct mhi_ep_cntrl, state_work); - struct device *dev = &mhi_cntrl->mhi_dev->dev; - struct mhi_ep_state_transition *itr, *tmp; - unsigned long flags; - LIST_HEAD(head); - int ret; - -<<<<<<< - spin_lock_irqsave(&mhi_cntrl->list_lock, flags); - list_splice_tail_init(&mhi_cntrl->st_transition_list, &head); - spin_unlock_irqrestore(&mhi_cntrl->list_lock, flags); -======= - spin_lock_irqsave(&mhi_cntrl->transition_lock, flags); - list_splice_tail_init(&mhi_cntrl->st_transition_list, &head); - spin_unlock_irqrestore(&mhi_cntrl->transition_lock, flags); ->>>>>>> - - list_for_each_entry_safe(itr, tmp, &head, node) { - list_del(&itr->node); - dev_dbg(dev, "Handling MHI state transition to %s\n", -<<<<<<< - TO_MHI_STATE_STR(itr->state)); -======= - mhi_state_str(itr->state)); ->>>>>>> - - switch (itr->state) { - case MHI_STATE_M0: - ret = mhi_ep_set_m0_state(mhi_cntrl); - if (ret) - dev_err(dev, "Failed to transition to M0 state\n"); - break; - case MHI_STATE_M3: - ret = mhi_ep_set_m3_state(mhi_cntrl); - if (ret) - dev_err(dev, "Failed to transition to M3 state\n"); - break; - default: -<<<<<<< - dev_err(dev, "Invalid MHI state transition: %d", itr->state); - break; - } -======= - dev_err(dev, "Invalid MHI state transition: %d\n", itr->state); - break; - } - kfree(itr); ->>>>>>> - } -} - -static void mhi_ep_process_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl, - enum mhi_state state) -{ - struct mhi_ep_state_transition *item = kmalloc(sizeof(*item), GFP_ATOMIC); - - item->state = state; -<<<<<<< - spin_lock(&mhi_cntrl->list_lock); - list_add_tail(&item->node, &mhi_cntrl->st_transition_list); - spin_unlock(&mhi_cntrl->list_lock); -======= - spin_lock(&mhi_cntrl->transition_lock); - list_add_tail(&item->node, &mhi_cntrl->st_transition_list); - spin_unlock(&mhi_cntrl->transition_lock); ->>>>>>> - - queue_work(mhi_cntrl->state_wq, &mhi_cntrl->state_work); -} - -<<<<<<< -======= -static void mhi_ep_abort_transfer(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct mhi_ep_ring *ch_ring, *ev_ring; - struct mhi_result result = {}; - struct mhi_ep_chan *mhi_chan; - int i; - - /* Stop all the channels */ - for (i = 0; i < mhi_cntrl->max_chan; i++) { - ch_ring = &mhi_cntrl->mhi_chan[i].ring; - if (ch_ring->state == RING_STATE_UINT) - continue; - - mhi_chan = &mhi_cntrl->mhi_chan[i]; - mutex_lock(&mhi_chan->lock); - /* Send channel disconnect status to client drivers */ - if (mhi_chan->xfer_cb) { - result.transaction_status = -ENOTCONN; - result.bytes_xferd = 0; - mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); - } - - /* Set channel state to DISABLED */ - mhi_chan->state = MHI_CH_STATE_DISABLED; - mutex_unlock(&mhi_chan->lock); - } - - flush_workqueue(mhi_cntrl->ring_wq); - flush_workqueue(mhi_cntrl->state_wq); - - /* Destroy devices associated with all channels */ - device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_ep_destroy_device); - - /* Stop and reset the transfer rings */ - for (i = 0; i < mhi_cntrl->max_chan; i++) { - ch_ring = &mhi_cntrl->mhi_chan[i].ring; - if (ch_ring->state == RING_STATE_UINT) - continue; - - mhi_chan = &mhi_cntrl->mhi_chan[i]; - mutex_lock(&mhi_chan->lock); - mhi_ep_ring_stop(mhi_cntrl, ch_ring); - mutex_unlock(&mhi_chan->lock); - } - - /* Stop and reset the event rings */ - for (i = 0; i < mhi_cntrl->event_rings; i++) { - ev_ring = &mhi_cntrl->mhi_event[i].ring; - if (ev_ring->state == RING_STATE_UINT) - continue; - - mutex_lock(&mhi_cntrl->event_lock); - mhi_ep_ring_stop(mhi_cntrl, ev_ring); - mutex_unlock(&mhi_cntrl->event_lock); - } - - /* Stop and reset the command ring */ - mhi_ep_ring_stop(mhi_cntrl, &mhi_cntrl->mhi_cmd->ring); - - mhi_ep_free_host_cfg(mhi_cntrl); - mhi_ep_mmio_mask_interrupts(mhi_cntrl); - - mhi_cntrl->is_enabled = false; -} - ->>>>>>> -/* - * Interrupt handler that services interrupts raised by the host writing to - * MHICTRL and Command ring doorbell (CRDB) registers for state change and - * channel interrupts. - */ -static irqreturn_t mhi_ep_irq(int irq, void *data) -{ - struct mhi_ep_cntrl *mhi_cntrl = data; -<<<<<<< - struct device *dev = &mhi_cntrl->mhi_dev->dev; - enum mhi_state state; - u32 int_value; - bool mhi_reset; - - /* Acknowledge the interrupts */ - int_value = mhi_ep_mmio_read(mhi_cntrl, MHI_CTRL_INT_STATUS_A7); -======= - - struct device *dev = &mhi_cntrl->mhi_dev->dev; - enum mhi_state state; - u32 int_value = 0; - bool mhi_reset; - - /* Acknowledge the interrupts */ - mhi_ep_mmio_read(mhi_cntrl, MHI_CTRL_INT_STATUS_A7, &int_value); ->>>>>>> - mhi_ep_mmio_write(mhi_cntrl, MHI_CTRL_INT_CLEAR_A7, int_value); - - /* Check for ctrl interrupt */ - if (FIELD_GET(MHI_CTRL_INT_STATUS_A7_MSK, int_value)) { - dev_dbg(dev, "Processing ctrl interrupt\n"); - mhi_ep_mmio_get_mhi_state(mhi_cntrl, &state, &mhi_reset); - if (mhi_reset) { - dev_info(dev, "Host triggered MHI reset!\n"); - disable_irq_nosync(mhi_cntrl->irq); - schedule_work(&mhi_cntrl->reset_work); - return IRQ_HANDLED; - } - - mhi_ep_process_ctrl_interrupt(mhi_cntrl, state); - } - - /* Check for command doorbell interrupt */ - if (FIELD_GET(MHI_CTRL_INT_STATUS_CRDB_MSK, int_value)) { - dev_dbg(dev, "Processing command doorbell interrupt\n"); - queue_work(mhi_cntrl->ring_wq, &mhi_cntrl->ring_work); - } - - /* Check for channel interrupts */ - mhi_ep_check_channel_interrupt(mhi_cntrl); - - return IRQ_HANDLED; -} - -<<<<<<< -static void mhi_ep_abort_transfer(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct mhi_ep_ring *ch_ring, *ev_ring; - struct mhi_result result = {}; - struct mhi_ep_chan *mhi_chan; - int i; - - /* Stop all the channels */ - for (i = 0; i < mhi_cntrl->max_chan; i++) { - ch_ring = &mhi_cntrl->mhi_chan[i].ring; - if (!ch_ring->started) - continue; - - mhi_chan = &mhi_cntrl->mhi_chan[i]; - mutex_lock(&mhi_chan->lock); - /* Send channel disconnect status to client drivers */ - if (mhi_chan->xfer_cb) { - result.transaction_status = -ENOTCONN; - result.bytes_xferd = 0; - mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); - } - - /* Set channel state to DISABLED */ - mhi_chan->state = MHI_CH_STATE_DISABLED; - mutex_unlock(&mhi_chan->lock); - } - - flush_workqueue(mhi_cntrl->ring_wq); - flush_workqueue(mhi_cntrl->state_wq); - - /* Destroy devices associated with all channels */ - device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_ep_destroy_device); - - /* Stop and reset the transfer rings */ - for (i = 0; i < mhi_cntrl->max_chan; i++) { - ch_ring = &mhi_cntrl->mhi_chan[i].ring; - if (!ch_ring->started) - continue; - - mhi_chan = &mhi_cntrl->mhi_chan[i]; - mutex_lock(&mhi_chan->lock); - mhi_ep_ring_reset(mhi_cntrl, ch_ring); - mutex_unlock(&mhi_chan->lock); - } - - /* Stop and reset the event rings */ - for (i = 0; i < mhi_cntrl->event_rings; i++) { - ev_ring = &mhi_cntrl->mhi_event[i].ring; - if (!ev_ring->started) - continue; - - mutex_lock(&mhi_cntrl->event_lock); - mhi_ep_ring_reset(mhi_cntrl, ev_ring); - mutex_unlock(&mhi_cntrl->event_lock); - } - - /* Stop and reset the command ring */ - mhi_ep_ring_reset(mhi_cntrl, &mhi_cntrl->mhi_cmd->ring); - - mhi_ep_free_host_cfg(mhi_cntrl); - mhi_ep_mmio_mask_interrupts(mhi_cntrl); - - mhi_cntrl->is_enabled = false; -} - -static void mhi_ep_reset_worker(struct work_struct *work) -======= -void mhi_ep_reset_worker(struct work_struct *work) ->>>>>>> -{ - struct mhi_ep_cntrl *mhi_cntrl = container_of(work, struct mhi_ep_cntrl, reset_work); - struct device *dev = &mhi_cntrl->mhi_dev->dev; - enum mhi_state cur_state; - int ret; - - mhi_ep_abort_transfer(mhi_cntrl); - - spin_lock_bh(&mhi_cntrl->state_lock); - /* Reset MMIO to signal host that the MHI_RESET is completed in endpoint */ - mhi_ep_mmio_reset(mhi_cntrl); - cur_state = mhi_cntrl->mhi_state; - spin_unlock_bh(&mhi_cntrl->state_lock); - - /* - * Only proceed further if the reset is due to SYS_ERR. The host will - * issue reset during shutdown also and we don't need to do re-init in - * that case. - */ - if (cur_state == MHI_STATE_SYS_ERR) { - mhi_ep_mmio_init(mhi_cntrl); - - /* Set AMSS EE before signaling ready state */ - mhi_ep_mmio_set_env(mhi_cntrl, MHI_EP_AMSS_EE); - - /* All set, notify the host that we are ready */ - ret = mhi_ep_set_ready_state(mhi_cntrl); - if (ret) - return; - - dev_dbg(dev, "READY state notification sent to the host\n"); - - ret = mhi_ep_enable(mhi_cntrl); - if (ret) { - dev_err(dev, "Failed to enable MHI endpoint: %d\n", ret); - return; - } - - enable_irq(mhi_cntrl->irq); - } -} - -<<<<<<< -/* - * We don't need to do anything special other than setting the MHI SYS_ERR - * state. The host issue will reset all contexts and issue MHI RESET so that we - * could also recover from error state. - */ -void mhi_ep_handle_syserr(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - int ret; - - /* If MHI EP is not enabled, nothing to do */ - if (!mhi_cntrl->is_enabled) - return; - - ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR); - if (ret) - return; - - /* Signal host that the device went to SYS_ERR state */ - ret = mhi_ep_send_state_change_event(mhi_cntrl, MHI_STATE_SYS_ERR); - if (ret) - dev_err(dev, "Failed sending SYS_ERR state change event: %d\n", ret); -} - -int mhi_ep_power_up(struct mhi_ep_cntrl *mhi_cntrl) -{ -======= -void mhi_ep_init_worker(struct work_struct *work) -{ - struct mhi_ep_cntrl *mhi_cntrl = container_of(work, struct mhi_ep_cntrl, init_work); ->>>>>>> - struct device *dev = &mhi_cntrl->mhi_dev->dev; - int ret, i; - - /* - * Mask all interrupts until the state machine is ready. Interrupts will - * be enabled later with mhi_ep_enable(). - */ - mhi_ep_mmio_mask_interrupts(mhi_cntrl); - mhi_ep_mmio_init(mhi_cntrl); - - mhi_cntrl->mhi_event = kzalloc(mhi_cntrl->event_rings * (sizeof(*mhi_cntrl->mhi_event)), -<<<<<<< - GFP_KERNEL); - if (!mhi_cntrl->mhi_event) - return -ENOMEM; -======= - GFP_KERNEL); - if (!mhi_cntrl->mhi_event) - return; ->>>>>>> - - /* Initialize command, channel and event rings */ - mhi_ep_ring_init(&mhi_cntrl->mhi_cmd->ring, RING_TYPE_CMD, 0); - for (i = 0; i < mhi_cntrl->max_chan; i++) - mhi_ep_ring_init(&mhi_cntrl->mhi_chan[i].ring, RING_TYPE_CH, i); - for (i = 0; i < mhi_cntrl->event_rings; i++) - mhi_ep_ring_init(&mhi_cntrl->mhi_event[i].ring, RING_TYPE_ER, i); - - spin_lock_bh(&mhi_cntrl->state_lock); - mhi_cntrl->mhi_state = MHI_STATE_RESET; - spin_unlock_bh(&mhi_cntrl->state_lock); - - /* Set AMSS EE before signaling ready state */ - mhi_ep_mmio_set_env(mhi_cntrl, MHI_EP_AMSS_EE); - - /* All set, notify the host that we are ready */ - ret = mhi_ep_set_ready_state(mhi_cntrl); - if (ret) - goto err_free_event; - - dev_dbg(dev, "READY state notification sent to the host\n"); - - ret = mhi_ep_enable(mhi_cntrl); - if (ret) { -<<<<<<< - dev_err(dev, "Failed to enable MHI endpoint: %d\n", ret); -======= - dev_err(dev, "Failed to enable MHI endpoint\n"); ->>>>>>> - goto err_free_event; - } - - enable_irq(mhi_cntrl->irq); -<<<<<<< - mhi_cntrl->is_enabled = true; - - return 0; - -err_free_event: - kfree(mhi_cntrl->mhi_event); - - return ret; -} -EXPORT_SYMBOL_GPL(mhi_ep_power_up); -======= - - return; - -err_free_event: - kfree(mhi_cntrl->mhi_event); -} - -static void skip_to_next_td(struct mhi_ep_chan *mhi_chan, struct mhi_ep_ring *ring) -{ - struct mhi_ep_ring_element *el; - u32 td_boundary_reached = 0; - - mhi_chan->skip_td = 1; - el = &ring->ring_cache[ring->rd_offset]; - while (ring->rd_offset != ring->wr_offset) { - if (td_boundary_reached) { - mhi_chan->skip_td = 0; - break; - } - - if (!MHI_EP_TRE_GET_CHAIN(el)) - td_boundary_reached = 1; - - mhi_ep_ring_inc_index(ring); - el = &ring->ring_cache[ring->rd_offset]; - } -} - -bool mhi_ep_queue_is_empty(struct mhi_ep_device *mhi_dev, enum dma_data_direction dir) -{ - struct mhi_ep_chan *mhi_chan = (dir == DMA_FROM_DEVICE) ? mhi_dev->dl_chan : - mhi_dev->ul_chan; - struct mhi_ep_cntrl *mhi_cntrl = mhi_dev->mhi_cntrl; - struct mhi_ep_ring *ring = &mhi_cntrl->mhi_chan[mhi_chan->chan].ring; - - return !!(ring->rd_offset == ring->wr_offset); -} -EXPORT_SYMBOL_GPL(mhi_ep_queue_is_empty); - -int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, enum dma_data_direction dir, - struct sk_buff *skb, size_t len, enum mhi_flags mflags) -{ - struct mhi_ep_chan *mhi_chan = (dir == DMA_FROM_DEVICE) ? mhi_dev->dl_chan : - mhi_dev->ul_chan; - size_t usr_buf_offset, bytes_to_write; - struct mhi_ep_cntrl *mhi_cntrl = mhi_dev->mhi_cntrl; - struct device *dev = &mhi_cntrl->mhi_dev->dev; - enum mhi_ev_ccs code = MHI_EV_CC_INVALID; - u64 write_to_loc, skip_tre = 0; - struct mhi_ep_ring_element *el; - struct mhi_ep_ring *ring; - u32 buf_remaining; - void *read_from_loc; - void __iomem *tre_buf; - phys_addr_t tre_phys; - u32 tre_len; - int ret = 0; - - if (dir == DMA_TO_DEVICE) - return -EINVAL; - - buf_remaining = len; - ring = &mhi_cntrl->mhi_chan[mhi_chan->chan].ring; - - mutex_lock(&mhi_chan->lock); - if (mhi_chan->skip_td) - skip_to_next_td(mhi_chan, ring); - - do { - /* Don't process the transfer ring if the channel is not in RUNNING state */ - if (mhi_chan->state != MHI_CH_STATE_RUNNING) { - dev_err(dev, "Channel (%d) not available", mhi_chan->chan); - ret = -ENODEV; - goto err_exit; - } - - if (mhi_ep_queue_is_empty(mhi_dev, dir)) { - dev_err(dev, "TRE not available!\n"); - ret = -EINVAL; - goto err_exit; - } - - el = &ring->ring_cache[ring->rd_offset]; - tre_len = MHI_EP_TRE_GET_LEN(el); - if (skb->len > tre_len) { - dev_err(dev, "Buffer size (%d) is too large for TRE length (%d)!\n", - skb->len, tre_len); - ret = -ENOMEM; - goto err_exit; - } - - bytes_to_write = min(buf_remaining, tre_len); - usr_buf_offset = skb->len - bytes_to_write; - read_from_loc = skb->data; - write_to_loc = MHI_EP_TRE_GET_PTR(el); - - tre_buf = mhi_cntrl->alloc_addr(mhi_cntrl, &tre_phys, bytes_to_write); - if (!tre_buf) { - dev_err(dev, "Failed to allocate TRE buffer\n"); - ret = -ENOMEM; - goto err_exit; - } - - ret = mhi_cntrl->map_addr(mhi_cntrl, tre_phys, write_to_loc, bytes_to_write); - if (ret) { - dev_err(dev, "Failed to map TRE buffer\n"); - goto err_tre_free; - } - - dev_dbg(dev, "Writing %d bytes to channel (%d)", bytes_to_write, ring->ch_id); - memcpy_toio(tre_buf, read_from_loc, bytes_to_write); - - mhi_cntrl->unmap_addr(mhi_cntrl, tre_phys); - mhi_cntrl->free_addr(mhi_cntrl, tre_phys, tre_buf, bytes_to_write); - - buf_remaining -= bytes_to_write; - if (buf_remaining) { - if (!MHI_EP_TRE_GET_CHAIN(el)) - code = MHI_EV_CC_OVERFLOW; - else if (MHI_EP_TRE_GET_IEOB(el)) - code = MHI_EV_CC_EOB; - } else { - if (MHI_EP_TRE_GET_CHAIN(el)) - skip_tre = 1; - code = MHI_EV_CC_EOT; - } - - ret = mhi_ep_send_completion_event(mhi_cntrl, ring, bytes_to_write, code); - if (ret) { - dev_err(dev, "Error sending completion event for channel (%d)\n", - ring->ch_id); - goto err_exit; - } - - mhi_ep_ring_inc_index(ring); - } while (!skip_tre && buf_remaining); - - if (skip_tre) - skip_to_next_td(mhi_chan, ring); - - mutex_unlock(&mhi_chan->lock); - - return 0; - -err_tre_free: - mhi_cntrl->free_addr(mhi_cntrl, tre_phys, tre_buf, bytes_to_write); -err_exit: - mutex_unlock(&mhi_chan->lock); - - return ret; -} -EXPORT_SYMBOL_GPL(mhi_ep_queue_skb); ->>>>>>> - -void mhi_ep_power_down(struct mhi_ep_cntrl *mhi_cntrl) -{ - if (mhi_cntrl->is_enabled) - mhi_ep_abort_transfer(mhi_cntrl); -<<<<<<< -======= - - kfree(mhi_cntrl->mhi_event); ->>>>>>> - disable_irq(mhi_cntrl->irq); -} -EXPORT_SYMBOL_GPL(mhi_ep_power_down); - -<<<<<<< -void mhi_ep_power_up(struct mhi_ep_cntrl *mhi_cntrl) -{ - schedule_work(&mhi_cntrl->init_work); - mhi_cntrl->is_enabled = true; -} -EXPORT_SYMBOL_GPL(mhi_ep_power_up); -======= -void mhi_ep_suspend_channels(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct mhi_ep_chan *mhi_chan; - u32 tmp; - int i; - - for (i = 0; i < mhi_cntrl->max_chan; i++) { - mhi_chan = &mhi_cntrl->mhi_chan[i]; - - if (!mhi_chan->mhi_dev) - continue; - - mutex_lock(&mhi_chan->lock); - /* Skip if the channel is not currently running */ - tmp = le32_to_cpu(mhi_cntrl->ch_ctx_cache[i].chcfg); - if (FIELD_GET(CHAN_CTX_CHSTATE_MASK, tmp) != MHI_CH_STATE_RUNNING) { - mutex_unlock(&mhi_chan->lock); - continue; - } - - dev_dbg(&mhi_chan->mhi_dev->dev, "Suspending channel\n"); - /* Set channel state to SUSPENDED */ - tmp &= ~CHAN_CTX_CHSTATE_MASK; - tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_SUSPENDED); - mhi_cntrl->ch_ctx_cache[i].chcfg = cpu_to_le32(tmp); - mutex_unlock(&mhi_chan->lock); - } -} - -void mhi_ep_resume_channels(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct mhi_ep_chan *mhi_chan; - u32 tmp; - int i; - - for (i = 0; i < mhi_cntrl->max_chan; i++) { - mhi_chan = &mhi_cntrl->mhi_chan[i]; - - if (!mhi_chan->mhi_dev) - continue; - - mutex_lock(&mhi_chan->lock); - /* Skip if the channel is not currently suspended */ - tmp = le32_to_cpu(mhi_cntrl->ch_ctx_cache[i].chcfg); - if (FIELD_GET(CHAN_CTX_CHSTATE_MASK, tmp) != MHI_CH_STATE_SUSPENDED) { - mutex_unlock(&mhi_chan->lock); - continue; - } - - dev_dbg(&mhi_chan->mhi_dev->dev, "Resuming channel\n"); - /* Set channel state to RUNNING */ - tmp &= ~CHAN_CTX_CHSTATE_MASK; - tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_RUNNING); - mhi_cntrl->ch_ctx_cache[i].chcfg = cpu_to_le32(tmp); - mutex_unlock(&mhi_chan->lock); - } -} ->>>>>>> - -static void mhi_ep_release_device(struct device *dev) -{ - struct mhi_ep_device *mhi_dev = to_mhi_ep_device(dev); - -<<<<<<< - /* - * We need to set the mhi_chan->mhi_dev to NULL here since the MHI - * devices for the channels will only get created if the mhi_dev - * associated with it is NULL. -======= - if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER) - mhi_dev->mhi_cntrl->mhi_dev = NULL; - - /* - * We need to set the mhi_chan->mhi_dev to NULL here since the MHI - * devices for the channels will only get created during start - * channel if the mhi_dev associated with it is NULL. ->>>>>>> - */ - if (mhi_dev->ul_chan) - mhi_dev->ul_chan->mhi_dev = NULL; - - if (mhi_dev->dl_chan) - mhi_dev->dl_chan->mhi_dev = NULL; - - kfree(mhi_dev); -} - -<<<<<<< -static struct mhi_ep_device *mhi_ep_alloc_device(struct mhi_ep_cntrl *mhi_cntrl, - enum mhi_device_type dev_type) -======= -struct mhi_ep_device *mhi_ep_alloc_device(struct mhi_ep_cntrl *mhi_cntrl) ->>>>>>> -{ - struct mhi_ep_device *mhi_dev; - struct device *dev; - - mhi_dev = kzalloc(sizeof(*mhi_dev), GFP_KERNEL); - if (!mhi_dev) - return ERR_PTR(-ENOMEM); - - dev = &mhi_dev->dev; - device_initialize(dev); - dev->bus = &mhi_ep_bus_type; - dev->release = mhi_ep_release_device; - -<<<<<<< - if (dev_type == MHI_DEVICE_CONTROLLER) - /* for MHI controller device, parent is the bus device (e.g. PCI EPF) */ - dev->parent = mhi_cntrl->cntrl_dev; - else - /* for MHI client devices, parent is the MHI controller device */ - dev->parent = &mhi_cntrl->mhi_dev->dev; - - mhi_dev->mhi_cntrl = mhi_cntrl; - mhi_dev->dev_type = dev_type; -======= - if (mhi_cntrl->mhi_dev) { - /* for MHI client devices, parent is the MHI controller device */ - dev->parent = &mhi_cntrl->mhi_dev->dev; - } else { - /* for MHI controller device, parent is the bus device (e.g. PCI EPF) */ - dev->parent = mhi_cntrl->cntrl_dev; - } - - mhi_dev->mhi_cntrl = mhi_cntrl; ->>>>>>> - - return mhi_dev; -} - -<<<<<<< -/* - * MHI channels are always defined in pairs with UL as the even numbered - * channel and DL as odd numbered one. - */ -static int mhi_ep_create_device(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id) -{ - struct mhi_ep_chan *mhi_chan = &mhi_cntrl->mhi_chan[ch_id]; - struct mhi_ep_device *mhi_dev; - int ret; - - /* Check if the channel name is same for both UL and DL */ - if (strcmp(mhi_chan->name, mhi_chan[1].name)) - return -EINVAL; - - mhi_dev = mhi_ep_alloc_device(mhi_cntrl, MHI_DEVICE_XFER); - if (IS_ERR(mhi_dev)) - return PTR_ERR(mhi_dev); - - /* Configure primary channel */ - mhi_dev->ul_chan = mhi_chan; -======= -static int mhi_ep_create_device(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id) -{ - struct mhi_ep_device *mhi_dev; - struct mhi_ep_chan *mhi_chan = &mhi_cntrl->mhi_chan[ch_id]; - int ret; - - mhi_dev = mhi_ep_alloc_device(mhi_cntrl); - if (IS_ERR(mhi_dev)) - return PTR_ERR(mhi_dev); - - mhi_dev->dev_type = MHI_DEVICE_XFER; - - /* Configure primary channel */ - if (mhi_chan->dir == DMA_TO_DEVICE) { - mhi_dev->ul_chan = mhi_chan; - mhi_dev->ul_chan_id = mhi_chan->chan; - } else { - mhi_dev->dl_chan = mhi_chan; - mhi_dev->dl_chan_id = mhi_chan->chan; - } - ->>>>>>> - get_device(&mhi_dev->dev); - mhi_chan->mhi_dev = mhi_dev; - - /* Configure secondary channel as well */ - mhi_chan++; -<<<<<<< - if (mhi_chan->dir == DMA_TO_DEVICE) { - mhi_dev->ul_chan = mhi_chan; - mhi_dev->ul_chan_id = mhi_chan->chan; - } else { - mhi_dev->dl_chan = mhi_chan; - mhi_dev->dl_chan_id = mhi_chan->chan; - } - -======= - mhi_dev->dl_chan = mhi_chan; ->>>>>>> - get_device(&mhi_dev->dev); - mhi_chan->mhi_dev = mhi_dev; - - /* Channel name is same for both UL and DL */ - mhi_dev->name = mhi_chan->name; - dev_set_name(&mhi_dev->dev, "%s_%s", - dev_name(&mhi_cntrl->mhi_dev->dev), - mhi_dev->name); - - ret = device_add(&mhi_dev->dev); - if (ret) - put_device(&mhi_dev->dev); - - return ret; -} - -static int mhi_ep_destroy_device(struct device *dev, void *data) -{ - struct mhi_ep_device *mhi_dev; - struct mhi_ep_cntrl *mhi_cntrl; - struct mhi_ep_chan *ul_chan, *dl_chan; - - if (dev->bus != &mhi_ep_bus_type) - return 0; - - mhi_dev = to_mhi_ep_device(dev); - mhi_cntrl = mhi_dev->mhi_cntrl; - - /* Only destroy devices created for channels */ - if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER) - return 0; - - ul_chan = mhi_dev->ul_chan; - dl_chan = mhi_dev->dl_chan; - - if (ul_chan) - put_device(&ul_chan->mhi_dev->dev); - - if (dl_chan) - put_device(&dl_chan->mhi_dev->dev); - - dev_dbg(&mhi_cntrl->mhi_dev->dev, "Destroying device for chan:%s\n", - mhi_dev->name); - - /* Notify the client and remove the device from MHI bus */ - device_del(dev); - put_device(dev); - - return 0; -} - -static int parse_ch_cfg(struct mhi_ep_cntrl *mhi_cntrl, - const struct mhi_ep_cntrl_config *config) -{ - const struct mhi_ep_channel_config *ch_cfg; - struct device *dev = mhi_cntrl->cntrl_dev; - u32 chan, i; - int ret = -EINVAL; - - mhi_cntrl->max_chan = config->max_channels; - - /* - * Allocate max_channels supported by the MHI endpoint and populate - * only the defined channels - */ - mhi_cntrl->mhi_chan = kcalloc(mhi_cntrl->max_chan, sizeof(*mhi_cntrl->mhi_chan), - GFP_KERNEL); - if (!mhi_cntrl->mhi_chan) - return -ENOMEM; - - for (i = 0; i < config->num_channels; i++) { - struct mhi_ep_chan *mhi_chan; - - ch_cfg = &config->ch_cfg[i]; - - chan = ch_cfg->num; - if (chan >= mhi_cntrl->max_chan) { - dev_err(dev, "Channel %d not available\n", chan); - goto error_chan_cfg; - } - -<<<<<<< -======= - /* Bi-directional and direction less channels are not supported */ - if (ch_cfg->dir == DMA_BIDIRECTIONAL || ch_cfg->dir == DMA_NONE) { - dev_err(dev, "Invalid channel configuration\n"); - goto error_chan_cfg; - } - ->>>>>>> - mhi_chan = &mhi_cntrl->mhi_chan[chan]; - mhi_chan->name = ch_cfg->name; - mhi_chan->chan = chan; - mhi_chan->dir = ch_cfg->dir; - mutex_init(&mhi_chan->lock); -<<<<<<< -======= - - /* Bi-directional and direction less channels are not supported */ - if (mhi_chan->dir == DMA_BIDIRECTIONAL || mhi_chan->dir == DMA_NONE) { - dev_err(dev, "Invalid channel configuration\n"); - goto error_chan_cfg; - } ->>>>>>> - } - - return 0; - -error_chan_cfg: - kfree(mhi_cntrl->mhi_chan); - - return ret; -} - -/* - * Allocate channel and command rings here. Event rings will be allocated -<<<<<<< - * in mhi_ep_init_worker() as the config comes from the host. -======= - * in mhi_ep_power_up() as the config comes from the host. ->>>>>>> - */ -int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl, - const struct mhi_ep_cntrl_config *config) -{ - struct mhi_ep_device *mhi_dev; - int ret; - - if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->mmio || !mhi_cntrl->irq) - return -EINVAL; - - ret = parse_ch_cfg(mhi_cntrl, config); - if (ret) - return ret; - - mhi_cntrl->mhi_cmd = kcalloc(NR_OF_CMD_RINGS, sizeof(*mhi_cntrl->mhi_cmd), GFP_KERNEL); - if (!mhi_cntrl->mhi_cmd) { - ret = -ENOMEM; - goto err_free_ch; - } - - INIT_WORK(&mhi_cntrl->ring_work, mhi_ep_ring_worker); - INIT_WORK(&mhi_cntrl->state_work, mhi_ep_state_worker); -<<<<<<< - INIT_WORK(&mhi_cntrl->init_work, mhi_ep_init_worker); - INIT_WORK(&mhi_cntrl->reset_work, mhi_ep_reset_worker); - - mhi_cntrl->ring_wq = alloc_ordered_workqueue("mhi_ep_ring_wq", WQ_HIGHPRI); -======= - INIT_WORK(&mhi_cntrl->reset_work, mhi_ep_reset_worker); - - mhi_cntrl->ring_wq = alloc_workqueue("mhi_ep_ring_wq", 0, 0); ->>>>>>> - if (!mhi_cntrl->ring_wq) { - ret = -ENOMEM; - goto err_free_cmd; - } - -<<<<<<< - mhi_cntrl->state_wq = alloc_ordered_workqueue("mhi_ep_state_wq", WQ_HIGHPRI); -======= - mhi_cntrl->state_wq = alloc_workqueue("mhi_ep_state_wq", 0, 0); ->>>>>>> - if (!mhi_cntrl->state_wq) { - ret = -ENOMEM; - goto err_destroy_ring_wq; - } - -<<<<<<< - INIT_LIST_HEAD(&mhi_cntrl->ch_db_list); - INIT_LIST_HEAD(&mhi_cntrl->st_transition_list); - spin_lock_init(&mhi_cntrl->list_lock); -======= - INIT_LIST_HEAD(&mhi_cntrl->ring_transition_list); - INIT_LIST_HEAD(&mhi_cntrl->st_transition_list); - spin_lock_init(&mhi_cntrl->transition_lock); ->>>>>>> - spin_lock_init(&mhi_cntrl->state_lock); - mutex_init(&mhi_cntrl->event_lock); - - /* Set MHI version and AMSS EE before enumeration */ - mhi_ep_mmio_write(mhi_cntrl, MHIVER, config->mhi_version); - mhi_ep_mmio_set_env(mhi_cntrl, MHI_EP_AMSS_EE); - - /* Set controller index */ - mhi_cntrl->index = ida_alloc(&mhi_ep_cntrl_ida, GFP_KERNEL); - if (mhi_cntrl->index < 0) { - ret = mhi_cntrl->index; - goto err_destroy_state_wq; - } - - irq_set_status_flags(mhi_cntrl->irq, IRQ_NOAUTOEN); - ret = request_irq(mhi_cntrl->irq, mhi_ep_irq, IRQF_TRIGGER_HIGH, - "doorbell_irq", mhi_cntrl); - if (ret) { -<<<<<<< - dev_err(mhi_cntrl->cntrl_dev, "Failed to request Doorbell IRQ: %d\n", ret); -======= - dev_err(mhi_cntrl->cntrl_dev, "Failed to request Doorbell IRQ\n"); ->>>>>>> - goto err_ida_free; - } - - /* Allocate the controller device */ -<<<<<<< - mhi_dev = mhi_ep_alloc_device(mhi_cntrl); -======= - mhi_dev = mhi_ep_alloc_device(mhi_cntrl, MHI_DEVICE_CONTROLLER); ->>>>>>> - if (IS_ERR(mhi_dev)) { - dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate controller device\n"); - ret = PTR_ERR(mhi_dev); - goto err_free_irq; - } - -<<<<<<< -======= - mhi_dev->dev_type = MHI_DEVICE_CONTROLLER; ->>>>>>> - dev_set_name(&mhi_dev->dev, "mhi_ep%d", mhi_cntrl->index); - mhi_dev->name = dev_name(&mhi_dev->dev); - - ret = device_add(&mhi_dev->dev); - if (ret) -<<<<<<< - goto err_put_dev; -======= - goto err_release_dev; ->>>>>>> - - mhi_cntrl->mhi_dev = mhi_dev; - - dev_dbg(&mhi_dev->dev, "MHI EP Controller registered\n"); - - return 0; - -<<<<<<< -err_put_dev: -======= -err_release_dev: ->>>>>>> - put_device(&mhi_dev->dev); -err_free_irq: - free_irq(mhi_cntrl->irq, mhi_cntrl); -err_ida_free: - ida_free(&mhi_ep_cntrl_ida, mhi_cntrl->index); -err_destroy_state_wq: - destroy_workqueue(mhi_cntrl->state_wq); -err_destroy_ring_wq: - destroy_workqueue(mhi_cntrl->ring_wq); -err_free_cmd: - kfree(mhi_cntrl->mhi_cmd); -err_free_ch: - kfree(mhi_cntrl->mhi_chan); - - return ret; -} -EXPORT_SYMBOL_GPL(mhi_ep_register_controller); - -/* - * It is expected that the controller drivers will power down the MHI EP stack - * using "mhi_ep_power_down()" before calling this function to unregister themselves. - */ -void mhi_ep_unregister_controller(struct mhi_ep_cntrl *mhi_cntrl) -{ - struct mhi_ep_device *mhi_dev = mhi_cntrl->mhi_dev; - - destroy_workqueue(mhi_cntrl->state_wq); - destroy_workqueue(mhi_cntrl->ring_wq); - - free_irq(mhi_cntrl->irq, mhi_cntrl); - - kfree(mhi_cntrl->mhi_cmd); -<<<<<<< -======= - kfree(mhi_cntrl->mhi_event); ->>>>>>> - kfree(mhi_cntrl->mhi_chan); - - device_del(&mhi_dev->dev); - put_device(&mhi_dev->dev); - - ida_free(&mhi_ep_cntrl_ida, mhi_cntrl->index); -} -EXPORT_SYMBOL_GPL(mhi_ep_unregister_controller); - -static int mhi_ep_driver_probe(struct device *dev) -{ - struct mhi_ep_device *mhi_dev = to_mhi_ep_device(dev); - struct mhi_ep_driver *mhi_drv = to_mhi_ep_driver(dev->driver); - struct mhi_ep_chan *ul_chan = mhi_dev->ul_chan; - struct mhi_ep_chan *dl_chan = mhi_dev->dl_chan; - -<<<<<<< - /* Client drivers should have callbacks for both channels */ - if (!mhi_drv->ul_xfer_cb || !mhi_drv->dl_xfer_cb) - return -EINVAL; - - ul_chan->xfer_cb = mhi_drv->ul_xfer_cb; - dl_chan->xfer_cb = mhi_drv->dl_xfer_cb; -======= - if (ul_chan) - ul_chan->xfer_cb = mhi_drv->ul_xfer_cb; - - if (dl_chan) - dl_chan->xfer_cb = mhi_drv->dl_xfer_cb; ->>>>>>> - - return mhi_drv->probe(mhi_dev, mhi_dev->id); -} - -static int mhi_ep_driver_remove(struct device *dev) -{ - struct mhi_ep_device *mhi_dev = to_mhi_ep_device(dev); - struct mhi_ep_driver *mhi_drv = to_mhi_ep_driver(dev->driver); - struct mhi_result result = {}; - struct mhi_ep_chan *mhi_chan; - int dir; - - /* Skip if it is a controller device */ - if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER) - return 0; - - /* Disconnect the channels associated with the driver */ - for (dir = 0; dir < 2; dir++) { - mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan; - - if (!mhi_chan) - continue; - - mutex_lock(&mhi_chan->lock); - /* Send channel disconnect status to the client driver */ - if (mhi_chan->xfer_cb) { - result.transaction_status = -ENOTCONN; - result.bytes_xferd = 0; - mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); - } - - /* Set channel state to DISABLED */ - mhi_chan->state = MHI_CH_STATE_DISABLED; - mhi_chan->xfer_cb = NULL; - mutex_unlock(&mhi_chan->lock); - } - - /* Remove the client driver now */ - mhi_drv->remove(mhi_dev); - - return 0; -} - -int __mhi_ep_driver_register(struct mhi_ep_driver *mhi_drv, struct module *owner) -{ - struct device_driver *driver = &mhi_drv->driver; - - if (!mhi_drv->probe || !mhi_drv->remove) - return -EINVAL; - - driver->bus = &mhi_ep_bus_type; - driver->owner = owner; - driver->probe = mhi_ep_driver_probe; - driver->remove = mhi_ep_driver_remove; - - return driver_register(driver); -} -EXPORT_SYMBOL_GPL(__mhi_ep_driver_register); - -void mhi_ep_driver_unregister(struct mhi_ep_driver *mhi_drv) -{ - driver_unregister(&mhi_drv->driver); -} -EXPORT_SYMBOL_GPL(mhi_ep_driver_unregister); - -static int mhi_ep_uevent(struct device *dev, struct kobj_uevent_env *env) -{ - struct mhi_ep_device *mhi_dev = to_mhi_ep_device(dev); - - return add_uevent_var(env, "MODALIAS=" MHI_EP_DEVICE_MODALIAS_FMT, - mhi_dev->name); -} - -static int mhi_ep_match(struct device *dev, struct device_driver *drv) -{ - struct mhi_ep_device *mhi_dev = to_mhi_ep_device(dev); - struct mhi_ep_driver *mhi_drv = to_mhi_ep_driver(drv); - const struct mhi_device_id *id; - - /* - * If the device is a controller type then there is no client driver - * associated with it - */ - if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER) - return 0; - - for (id = mhi_drv->id_table; id->chan[0]; id++) - if (!strcmp(mhi_dev->name, id->chan)) { - mhi_dev->id = id; - return 1; - } - - return 0; -}; - -struct bus_type mhi_ep_bus_type = { - .name = "mhi_ep", - .dev_name = "mhi_ep", - .match = mhi_ep_match, - .uevent = mhi_ep_uevent, -}; - -static int __init mhi_ep_init(void) -{ - return bus_register(&mhi_ep_bus_type); -} - -static void __exit mhi_ep_exit(void) -{ - bus_unregister(&mhi_ep_bus_type); -} - -postcore_initcall(mhi_ep_init); -module_exit(mhi_ep_exit); - -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("MHI Bus Endpoint stack"); -MODULE_AUTHOR("Manivannan Sadhasivam "); diff --git a/rr-cache/34e51a35d1bed604fc421929e339a9cda9249811/postimage b/rr-cache/34e51a35d1bed604fc421929e339a9cda9249811/postimage deleted file mode 100644 index cf538f4..0000000 --- a/rr-cache/34e51a35d1bed604fc421929e339a9cda9249811/postimage +++ /dev/null @@ -1,551 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -/dts-v1/; - -#include -#include -#include "sm8150.dtsi" -#include "pmm8155au_1.dtsi" -#include "pmm8155au_2.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SA8155P ADP"; - compatible = "qcom,sa8155p-adp", "qcom,sa8155p"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vreg_3p3: vreg_3p3_regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_3p3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* - * S4A is always on and not controllable through RPMh. - * So model it as a fixed regulator. - */ - vreg_s4a_1p8: smps4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - - vin-supply = <&vreg_3p3>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xC>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; - snps,tx-sched-wrr; - - queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; - }; - - queue1 { - snps,weight = <0x11>; - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue2 { - snps,weight = <0x12>; - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue3 { - snps,weight = <0x13>; - snps,dcb-algorithm; - snps,priority = <0x3>; - }; - }; -}; - -&apps_rsc { - pmm8155au-1-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>; - vdd-l6-l9-supply = <&vreg_s6a_0p92>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s5a_2p04: smps5 { - regulator-name = "vreg_s5a_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6a_0p92: smps6 { - regulator-name = "vreg_s6a_0p92"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1a_0p752: ldo1 { - regulator-name = "vreg_l1a_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_3p1: - vreg_l2a_3p072: ldo2 { - regulator-name = "vreg_l2a_3p072"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p8: ldo3 { - regulator-name = "vreg_l3a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdd_usb_hs_core: - vdda_usb_ss_dp_core_1: - vreg_l5a_0p88: ldo5 { - regulator-name = "vreg_l5a_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7a_1p8: ldo7 { - regulator-name = "vreg_l7a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l10a_2p96: ldo10 { - regulator-name = "vreg_l10a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l11a_0p8: ldo11 { - regulator-name = "vreg_l11a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_1p8: - vreg_l12a_1p8: ldo12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p7: ldo13 { - regulator-name = "vreg_l13a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p7: ldo15 { - regulator-name = "vreg_l15a_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1704000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_2p96: ldo17 { - regulator-name = "vreg_l17a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - }; - - pmm8155au-2-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>; - vdd-l6-l9-supply = <&vreg_s6c_1p128>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s4c_1p352: smps4 { - regulator-name = "vreg_s4c_1p352"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5c_2p04: smps5 { - regulator-name = "vreg_s5c_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6c_1p128: smps6 { - regulator-name = "vreg_s6c_1p128"; - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1c_1p304: ldo1 { - regulator-name = "vreg_l1c_1p304"; - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p808: ldo2 { - regulator-name = "vreg_l2c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p2: ldo5 { - regulator-name = "vreg_l5c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7c_1p8: ldo7 { - regulator-name = "vreg_l7c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p2: ldo8 { - regulator-name = "vreg_l8c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l10c_3p3: ldo10 { - regulator-name = "vreg_l10c_3p3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l11c_0p8: ldo11 { - regulator-name = "vreg_l11c_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l12c_1p808: ldo12 { - regulator-name = "vreg_l12c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l13c_2p96: ldo13 { - regulator-name = "vreg_l13c_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l15c_1p9: ldo15 { - regulator-name = "vreg_l15c_1p9"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l16c_3p008: ldo16 { - regulator-name = "vreg_l16c_3p008"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l18c_0p88: ldo18 { - regulator-name = "vreg_l18c_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - }; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&remoteproc_adsp { - status = "okay"; - firmware-name = "qcom/sa8155p/adsp.mdt"; -}; - -&remoteproc_cdsp { - status = "okay"; - firmware-name = "qcom/sa8155p/cdsp.mdt"; -}; - -ðernet { - status = "okay"; - - snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 11000 70000>; - - snps,ptp-ref-clk-rate = <250000000>; - snps,ptp-req-clk-rate = <96000000>; - - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - - pinctrl-names = "default"; - pinctrl-0 = <ðernet_defaults>; - - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - - compatible = "snps,dwmac-mdio"; - - /* Micrel KSZ9031RNZ PHY */ - rgmii_phy: phy@7 { - reg = <0x7>; - device_type = "ethernet-phy"; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l10a_2p96>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l5c_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vreg_l5a_0p88>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en1_default>; -}; - -&usb_1_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_1_qmpphy { - status = "disabled"; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en2_default>; -}; - -&usb_2_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_2_qmpphy { - status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>; - - usb2phy_ac_en1_default: usb2phy_ac_en1_default { - mux { - pins = "gpio113"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - usb2phy_ac_en2_default: usb2phy_ac_en2_default { - mux { - pins = "gpio123"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - ethernet_defaults: ethernet-defaults { - mdc { - pins = "gpio7"; - function = "rgmii"; - bias-pull-up; - }; - - mdio { - pins = "gpio59"; - function = "rgmii"; - bias-pull-up; - }; - - rgmii-rx { - pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116"; - function = "rgmii"; - bias-disable; - drive-strength = <2>; - }; - - rgmii-tx { - pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121"; - function = "rgmii"; - bias-pull-up; - drive-strength = <16>; - }; - - phy-intr { - pins = "gpio124"; - function = "emac_phy"; - bias-disable; - drive-strength = <8>; - }; - - pps { - pins = "gpio81"; - function = "emac_pps"; - bias-disable; - drive-strength = <8>; - }; - - phy-reset { - pins = "gpio79"; - function = "gpio"; - bias-pull-up; - drive-strength = <16>; - }; - }; -}; diff --git a/rr-cache/34e51a35d1bed604fc421929e339a9cda9249811/preimage b/rr-cache/34e51a35d1bed604fc421929e339a9cda9249811/preimage deleted file mode 100644 index c0e7d95..0000000 --- a/rr-cache/34e51a35d1bed604fc421929e339a9cda9249811/preimage +++ /dev/null @@ -1,600 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -/dts-v1/; - -#include -#include -#include "sm8150.dtsi" -#include "pmm8155au_1.dtsi" -#include "pmm8155au_2.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SA8155P ADP"; - compatible = "qcom,sa8155p-adp", "qcom,sa8155p"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vreg_3p3: vreg_3p3_regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_3p3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* - * S4A is always on and not controllable through RPMh. - * So model it as a fixed regulator. - */ - vreg_s4a_1p8: smps4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - - vin-supply = <&vreg_3p3>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xC>; - }; - }; - - mtl_tx_setup: tx-queues-config { -<<<<<<< - snps,tx-queues-to-use = <4>; - snps,tx-sched-wrr; - - queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; - }; - - queue1 { - snps,weight = <0x11>; - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue2 { - snps,weight = <0x12>; - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue3 { - snps,weight = <0x13>; - snps,dcb-algorithm; - snps,priority = <0x3>; - }; -======= - snps,tx-queues-to-use = <4>; - snps,tx-sched-sp; - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3E800>; - snps,low_credit = <0xFFC18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3E800>; - snps,low_credit = <0xFFC18000>; - }; ->>>>>>> - }; -}; - -&apps_rsc { - pmm8155au-1-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>; - vdd-l6-l9-supply = <&vreg_s6a_0p92>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s5a_2p04: smps5 { - regulator-name = "vreg_s5a_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6a_0p92: smps6 { - regulator-name = "vreg_s6a_0p92"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1a_0p752: ldo1 { - regulator-name = "vreg_l1a_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_3p1: - vreg_l2a_3p072: ldo2 { - regulator-name = "vreg_l2a_3p072"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p8: ldo3 { - regulator-name = "vreg_l3a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdd_usb_hs_core: - vdda_usb_ss_dp_core_1: - vreg_l5a_0p88: ldo5 { - regulator-name = "vreg_l5a_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7a_1p8: ldo7 { - regulator-name = "vreg_l7a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l10a_2p96: ldo10 { - regulator-name = "vreg_l10a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l11a_0p8: ldo11 { - regulator-name = "vreg_l11a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_1p8: - vreg_l12a_1p8: ldo12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p7: ldo13 { - regulator-name = "vreg_l13a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p7: ldo15 { - regulator-name = "vreg_l15a_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1704000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_2p96: ldo17 { - regulator-name = "vreg_l17a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - }; - - pmm8155au-2-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>; - vdd-l6-l9-supply = <&vreg_s6c_1p128>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s4c_1p352: smps4 { - regulator-name = "vreg_s4c_1p352"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5c_2p04: smps5 { - regulator-name = "vreg_s5c_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6c_1p128: smps6 { - regulator-name = "vreg_s6c_1p128"; - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1c_1p304: ldo1 { - regulator-name = "vreg_l1c_1p304"; - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p808: ldo2 { - regulator-name = "vreg_l2c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p2: ldo5 { - regulator-name = "vreg_l5c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7c_1p8: ldo7 { - regulator-name = "vreg_l7c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p2: ldo8 { - regulator-name = "vreg_l8c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l10c_3p3: ldo10 { - regulator-name = "vreg_l10c_3p3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l11c_0p8: ldo11 { - regulator-name = "vreg_l11c_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l12c_1p808: ldo12 { - regulator-name = "vreg_l12c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l13c_2p96: ldo13 { - regulator-name = "vreg_l13c_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l15c_1p9: ldo15 { - regulator-name = "vreg_l15c_1p9"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l16c_3p008: ldo16 { - regulator-name = "vreg_l16c_3p008"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l18c_0p88: ldo18 { - regulator-name = "vreg_l18c_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - }; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&remoteproc_adsp { - status = "okay"; - firmware-name = "qcom/sa8155p/adsp.mdt"; -}; - -&remoteproc_cdsp { - status = "okay"; - firmware-name = "qcom/sa8155p/cdsp.mdt"; -}; - -ðernet { - status = "okay"; - - snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 11000 70000>; - - snps,ptp-ref-clk-rate = <250000000>; - snps,ptp-req-clk-rate = <96000000>; - - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - - pinctrl-names = "default"; - pinctrl-0 = <ðernet_defaults>; - - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - - compatible = "snps,dwmac-mdio"; - - /* Micrel KSZ9031RNZ PHY */ - rgmii_phy: phy@7 { - reg = <0x7>; - device_type = "ethernet-phy"; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l10a_2p96>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l5c_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vreg_l5a_0p88>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en1_default>; -}; - -&usb_1_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_1_qmpphy { - status = "disabled"; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en2_default>; -}; - -&usb_2_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_2_qmpphy { - status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>; - - usb2phy_ac_en1_default: usb2phy_ac_en1_default { - mux { - pins = "gpio113"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - usb2phy_ac_en2_default: usb2phy_ac_en2_default { - mux { - pins = "gpio123"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - ethernet_defaults: ethernet-defaults { -<<<<<<< - mdc { - pins = "gpio7"; - function = "rgmii"; - bias-pull-up; - }; - - mdio { - pins = "gpio59"; - function = "rgmii"; - bias-pull-up; - }; - - rgmii-rx { - pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116"; -======= - rgmii { - pins = "gpio4", "gpio5", "gpio6", "gpio7", "gpio59", - "gpio114", "gpio115", "gpio116", "gpio117", - "gpio118", "gpio119", "gpio120", "gpio121", "gpio122"; ->>>>>>> - function = "rgmii"; - bias-disable; - drive-strength = <2>; - }; - -<<<<<<< - emac_phy { -======= - rgmii-tx { - pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121"; - function = "rgmii"; - bias-pull-up; - drive-strength = <16>; - }; - - phy-intr { ->>>>>>> - pins = "gpio124"; - function = "emac_phy"; - bias-disable; - drive-strength = <8>; - }; - -<<<<<<< - emac_pps { -======= - pps { ->>>>>>> - pins = "gpio81"; - function = "emac_pps"; - bias-disable; - drive-strength = <8>; - }; - -<<<<<<< - phy-reset { - pins = "gpio79"; - function = "gpio"; -======= - phy_reset { - pins = "gpio79"; - function = "phase_flag"; ->>>>>>> - bias-pull-up; - drive-strength = <16>; - }; - }; -}; diff --git a/rr-cache/43d8e080061e294b75f5fa0ca3fc3b238c87f837/preimage b/rr-cache/43d8e080061e294b75f5fa0ca3fc3b238c87f837/preimage deleted file mode 100644 index 9a05792..0000000 --- a/rr-cache/43d8e080061e294b75f5fa0ca3fc3b238c87f837/preimage +++ /dev/null @@ -1,1029 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include -#include -#include -#include -#include "sm8250.dtsi" -#include "pm8150.dtsi" -#include "pm8150b.dtsi" -#include "pm8150l.dtsi" -#include "pm8009.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SM8250 MTP"; - compatible = "qcom,sm8250-mtp", "qcom,sm8250"; - - aliases { - serial0 = &uart12; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - thermal-zones { - camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150l_adc_tm 0>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - conn-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150b_adc_tm 0>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - mmw-pa1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150_adc_tm 2>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - mmw-pa2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150l_adc_tm 2>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - skin-msm-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150l_adc_tm 1>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - skin-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150_adc_tm 1>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150_adc_tm 0>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - vreg_s4a_1p8: pm8150-s4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; - - vreg_s6c_0p88: smpc6-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_s6c_0p88"; - - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-always-on; - vin-supply = <&vph_pwr>; - }; - - display_panel_avdd: display_gpio_regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "display_panel_avdd"; - regulator-min-microvolt = <5500000>; - regulator-max-microvolt = <5500000>; - regulator-enable-ramp-delay = <233>; - gpio = <&tlmm 61 0>; - enable-active-high; - regulator-boot-on; - pinctrl-names = "default"; - pinctrl-0 = <&display_panel_avdd_default>; - }; - -}; - -&adsp { - status = "okay"; - firmware-name = "qcom/sm8250/adsp.mbn"; -}; - -&apps_rsc { - pm8150-rpmh-regulators { - compatible = "qcom,pm8150-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; - vdd-l2-l10-supply = <&vreg_bob>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; - vdd-l6-l9-supply = <&vreg_s8c_1p3>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; - vdd-l13-l16-l17-supply = <&vreg_bob>; - - vreg_s5a_1p9: smps5 { - regulator-name = "vreg_s5a_1p9"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - vreg_s6a_0p95: smps6 { - regulator-name = "vreg_s6a_0p95"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - regulator-initial-mode = ; - }; - - vreg_l2a_3p1: ldo2 { - regulator-name = "vreg_l2a_3p1"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p9: ldo3 { - regulator-name = "vreg_l3a_0p9"; - regulator-min-microvolt = <928000>; - regulator-max-microvolt = <932000>; - regulator-initial-mode = ; - }; - - vreg_l5a_0p875: ldo5 { - regulator-name = "vreg_l5a_0p875"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l6a_1p2: ldo6 { - regulator-name = "vreg_l6a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p7: ldo7 { - regulator-name = "vreg_l7a_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l9a_1p2: ldo9 { - regulator-name = "vreg_l9a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l10a_1p8: ldo10 { - regulator-name = "vreg_l10a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l12a_1p8: ldo12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_ts_3p0: ldo13 { - regulator-name = "vreg_l13a_ts_3p0"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l14a_1p8: ldo14 { - regulator-name = "vreg_l14a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1880000>; - regulator-initial-mode = ; - }; - - vreg_l15a_11ad_io_1p8: ldo15 { - regulator-name = "vreg_l15a_11ad_io_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_3p0: ldo17 { - regulator-name = "vreg_l17a_3p0"; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l18a_0p9: ldo18 { - regulator-name = "vreg_l18a_0p9"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - }; - }; - - pm8150l-rpmh-regulators { - compatible = "qcom,pm8150l-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-l1-l8-supply = <&vreg_s4a_1p8>; - vdd-l2-l3-supply = <&vreg_s8c_1p3>; - vdd-l4-l5-l6-supply = <&vreg_bob>; - vdd-l7-l11-supply = <&vreg_bob>; - vdd-l9-l10-supply = <&vreg_bob>; - vdd-bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-name = "vreg_bob"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <4000000>; - regulator-initial-mode = ; - }; - - vreg_s8c_1p3: smps8 { - regulator-name = "vreg_s8c_1p3"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - regulator-initial-mode = ; - }; - - vreg_l1c_1p8: ldo1 { - regulator-name = "vreg_l1c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p2: ldo2 { - regulator-name = "vreg_l2c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l3c_0p92: ldo3 { - regulator-name = "vreg_l3c_0p92"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l4c_1p7: ldo4 { - regulator-name = "vreg_l4c_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p8: ldo5 { - regulator-name = "vreg_l5c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l6c_2p9: ldo6 { - regulator-name = "vreg_l6c_2p9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l7c_cam_vcm0_2p85: ldo7 { - regulator-name = "vreg_l7c_cam_vcm0_2p85"; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3104000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p8: ldo8 { - regulator-name = "vreg_l8c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l9c_2p9: ldo9 { - regulator-name = "vreg_l9c_2p9"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l10c_3p0: ldo10 { - regulator-name = "vreg_l10c_3p0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = ; - }; - - vreg_l11c_3p3: ldo11 { - regulator-name = "vreg_l11c_3p3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - }; - - pm8009-rpmh-regulators { - compatible = "qcom,pm8009-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vreg_bob>; - vdd-l2-supply = <&vreg_s8c_1p3>; - vdd-l5-l6-supply = <&vreg_bob>; - vdd-l7-supply = <&vreg_s4a_1p8>; - - vreg_l1f_cam_dvdd1_1p1: ldo1 { - regulator-name = "vreg_l1f_cam_dvdd1_1p1"; - regulator-min-microvolt = <1104000>; - regulator-max-microvolt = <1104000>; - regulator-initial-mode = ; - }; - - vreg_l2f_cam_dvdd0_1p2: ldo2 { - regulator-name = "vreg_l2f_cam_dvdd0_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l3f_cam_dvdd2_1p05: ldo3 { - regulator-name = "vreg_l3f_cam_dvdd2_1p05"; - regulator-min-microvolt = <1056000>; - regulator-max-microvolt = <1056000>; - regulator-initial-mode = ; - }; - - vreg_l5f_cam_avdd0_2p85: ldo5 { - regulator-name = "vreg_l5f_cam_avdd0_2p85"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = ; - }; - - vreg_l6f_cam_avdd1_2p85: ldo6 { - regulator-name = "vreg_l6f_cam_avdd1_2p85"; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <2856000>; - regulator-initial-mode = ; - }; - - vreg_l7f_1p8: ldo7 { - regulator-name = "vreg_l7f_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; -}; - -&cdsp { - status = "okay"; - firmware-name = "qcom/sm8250/cdsp.mbn"; -}; - -&dsi0 { - status = "okay"; - vdda-supply = <&vreg_l9a_1p2>; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - port@1 { - endpoint { - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l5a_0p875>; -}; - -#if 0 -&dsi1 { - status = "okay"; - vdda-supply = <&vreg_l9a_1p2>; - - ports { - port@1 { - endpoint { - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi1_phy { - status = "okay"; - vdds-supply = <&vreg_l5a_0p875>; -}; -#endif - -&gmu { - status = "okay"; -}; - -&gpu { - status = "okay"; - - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sm8250/a650_zap.mbn"; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <1000000>; - - /* NQ NFC chip @28 */ -}; - -&i2c13 { - status = "okay"; - - /* st,stmfts @ 49 */ -}; - -&i2c15 { - status = "okay"; - - /* smb1390 @ 10 */ - /* rtc6226 @ 64 */ -}; - -&mdss { - status = "okay"; -}; - -&mdss_mdp { - status = "okay"; -}; - -&pm8150_adc { - xo-therm@4c { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; - - skin-therm@4d { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; - - pa-therm1@4e { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; -}; - -&pm8150_adc_tm { - status = "okay"; - - xo-therm@0 { - reg = <0>; - io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; - - skin-therm@1 { - reg = <1>; - io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; - - pa-therm1@2 { - reg = <2>; - io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; -}; - -&pm8150b_adc { - conn-therm@4f { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; -}; - -&pm8150b_adc_tm { - status = "okay"; - - conn-therm@0 { - reg = <0>; - io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; -}; - -&pm8150l_adc_tm { - status = "okay"; - - camera-flash-therm@0 { - reg = <0>; - io-channels = <&pm8150l_adc ADC5_AMUX_THM1_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; - - skin-msm-therm@1 { - reg = <1>; - io-channels = <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; - - pa-therm2@2 { - reg = <2>; - io-channels = <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; -}; - -&pm8150l_adc { - camera-flash-therm@4d { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; - - skin-msm-therm@4e { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; - - pa-therm2@4f { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&qupv3_id_2 { - status = "okay"; -}; - -&slpi { - status = "okay"; - firmware-name = "qcom/sm8250/slpi.mbn"; -}; - -&soc { - wcd938x: codec { - compatible = "qcom,wcd9380-codec"; - #sound-dai-cells = <1>; - reset-gpios = <&tlmm 32 0>; - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-rxtx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; - vdd-mic-bias-supply = <&vreg_bob>; - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; - qcom,mbhc-headset-vthreshold-microvolt = <1700000>; - qcom,mbhc-headphone-vthreshold-microvolt = <50000>; - qcom,rx-device = <&wcd_rx>; - qcom,tx-device = <&wcd_tx>; - }; -}; - -&sound { - compatible = "qcom,sm8250-sndcard"; - model = "SM8250-MTP-WCD9380-WSA8810-VA-DMIC"; - audio-routing = - "SpkrLeft IN", "WSA_SPK1 OUT", - "SpkrRight IN", "WSA_SPK2 OUT", - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "AMIC1", "MIC BIAS1", - "AMIC2", "MIC BIAS2", - "AMIC3", "MIC BIAS3", - "AMIC4", "MIC BIAS3", - "AMIC5", "MIC BIAS4", - "TX SWR_ADC0", "ADC1_OUTPUT", - "TX SWR_ADC1", "ADC2_OUTPUT", - "TX SWR_ADC2", "ADC3_OUTPUT", - "TX SWR_ADC3", "ADC4_OUTPUT", - "TX SWR_DMIC0", "DMIC1_OUTPUT", - "TX SWR_DMIC1", "DMIC2_OUTPUT", - "TX SWR_DMIC2", "DMIC3_OUTPUT", - "TX SWR_DMIC3", "DMIC4_OUTPUT", - "TX SWR_DMIC4", "DMIC5_OUTPUT", - "TX SWR_DMIC5", "DMIC6_OUTPUT", - "TX SWR_DMIC6", "DMIC7_OUTPUT", - "TX SWR_DMIC7", "DMIC8_OUTPUT"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - mm2-dai-link { - link-name = "MultiMedia2"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; - }; - }; - - mm3-dai-link { - link-name = "MultiMedia3"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; - }; - }; - - wcd-playback-dai-link { - link-name = "WCD Playback"; - cpu { - sound-dai = <&q6afedai RX_CODEC_DMA_RX_0>; - }; - codec { - sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; - }; - platform { - sound-dai = <&q6routing>; - }; - }; - - wcd-capture-dai-link { - link-name = "WCD Capture"; - cpu { - sound-dai = <&q6afedai TX_CODEC_DMA_TX_3>; - }; - - codec { - sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>; - }; - platform { - sound-dai = <&q6routing>; - }; - }; - - wsa-dai-link { - link-name = "WSA Playback"; - cpu { - sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>; - }; - - codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; - }; - platform { - sound-dai = <&q6routing>; - }; - }; - - va-dai-link { - link-name = "VA Capture"; - cpu { - sound-dai = <&q6afedai VA_CODEC_DMA_TX_0>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&vamacro 0>; - }; - }; -}; - -&swr0 { - left_spkr: wsa8810-right@0,3{ - compatible = "sdw10217211000"; - reg = <0 3>; - powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrLeft"; - #sound-dai-cells = <0>; - }; - - right_spkr: wsa8810-left@0,4{ - compatible = "sdw10217211000"; - reg = <0 4>; - powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrRight"; - #sound-dai-cells = <0>; - }; -}; - -&swr1 { - wcd_rx: wcd9380-rx@0,4 { - compatible = "sdw20217010d00"; - reg = <0 4>; - qcom,rx-port-mapping = <1 2 3 4 5>; - }; -}; - -&swr2 { - wcd_tx: wcd9380-tx@0,3 { - compatible = "sdw20217010d00"; - reg = <0 3>; - qcom,tx-port-mapping = <2 3 4 5>; - }; -}; - -&tlmm { - gpio-reserved-ranges = <28 4>, <40 4>; - - display_panel_avdd_default: display_panel_avdd_default { - mux { - pins = "gpio61"; - function = "gpio"; - }; - - config { - pins = "gpio61"; - drive-strength = <8>; - bias-disable = <0>; - output-high; - }; - }; - -<<<<<<< -======= - wcd938x_reset_default: wcd938x_reset_default { - mux { - pins = "gpio32"; - function = "gpio"; - }; - - config { - pins = "gpio32"; - drive-strength = <16>; - output-high; - }; - }; - - wcd938x_reset_sleep: wcd938x_reset_sleep { - mux { - pins = "gpio32"; - function = "gpio"; - }; - - config { - pins = "gpio32"; - drive-strength = <16>; - bias-disable; - output-low; - }; - }; ->>>>>>> -}; - -&uart12 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - vcc-supply = <&vreg_l17a_3p0>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l6a_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l5a_0p875>; - vdda-pll-supply = <&vreg_l9a_1p2>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdda-pll-supply = <&vreg_l5a_0p875>; - vdda18-supply = <&vreg_l12a_1p8>; - vdda33-supply = <&vreg_l2a_3p1>; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdda-pll-supply = <&vreg_l5a_0p875>; - vdda18-supply = <&vreg_l12a_1p8>; - vdda33-supply = <&vreg_l2a_3p1>; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; -}; - -&swr0 { - left_right: wsa8810-right{ - compatible = "sdw10217211000"; - reg = <0 2>; - powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrRight"; - #sound-dai-cells = <0>; - }; - - left_spkr: wsa8810-left{ - compatible = "sdw10217211000"; - reg = <0 1>; - powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrLeft"; - #sound-dai-cells = <0>; - }; -}; - -&q6asmdai { - dai@0 { - reg = <0>; - direction = <2>; - }; -}; - -&sound { - compatible = "qcom,sm8250-sndcard"; - model = "SM8250"; - audio-routing = - "SpkrLeft IN", "WSA_SPK1 OUT", - "MM_DL1", "MultiMedia1 Playback"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - dma-dai-link { - link-name = "WSA Playback"; - cpu { - sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&left_spkr>, <&swr0 0>, <&wsamacro 0>; - }; - }; -}; - -&venus { - status = "okay"; -}; diff --git a/rr-cache/447b0ec5bb7ddefa9f58500a4486e62623e1dedb/preimage b/rr-cache/447b0ec5bb7ddefa9f58500a4486e62623e1dedb/preimage deleted file mode 100644 index 9fb5606..0000000 --- a/rr-cache/447b0ec5bb7ddefa9f58500a4486e62623e1dedb/preimage +++ /dev/null @@ -1,634 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* -<<<<<<< - * PCI EPF driver for MHI Endpoint -======= - * PCI EPF driver for MHI Endpoint devices ->>>>>>> - * - * Copyright (C) 2021 Linaro Ltd. - * Author: Manivannan Sadhasivam - */ - -<<<<<<< -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -======= -#include -#include -#include ->>>>>>> -#include -#include - -#define MHI_VERSION_1_0 0x01000000 - -<<<<<<< -======= -static struct workqueue_struct *pci_epf_mhi_wq; - ->>>>>>> -struct pci_epf_mhi_ep_info { - const struct mhi_ep_cntrl_config *config; - struct pci_epf_header *epf_header; - enum pci_barno bar_num; - u32 epf_flags; - u32 msi_count; -<<<<<<< -======= - u32 mru; ->>>>>>> -}; - -#define MHI_EP_CHANNEL_CONFIG_UL(ch_num, ch_name) \ - { \ - .num = ch_num, \ - .name = ch_name, \ - .dir = DMA_TO_DEVICE, \ - } - -#define MHI_EP_CHANNEL_CONFIG_DL(ch_num, ch_name) \ - { \ - .num = ch_num, \ - .name = ch_name, \ - .dir = DMA_FROM_DEVICE, \ - } - -static const struct mhi_ep_channel_config mhi_v1_channels[] = { - MHI_EP_CHANNEL_CONFIG_UL(0, "LOOPBACK"), - MHI_EP_CHANNEL_CONFIG_DL(1, "LOOPBACK"), - MHI_EP_CHANNEL_CONFIG_UL(2, "SAHARA"), - MHI_EP_CHANNEL_CONFIG_DL(3, "SAHARA"), - MHI_EP_CHANNEL_CONFIG_UL(4, "DIAG"), - MHI_EP_CHANNEL_CONFIG_DL(5, "DIAG"), - MHI_EP_CHANNEL_CONFIG_UL(6, "SSR"), - MHI_EP_CHANNEL_CONFIG_DL(7, "SSR"), - MHI_EP_CHANNEL_CONFIG_UL(8, "QDSS"), - MHI_EP_CHANNEL_CONFIG_DL(9, "QDSS"), - MHI_EP_CHANNEL_CONFIG_UL(10, "EFS"), - MHI_EP_CHANNEL_CONFIG_DL(11, "EFS"), - MHI_EP_CHANNEL_CONFIG_UL(12, "MBIM"), - MHI_EP_CHANNEL_CONFIG_DL(13, "MBIM"), - MHI_EP_CHANNEL_CONFIG_UL(14, "QMI"), - MHI_EP_CHANNEL_CONFIG_DL(15, "QMI"), - MHI_EP_CHANNEL_CONFIG_UL(16, "QMI"), - MHI_EP_CHANNEL_CONFIG_DL(17, "QMI"), - MHI_EP_CHANNEL_CONFIG_UL(18, "IP-CTRL-1"), - MHI_EP_CHANNEL_CONFIG_DL(19, "IP-CTRL-1"), - MHI_EP_CHANNEL_CONFIG_UL(20, "IPCR"), - MHI_EP_CHANNEL_CONFIG_DL(21, "IPCR"), - MHI_EP_CHANNEL_CONFIG_UL(32, "DUN"), - MHI_EP_CHANNEL_CONFIG_DL(33, "DUN"), - MHI_EP_CHANNEL_CONFIG_UL(36, "IP_SW0"), - MHI_EP_CHANNEL_CONFIG_DL(37, "IP_SW0"), -}; - -static const struct mhi_ep_cntrl_config mhi_v1_config = { - .max_channels = 128, - .num_channels = ARRAY_SIZE(mhi_v1_channels), - .ch_cfg = mhi_v1_channels, - .mhi_version = MHI_VERSION_1_0, -}; - -static struct pci_epf_header sdx55_header = { -<<<<<<< - .vendorid = 0x17cb, - .deviceid = 0x0306, - .revid = 0x0, - .progif_code = 0x0, - .subclass_code = 0x0, - .baseclass_code = 0xff, - .cache_line_size = 0x10, - .subsys_vendor_id = 0x0, - .subsys_id = 0x0, -======= - .vendorid = PCI_VENDOR_ID_QCOM, - .deviceid = 0x0306, - .baseclass_code = PCI_CLASS_OTHERS, - .interrupt_pin = PCI_INTERRUPT_INTA, ->>>>>>> -}; - -static const struct pci_epf_mhi_ep_info sdx55_info = { - .config = &mhi_v1_config, - .epf_header = &sdx55_header, - .bar_num = BAR_0, - .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32, -<<<<<<< - .msi_count = 32, -}; - -struct pci_epf_mhi { - const struct pci_epf_mhi_ep_info *info; - struct mhi_ep_cntrl mhi_cntrl; - struct work_struct work; - struct pci_epf *epf; - struct mutex lock; - void __iomem *mmio; - resource_size_t mmio_phys; - enum pci_notify_event event; - u32 mmio_size; - int irq; - bool mhi_registered; -======= - .msi_count = 4, -}; - -struct pci_epf_mhi { - struct mhi_ep_cntrl mhi_cntrl; - struct pci_epf *epf; - const struct pci_epf_mhi_ep_info *info; - void __iomem *mmio; - resource_size_t mmio_phys; - bool link_up; - bool link_enabled; - bool mhi_registered; - u32 mmio_size; - int irq; ->>>>>>> -}; - -void __iomem *pci_epf_mhi_alloc_addr(struct mhi_ep_cntrl *mhi_cntrl, - phys_addr_t *phys_addr, size_t size) -{ - struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); - struct pci_epc *epc = epf_mhi->epf->epc; - - return pci_epc_mem_alloc_addr(epc, phys_addr, size); -} - -void pci_epf_mhi_free_addr(struct mhi_ep_cntrl *mhi_cntrl, - phys_addr_t phys_addr, void __iomem *virt_addr, size_t size) -{ - struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); - struct pci_epc *epc = epf_mhi->epf->epc; - - pci_epc_mem_free_addr(epc, phys_addr, virt_addr, size); -} - -<<<<<<< -inline int pci_epf_mhi_map_addr(struct mhi_ep_cntrl *mhi_cntrl, -======= -int pci_epf_mhi_map_addr(struct mhi_ep_cntrl *mhi_cntrl, ->>>>>>> - phys_addr_t phys_addr, u64 pci_addr, size_t size) -{ - struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); - struct pci_epf *epf = epf_mhi->epf; - struct pci_epc *epc = epf->epc; - - return pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, phys_addr, pci_addr, size); -} - -void pci_epf_mhi_unmap_addr(struct mhi_ep_cntrl *mhi_cntrl, phys_addr_t phys_addr) -{ - struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); - struct pci_epf *epf = epf_mhi->epf; - struct pci_epc *epc = epf->epc; - - pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, phys_addr); -} - -<<<<<<< -void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl) -======= -void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector) ->>>>>>> -{ - struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); - struct pci_epf *epf = epf_mhi->epf; - struct pci_epc *epc = epf->epc; - -<<<<<<< - /* - * Vector is incremented by 1 here as the DWC core will decrement it before - * writing to iATU. - */ - pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI, vector + 1); -} - -int pci_epf_mhi_read_from_host(struct mhi_ep_cntrl *mhi_cntrl, u64 from, void __iomem *to, - size_t size) -{ - struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); - struct pci_epf *epf = epf_mhi->epf; - struct pci_epc *epc = epf_mhi->epf->epc; - void __iomem *tre_buf; - phys_addr_t tre_phys; - size_t offset = from % 0x1000; - int ret; - - mutex_lock(&epf_mhi->lock); - - tre_buf = pci_epc_mem_alloc_addr(epc, &tre_phys, size + offset); - if (!tre_buf) - return -ENOMEM; - - ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, tre_phys, from - offset, - size + offset); - if (ret) { - pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); - mutex_unlock(&epf_mhi->lock); - return ret; - } - - memcpy_fromio(to, tre_buf + offset, size); - - pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, tre_phys); - pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); - - mutex_unlock(&epf_mhi->lock); - - return 0; -} - -int pci_epf_mhi_write_to_host(struct mhi_ep_cntrl *mhi_cntrl, void __iomem *from, u64 to, - size_t size) -{ - struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl); - struct pci_epf *epf = epf_mhi->epf; - struct pci_epc *epc = epf_mhi->epf->epc; - void __iomem *tre_buf; - phys_addr_t tre_phys; - size_t offset = to % 0x1000; - int ret; - - mutex_lock(&epf_mhi->lock); - - tre_buf = pci_epc_mem_alloc_addr(epc, &tre_phys, size + offset); - if (!tre_buf) - return -ENOMEM; - - ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, tre_phys, to - offset, - size + offset); - if (ret) { - pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); - mutex_unlock(&epf_mhi->lock); - return ret; - } - - memcpy_toio(tre_buf + offset, from, size); - - pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, tre_phys); - pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); - - mutex_unlock(&epf_mhi->lock); - - return 0; -} - -static int pci_epf_mhi_notifier(struct notifier_block *nb, unsigned long val, void *data) -{ - struct pci_epf *epf = container_of(nb, struct pci_epf, nb); - struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); -======= - /* Using fixed MSI for now */ - pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI, 1); -} - -static int pci_epf_mhi_notifier(struct notifier_block *nb, unsigned long val, - void *data) -{ - struct pci_epf *epf = container_of(nb, struct pci_epf, nb); - struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); - struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; ->>>>>>> - const struct pci_epf_mhi_ep_info *info = epf_mhi->info; - struct pci_epf_bar *epf_bar = &epf->bar[info->bar_num]; - struct pci_epc *epc = epf->epc; - struct device *dev = &epf->dev; - int ret; - -<<<<<<< - /* - * If the notification is other than CORE_INIT and if MHI EP is not - * yet registered, then error out. - */ - if ((val != CORE_INIT) && !epf_mhi->mhi_registered) { - dev_err(dev, "MHI EP not yet registered\n"); - return NOTIFY_BAD; - } - - switch (val) { - case CORE_INIT: -======= - if (val == CORE_INIT) { ->>>>>>> - epf_bar->phys_addr = epf_mhi->mmio_phys; - epf_bar->size = epf_mhi->mmio_size; - epf_bar->barno = info->bar_num; - epf_bar->flags = info->epf_flags; - ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); - if (ret) { - dev_err(dev, "Failed to set BAR: %d\n", ret); - return NOTIFY_BAD; - } - -<<<<<<< - ret = pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no, - order_base_2(info->msi_count)); -======= - ret = pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no, order_base_2(info->msi_count)); ->>>>>>> - if (ret) { - dev_err(dev, "Failed to set MSI configuration: %d\n", ret); - return NOTIFY_BAD; - } - -<<<<<<< - ret = pci_epc_write_header(epc, epf->func_no, epf->vfunc_no, epf->header); -======= - ret = pci_epc_write_header(epc, epf->func_no, epf->vfunc_no, info->epf_header); ->>>>>>> - if (ret) { - dev_err(dev, "Failed to set Configuration header: %d\n", ret); - return NOTIFY_BAD; - } - -<<<<<<< - mhi_cntrl->mmio = epf_mhi->mmio; - mhi_cntrl->irq = epf_mhi->irq; -======= - return NOTIFY_OK; - } - - epf_mhi->event = val; - queue_work(pci_epf_mhi_wq, &epf_mhi->work); - - return NOTIFY_OK; -} - -static void pci_epf_mhi_worker(struct work_struct *work) -{ - struct pci_epf_mhi *epf_mhi = container_of(work, struct pci_epf_mhi, work); - const struct pci_epf_mhi_ep_info *info = epf_mhi->info; - struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; - struct pci_epf *epf = epf_mhi->epf; - struct pci_epc *epc = epf->epc; - struct device *dev = &epf->dev; - int ret; - - switch (epf_mhi->event) { - case LINK_UP: - mhi_cntrl->mmio = epf_mhi->mmio; - mhi_cntrl->irq = epf_mhi->irq; - mhi_cntrl->mru = info->mru; ->>>>>>> - - /* Assign the struct dev of PCI EP as MHI controller device */ - mhi_cntrl->cntrl_dev = epc->dev.parent; - mhi_cntrl->raise_irq = pci_epf_mhi_raise_irq; - mhi_cntrl->alloc_addr = pci_epf_mhi_alloc_addr; - mhi_cntrl->free_addr = pci_epf_mhi_free_addr; - mhi_cntrl->map_addr = pci_epf_mhi_map_addr; - mhi_cntrl->unmap_addr = pci_epf_mhi_unmap_addr; -<<<<<<< -======= - mhi_cntrl->read_from_host = pci_epf_mhi_read_from_host; - mhi_cntrl->write_to_host = pci_epf_mhi_write_to_host; ->>>>>>> - - /* Register the MHI EP controller */ - ret = mhi_ep_register_controller(mhi_cntrl, info->config); - if (ret) { -<<<<<<< - dev_err(dev, "Failed to register MHI EP controller: %d\n", ret); - return; -======= - dev_err(dev, "Failed to register MHI EP controller\n"); - return NOTIFY_BAD; ->>>>>>> - } - - epf_mhi->mhi_registered = true; - break; -<<<<<<< - case LINK_DOWN: - /* - * Power down the MHI EP stack and unregister the controller - * if both link and MHI EP stack were up - */ - if (epf_mhi->mhi_registered) { - if (mhi_cntrl->is_enabled) - mhi_ep_power_down(mhi_cntrl); - mhi_ep_unregister_controller(mhi_cntrl); - epf_mhi->mhi_registered = false; - } - break; - case BME: - /* Power up the MHI EP stack if link was up and stack was powered down */ - if (!mhi_cntrl->is_enabled && epf_mhi->mhi_registered) { - ret = mhi_ep_power_up(mhi_cntrl); - if (ret) { - dev_err(dev, "Failed to power up MHI EP: %d\n", ret); - return; - } -======= - case LINK_UP: - epf_mhi->link_up = true; - break; - case LINK_DOWN: - /* Power down the MHI EP stack if link is up and link state is enabled */ - if (epf_mhi->link_enabled && epf_mhi->link_up) { - mhi_ep_power_down(mhi_cntrl); - epf_mhi->link_enabled = false; - } - epf_mhi->link_up = false; - break; - case BME: - /* Power up the MHI EP stack if link is up and link state is not enabled */ - if (!epf_mhi->link_enabled && epf_mhi->link_up) { - /* Power up the MHI EP controller */ - mhi_ep_power_up(mhi_cntrl); - epf_mhi->link_enabled = true; ->>>>>>> - } - - break; - default: -<<<<<<< - dev_err(&epf->dev, "Invalid MHI EP notifier event: %d\n", epf_mhi->event); - } -======= - dev_err(&epf->dev, "Invalid MHI device notifier event: %ld\n", val); - return NOTIFY_BAD; - } - - return NOTIFY_OK; ->>>>>>> -} - -static int pci_epf_mhi_bind(struct pci_epf *epf) -{ - struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); - struct pci_epc *epc = epf->epc; - struct platform_device *pdev = to_platform_device(epc->dev.parent); - struct device *dev = &epf->dev; - struct resource *res; - int ret; - - if (WARN_ON_ONCE(!epc)) - return -EINVAL; - - /* Get MMIO physical and virtual address from controller device */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mmio"); - epf_mhi->mmio_phys = res->start; - epf_mhi->mmio_size = resource_size(res); - - epf_mhi->mmio = ioremap_wc(epf_mhi->mmio_phys, epf_mhi->mmio_size); - if (IS_ERR(epf_mhi->mmio)) - return PTR_ERR(epf_mhi->mmio); - - ret = platform_get_irq_byname(pdev, "doorbell"); - if (ret < 0) { - dev_err(dev, "Failed to get Doorbell IRQ\n"); - iounmap(epf_mhi->mmio); - return ret; - } - - epf_mhi->irq = ret; - epf->nb.notifier_call = pci_epf_mhi_notifier; - pci_epc_register_notifier(epc, &epf->nb); - - return 0; -} - -static void pci_epf_mhi_unbind(struct pci_epf *epf) -{ - struct pci_epc *epc = epf->epc; - struct pci_epf_bar *epf_bar = &epf->bar[0]; - struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); - struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; - - pci_epc_unregister_notifier(epc, &epf->nb); - - /* - * Forcefully power down the MHI EP stack. Only way to bring the MHI EP stack - * back to working state after successive bind is by getting BME from host. - */ - if (epf_mhi->mhi_registered) { -<<<<<<< - if (epf_mhi->link_enabled && epf_mhi->link_up) { - mhi_ep_power_down(mhi_cntrl); - epf_mhi->link_enabled = false; - } -======= - if (mhi_cntrl->is_enabled) - mhi_ep_power_down(mhi_cntrl); - ->>>>>>> - mhi_ep_unregister_controller(mhi_cntrl); - epf_mhi->mhi_registered = false; - } - - pci_epc_clear_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); - iounmap(epf_mhi->mmio); -} - -static int pci_epf_mhi_probe(struct pci_epf *epf) -{ - struct pci_epf_mhi_ep_info *info = - (struct pci_epf_mhi_ep_info *) epf->driver->id_table->driver_data; - struct pci_epf_mhi *epf_mhi; - struct device *dev = &epf->dev; - - epf_mhi = devm_kzalloc(dev, sizeof(*epf_mhi), GFP_KERNEL); - if (!epf_mhi) - return -ENOMEM; - -<<<<<<< - epf->header = info->epf_header; - epf_mhi->info = info; - epf_mhi->epf = epf; - - INIT_WORK(&epf_mhi->work, pci_epf_mhi_worker); - mutex_init(&epf_mhi->lock); - -======= - epf_mhi->info = info; - epf_mhi->epf = epf; ->>>>>>> - epf_set_drvdata(epf, epf_mhi); - - return 0; -} - -static const struct pci_epf_device_id pci_epf_mhi_ids[] = { - { -<<<<<<< - .name = "pci_epf_mhi", .driver_data = (kernel_ulong_t) &sdx55_info, -======= - .name = "sdx55", .driver_data = (kernel_ulong_t) &sdx55_info, ->>>>>>> - }, - {}, -}; - -static struct pci_epf_ops pci_epf_mhi_ops = { - .unbind = pci_epf_mhi_unbind, - .bind = pci_epf_mhi_bind, -}; - -static struct pci_epf_driver pci_epf_mhi_driver = { - .driver.name = "pci_epf_mhi", - .probe = pci_epf_mhi_probe, - .id_table = pci_epf_mhi_ids, - .ops = &pci_epf_mhi_ops, - .owner = THIS_MODULE, -}; - -static int __init pci_epf_mhi_init(void) -{ - int ret; - -<<<<<<< - pci_epf_mhi_wq = alloc_ordered_workqueue("pci_epf_mhi_wq", WQ_MEM_RECLAIM | WQ_HIGHPRI); - if (!pci_epf_mhi_wq) { - pr_err("Failed to allocate the mhi_epf work queue\n"); - return -ENOMEM; - } - - ret = pci_epf_register_driver(&pci_epf_mhi_driver); - if (ret) { - destroy_workqueue(pci_epf_mhi_wq); -======= - ret = pci_epf_register_driver(&pci_epf_mhi_driver); - if (ret) { ->>>>>>> - pr_err("Failed to register PCI EPF MHI driver: %d\n", ret); - return ret; - } - - return 0; -} -module_init(pci_epf_mhi_init); - -static void __exit pci_epf_mhi_exit(void) -{ -<<<<<<< -======= - if (pci_epf_mhi_wq) - destroy_workqueue(pci_epf_mhi_wq); ->>>>>>> - pci_epf_unregister_driver(&pci_epf_mhi_driver); -} -module_exit(pci_epf_mhi_exit); - -<<<<<<< -MODULE_DESCRIPTION("PCI EPF driver for MHI Endpoint devices"); -======= -MODULE_DESCRIPTION("PCI EPF driver for MHI Endpoint"); ->>>>>>> -MODULE_AUTHOR("Manivannan Sadhasivam "); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/44d452090fa53039b18712f49f6bfd1c46214c5f/preimage b/rr-cache/44d452090fa53039b18712f49f6bfd1c46214c5f/preimage deleted file mode 100644 index 2632a48..0000000 --- a/rr-cache/44d452090fa53039b18712f49f6bfd1c46214c5f/preimage +++ /dev/null @@ -1,519 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * MHI Endpoint Network driver - * -<<<<<<< - * Based on drivers/net/mhi_ep_net.c - * - * Copyright (c) 2021, Linaro Ltd. - * Author: Manivannan Sadhasivam ->>>>>>> - */ - -#include -#include -#include -#include -#include -#include -#include - -#define MHI_NET_MIN_MTU ETH_MIN_MTU -<<<<<<< -#define MHI_NET_MAX_MTU 0x8000 -======= -#define MHI_NET_MAX_MTU 0xffff ->>>>>>> - -struct mhi_ep_net_stats { - u64_stats_t rx_packets; - u64_stats_t rx_bytes; - u64_stats_t rx_errors; - u64_stats_t tx_packets; - u64_stats_t tx_bytes; - u64_stats_t tx_errors; - u64_stats_t tx_dropped; - struct u64_stats_sync tx_syncp; - struct u64_stats_sync rx_syncp; -}; - -struct mhi_ep_net_dev { - struct mhi_ep_device *mdev; - struct net_device *ndev; -<<<<<<< -======= - struct sk_buff *skbagg_head; - struct sk_buff *skbagg_tail; ->>>>>>> - struct mhi_ep_net_stats stats; - struct workqueue_struct *xmit_wq; - struct work_struct xmit_work; - struct sk_buff_head tx_buffers; - spinlock_t tx_lock; /* Lock for protecting tx_buffers */ -<<<<<<< - u32 mru; -======= -}; - -struct mhi_ep_device_info { - const char *netname; ->>>>>>> -}; - -static void mhi_ep_net_dev_process_queue_packets(struct work_struct *work) -{ -<<<<<<< - struct mhi_ep_net_dev *client = container_of(work, - struct mhi_ep_net_dev, xmit_work); - struct mhi_ep_device *mdev = client->mdev; - struct sk_buff *skb = NULL; - unsigned long flags = 0; - int ret; - - if (mhi_ep_queue_is_empty(mdev, DMA_FROM_DEVICE)) { - netif_stop_queue(client->ndev); - return; - } - - while (!skb_queue_empty(&client->tx_buffers)) { - spin_lock_irqsave(&client->tx_lock, flags); - skb = skb_dequeue(&client->tx_buffers); - if (!skb) { - spin_unlock_irqrestore(&client->tx_lock, flags); - return; - } - spin_unlock_irqrestore(&client->tx_lock, flags); - - ret = mhi_ep_queue_skb(mdev, DMA_FROM_DEVICE, skb, skb->len, MHI_EOT); - if (ret) { - kfree(skb); - return; - } - - u64_stats_update_begin(&client->stats.tx_syncp); - u64_stats_inc(&client->stats.tx_packets); - u64_stats_update_end(&client->stats.tx_syncp); - - /* Check if queue is empty */ - if (mhi_ep_queue_is_empty(mdev, DMA_FROM_DEVICE)) { - netif_stop_queue(client->ndev); -======= - struct mhi_ep_net_dev *mhi_ep_netdev = container_of(work, - struct mhi_ep_net_dev, xmit_work); - struct mhi_ep_device *mdev = mhi_ep_netdev->mdev; - struct sk_buff_head q; - struct sk_buff *skb; - int ret; - - if (mhi_ep_queue_is_empty(mdev, DMA_FROM_DEVICE)) { - netif_stop_queue(mhi_ep_netdev->ndev); - return; - } - - __skb_queue_head_init(&q); - - spin_lock_bh(&mhi_ep_netdev->tx_lock); - skb_queue_splice_init(&mhi_ep_netdev->tx_buffers, &q); - spin_unlock_bh(&mhi_ep_netdev->tx_lock); - - while ((skb = __skb_dequeue(&q))) { - ret = mhi_ep_queue_skb(mdev, DMA_FROM_DEVICE, skb, skb->len, MHI_EOT); - if (ret) { - kfree(skb); - goto exit_drop; - } - - u64_stats_update_begin(&mhi_ep_netdev->stats.tx_syncp); - u64_stats_inc(&mhi_ep_netdev->stats.tx_packets); - u64_stats_add(&mhi_ep_netdev->stats.tx_bytes, skb->len); - u64_stats_update_end(&mhi_ep_netdev->stats.tx_syncp); - - /* Check if queue is empty */ - if (mhi_ep_queue_is_empty(mdev, DMA_FROM_DEVICE)) { - netif_stop_queue(mhi_ep_netdev->ndev); ->>>>>>> - break; - } - - consume_skb(skb); -<<<<<<< - cond_resched(); - } - - return; - -exit_drop: - u64_stats_update_begin(&mhi_ep_netdev->stats.tx_syncp); - u64_stats_inc(&mhi_ep_netdev->stats.tx_dropped); - u64_stats_update_end(&mhi_ep_netdev->stats.tx_syncp); -======= - } ->>>>>>> -} - -static int mhi_ndo_open(struct net_device *ndev) -{ - /* Carrier is established via out-of-band channel (e.g. qmi) */ - netif_carrier_on(ndev); - - netif_start_queue(ndev); - - return 0; -} - -static int mhi_ndo_stop(struct net_device *ndev) -{ - netif_stop_queue(ndev); - netif_carrier_off(ndev); - - return 0; -} - -static netdev_tx_t mhi_ndo_xmit(struct sk_buff *skb, struct net_device *ndev) -{ - struct mhi_ep_net_dev *mhi_ep_netdev = netdev_priv(ndev); -<<<<<<< - unsigned long flags; - - spin_lock_irqsave(&mhi_ep_netdev->tx_lock, flags); - skb_queue_tail(&mhi_ep_netdev->tx_buffers, skb); - spin_unlock_irqrestore(&mhi_ep_netdev->tx_lock, flags); -======= - - spin_lock(&mhi_ep_netdev->tx_lock); - skb_queue_tail(&mhi_ep_netdev->tx_buffers, skb); - spin_unlock(&mhi_ep_netdev->tx_lock); ->>>>>>> - - queue_work(mhi_ep_netdev->xmit_wq, &mhi_ep_netdev->xmit_work); - - return NETDEV_TX_OK; -} - -static void mhi_ndo_get_stats64(struct net_device *ndev, - struct rtnl_link_stats64 *stats) -{ - struct mhi_ep_net_dev *mhi_ep_netdev = netdev_priv(ndev); - unsigned int start; - - do { - start = u64_stats_fetch_begin_irq(&mhi_ep_netdev->stats.rx_syncp); - stats->rx_packets = u64_stats_read(&mhi_ep_netdev->stats.rx_packets); - stats->rx_bytes = u64_stats_read(&mhi_ep_netdev->stats.rx_bytes); - stats->rx_errors = u64_stats_read(&mhi_ep_netdev->stats.rx_errors); - } while (u64_stats_fetch_retry_irq(&mhi_ep_netdev->stats.rx_syncp, start)); - - do { - start = u64_stats_fetch_begin_irq(&mhi_ep_netdev->stats.tx_syncp); - stats->tx_packets = u64_stats_read(&mhi_ep_netdev->stats.tx_packets); - stats->tx_bytes = u64_stats_read(&mhi_ep_netdev->stats.tx_bytes); - stats->tx_errors = u64_stats_read(&mhi_ep_netdev->stats.tx_errors); - stats->tx_dropped = u64_stats_read(&mhi_ep_netdev->stats.tx_dropped); - } while (u64_stats_fetch_retry_irq(&mhi_ep_netdev->stats.tx_syncp, start)); -} - -static const struct net_device_ops mhi_ep_netdev_ops = { - .ndo_open = mhi_ndo_open, - .ndo_stop = mhi_ndo_stop, - .ndo_start_xmit = mhi_ndo_xmit, - .ndo_get_stats64 = mhi_ndo_get_stats64, -}; - -static void mhi_ep_net_setup(struct net_device *ndev) -{ - ndev->header_ops = NULL; /* No header */ - ndev->type = ARPHRD_RAWIP; - ndev->hard_header_len = 0; - ndev->addr_len = 0; - ndev->flags = IFF_POINTOPOINT | IFF_NOARP; - ndev->netdev_ops = &mhi_ep_netdev_ops; - ndev->mtu = MHI_EP_DEFAULT_MTU; - ndev->min_mtu = MHI_NET_MIN_MTU; - ndev->max_mtu = MHI_NET_MAX_MTU; - ndev->tx_queue_len = 1000; -} - -<<<<<<< -======= -static struct sk_buff *mhi_ep_net_skb_agg(struct mhi_ep_net_dev *mhi_ep_netdev, - struct sk_buff *skb) -{ - struct sk_buff *head = mhi_ep_netdev->skbagg_head; - struct sk_buff *tail = mhi_ep_netdev->skbagg_tail; - - /* This is non-paged skb chaining using frag_list */ - if (!head) { - mhi_ep_netdev->skbagg_head = skb; - return skb; - } - - if (!skb_shinfo(head)->frag_list) - skb_shinfo(head)->frag_list = skb; - else - tail->next = skb; - - head->len += skb->len; - head->data_len += skb->len; - head->truesize += skb->truesize; - - mhi_ep_netdev->skbagg_tail = skb; - - return mhi_ep_netdev->skbagg_head; -} - ->>>>>>> -static void mhi_ep_net_ul_callback(struct mhi_ep_device *mhi_dev, - struct mhi_result *mhi_res) -{ - struct mhi_ep_net_dev *mhi_ep_netdev = dev_get_drvdata(&mhi_dev->dev); - struct net_device *ndev = mhi_ep_netdev->ndev; - struct sk_buff *skb; -<<<<<<< - size_t size; - - size = mhi_ep_netdev->mru ? mhi_ep_netdev->mru : READ_ONCE(ndev->mtu); - - skb = netdev_alloc_skb(ndev, size); - if (unlikely(!skb)) { - u64_stats_update_begin(&mhi_ep_netdev->stats.rx_syncp); - u64_stats_inc(&mhi_ep_netdev->stats.rx_errors); - u64_stats_update_end(&mhi_ep_netdev->stats.rx_syncp); - return; -======= - - skb = netdev_alloc_skb(ndev, 8192); - if (!skb) { - u64_stats_update_begin(&mhi_ep_netdev->stats.rx_syncp); - u64_stats_inc(&mhi_ep_netdev->stats.rx_errors); - u64_stats_update_end(&mhi_ep_netdev->stats.rx_syncp); ->>>>>>> - } - - skb_copy_to_linear_data(skb, mhi_res->buf_addr, mhi_res->bytes_xferd); - skb->len = mhi_res->bytes_xferd; - skb->dev = mhi_ep_netdev->ndev; - - if (unlikely(mhi_res->transaction_status)) { - switch (mhi_res->transaction_status) { -<<<<<<< - case -ENOTCONN: - /* MHI layer stopping/resetting the UL channel */ -======= - case -EOVERFLOW: - /* Packet can not fit in one MHI buffer and has been - * split over multiple MHI transfers, do re-aggregation. - * That usually means the device side MTU is larger than - * the host side MTU/MRU. Since this is not optimal, - * print a warning (once). - */ - netdev_warn_once(mhi_ep_netdev->ndev, - "Fragmented packets received, fix MTU?\n"); - skb_put(skb, mhi_res->bytes_xferd); - mhi_ep_net_skb_agg(mhi_ep_netdev, skb); - break; - case -ENOTCONN: - /* MHI layer stopping/resetting the DL channel */ ->>>>>>> - dev_kfree_skb_any(skb); - return; - default: - /* Unknown error, simply drop */ - dev_kfree_skb_any(skb); - u64_stats_update_begin(&mhi_ep_netdev->stats.rx_syncp); - u64_stats_inc(&mhi_ep_netdev->stats.rx_errors); - u64_stats_update_end(&mhi_ep_netdev->stats.rx_syncp); - } - } else { - skb_put(skb, mhi_res->bytes_xferd); - -<<<<<<< -======= - if (mhi_ep_netdev->skbagg_head) { - /* Aggregate the final fragment */ - skb = mhi_ep_net_skb_agg(mhi_ep_netdev, skb); - mhi_ep_netdev->skbagg_head = NULL; - } - ->>>>>>> - switch (skb->data[0] & 0xf0) { - case 0x40: - skb->protocol = htons(ETH_P_IP); - break; - case 0x60: - skb->protocol = htons(ETH_P_IPV6); - break; - default: - skb->protocol = htons(ETH_P_MAP); - break; - } - - u64_stats_update_begin(&mhi_ep_netdev->stats.rx_syncp); - u64_stats_inc(&mhi_ep_netdev->stats.rx_packets); - u64_stats_add(&mhi_ep_netdev->stats.rx_bytes, skb->len); - u64_stats_update_end(&mhi_ep_netdev->stats.rx_syncp); - netif_receive_skb(skb); - } -} - -static void mhi_ep_net_dl_callback(struct mhi_ep_device *mhi_dev, - struct mhi_result *mhi_res) -{ - struct mhi_ep_net_dev *mhi_ep_netdev = dev_get_drvdata(&mhi_dev->dev); - - if (unlikely(mhi_res->transaction_status == -ENOTCONN)) - return; - - /* Since we got enough buffers to queue, wake the queue if stopped */ - if (netif_queue_stopped(mhi_ep_netdev->ndev)) { - netif_wake_queue(mhi_ep_netdev->ndev); - queue_work(mhi_ep_netdev->xmit_wq, &mhi_ep_netdev->xmit_work); - } -} - -static int mhi_ep_net_newlink(struct mhi_ep_device *mhi_dev, struct net_device *ndev) -{ - struct mhi_ep_net_dev *mhi_ep_netdev; -<<<<<<< - int err; -======= - int ret; ->>>>>>> - - mhi_ep_netdev = netdev_priv(ndev); - - dev_set_drvdata(&mhi_dev->dev, mhi_ep_netdev); - mhi_ep_netdev->ndev = ndev; - mhi_ep_netdev->mdev = mhi_dev; -<<<<<<< - mhi_ep_netdev->mru = mhi_dev->mhi_cntrl->mru; - - skb_queue_head_init(&mhi_ep_netdev->tx_buffers); - spin_lock_init(&mhi_ep_netdev->tx_lock); -======= - mhi_ep_netdev->skbagg_head = NULL; - - skb_queue_head_init(&mhi_ep_netdev->tx_buffers); ->>>>>>> - - u64_stats_init(&mhi_ep_netdev->stats.rx_syncp); - u64_stats_init(&mhi_ep_netdev->stats.tx_syncp); - -<<<<<<< - mhi_ep_netdev->xmit_wq = alloc_workqueue("mhi_ep_net_xmit_wq", 0, WQ_HIGHPRI); - INIT_WORK(&mhi_ep_netdev->xmit_work, mhi_ep_net_dev_process_queue_packets); - - ret = register_netdev(ndev); - if (ret) - return ret; -======= - mhi_ep_netdev->xmit_wq = create_singlethread_workqueue("mhi_ep_net_xmit_wq"); - INIT_WORK(&mhi_ep_netdev->xmit_work, mhi_ep_net_dev_process_queue_packets); - err = register_netdev(ndev); - if (err) - return err; ->>>>>>> - - return 0; -} - -static void mhi_ep_net_dellink(struct mhi_ep_device *mhi_dev, struct net_device *ndev) -{ - struct mhi_ep_net_dev *mhi_ep_netdev = netdev_priv(ndev); - - destroy_workqueue(mhi_ep_netdev->xmit_wq); - unregister_netdev(ndev); -<<<<<<< - free_netdev(ndev); -======= - kfree_skb(mhi_ep_netdev->skbagg_head); ->>>>>>> - dev_set_drvdata(&mhi_dev->dev, NULL); -} - -static int mhi_ep_net_probe(struct mhi_ep_device *mhi_dev, const struct mhi_device_id *id) -{ -<<<<<<< - const struct mhi_ep_device_info *info = (struct mhi_ep_device_info *)id->driver_data; - struct net_device *ndev; - int err; - - ndev = alloc_netdev(sizeof(struct mhi_ep_net_dev), info->netname, -======= - struct net_device *ndev; - int ret; - - ndev = alloc_netdev(sizeof(struct mhi_ep_net_dev), (const char *)id->driver_data, ->>>>>>> - NET_NAME_PREDICTABLE, mhi_ep_net_setup); - if (!ndev) - return -ENOMEM; - - SET_NETDEV_DEV(ndev, &mhi_dev->dev); - -<<<<<<< - err = mhi_ep_net_newlink(mhi_dev, ndev); - if (err) { - free_netdev(ndev); - return err; -======= - ret = mhi_ep_net_newlink(mhi_dev, ndev); - if (ret) { - free_netdev(ndev); - return ret; ->>>>>>> - } - - return 0; -} - -static void mhi_ep_net_remove(struct mhi_ep_device *mhi_dev) -{ - struct mhi_ep_net_dev *mhi_ep_netdev = dev_get_drvdata(&mhi_dev->dev); - - mhi_ep_net_dellink(mhi_dev, mhi_ep_netdev->ndev); -} - -<<<<<<< -static const struct mhi_device_id mhi_ep_net_id_table[] = { - /* Software data PATH (from modem CPU) */ - { .chan = "IP_SW0", .driver_data = (kernel_ulong_t)"mhi_swip%d" }, -======= -static const struct mhi_ep_device_info mhi_swip0 = { - .netname = "mhi_swip%d", -}; - -static const struct mhi_device_id mhi_ep_net_id_table[] = { - /* Software data PATH (from modem CPU) */ - { .chan = "IP_SW0", .driver_data = (kernel_ulong_t)&mhi_swip0 }, ->>>>>>> - {} -}; -MODULE_DEVICE_TABLE(mhi, mhi_ep_net_id_table); - -static struct mhi_ep_driver mhi_ep_net_driver = { - .probe = mhi_ep_net_probe, - .remove = mhi_ep_net_remove, - .dl_xfer_cb = mhi_ep_net_dl_callback, - .ul_xfer_cb = mhi_ep_net_ul_callback, - .id_table = mhi_ep_net_id_table, - .driver = { - .name = "mhi_ep_net", - .owner = THIS_MODULE, - }, -}; - -module_mhi_ep_driver(mhi_ep_net_driver); - -<<<<<<< -MODULE_AUTHOR("Loic Poulain "); -MODULE_DESCRIPTION("Network over MHI"); -======= -MODULE_AUTHOR("Manivannan Sadhasivam "); -MODULE_DESCRIPTION("MHI Endpoint Network driver"); ->>>>>>> -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/4633b939fb86e95eb6b514e585c3a637b5de279f/preimage b/rr-cache/4633b939fb86e95eb6b514e585c3a637b5de279f/preimage deleted file mode 100644 index a5bd618..0000000 --- a/rr-cache/4633b939fb86e95eb6b514e585c3a637b5de279f/preimage +++ /dev/null @@ -1,579 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -/dts-v1/; - -#include -#include -#include "sm8150.dtsi" -#include "pmm8155au_1.dtsi" -#include "pmm8155au_2.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SA8155P ADP"; - compatible = "qcom,sa8155p-adp", "qcom,sa8155p"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vreg_3p3: vreg_3p3_regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_3p3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* - * S4A is always on and not controllable through RPMh. - * So model it as a fixed regulator. - */ - vreg_s4a_1p8: smps4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - - vin-supply = <&vreg_3p3>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xC>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; - snps,tx-sched-wrr; - - queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; - }; - - queue1 { - snps,weight = <0x11>; - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue2 { - snps,weight = <0x12>; - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue3 { - snps,weight = <0x13>; - snps,dcb-algorithm; - snps,priority = <0x3>; - }; - }; -}; - -&apps_rsc { - pmm8155au-1-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>; - vdd-l6-l9-supply = <&vreg_s6a_0p92>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s5a_2p04: smps5 { - regulator-name = "vreg_s5a_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6a_0p92: smps6 { - regulator-name = "vreg_s6a_0p92"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1a_0p752: ldo1 { - regulator-name = "vreg_l1a_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_3p1: - vreg_l2a_3p072: ldo2 { - regulator-name = "vreg_l2a_3p072"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p8: ldo3 { - regulator-name = "vreg_l3a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdd_usb_hs_core: - vdda_usb_ss_dp_core_1: - vreg_l5a_0p88: ldo5 { - regulator-name = "vreg_l5a_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7a_1p8: ldo7 { - regulator-name = "vreg_l7a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l10a_2p96: ldo10 { - regulator-name = "vreg_l10a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l11a_0p8: ldo11 { - regulator-name = "vreg_l11a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_1p8: - vreg_l12a_1p8: ldo12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p7: ldo13 { - regulator-name = "vreg_l13a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p7: ldo15 { - regulator-name = "vreg_l15a_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1704000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_2p96: ldo17 { - regulator-name = "vreg_l17a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - }; - - pmm8155au-2-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>; - vdd-l6-l9-supply = <&vreg_s6c_1p128>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s4c_1p352: smps4 { - regulator-name = "vreg_s4c_1p352"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5c_2p04: smps5 { - regulator-name = "vreg_s5c_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6c_1p128: smps6 { - regulator-name = "vreg_s6c_1p128"; - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1c_1p304: ldo1 { - regulator-name = "vreg_l1c_1p304"; - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p808: ldo2 { - regulator-name = "vreg_l2c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p2: ldo5 { - regulator-name = "vreg_l5c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7c_1p8: ldo7 { - regulator-name = "vreg_l7c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p2: ldo8 { - regulator-name = "vreg_l8c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l10c_3p3: ldo10 { - regulator-name = "vreg_l10c_3p3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l11c_0p8: ldo11 { - regulator-name = "vreg_l11c_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l12c_1p808: ldo12 { - regulator-name = "vreg_l12c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l13c_2p96: ldo13 { - regulator-name = "vreg_l13c_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l15c_1p9: ldo15 { - regulator-name = "vreg_l15c_1p9"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l16c_3p008: ldo16 { - regulator-name = "vreg_l16c_3p008"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l18c_0p88: ldo18 { - regulator-name = "vreg_l18c_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - }; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&remoteproc_adsp { - status = "okay"; - firmware-name = "qcom/sa8155p/adsp.mdt"; -}; - -&remoteproc_cdsp { - status = "okay"; - firmware-name = "qcom/sa8155p/cdsp.mdt"; -}; - -ðernet { - status = "okay"; - - snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 11000 70000>; - - snps,ptp-ref-clk-rate = <250000000>; - snps,ptp-req-clk-rate = <96000000>; - -<<<<<<< - //snps,mtl-rx-config = <&mtl_rx_setup>; - //snps,mtl-tx-config = <&mtl_tx_setup>; -======= - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; ->>>>>>> - - pinctrl-names = "default"; - pinctrl-0 = <ðernet_defaults>; - - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - - compatible = "snps,dwmac-mdio"; - - /* Micrel KSZ9031RNZ PHY */ - rgmii_phy: phy@7 { - reg = <0x7>; - -<<<<<<< - interrupt-parent = <&tlmm>; - interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ -======= - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - interrupt-parent = <&tlmm>; - interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ - ->>>>>>> - device_type = "ethernet-phy"; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l10a_2p96>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l5c_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vreg_l5a_0p88>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en1_default>; -}; - -&usb_1_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_1_qmpphy { - status = "disabled"; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en2_default>; -}; - -&usb_2_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_2_qmpphy { - status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>; - - usb2phy_ac_en1_default: usb2phy_ac_en1_default { - mux { - pins = "gpio113"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - usb2phy_ac_en2_default: usb2phy_ac_en2_default { - mux { - pins = "gpio123"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - ethernet_defaults: ethernet-defaults { - mdc { - pins = "gpio7"; - function = "rgmii"; - bias-pull-up; - }; - - mdio { - pins = "gpio59"; - function = "rgmii"; - bias-pull-up; - }; - - rgmii-rx { - pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116"; - function = "rgmii"; - bias-disable; - drive-strength = <2>; - }; - - rgmii-tx { - pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121"; - function = "rgmii"; - bias-pull-up; - drive-strength = <16>; - }; - - phy-intr { -<<<<<<< - pins = "gpio124"; -======= - pins = "gpio124"; ->>>>>>> - function = "emac_phy"; - bias-disable; - drive-strength = <8>; - }; - - pps { -<<<<<<< - pins = "gpio81"; -======= - pins = "gpio81"; ->>>>>>> - function = "emac_pps"; - bias-disable; - drive-strength = <8>; - }; - - phy-reset { -<<<<<<< - pins = "gpio79"; -======= - pins = "gpio79"; ->>>>>>> - function = "gpio"; - bias-pull-up; - drive-strength = <16>; - }; - }; -}; diff --git a/rr-cache/4633b939fb86e95eb6b514e585c3a637b5de279f/preimage.1 b/rr-cache/4633b939fb86e95eb6b514e585c3a637b5de279f/preimage.1 deleted file mode 100644 index a5bd618..0000000 --- a/rr-cache/4633b939fb86e95eb6b514e585c3a637b5de279f/preimage.1 +++ /dev/null @@ -1,579 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -/dts-v1/; - -#include -#include -#include "sm8150.dtsi" -#include "pmm8155au_1.dtsi" -#include "pmm8155au_2.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SA8155P ADP"; - compatible = "qcom,sa8155p-adp", "qcom,sa8155p"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vreg_3p3: vreg_3p3_regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_3p3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* - * S4A is always on and not controllable through RPMh. - * So model it as a fixed regulator. - */ - vreg_s4a_1p8: smps4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - - vin-supply = <&vreg_3p3>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xC>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; - snps,tx-sched-wrr; - - queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; - }; - - queue1 { - snps,weight = <0x11>; - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue2 { - snps,weight = <0x12>; - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue3 { - snps,weight = <0x13>; - snps,dcb-algorithm; - snps,priority = <0x3>; - }; - }; -}; - -&apps_rsc { - pmm8155au-1-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>; - vdd-l6-l9-supply = <&vreg_s6a_0p92>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s5a_2p04: smps5 { - regulator-name = "vreg_s5a_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6a_0p92: smps6 { - regulator-name = "vreg_s6a_0p92"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1a_0p752: ldo1 { - regulator-name = "vreg_l1a_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_3p1: - vreg_l2a_3p072: ldo2 { - regulator-name = "vreg_l2a_3p072"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p8: ldo3 { - regulator-name = "vreg_l3a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdd_usb_hs_core: - vdda_usb_ss_dp_core_1: - vreg_l5a_0p88: ldo5 { - regulator-name = "vreg_l5a_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7a_1p8: ldo7 { - regulator-name = "vreg_l7a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l10a_2p96: ldo10 { - regulator-name = "vreg_l10a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l11a_0p8: ldo11 { - regulator-name = "vreg_l11a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_1p8: - vreg_l12a_1p8: ldo12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p7: ldo13 { - regulator-name = "vreg_l13a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p7: ldo15 { - regulator-name = "vreg_l15a_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1704000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_2p96: ldo17 { - regulator-name = "vreg_l17a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - }; - - pmm8155au-2-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>; - vdd-l6-l9-supply = <&vreg_s6c_1p128>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s4c_1p352: smps4 { - regulator-name = "vreg_s4c_1p352"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5c_2p04: smps5 { - regulator-name = "vreg_s5c_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6c_1p128: smps6 { - regulator-name = "vreg_s6c_1p128"; - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1c_1p304: ldo1 { - regulator-name = "vreg_l1c_1p304"; - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p808: ldo2 { - regulator-name = "vreg_l2c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p2: ldo5 { - regulator-name = "vreg_l5c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7c_1p8: ldo7 { - regulator-name = "vreg_l7c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p2: ldo8 { - regulator-name = "vreg_l8c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l10c_3p3: ldo10 { - regulator-name = "vreg_l10c_3p3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l11c_0p8: ldo11 { - regulator-name = "vreg_l11c_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l12c_1p808: ldo12 { - regulator-name = "vreg_l12c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l13c_2p96: ldo13 { - regulator-name = "vreg_l13c_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l15c_1p9: ldo15 { - regulator-name = "vreg_l15c_1p9"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l16c_3p008: ldo16 { - regulator-name = "vreg_l16c_3p008"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l18c_0p88: ldo18 { - regulator-name = "vreg_l18c_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - }; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&remoteproc_adsp { - status = "okay"; - firmware-name = "qcom/sa8155p/adsp.mdt"; -}; - -&remoteproc_cdsp { - status = "okay"; - firmware-name = "qcom/sa8155p/cdsp.mdt"; -}; - -ðernet { - status = "okay"; - - snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 11000 70000>; - - snps,ptp-ref-clk-rate = <250000000>; - snps,ptp-req-clk-rate = <96000000>; - -<<<<<<< - //snps,mtl-rx-config = <&mtl_rx_setup>; - //snps,mtl-tx-config = <&mtl_tx_setup>; -======= - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; ->>>>>>> - - pinctrl-names = "default"; - pinctrl-0 = <ðernet_defaults>; - - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - - compatible = "snps,dwmac-mdio"; - - /* Micrel KSZ9031RNZ PHY */ - rgmii_phy: phy@7 { - reg = <0x7>; - -<<<<<<< - interrupt-parent = <&tlmm>; - interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ -======= - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - interrupt-parent = <&tlmm>; - interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ - ->>>>>>> - device_type = "ethernet-phy"; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l10a_2p96>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l5c_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vreg_l5a_0p88>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en1_default>; -}; - -&usb_1_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_1_qmpphy { - status = "disabled"; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en2_default>; -}; - -&usb_2_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_2_qmpphy { - status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>; - - usb2phy_ac_en1_default: usb2phy_ac_en1_default { - mux { - pins = "gpio113"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - usb2phy_ac_en2_default: usb2phy_ac_en2_default { - mux { - pins = "gpio123"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - ethernet_defaults: ethernet-defaults { - mdc { - pins = "gpio7"; - function = "rgmii"; - bias-pull-up; - }; - - mdio { - pins = "gpio59"; - function = "rgmii"; - bias-pull-up; - }; - - rgmii-rx { - pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116"; - function = "rgmii"; - bias-disable; - drive-strength = <2>; - }; - - rgmii-tx { - pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121"; - function = "rgmii"; - bias-pull-up; - drive-strength = <16>; - }; - - phy-intr { -<<<<<<< - pins = "gpio124"; -======= - pins = "gpio124"; ->>>>>>> - function = "emac_phy"; - bias-disable; - drive-strength = <8>; - }; - - pps { -<<<<<<< - pins = "gpio81"; -======= - pins = "gpio81"; ->>>>>>> - function = "emac_pps"; - bias-disable; - drive-strength = <8>; - }; - - phy-reset { -<<<<<<< - pins = "gpio79"; -======= - pins = "gpio79"; ->>>>>>> - function = "gpio"; - bias-pull-up; - drive-strength = <16>; - }; - }; -}; diff --git a/rr-cache/4633b939fb86e95eb6b514e585c3a637b5de279f/preimage.2 b/rr-cache/4633b939fb86e95eb6b514e585c3a637b5de279f/preimage.2 deleted file mode 100644 index a5bd618..0000000 --- a/rr-cache/4633b939fb86e95eb6b514e585c3a637b5de279f/preimage.2 +++ /dev/null @@ -1,579 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -/dts-v1/; - -#include -#include -#include "sm8150.dtsi" -#include "pmm8155au_1.dtsi" -#include "pmm8155au_2.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SA8155P ADP"; - compatible = "qcom,sa8155p-adp", "qcom,sa8155p"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vreg_3p3: vreg_3p3_regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_3p3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* - * S4A is always on and not controllable through RPMh. - * So model it as a fixed regulator. - */ - vreg_s4a_1p8: smps4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - - vin-supply = <&vreg_3p3>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xC>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; - snps,tx-sched-wrr; - - queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; - }; - - queue1 { - snps,weight = <0x11>; - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue2 { - snps,weight = <0x12>; - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue3 { - snps,weight = <0x13>; - snps,dcb-algorithm; - snps,priority = <0x3>; - }; - }; -}; - -&apps_rsc { - pmm8155au-1-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>; - vdd-l6-l9-supply = <&vreg_s6a_0p92>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s5a_2p04: smps5 { - regulator-name = "vreg_s5a_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6a_0p92: smps6 { - regulator-name = "vreg_s6a_0p92"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1a_0p752: ldo1 { - regulator-name = "vreg_l1a_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_3p1: - vreg_l2a_3p072: ldo2 { - regulator-name = "vreg_l2a_3p072"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p8: ldo3 { - regulator-name = "vreg_l3a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdd_usb_hs_core: - vdda_usb_ss_dp_core_1: - vreg_l5a_0p88: ldo5 { - regulator-name = "vreg_l5a_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7a_1p8: ldo7 { - regulator-name = "vreg_l7a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l10a_2p96: ldo10 { - regulator-name = "vreg_l10a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l11a_0p8: ldo11 { - regulator-name = "vreg_l11a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_1p8: - vreg_l12a_1p8: ldo12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p7: ldo13 { - regulator-name = "vreg_l13a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p7: ldo15 { - regulator-name = "vreg_l15a_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1704000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_2p96: ldo17 { - regulator-name = "vreg_l17a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - }; - - pmm8155au-2-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>; - vdd-l6-l9-supply = <&vreg_s6c_1p128>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s4c_1p352: smps4 { - regulator-name = "vreg_s4c_1p352"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5c_2p04: smps5 { - regulator-name = "vreg_s5c_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6c_1p128: smps6 { - regulator-name = "vreg_s6c_1p128"; - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1c_1p304: ldo1 { - regulator-name = "vreg_l1c_1p304"; - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p808: ldo2 { - regulator-name = "vreg_l2c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p2: ldo5 { - regulator-name = "vreg_l5c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7c_1p8: ldo7 { - regulator-name = "vreg_l7c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p2: ldo8 { - regulator-name = "vreg_l8c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l10c_3p3: ldo10 { - regulator-name = "vreg_l10c_3p3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l11c_0p8: ldo11 { - regulator-name = "vreg_l11c_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l12c_1p808: ldo12 { - regulator-name = "vreg_l12c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l13c_2p96: ldo13 { - regulator-name = "vreg_l13c_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l15c_1p9: ldo15 { - regulator-name = "vreg_l15c_1p9"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l16c_3p008: ldo16 { - regulator-name = "vreg_l16c_3p008"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l18c_0p88: ldo18 { - regulator-name = "vreg_l18c_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - }; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&remoteproc_adsp { - status = "okay"; - firmware-name = "qcom/sa8155p/adsp.mdt"; -}; - -&remoteproc_cdsp { - status = "okay"; - firmware-name = "qcom/sa8155p/cdsp.mdt"; -}; - -ðernet { - status = "okay"; - - snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 11000 70000>; - - snps,ptp-ref-clk-rate = <250000000>; - snps,ptp-req-clk-rate = <96000000>; - -<<<<<<< - //snps,mtl-rx-config = <&mtl_rx_setup>; - //snps,mtl-tx-config = <&mtl_tx_setup>; -======= - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; ->>>>>>> - - pinctrl-names = "default"; - pinctrl-0 = <ðernet_defaults>; - - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - - compatible = "snps,dwmac-mdio"; - - /* Micrel KSZ9031RNZ PHY */ - rgmii_phy: phy@7 { - reg = <0x7>; - -<<<<<<< - interrupt-parent = <&tlmm>; - interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ -======= - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - interrupt-parent = <&tlmm>; - interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ - ->>>>>>> - device_type = "ethernet-phy"; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l10a_2p96>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l5c_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vreg_l5a_0p88>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en1_default>; -}; - -&usb_1_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_1_qmpphy { - status = "disabled"; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en2_default>; -}; - -&usb_2_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_2_qmpphy { - status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>; - - usb2phy_ac_en1_default: usb2phy_ac_en1_default { - mux { - pins = "gpio113"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - usb2phy_ac_en2_default: usb2phy_ac_en2_default { - mux { - pins = "gpio123"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - ethernet_defaults: ethernet-defaults { - mdc { - pins = "gpio7"; - function = "rgmii"; - bias-pull-up; - }; - - mdio { - pins = "gpio59"; - function = "rgmii"; - bias-pull-up; - }; - - rgmii-rx { - pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116"; - function = "rgmii"; - bias-disable; - drive-strength = <2>; - }; - - rgmii-tx { - pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121"; - function = "rgmii"; - bias-pull-up; - drive-strength = <16>; - }; - - phy-intr { -<<<<<<< - pins = "gpio124"; -======= - pins = "gpio124"; ->>>>>>> - function = "emac_phy"; - bias-disable; - drive-strength = <8>; - }; - - pps { -<<<<<<< - pins = "gpio81"; -======= - pins = "gpio81"; ->>>>>>> - function = "emac_pps"; - bias-disable; - drive-strength = <8>; - }; - - phy-reset { -<<<<<<< - pins = "gpio79"; -======= - pins = "gpio79"; ->>>>>>> - function = "gpio"; - bias-pull-up; - drive-strength = <16>; - }; - }; -}; diff --git a/rr-cache/491429b1ad33dfa52bf5626de448a4ae7d3a98ea/preimage b/rr-cache/491429b1ad33dfa52bf5626de448a4ae7d3a98ea/preimage deleted file mode 100644 index b416345..0000000 --- a/rr-cache/491429b1ad33dfa52bf5626de448a4ae7d3a98ea/preimage +++ /dev/null @@ -1,791 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * SDX55 SoC device tree source - * - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Copyright (c) 2020, Linaro Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; - interrupt-parent = <&intc>; - - memory { - device_type = "memory"; - reg = <0 0>; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - - nand_clk_dummy: nand-clk-dummy { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - enable-method = "psci"; - clocks = <&apcs>; - power-domains = <&rpmhpd SDX55_CX>; - power-domain-names = "rpmhpd"; - operating-points-v2 = <&cpu_opp_table>; - }; - }; - - cpu_opp_table: cpu-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-345600000 { - opp-hz = /bits/ 64 <345600000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-1094400000 { - opp-hz = /bits/ 64 <1094400000>; - required-opps = <&rpmhpd_opp_nom>; - }; - - opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - required-opps = <&rpmhpd_opp_turbo>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-sdx55", "qcom,scm"; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - hyp_mem: memory@8fc00000 { - no-map; - reg = <0x8fc00000 0x80000>; - }; - - ac_db_mem: memory@8fc80000 { - no-map; - reg = <0x8fc80000 0x40000>; - }; - - secdata_mem: memory@8fcfd000 { - no-map; - reg = <0x8fcfd000 0x1000>; - }; - - sbl_mem: memory@8fd00000 { - no-map; - reg = <0x8fd00000 0x100000>; - }; - - aop_image: memory@8fe00000 { - no-map; - reg = <0x8fe00000 0x20000>; - }; - - aop_cmd_db: memory@8fe20000 { - compatible = "qcom,cmd-db"; - reg = <0x8fe20000 0x20000>; - no-map; - }; - - smem_mem: memory@8fe40000 { - no-map; - reg = <0x8fe40000 0xc0000>; - }; - - tz_mem: memory@8ff00000 { - no-map; - reg = <0x8ff00000 0x100000>; - }; - - tz_apps_mem: memory@90000000 { - no-map; - reg = <0x90000000 0x500000>; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = ; - mboxes = <&apcs 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdx55"; - reg = <0x100000 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; - }; - - blsp1_uart3: serial@831000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x00831000 0x200>; - interrupts = ; - clocks = <&gcc 30>, - <&gcc 9>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - usb_hsphy: phy@ff4000 { - compatible = "qcom,usb-snps-hs-7nm-phy"; - reg = <0x00ff4000 0x114>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_BCR>; - }; - - usb_qmpphy: phy@ff6000 { - compatible = "qcom,sdx55-qmp-usb3-uni-phy"; - reg = <0x00ff6000 0x1c0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_USB3PHY_PHY_BCR>, - <&gcc GCC_USB3_PHY_BCR>; - reset-names = "phy", "common"; - - usb_ssphy: phy@ff6200 { - reg = <0x00ff6200 0x170>, - <0x00ff6400 0x200>, - <0x00ff6800 0x800>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - mc_virt: interconnect@1100000 { - compatible = "qcom,sdx55-mc-virt"; - reg = <0x01100000 0x400000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mem_noc: interconnect@9680000 { - compatible = "qcom,sdx55-mem-noc"; - reg = <0x09680000 0x40000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@162c000 { - compatible = "qcom,sdx55-system-noc"; - reg = <0x0162c000 0x31200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sdx55-ipa-virt"; - reg = <0x01e00000 0x100000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - qpic_bam: dma-controller@1b04000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x01b04000 0x1c000>; - interrupts = ; - clocks = <&rpmhcc RPMH_QPIC_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - status = "disabled"; - }; - - qpic_nand: nand-controller@1b30000 { - compatible = "qcom,sdx55-nand"; - reg = <0x01b30000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&rpmhcc RPMH_QPIC_CLK>, - <&nand_clk_dummy>; - clock-names = "core", "aon"; - - dmas = <&qpic_bam 0>, - <&qpic_bam 1>, - <&qpic_bam 2>; - dma-names = "tx", "rx", "cmd"; - status = "disabled"; - }; - - pcie0_phy: phy@1c07000 { - compatible = "qcom,sdx55-qmp-pcie-phy"; - reg = <0x01c07000 0x1c4>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE_RCHNG_PHY_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie0_lane: lanes@1c06000 { - reg = <0x01c06000 0x104>, /* tx0 */ - <0x01c06200 0x328>, /* rx0 */ - <0x01c07200 0x1e8>, /* pcs */ - <0x01c06800 0x104>, /* tx1 */ - <0x01c06a00 0x328>, /* rx1 */ - <0x01c07600 0x800>; /* pcs_misc */ - clocks = <&gcc GCC_PCIE_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_pipe_clk"; - }; - }; - - ipa: ipa@1e40000 { - compatible = "qcom,sdx55-ipa"; - - iommus = <&apps_smmu 0x5e0 0x0>, - <&apps_smmu 0x5e2 0x0>; - reg = <0x1e40000 0x7000>, - <0x1e50000 0x4b20>, - <0x1e04000 0x2c000>; - reg-names = "ipa-reg", - "ipa-shared", - "gsi"; - - interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, - <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ipa", - "gsi", - "ipa-clock-query", - "ipa-setup-ready"; - - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - - interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>, - <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, - <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>; - interconnect-names = "memory", - "imem", - "config"; - - qcom,smem-states = <&ipa_smp2p_out 0>, - <&ipa_smp2p_out 1>; - qcom,smem-state-names = "ipa-clock-enabled-valid", - "ipa-clock-enabled"; - - status = "disabled"; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x01f40000 0x40000>; - #hwlock-cells = <1>; - }; - - tcsr: syscon@1fcb000 { - compatible = "syscon"; - reg = <0x01fc0000 0x1000>; - }; - - sdhc_1: sdhci@8804000 { - compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x08804000 0x1000>; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>; - clock-names = "iface", "core"; - status = "disabled"; - }; - - pcie_ep: pcie-ep@40000000 { - compatible = "qcom,sdx55-pcie-ep"; - reg = <0x01c00000 0x3000>, - <0x40000000 0xf1d>, - <0x40000f20 0xc8>, - <0x40001000 0x1000>, -<<<<<<< - <0x40002000 0x10000>, -======= - <0x40200000 0x100000>, ->>>>>>> - <0x01c03000 0x3000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", - "mmio"; - - qcom,perst-regs = <&tcsr 0xb258 0xb270>; - - clocks = <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; - - interrupts = , - ; - interrupt-names = "global", "doorbell"; - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_PCIE_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; - phy-names = "pciephy"; - max-link-speed = <3>; - num-lanes = <2>; - - status = "disabled"; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sdx55-mpss-pas"; - reg = <0x04080000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SDX55_CX>, - <&rpmhpd SDX55_MSS>; - power-domain-names = "cx", "mss"; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "mpss"; - qcom,remote-pid = <1>; - mboxes = <&apcs 15>; - }; - }; - - usb: usb@a6f8800 { - compatible = "qcom,sdx55-dwc3", "qcom,dwc3"; - reg = <0x0a6f8800 0x400>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, - <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_USB30_MSTR_AXI_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_GDSC>; - - resets = <&gcc GCC_USB30_BCR>; - - usb_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0x0a600000 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x1a0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_hsphy>, <&usb_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - pdc: interrupt-controller@b210000 { - compatible = "qcom,sdx55-pdc", "qcom,pdc"; - reg = <0x0b210000 0x30000>; - qcom,pdc-ranges = <0 179 52>; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - restart@c264000 { - compatible = "qcom,pshold"; - reg = <0x0c264000 0x1000>; - }; - - spmi_bus: qcom,spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0c440000 0x0000d00>, - <0x0c600000 0x2000000>, - <0x0e600000 0x0100000>, - <0x0e700000 0x00a0000>, - <0x0c40a000 0x0000700>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sdx55-pinctrl"; - reg = <0xf100000 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - imem@1468f000 { - compatible = "simple-mfd"; - reg = <0x1468f000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x0 0x1468f000 0x1000>; - - pil-reloc@94c { - compatible = "qcom,pil-reloc-info"; - reg = <0x94c 0x200>; - }; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sdx55-smmu-500", "arm,mmu-500"; - reg = <0x15000000 0x20000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - intc: interrupt-controller@17800000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - interrupt-parent = <&intc>; - #interrupt-cells = <3>; - reg = <0x17800000 0x1000>, - <0x17802000 0x1000>; - }; - - a7pll: clock@17808000 { - compatible = "qcom,sdx55-a7pll"; - reg = <0x17808000 0x1000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "bi_tcxo"; - #clock-cells = <0>; - }; - - apcs: mailbox@17810000 { - compatible = "qcom,sdx55-apcs-gcc", "syscon"; - reg = <0x17810000 0x2000>; - #mbox-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; - clock-names = "ref", "pll", "aux"; - #clock-cells = <0>; - }; - - watchdog@17817000 { - compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; - reg = <0x17817000 0x1000>; - clocks = <&sleep_clk>; - }; - - timer@17820000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x17820000 0x1000>; - clock-frequency = <19200000>; - - frame@17821000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x17821000 0x1000>, - <0x17822000 0x1000>; - }; - - frame@17823000 { - frame-number = <1>; - interrupts = ; - reg = <0x17823000 0x1000>; - status = "disabled"; - }; - - frame@17824000 { - frame-number = <2>; - interrupts = ; - reg = <0x17824000 0x1000>; - status = "disabled"; - }; - - frame@17825000 { - frame-number = <3>; - interrupts = ; - reg = <0x17825000 0x1000>; - status = "disabled"; - }; - - frame@17826000 { - frame-number = <4>; - interrupts = ; - reg = <0x17826000 0x1000>; - status = "disabled"; - }; - - frame@17827000 { - frame-number = <5>; - interrupts = ; - reg = <0x17827000 0x1000>; - status = "disabled"; - }; - - frame@17828000 { - frame-number = <6>; - interrupts = ; - reg = <0x17828000 0x1000>; - status = "disabled"; - }; - - frame@17829000 { - frame-number = <7>; - interrupts = ; - reg = <0x17829000 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@17840000 { - compatible = "qcom,rpmh-rsc"; - reg = <0x17830000 0x10000>, <0x17840000 0x10000>; - reg-names = "drv-0", "drv-1"; - interrupts = , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <1>; - qcom,tcs-config = , , - , ; - - rpmhcc: clock-controller { - compatible = "qcom,sdx55-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sdx55-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <19200000>; - }; -}; diff --git a/rr-cache/49b87c48bf2ac9331db89b2d5c14b64e2a07542a/preimage.1 b/rr-cache/49b87c48bf2ac9331db89b2d5c14b64e2a07542a/preimage.1 deleted file mode 100644 index 482c273..0000000 --- a/rr-cache/49b87c48bf2ac9331db89b2d5c14b64e2a07542a/preimage.1 +++ /dev/null @@ -1,121 +0,0 @@ -<<<<<<< -# The config is based on running daily CI for enterprise Linux distros to -# seek regressions on linux-next builds on different bare-metal and virtual -# platforms. It can be used for example, -# -# $ make ARCH=arm64 defconfig debug.config -# -# Keep alphabetically sorted inside each section. -# -# printk and dmesg options -# -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_PRINTK_CALLER=y -CONFIG_PRINTK_TIME=y -CONFIG_SYMBOLIC_ERRNAME=y -# -# Compile-time checks and compiler options -# -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_FRAME_WARN=2048 -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# -# Generic Kernel Debugging Instruments -# -# CONFIG_UBSAN_ALIGNMENT is not set -# CONFIG_UBSAN_DIV_ZERO is not set -# CONFIG_UBSAN_TRAP is not set -# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_FS_ALLOW_ALL=y -CONFIG_DEBUG_IRQFLAGS=y -CONFIG_UBSAN=y -CONFIG_UBSAN_BOOL=y -CONFIG_UBSAN_BOUNDS=y -CONFIG_UBSAN_ENUM=y -CONFIG_UBSAN_SHIFT=y -CONFIG_UBSAN_UNREACHABLE=y -# -# Memory Debugging -# -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF is not set -# CONFIG_DEBUG_RODATA_TEST is not set -# CONFIG_DEBUG_WX is not set -# CONFIG_KFENCE is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_SLUB_STATS is not set -CONFIG_PAGE_EXTENSION=y -CONFIG_PAGE_OWNER=y -CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y -CONFIG_DEBUG_OBJECTS=y -CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 -CONFIG_DEBUG_OBJECTS_FREE=y -CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y -CONFIG_DEBUG_OBJECTS_RCU_HEAD=y -CONFIG_DEBUG_OBJECTS_TIMERS=y -CONFIG_DEBUG_OBJECTS_WORK=y -CONFIG_DEBUG_PER_CPU_MAPS=y -CONFIG_DEBUG_STACK_USAGE=y -CONFIG_DEBUG_VIRTUAL=y -CONFIG_DEBUG_VM=y -CONFIG_DEBUG_VM_PGFLAGS=y -CONFIG_DEBUG_VM_RB=y -CONFIG_DEBUG_VM_VMACACHE=y -CONFIG_GENERIC_PTDUMP=y -CONFIG_KASAN=y -CONFIG_KASAN_GENERIC=y -CONFIG_KASAN_INLINE=y -CONFIG_KASAN_VMALLOC=y -CONFIG_PTDUMP_DEBUGFS=y -CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_SLUB_DEBUG_ON=y -# -# Debug Oops, Lockups and Hangs -# -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_PANIC_ON_OOPS=y -CONFIG_PANIC_TIMEOUT=0 -CONFIG_SOFTLOCKUP_DETECTOR=y -# -# Lock Debugging (spinlocks, mutexes, etc...) -# -# CONFIG_PROVE_RAW_LOCK_NESTING is not set -CONFIG_PROVE_LOCKING=y -# -# Debug kernel data structures -# -CONFIG_BUG_ON_DATA_CORRUPTION=y -# -# RCU Debugging -# -CONFIG_PROVE_RCU=y -CONFIG_PROVE_RCU_LIST=y -# -# Tracers -# -CONFIG_BRANCH_PROFILE_NONE=y -CONFIG_DYNAMIC_FTRACE=y -CONFIG_FTRACE=y -CONFIG_FUNCTION_TRACER=y -======= -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_DEBUG_PAGEALLOC=y -CONFIG_DEBUG_LOCK_ALLOC=y -CONFIG_PROVE_LOCKING=y -CONFIG_PROVE_RCU=y -CONFIG_SLUB_DEBUG=y -CONFIG_SLUB_DEBUG_ON=y -CONFIG_KASAN=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_USB_GADGET_DEBUG=y -CONFIG_USB_GADGET_DEBUG_FILES=y ->>>>>>> diff --git a/rr-cache/525bf386cbe2f3528cd23f14e44f72d9a6f48474/preimage b/rr-cache/525bf386cbe2f3528cd23f14e44f72d9a6f48474/preimage deleted file mode 100644 index 974e2a2..0000000 --- a/rr-cache/525bf386cbe2f3528cd23f14e44f72d9a6f48474/preimage +++ /dev/null @@ -1,3865 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "reset.h" -#include "gdsc.h" - -enum { - P_BI_TCXO, - P_AUD_REF_CLK, - P_CORE_BI_PLL_TEST_SE, - P_GPLL0_OUT_EVEN, - P_GPLL0_OUT_MAIN, - P_GPLL7_OUT_MAIN, - P_GPLL9_OUT_MAIN, - P_SLEEP_CLK, -}; - -static struct clk_alpha_pll gpll0 = { - .offset = 0x0, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_trion_even[] = { - { 0x0, 1 }, - { 0x1, 2 }, - { 0x3, 4 }, - { 0x7, 8 }, - { } -}; - -static struct clk_alpha_pll_postdiv gpll0_out_even = { - .offset = 0x0, - .post_div_shift = 8, - .post_div_table = post_div_table_trion_even, - .num_post_div = ARRAY_SIZE(post_div_table_trion_even), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .width = 4, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll0_out_even", - .parent_hws = (const struct clk_hw*[]){ - &gpll0.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_postdiv_trion_ops, - }, -}; - -static struct clk_alpha_pll gpll7 = { - .offset = 0x1a000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gpll7", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll9 = { - .offset = 0x1c000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gpll9", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static const struct parent_map gcc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_0[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_SLEEP_CLK, 5 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_1[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "sleep_clk", .name = "sleep_clk" }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_SLEEP_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_2[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "sleep_clk", .name = "sleep_clk" }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_3[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_3[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se"}, -}; - -static const struct parent_map gcc_parent_map_4[] = { - { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_4[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_5[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL7_OUT_MAIN, 3 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_5[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll7.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_6[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL9_OUT_MAIN, 2 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_6[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll9.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_7[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_AUD_REF_CLK, 2 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_7[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { - .cmd_rcgr = 0x48014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), - F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_emac_ptp_clk_src = { - .cmd_rcgr = 0x6038, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_emac_ptp_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_emac_ptp_clk_src", - .parent_data = gcc_parents_5, - .num_parents = ARRAY_SIZE(gcc_parents_5), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { - F(2500000, P_BI_TCXO, 1, 25, 192), - F(5000000, P_BI_TCXO, 1, 25, 96), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), - F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_emac_rgmii_clk_src = { - .cmd_rcgr = 0x601c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_emac_rgmii_clk_src", - .parent_data = gcc_parents_5, - .num_parents = ARRAY_SIZE(gcc_parents_5), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_gp1_clk_src = { - .cmd_rcgr = 0x64004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp2_clk_src = { - .cmd_rcgr = 0x65004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp3_clk_src = { - .cmd_rcgr = 0x66004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { - .cmd_rcgr = 0x6b02c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { - .cmd_rcgr = 0x8d02c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { - .cmd_rcgr = 0x6f014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_phy_refgen_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pdm2_clk_src = { - .cmd_rcgr = 0x33010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pdm2_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_qspi_core_clk_src = { - .cmd_rcgr = 0x4b008, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qspi_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { - F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), - F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), - F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), - F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), - F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), - F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), - F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), - F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), - F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), - F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), - F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), - F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), - F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), - { } -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { - .cmd_rcgr = 0x17148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { - .cmd_rcgr = 0x17278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { - .cmd_rcgr = 0x173a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { - .cmd_rcgr = 0x174d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { - .cmd_rcgr = 0x17608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { - .cmd_rcgr = 0x17738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { - .cmd_rcgr = 0x17868, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s6_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { - .cmd_rcgr = 0x17998, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s7_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { - .cmd_rcgr = 0x18148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { - .cmd_rcgr = 0x18278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { - .cmd_rcgr = 0x183a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { - .cmd_rcgr = 0x184d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { - .cmd_rcgr = 0x18608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { - .cmd_rcgr = 0x18738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { - .cmd_rcgr = 0x1e148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { - .cmd_rcgr = 0x1e278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { - .cmd_rcgr = 0x1e3a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { - .cmd_rcgr = 0x1e4d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { - .cmd_rcgr = 0x1e608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { - .cmd_rcgr = 0x1e738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { - F(400000, P_BI_TCXO, 12, 1, 4), - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { - .cmd_rcgr = 0x1400c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_6, - .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk_src", - .parent_data = gcc_parents_6, - .num_parents = ARRAY_SIZE(gcc_parents_6), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_floor_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { - F(400000, P_BI_TCXO, 12, 1, 4), - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { - .cmd_rcgr = 0x1600c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_3, - .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_apps_clk_src", - .parent_data = gcc_parents_3, - .num_parents = ARRAY_SIZE(gcc_parents_3), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_floor_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { - F(105495, P_BI_TCXO, 2, 1, 91), - { } -}; - -static struct clk_rcg2 gcc_tsif_ref_clk_src = { - .cmd_rcgr = 0x36010, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_7, - .freq_tbl = ftbl_gcc_tsif_ref_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ref_clk_src", - .parent_data = gcc_parents_7, - .num_parents = ARRAY_SIZE(gcc_parents_7), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { - .cmd_rcgr = 0x75020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { - .cmd_rcgr = 0x75060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { - .cmd_rcgr = 0x75094, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_clk_src", - .parent_data = gcc_parents_4, - .num_parents = ARRAY_SIZE(gcc_parents_4), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { - .cmd_rcgr = 0x75078, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { - .cmd_rcgr = 0x77020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { - .cmd_rcgr = 0x77060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { - .cmd_rcgr = 0x77094, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk_src", - .parent_data = gcc_parents_4, - .num_parents = ARRAY_SIZE(gcc_parents_4), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { - .cmd_rcgr = 0x77078, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { - F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), - F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), - F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { - .cmd_rcgr = 0xf01c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), - F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { - .cmd_rcgr = 0xf034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { - .cmd_rcgr = 0x1001c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_master_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { - .cmd_rcgr = 0x10034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_mock_utmi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { - .cmd_rcgr = 0xf060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { - .cmd_rcgr = 0x10060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { - .halt_reg = 0x90018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x90018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_noc_pcie_tbu_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_card_axi_clk = { - .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x750c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x750c0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_card_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { - .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x750c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x750c0, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_aggre_ufs_card_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { - .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x770c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x770c0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x770c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x770c0, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_aggre_ufs_phy_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { - .halt_reg = 0xf07c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf07c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { - .halt_reg = 0x1007c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1007c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_usb3_sec_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_boot_rom_ahb_clk = { - .halt_reg = 0x38004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x38004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_boot_rom_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for camss boot - */ -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0xb008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_hf_axi_clk = { - .halt_reg = 0xb030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_sf_axi_clk = { - .halt_reg = 0xb034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_sf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to camss, so no need to poll */ -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0xb044, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb044, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { - .halt_reg = 0xf078, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { - .halt_reg = 0x10078, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_sec_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_ahb_clk = { - .halt_reg = 0x48000, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw }, - .num_parents = 1, - /* required for cpuss */ - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_dvm_bus_clk = { - .halt_reg = 0x48190, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48190, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_dvm_bus_clk", - /* required for cpuss */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_gnoc_clk = { - .halt_reg = 0x48004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x48004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_gnoc_clk", - /* required for cpuss */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_rbcpr_clk = { - .halt_reg = 0x48008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_rbcpr_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ddrss_gpu_axi_clk = { - .halt_reg = 0x71154, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x71154, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ddrss_gpu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for disp boot - */ -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0xb00c, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb00c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_hf_axi_clk = { - .halt_reg = 0xb038, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_sf_axi_clk = { - .halt_reg = 0xb03c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb03c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_sf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to disp, so no need to poll */ -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0xb048, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_axi_clk = { - .halt_reg = 0x6010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_ptp_clk = { - .halt_reg = 0x6034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_ptp_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_emac_ptp_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_rgmii_clk = { - .halt_reg = 0x6018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_rgmii_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_emac_rgmii_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_slv_ahb_clk = { - .halt_reg = 0x6014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x6014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x6014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_slv_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp1_clk = { - .halt_reg = 0x64000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x64000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp2_clk = { - .halt_reg = 0x65000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x65000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp3_clk = { - .halt_reg = 0x66000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x66000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x71004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x71004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x71004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - /* required for gpu */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0_out_even.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_iref_clk = { - .halt_reg = 0x8c010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_iref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_memnoc_gfx_clk = { - .halt_reg = 0x7100c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7100c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_memnoc_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { - .halt_reg = 0x71018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x71018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_snoc_dvm_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_at_clk = { - .halt_reg = 0x4d010, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_at_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_axi_clk = { - .halt_reg = 0x4d008, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_cfg_ahb_clk = { - .halt_reg = 0x4d004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x4d004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x4d004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_cfg_ahb_clk", - /* required for npu */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(18), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(19), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0_out_even.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_trig_clk = { - .halt_reg = 0x4d00c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_trig_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie0_phy_refgen_clk = { - .halt_reg = 0x6f02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie0_phy_refgen_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_phy_refgen_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie1_phy_refgen_clk = { - .halt_reg = 0x6f030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie1_phy_refgen_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_phy_refgen_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_aux_clk = { - .halt_reg = 0x6b020, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { - .halt_reg = 0x6b01c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x6b01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_clkref_clk = { - .halt_reg = 0x8c00c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_mstr_axi_clk = { - .halt_reg = 0x6b018, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_mstr_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ -static struct clk_branch gcc_pcie_0_pipe_clk = { - .halt_reg = 0x6b024, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_axi_clk = { - .halt_reg = 0x6b014, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x6b014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_slv_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { - .halt_reg = 0x6b010, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_slv_q2a_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_aux_clk = { - .halt_reg = 0x8d020, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(29), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_1_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { - .halt_reg = 0x8d01c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8d01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(28), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_clkref_clk = { - .halt_reg = 0x8c02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_mstr_axi_clk = { - .halt_reg = 0x8d018, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_mstr_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ -static struct clk_branch gcc_pcie_1_pipe_clk = { - .halt_reg = 0x8d024, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(30), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_axi_clk = { - .halt_reg = 0x8d014, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8d014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_slv_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { - .halt_reg = 0x8d010, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_slv_q2a_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_phy_aux_clk = { - .halt_reg = 0x6f004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm2_clk = { - .halt_reg = 0x3300c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3300c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pdm2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_ahb_clk = { - .halt_reg = 0x33004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x33004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x33004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_xo4_clk = { - .halt_reg = 0x33008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_xo4_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_prng_ahb_clk = { - .halt_reg = 0x34004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_prng_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { - .halt_reg = 0xb018, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb018, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_camera_nrt_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { - .halt_reg = 0xb01c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb01c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_camera_rt_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_disp_ahb_clk = { - .halt_reg = 0xb020, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb020, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb020, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_disp_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { - .halt_reg = 0xb010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_video_cvp_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { - .halt_reg = 0xb014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_video_vcodec_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { - .halt_reg = 0x4b000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4b000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_cnoc_periph_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_core_clk = { - .halt_reg = 0x4b004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4b004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qspi_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s0_clk = { - .halt_reg = 0x17144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s1_clk = { - .halt_reg = 0x17274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s2_clk = { - .halt_reg = 0x173a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s3_clk = { - .halt_reg = 0x174d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s4_clk = { - .halt_reg = 0x17604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(14), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s5_clk = { - .halt_reg = 0x17734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s6_clk = { - .halt_reg = 0x17864, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s6_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s6_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s7_clk = { - .halt_reg = 0x17994, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s7_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s7_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s0_clk = { - .halt_reg = 0x18144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s1_clk = { - .halt_reg = 0x18274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(23), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s2_clk = { - .halt_reg = 0x183a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(24), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s3_clk = { - .halt_reg = 0x184d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s4_clk = { - .halt_reg = 0x18604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s5_clk = { - .halt_reg = 0x18734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s0_clk = { - .halt_reg = 0x1e144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s1_clk = { - .halt_reg = 0x1e274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s2_clk = { - .halt_reg = 0x1e3a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s3_clk = { - .halt_reg = 0x1e4d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s4_clk = { - .halt_reg = 0x1e604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(8), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s5_clk = { - .halt_reg = 0x1e734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { - .halt_reg = 0x17004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { - .halt_reg = 0x18004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(20), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { - .halt_reg = 0x18008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x18008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { - .halt_reg = 0x1e004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_2_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { - .halt_reg = 0x1e008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x1e008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_2_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_ahb_clk = { - .halt_reg = 0x14008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_apps_clk = { - .halt_reg = 0x14004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_sdcc2_apps_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_ahb_clk = { - .halt_reg = 0x16008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_apps_clk = { - .halt_reg = 0x16004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_apps_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_sdcc4_apps_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x4819c, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw }, - .num_parents = 1, - /* required for cpuss */ - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_inactivity_timers_clk = { - .halt_reg = 0x3600c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3600c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_inactivity_timers_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ref_clk = { - .halt_reg = 0x36008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ref_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_tsif_ref_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ahb_clk = { - .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_axi_clk = { - .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { - .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_clkref_clk = { - .halt_reg = 0x8c004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ice_core_clk = { - .halt_reg = 0x7505c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7505c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7505c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_ice_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { - .halt_reg = 0x7505c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7505c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7505c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_ice_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_phy_aux_clk = { - .halt_reg = 0x75090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75090, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { - .halt_reg = 0x75090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75090, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_phy_aux_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x7501c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_rx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x750ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_rx_symbol_1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x75018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_tx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_unipro_core_clk = { - .halt_reg = 0x75058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_unipro_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { - .halt_reg = 0x75058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75058, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_unipro_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_mem_clkref_clk = { - .halt_reg = 0x8c000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_mem_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ahb_clk = { - .halt_reg = 0x77014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_clk = { - .halt_reg = 0x77010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x77010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77010, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_clk = { - .halt_reg = 0x7705c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7705c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7705c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_ice_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { - .halt_reg = 0x7705c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7705c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7705c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_ice_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_clk = { - .halt_reg = 0x77090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77090, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { - .halt_reg = 0x77090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77090, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_phy_aux_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x7701c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_rx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x770ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_rx_symbol_1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x77018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_tx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_clk = { - .halt_reg = 0x77058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_unipro_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { - .halt_reg = 0x77058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77058, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_unipro_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_master_clk = { - .halt_reg = 0xf010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { - .halt_reg = 0xf018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_sleep_clk = { - .halt_reg = 0xf014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_master_clk = { - .halt_reg = 0x10010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_master_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { - .halt_reg = 0x10018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_mock_utmi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_sleep_clk = { - .halt_reg = 0x10014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_clkref_clk = { - .halt_reg = 0x8c008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_aux_clk = { - .halt_reg = 0xf050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { - .halt_reg = 0xf054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0xf058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_clkref_clk = { - .halt_reg = 0x8c028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_aux_clk = { - .halt_reg = 0x10050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { - .halt_reg = 0x10054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_com_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x10058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for video boot - */ -static struct clk_branch gcc_video_ahb_clk = { - .halt_reg = 0xb004, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi0_clk = { - .halt_reg = 0xb024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axi0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi1_clk = { - .halt_reg = 0xb028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axi1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axic_clk = { - .halt_reg = 0xb02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axic_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to video, so no need to poll */ -static struct clk_branch gcc_video_xo_clk = { - .halt_reg = 0xb040, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -<<<<<<< -======= -/* To Do: EMAC GDSC currently has issues when its turn'ed ON, once - * its already in OFF state. So use PWRSTS_ON state (only) as a - * workaround for now. - */ ->>>>>>> -static struct gdsc emac_gdsc = { - .gdscr = 0x6004, - .pd = { - .name = "emac_gdsc", - }, -<<<<<<< - .pwrsts = PWRSTS_OFF_ON, -======= - .pwrsts = PWRSTS_ON, ->>>>>>> - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc pcie_0_gdsc = { - .gdscr = 0x6b004, - .pd = { - .name = "pcie_0_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc pcie_1_gdsc = { - .gdscr = 0x8d004, - .pd = { - .name = "pcie_1_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_card_gdsc = { - .gdscr = 0x75004, - .pd = { - .name = "ufs_card_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_phy_gdsc = { - .gdscr = 0x77004, - .pd = { - .name = "ufs_phy_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_prim_gdsc = { - .gdscr = 0xf004, - .pd = { - .name = "usb30_prim_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_sec_gdsc = { - .gdscr = 0x10004, - .pd = { - .name = "usb30_sec_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct clk_regmap *gcc_sm8150_clocks[] = { - [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, - [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, - [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = - &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, - [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, - [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = - &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, - [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, - [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, - [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, - [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, - [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, - [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, - [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, - [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, - [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, - [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, - [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, - [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, - [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, - [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr, - [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr, - [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, - [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr, - [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr, - [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr, - [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, - [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, - [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, - [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, - [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, - [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, - [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, - [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, - [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, - [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, - [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, - [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr, - [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, - [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, - [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, - [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, - [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr, - [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, - [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, - [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, - [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, - [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, - [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, - [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, - [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, - [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, - [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, - [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, - [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, - [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, - [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, - [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, - [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, - [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, - [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, - [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, - [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, - [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, - [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, - [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, - [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, - [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, - [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, - [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, - [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, - [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, - [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, - [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, - [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, - [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, - [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, - [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, - [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, - [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, - [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, - [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, - [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, - [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, - [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, - [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, - [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, - [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, - [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, - [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, - [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, - [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, - [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, - [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, - [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, - [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, - [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, - [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, - [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, - [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, - [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, - [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, - [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, - [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, - [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, - [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, - [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, - [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, - [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, - [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, - [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, - [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, - [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, - [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, - [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, - [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, - [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, - [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, - [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, - [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, - [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, - [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, - [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, - [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, - [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, - [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, - [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, - [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, - [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, - [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, - [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, - [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, - [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, - [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = - &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, - [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, - [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = - &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, - [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, - [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = - &gcc_ufs_card_unipro_core_clk_src.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = - &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, - [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, - [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, - [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, - [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, - [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, - [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = - &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, - [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, - [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, - [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = - &gcc_ufs_phy_unipro_core_clk_src.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = - &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, - [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, - [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = - &gcc_usb30_prim_mock_utmi_clk_src.clkr, - [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, - [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, - [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, - [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, - [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = - &gcc_usb30_sec_mock_utmi_clk_src.clkr, - [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, - [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, - [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, - [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, - [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, - [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, - [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, - [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, - [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, - [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, - [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, - [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr, - [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, - [GPLL0] = &gpll0.clkr, - [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, - [GPLL7] = &gpll7.clkr, - [GPLL9] = &gpll9.clkr, -}; - -static const struct qcom_reset_map gcc_sm8150_resets[] = { - [GCC_EMAC_BCR] = { 0x6000 }, - [GCC_GPU_BCR] = { 0x71000 }, - [GCC_MMSS_BCR] = { 0xb000 }, - [GCC_NPU_BCR] = { 0x4d000 }, - [GCC_PCIE_0_BCR] = { 0x6b000 }, - [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, - [GCC_PCIE_1_BCR] = { 0x8d000 }, - [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, - [GCC_PCIE_PHY_BCR] = { 0x6f000 }, - [GCC_PDM_BCR] = { 0x33000 }, - [GCC_PRNG_BCR] = { 0x34000 }, - [GCC_QSPI_BCR] = { 0x24008 }, - [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, - [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, - [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, - [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, - [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, - [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, - [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, - [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, - [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, - [GCC_SDCC2_BCR] = { 0x14000 }, - [GCC_SDCC4_BCR] = { 0x16000 }, - [GCC_TSIF_BCR] = { 0x36000 }, - [GCC_UFS_CARD_BCR] = { 0x75000 }, - [GCC_UFS_PHY_BCR] = { 0x77000 }, - [GCC_USB30_PRIM_BCR] = { 0xf000 }, - [GCC_USB30_SEC_BCR] = { 0x10000 }, - [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, -}; - -static struct gdsc *gcc_sm8150_gdscs[] = { - [EMAC_GDSC] = &emac_gdsc, - [PCIE_0_GDSC] = &pcie_0_gdsc, - [PCIE_1_GDSC] = &pcie_1_gdsc, - [UFS_CARD_GDSC] = &ufs_card_gdsc, - [UFS_PHY_GDSC] = &ufs_phy_gdsc, - [USB30_PRIM_GDSC] = &usb30_prim_gdsc, - [USB30_SEC_GDSC] = &usb30_sec_gdsc, -}; - -static const struct regmap_config gcc_sm8150_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x9c040, - .fast_io = true, -}; - -static const struct qcom_cc_desc gcc_sm8150_desc = { - .config = &gcc_sm8150_regmap_config, - .clks = gcc_sm8150_clocks, - .num_clks = ARRAY_SIZE(gcc_sm8150_clocks), - .resets = gcc_sm8150_resets, - .num_resets = ARRAY_SIZE(gcc_sm8150_resets), - .gdscs = gcc_sm8150_gdscs, - .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs), -}; - -static const struct of_device_id gcc_sm8150_match_table[] = { - { .compatible = "qcom,gcc-sm8150" }, - { } -}; -MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table); - -static void gcc_sm8150_pm_runtime_disable(void *data) -{ - pm_runtime_disable(data); -} - -static int gcc_sm8150_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - int ret; - - pm_runtime_enable(&pdev->dev); - - ret = devm_add_action_or_reset(&pdev->dev, gcc_sm8150_pm_runtime_disable, &pdev->dev); - if (ret) - return ret; - - ret = pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap = qcom_cc_map(pdev, &gcc_sm8150_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - - /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ - regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); - regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - - ret = qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap); - - pm_runtime_put(&pdev->dev); - - return ret; -} - -static struct platform_driver gcc_sm8150_driver = { - .probe = gcc_sm8150_probe, - .driver = { - .name = "gcc-sm8150", - .of_match_table = gcc_sm8150_match_table, - }, -}; - -static int __init gcc_sm8150_init(void) -{ - return platform_driver_register(&gcc_sm8150_driver); -} -subsys_initcall(gcc_sm8150_init); - -static void __exit gcc_sm8150_exit(void) -{ - platform_driver_unregister(&gcc_sm8150_driver); -} -module_exit(gcc_sm8150_exit); - -MODULE_DESCRIPTION("QTI GCC SM8150 Driver"); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/525bf386cbe2f3528cd23f14e44f72d9a6f48474/preimage.1 b/rr-cache/525bf386cbe2f3528cd23f14e44f72d9a6f48474/preimage.1 deleted file mode 100644 index 974e2a2..0000000 --- a/rr-cache/525bf386cbe2f3528cd23f14e44f72d9a6f48474/preimage.1 +++ /dev/null @@ -1,3865 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "reset.h" -#include "gdsc.h" - -enum { - P_BI_TCXO, - P_AUD_REF_CLK, - P_CORE_BI_PLL_TEST_SE, - P_GPLL0_OUT_EVEN, - P_GPLL0_OUT_MAIN, - P_GPLL7_OUT_MAIN, - P_GPLL9_OUT_MAIN, - P_SLEEP_CLK, -}; - -static struct clk_alpha_pll gpll0 = { - .offset = 0x0, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_trion_even[] = { - { 0x0, 1 }, - { 0x1, 2 }, - { 0x3, 4 }, - { 0x7, 8 }, - { } -}; - -static struct clk_alpha_pll_postdiv gpll0_out_even = { - .offset = 0x0, - .post_div_shift = 8, - .post_div_table = post_div_table_trion_even, - .num_post_div = ARRAY_SIZE(post_div_table_trion_even), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .width = 4, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll0_out_even", - .parent_hws = (const struct clk_hw*[]){ - &gpll0.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_postdiv_trion_ops, - }, -}; - -static struct clk_alpha_pll gpll7 = { - .offset = 0x1a000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gpll7", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll9 = { - .offset = 0x1c000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gpll9", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static const struct parent_map gcc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_0[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_SLEEP_CLK, 5 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_1[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "sleep_clk", .name = "sleep_clk" }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_SLEEP_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_2[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "sleep_clk", .name = "sleep_clk" }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_3[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_3[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se"}, -}; - -static const struct parent_map gcc_parent_map_4[] = { - { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_4[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_5[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL7_OUT_MAIN, 3 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_5[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll7.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_6[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL9_OUT_MAIN, 2 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_6[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll9.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_7[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_AUD_REF_CLK, 2 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_7[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { - .cmd_rcgr = 0x48014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), - F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_emac_ptp_clk_src = { - .cmd_rcgr = 0x6038, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_emac_ptp_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_emac_ptp_clk_src", - .parent_data = gcc_parents_5, - .num_parents = ARRAY_SIZE(gcc_parents_5), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { - F(2500000, P_BI_TCXO, 1, 25, 192), - F(5000000, P_BI_TCXO, 1, 25, 96), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), - F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_emac_rgmii_clk_src = { - .cmd_rcgr = 0x601c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_emac_rgmii_clk_src", - .parent_data = gcc_parents_5, - .num_parents = ARRAY_SIZE(gcc_parents_5), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_gp1_clk_src = { - .cmd_rcgr = 0x64004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp2_clk_src = { - .cmd_rcgr = 0x65004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp3_clk_src = { - .cmd_rcgr = 0x66004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { - .cmd_rcgr = 0x6b02c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { - .cmd_rcgr = 0x8d02c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { - .cmd_rcgr = 0x6f014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_phy_refgen_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pdm2_clk_src = { - .cmd_rcgr = 0x33010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pdm2_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_qspi_core_clk_src = { - .cmd_rcgr = 0x4b008, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qspi_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { - F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), - F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), - F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), - F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), - F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), - F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), - F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), - F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), - F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), - F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), - F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), - F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), - F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), - { } -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { - .cmd_rcgr = 0x17148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { - .cmd_rcgr = 0x17278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { - .cmd_rcgr = 0x173a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { - .cmd_rcgr = 0x174d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { - .cmd_rcgr = 0x17608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { - .cmd_rcgr = 0x17738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { - .cmd_rcgr = 0x17868, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s6_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { - .cmd_rcgr = 0x17998, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s7_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { - .cmd_rcgr = 0x18148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { - .cmd_rcgr = 0x18278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { - .cmd_rcgr = 0x183a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { - .cmd_rcgr = 0x184d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { - .cmd_rcgr = 0x18608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { - .cmd_rcgr = 0x18738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { - .cmd_rcgr = 0x1e148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { - .cmd_rcgr = 0x1e278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { - .cmd_rcgr = 0x1e3a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { - .cmd_rcgr = 0x1e4d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { - .cmd_rcgr = 0x1e608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { - .cmd_rcgr = 0x1e738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { - F(400000, P_BI_TCXO, 12, 1, 4), - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { - .cmd_rcgr = 0x1400c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_6, - .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk_src", - .parent_data = gcc_parents_6, - .num_parents = ARRAY_SIZE(gcc_parents_6), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_floor_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { - F(400000, P_BI_TCXO, 12, 1, 4), - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { - .cmd_rcgr = 0x1600c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_3, - .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_apps_clk_src", - .parent_data = gcc_parents_3, - .num_parents = ARRAY_SIZE(gcc_parents_3), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_floor_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { - F(105495, P_BI_TCXO, 2, 1, 91), - { } -}; - -static struct clk_rcg2 gcc_tsif_ref_clk_src = { - .cmd_rcgr = 0x36010, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_7, - .freq_tbl = ftbl_gcc_tsif_ref_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ref_clk_src", - .parent_data = gcc_parents_7, - .num_parents = ARRAY_SIZE(gcc_parents_7), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { - .cmd_rcgr = 0x75020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { - .cmd_rcgr = 0x75060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { - .cmd_rcgr = 0x75094, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_clk_src", - .parent_data = gcc_parents_4, - .num_parents = ARRAY_SIZE(gcc_parents_4), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { - .cmd_rcgr = 0x75078, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { - .cmd_rcgr = 0x77020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { - .cmd_rcgr = 0x77060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { - .cmd_rcgr = 0x77094, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk_src", - .parent_data = gcc_parents_4, - .num_parents = ARRAY_SIZE(gcc_parents_4), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { - .cmd_rcgr = 0x77078, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { - F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), - F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), - F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { - .cmd_rcgr = 0xf01c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), - F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { - .cmd_rcgr = 0xf034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { - .cmd_rcgr = 0x1001c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_master_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { - .cmd_rcgr = 0x10034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_mock_utmi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { - .cmd_rcgr = 0xf060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { - .cmd_rcgr = 0x10060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { - .halt_reg = 0x90018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x90018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_noc_pcie_tbu_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_card_axi_clk = { - .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x750c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x750c0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_card_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { - .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x750c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x750c0, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_aggre_ufs_card_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { - .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x770c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x770c0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x770c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x770c0, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_aggre_ufs_phy_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { - .halt_reg = 0xf07c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf07c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { - .halt_reg = 0x1007c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1007c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_usb3_sec_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_boot_rom_ahb_clk = { - .halt_reg = 0x38004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x38004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_boot_rom_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for camss boot - */ -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0xb008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_hf_axi_clk = { - .halt_reg = 0xb030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_sf_axi_clk = { - .halt_reg = 0xb034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_sf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to camss, so no need to poll */ -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0xb044, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb044, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { - .halt_reg = 0xf078, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { - .halt_reg = 0x10078, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_sec_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_ahb_clk = { - .halt_reg = 0x48000, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw }, - .num_parents = 1, - /* required for cpuss */ - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_dvm_bus_clk = { - .halt_reg = 0x48190, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48190, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_dvm_bus_clk", - /* required for cpuss */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_gnoc_clk = { - .halt_reg = 0x48004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x48004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_gnoc_clk", - /* required for cpuss */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_rbcpr_clk = { - .halt_reg = 0x48008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_rbcpr_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ddrss_gpu_axi_clk = { - .halt_reg = 0x71154, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x71154, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ddrss_gpu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for disp boot - */ -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0xb00c, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb00c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_hf_axi_clk = { - .halt_reg = 0xb038, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_sf_axi_clk = { - .halt_reg = 0xb03c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb03c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_sf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to disp, so no need to poll */ -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0xb048, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_axi_clk = { - .halt_reg = 0x6010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_ptp_clk = { - .halt_reg = 0x6034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_ptp_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_emac_ptp_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_rgmii_clk = { - .halt_reg = 0x6018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_rgmii_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_emac_rgmii_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_slv_ahb_clk = { - .halt_reg = 0x6014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x6014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x6014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_slv_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp1_clk = { - .halt_reg = 0x64000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x64000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp2_clk = { - .halt_reg = 0x65000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x65000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp3_clk = { - .halt_reg = 0x66000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x66000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x71004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x71004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x71004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - /* required for gpu */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0_out_even.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_iref_clk = { - .halt_reg = 0x8c010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_iref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_memnoc_gfx_clk = { - .halt_reg = 0x7100c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7100c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_memnoc_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { - .halt_reg = 0x71018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x71018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_snoc_dvm_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_at_clk = { - .halt_reg = 0x4d010, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_at_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_axi_clk = { - .halt_reg = 0x4d008, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_cfg_ahb_clk = { - .halt_reg = 0x4d004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x4d004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x4d004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_cfg_ahb_clk", - /* required for npu */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(18), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(19), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0_out_even.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_trig_clk = { - .halt_reg = 0x4d00c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_trig_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie0_phy_refgen_clk = { - .halt_reg = 0x6f02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie0_phy_refgen_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_phy_refgen_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie1_phy_refgen_clk = { - .halt_reg = 0x6f030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie1_phy_refgen_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_phy_refgen_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_aux_clk = { - .halt_reg = 0x6b020, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { - .halt_reg = 0x6b01c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x6b01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_clkref_clk = { - .halt_reg = 0x8c00c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_mstr_axi_clk = { - .halt_reg = 0x6b018, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_mstr_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ -static struct clk_branch gcc_pcie_0_pipe_clk = { - .halt_reg = 0x6b024, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_axi_clk = { - .halt_reg = 0x6b014, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x6b014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_slv_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { - .halt_reg = 0x6b010, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_slv_q2a_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_aux_clk = { - .halt_reg = 0x8d020, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(29), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_1_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { - .halt_reg = 0x8d01c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8d01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(28), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_clkref_clk = { - .halt_reg = 0x8c02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_mstr_axi_clk = { - .halt_reg = 0x8d018, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_mstr_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ -static struct clk_branch gcc_pcie_1_pipe_clk = { - .halt_reg = 0x8d024, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(30), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_axi_clk = { - .halt_reg = 0x8d014, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8d014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_slv_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { - .halt_reg = 0x8d010, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_slv_q2a_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_phy_aux_clk = { - .halt_reg = 0x6f004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm2_clk = { - .halt_reg = 0x3300c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3300c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pdm2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_ahb_clk = { - .halt_reg = 0x33004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x33004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x33004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_xo4_clk = { - .halt_reg = 0x33008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_xo4_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_prng_ahb_clk = { - .halt_reg = 0x34004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_prng_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { - .halt_reg = 0xb018, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb018, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_camera_nrt_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { - .halt_reg = 0xb01c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb01c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_camera_rt_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_disp_ahb_clk = { - .halt_reg = 0xb020, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb020, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb020, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_disp_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { - .halt_reg = 0xb010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_video_cvp_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { - .halt_reg = 0xb014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_video_vcodec_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { - .halt_reg = 0x4b000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4b000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_cnoc_periph_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_core_clk = { - .halt_reg = 0x4b004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4b004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qspi_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s0_clk = { - .halt_reg = 0x17144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s1_clk = { - .halt_reg = 0x17274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s2_clk = { - .halt_reg = 0x173a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s3_clk = { - .halt_reg = 0x174d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s4_clk = { - .halt_reg = 0x17604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(14), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s5_clk = { - .halt_reg = 0x17734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s6_clk = { - .halt_reg = 0x17864, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s6_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s6_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s7_clk = { - .halt_reg = 0x17994, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s7_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s7_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s0_clk = { - .halt_reg = 0x18144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s1_clk = { - .halt_reg = 0x18274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(23), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s2_clk = { - .halt_reg = 0x183a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(24), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s3_clk = { - .halt_reg = 0x184d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s4_clk = { - .halt_reg = 0x18604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s5_clk = { - .halt_reg = 0x18734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s0_clk = { - .halt_reg = 0x1e144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s1_clk = { - .halt_reg = 0x1e274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s2_clk = { - .halt_reg = 0x1e3a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s3_clk = { - .halt_reg = 0x1e4d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s4_clk = { - .halt_reg = 0x1e604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(8), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s5_clk = { - .halt_reg = 0x1e734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { - .halt_reg = 0x17004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { - .halt_reg = 0x18004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(20), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { - .halt_reg = 0x18008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x18008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { - .halt_reg = 0x1e004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_2_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { - .halt_reg = 0x1e008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x1e008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_2_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_ahb_clk = { - .halt_reg = 0x14008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_apps_clk = { - .halt_reg = 0x14004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_sdcc2_apps_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_ahb_clk = { - .halt_reg = 0x16008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_apps_clk = { - .halt_reg = 0x16004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_apps_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_sdcc4_apps_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x4819c, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw }, - .num_parents = 1, - /* required for cpuss */ - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_inactivity_timers_clk = { - .halt_reg = 0x3600c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3600c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_inactivity_timers_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ref_clk = { - .halt_reg = 0x36008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ref_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_tsif_ref_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ahb_clk = { - .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_axi_clk = { - .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { - .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_clkref_clk = { - .halt_reg = 0x8c004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ice_core_clk = { - .halt_reg = 0x7505c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7505c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7505c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_ice_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { - .halt_reg = 0x7505c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7505c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7505c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_ice_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_phy_aux_clk = { - .halt_reg = 0x75090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75090, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { - .halt_reg = 0x75090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75090, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_phy_aux_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x7501c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_rx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x750ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_rx_symbol_1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x75018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_tx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_unipro_core_clk = { - .halt_reg = 0x75058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_unipro_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { - .halt_reg = 0x75058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75058, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_unipro_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_mem_clkref_clk = { - .halt_reg = 0x8c000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_mem_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ahb_clk = { - .halt_reg = 0x77014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_clk = { - .halt_reg = 0x77010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x77010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77010, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_clk = { - .halt_reg = 0x7705c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7705c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7705c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_ice_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { - .halt_reg = 0x7705c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7705c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7705c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_ice_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_clk = { - .halt_reg = 0x77090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77090, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { - .halt_reg = 0x77090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77090, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_phy_aux_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x7701c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_rx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x770ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_rx_symbol_1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x77018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_tx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_clk = { - .halt_reg = 0x77058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_unipro_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { - .halt_reg = 0x77058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77058, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_unipro_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_master_clk = { - .halt_reg = 0xf010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { - .halt_reg = 0xf018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_sleep_clk = { - .halt_reg = 0xf014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_master_clk = { - .halt_reg = 0x10010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_master_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { - .halt_reg = 0x10018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_mock_utmi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_sleep_clk = { - .halt_reg = 0x10014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_clkref_clk = { - .halt_reg = 0x8c008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_aux_clk = { - .halt_reg = 0xf050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { - .halt_reg = 0xf054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0xf058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_clkref_clk = { - .halt_reg = 0x8c028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_aux_clk = { - .halt_reg = 0x10050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { - .halt_reg = 0x10054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_com_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x10058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for video boot - */ -static struct clk_branch gcc_video_ahb_clk = { - .halt_reg = 0xb004, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi0_clk = { - .halt_reg = 0xb024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axi0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi1_clk = { - .halt_reg = 0xb028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axi1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axic_clk = { - .halt_reg = 0xb02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axic_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to video, so no need to poll */ -static struct clk_branch gcc_video_xo_clk = { - .halt_reg = 0xb040, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -<<<<<<< -======= -/* To Do: EMAC GDSC currently has issues when its turn'ed ON, once - * its already in OFF state. So use PWRSTS_ON state (only) as a - * workaround for now. - */ ->>>>>>> -static struct gdsc emac_gdsc = { - .gdscr = 0x6004, - .pd = { - .name = "emac_gdsc", - }, -<<<<<<< - .pwrsts = PWRSTS_OFF_ON, -======= - .pwrsts = PWRSTS_ON, ->>>>>>> - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc pcie_0_gdsc = { - .gdscr = 0x6b004, - .pd = { - .name = "pcie_0_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc pcie_1_gdsc = { - .gdscr = 0x8d004, - .pd = { - .name = "pcie_1_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_card_gdsc = { - .gdscr = 0x75004, - .pd = { - .name = "ufs_card_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_phy_gdsc = { - .gdscr = 0x77004, - .pd = { - .name = "ufs_phy_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_prim_gdsc = { - .gdscr = 0xf004, - .pd = { - .name = "usb30_prim_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_sec_gdsc = { - .gdscr = 0x10004, - .pd = { - .name = "usb30_sec_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct clk_regmap *gcc_sm8150_clocks[] = { - [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, - [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, - [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = - &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, - [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, - [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = - &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, - [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, - [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, - [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, - [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, - [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, - [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, - [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, - [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, - [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, - [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, - [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, - [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, - [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, - [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr, - [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr, - [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, - [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr, - [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr, - [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr, - [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, - [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, - [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, - [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, - [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, - [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, - [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, - [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, - [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, - [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, - [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, - [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr, - [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, - [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, - [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, - [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, - [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr, - [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, - [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, - [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, - [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, - [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, - [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, - [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, - [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, - [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, - [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, - [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, - [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, - [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, - [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, - [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, - [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, - [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, - [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, - [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, - [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, - [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, - [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, - [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, - [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, - [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, - [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, - [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, - [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, - [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, - [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, - [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, - [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, - [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, - [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, - [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, - [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, - [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, - [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, - [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, - [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, - [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, - [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, - [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, - [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, - [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, - [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, - [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, - [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, - [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, - [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, - [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, - [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, - [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, - [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, - [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, - [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, - [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, - [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, - [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, - [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, - [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, - [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, - [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, - [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, - [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, - [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, - [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, - [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, - [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, - [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, - [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, - [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, - [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, - [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, - [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, - [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, - [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, - [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, - [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, - [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, - [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, - [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, - [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, - [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, - [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, - [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, - [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, - [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, - [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, - [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, - [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = - &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, - [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, - [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = - &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, - [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, - [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = - &gcc_ufs_card_unipro_core_clk_src.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = - &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, - [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, - [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, - [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, - [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, - [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, - [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = - &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, - [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, - [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, - [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = - &gcc_ufs_phy_unipro_core_clk_src.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = - &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, - [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, - [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = - &gcc_usb30_prim_mock_utmi_clk_src.clkr, - [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, - [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, - [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, - [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, - [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = - &gcc_usb30_sec_mock_utmi_clk_src.clkr, - [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, - [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, - [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, - [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, - [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, - [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, - [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, - [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, - [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, - [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, - [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, - [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr, - [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, - [GPLL0] = &gpll0.clkr, - [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, - [GPLL7] = &gpll7.clkr, - [GPLL9] = &gpll9.clkr, -}; - -static const struct qcom_reset_map gcc_sm8150_resets[] = { - [GCC_EMAC_BCR] = { 0x6000 }, - [GCC_GPU_BCR] = { 0x71000 }, - [GCC_MMSS_BCR] = { 0xb000 }, - [GCC_NPU_BCR] = { 0x4d000 }, - [GCC_PCIE_0_BCR] = { 0x6b000 }, - [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, - [GCC_PCIE_1_BCR] = { 0x8d000 }, - [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, - [GCC_PCIE_PHY_BCR] = { 0x6f000 }, - [GCC_PDM_BCR] = { 0x33000 }, - [GCC_PRNG_BCR] = { 0x34000 }, - [GCC_QSPI_BCR] = { 0x24008 }, - [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, - [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, - [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, - [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, - [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, - [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, - [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, - [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, - [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, - [GCC_SDCC2_BCR] = { 0x14000 }, - [GCC_SDCC4_BCR] = { 0x16000 }, - [GCC_TSIF_BCR] = { 0x36000 }, - [GCC_UFS_CARD_BCR] = { 0x75000 }, - [GCC_UFS_PHY_BCR] = { 0x77000 }, - [GCC_USB30_PRIM_BCR] = { 0xf000 }, - [GCC_USB30_SEC_BCR] = { 0x10000 }, - [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, -}; - -static struct gdsc *gcc_sm8150_gdscs[] = { - [EMAC_GDSC] = &emac_gdsc, - [PCIE_0_GDSC] = &pcie_0_gdsc, - [PCIE_1_GDSC] = &pcie_1_gdsc, - [UFS_CARD_GDSC] = &ufs_card_gdsc, - [UFS_PHY_GDSC] = &ufs_phy_gdsc, - [USB30_PRIM_GDSC] = &usb30_prim_gdsc, - [USB30_SEC_GDSC] = &usb30_sec_gdsc, -}; - -static const struct regmap_config gcc_sm8150_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x9c040, - .fast_io = true, -}; - -static const struct qcom_cc_desc gcc_sm8150_desc = { - .config = &gcc_sm8150_regmap_config, - .clks = gcc_sm8150_clocks, - .num_clks = ARRAY_SIZE(gcc_sm8150_clocks), - .resets = gcc_sm8150_resets, - .num_resets = ARRAY_SIZE(gcc_sm8150_resets), - .gdscs = gcc_sm8150_gdscs, - .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs), -}; - -static const struct of_device_id gcc_sm8150_match_table[] = { - { .compatible = "qcom,gcc-sm8150" }, - { } -}; -MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table); - -static void gcc_sm8150_pm_runtime_disable(void *data) -{ - pm_runtime_disable(data); -} - -static int gcc_sm8150_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - int ret; - - pm_runtime_enable(&pdev->dev); - - ret = devm_add_action_or_reset(&pdev->dev, gcc_sm8150_pm_runtime_disable, &pdev->dev); - if (ret) - return ret; - - ret = pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap = qcom_cc_map(pdev, &gcc_sm8150_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - - /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ - regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); - regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - - ret = qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap); - - pm_runtime_put(&pdev->dev); - - return ret; -} - -static struct platform_driver gcc_sm8150_driver = { - .probe = gcc_sm8150_probe, - .driver = { - .name = "gcc-sm8150", - .of_match_table = gcc_sm8150_match_table, - }, -}; - -static int __init gcc_sm8150_init(void) -{ - return platform_driver_register(&gcc_sm8150_driver); -} -subsys_initcall(gcc_sm8150_init); - -static void __exit gcc_sm8150_exit(void) -{ - platform_driver_unregister(&gcc_sm8150_driver); -} -module_exit(gcc_sm8150_exit); - -MODULE_DESCRIPTION("QTI GCC SM8150 Driver"); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/525bf386cbe2f3528cd23f14e44f72d9a6f48474/preimage.2 b/rr-cache/525bf386cbe2f3528cd23f14e44f72d9a6f48474/preimage.2 deleted file mode 100644 index 974e2a2..0000000 --- a/rr-cache/525bf386cbe2f3528cd23f14e44f72d9a6f48474/preimage.2 +++ /dev/null @@ -1,3865 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "reset.h" -#include "gdsc.h" - -enum { - P_BI_TCXO, - P_AUD_REF_CLK, - P_CORE_BI_PLL_TEST_SE, - P_GPLL0_OUT_EVEN, - P_GPLL0_OUT_MAIN, - P_GPLL7_OUT_MAIN, - P_GPLL9_OUT_MAIN, - P_SLEEP_CLK, -}; - -static struct clk_alpha_pll gpll0 = { - .offset = 0x0, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_trion_even[] = { - { 0x0, 1 }, - { 0x1, 2 }, - { 0x3, 4 }, - { 0x7, 8 }, - { } -}; - -static struct clk_alpha_pll_postdiv gpll0_out_even = { - .offset = 0x0, - .post_div_shift = 8, - .post_div_table = post_div_table_trion_even, - .num_post_div = ARRAY_SIZE(post_div_table_trion_even), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .width = 4, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll0_out_even", - .parent_hws = (const struct clk_hw*[]){ - &gpll0.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_postdiv_trion_ops, - }, -}; - -static struct clk_alpha_pll gpll7 = { - .offset = 0x1a000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gpll7", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll9 = { - .offset = 0x1c000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gpll9", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_trion_ops, - }, - }, -}; - -static const struct parent_map gcc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_0[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_SLEEP_CLK, 5 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_1[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "sleep_clk", .name = "sleep_clk" }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_SLEEP_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_2[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "sleep_clk", .name = "sleep_clk" }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_3[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_3[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se"}, -}; - -static const struct parent_map gcc_parent_map_4[] = { - { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_4[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_5[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL7_OUT_MAIN, 3 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_5[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll7.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_6[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL9_OUT_MAIN, 2 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_6[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll9.clkr.hw }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct parent_map gcc_parent_map_7[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_AUD_REF_CLK, 2 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const struct clk_parent_data gcc_parents_7[] = { - { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .hw = &gpll0.clkr.hw }, - { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, - { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, -}; - -static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { - .cmd_rcgr = 0x48014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), - F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_emac_ptp_clk_src = { - .cmd_rcgr = 0x6038, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_emac_ptp_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_emac_ptp_clk_src", - .parent_data = gcc_parents_5, - .num_parents = ARRAY_SIZE(gcc_parents_5), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { - F(2500000, P_BI_TCXO, 1, 25, 192), - F(5000000, P_BI_TCXO, 1, 25, 96), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), - F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_emac_rgmii_clk_src = { - .cmd_rcgr = 0x601c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_emac_rgmii_clk_src", - .parent_data = gcc_parents_5, - .num_parents = ARRAY_SIZE(gcc_parents_5), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_gp1_clk_src = { - .cmd_rcgr = 0x64004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp2_clk_src = { - .cmd_rcgr = 0x65004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp3_clk_src = { - .cmd_rcgr = 0x66004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk_src", - .parent_data = gcc_parents_1, - .num_parents = ARRAY_SIZE(gcc_parents_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { - .cmd_rcgr = 0x6b02c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { - .cmd_rcgr = 0x8d02c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { - .cmd_rcgr = 0x6f014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_phy_refgen_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pdm2_clk_src = { - .cmd_rcgr = 0x33010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pdm2_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_qspi_core_clk_src = { - .cmd_rcgr = 0x4b008, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qspi_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { - F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), - F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), - F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), - F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), - F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), - F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), - F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), - F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), - F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), - F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), - F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), - F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), - F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), - { } -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { - .cmd_rcgr = 0x17148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { - .cmd_rcgr = 0x17278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { - .cmd_rcgr = 0x173a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { - .cmd_rcgr = 0x174d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { - .cmd_rcgr = 0x17608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { - .cmd_rcgr = 0x17738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { - .cmd_rcgr = 0x17868, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s6_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { - .cmd_rcgr = 0x17998, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s7_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { - .cmd_rcgr = 0x18148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { - .cmd_rcgr = 0x18278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { - .cmd_rcgr = 0x183a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { - .cmd_rcgr = 0x184d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { - .cmd_rcgr = 0x18608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { - .cmd_rcgr = 0x18738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { - .cmd_rcgr = 0x1e148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s0_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { - .cmd_rcgr = 0x1e278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s1_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { - .cmd_rcgr = 0x1e3a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s2_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { - .cmd_rcgr = 0x1e4d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s3_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { - .cmd_rcgr = 0x1e608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s4_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { - .cmd_rcgr = 0x1e738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s5_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { - F(400000, P_BI_TCXO, 12, 1, 4), - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { - .cmd_rcgr = 0x1400c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_6, - .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk_src", - .parent_data = gcc_parents_6, - .num_parents = ARRAY_SIZE(gcc_parents_6), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_floor_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { - F(400000, P_BI_TCXO, 12, 1, 4), - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { - .cmd_rcgr = 0x1600c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_3, - .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_apps_clk_src", - .parent_data = gcc_parents_3, - .num_parents = ARRAY_SIZE(gcc_parents_3), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_floor_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { - F(105495, P_BI_TCXO, 2, 1, 91), - { } -}; - -static struct clk_rcg2 gcc_tsif_ref_clk_src = { - .cmd_rcgr = 0x36010, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_7, - .freq_tbl = ftbl_gcc_tsif_ref_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ref_clk_src", - .parent_data = gcc_parents_7, - .num_parents = ARRAY_SIZE(gcc_parents_7), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { - .cmd_rcgr = 0x75020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { - .cmd_rcgr = 0x75060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { - .cmd_rcgr = 0x75094, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_clk_src", - .parent_data = gcc_parents_4, - .num_parents = ARRAY_SIZE(gcc_parents_4), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { - .cmd_rcgr = 0x75078, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { - .cmd_rcgr = 0x77020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { - .cmd_rcgr = 0x77060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { - .cmd_rcgr = 0x77094, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk_src", - .parent_data = gcc_parents_4, - .num_parents = ARRAY_SIZE(gcc_parents_4), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { - .cmd_rcgr = 0x77078, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { - F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), - F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), - F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { - .cmd_rcgr = 0xf01c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), - F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { - .cmd_rcgr = 0xf034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { - .cmd_rcgr = 0x1001c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_master_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { - .cmd_rcgr = 0x10034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_mock_utmi_clk_src", - .parent_data = gcc_parents_0, - .num_parents = ARRAY_SIZE(gcc_parents_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { - .cmd_rcgr = 0xf060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { - .cmd_rcgr = 0x10060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_aux_clk_src", - .parent_data = gcc_parents_2, - .num_parents = ARRAY_SIZE(gcc_parents_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { - .halt_reg = 0x90018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x90018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_noc_pcie_tbu_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_card_axi_clk = { - .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x750c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x750c0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_card_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { - .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x750c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x750c0, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_aggre_ufs_card_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { - .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x770c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x770c0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x770c0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x770c0, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_aggre_ufs_phy_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { - .halt_reg = 0xf07c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf07c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { - .halt_reg = 0x1007c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1007c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_usb3_sec_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_boot_rom_ahb_clk = { - .halt_reg = 0x38004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x38004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_boot_rom_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for camss boot - */ -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0xb008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_hf_axi_clk = { - .halt_reg = 0xb030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_sf_axi_clk = { - .halt_reg = 0xb034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_sf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to camss, so no need to poll */ -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0xb044, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb044, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { - .halt_reg = 0xf078, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { - .halt_reg = 0x10078, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_sec_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_ahb_clk = { - .halt_reg = 0x48000, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw }, - .num_parents = 1, - /* required for cpuss */ - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_dvm_bus_clk = { - .halt_reg = 0x48190, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48190, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_dvm_bus_clk", - /* required for cpuss */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_gnoc_clk = { - .halt_reg = 0x48004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x48004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_gnoc_clk", - /* required for cpuss */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_rbcpr_clk = { - .halt_reg = 0x48008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_rbcpr_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ddrss_gpu_axi_clk = { - .halt_reg = 0x71154, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x71154, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ddrss_gpu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for disp boot - */ -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0xb00c, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb00c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_hf_axi_clk = { - .halt_reg = 0xb038, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_sf_axi_clk = { - .halt_reg = 0xb03c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb03c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_sf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to disp, so no need to poll */ -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0xb048, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_axi_clk = { - .halt_reg = 0x6010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_ptp_clk = { - .halt_reg = 0x6034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_ptp_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_emac_ptp_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_rgmii_clk = { - .halt_reg = 0x6018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_rgmii_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_emac_rgmii_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_emac_slv_ahb_clk = { - .halt_reg = 0x6014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x6014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x6014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_emac_slv_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp1_clk = { - .halt_reg = 0x64000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x64000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp2_clk = { - .halt_reg = 0x65000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x65000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp3_clk = { - .halt_reg = 0x66000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x66000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_gp3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x71004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x71004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x71004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - /* required for gpu */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0_out_even.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_iref_clk = { - .halt_reg = 0x8c010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_iref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_memnoc_gfx_clk = { - .halt_reg = 0x7100c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7100c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_memnoc_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { - .halt_reg = 0x71018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x71018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_snoc_dvm_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_at_clk = { - .halt_reg = 0x4d010, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_at_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_axi_clk = { - .halt_reg = 0x4d008, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_cfg_ahb_clk = { - .halt_reg = 0x4d004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x4d004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x4d004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_cfg_ahb_clk", - /* required for npu */ - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(18), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(19), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw *[]){ - &gpll0_out_even.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_trig_clk = { - .halt_reg = 0x4d00c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4d00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_trig_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie0_phy_refgen_clk = { - .halt_reg = 0x6f02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie0_phy_refgen_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_phy_refgen_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie1_phy_refgen_clk = { - .halt_reg = 0x6f030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie1_phy_refgen_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_phy_refgen_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_aux_clk = { - .halt_reg = 0x6b020, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { - .halt_reg = 0x6b01c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x6b01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_clkref_clk = { - .halt_reg = 0x8c00c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_mstr_axi_clk = { - .halt_reg = 0x6b018, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_mstr_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ -static struct clk_branch gcc_pcie_0_pipe_clk = { - .halt_reg = 0x6b024, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_axi_clk = { - .halt_reg = 0x6b014, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x6b014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_slv_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { - .halt_reg = 0x6b010, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_slv_q2a_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_aux_clk = { - .halt_reg = 0x8d020, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(29), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_1_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { - .halt_reg = 0x8d01c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8d01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(28), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_clkref_clk = { - .halt_reg = 0x8c02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_mstr_axi_clk = { - .halt_reg = 0x8d018, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_mstr_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ -static struct clk_branch gcc_pcie_1_pipe_clk = { - .halt_reg = 0x8d024, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(30), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_axi_clk = { - .halt_reg = 0x8d014, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8d014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_slv_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { - .halt_reg = 0x8d010, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_slv_q2a_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_phy_aux_clk = { - .halt_reg = 0x6f004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6f004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm2_clk = { - .halt_reg = 0x3300c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3300c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_pdm2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_ahb_clk = { - .halt_reg = 0x33004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x33004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x33004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_xo4_clk = { - .halt_reg = 0x33008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_xo4_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_prng_ahb_clk = { - .halt_reg = 0x34004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_prng_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { - .halt_reg = 0xb018, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb018, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_camera_nrt_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { - .halt_reg = 0xb01c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb01c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb01c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_camera_rt_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_disp_ahb_clk = { - .halt_reg = 0xb020, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb020, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb020, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_disp_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { - .halt_reg = 0xb010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_video_cvp_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { - .halt_reg = 0xb014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qmip_video_vcodec_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { - .halt_reg = 0x4b000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4b000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_cnoc_periph_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_core_clk = { - .halt_reg = 0x4b004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4b004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qspi_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s0_clk = { - .halt_reg = 0x17144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s1_clk = { - .halt_reg = 0x17274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s2_clk = { - .halt_reg = 0x173a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s3_clk = { - .halt_reg = 0x174d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s4_clk = { - .halt_reg = 0x17604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(14), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s5_clk = { - .halt_reg = 0x17734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s6_clk = { - .halt_reg = 0x17864, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s6_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s6_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s7_clk = { - .halt_reg = 0x17994, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s7_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap0_s7_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s0_clk = { - .halt_reg = 0x18144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s1_clk = { - .halt_reg = 0x18274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(23), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s2_clk = { - .halt_reg = 0x183a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(24), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s3_clk = { - .halt_reg = 0x184d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s4_clk = { - .halt_reg = 0x18604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s5_clk = { - .halt_reg = 0x18734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap1_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s0_clk = { - .halt_reg = 0x1e144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s0_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s0_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s1_clk = { - .halt_reg = 0x1e274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s1_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s1_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s2_clk = { - .halt_reg = 0x1e3a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s2_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s2_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s3_clk = { - .halt_reg = 0x1e4d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s3_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s3_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s4_clk = { - .halt_reg = 0x1e604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(8), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s4_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s4_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap2_s5_clk = { - .halt_reg = 0x1e734, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap2_s5_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_qupv3_wrap2_s5_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { - .halt_reg = 0x17004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { - .halt_reg = 0x18004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(20), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { - .halt_reg = 0x18008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x18008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { - .halt_reg = 0x1e004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_2_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { - .halt_reg = 0x1e008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x1e008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52014, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_2_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_ahb_clk = { - .halt_reg = 0x14008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_apps_clk = { - .halt_reg = 0x14004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_sdcc2_apps_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_ahb_clk = { - .halt_reg = 0x16008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_apps_clk = { - .halt_reg = 0x16004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_apps_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_sdcc4_apps_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x4819c, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw }, - .num_parents = 1, - /* required for cpuss */ - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_inactivity_timers_clk = { - .halt_reg = 0x3600c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3600c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_inactivity_timers_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ref_clk = { - .halt_reg = 0x36008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ref_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_tsif_ref_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ahb_clk = { - .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_axi_clk = { - .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { - .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_clkref_clk = { - .halt_reg = 0x8c004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ice_core_clk = { - .halt_reg = 0x7505c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7505c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7505c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_ice_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { - .halt_reg = 0x7505c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7505c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7505c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_ice_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_phy_aux_clk = { - .halt_reg = 0x75090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75090, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { - .halt_reg = 0x75090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75090, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_phy_aux_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x7501c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_rx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x750ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_rx_symbol_1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x75018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_tx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_unipro_core_clk = { - .halt_reg = 0x75058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_unipro_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { - .halt_reg = 0x75058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x75058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x75058, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_card_unipro_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_mem_clkref_clk = { - .halt_reg = 0x8c000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_mem_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ahb_clk = { - .halt_reg = 0x77014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_clk = { - .halt_reg = 0x77010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x77010, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77010, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_axi_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_clk = { - .halt_reg = 0x7705c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7705c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7705c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_ice_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { - .halt_reg = 0x7705c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7705c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7705c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_ice_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_clk = { - .halt_reg = 0x77090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77090, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { - .halt_reg = 0x77090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77090, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_phy_aux_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x7701c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_rx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x770ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_rx_symbol_1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* external clocks so add BRANCH_HALT_SKIP */ -static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x77018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_tx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_clk = { - .halt_reg = 0x77058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_unipro_core_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { - .halt_reg = 0x77058, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77058, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77058, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_ufs_phy_unipro_core_clk.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch_simple_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_master_clk = { - .halt_reg = 0xf010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { - .halt_reg = 0xf018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_sleep_clk = { - .halt_reg = 0xf014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_master_clk = { - .halt_reg = 0x10010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_master_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { - .halt_reg = 0x10018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_mock_utmi_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_sleep_clk = { - .halt_reg = 0x10014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_clkref_clk = { - .halt_reg = 0x8c008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_aux_clk = { - .halt_reg = 0xf050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { - .halt_reg = 0xf054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0xf058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_clkref_clk = { - .halt_reg = 0x8c028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_aux_clk = { - .halt_reg = 0x10050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { - .halt_reg = 0x10054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_com_aux_clk", - .parent_hws = (const struct clk_hw *[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x10058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* - * Clock ON depends on external parent 'config noc', so cant poll - * delay and also mark as crtitical for video boot - */ -static struct clk_branch gcc_video_ahb_clk = { - .halt_reg = 0xb004, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0xb004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi0_clk = { - .halt_reg = 0xb024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axi0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi1_clk = { - .halt_reg = 0xb028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axi1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axic_clk = { - .halt_reg = 0xb02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axic_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -/* XO critical input to video, so no need to poll */ -static struct clk_branch gcc_video_xo_clk = { - .halt_reg = 0xb040, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -<<<<<<< -======= -/* To Do: EMAC GDSC currently has issues when its turn'ed ON, once - * its already in OFF state. So use PWRSTS_ON state (only) as a - * workaround for now. - */ ->>>>>>> -static struct gdsc emac_gdsc = { - .gdscr = 0x6004, - .pd = { - .name = "emac_gdsc", - }, -<<<<<<< - .pwrsts = PWRSTS_OFF_ON, -======= - .pwrsts = PWRSTS_ON, ->>>>>>> - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc pcie_0_gdsc = { - .gdscr = 0x6b004, - .pd = { - .name = "pcie_0_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc pcie_1_gdsc = { - .gdscr = 0x8d004, - .pd = { - .name = "pcie_1_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_card_gdsc = { - .gdscr = 0x75004, - .pd = { - .name = "ufs_card_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_phy_gdsc = { - .gdscr = 0x77004, - .pd = { - .name = "ufs_phy_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_prim_gdsc = { - .gdscr = 0xf004, - .pd = { - .name = "usb30_prim_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_sec_gdsc = { - .gdscr = 0x10004, - .pd = { - .name = "usb30_sec_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct clk_regmap *gcc_sm8150_clocks[] = { - [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, - [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, - [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = - &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, - [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, - [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = - &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, - [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, - [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, - [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, - [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, - [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, - [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, - [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, - [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, - [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, - [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, - [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, - [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, - [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, - [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr, - [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr, - [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, - [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr, - [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr, - [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr, - [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, - [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, - [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, - [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, - [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, - [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, - [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, - [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, - [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, - [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, - [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, - [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr, - [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, - [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, - [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, - [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, - [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr, - [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, - [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, - [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, - [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, - [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, - [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, - [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, - [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, - [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, - [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, - [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, - [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, - [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, - [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, - [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, - [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, - [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, - [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, - [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, - [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, - [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, - [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, - [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, - [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, - [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, - [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, - [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, - [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, - [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, - [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, - [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, - [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, - [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, - [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, - [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, - [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, - [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, - [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, - [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, - [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, - [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, - [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, - [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, - [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, - [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, - [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, - [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, - [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, - [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, - [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, - [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, - [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, - [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, - [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, - [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, - [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, - [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, - [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, - [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, - [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, - [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, - [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, - [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, - [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, - [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, - [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, - [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, - [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, - [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, - [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, - [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, - [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, - [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, - [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, - [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, - [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, - [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, - [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, - [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, - [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, - [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, - [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, - [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, - [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, - [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, - [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, - [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, - [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, - [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, - [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, - [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = - &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, - [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, - [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = - &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, - [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, - [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = - &gcc_ufs_card_unipro_core_clk_src.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = - &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, - [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, - [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, - [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, - [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, - [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, - [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = - &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, - [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, - [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, - [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = - &gcc_ufs_phy_unipro_core_clk_src.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = - &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, - [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, - [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = - &gcc_usb30_prim_mock_utmi_clk_src.clkr, - [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, - [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, - [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, - [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, - [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = - &gcc_usb30_sec_mock_utmi_clk_src.clkr, - [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, - [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, - [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, - [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, - [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, - [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, - [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, - [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, - [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, - [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, - [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, - [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr, - [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, - [GPLL0] = &gpll0.clkr, - [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, - [GPLL7] = &gpll7.clkr, - [GPLL9] = &gpll9.clkr, -}; - -static const struct qcom_reset_map gcc_sm8150_resets[] = { - [GCC_EMAC_BCR] = { 0x6000 }, - [GCC_GPU_BCR] = { 0x71000 }, - [GCC_MMSS_BCR] = { 0xb000 }, - [GCC_NPU_BCR] = { 0x4d000 }, - [GCC_PCIE_0_BCR] = { 0x6b000 }, - [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, - [GCC_PCIE_1_BCR] = { 0x8d000 }, - [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, - [GCC_PCIE_PHY_BCR] = { 0x6f000 }, - [GCC_PDM_BCR] = { 0x33000 }, - [GCC_PRNG_BCR] = { 0x34000 }, - [GCC_QSPI_BCR] = { 0x24008 }, - [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, - [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, - [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, - [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, - [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, - [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, - [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, - [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, - [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, - [GCC_SDCC2_BCR] = { 0x14000 }, - [GCC_SDCC4_BCR] = { 0x16000 }, - [GCC_TSIF_BCR] = { 0x36000 }, - [GCC_UFS_CARD_BCR] = { 0x75000 }, - [GCC_UFS_PHY_BCR] = { 0x77000 }, - [GCC_USB30_PRIM_BCR] = { 0xf000 }, - [GCC_USB30_SEC_BCR] = { 0x10000 }, - [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, -}; - -static struct gdsc *gcc_sm8150_gdscs[] = { - [EMAC_GDSC] = &emac_gdsc, - [PCIE_0_GDSC] = &pcie_0_gdsc, - [PCIE_1_GDSC] = &pcie_1_gdsc, - [UFS_CARD_GDSC] = &ufs_card_gdsc, - [UFS_PHY_GDSC] = &ufs_phy_gdsc, - [USB30_PRIM_GDSC] = &usb30_prim_gdsc, - [USB30_SEC_GDSC] = &usb30_sec_gdsc, -}; - -static const struct regmap_config gcc_sm8150_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x9c040, - .fast_io = true, -}; - -static const struct qcom_cc_desc gcc_sm8150_desc = { - .config = &gcc_sm8150_regmap_config, - .clks = gcc_sm8150_clocks, - .num_clks = ARRAY_SIZE(gcc_sm8150_clocks), - .resets = gcc_sm8150_resets, - .num_resets = ARRAY_SIZE(gcc_sm8150_resets), - .gdscs = gcc_sm8150_gdscs, - .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs), -}; - -static const struct of_device_id gcc_sm8150_match_table[] = { - { .compatible = "qcom,gcc-sm8150" }, - { } -}; -MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table); - -static void gcc_sm8150_pm_runtime_disable(void *data) -{ - pm_runtime_disable(data); -} - -static int gcc_sm8150_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - int ret; - - pm_runtime_enable(&pdev->dev); - - ret = devm_add_action_or_reset(&pdev->dev, gcc_sm8150_pm_runtime_disable, &pdev->dev); - if (ret) - return ret; - - ret = pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap = qcom_cc_map(pdev, &gcc_sm8150_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - - /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ - regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); - regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - - ret = qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap); - - pm_runtime_put(&pdev->dev); - - return ret; -} - -static struct platform_driver gcc_sm8150_driver = { - .probe = gcc_sm8150_probe, - .driver = { - .name = "gcc-sm8150", - .of_match_table = gcc_sm8150_match_table, - }, -}; - -static int __init gcc_sm8150_init(void) -{ - return platform_driver_register(&gcc_sm8150_driver); -} -subsys_initcall(gcc_sm8150_init); - -static void __exit gcc_sm8150_exit(void) -{ - platform_driver_unregister(&gcc_sm8150_driver); -} -module_exit(gcc_sm8150_exit); - -MODULE_DESCRIPTION("QTI GCC SM8150 Driver"); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/5ba192efab6a03f1b22d248d369c298075567017/preimage b/rr-cache/5ba192efab6a03f1b22d248d369c298075567017/preimage deleted file mode 100644 index 89bf164..0000000 --- a/rr-cache/5ba192efab6a03f1b22d248d369c298075567017/preimage +++ /dev/null @@ -1,6 +0,0 @@ -obj-$(CONFIG_MHI_BUS_EP) += mhi_ep.o -<<<<<<< -mhi_ep-y := main.o mmio.o ring.o sm.o -======= -mhi_ep-y := main.o mmio.o sm.o ring.o ->>>>>>> diff --git a/rr-cache/64961dbbc5172eb6a1daf967c6bbb881f991617d/preimage b/rr-cache/64961dbbc5172eb6a1daf967c6bbb881f991617d/preimage deleted file mode 100644 index 19e8351..0000000 --- a/rr-cache/64961dbbc5172eb6a1daf967c6bbb881f991617d/preimage +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2021, Intel Corporation. */ - -#ifndef _STMMAC_XDP_H_ -#define _STMMAC_XDP_H_ - -#define STMMAC_MAX_RX_BUF_SIZE(num) (((num) * PAGE_SIZE) - XDP_PACKET_HEADROOM) -<<<<<<< - -======= -#define STMMAC_RX_DMA_ATTR (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) - -int stmmac_xdp_setup_pool(struct stmmac_priv *priv, struct xsk_buff_pool *pool, - u16 queue); ->>>>>>> -int stmmac_xdp_set_prog(struct stmmac_priv *priv, struct bpf_prog *prog, - struct netlink_ext_ack *extack); - -#endif /* _STMMAC_XDP_H_ */ diff --git a/rr-cache/6551e48ae8bd0fa5cc74ca7a45e90cf14d51a9d8/preimage b/rr-cache/6551e48ae8bd0fa5cc74ca7a45e90cf14d51a9d8/preimage deleted file mode 100644 index 5cf90b5..0000000 --- a/rr-cache/6551e48ae8bd0fa5cc74ca7a45e90cf14d51a9d8/preimage +++ /dev/null @@ -1,452 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Linaro Ltd. - * Author: Manivannan Sadhasivam - */ - -#include -#include "internal.h" - -size_t mhi_ep_ring_addr2offset(struct mhi_ep_ring *ring, u64 ptr) -{ - u64 rbase; - -<<<<<<< - rbase = le64_to_cpu(ring->ring_ctx->generic.rbase); -======= - rbase = ring->ring_ctx->generic.rbase; ->>>>>>> - - return (ptr - rbase) / sizeof(struct mhi_ep_ring_element); -} - -static u32 mhi_ep_ring_num_elems(struct mhi_ep_ring *ring) -{ -<<<<<<< - return le64_to_cpu(ring->ring_ctx->generic.rlen) / sizeof(struct mhi_ep_ring_element); -======= - return ring->ring_ctx->generic.rlen / sizeof(struct mhi_ep_ring_element); ->>>>>>> -} - -void mhi_ep_ring_inc_index(struct mhi_ep_ring *ring) -{ - ring->rd_offset++; - if (ring->rd_offset == ring->ring_size) - ring->rd_offset = 0; -} - -<<<<<<< -int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, size_t end) -======= -static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, size_t end) ->>>>>>> -{ - struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl; - struct device *dev = &mhi_cntrl->mhi_dev->dev; - size_t start, copy_size; -<<<<<<< -======= - struct mhi_ep_ring_element *ring_shadow; - phys_addr_t ring_shadow_phys; - size_t size = ring->ring_size * sizeof(struct mhi_ep_ring_element); ->>>>>>> - int ret; - - /* No need to cache event rings */ - if (ring->type == RING_TYPE_ER) - return 0; - - /* No need to cache the ring if write pointer is unmodified */ - if (ring->wr_offset == end) - return 0; - - start = ring->wr_offset; -<<<<<<< - if (start < end) { - copy_size = (end - start) * sizeof(struct mhi_ep_ring_element); - ret = mhi_cntrl->read_from_host(mhi_cntrl, - (le64_to_cpu(ring->ring_ctx->generic.rbase) + - (start * sizeof(struct mhi_ep_ring_element))), - &ring->ring_cache[start], copy_size); - if (ret < 0) - return ret; - } else { - copy_size = (ring->ring_size - start) * sizeof(struct mhi_ep_ring_element); - ret = mhi_cntrl->read_from_host(mhi_cntrl, - (le64_to_cpu(ring->ring_ctx->generic.rbase) + - (start * sizeof(struct mhi_ep_ring_element))), - &ring->ring_cache[start], copy_size); - if (ret < 0) - return ret; - - if (end) { - ret = mhi_cntrl->read_from_host(mhi_cntrl, - le64_to_cpu(ring->ring_ctx->generic.rbase), - &ring->ring_cache[0], - end * sizeof(struct mhi_ep_ring_element)); - if (ret < 0) - return ret; - } - } - - dev_dbg(dev, "Cached ring: start %zu end %zu size %zu\n", start, end, copy_size); - - return 0; -} - -static int mhi_ep_cache_ring(struct mhi_ep_ring *ring, u64 wr_ptr) -======= - - /* Allocate memory for host ring */ - ring_shadow = mhi_cntrl->alloc_addr(mhi_cntrl, &ring_shadow_phys, - size); - if (!ring_shadow) { - dev_err(dev, "Failed to allocate memory for ring_shadow\n"); - return -ENOMEM; - } - - /* Map host ring */ - ret = mhi_cntrl->map_addr(mhi_cntrl, ring_shadow_phys, - ring->ring_ctx->generic.rbase, size); - if (ret) { - dev_err(dev, "Failed to map ring_shadow\n\n"); - goto err_ring_free; - } - - dev_dbg(dev, "Caching ring: start %d end %d size %d", start, end, copy_size); - - if (start < end) { - copy_size = (end - start) * sizeof(struct mhi_ep_ring_element); - memcpy_fromio(&ring->ring_cache[start], &ring_shadow[start], copy_size); - } else { - copy_size = (ring->ring_size - start) * sizeof(struct mhi_ep_ring_element); - memcpy_fromio(&ring->ring_cache[start], &ring_shadow[start], copy_size); - if (end) - memcpy_fromio(&ring->ring_cache[0], &ring_shadow[0], - end * sizeof(struct mhi_ep_ring_element)); - } - - /* Now unmap and free host ring */ - mhi_cntrl->unmap_addr(mhi_cntrl, ring_shadow_phys); - mhi_cntrl->free_addr(mhi_cntrl, ring_shadow_phys, ring_shadow, size); - - return 0; - -err_ring_free: - mhi_cntrl->free_addr(mhi_cntrl, ring_shadow_phys, &ring_shadow, size); - - return ret; -} - -int mhi_ep_cache_ring(struct mhi_ep_ring *ring, u64 wr_ptr) ->>>>>>> -{ - size_t wr_offset; - int ret; - - wr_offset = mhi_ep_ring_addr2offset(ring, wr_ptr); - - /* Cache the host ring till write offset */ - ret = __mhi_ep_cache_ring(ring, wr_offset); - if (ret) - return ret; - - ring->wr_offset = wr_offset; - - return 0; -} - -int mhi_ep_update_wr_offset(struct mhi_ep_ring *ring) -{ - u64 wr_ptr; - -<<<<<<< - switch (ring->type) { - case RING_TYPE_CMD: - mhi_ep_mmio_get_cmd_db(ring, &wr_ptr); - break; - case RING_TYPE_ER: - mhi_ep_mmio_get_er_db(ring, &wr_ptr); - break; - case RING_TYPE_CH: - mhi_ep_mmio_get_ch_db(ring, &wr_ptr); - break; - default: - return -EINVAL; - } -======= - wr_ptr = mhi_ep_mmio_get_db(ring); ->>>>>>> - - return mhi_ep_cache_ring(ring, wr_ptr); -} - -<<<<<<< -int mhi_ep_process_ring_element(struct mhi_ep_ring *ring, size_t offset) -{ - struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl; - struct device *dev = &mhi_cntrl->mhi_dev->dev; - struct mhi_ep_ring_element *el; - int ret = -ENODEV; -======= -static int mhi_ep_process_ring_element(struct mhi_ep_ring *ring, size_t offset) -{ - struct mhi_ep_ring_element *el; ->>>>>>> - - /* Get the element and invoke the respective callback */ - el = &ring->ring_cache[offset]; - -<<<<<<< - if (ring->ring_cb) - ret = ring->ring_cb(ring, el); - else - dev_err(dev, "No callback registered for ring\n"); - - return ret; -======= - return ring->ring_cb(ring, el); ->>>>>>> -} - -int mhi_ep_process_ring(struct mhi_ep_ring *ring) -{ - struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl; - struct device *dev = &mhi_cntrl->mhi_dev->dev; - int ret = 0; - - /* Event rings should not be processed */ - if (ring->type == RING_TYPE_ER) - return -EINVAL; - - dev_dbg(dev, "Processing ring of type: %d\n", ring->type); - - /* Update the write offset for the ring */ - ret = mhi_ep_update_wr_offset(ring); - if (ret) { - dev_err(dev, "Error updating write offset for ring\n"); - return ret; - } - - /* Sanity check to make sure there are elements in the ring */ - if (ring->rd_offset == ring->wr_offset) - return 0; - - /* Process channel ring first */ - if (ring->type == RING_TYPE_CH) { - ret = mhi_ep_process_ring_element(ring, ring->rd_offset); - if (ret) -<<<<<<< - dev_err(dev, "Error processing ch ring element: %d\n", ring->rd_offset); -======= - dev_err(dev, "Error processing ch ring element: %zu\n", ring->rd_offset); ->>>>>>> - - return ret; - } - - /* Process command ring now */ - while (ring->rd_offset != ring->wr_offset) { - ret = mhi_ep_process_ring_element(ring, ring->rd_offset); - if (ret) { -<<<<<<< - dev_err(dev, "Error processing cmd ring element: %d\n", ring->rd_offset); -======= - dev_err(dev, "Error processing cmd ring element: %zu\n", ring->rd_offset); ->>>>>>> - return ret; - } - - mhi_ep_ring_inc_index(ring); - } - - return 0; -} - -/* TODO: Support for adding multiple ring elements to the ring */ -<<<<<<< -int mhi_ep_ring_add_element(struct mhi_ep_ring *ring, struct mhi_ep_ring_element *el) -{ - struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl; - struct device *dev = &mhi_cntrl->mhi_dev->dev; - __le64 rbase = ring->ring_ctx->generic.rbase; -======= -int mhi_ep_ring_add_element(struct mhi_ep_ring *ring, struct mhi_ep_ring_element *el, int size) -{ - struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl; - struct device *dev = &mhi_cntrl->mhi_dev->dev; - struct mhi_ep_ring_element *ring_shadow; - size_t ring_size = ring->ring_size * sizeof(struct mhi_ep_ring_element); - phys_addr_t ring_shadow_phys; ->>>>>>> - size_t old_offset = 0; - u32 num_free_elem; - int ret; - - ret = mhi_ep_update_wr_offset(ring); - if (ret) { - dev_err(dev, "Error updating write pointer\n"); - return ret; - } - - if (ring->rd_offset < ring->wr_offset) - num_free_elem = (ring->wr_offset - ring->rd_offset) - 1; - else - num_free_elem = ((ring->ring_size - ring->rd_offset) + ring->wr_offset) - 1; - - /* Check if there is space in ring for adding at least an element */ -<<<<<<< - if (!num_free_elem) { -======= - if (num_free_elem < 1) { ->>>>>>> - dev_err(dev, "No space left in the ring\n"); - return -ENOSPC; - } - - old_offset = ring->rd_offset; - mhi_ep_ring_inc_index(ring); - -<<<<<<< - dev_dbg(dev, "Adding an element to ring at offset (%d)\n", ring->rd_offset); - - /* Update rp in ring context */ - ring->ring_ctx->generic.rp = (ring->rd_offset * sizeof(struct mhi_ep_ring_element)) + - ring->ring_ctx->generic.rbase; - - /* Allocate memory for host ring */ - ring_shadow = mhi_cntrl->alloc_addr(mhi_cntrl, &ring_shadow_phys, ring_size); - if (!ring_shadow) { - dev_err(dev, "failed to allocate ring_shadow\n"); - return -ENOMEM; - } - - /* Map host ring */ - ret = mhi_cntrl->map_addr(mhi_cntrl, ring_shadow_phys, - ring->ring_ctx->generic.rbase, ring_size); - if (ret) { - dev_err(dev, "failed to map ring_shadow\n\n"); - goto err_ring_free; - } - - /* Copy the element to ring */ - memcpy_toio(&ring_shadow[old_offset], el, sizeof(struct mhi_ep_ring_element)); - - /* Now unmap and free host ring */ - mhi_cntrl->unmap_addr(mhi_cntrl, ring_shadow_phys); - mhi_cntrl->free_addr(mhi_cntrl, ring_shadow_phys, ring_shadow, ring_size); - - return 0; - -err_ring_free: - mhi_cntrl->free_addr(mhi_cntrl, ring_shadow_phys, ring_shadow, ring_size); - - return ret; -======= - dev_dbg(dev, "Adding an element to ring at offset (%zu)\n", ring->rd_offset); - - /* Update rp in ring context */ - ring->ring_ctx->generic.rp = cpu_to_le64((ring->rd_offset * sizeof(*el))) + rbase; - - /* Ensure that the ring pointer gets updated before writing the element to ring */ - smp_wmb(); - - ret = mhi_cntrl->write_to_host(mhi_cntrl, el, (le64_to_cpu(rbase) + - (old_offset * sizeof(*el))), sizeof(*el)); - if (ret < 0) - return ret; - - return 0; ->>>>>>> -} - -void mhi_ep_ring_init(struct mhi_ep_ring *ring, enum mhi_ep_ring_type type, u32 id) -{ -<<<<<<< -======= - ring->state = RING_STATE_UINT; ->>>>>>> - ring->type = type; - if (ring->type == RING_TYPE_CMD) { - ring->ring_cb = mhi_ep_process_cmd_ring; - ring->db_offset_h = CRDB_HIGHER; - ring->db_offset_l = CRDB_LOWER; - } else if (ring->type == RING_TYPE_CH) { - ring->ring_cb = mhi_ep_process_tre_ring; - ring->db_offset_h = CHDB_HIGHER_n(id); - ring->db_offset_l = CHDB_LOWER_n(id); - ring->ch_id = id; -<<<<<<< - } else if (ring->type == RING_TYPE_ER) { -======= - } else { ->>>>>>> - ring->db_offset_h = ERDB_HIGHER_n(id); - ring->db_offset_l = ERDB_LOWER_n(id); - } -} - -int mhi_ep_ring_start(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring, - union mhi_ep_ring_ctx *ctx) -{ - struct device *dev = &mhi_cntrl->mhi_dev->dev; - int ret; - - ring->mhi_cntrl = mhi_cntrl; - ring->ring_ctx = ctx; - ring->ring_size = mhi_ep_ring_num_elems(ring); - -<<<<<<< - /* During ring init, both rp and wp are equal */ - ring->rd_offset = mhi_ep_ring_addr2offset(ring, ring->ring_ctx->generic.rp); - ring->wr_offset = mhi_ep_ring_addr2offset(ring, ring->ring_ctx->generic.rp); - ring->state = RING_STATE_IDLE; -======= - if (ring->type == RING_TYPE_CH) - ring->er_index = le32_to_cpu(ring->ring_ctx->ch.erindex); - - if (ring->type == RING_TYPE_ER) - ring->irq_vector = le32_to_cpu(ring->ring_ctx->ev.msivec); - - /* During ring init, both rp and wp are equal */ - ring->rd_offset = mhi_ep_ring_addr2offset(ring, le64_to_cpu(ring->ring_ctx->generic.rp)); - ring->wr_offset = mhi_ep_ring_addr2offset(ring, le64_to_cpu(ring->ring_ctx->generic.rp)); ->>>>>>> - - /* Allocate ring cache memory for holding the copy of host ring */ - ring->ring_cache = kcalloc(ring->ring_size, sizeof(struct mhi_ep_ring_element), - GFP_KERNEL); - if (!ring->ring_cache) - return -ENOMEM; - -<<<<<<< - ret = mhi_ep_cache_ring(ring, le64_to_cpu(ring->ring_ctx->generic.wp)); -======= - ret = mhi_ep_cache_ring(ring, ring->ring_ctx->generic.wp); ->>>>>>> - if (ret) { - dev_err(dev, "Failed to cache ring\n"); - kfree(ring->ring_cache); - return ret; - } - -<<<<<<< - return 0; -} - -void mhi_ep_ring_stop(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring) -{ - ring->state = RING_STATE_UINT; -======= - ring->started = true; - - return 0; -} - -void mhi_ep_ring_reset(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring) -{ - ring->started = false; ->>>>>>> - kfree(ring->ring_cache); -} diff --git a/rr-cache/6594cb3d560f5363f8ab1a6c52ef7f51e3ff778b/postimage b/rr-cache/6594cb3d560f5363f8ab1a6c52ef7f51e3ff778b/postimage deleted file mode 100644 index 30630e3..0000000 --- a/rr-cache/6594cb3d560f5363f8ab1a6c52ef7f51e3ff778b/postimage +++ /dev/null @@ -1,4549 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x200>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x300>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <421>; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 2>; - operating-points-v2 = <&cpu7_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <355>; - exit-latency-us = <909>; - min-residency-us = <3934>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <241>; - exit-latency-us = <1461>; - min-residency-us = <4488>; - local-timer-stop; - }; - }; - - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; - arm,psci-suspend-param = <0x4100c244>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9987>; - local-timer-stop; - }; - }; - }; - - cpu0_opp_table: cpu0_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu0_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp2: opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp3: opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-peak-kBps = <800000 12902400>; - }; - - cpu0_opp4: opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <800000 12902400>; - }; - - cpu0_opp5: opp-672000000 { - opp-hz = /bits/ 64 <672000000>; - opp-peak-kBps = <800000 15974400>; - }; - - cpu0_opp6: opp-768000000 { - opp-hz = /bits/ 64 <768000000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu0_opp7: opp-844800000 { - opp-hz = /bits/ 64 <844800000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu0_opp8: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <1804000 22732800>; - }; - - cpu0_opp9: opp-1036800000 { - opp-hz = /bits/ 64 <1036800000>; - opp-peak-kBps = <1804000 22732800>; - }; - - cpu0_opp10: opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-peak-kBps = <2188000 25804800>; - }; - - cpu0_opp11: opp-1209600000 { - opp-hz = /bits/ 64 <1209600000>; - opp-peak-kBps = <2188000 31948800>; - }; - - cpu0_opp12: opp-1305600000 { - opp-hz = /bits/ 64 <1305600000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp13: opp-1382400000 { - opp-hz = /bits/ 64 <1382400000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp14: opp-1478400000 { - opp-hz = /bits/ 64 <1478400000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp15: opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - opp-peak-kBps = <3072000 40550400>; - }; - - cpu0_opp16: opp-1632000000 { - opp-hz = /bits/ 64 <1632000000>; - opp-peak-kBps = <3072000 40550400>; - }; - - cpu0_opp17: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <3072000 43008000>; - }; - - cpu0_opp18: opp-1785600000 { - opp-hz = /bits/ 64 <1785600000>; - opp-peak-kBps = <3072000 43008000>; - }; - }; - - cpu4_opp_table: cpu4_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu4_opp1: opp-710400000 { - opp-hz = /bits/ 64 <710400000>; - opp-peak-kBps = <1804000 15974400>; - }; - - cpu4_opp2: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 19660800>; - }; - - cpu4_opp3: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <2188000 22732800>; - }; - - cpu4_opp4: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 25804800>; - }; - - cpu4_opp5: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu4_opp6: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu4_opp7: opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu4_opp8: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu4_opp9: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu4_opp10: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <4068000 43008000>; - }; - - cpu4_opp11: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <6220000 43008000>; - }; - - cpu4_opp12: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <6220000 49152000>; - }; - - cpu4_opp13: opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-peak-kBps = <7216000 49152000>; - }; - - cpu4_opp14: opp-2131200000 { - opp-hz = /bits/ 64 <2131200000>; - opp-peak-kBps = <8368000 49152000>; - }; - - cpu4_opp15: opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu4_opp16: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu4_opp17: opp-2419200000 { - opp-hz = /bits/ 64 <2419200000>; - opp-peak-kBps = <8368000 51609600>; - }; - }; - - cpu7_opp_table: cpu7_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu7_opp1: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 19660800>; - }; - - cpu7_opp2: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <2188000 22732800>; - }; - - cpu7_opp3: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 25804800>; - }; - - cpu7_opp4: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu7_opp5: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu7_opp6: opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu7_opp7: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu7_opp8: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu7_opp9: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <4068000 43008000>; - }; - - cpu7_opp10: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <6220000 43008000>; - }; - - cpu7_opp11: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <6220000 49152000>; - }; - - cpu7_opp12: opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-peak-kBps = <7216000 49152000>; - }; - - cpu7_opp13: opp-2131200000 { - opp-hz = /bits/ 64 <2131200000>; - opp-peak-kBps = <8368000 49152000>; - }; - - cpu7_opp14: opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp15: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp16: opp-2419200000 { - opp-hz = /bits/ 64 <2419200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp17: opp-2534400000 { - opp-hz = /bits/ 64 <2534400000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp18: opp-2649600000 { - opp-hz = /bits/ 64 <2649600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp19: opp-2745600000 { - opp-hz = /bits/ 64 <2745600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp20: opp-2841600000 { - opp-hz = /bits/ 64 <2841600000>; - opp-peak-kBps = <8368000 51609600>; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8150", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: cpu-cluster0 { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@85d00000 { - reg = <0x0 0x85d00000 0x0 0x140000>; - no-map; - }; - - aop_mem: memory@85f00000 { - reg = <0x0 0x85f00000 0x0 0x20000>; - no-map; - }; - - aop_cmd_db: memory@85f20000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85f20000 0x0 0x20000>; - no-map; - }; - - smem_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x3900000>; - no-map; - }; - - rmtfs_mem: memory@89b00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x89b00000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - camera_mem: memory@8b700000 { - reg = <0x0 0x8b700000 0x0 0x500000>; - no-map; - }; - - wlan_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x180000>; - no-map; - }; - - npu_mem: memory@8bd80000 { - reg = <0x0 0x8bd80000 0x0 0x80000>; - no-map; - }; - - adsp_mem: memory@8be00000 { - reg = <0x0 0x8be00000 0x0 0x1a00000>; - no-map; - }; - - mpss_mem: memory@8d800000 { - reg = <0x0 0x8d800000 0x0 0x9600000>; - no-map; - }; - - venus_mem: memory@96e00000 { - reg = <0x0 0x96e00000 0x0 0x500000>; - no-map; - }; - - slpi_mem: memory@97300000 { - reg = <0x0 0x97300000 0x0 0x1400000>; - no-map; - }; - - ipa_fw_mem: memory@98700000 { - reg = <0x0 0x98700000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@98710000 { - reg = <0x0 0x98710000 0x0 0x5000>; - no-map; - }; - - gpu_mem: memory@98715000 { - reg = <0x0 0x98715000 0x0 0x2000>; - no-map; - }; - - spss_mem: memory@98800000 { - reg = <0x0 0x98800000 0x0 0x100000>; - no-map; - }; - - cdsp_mem: memory@98900000 { - reg = <0x0 0x98900000 0x0 0x1400000>; - no-map; - }; - - qseecom_mem: memory@9e400000 { - reg = <0x0 0x9e400000 0x0 0x1400000>; - no-map; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = ; - - mboxes = <&apss_shared 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - - interrupts = ; - - mboxes = <&apss_shared 26>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x0 0x00100000 0x0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; - }; - - gpi_dma0: dma-controller@800000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0x800000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x00d6 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - ethernet: ethernet@20000 { - compatible = "qcom,sm8150-ethqos"; - reg = <0x0 0x00020000 0x0 0x10000>, - <0x0 0x00036000 0x0 0x100>; - reg-names = "stmmaceth", "rgmii"; - clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; - clocks = <&gcc GCC_EMAC_AXI_CLK>, - <&gcc GCC_EMAC_SLV_AHB_CLK>, - <&gcc GCC_EMAC_PTP_CLK>, - <&gcc GCC_EMAC_RGMII_CLK>; - interrupts = , - ; - interrupt-names = "macirq", "eth_lpi"; - - power-domains = <&gcc EMAC_GDSC>; - resets = <&gcc GCC_EMAC_BCR>; - - iommus = <&apps_smmu 0x3C0 0x0>; - - snps,tso; - rx-fifo-depth = <16384>; //4096 default - tx-fifo-depth = <32768>; //4096 default - - status = "disabled"; - }; - - qupv3_id_0: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - iommus = <&apps_smmu 0xc3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c0: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x880000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x884000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@888000 { - compatible = "qcom,geni-spi"; - reg = <0 0x888000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x88c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@890000 { - compatible = "qcom,geni-spi"; - reg = <0 0x890000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x894000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@898000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@898000 { - compatible = "qcom,geni-spi"; - reg = <0 0x898000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@89c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi7: spi@89c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x89c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma1: dma-controller@a00000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0xa00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x0616 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - iommus = <&apps_smmu 0x603 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c8: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi8: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa80000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c9: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi9: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa84000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi10: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa88000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c11: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi11: spi@a8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa8c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart2: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a90000 0x0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = ; - status = "disabled"; - }; - - i2c12: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c12_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi12: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa90000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c16: i2c@94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0094000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c16_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi16: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa94000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi16_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma2: dma-controller@c00000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0xc00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x07b6 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_2: geniqup@cc0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00cc0000 0x0 0x6000>; - - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - iommus = <&apps_smmu 0x7a3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c17: i2c@c80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c17_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi17: spi@c80000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc80000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi17_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c18: i2c@c84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c18_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi18: spi@c84000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc84000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi18_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c19: i2c@c88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c19_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi19: spi@c88000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc88000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi19_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c13: i2c@c8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi13: spi@c8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc8c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c14: i2c@c90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi14: spi@c90000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc90000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c15: i2c@c94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c15_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi15: spi@c94000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc94000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8150-config-noc"; - reg = <0 0x01500000 0 0x7400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sm8150-system-noc"; - reg = <0 0x01620000 0 0x19400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@163a000 { - compatible = "qcom,sm8150-mc-virt"; - reg = <0 0x0163a000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8150-aggre1-noc"; - reg = <0 0x016e0000 0 0xd080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8150-aggre2-noc"; - reg = <0 0x01700000 0 0x20000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - compute_noc: interconnect@1720000 { - compatible = "qcom,sm8150-compute-noc"; - reg = <0 0x01720000 0 0x7000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8150-mmss-noc"; - reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@9200000 { - compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8150-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - - power-domains = <&gcc UFS_PHY_GDSC>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; - pinctrl-0 = <&ufs_dev_reset_assert>; - pinctrl-1 = <&ufs_dev_reset_deassert>; - - iommus = <&apps_smmu 0x300 0>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 300000000>; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8150-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - power-domains = <&gcc UFS_CARD_GDSC>, - <&gcc UFS_PHY_GDSC>; - power-domain-names = "ufs_card_gdsc", "ufs_phy_gdsc"; - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8150-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x0 0x01f40000 0x0 0x40000>; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8150-slpi-pas"; - reg = <0x0 0x02400000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 3>, - <&rpmhpd 2>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "dsps"; - qcom,remote-pid = <3>; - mboxes = <&apss_shared 24>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x05a1 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x05a2 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x05a3 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - - gpu: gpu@2c00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ - compatible = "qcom,adreno-640.1", - "qcom,adreno", - "amd,imageon"; - #stream-id-cells = <16>; - - reg = <0 0x02c00000 0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = ; - - iommus = <&adreno_smmu 0 0x401>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - - status = "disabled"; - - zap-shader { - memory-region = <&gpu_mem>; - }; - - /* note: downstream checks gpu binning for 675 Mhz */ - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-675000000 { - opp-hz = /bits/ 64 <675000000>; - opp-level = ; - }; - - opp-585000000 { - opp-hz = /bits/ 64 <585000000>; - opp-level = ; - }; - - opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-level = ; - }; - - opp-427000000 { - opp-hz = /bits/ 64 <427000000>; - opp-level = ; - }; - - opp-345000000 { - opp-hz = /bits/ 64 <345000000>; - opp-level = ; - }; - - opp-257000000 { - opp-hz = /bits/ 64 <257000000>; - opp-level = ; - }; - }; - }; - - gmu: gmu@2c6a000 { - compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; - - reg = <0 0x02c6a000 0 0x30000>, - <0 0x0b290000 0 0x10000>, - <0 0x0b490000 0 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5 0x400>; - - operating-points-v2 = <&gmu_opp_table>; - - status = "disabled"; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = ; - }; - }; - }; - - gpucc: clock-controller@2c90000 { - compatible = "qcom,sm8150-gpucc"; - reg = <0 0x02c90000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - adreno_smmu: iommu@2ca0000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; - reg = <0 0x02ca0000 0 0x10000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; - clock-names = "ahb", "bus", "iface"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - tlmm: pinctrl@3100000 { - compatible = "qcom,sm8150-pinctrl"; - reg = <0x0 0x03100000 0x0 0x300000>, - <0x0 0x03500000 0x0 0x300000>, - <0x0 0x03900000 0x0 0x300000>, - <0x0 0x03D00000 0x0 0x300000>; - reg-names = "west", "east", "north", "south"; - interrupts = ; - gpio-ranges = <&tlmm 0 0 176>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - qup_i2c0_default: qup-i2c0-default { - mux { - pins = "gpio0", "gpio1"; - function = "qup0"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi0_default: qup-spi0-default { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "qup0"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c1_default: qup-i2c1-default { - mux { - pins = "gpio114", "gpio115"; - function = "qup1"; - }; - - config { - pins = "gpio114", "gpio115"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi1_default: qup-spi1-default { - pins = "gpio114", "gpio115", "gpio116", "gpio117"; - function = "qup1"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c2_default: qup-i2c2-default { - mux { - pins = "gpio126", "gpio127"; - function = "qup2"; - }; - - config { - pins = "gpio126", "gpio127"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi2_default: qup-spi2-default { - pins = "gpio126", "gpio127", "gpio128", "gpio129"; - function = "qup2"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c3_default: qup-i2c3-default { - mux { - pins = "gpio144", "gpio145"; - function = "qup3"; - }; - - config { - pins = "gpio144", "gpio145"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi3_default: qup-spi3-default { - pins = "gpio144", "gpio145", "gpio146", "gpio147"; - function = "qup3"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c4_default: qup-i2c4-default { - mux { - pins = "gpio51", "gpio52"; - function = "qup4"; - }; - - config { - pins = "gpio51", "gpio52"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi4_default: qup-spi4-default { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - function = "qup4"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c5_default: qup-i2c5-default { - mux { - pins = "gpio121", "gpio122"; - function = "qup5"; - }; - - config { - pins = "gpio121", "gpio122"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi5_default: qup-spi5-default { - pins = "gpio119", "gpio120", "gpio121", "gpio122"; - function = "qup5"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c6_default: qup-i2c6-default { - mux { - pins = "gpio6", "gpio7"; - function = "qup6"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi6_default: qup-spi6_default { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "qup6"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c7_default: qup-i2c7-default { - mux { - pins = "gpio98", "gpio99"; - function = "qup7"; - }; - - config { - pins = "gpio98", "gpio99"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi7_default: qup-spi7_default { - pins = "gpio98", "gpio99", "gpio100", "gpio101"; - function = "qup7"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c8_default: qup-i2c8-default { - mux { - pins = "gpio88", "gpio89"; - function = "qup8"; - }; - - config { - pins = "gpio88", "gpio89"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi8_default: qup-spi8-default { - pins = "gpio88", "gpio89", "gpio90", "gpio91"; - function = "qup8"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c9_default: qup-i2c9-default { - mux { - pins = "gpio39", "gpio40"; - function = "qup9"; - }; - - config { - pins = "gpio39", "gpio40"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi9_default: qup-spi9-default { - pins = "gpio39", "gpio40", "gpio41", "gpio42"; - function = "qup9"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c10_default: qup-i2c10-default { - mux { - pins = "gpio9", "gpio10"; - function = "qup10"; - }; - - config { - pins = "gpio9", "gpio10"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi10_default: qup-spi10-default { - pins = "gpio9", "gpio10", "gpio11", "gpio12"; - function = "qup10"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c11_default: qup-i2c11-default { - mux { - pins = "gpio94", "gpio95"; - function = "qup11"; - }; - - config { - pins = "gpio94", "gpio95"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi11_default: qup-spi11-default { - pins = "gpio92", "gpio93", "gpio94", "gpio95"; - function = "qup11"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c12_default: qup-i2c12-default { - mux { - pins = "gpio83", "gpio84"; - function = "qup12"; - }; - - config { - pins = "gpio83", "gpio84"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi12_default: qup-spi12-default { - pins = "gpio83", "gpio84", "gpio85", "gpio86"; - function = "qup12"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c13_default: qup-i2c13-default { - mux { - pins = "gpio43", "gpio44"; - function = "qup13"; - }; - - config { - pins = "gpio43", "gpio44"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi13_default: qup-spi13-default { - pins = "gpio43", "gpio44", "gpio45", "gpio46"; - function = "qup13"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c14_default: qup-i2c14-default { - mux { - pins = "gpio47", "gpio48"; - function = "qup14"; - }; - - config { - pins = "gpio47", "gpio48"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi14_default: qup-spi14-default { - pins = "gpio47", "gpio48", "gpio49", "gpio50"; - function = "qup14"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c15_default: qup-i2c15-default { - mux { - pins = "gpio27", "gpio28"; - function = "qup15"; - }; - - config { - pins = "gpio27", "gpio28"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi15_default: qup-spi15-default { - pins = "gpio27", "gpio28", "gpio29", "gpio30"; - function = "qup15"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c16_default: qup-i2c16-default { - mux { - pins = "gpio86", "gpio85"; - function = "qup16"; - }; - - config { - pins = "gpio86", "gpio85"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi16_default: qup-spi16-default { - pins = "gpio83", "gpio84", "gpio85", "gpio86"; - function = "qup16"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c17_default: qup-i2c17-default { - mux { - pins = "gpio55", "gpio56"; - function = "qup17"; - }; - - config { - pins = "gpio55", "gpio56"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi17_default: qup-spi17-default { - pins = "gpio55", "gpio56", "gpio57", "gpio58"; - function = "qup17"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c18_default: qup-i2c18-default { - mux { - pins = "gpio23", "gpio24"; - function = "qup18"; - }; - - config { - pins = "gpio23", "gpio24"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi18_default: qup-spi18-default { - pins = "gpio23", "gpio24", "gpio25", "gpio26"; - function = "qup18"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c19_default: qup-i2c19-default { - mux { - pins = "gpio57", "gpio58"; - function = "qup19"; - }; - - config { - pins = "gpio57", "gpio58"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi19_default: qup-spi19-default { - pins = "gpio55", "gpio56", "gpio57", "gpio58"; - function = "qup19"; - drive-strength = <6>; - bias-disable; - }; - - ufs_dev_reset_assert: ufs_dev_reset_assert { - config { - pins = "ufs_reset"; - bias-pull-down; /* default: pull down */ - drive-strength = <8>; /* default: 3.1 mA */ - output-low; /* active low reset */ - }; - }; - - ufs_dev_reset_deassert: ufs_dev_reset_deassert { - config { - pins = "ufs_reset"; - bias-pull-down; /* default: pull down */ - /* - * default: 3.1 mA - * check comments under ufs_dev_reset_assert - */ - drive-strength = <8>; - output-high; /* active low reset */ - }; - }; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8150-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>, - <&rpmhpd 0>; - power-domain-names = "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apss_shared 12>; - }; - }; - - stm@6002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x06002000 0 0x1000>, - <0 0x16280000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel0_in7>; - }; - }; - }; - }; - - funnel@6041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06041000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&merge_funnel_in0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - }; - - funnel@6042000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06042000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&merge_funnel_in1>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - funnel1_in4: endpoint { - remote-endpoint = <&swao_replicator_out>; - }; - }; - }; - }; - - funnel@6043000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06043000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel2_out: endpoint { - remote-endpoint = <&merge_funnel_in2>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - reg = <2>; - funnel2_in2: endpoint { - remote-endpoint = <&apss_merge_funnel_out>; - }; - }; - }; - }; - - funnel@6045000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06045000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - merge_funnel_in1: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - - port@2 { - reg = <2>; - merge_funnel_in2: endpoint { - remote-endpoint = <&funnel2_out>; - }; - }; - }; - }; - - replicator@6046000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06046000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&replicator1_in>; - }; - }; - }; - - in-ports { - port { - replicator_in0: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf@6047000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06047000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in0>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&merge_funnel_out>; - }; - }; - }; - }; - - etr@6048000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06048000 0 0x1000>; - iommus = <&apps_smmu 0x05e0 0x0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - replicator@604a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x0604a000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - replicator1_out: endpoint { - remote-endpoint = <&swao_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - replicator1_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - funnel@6b08000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06b08000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - swao_funnel_out: endpoint { - remote-endpoint = <&swao_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - swao_funnel_in: endpoint { - remote-endpoint = <&replicator1_out>; - }; - }; - }; - }; - - etf@6b09000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06b09000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - swao_etf_out: endpoint { - remote-endpoint = <&swao_replicator_in>; - }; - }; - }; - - in-ports { - port { - swao_etf_in: endpoint { - remote-endpoint = <&swao_funnel_out>; - }; - }; - }; - }; - - replicator@6b0a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06b0a000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - qcom,replicator-loses-context; - - out-ports { - port { - swao_replicator_out: endpoint { - remote-endpoint = <&funnel1_in4>; - }; - }; - }; - - in-ports { - port { - swao_replicator_in: endpoint { - remote-endpoint = <&swao_etf_out>; - }; - }; - }; - }; - - etm@7040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07040000 0 0x1000>; - - cpu = <&CPU0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&apss_funnel_in0>; - }; - }; - }; - }; - - etm@7140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07140000 0 0x1000>; - - cpu = <&CPU1>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&apss_funnel_in1>; - }; - }; - }; - }; - - etm@7240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07240000 0 0x1000>; - - cpu = <&CPU2>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&apss_funnel_in2>; - }; - }; - }; - }; - - etm@7340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07340000 0 0x1000>; - - cpu = <&CPU3>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&apss_funnel_in3>; - }; - }; - }; - }; - - etm@7440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07440000 0 0x1000>; - - cpu = <&CPU4>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = <&apss_funnel_in4>; - }; - }; - }; - }; - - etm@7540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07540000 0 0x1000>; - - cpu = <&CPU5>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = <&apss_funnel_in5>; - }; - }; - }; - }; - - etm@7640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07640000 0 0x1000>; - - cpu = <&CPU6>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = <&apss_funnel_in6>; - }; - }; - }; - }; - - etm@7740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07740000 0 0x1000>; - - cpu = <&CPU7>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = <&apss_funnel_in7>; - }; - }; - }; - }; - - funnel@7800000 { /* APSS Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07800000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_funnel_out: endpoint { - remote-endpoint = <&apss_merge_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - apss_funnel_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - apss_funnel_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - apss_funnel_in4: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - apss_funnel_in5: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - apss_funnel_in6: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - apss_funnel_in7: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - funnel@7810000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07810000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = <&funnel2_in2>; - }; - }; - }; - - in-ports { - port { - apss_merge_funnel_in: endpoint { - remote-endpoint = <&apss_funnel_out>; - }; - }; - }; - }; - - remoteproc_cdsp: remoteproc@8300000 { - compatible = "qcom,sm8150-cdsp-pas"; - reg = <0x0 0x08300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "cdsp"; - qcom,remote-pid = <5>; - mboxes = <&apss_shared 4>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x1401 0x2040>, - <&apps_smmu 0x1421 0x0>, - <&apps_smmu 0x2001 0x420>, - <&apps_smmu 0x2041 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2 0x3440>, - <&apps_smmu 0x22 0x3400>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x3 0x3440>, - <&apps_smmu 0x1423 0x0>, - <&apps_smmu 0x2023 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x4 0x3440>, - <&apps_smmu 0x24 0x3400>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x5 0x3440>, - <&apps_smmu 0x25 0x3400>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x6 0x3460>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x7 0x3460>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x8 0x3460>; - }; - - /* note: secure cb9 in downstream */ - }; - }; - }; - - usb_1_hsphy: phy@88e2000 { - compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e2000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_2_hsphy: phy@88e3000 { - compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - }; - - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sm8150-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - usb_2_qmpphy: phy@88eb000 { - compatible = "qcom,sm8150-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: phy@88eb200 { - reg = <0 0x088eb200 0 0x200>, - <0 0x088eb400 0 0x200>, - <0 0x088eb800 0 0x800>, - <0 0x088eb600 0 0x200>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - dc_noc: interconnect@9160000 { - compatible = "qcom,sm8150-dc-noc"; - reg = <0 0x09160000 0 0x3200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9680000 { - compatible = "qcom,sm8150-gem-noc"; - reg = <0 0x09680000 0 0x3e200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x140 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x160 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - camnoc_virt: interconnect@ac00000 { - compatible = "qcom,sm8150-camnoc-virt"; - reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8150-aoss-qmp"; - reg = <0x0 0x0c300000 0x0 0x400>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - }; - - sram@c3f0000 { - compatible = "qcom,rpmh-stats"; - reg = <0 0x0c3f0000 0 0x400>; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c440000 0x0 0x0001100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x0100000>, - <0x0 0x0e700000 0x0 0x00a0000>, - <0x0 0x0c40a000 0x0 0x0026000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - remoteproc_adsp: remoteproc@17300000 { - compatible = "qcom,sm8150-adsp-pas"; - reg = <0x0 0x17300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apss_shared 8>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1b23 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1b24 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1b25 0x0>; - }; - }; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; - - apss_shared: mailbox@17c00000 { - compatible = "qcom,sm8150-apss-shared"; - reg = <0x0 0x17c00000 0x0 0x1000>; - #mbox-cells = <1>; - }; - - watchdog@17c10000 { - compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; - clocks = <&sleep_clk>; - interrupts = ; - }; - - timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17c21000{ - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17c23000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17c25000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17c26000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17c29000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x17c2b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x17c2d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - rpmhcc: clock-controller { - compatible = "qcom,sm8150-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8150-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_svs_l2: opp6 { - opp-level = <224>; - }; - - rpmhpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp8 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp10 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp11 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - - osm_l3: interconnect@18321000 { - compatible = "qcom,sm8150-osm-l3"; - reg = <0 0x18321000 0 0x1400>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; - reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, - <0 0x18327800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1", - "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0 0x18800000 0 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_mem>; - clock-names = "cxo_ref_clk_pin", "qdss"; - clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&apps_smmu 0x0640 0x1>; - status = "disabled"; - }; - - cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0 0x01dc4000 0 0x24000>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - iommus = <&apps_smmu 0x504 0x0011>, - <&apps_smmu 0x506 0x0011>, - <&apps_smmu 0x514 0x0011>, - <&apps_smmu 0x516 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - - crypto: crypto@1dfa000 { - compatible = "qcom,sm8150-qce"; - reg = <0 0x01dfa000 0 0x6000>; - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x504 0x0011>, - <&apps_smmu 0x506 0x0011>, - <&apps_smmu 0x514 0x0011>, - <&apps_smmu 0x516 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 14>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 15>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - compute-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - compute_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - npu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 8>; - - trips { - npu_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-vec-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 9>; - - trips { - modem_vec_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-scl-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 10>; - - trips { - modem_scl_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 11>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/rr-cache/6594cb3d560f5363f8ab1a6c52ef7f51e3ff778b/preimage b/rr-cache/6594cb3d560f5363f8ab1a6c52ef7f51e3ff778b/preimage deleted file mode 100644 index 6a2d56a..0000000 --- a/rr-cache/6594cb3d560f5363f8ab1a6c52ef7f51e3ff778b/preimage +++ /dev/null @@ -1,4563 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x200>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x300>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <421>; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 2>; - operating-points-v2 = <&cpu7_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <355>; - exit-latency-us = <909>; - min-residency-us = <3934>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <241>; - exit-latency-us = <1461>; - min-residency-us = <4488>; - local-timer-stop; - }; - }; - - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; - arm,psci-suspend-param = <0x4100c244>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9987>; - local-timer-stop; - }; - }; - }; - - cpu0_opp_table: cpu0_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu0_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp2: opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp3: opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-peak-kBps = <800000 12902400>; - }; - - cpu0_opp4: opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <800000 12902400>; - }; - - cpu0_opp5: opp-672000000 { - opp-hz = /bits/ 64 <672000000>; - opp-peak-kBps = <800000 15974400>; - }; - - cpu0_opp6: opp-768000000 { - opp-hz = /bits/ 64 <768000000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu0_opp7: opp-844800000 { - opp-hz = /bits/ 64 <844800000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu0_opp8: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <1804000 22732800>; - }; - - cpu0_opp9: opp-1036800000 { - opp-hz = /bits/ 64 <1036800000>; - opp-peak-kBps = <1804000 22732800>; - }; - - cpu0_opp10: opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-peak-kBps = <2188000 25804800>; - }; - - cpu0_opp11: opp-1209600000 { - opp-hz = /bits/ 64 <1209600000>; - opp-peak-kBps = <2188000 31948800>; - }; - - cpu0_opp12: opp-1305600000 { - opp-hz = /bits/ 64 <1305600000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp13: opp-1382400000 { - opp-hz = /bits/ 64 <1382400000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp14: opp-1478400000 { - opp-hz = /bits/ 64 <1478400000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp15: opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - opp-peak-kBps = <3072000 40550400>; - }; - - cpu0_opp16: opp-1632000000 { - opp-hz = /bits/ 64 <1632000000>; - opp-peak-kBps = <3072000 40550400>; - }; - - cpu0_opp17: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <3072000 43008000>; - }; - - cpu0_opp18: opp-1785600000 { - opp-hz = /bits/ 64 <1785600000>; - opp-peak-kBps = <3072000 43008000>; - }; - }; - - cpu4_opp_table: cpu4_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu4_opp1: opp-710400000 { - opp-hz = /bits/ 64 <710400000>; - opp-peak-kBps = <1804000 15974400>; - }; - - cpu4_opp2: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 19660800>; - }; - - cpu4_opp3: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <2188000 22732800>; - }; - - cpu4_opp4: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 25804800>; - }; - - cpu4_opp5: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu4_opp6: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu4_opp7: opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu4_opp8: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu4_opp9: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu4_opp10: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <4068000 43008000>; - }; - - cpu4_opp11: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <6220000 43008000>; - }; - - cpu4_opp12: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <6220000 49152000>; - }; - - cpu4_opp13: opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-peak-kBps = <7216000 49152000>; - }; - - cpu4_opp14: opp-2131200000 { - opp-hz = /bits/ 64 <2131200000>; - opp-peak-kBps = <8368000 49152000>; - }; - - cpu4_opp15: opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu4_opp16: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu4_opp17: opp-2419200000 { - opp-hz = /bits/ 64 <2419200000>; - opp-peak-kBps = <8368000 51609600>; - }; - }; - - cpu7_opp_table: cpu7_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu7_opp1: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 19660800>; - }; - - cpu7_opp2: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <2188000 22732800>; - }; - - cpu7_opp3: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 25804800>; - }; - - cpu7_opp4: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu7_opp5: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu7_opp6: opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu7_opp7: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu7_opp8: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu7_opp9: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <4068000 43008000>; - }; - - cpu7_opp10: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <6220000 43008000>; - }; - - cpu7_opp11: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <6220000 49152000>; - }; - - cpu7_opp12: opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-peak-kBps = <7216000 49152000>; - }; - - cpu7_opp13: opp-2131200000 { - opp-hz = /bits/ 64 <2131200000>; - opp-peak-kBps = <8368000 49152000>; - }; - - cpu7_opp14: opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp15: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp16: opp-2419200000 { - opp-hz = /bits/ 64 <2419200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp17: opp-2534400000 { - opp-hz = /bits/ 64 <2534400000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp18: opp-2649600000 { - opp-hz = /bits/ 64 <2649600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp19: opp-2745600000 { - opp-hz = /bits/ 64 <2745600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp20: opp-2841600000 { - opp-hz = /bits/ 64 <2841600000>; - opp-peak-kBps = <8368000 51609600>; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8150", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: cpu-cluster0 { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@85d00000 { - reg = <0x0 0x85d00000 0x0 0x140000>; - no-map; - }; - - aop_mem: memory@85f00000 { - reg = <0x0 0x85f00000 0x0 0x20000>; - no-map; - }; - - aop_cmd_db: memory@85f20000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85f20000 0x0 0x20000>; - no-map; - }; - - smem_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x3900000>; - no-map; - }; - - rmtfs_mem: memory@89b00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x89b00000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - camera_mem: memory@8b700000 { - reg = <0x0 0x8b700000 0x0 0x500000>; - no-map; - }; - - wlan_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x180000>; - no-map; - }; - - npu_mem: memory@8bd80000 { - reg = <0x0 0x8bd80000 0x0 0x80000>; - no-map; - }; - - adsp_mem: memory@8be00000 { - reg = <0x0 0x8be00000 0x0 0x1a00000>; - no-map; - }; - - mpss_mem: memory@8d800000 { - reg = <0x0 0x8d800000 0x0 0x9600000>; - no-map; - }; - - venus_mem: memory@96e00000 { - reg = <0x0 0x96e00000 0x0 0x500000>; - no-map; - }; - - slpi_mem: memory@97300000 { - reg = <0x0 0x97300000 0x0 0x1400000>; - no-map; - }; - - ipa_fw_mem: memory@98700000 { - reg = <0x0 0x98700000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@98710000 { - reg = <0x0 0x98710000 0x0 0x5000>; - no-map; - }; - - gpu_mem: memory@98715000 { - reg = <0x0 0x98715000 0x0 0x2000>; - no-map; - }; - - spss_mem: memory@98800000 { - reg = <0x0 0x98800000 0x0 0x100000>; - no-map; - }; - - cdsp_mem: memory@98900000 { - reg = <0x0 0x98900000 0x0 0x1400000>; - no-map; - }; - - qseecom_mem: memory@9e400000 { - reg = <0x0 0x9e400000 0x0 0x1400000>; - no-map; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = ; - - mboxes = <&apss_shared 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - - interrupts = ; - - mboxes = <&apss_shared 26>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x0 0x00100000 0x0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; - }; - - gpi_dma0: dma-controller@800000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0x800000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x00d6 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - ethernet: ethernet@20000 { - compatible = "qcom,sm8150-ethqos"; - reg = <0x0 0x00020000 0x0 0x10000>, - <0x0 0x00036000 0x0 0x100>; - reg-names = "stmmaceth", "rgmii"; - clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; - clocks = <&gcc GCC_EMAC_AXI_CLK>, - <&gcc GCC_EMAC_SLV_AHB_CLK>, - <&gcc GCC_EMAC_PTP_CLK>, - <&gcc GCC_EMAC_RGMII_CLK>; -<<<<<<< - interrupts = , - ; -======= - interrupts = , - ; ->>>>>>> - interrupt-names = "macirq", "eth_lpi"; - - power-domains = <&gcc EMAC_GDSC>; - resets = <&gcc GCC_EMAC_BCR>; - - iommus = <&apps_smmu 0x3C0 0x0>; - - snps,tso; -<<<<<<< - rx-fifo-depth = <16384>; //4096 default - tx-fifo-depth = <32768>; //4096 default -======= - rx-fifo-depth = <4096>; //test with 16384 - tx-fifo-depth = <4096>; //test with 32768 ->>>>>>> - - status = "disabled"; - }; - -<<<<<<< -======= - ->>>>>>> - qupv3_id_0: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - iommus = <&apps_smmu 0xc3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c0: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x880000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x884000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@888000 { - compatible = "qcom,geni-spi"; - reg = <0 0x888000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x88c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@890000 { - compatible = "qcom,geni-spi"; - reg = <0 0x890000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x894000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@898000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@898000 { - compatible = "qcom,geni-spi"; - reg = <0 0x898000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@89c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi7: spi@89c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x89c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma1: dma-controller@a00000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0xa00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x0616 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - iommus = <&apps_smmu 0x603 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c8: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi8: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa80000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c9: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi9: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa84000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi10: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa88000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c11: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi11: spi@a8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa8c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart2: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a90000 0x0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = ; - status = "disabled"; - }; - - i2c12: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c12_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi12: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa90000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c16: i2c@94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0094000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c16_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi16: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa94000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi16_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma2: dma-controller@c00000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0xc00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x07b6 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_2: geniqup@cc0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00cc0000 0x0 0x6000>; - - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - iommus = <&apps_smmu 0x7a3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c17: i2c@c80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c17_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi17: spi@c80000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc80000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi17_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c18: i2c@c84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c18_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi18: spi@c84000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc84000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi18_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c19: i2c@c88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c19_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi19: spi@c88000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc88000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi19_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c13: i2c@c8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi13: spi@c8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc8c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c14: i2c@c90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi14: spi@c90000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc90000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c15: i2c@c94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c15_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi15: spi@c94000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc94000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8150-config-noc"; - reg = <0 0x01500000 0 0x7400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sm8150-system-noc"; - reg = <0 0x01620000 0 0x19400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@163a000 { - compatible = "qcom,sm8150-mc-virt"; - reg = <0 0x0163a000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8150-aggre1-noc"; - reg = <0 0x016e0000 0 0xd080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8150-aggre2-noc"; - reg = <0 0x01700000 0 0x20000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - compute_noc: interconnect@1720000 { - compatible = "qcom,sm8150-compute-noc"; - reg = <0 0x01720000 0 0x7000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8150-mmss-noc"; - reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@9200000 { - compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8150-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - - power-domains = <&gcc UFS_PHY_GDSC>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; - pinctrl-0 = <&ufs_dev_reset_assert>; - pinctrl-1 = <&ufs_dev_reset_deassert>; - - iommus = <&apps_smmu 0x300 0>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 300000000>; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8150-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - power-domains = <&gcc UFS_CARD_GDSC>, - <&gcc UFS_PHY_GDSC>; - power-domain-names = "ufs_card_gdsc", "ufs_phy_gdsc"; - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8150-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x0 0x01f40000 0x0 0x40000>; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8150-slpi-pas"; - reg = <0x0 0x02400000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 3>, - <&rpmhpd 2>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "dsps"; - qcom,remote-pid = <3>; - mboxes = <&apss_shared 24>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x05a1 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x05a2 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x05a3 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - - gpu: gpu@2c00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ - compatible = "qcom,adreno-640.1", - "qcom,adreno", - "amd,imageon"; - #stream-id-cells = <16>; - - reg = <0 0x02c00000 0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = ; - - iommus = <&adreno_smmu 0 0x401>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - - status = "disabled"; - - zap-shader { - memory-region = <&gpu_mem>; - }; - - /* note: downstream checks gpu binning for 675 Mhz */ - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-675000000 { - opp-hz = /bits/ 64 <675000000>; - opp-level = ; - }; - - opp-585000000 { - opp-hz = /bits/ 64 <585000000>; - opp-level = ; - }; - - opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-level = ; - }; - - opp-427000000 { - opp-hz = /bits/ 64 <427000000>; - opp-level = ; - }; - - opp-345000000 { - opp-hz = /bits/ 64 <345000000>; - opp-level = ; - }; - - opp-257000000 { - opp-hz = /bits/ 64 <257000000>; - opp-level = ; - }; - }; - }; - - gmu: gmu@2c6a000 { - compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; - - reg = <0 0x02c6a000 0 0x30000>, - <0 0x0b290000 0 0x10000>, - <0 0x0b490000 0 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5 0x400>; - - operating-points-v2 = <&gmu_opp_table>; - - status = "disabled"; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = ; - }; - }; - }; - - gpucc: clock-controller@2c90000 { - compatible = "qcom,sm8150-gpucc"; - reg = <0 0x02c90000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - adreno_smmu: iommu@2ca0000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; - reg = <0 0x02ca0000 0 0x10000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; - clock-names = "ahb", "bus", "iface"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - tlmm: pinctrl@3100000 { - compatible = "qcom,sm8150-pinctrl"; - reg = <0x0 0x03100000 0x0 0x300000>, - <0x0 0x03500000 0x0 0x300000>, - <0x0 0x03900000 0x0 0x300000>, - <0x0 0x03D00000 0x0 0x300000>; - reg-names = "west", "east", "north", "south"; - interrupts = ; - gpio-ranges = <&tlmm 0 0 176>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - qup_i2c0_default: qup-i2c0-default { - mux { - pins = "gpio0", "gpio1"; - function = "qup0"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi0_default: qup-spi0-default { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "qup0"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c1_default: qup-i2c1-default { - mux { - pins = "gpio114", "gpio115"; - function = "qup1"; - }; - - config { - pins = "gpio114", "gpio115"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi1_default: qup-spi1-default { - pins = "gpio114", "gpio115", "gpio116", "gpio117"; - function = "qup1"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c2_default: qup-i2c2-default { - mux { - pins = "gpio126", "gpio127"; - function = "qup2"; - }; - - config { - pins = "gpio126", "gpio127"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi2_default: qup-spi2-default { - pins = "gpio126", "gpio127", "gpio128", "gpio129"; - function = "qup2"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c3_default: qup-i2c3-default { - mux { - pins = "gpio144", "gpio145"; - function = "qup3"; - }; - - config { - pins = "gpio144", "gpio145"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi3_default: qup-spi3-default { - pins = "gpio144", "gpio145", "gpio146", "gpio147"; - function = "qup3"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c4_default: qup-i2c4-default { - mux { - pins = "gpio51", "gpio52"; - function = "qup4"; - }; - - config { - pins = "gpio51", "gpio52"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi4_default: qup-spi4-default { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - function = "qup4"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c5_default: qup-i2c5-default { - mux { - pins = "gpio121", "gpio122"; - function = "qup5"; - }; - - config { - pins = "gpio121", "gpio122"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi5_default: qup-spi5-default { - pins = "gpio119", "gpio120", "gpio121", "gpio122"; - function = "qup5"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c6_default: qup-i2c6-default { - mux { - pins = "gpio6", "gpio7"; - function = "qup6"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi6_default: qup-spi6_default { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "qup6"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c7_default: qup-i2c7-default { - mux { - pins = "gpio98", "gpio99"; - function = "qup7"; - }; - - config { - pins = "gpio98", "gpio99"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi7_default: qup-spi7_default { - pins = "gpio98", "gpio99", "gpio100", "gpio101"; - function = "qup7"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c8_default: qup-i2c8-default { - mux { - pins = "gpio88", "gpio89"; - function = "qup8"; - }; - - config { - pins = "gpio88", "gpio89"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi8_default: qup-spi8-default { - pins = "gpio88", "gpio89", "gpio90", "gpio91"; - function = "qup8"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c9_default: qup-i2c9-default { - mux { - pins = "gpio39", "gpio40"; - function = "qup9"; - }; - - config { - pins = "gpio39", "gpio40"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi9_default: qup-spi9-default { - pins = "gpio39", "gpio40", "gpio41", "gpio42"; - function = "qup9"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c10_default: qup-i2c10-default { - mux { - pins = "gpio9", "gpio10"; - function = "qup10"; - }; - - config { - pins = "gpio9", "gpio10"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi10_default: qup-spi10-default { - pins = "gpio9", "gpio10", "gpio11", "gpio12"; - function = "qup10"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c11_default: qup-i2c11-default { - mux { - pins = "gpio94", "gpio95"; - function = "qup11"; - }; - - config { - pins = "gpio94", "gpio95"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi11_default: qup-spi11-default { - pins = "gpio92", "gpio93", "gpio94", "gpio95"; - function = "qup11"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c12_default: qup-i2c12-default { - mux { - pins = "gpio83", "gpio84"; - function = "qup12"; - }; - - config { - pins = "gpio83", "gpio84"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi12_default: qup-spi12-default { - pins = "gpio83", "gpio84", "gpio85", "gpio86"; - function = "qup12"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c13_default: qup-i2c13-default { - mux { - pins = "gpio43", "gpio44"; - function = "qup13"; - }; - - config { - pins = "gpio43", "gpio44"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi13_default: qup-spi13-default { - pins = "gpio43", "gpio44", "gpio45", "gpio46"; - function = "qup13"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c14_default: qup-i2c14-default { - mux { - pins = "gpio47", "gpio48"; - function = "qup14"; - }; - - config { - pins = "gpio47", "gpio48"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi14_default: qup-spi14-default { - pins = "gpio47", "gpio48", "gpio49", "gpio50"; - function = "qup14"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c15_default: qup-i2c15-default { - mux { - pins = "gpio27", "gpio28"; - function = "qup15"; - }; - - config { - pins = "gpio27", "gpio28"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi15_default: qup-spi15-default { - pins = "gpio27", "gpio28", "gpio29", "gpio30"; - function = "qup15"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c16_default: qup-i2c16-default { - mux { - pins = "gpio86", "gpio85"; - function = "qup16"; - }; - - config { - pins = "gpio86", "gpio85"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi16_default: qup-spi16-default { - pins = "gpio83", "gpio84", "gpio85", "gpio86"; - function = "qup16"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c17_default: qup-i2c17-default { - mux { - pins = "gpio55", "gpio56"; - function = "qup17"; - }; - - config { - pins = "gpio55", "gpio56"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi17_default: qup-spi17-default { - pins = "gpio55", "gpio56", "gpio57", "gpio58"; - function = "qup17"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c18_default: qup-i2c18-default { - mux { - pins = "gpio23", "gpio24"; - function = "qup18"; - }; - - config { - pins = "gpio23", "gpio24"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi18_default: qup-spi18-default { - pins = "gpio23", "gpio24", "gpio25", "gpio26"; - function = "qup18"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c19_default: qup-i2c19-default { - mux { - pins = "gpio57", "gpio58"; - function = "qup19"; - }; - - config { - pins = "gpio57", "gpio58"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi19_default: qup-spi19-default { - pins = "gpio55", "gpio56", "gpio57", "gpio58"; - function = "qup19"; - drive-strength = <6>; - bias-disable; - }; - - ufs_dev_reset_assert: ufs_dev_reset_assert { - config { - pins = "ufs_reset"; - bias-pull-down; /* default: pull down */ - drive-strength = <8>; /* default: 3.1 mA */ - output-low; /* active low reset */ - }; - }; - - ufs_dev_reset_deassert: ufs_dev_reset_deassert { - config { - pins = "ufs_reset"; - bias-pull-down; /* default: pull down */ - /* - * default: 3.1 mA - * check comments under ufs_dev_reset_assert - */ - drive-strength = <8>; - output-high; /* active low reset */ - }; - }; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8150-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>, - <&rpmhpd 0>; - power-domain-names = "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apss_shared 12>; - }; - }; - - stm@6002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x06002000 0 0x1000>, - <0 0x16280000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel0_in7>; - }; - }; - }; - }; - - funnel@6041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06041000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&merge_funnel_in0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - }; - - funnel@6042000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06042000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&merge_funnel_in1>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - funnel1_in4: endpoint { - remote-endpoint = <&swao_replicator_out>; - }; - }; - }; - }; - - funnel@6043000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06043000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel2_out: endpoint { - remote-endpoint = <&merge_funnel_in2>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - reg = <2>; - funnel2_in2: endpoint { - remote-endpoint = <&apss_merge_funnel_out>; - }; - }; - }; - }; - - funnel@6045000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06045000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - merge_funnel_in1: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - - port@2 { - reg = <2>; - merge_funnel_in2: endpoint { - remote-endpoint = <&funnel2_out>; - }; - }; - }; - }; - - replicator@6046000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06046000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&replicator1_in>; - }; - }; - }; - - in-ports { - port { - replicator_in0: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf@6047000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06047000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in0>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&merge_funnel_out>; - }; - }; - }; - }; - - etr@6048000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06048000 0 0x1000>; - iommus = <&apps_smmu 0x05e0 0x0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - replicator@604a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x0604a000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - replicator1_out: endpoint { - remote-endpoint = <&swao_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - replicator1_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - funnel@6b08000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06b08000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - swao_funnel_out: endpoint { - remote-endpoint = <&swao_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - swao_funnel_in: endpoint { - remote-endpoint = <&replicator1_out>; - }; - }; - }; - }; - - etf@6b09000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06b09000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - swao_etf_out: endpoint { - remote-endpoint = <&swao_replicator_in>; - }; - }; - }; - - in-ports { - port { - swao_etf_in: endpoint { - remote-endpoint = <&swao_funnel_out>; - }; - }; - }; - }; - - replicator@6b0a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06b0a000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - qcom,replicator-loses-context; - - out-ports { - port { - swao_replicator_out: endpoint { - remote-endpoint = <&funnel1_in4>; - }; - }; - }; - - in-ports { - port { - swao_replicator_in: endpoint { - remote-endpoint = <&swao_etf_out>; - }; - }; - }; - }; - - etm@7040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07040000 0 0x1000>; - - cpu = <&CPU0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&apss_funnel_in0>; - }; - }; - }; - }; - - etm@7140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07140000 0 0x1000>; - - cpu = <&CPU1>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&apss_funnel_in1>; - }; - }; - }; - }; - - etm@7240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07240000 0 0x1000>; - - cpu = <&CPU2>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&apss_funnel_in2>; - }; - }; - }; - }; - - etm@7340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07340000 0 0x1000>; - - cpu = <&CPU3>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&apss_funnel_in3>; - }; - }; - }; - }; - - etm@7440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07440000 0 0x1000>; - - cpu = <&CPU4>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = <&apss_funnel_in4>; - }; - }; - }; - }; - - etm@7540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07540000 0 0x1000>; - - cpu = <&CPU5>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = <&apss_funnel_in5>; - }; - }; - }; - }; - - etm@7640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07640000 0 0x1000>; - - cpu = <&CPU6>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = <&apss_funnel_in6>; - }; - }; - }; - }; - - etm@7740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07740000 0 0x1000>; - - cpu = <&CPU7>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = <&apss_funnel_in7>; - }; - }; - }; - }; - - funnel@7800000 { /* APSS Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07800000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_funnel_out: endpoint { - remote-endpoint = <&apss_merge_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - apss_funnel_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - apss_funnel_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - apss_funnel_in4: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - apss_funnel_in5: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - apss_funnel_in6: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - apss_funnel_in7: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - funnel@7810000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07810000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = <&funnel2_in2>; - }; - }; - }; - - in-ports { - port { - apss_merge_funnel_in: endpoint { - remote-endpoint = <&apss_funnel_out>; - }; - }; - }; - }; - - remoteproc_cdsp: remoteproc@8300000 { - compatible = "qcom,sm8150-cdsp-pas"; - reg = <0x0 0x08300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "cdsp"; - qcom,remote-pid = <5>; - mboxes = <&apss_shared 4>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x1401 0x2040>, - <&apps_smmu 0x1421 0x0>, - <&apps_smmu 0x2001 0x420>, - <&apps_smmu 0x2041 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2 0x3440>, - <&apps_smmu 0x22 0x3400>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x3 0x3440>, - <&apps_smmu 0x1423 0x0>, - <&apps_smmu 0x2023 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x4 0x3440>, - <&apps_smmu 0x24 0x3400>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x5 0x3440>, - <&apps_smmu 0x25 0x3400>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x6 0x3460>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x7 0x3460>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x8 0x3460>; - }; - - /* note: secure cb9 in downstream */ - }; - }; - }; - - usb_1_hsphy: phy@88e2000 { - compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e2000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_2_hsphy: phy@88e3000 { - compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - }; - - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sm8150-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - usb_2_qmpphy: phy@88eb000 { - compatible = "qcom,sm8150-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: phy@88eb200 { - reg = <0 0x088eb200 0 0x200>, - <0 0x088eb400 0 0x200>, - <0 0x088eb800 0 0x800>, - <0 0x088eb600 0 0x200>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - dc_noc: interconnect@9160000 { - compatible = "qcom,sm8150-dc-noc"; - reg = <0 0x09160000 0 0x3200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9680000 { - compatible = "qcom,sm8150-gem-noc"; - reg = <0 0x09680000 0 0x3e200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x140 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x160 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - camnoc_virt: interconnect@ac00000 { - compatible = "qcom,sm8150-camnoc-virt"; - reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8150-aoss-qmp"; - reg = <0x0 0x0c300000 0x0 0x400>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - }; - - sram@c3f0000 { - compatible = "qcom,rpmh-stats"; - reg = <0 0x0c3f0000 0 0x400>; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c440000 0x0 0x0001100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x0100000>, - <0x0 0x0e700000 0x0 0x00a0000>, - <0x0 0x0c40a000 0x0 0x0026000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - remoteproc_adsp: remoteproc@17300000 { - compatible = "qcom,sm8150-adsp-pas"; - reg = <0x0 0x17300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apss_shared 8>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1b23 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1b24 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1b25 0x0>; - }; - }; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; - - apss_shared: mailbox@17c00000 { - compatible = "qcom,sm8150-apss-shared"; - reg = <0x0 0x17c00000 0x0 0x1000>; - #mbox-cells = <1>; - }; - - watchdog@17c10000 { - compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; - clocks = <&sleep_clk>; - interrupts = ; - }; - - timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17c21000{ - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17c23000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17c25000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17c26000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17c29000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x17c2b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x17c2d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - rpmhcc: clock-controller { - compatible = "qcom,sm8150-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8150-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_svs_l2: opp6 { - opp-level = <224>; - }; - - rpmhpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp8 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp10 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp11 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - - osm_l3: interconnect@18321000 { - compatible = "qcom,sm8150-osm-l3"; - reg = <0 0x18321000 0 0x1400>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; - reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, - <0 0x18327800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1", - "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0 0x18800000 0 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_mem>; - clock-names = "cxo_ref_clk_pin", "qdss"; - clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&apps_smmu 0x0640 0x1>; - status = "disabled"; - }; - - cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0 0x01dc4000 0 0x24000>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - iommus = <&apps_smmu 0x504 0x0011>, - <&apps_smmu 0x506 0x0011>, - <&apps_smmu 0x514 0x0011>, - <&apps_smmu 0x516 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - - crypto: crypto@1dfa000 { - compatible = "qcom,sm8150-qce"; - reg = <0 0x01dfa000 0 0x6000>; - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x504 0x0011>, - <&apps_smmu 0x506 0x0011>, - <&apps_smmu 0x514 0x0011>, - <&apps_smmu 0x516 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 14>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 15>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - compute-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - compute_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - npu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 8>; - - trips { - npu_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-vec-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 9>; - - trips { - modem_vec_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-scl-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 10>; - - trips { - modem_scl_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 11>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/rr-cache/6f338eecf47a026b410d91892f725a5532be98ea/preimage b/rr-cache/6f338eecf47a026b410d91892f725a5532be98ea/preimage deleted file mode 100644 index adf6d25..0000000 --- a/rr-cache/6f338eecf47a026b410d91892f725a5532be98ea/preimage +++ /dev/null @@ -1,4572 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x200>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x300>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <421>; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 2>; - operating-points-v2 = <&cpu7_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <355>; - exit-latency-us = <909>; - min-residency-us = <3934>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <241>; - exit-latency-us = <1461>; - min-residency-us = <4488>; - local-timer-stop; - }; - }; - - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; - arm,psci-suspend-param = <0x4100c244>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9987>; - local-timer-stop; - }; - }; - }; - - cpu0_opp_table: cpu0_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu0_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp2: opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp3: opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-peak-kBps = <800000 12902400>; - }; - - cpu0_opp4: opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <800000 12902400>; - }; - - cpu0_opp5: opp-672000000 { - opp-hz = /bits/ 64 <672000000>; - opp-peak-kBps = <800000 15974400>; - }; - - cpu0_opp6: opp-768000000 { - opp-hz = /bits/ 64 <768000000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu0_opp7: opp-844800000 { - opp-hz = /bits/ 64 <844800000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu0_opp8: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <1804000 22732800>; - }; - - cpu0_opp9: opp-1036800000 { - opp-hz = /bits/ 64 <1036800000>; - opp-peak-kBps = <1804000 22732800>; - }; - - cpu0_opp10: opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-peak-kBps = <2188000 25804800>; - }; - - cpu0_opp11: opp-1209600000 { - opp-hz = /bits/ 64 <1209600000>; - opp-peak-kBps = <2188000 31948800>; - }; - - cpu0_opp12: opp-1305600000 { - opp-hz = /bits/ 64 <1305600000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp13: opp-1382400000 { - opp-hz = /bits/ 64 <1382400000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp14: opp-1478400000 { - opp-hz = /bits/ 64 <1478400000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp15: opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - opp-peak-kBps = <3072000 40550400>; - }; - - cpu0_opp16: opp-1632000000 { - opp-hz = /bits/ 64 <1632000000>; - opp-peak-kBps = <3072000 40550400>; - }; - - cpu0_opp17: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <3072000 43008000>; - }; - - cpu0_opp18: opp-1785600000 { - opp-hz = /bits/ 64 <1785600000>; - opp-peak-kBps = <3072000 43008000>; - }; - }; - - cpu4_opp_table: cpu4_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu4_opp1: opp-710400000 { - opp-hz = /bits/ 64 <710400000>; - opp-peak-kBps = <1804000 15974400>; - }; - - cpu4_opp2: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 19660800>; - }; - - cpu4_opp3: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <2188000 22732800>; - }; - - cpu4_opp4: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 25804800>; - }; - - cpu4_opp5: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu4_opp6: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu4_opp7: opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu4_opp8: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu4_opp9: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu4_opp10: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <4068000 43008000>; - }; - - cpu4_opp11: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <6220000 43008000>; - }; - - cpu4_opp12: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <6220000 49152000>; - }; - - cpu4_opp13: opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-peak-kBps = <7216000 49152000>; - }; - - cpu4_opp14: opp-2131200000 { - opp-hz = /bits/ 64 <2131200000>; - opp-peak-kBps = <8368000 49152000>; - }; - - cpu4_opp15: opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu4_opp16: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu4_opp17: opp-2419200000 { - opp-hz = /bits/ 64 <2419200000>; - opp-peak-kBps = <8368000 51609600>; - }; - }; - - cpu7_opp_table: cpu7_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu7_opp1: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 19660800>; - }; - - cpu7_opp2: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <2188000 22732800>; - }; - - cpu7_opp3: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 25804800>; - }; - - cpu7_opp4: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu7_opp5: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu7_opp6: opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu7_opp7: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu7_opp8: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu7_opp9: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <4068000 43008000>; - }; - - cpu7_opp10: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <6220000 43008000>; - }; - - cpu7_opp11: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <6220000 49152000>; - }; - - cpu7_opp12: opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-peak-kBps = <7216000 49152000>; - }; - - cpu7_opp13: opp-2131200000 { - opp-hz = /bits/ 64 <2131200000>; - opp-peak-kBps = <8368000 49152000>; - }; - - cpu7_opp14: opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp15: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp16: opp-2419200000 { - opp-hz = /bits/ 64 <2419200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp17: opp-2534400000 { - opp-hz = /bits/ 64 <2534400000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp18: opp-2649600000 { - opp-hz = /bits/ 64 <2649600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp19: opp-2745600000 { - opp-hz = /bits/ 64 <2745600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp20: opp-2841600000 { - opp-hz = /bits/ 64 <2841600000>; - opp-peak-kBps = <8368000 51609600>; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8150", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: cpu-cluster0 { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@85d00000 { - reg = <0x0 0x85d00000 0x0 0x140000>; - no-map; - }; - - aop_mem: memory@85f00000 { - reg = <0x0 0x85f00000 0x0 0x20000>; - no-map; - }; - - aop_cmd_db: memory@85f20000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85f20000 0x0 0x20000>; - no-map; - }; - - smem_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x3900000>; - no-map; - }; - - rmtfs_mem: memory@89b00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x89b00000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - camera_mem: memory@8b700000 { - reg = <0x0 0x8b700000 0x0 0x500000>; - no-map; - }; - - wlan_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x180000>; - no-map; - }; - - npu_mem: memory@8bd80000 { - reg = <0x0 0x8bd80000 0x0 0x80000>; - no-map; - }; - - adsp_mem: memory@8be00000 { - reg = <0x0 0x8be00000 0x0 0x1a00000>; - no-map; - }; - - mpss_mem: memory@8d800000 { - reg = <0x0 0x8d800000 0x0 0x9600000>; - no-map; - }; - - venus_mem: memory@96e00000 { - reg = <0x0 0x96e00000 0x0 0x500000>; - no-map; - }; - - slpi_mem: memory@97300000 { - reg = <0x0 0x97300000 0x0 0x1400000>; - no-map; - }; - - ipa_fw_mem: memory@98700000 { - reg = <0x0 0x98700000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@98710000 { - reg = <0x0 0x98710000 0x0 0x5000>; - no-map; - }; - - gpu_mem: memory@98715000 { - reg = <0x0 0x98715000 0x0 0x2000>; - no-map; - }; - - spss_mem: memory@98800000 { - reg = <0x0 0x98800000 0x0 0x100000>; - no-map; - }; - - cdsp_mem: memory@98900000 { - reg = <0x0 0x98900000 0x0 0x1400000>; - no-map; - }; - - qseecom_mem: memory@9e400000 { - reg = <0x0 0x9e400000 0x0 0x1400000>; - no-map; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = ; - - mboxes = <&apss_shared 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - - interrupts = ; - - mboxes = <&apss_shared 26>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x0 0x00100000 0x0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; - }; - - gpi_dma0: dma-controller@800000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0x800000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x00d6 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - ethernet: ethernet@20000 { - compatible = "qcom,sm8150-ethqos"; - reg = <0x0 0x00020000 0x0 0x10000>, - <0x0 0x00036000 0x0 0x100>; - reg-names = "stmmaceth", "rgmii"; - clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; - clocks = <&gcc GCC_EMAC_AXI_CLK>, - <&gcc GCC_EMAC_SLV_AHB_CLK>, - <&gcc GCC_EMAC_PTP_CLK>, - <&gcc GCC_EMAC_RGMII_CLK>; - interrupts = , - ; - interrupt-names = "macirq", "eth_lpi"; - - power-domains = <&gcc EMAC_GDSC>; - resets = <&gcc GCC_EMAC_BCR>; - - iommus = <&apps_smmu 0x3C0 0x0>; - - snps,tso; -<<<<<<< - rx-fifo-depth = <16384>; //4096 default - tx-fifo-depth = <32768>; //4096 default -======= - rx-fifo-depth = <4096>; - tx-fifo-depth = <4096>; ->>>>>>> - - status = "disabled"; - }; - -<<<<<<< -======= - ->>>>>>> - qupv3_id_0: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - iommus = <&apps_smmu 0xc3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c0: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x880000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x884000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@888000 { - compatible = "qcom,geni-spi"; - reg = <0 0x888000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x88c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@890000 { - compatible = "qcom,geni-spi"; - reg = <0 0x890000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x894000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@898000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@898000 { - compatible = "qcom,geni-spi"; - reg = <0 0x898000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@89c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi7: spi@89c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x89c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma1: dma-controller@a00000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0xa00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x0616 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - iommus = <&apps_smmu 0x603 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c8: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi8: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa80000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c9: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi9: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa84000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi10: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa88000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c11: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi11: spi@a8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa8c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart2: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a90000 0x0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = ; - status = "disabled"; - }; - - i2c12: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c12_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi12: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa90000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c16: i2c@94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0094000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c16_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi16: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa94000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi16_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma2: dma-controller@c00000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0xc00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x07b6 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_2: geniqup@cc0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00cc0000 0x0 0x6000>; - - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - iommus = <&apps_smmu 0x7a3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c17: i2c@c80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c17_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi17: spi@c80000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc80000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi17_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c18: i2c@c84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c18_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi18: spi@c84000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc84000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi18_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c19: i2c@c88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c19_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi19: spi@c88000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc88000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi19_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c13: i2c@c8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi13: spi@c8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc8c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c14: i2c@c90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi14: spi@c90000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc90000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c15: i2c@c94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c15_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi15: spi@c94000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc94000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8150-config-noc"; - reg = <0 0x01500000 0 0x7400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sm8150-system-noc"; - reg = <0 0x01620000 0 0x19400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@163a000 { - compatible = "qcom,sm8150-mc-virt"; - reg = <0 0x0163a000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8150-aggre1-noc"; - reg = <0 0x016e0000 0 0xd080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8150-aggre2-noc"; - reg = <0 0x01700000 0 0x20000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - compute_noc: interconnect@1720000 { - compatible = "qcom,sm8150-compute-noc"; - reg = <0 0x01720000 0 0x7000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8150-mmss-noc"; - reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@9200000 { - compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8150-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x400>, <0 0x17c000f0 0 0x60>; - qcom,pdc-ranges = <0 480 94>, <94 609 31>, - <125 63 1>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8150-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; -<<<<<<< - -======= - ->>>>>>> - power-domains = <&gcc UFS_PHY_GDSC>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; - pinctrl-0 = <&ufs_dev_reset_assert>; - pinctrl-1 = <&ufs_dev_reset_deassert>; - - iommus = <&apps_smmu 0x300 0>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 300000000>; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8150-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - power-domains = <&gcc UFS_CARD_GDSC>, - <&gcc UFS_PHY_GDSC>; - power-domain-names = "ufs_card_gdsc", "ufs_phy_gdsc"; - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8150-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x0 0x01f40000 0x0 0x40000>; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8150-slpi-pas"; - reg = <0x0 0x02400000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 3>, - <&rpmhpd 2>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "dsps"; - qcom,remote-pid = <3>; - mboxes = <&apss_shared 24>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x05a1 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x05a2 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x05a3 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - - gpu: gpu@2c00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ - compatible = "qcom,adreno-640.1", - "qcom,adreno", - "amd,imageon"; - - reg = <0 0x02c00000 0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = ; - - iommus = <&adreno_smmu 0 0x401>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - - status = "disabled"; - - zap-shader { - memory-region = <&gpu_mem>; - }; - - /* note: downstream checks gpu binning for 675 Mhz */ - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-675000000 { - opp-hz = /bits/ 64 <675000000>; - opp-level = ; - }; - - opp-585000000 { - opp-hz = /bits/ 64 <585000000>; - opp-level = ; - }; - - opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-level = ; - }; - - opp-427000000 { - opp-hz = /bits/ 64 <427000000>; - opp-level = ; - }; - - opp-345000000 { - opp-hz = /bits/ 64 <345000000>; - opp-level = ; - }; - - opp-257000000 { - opp-hz = /bits/ 64 <257000000>; - opp-level = ; - }; - }; - }; - - gmu: gmu@2c6a000 { - compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; - - reg = <0 0x02c6a000 0 0x30000>, - <0 0x0b290000 0 0x10000>, - <0 0x0b490000 0 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5 0x400>; - - operating-points-v2 = <&gmu_opp_table>; - - status = "disabled"; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = ; - }; - }; - }; - - gpucc: clock-controller@2c90000 { - compatible = "qcom,sm8150-gpucc"; - reg = <0 0x02c90000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - adreno_smmu: iommu@2ca0000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; - reg = <0 0x02ca0000 0 0x10000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; - clock-names = "ahb", "bus", "iface"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - tlmm: pinctrl@3100000 { - compatible = "qcom,sm8150-pinctrl"; - reg = <0x0 0x03100000 0x0 0x300000>, - <0x0 0x03500000 0x0 0x300000>, - <0x0 0x03900000 0x0 0x300000>, - <0x0 0x03D00000 0x0 0x300000>; - reg-names = "west", "east", "north", "south"; - interrupts = ; - gpio-ranges = <&tlmm 0 0 176>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - wakeup-parent = <&pdc>; - - qup_i2c0_default: qup-i2c0-default { - mux { - pins = "gpio0", "gpio1"; - function = "qup0"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi0_default: qup-spi0-default { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "qup0"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c1_default: qup-i2c1-default { - mux { - pins = "gpio114", "gpio115"; - function = "qup1"; - }; - - config { - pins = "gpio114", "gpio115"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi1_default: qup-spi1-default { - pins = "gpio114", "gpio115", "gpio116", "gpio117"; - function = "qup1"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c2_default: qup-i2c2-default { - mux { - pins = "gpio126", "gpio127"; - function = "qup2"; - }; - - config { - pins = "gpio126", "gpio127"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi2_default: qup-spi2-default { - pins = "gpio126", "gpio127", "gpio128", "gpio129"; - function = "qup2"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c3_default: qup-i2c3-default { - mux { - pins = "gpio144", "gpio145"; - function = "qup3"; - }; - - config { - pins = "gpio144", "gpio145"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi3_default: qup-spi3-default { - pins = "gpio144", "gpio145", "gpio146", "gpio147"; - function = "qup3"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c4_default: qup-i2c4-default { - mux { - pins = "gpio51", "gpio52"; - function = "qup4"; - }; - - config { - pins = "gpio51", "gpio52"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi4_default: qup-spi4-default { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - function = "qup4"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c5_default: qup-i2c5-default { - mux { - pins = "gpio121", "gpio122"; - function = "qup5"; - }; - - config { - pins = "gpio121", "gpio122"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi5_default: qup-spi5-default { - pins = "gpio119", "gpio120", "gpio121", "gpio122"; - function = "qup5"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c6_default: qup-i2c6-default { - mux { - pins = "gpio6", "gpio7"; - function = "qup6"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi6_default: qup-spi6_default { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "qup6"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c7_default: qup-i2c7-default { - mux { - pins = "gpio98", "gpio99"; - function = "qup7"; - }; - - config { - pins = "gpio98", "gpio99"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi7_default: qup-spi7_default { - pins = "gpio98", "gpio99", "gpio100", "gpio101"; - function = "qup7"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c8_default: qup-i2c8-default { - mux { - pins = "gpio88", "gpio89"; - function = "qup8"; - }; - - config { - pins = "gpio88", "gpio89"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi8_default: qup-spi8-default { - pins = "gpio88", "gpio89", "gpio90", "gpio91"; - function = "qup8"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c9_default: qup-i2c9-default { - mux { - pins = "gpio39", "gpio40"; - function = "qup9"; - }; - - config { - pins = "gpio39", "gpio40"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi9_default: qup-spi9-default { - pins = "gpio39", "gpio40", "gpio41", "gpio42"; - function = "qup9"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c10_default: qup-i2c10-default { - mux { - pins = "gpio9", "gpio10"; - function = "qup10"; - }; - - config { - pins = "gpio9", "gpio10"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi10_default: qup-spi10-default { - pins = "gpio9", "gpio10", "gpio11", "gpio12"; - function = "qup10"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c11_default: qup-i2c11-default { - mux { - pins = "gpio94", "gpio95"; - function = "qup11"; - }; - - config { - pins = "gpio94", "gpio95"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi11_default: qup-spi11-default { - pins = "gpio92", "gpio93", "gpio94", "gpio95"; - function = "qup11"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c12_default: qup-i2c12-default { - mux { - pins = "gpio83", "gpio84"; - function = "qup12"; - }; - - config { - pins = "gpio83", "gpio84"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi12_default: qup-spi12-default { - pins = "gpio83", "gpio84", "gpio85", "gpio86"; - function = "qup12"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c13_default: qup-i2c13-default { - mux { - pins = "gpio43", "gpio44"; - function = "qup13"; - }; - - config { - pins = "gpio43", "gpio44"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi13_default: qup-spi13-default { - pins = "gpio43", "gpio44", "gpio45", "gpio46"; - function = "qup13"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c14_default: qup-i2c14-default { - mux { - pins = "gpio47", "gpio48"; - function = "qup14"; - }; - - config { - pins = "gpio47", "gpio48"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi14_default: qup-spi14-default { - pins = "gpio47", "gpio48", "gpio49", "gpio50"; - function = "qup14"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c15_default: qup-i2c15-default { - mux { - pins = "gpio27", "gpio28"; - function = "qup15"; - }; - - config { - pins = "gpio27", "gpio28"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi15_default: qup-spi15-default { - pins = "gpio27", "gpio28", "gpio29", "gpio30"; - function = "qup15"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c16_default: qup-i2c16-default { - mux { - pins = "gpio86", "gpio85"; - function = "qup16"; - }; - - config { - pins = "gpio86", "gpio85"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi16_default: qup-spi16-default { - pins = "gpio83", "gpio84", "gpio85", "gpio86"; - function = "qup16"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c17_default: qup-i2c17-default { - mux { - pins = "gpio55", "gpio56"; - function = "qup17"; - }; - - config { - pins = "gpio55", "gpio56"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi17_default: qup-spi17-default { - pins = "gpio55", "gpio56", "gpio57", "gpio58"; - function = "qup17"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c18_default: qup-i2c18-default { - mux { - pins = "gpio23", "gpio24"; - function = "qup18"; - }; - - config { - pins = "gpio23", "gpio24"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi18_default: qup-spi18-default { - pins = "gpio23", "gpio24", "gpio25", "gpio26"; - function = "qup18"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c19_default: qup-i2c19-default { - mux { - pins = "gpio57", "gpio58"; - function = "qup19"; - }; - - config { - pins = "gpio57", "gpio58"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi19_default: qup-spi19-default { - pins = "gpio55", "gpio56", "gpio57", "gpio58"; - function = "qup19"; - drive-strength = <6>; - bias-disable; - }; - - ufs_dev_reset_assert: ufs_dev_reset_assert { - config { - pins = "ufs_reset"; - bias-pull-down; /* default: pull down */ - drive-strength = <8>; /* default: 3.1 mA */ - output-low; /* active low reset */ - }; - }; - - ufs_dev_reset_deassert: ufs_dev_reset_deassert { - config { - pins = "ufs_reset"; - bias-pull-down; /* default: pull down */ - /* - * default: 3.1 mA - * check comments under ufs_dev_reset_assert - */ - drive-strength = <8>; - output-high; /* active low reset */ - }; - }; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8150-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>, - <&rpmhpd 0>; - power-domain-names = "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apss_shared 12>; - }; - }; - - stm@6002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x06002000 0 0x1000>, - <0 0x16280000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel0_in7>; - }; - }; - }; - }; - - funnel@6041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06041000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&merge_funnel_in0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - }; - - funnel@6042000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06042000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&merge_funnel_in1>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - funnel1_in4: endpoint { - remote-endpoint = <&swao_replicator_out>; - }; - }; - }; - }; - - funnel@6043000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06043000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel2_out: endpoint { - remote-endpoint = <&merge_funnel_in2>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - reg = <2>; - funnel2_in2: endpoint { - remote-endpoint = <&apss_merge_funnel_out>; - }; - }; - }; - }; - - funnel@6045000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06045000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - merge_funnel_in1: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - - port@2 { - reg = <2>; - merge_funnel_in2: endpoint { - remote-endpoint = <&funnel2_out>; - }; - }; - }; - }; - - replicator@6046000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06046000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&replicator1_in>; - }; - }; - }; - - in-ports { - port { - replicator_in0: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf@6047000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06047000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in0>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&merge_funnel_out>; - }; - }; - }; - }; - - etr@6048000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06048000 0 0x1000>; - iommus = <&apps_smmu 0x05e0 0x0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - replicator@604a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x0604a000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - replicator1_out: endpoint { - remote-endpoint = <&swao_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - replicator1_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - funnel@6b08000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06b08000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - swao_funnel_out: endpoint { - remote-endpoint = <&swao_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - swao_funnel_in: endpoint { - remote-endpoint = <&replicator1_out>; - }; - }; - }; - }; - - etf@6b09000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06b09000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - swao_etf_out: endpoint { - remote-endpoint = <&swao_replicator_in>; - }; - }; - }; - - in-ports { - port { - swao_etf_in: endpoint { - remote-endpoint = <&swao_funnel_out>; - }; - }; - }; - }; - - replicator@6b0a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06b0a000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - qcom,replicator-loses-context; - - out-ports { - port { - swao_replicator_out: endpoint { - remote-endpoint = <&funnel1_in4>; - }; - }; - }; - - in-ports { - port { - swao_replicator_in: endpoint { - remote-endpoint = <&swao_etf_out>; - }; - }; - }; - }; - - etm@7040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07040000 0 0x1000>; - - cpu = <&CPU0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&apss_funnel_in0>; - }; - }; - }; - }; - - etm@7140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07140000 0 0x1000>; - - cpu = <&CPU1>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&apss_funnel_in1>; - }; - }; - }; - }; - - etm@7240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07240000 0 0x1000>; - - cpu = <&CPU2>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&apss_funnel_in2>; - }; - }; - }; - }; - - etm@7340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07340000 0 0x1000>; - - cpu = <&CPU3>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&apss_funnel_in3>; - }; - }; - }; - }; - - etm@7440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07440000 0 0x1000>; - - cpu = <&CPU4>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = <&apss_funnel_in4>; - }; - }; - }; - }; - - etm@7540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07540000 0 0x1000>; - - cpu = <&CPU5>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = <&apss_funnel_in5>; - }; - }; - }; - }; - - etm@7640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07640000 0 0x1000>; - - cpu = <&CPU6>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = <&apss_funnel_in6>; - }; - }; - }; - }; - - etm@7740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07740000 0 0x1000>; - - cpu = <&CPU7>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = <&apss_funnel_in7>; - }; - }; - }; - }; - - funnel@7800000 { /* APSS Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07800000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_funnel_out: endpoint { - remote-endpoint = <&apss_merge_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - apss_funnel_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - apss_funnel_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - apss_funnel_in4: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - apss_funnel_in5: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - apss_funnel_in6: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - apss_funnel_in7: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - funnel@7810000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07810000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = <&funnel2_in2>; - }; - }; - }; - - in-ports { - port { - apss_merge_funnel_in: endpoint { - remote-endpoint = <&apss_funnel_out>; - }; - }; - }; - }; - - remoteproc_cdsp: remoteproc@8300000 { - compatible = "qcom,sm8150-cdsp-pas"; - reg = <0x0 0x08300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "cdsp"; - qcom,remote-pid = <5>; - mboxes = <&apss_shared 4>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x1401 0x2040>, - <&apps_smmu 0x1421 0x0>, - <&apps_smmu 0x2001 0x420>, - <&apps_smmu 0x2041 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2 0x3440>, - <&apps_smmu 0x22 0x3400>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x3 0x3440>, - <&apps_smmu 0x1423 0x0>, - <&apps_smmu 0x2023 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x4 0x3440>, - <&apps_smmu 0x24 0x3400>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x5 0x3440>, - <&apps_smmu 0x25 0x3400>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x6 0x3460>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x7 0x3460>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x8 0x3460>; - }; - - /* note: secure cb9 in downstream */ - }; - }; - }; - - usb_1_hsphy: phy@88e2000 { - compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e2000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_2_hsphy: phy@88e3000 { - compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - }; - - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sm8150-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - usb_2_qmpphy: phy@88eb000 { - compatible = "qcom,sm8150-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: phy@88eb200 { - reg = <0 0x088eb200 0 0x200>, - <0 0x088eb400 0 0x200>, - <0 0x088eb800 0 0x800>, - <0 0x088eb600 0 0x200>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - dc_noc: interconnect@9160000 { - compatible = "qcom,sm8150-dc-noc"; - reg = <0 0x09160000 0 0x3200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9680000 { - compatible = "qcom,sm8150-gem-noc"; - reg = <0 0x09680000 0 0x3e200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x140 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x160 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - camnoc_virt: interconnect@ac00000 { - compatible = "qcom,sm8150-camnoc-virt"; - reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8150-aoss-qmp"; - reg = <0x0 0x0c300000 0x0 0x400>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - }; - - sram@c3f0000 { - compatible = "qcom,rpmh-stats"; - reg = <0 0x0c3f0000 0 0x400>; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c440000 0x0 0x0001100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x0100000>, - <0x0 0x0e700000 0x0 0x00a0000>, - <0x0 0x0c40a000 0x0 0x0026000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - remoteproc_adsp: remoteproc@17300000 { - compatible = "qcom,sm8150-adsp-pas"; - reg = <0x0 0x17300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apss_shared 8>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1b23 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1b24 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1b25 0x0>; - }; - }; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; - - apss_shared: mailbox@17c00000 { - compatible = "qcom,sm8150-apss-shared"; - reg = <0x0 0x17c00000 0x0 0x1000>; - #mbox-cells = <1>; - }; - - watchdog@17c10000 { - compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; - clocks = <&sleep_clk>; - interrupts = ; - }; - - timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17c21000{ - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17c23000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17c25000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17c26000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17c29000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x17c2b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x17c2d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - rpmhcc: clock-controller { - compatible = "qcom,sm8150-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8150-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_svs_l2: opp6 { - opp-level = <224>; - }; - - rpmhpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp8 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp10 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp11 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - - osm_l3: interconnect@18321000 { - compatible = "qcom,sm8150-osm-l3"; - reg = <0 0x18321000 0 0x1400>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; - reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, - <0 0x18327800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1", - "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0 0x18800000 0 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_mem>; - clock-names = "cxo_ref_clk_pin", "qdss"; - clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&apps_smmu 0x0640 0x1>; - status = "disabled"; - }; - - cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0 0x01dc4000 0 0x24000>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - iommus = <&apps_smmu 0x504 0x0011>, - <&apps_smmu 0x506 0x0011>, - <&apps_smmu 0x514 0x0011>, - <&apps_smmu 0x516 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - - crypto: crypto@1dfa000 { - compatible = "qcom,sm8150-qce"; - reg = <0 0x01dfa000 0 0x6000>; - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x504 0x0011>, - <&apps_smmu 0x506 0x0011>, - <&apps_smmu 0x514 0x0011>, - <&apps_smmu 0x516 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 14>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 15>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - compute-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - compute_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - npu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 8>; - - trips { - npu_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-vec-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 9>; - - trips { - modem_vec_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-scl-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 10>; - - trips { - modem_scl_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 11>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/rr-cache/6f338eecf47a026b410d91892f725a5532be98ea/preimage.1 b/rr-cache/6f338eecf47a026b410d91892f725a5532be98ea/preimage.1 deleted file mode 100644 index adf6d25..0000000 --- a/rr-cache/6f338eecf47a026b410d91892f725a5532be98ea/preimage.1 +++ /dev/null @@ -1,4572 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x200>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x300>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <421>; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 2>; - operating-points-v2 = <&cpu7_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <355>; - exit-latency-us = <909>; - min-residency-us = <3934>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <241>; - exit-latency-us = <1461>; - min-residency-us = <4488>; - local-timer-stop; - }; - }; - - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; - arm,psci-suspend-param = <0x4100c244>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9987>; - local-timer-stop; - }; - }; - }; - - cpu0_opp_table: cpu0_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu0_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp2: opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp3: opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-peak-kBps = <800000 12902400>; - }; - - cpu0_opp4: opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <800000 12902400>; - }; - - cpu0_opp5: opp-672000000 { - opp-hz = /bits/ 64 <672000000>; - opp-peak-kBps = <800000 15974400>; - }; - - cpu0_opp6: opp-768000000 { - opp-hz = /bits/ 64 <768000000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu0_opp7: opp-844800000 { - opp-hz = /bits/ 64 <844800000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu0_opp8: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <1804000 22732800>; - }; - - cpu0_opp9: opp-1036800000 { - opp-hz = /bits/ 64 <1036800000>; - opp-peak-kBps = <1804000 22732800>; - }; - - cpu0_opp10: opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-peak-kBps = <2188000 25804800>; - }; - - cpu0_opp11: opp-1209600000 { - opp-hz = /bits/ 64 <1209600000>; - opp-peak-kBps = <2188000 31948800>; - }; - - cpu0_opp12: opp-1305600000 { - opp-hz = /bits/ 64 <1305600000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp13: opp-1382400000 { - opp-hz = /bits/ 64 <1382400000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp14: opp-1478400000 { - opp-hz = /bits/ 64 <1478400000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp15: opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - opp-peak-kBps = <3072000 40550400>; - }; - - cpu0_opp16: opp-1632000000 { - opp-hz = /bits/ 64 <1632000000>; - opp-peak-kBps = <3072000 40550400>; - }; - - cpu0_opp17: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <3072000 43008000>; - }; - - cpu0_opp18: opp-1785600000 { - opp-hz = /bits/ 64 <1785600000>; - opp-peak-kBps = <3072000 43008000>; - }; - }; - - cpu4_opp_table: cpu4_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu4_opp1: opp-710400000 { - opp-hz = /bits/ 64 <710400000>; - opp-peak-kBps = <1804000 15974400>; - }; - - cpu4_opp2: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 19660800>; - }; - - cpu4_opp3: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <2188000 22732800>; - }; - - cpu4_opp4: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 25804800>; - }; - - cpu4_opp5: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu4_opp6: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu4_opp7: opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu4_opp8: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu4_opp9: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu4_opp10: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <4068000 43008000>; - }; - - cpu4_opp11: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <6220000 43008000>; - }; - - cpu4_opp12: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <6220000 49152000>; - }; - - cpu4_opp13: opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-peak-kBps = <7216000 49152000>; - }; - - cpu4_opp14: opp-2131200000 { - opp-hz = /bits/ 64 <2131200000>; - opp-peak-kBps = <8368000 49152000>; - }; - - cpu4_opp15: opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu4_opp16: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu4_opp17: opp-2419200000 { - opp-hz = /bits/ 64 <2419200000>; - opp-peak-kBps = <8368000 51609600>; - }; - }; - - cpu7_opp_table: cpu7_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu7_opp1: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 19660800>; - }; - - cpu7_opp2: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <2188000 22732800>; - }; - - cpu7_opp3: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 25804800>; - }; - - cpu7_opp4: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu7_opp5: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu7_opp6: opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu7_opp7: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu7_opp8: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu7_opp9: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <4068000 43008000>; - }; - - cpu7_opp10: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <6220000 43008000>; - }; - - cpu7_opp11: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <6220000 49152000>; - }; - - cpu7_opp12: opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-peak-kBps = <7216000 49152000>; - }; - - cpu7_opp13: opp-2131200000 { - opp-hz = /bits/ 64 <2131200000>; - opp-peak-kBps = <8368000 49152000>; - }; - - cpu7_opp14: opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp15: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp16: opp-2419200000 { - opp-hz = /bits/ 64 <2419200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp17: opp-2534400000 { - opp-hz = /bits/ 64 <2534400000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp18: opp-2649600000 { - opp-hz = /bits/ 64 <2649600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp19: opp-2745600000 { - opp-hz = /bits/ 64 <2745600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp20: opp-2841600000 { - opp-hz = /bits/ 64 <2841600000>; - opp-peak-kBps = <8368000 51609600>; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8150", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: cpu-cluster0 { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@85d00000 { - reg = <0x0 0x85d00000 0x0 0x140000>; - no-map; - }; - - aop_mem: memory@85f00000 { - reg = <0x0 0x85f00000 0x0 0x20000>; - no-map; - }; - - aop_cmd_db: memory@85f20000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85f20000 0x0 0x20000>; - no-map; - }; - - smem_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x3900000>; - no-map; - }; - - rmtfs_mem: memory@89b00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x89b00000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - camera_mem: memory@8b700000 { - reg = <0x0 0x8b700000 0x0 0x500000>; - no-map; - }; - - wlan_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x180000>; - no-map; - }; - - npu_mem: memory@8bd80000 { - reg = <0x0 0x8bd80000 0x0 0x80000>; - no-map; - }; - - adsp_mem: memory@8be00000 { - reg = <0x0 0x8be00000 0x0 0x1a00000>; - no-map; - }; - - mpss_mem: memory@8d800000 { - reg = <0x0 0x8d800000 0x0 0x9600000>; - no-map; - }; - - venus_mem: memory@96e00000 { - reg = <0x0 0x96e00000 0x0 0x500000>; - no-map; - }; - - slpi_mem: memory@97300000 { - reg = <0x0 0x97300000 0x0 0x1400000>; - no-map; - }; - - ipa_fw_mem: memory@98700000 { - reg = <0x0 0x98700000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@98710000 { - reg = <0x0 0x98710000 0x0 0x5000>; - no-map; - }; - - gpu_mem: memory@98715000 { - reg = <0x0 0x98715000 0x0 0x2000>; - no-map; - }; - - spss_mem: memory@98800000 { - reg = <0x0 0x98800000 0x0 0x100000>; - no-map; - }; - - cdsp_mem: memory@98900000 { - reg = <0x0 0x98900000 0x0 0x1400000>; - no-map; - }; - - qseecom_mem: memory@9e400000 { - reg = <0x0 0x9e400000 0x0 0x1400000>; - no-map; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = ; - - mboxes = <&apss_shared 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - - interrupts = ; - - mboxes = <&apss_shared 26>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x0 0x00100000 0x0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; - }; - - gpi_dma0: dma-controller@800000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0x800000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x00d6 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - ethernet: ethernet@20000 { - compatible = "qcom,sm8150-ethqos"; - reg = <0x0 0x00020000 0x0 0x10000>, - <0x0 0x00036000 0x0 0x100>; - reg-names = "stmmaceth", "rgmii"; - clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; - clocks = <&gcc GCC_EMAC_AXI_CLK>, - <&gcc GCC_EMAC_SLV_AHB_CLK>, - <&gcc GCC_EMAC_PTP_CLK>, - <&gcc GCC_EMAC_RGMII_CLK>; - interrupts = , - ; - interrupt-names = "macirq", "eth_lpi"; - - power-domains = <&gcc EMAC_GDSC>; - resets = <&gcc GCC_EMAC_BCR>; - - iommus = <&apps_smmu 0x3C0 0x0>; - - snps,tso; -<<<<<<< - rx-fifo-depth = <16384>; //4096 default - tx-fifo-depth = <32768>; //4096 default -======= - rx-fifo-depth = <4096>; - tx-fifo-depth = <4096>; ->>>>>>> - - status = "disabled"; - }; - -<<<<<<< -======= - ->>>>>>> - qupv3_id_0: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - iommus = <&apps_smmu 0xc3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c0: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x880000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x884000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@888000 { - compatible = "qcom,geni-spi"; - reg = <0 0x888000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x88c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@890000 { - compatible = "qcom,geni-spi"; - reg = <0 0x890000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x894000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@898000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@898000 { - compatible = "qcom,geni-spi"; - reg = <0 0x898000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@89c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi7: spi@89c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x89c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma1: dma-controller@a00000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0xa00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x0616 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - iommus = <&apps_smmu 0x603 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c8: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi8: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa80000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c9: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi9: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa84000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi10: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa88000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c11: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi11: spi@a8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa8c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart2: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a90000 0x0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = ; - status = "disabled"; - }; - - i2c12: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c12_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi12: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa90000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c16: i2c@94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0094000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c16_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi16: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa94000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi16_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma2: dma-controller@c00000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0xc00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x07b6 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_2: geniqup@cc0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00cc0000 0x0 0x6000>; - - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - iommus = <&apps_smmu 0x7a3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c17: i2c@c80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c17_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi17: spi@c80000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc80000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi17_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c18: i2c@c84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c18_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi18: spi@c84000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc84000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi18_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c19: i2c@c88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c19_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi19: spi@c88000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc88000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi19_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c13: i2c@c8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi13: spi@c8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc8c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c14: i2c@c90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi14: spi@c90000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc90000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c15: i2c@c94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c15_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi15: spi@c94000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc94000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8150-config-noc"; - reg = <0 0x01500000 0 0x7400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sm8150-system-noc"; - reg = <0 0x01620000 0 0x19400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@163a000 { - compatible = "qcom,sm8150-mc-virt"; - reg = <0 0x0163a000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8150-aggre1-noc"; - reg = <0 0x016e0000 0 0xd080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8150-aggre2-noc"; - reg = <0 0x01700000 0 0x20000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - compute_noc: interconnect@1720000 { - compatible = "qcom,sm8150-compute-noc"; - reg = <0 0x01720000 0 0x7000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8150-mmss-noc"; - reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@9200000 { - compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8150-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x400>, <0 0x17c000f0 0 0x60>; - qcom,pdc-ranges = <0 480 94>, <94 609 31>, - <125 63 1>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8150-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; -<<<<<<< - -======= - ->>>>>>> - power-domains = <&gcc UFS_PHY_GDSC>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; - pinctrl-0 = <&ufs_dev_reset_assert>; - pinctrl-1 = <&ufs_dev_reset_deassert>; - - iommus = <&apps_smmu 0x300 0>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 300000000>; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8150-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - power-domains = <&gcc UFS_CARD_GDSC>, - <&gcc UFS_PHY_GDSC>; - power-domain-names = "ufs_card_gdsc", "ufs_phy_gdsc"; - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8150-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x0 0x01f40000 0x0 0x40000>; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8150-slpi-pas"; - reg = <0x0 0x02400000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 3>, - <&rpmhpd 2>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "dsps"; - qcom,remote-pid = <3>; - mboxes = <&apss_shared 24>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x05a1 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x05a2 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x05a3 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - - gpu: gpu@2c00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ - compatible = "qcom,adreno-640.1", - "qcom,adreno", - "amd,imageon"; - - reg = <0 0x02c00000 0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = ; - - iommus = <&adreno_smmu 0 0x401>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - - status = "disabled"; - - zap-shader { - memory-region = <&gpu_mem>; - }; - - /* note: downstream checks gpu binning for 675 Mhz */ - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-675000000 { - opp-hz = /bits/ 64 <675000000>; - opp-level = ; - }; - - opp-585000000 { - opp-hz = /bits/ 64 <585000000>; - opp-level = ; - }; - - opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-level = ; - }; - - opp-427000000 { - opp-hz = /bits/ 64 <427000000>; - opp-level = ; - }; - - opp-345000000 { - opp-hz = /bits/ 64 <345000000>; - opp-level = ; - }; - - opp-257000000 { - opp-hz = /bits/ 64 <257000000>; - opp-level = ; - }; - }; - }; - - gmu: gmu@2c6a000 { - compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; - - reg = <0 0x02c6a000 0 0x30000>, - <0 0x0b290000 0 0x10000>, - <0 0x0b490000 0 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5 0x400>; - - operating-points-v2 = <&gmu_opp_table>; - - status = "disabled"; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = ; - }; - }; - }; - - gpucc: clock-controller@2c90000 { - compatible = "qcom,sm8150-gpucc"; - reg = <0 0x02c90000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - adreno_smmu: iommu@2ca0000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; - reg = <0 0x02ca0000 0 0x10000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; - clock-names = "ahb", "bus", "iface"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - tlmm: pinctrl@3100000 { - compatible = "qcom,sm8150-pinctrl"; - reg = <0x0 0x03100000 0x0 0x300000>, - <0x0 0x03500000 0x0 0x300000>, - <0x0 0x03900000 0x0 0x300000>, - <0x0 0x03D00000 0x0 0x300000>; - reg-names = "west", "east", "north", "south"; - interrupts = ; - gpio-ranges = <&tlmm 0 0 176>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - wakeup-parent = <&pdc>; - - qup_i2c0_default: qup-i2c0-default { - mux { - pins = "gpio0", "gpio1"; - function = "qup0"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi0_default: qup-spi0-default { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "qup0"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c1_default: qup-i2c1-default { - mux { - pins = "gpio114", "gpio115"; - function = "qup1"; - }; - - config { - pins = "gpio114", "gpio115"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi1_default: qup-spi1-default { - pins = "gpio114", "gpio115", "gpio116", "gpio117"; - function = "qup1"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c2_default: qup-i2c2-default { - mux { - pins = "gpio126", "gpio127"; - function = "qup2"; - }; - - config { - pins = "gpio126", "gpio127"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi2_default: qup-spi2-default { - pins = "gpio126", "gpio127", "gpio128", "gpio129"; - function = "qup2"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c3_default: qup-i2c3-default { - mux { - pins = "gpio144", "gpio145"; - function = "qup3"; - }; - - config { - pins = "gpio144", "gpio145"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi3_default: qup-spi3-default { - pins = "gpio144", "gpio145", "gpio146", "gpio147"; - function = "qup3"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c4_default: qup-i2c4-default { - mux { - pins = "gpio51", "gpio52"; - function = "qup4"; - }; - - config { - pins = "gpio51", "gpio52"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi4_default: qup-spi4-default { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - function = "qup4"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c5_default: qup-i2c5-default { - mux { - pins = "gpio121", "gpio122"; - function = "qup5"; - }; - - config { - pins = "gpio121", "gpio122"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi5_default: qup-spi5-default { - pins = "gpio119", "gpio120", "gpio121", "gpio122"; - function = "qup5"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c6_default: qup-i2c6-default { - mux { - pins = "gpio6", "gpio7"; - function = "qup6"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi6_default: qup-spi6_default { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "qup6"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c7_default: qup-i2c7-default { - mux { - pins = "gpio98", "gpio99"; - function = "qup7"; - }; - - config { - pins = "gpio98", "gpio99"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi7_default: qup-spi7_default { - pins = "gpio98", "gpio99", "gpio100", "gpio101"; - function = "qup7"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c8_default: qup-i2c8-default { - mux { - pins = "gpio88", "gpio89"; - function = "qup8"; - }; - - config { - pins = "gpio88", "gpio89"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi8_default: qup-spi8-default { - pins = "gpio88", "gpio89", "gpio90", "gpio91"; - function = "qup8"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c9_default: qup-i2c9-default { - mux { - pins = "gpio39", "gpio40"; - function = "qup9"; - }; - - config { - pins = "gpio39", "gpio40"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi9_default: qup-spi9-default { - pins = "gpio39", "gpio40", "gpio41", "gpio42"; - function = "qup9"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c10_default: qup-i2c10-default { - mux { - pins = "gpio9", "gpio10"; - function = "qup10"; - }; - - config { - pins = "gpio9", "gpio10"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi10_default: qup-spi10-default { - pins = "gpio9", "gpio10", "gpio11", "gpio12"; - function = "qup10"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c11_default: qup-i2c11-default { - mux { - pins = "gpio94", "gpio95"; - function = "qup11"; - }; - - config { - pins = "gpio94", "gpio95"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi11_default: qup-spi11-default { - pins = "gpio92", "gpio93", "gpio94", "gpio95"; - function = "qup11"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c12_default: qup-i2c12-default { - mux { - pins = "gpio83", "gpio84"; - function = "qup12"; - }; - - config { - pins = "gpio83", "gpio84"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi12_default: qup-spi12-default { - pins = "gpio83", "gpio84", "gpio85", "gpio86"; - function = "qup12"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c13_default: qup-i2c13-default { - mux { - pins = "gpio43", "gpio44"; - function = "qup13"; - }; - - config { - pins = "gpio43", "gpio44"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi13_default: qup-spi13-default { - pins = "gpio43", "gpio44", "gpio45", "gpio46"; - function = "qup13"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c14_default: qup-i2c14-default { - mux { - pins = "gpio47", "gpio48"; - function = "qup14"; - }; - - config { - pins = "gpio47", "gpio48"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi14_default: qup-spi14-default { - pins = "gpio47", "gpio48", "gpio49", "gpio50"; - function = "qup14"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c15_default: qup-i2c15-default { - mux { - pins = "gpio27", "gpio28"; - function = "qup15"; - }; - - config { - pins = "gpio27", "gpio28"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi15_default: qup-spi15-default { - pins = "gpio27", "gpio28", "gpio29", "gpio30"; - function = "qup15"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c16_default: qup-i2c16-default { - mux { - pins = "gpio86", "gpio85"; - function = "qup16"; - }; - - config { - pins = "gpio86", "gpio85"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi16_default: qup-spi16-default { - pins = "gpio83", "gpio84", "gpio85", "gpio86"; - function = "qup16"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c17_default: qup-i2c17-default { - mux { - pins = "gpio55", "gpio56"; - function = "qup17"; - }; - - config { - pins = "gpio55", "gpio56"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi17_default: qup-spi17-default { - pins = "gpio55", "gpio56", "gpio57", "gpio58"; - function = "qup17"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c18_default: qup-i2c18-default { - mux { - pins = "gpio23", "gpio24"; - function = "qup18"; - }; - - config { - pins = "gpio23", "gpio24"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi18_default: qup-spi18-default { - pins = "gpio23", "gpio24", "gpio25", "gpio26"; - function = "qup18"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c19_default: qup-i2c19-default { - mux { - pins = "gpio57", "gpio58"; - function = "qup19"; - }; - - config { - pins = "gpio57", "gpio58"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi19_default: qup-spi19-default { - pins = "gpio55", "gpio56", "gpio57", "gpio58"; - function = "qup19"; - drive-strength = <6>; - bias-disable; - }; - - ufs_dev_reset_assert: ufs_dev_reset_assert { - config { - pins = "ufs_reset"; - bias-pull-down; /* default: pull down */ - drive-strength = <8>; /* default: 3.1 mA */ - output-low; /* active low reset */ - }; - }; - - ufs_dev_reset_deassert: ufs_dev_reset_deassert { - config { - pins = "ufs_reset"; - bias-pull-down; /* default: pull down */ - /* - * default: 3.1 mA - * check comments under ufs_dev_reset_assert - */ - drive-strength = <8>; - output-high; /* active low reset */ - }; - }; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8150-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>, - <&rpmhpd 0>; - power-domain-names = "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apss_shared 12>; - }; - }; - - stm@6002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x06002000 0 0x1000>, - <0 0x16280000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel0_in7>; - }; - }; - }; - }; - - funnel@6041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06041000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&merge_funnel_in0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - }; - - funnel@6042000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06042000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&merge_funnel_in1>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - funnel1_in4: endpoint { - remote-endpoint = <&swao_replicator_out>; - }; - }; - }; - }; - - funnel@6043000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06043000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel2_out: endpoint { - remote-endpoint = <&merge_funnel_in2>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - reg = <2>; - funnel2_in2: endpoint { - remote-endpoint = <&apss_merge_funnel_out>; - }; - }; - }; - }; - - funnel@6045000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06045000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - merge_funnel_in1: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - - port@2 { - reg = <2>; - merge_funnel_in2: endpoint { - remote-endpoint = <&funnel2_out>; - }; - }; - }; - }; - - replicator@6046000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06046000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&replicator1_in>; - }; - }; - }; - - in-ports { - port { - replicator_in0: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf@6047000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06047000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in0>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&merge_funnel_out>; - }; - }; - }; - }; - - etr@6048000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06048000 0 0x1000>; - iommus = <&apps_smmu 0x05e0 0x0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - replicator@604a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x0604a000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - replicator1_out: endpoint { - remote-endpoint = <&swao_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - replicator1_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - funnel@6b08000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06b08000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - swao_funnel_out: endpoint { - remote-endpoint = <&swao_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - swao_funnel_in: endpoint { - remote-endpoint = <&replicator1_out>; - }; - }; - }; - }; - - etf@6b09000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06b09000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - swao_etf_out: endpoint { - remote-endpoint = <&swao_replicator_in>; - }; - }; - }; - - in-ports { - port { - swao_etf_in: endpoint { - remote-endpoint = <&swao_funnel_out>; - }; - }; - }; - }; - - replicator@6b0a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06b0a000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - qcom,replicator-loses-context; - - out-ports { - port { - swao_replicator_out: endpoint { - remote-endpoint = <&funnel1_in4>; - }; - }; - }; - - in-ports { - port { - swao_replicator_in: endpoint { - remote-endpoint = <&swao_etf_out>; - }; - }; - }; - }; - - etm@7040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07040000 0 0x1000>; - - cpu = <&CPU0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&apss_funnel_in0>; - }; - }; - }; - }; - - etm@7140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07140000 0 0x1000>; - - cpu = <&CPU1>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&apss_funnel_in1>; - }; - }; - }; - }; - - etm@7240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07240000 0 0x1000>; - - cpu = <&CPU2>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&apss_funnel_in2>; - }; - }; - }; - }; - - etm@7340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07340000 0 0x1000>; - - cpu = <&CPU3>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&apss_funnel_in3>; - }; - }; - }; - }; - - etm@7440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07440000 0 0x1000>; - - cpu = <&CPU4>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = <&apss_funnel_in4>; - }; - }; - }; - }; - - etm@7540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07540000 0 0x1000>; - - cpu = <&CPU5>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = <&apss_funnel_in5>; - }; - }; - }; - }; - - etm@7640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07640000 0 0x1000>; - - cpu = <&CPU6>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = <&apss_funnel_in6>; - }; - }; - }; - }; - - etm@7740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07740000 0 0x1000>; - - cpu = <&CPU7>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = <&apss_funnel_in7>; - }; - }; - }; - }; - - funnel@7800000 { /* APSS Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07800000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_funnel_out: endpoint { - remote-endpoint = <&apss_merge_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - apss_funnel_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - apss_funnel_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - apss_funnel_in4: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - apss_funnel_in5: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - apss_funnel_in6: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - apss_funnel_in7: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - funnel@7810000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07810000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = <&funnel2_in2>; - }; - }; - }; - - in-ports { - port { - apss_merge_funnel_in: endpoint { - remote-endpoint = <&apss_funnel_out>; - }; - }; - }; - }; - - remoteproc_cdsp: remoteproc@8300000 { - compatible = "qcom,sm8150-cdsp-pas"; - reg = <0x0 0x08300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "cdsp"; - qcom,remote-pid = <5>; - mboxes = <&apss_shared 4>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x1401 0x2040>, - <&apps_smmu 0x1421 0x0>, - <&apps_smmu 0x2001 0x420>, - <&apps_smmu 0x2041 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2 0x3440>, - <&apps_smmu 0x22 0x3400>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x3 0x3440>, - <&apps_smmu 0x1423 0x0>, - <&apps_smmu 0x2023 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x4 0x3440>, - <&apps_smmu 0x24 0x3400>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x5 0x3440>, - <&apps_smmu 0x25 0x3400>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x6 0x3460>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x7 0x3460>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x8 0x3460>; - }; - - /* note: secure cb9 in downstream */ - }; - }; - }; - - usb_1_hsphy: phy@88e2000 { - compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e2000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_2_hsphy: phy@88e3000 { - compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - }; - - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sm8150-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - usb_2_qmpphy: phy@88eb000 { - compatible = "qcom,sm8150-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: phy@88eb200 { - reg = <0 0x088eb200 0 0x200>, - <0 0x088eb400 0 0x200>, - <0 0x088eb800 0 0x800>, - <0 0x088eb600 0 0x200>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - dc_noc: interconnect@9160000 { - compatible = "qcom,sm8150-dc-noc"; - reg = <0 0x09160000 0 0x3200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9680000 { - compatible = "qcom,sm8150-gem-noc"; - reg = <0 0x09680000 0 0x3e200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x140 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x160 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - camnoc_virt: interconnect@ac00000 { - compatible = "qcom,sm8150-camnoc-virt"; - reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8150-aoss-qmp"; - reg = <0x0 0x0c300000 0x0 0x400>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - }; - - sram@c3f0000 { - compatible = "qcom,rpmh-stats"; - reg = <0 0x0c3f0000 0 0x400>; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c440000 0x0 0x0001100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x0100000>, - <0x0 0x0e700000 0x0 0x00a0000>, - <0x0 0x0c40a000 0x0 0x0026000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - remoteproc_adsp: remoteproc@17300000 { - compatible = "qcom,sm8150-adsp-pas"; - reg = <0x0 0x17300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apss_shared 8>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1b23 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1b24 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1b25 0x0>; - }; - }; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; - - apss_shared: mailbox@17c00000 { - compatible = "qcom,sm8150-apss-shared"; - reg = <0x0 0x17c00000 0x0 0x1000>; - #mbox-cells = <1>; - }; - - watchdog@17c10000 { - compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; - clocks = <&sleep_clk>; - interrupts = ; - }; - - timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17c21000{ - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17c23000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17c25000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17c26000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17c29000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x17c2b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x17c2d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - rpmhcc: clock-controller { - compatible = "qcom,sm8150-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8150-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_svs_l2: opp6 { - opp-level = <224>; - }; - - rpmhpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp8 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp10 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp11 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - - osm_l3: interconnect@18321000 { - compatible = "qcom,sm8150-osm-l3"; - reg = <0 0x18321000 0 0x1400>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; - reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, - <0 0x18327800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1", - "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0 0x18800000 0 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_mem>; - clock-names = "cxo_ref_clk_pin", "qdss"; - clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&apps_smmu 0x0640 0x1>; - status = "disabled"; - }; - - cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0 0x01dc4000 0 0x24000>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - iommus = <&apps_smmu 0x504 0x0011>, - <&apps_smmu 0x506 0x0011>, - <&apps_smmu 0x514 0x0011>, - <&apps_smmu 0x516 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - - crypto: crypto@1dfa000 { - compatible = "qcom,sm8150-qce"; - reg = <0 0x01dfa000 0 0x6000>; - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x504 0x0011>, - <&apps_smmu 0x506 0x0011>, - <&apps_smmu 0x514 0x0011>, - <&apps_smmu 0x516 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 14>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 15>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - compute-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - compute_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - npu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 8>; - - trips { - npu_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-vec-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 9>; - - trips { - modem_vec_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-scl-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 10>; - - trips { - modem_scl_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 11>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/rr-cache/6f338eecf47a026b410d91892f725a5532be98ea/preimage.2 b/rr-cache/6f338eecf47a026b410d91892f725a5532be98ea/preimage.2 deleted file mode 100644 index adf6d25..0000000 --- a/rr-cache/6f338eecf47a026b410d91892f725a5532be98ea/preimage.2 +++ /dev/null @@ -1,4572 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x200>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x300>; - enable-method = "psci"; - capacity-dmips-mhz = <488>; - dynamic-power-coefficient = <232>; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <369>; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <421>; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 2>; - operating-points-v2 = <&cpu7_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <355>; - exit-latency-us = <909>; - min-residency-us = <3934>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <241>; - exit-latency-us = <1461>; - min-residency-us = <4488>; - local-timer-stop; - }; - }; - - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; - arm,psci-suspend-param = <0x4100c244>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9987>; - local-timer-stop; - }; - }; - }; - - cpu0_opp_table: cpu0_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu0_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp2: opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp3: opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-peak-kBps = <800000 12902400>; - }; - - cpu0_opp4: opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <800000 12902400>; - }; - - cpu0_opp5: opp-672000000 { - opp-hz = /bits/ 64 <672000000>; - opp-peak-kBps = <800000 15974400>; - }; - - cpu0_opp6: opp-768000000 { - opp-hz = /bits/ 64 <768000000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu0_opp7: opp-844800000 { - opp-hz = /bits/ 64 <844800000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu0_opp8: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <1804000 22732800>; - }; - - cpu0_opp9: opp-1036800000 { - opp-hz = /bits/ 64 <1036800000>; - opp-peak-kBps = <1804000 22732800>; - }; - - cpu0_opp10: opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-peak-kBps = <2188000 25804800>; - }; - - cpu0_opp11: opp-1209600000 { - opp-hz = /bits/ 64 <1209600000>; - opp-peak-kBps = <2188000 31948800>; - }; - - cpu0_opp12: opp-1305600000 { - opp-hz = /bits/ 64 <1305600000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp13: opp-1382400000 { - opp-hz = /bits/ 64 <1382400000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp14: opp-1478400000 { - opp-hz = /bits/ 64 <1478400000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu0_opp15: opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - opp-peak-kBps = <3072000 40550400>; - }; - - cpu0_opp16: opp-1632000000 { - opp-hz = /bits/ 64 <1632000000>; - opp-peak-kBps = <3072000 40550400>; - }; - - cpu0_opp17: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <3072000 43008000>; - }; - - cpu0_opp18: opp-1785600000 { - opp-hz = /bits/ 64 <1785600000>; - opp-peak-kBps = <3072000 43008000>; - }; - }; - - cpu4_opp_table: cpu4_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu4_opp1: opp-710400000 { - opp-hz = /bits/ 64 <710400000>; - opp-peak-kBps = <1804000 15974400>; - }; - - cpu4_opp2: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 19660800>; - }; - - cpu4_opp3: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <2188000 22732800>; - }; - - cpu4_opp4: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 25804800>; - }; - - cpu4_opp5: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu4_opp6: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu4_opp7: opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu4_opp8: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu4_opp9: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu4_opp10: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <4068000 43008000>; - }; - - cpu4_opp11: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <6220000 43008000>; - }; - - cpu4_opp12: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <6220000 49152000>; - }; - - cpu4_opp13: opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-peak-kBps = <7216000 49152000>; - }; - - cpu4_opp14: opp-2131200000 { - opp-hz = /bits/ 64 <2131200000>; - opp-peak-kBps = <8368000 49152000>; - }; - - cpu4_opp15: opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu4_opp16: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu4_opp17: opp-2419200000 { - opp-hz = /bits/ 64 <2419200000>; - opp-peak-kBps = <8368000 51609600>; - }; - }; - - cpu7_opp_table: cpu7_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu7_opp1: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 19660800>; - }; - - cpu7_opp2: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <2188000 22732800>; - }; - - cpu7_opp3: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 25804800>; - }; - - cpu7_opp4: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <3072000 31948800>; - }; - - cpu7_opp5: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu7_opp6: opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <4068000 31948800>; - }; - - cpu7_opp7: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu7_opp8: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 40550400>; - }; - - cpu7_opp9: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <4068000 43008000>; - }; - - cpu7_opp10: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <6220000 43008000>; - }; - - cpu7_opp11: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <6220000 49152000>; - }; - - cpu7_opp12: opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-peak-kBps = <7216000 49152000>; - }; - - cpu7_opp13: opp-2131200000 { - opp-hz = /bits/ 64 <2131200000>; - opp-peak-kBps = <8368000 49152000>; - }; - - cpu7_opp14: opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp15: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp16: opp-2419200000 { - opp-hz = /bits/ 64 <2419200000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp17: opp-2534400000 { - opp-hz = /bits/ 64 <2534400000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp18: opp-2649600000 { - opp-hz = /bits/ 64 <2649600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp19: opp-2745600000 { - opp-hz = /bits/ 64 <2745600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp20: opp-2841600000 { - opp-hz = /bits/ 64 <2841600000>; - opp-peak-kBps = <8368000 51609600>; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8150", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: cpu-cluster0 { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@85d00000 { - reg = <0x0 0x85d00000 0x0 0x140000>; - no-map; - }; - - aop_mem: memory@85f00000 { - reg = <0x0 0x85f00000 0x0 0x20000>; - no-map; - }; - - aop_cmd_db: memory@85f20000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85f20000 0x0 0x20000>; - no-map; - }; - - smem_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x3900000>; - no-map; - }; - - rmtfs_mem: memory@89b00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x89b00000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - camera_mem: memory@8b700000 { - reg = <0x0 0x8b700000 0x0 0x500000>; - no-map; - }; - - wlan_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x180000>; - no-map; - }; - - npu_mem: memory@8bd80000 { - reg = <0x0 0x8bd80000 0x0 0x80000>; - no-map; - }; - - adsp_mem: memory@8be00000 { - reg = <0x0 0x8be00000 0x0 0x1a00000>; - no-map; - }; - - mpss_mem: memory@8d800000 { - reg = <0x0 0x8d800000 0x0 0x9600000>; - no-map; - }; - - venus_mem: memory@96e00000 { - reg = <0x0 0x96e00000 0x0 0x500000>; - no-map; - }; - - slpi_mem: memory@97300000 { - reg = <0x0 0x97300000 0x0 0x1400000>; - no-map; - }; - - ipa_fw_mem: memory@98700000 { - reg = <0x0 0x98700000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@98710000 { - reg = <0x0 0x98710000 0x0 0x5000>; - no-map; - }; - - gpu_mem: memory@98715000 { - reg = <0x0 0x98715000 0x0 0x2000>; - no-map; - }; - - spss_mem: memory@98800000 { - reg = <0x0 0x98800000 0x0 0x100000>; - no-map; - }; - - cdsp_mem: memory@98900000 { - reg = <0x0 0x98900000 0x0 0x1400000>; - no-map; - }; - - qseecom_mem: memory@9e400000 { - reg = <0x0 0x9e400000 0x0 0x1400000>; - no-map; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = ; - - mboxes = <&apss_shared 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - - interrupts = ; - - mboxes = <&apss_shared 26>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x0 0x00100000 0x0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; - }; - - gpi_dma0: dma-controller@800000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0x800000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x00d6 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - ethernet: ethernet@20000 { - compatible = "qcom,sm8150-ethqos"; - reg = <0x0 0x00020000 0x0 0x10000>, - <0x0 0x00036000 0x0 0x100>; - reg-names = "stmmaceth", "rgmii"; - clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; - clocks = <&gcc GCC_EMAC_AXI_CLK>, - <&gcc GCC_EMAC_SLV_AHB_CLK>, - <&gcc GCC_EMAC_PTP_CLK>, - <&gcc GCC_EMAC_RGMII_CLK>; - interrupts = , - ; - interrupt-names = "macirq", "eth_lpi"; - - power-domains = <&gcc EMAC_GDSC>; - resets = <&gcc GCC_EMAC_BCR>; - - iommus = <&apps_smmu 0x3C0 0x0>; - - snps,tso; -<<<<<<< - rx-fifo-depth = <16384>; //4096 default - tx-fifo-depth = <32768>; //4096 default -======= - rx-fifo-depth = <4096>; - tx-fifo-depth = <4096>; ->>>>>>> - - status = "disabled"; - }; - -<<<<<<< -======= - ->>>>>>> - qupv3_id_0: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - iommus = <&apps_smmu 0xc3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c0: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x880000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x884000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@888000 { - compatible = "qcom,geni-spi"; - reg = <0 0x888000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x88c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@890000 { - compatible = "qcom,geni-spi"; - reg = <0 0x890000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x894000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@898000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@898000 { - compatible = "qcom,geni-spi"; - reg = <0 0x898000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@89c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi7: spi@89c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x89c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma1: dma-controller@a00000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0xa00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x0616 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - iommus = <&apps_smmu 0x603 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c8: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi8: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa80000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c9: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi9: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa84000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi10: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa88000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c11: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi11: spi@a8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa8c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart2: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a90000 0x0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = ; - status = "disabled"; - }; - - i2c12: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c12_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi12: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa90000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c16: i2c@94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0094000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c16_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi16: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0xa94000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi16_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma2: dma-controller@c00000 { - compatible = "qcom,sm8150-gpi-dma"; - reg = <0 0xc00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <13>; - dma-channel-mask = <0xfa>; - iommus = <&apps_smmu 0x07b6 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_2: geniqup@cc0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00cc0000 0x0 0x6000>; - - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - iommus = <&apps_smmu 0x7a3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c17: i2c@c80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c17_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi17: spi@c80000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc80000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi17_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c18: i2c@c84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c18_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi18: spi@c84000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc84000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi18_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c19: i2c@c88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c19_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi19: spi@c88000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc88000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi19_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c13: i2c@c8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi13: spi@c8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc8c000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c14: i2c@c90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi14: spi@c90000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc90000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c15: i2c@c94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00c94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c15_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi15: spi@c94000 { - compatible = "qcom,geni-spi"; - reg = <0 0xc94000 0 0x4000>; - reg-names = "se"; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; - interrupts = ; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8150-config-noc"; - reg = <0 0x01500000 0 0x7400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sm8150-system-noc"; - reg = <0 0x01620000 0 0x19400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@163a000 { - compatible = "qcom,sm8150-mc-virt"; - reg = <0 0x0163a000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8150-aggre1-noc"; - reg = <0 0x016e0000 0 0xd080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8150-aggre2-noc"; - reg = <0 0x01700000 0 0x20000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - compute_noc: interconnect@1720000 { - compatible = "qcom,sm8150-compute-noc"; - reg = <0 0x01720000 0 0x7000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8150-mmss-noc"; - reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@9200000 { - compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8150-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x400>, <0 0x17c000f0 0 0x60>; - qcom,pdc-ranges = <0 480 94>, <94 609 31>, - <125 63 1>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8150-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; -<<<<<<< - -======= - ->>>>>>> - power-domains = <&gcc UFS_PHY_GDSC>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; - pinctrl-0 = <&ufs_dev_reset_assert>; - pinctrl-1 = <&ufs_dev_reset_deassert>; - - iommus = <&apps_smmu 0x300 0>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 300000000>; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8150-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - power-domains = <&gcc UFS_CARD_GDSC>, - <&gcc UFS_PHY_GDSC>; - power-domain-names = "ufs_card_gdsc", "ufs_phy_gdsc"; - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8150-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x0 0x01f40000 0x0 0x40000>; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8150-slpi-pas"; - reg = <0x0 0x02400000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 3>, - <&rpmhpd 2>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "dsps"; - qcom,remote-pid = <3>; - mboxes = <&apss_shared 24>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x05a1 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x05a2 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x05a3 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - - gpu: gpu@2c00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ - compatible = "qcom,adreno-640.1", - "qcom,adreno", - "amd,imageon"; - - reg = <0 0x02c00000 0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = ; - - iommus = <&adreno_smmu 0 0x401>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - - status = "disabled"; - - zap-shader { - memory-region = <&gpu_mem>; - }; - - /* note: downstream checks gpu binning for 675 Mhz */ - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-675000000 { - opp-hz = /bits/ 64 <675000000>; - opp-level = ; - }; - - opp-585000000 { - opp-hz = /bits/ 64 <585000000>; - opp-level = ; - }; - - opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-level = ; - }; - - opp-427000000 { - opp-hz = /bits/ 64 <427000000>; - opp-level = ; - }; - - opp-345000000 { - opp-hz = /bits/ 64 <345000000>; - opp-level = ; - }; - - opp-257000000 { - opp-hz = /bits/ 64 <257000000>; - opp-level = ; - }; - }; - }; - - gmu: gmu@2c6a000 { - compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; - - reg = <0 0x02c6a000 0 0x30000>, - <0 0x0b290000 0 0x10000>, - <0 0x0b490000 0 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5 0x400>; - - operating-points-v2 = <&gmu_opp_table>; - - status = "disabled"; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = ; - }; - }; - }; - - gpucc: clock-controller@2c90000 { - compatible = "qcom,sm8150-gpucc"; - reg = <0 0x02c90000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - adreno_smmu: iommu@2ca0000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; - reg = <0 0x02ca0000 0 0x10000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; - clock-names = "ahb", "bus", "iface"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - tlmm: pinctrl@3100000 { - compatible = "qcom,sm8150-pinctrl"; - reg = <0x0 0x03100000 0x0 0x300000>, - <0x0 0x03500000 0x0 0x300000>, - <0x0 0x03900000 0x0 0x300000>, - <0x0 0x03D00000 0x0 0x300000>; - reg-names = "west", "east", "north", "south"; - interrupts = ; - gpio-ranges = <&tlmm 0 0 176>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - wakeup-parent = <&pdc>; - - qup_i2c0_default: qup-i2c0-default { - mux { - pins = "gpio0", "gpio1"; - function = "qup0"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi0_default: qup-spi0-default { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "qup0"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c1_default: qup-i2c1-default { - mux { - pins = "gpio114", "gpio115"; - function = "qup1"; - }; - - config { - pins = "gpio114", "gpio115"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi1_default: qup-spi1-default { - pins = "gpio114", "gpio115", "gpio116", "gpio117"; - function = "qup1"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c2_default: qup-i2c2-default { - mux { - pins = "gpio126", "gpio127"; - function = "qup2"; - }; - - config { - pins = "gpio126", "gpio127"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi2_default: qup-spi2-default { - pins = "gpio126", "gpio127", "gpio128", "gpio129"; - function = "qup2"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c3_default: qup-i2c3-default { - mux { - pins = "gpio144", "gpio145"; - function = "qup3"; - }; - - config { - pins = "gpio144", "gpio145"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi3_default: qup-spi3-default { - pins = "gpio144", "gpio145", "gpio146", "gpio147"; - function = "qup3"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c4_default: qup-i2c4-default { - mux { - pins = "gpio51", "gpio52"; - function = "qup4"; - }; - - config { - pins = "gpio51", "gpio52"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi4_default: qup-spi4-default { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - function = "qup4"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c5_default: qup-i2c5-default { - mux { - pins = "gpio121", "gpio122"; - function = "qup5"; - }; - - config { - pins = "gpio121", "gpio122"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi5_default: qup-spi5-default { - pins = "gpio119", "gpio120", "gpio121", "gpio122"; - function = "qup5"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c6_default: qup-i2c6-default { - mux { - pins = "gpio6", "gpio7"; - function = "qup6"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi6_default: qup-spi6_default { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "qup6"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c7_default: qup-i2c7-default { - mux { - pins = "gpio98", "gpio99"; - function = "qup7"; - }; - - config { - pins = "gpio98", "gpio99"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi7_default: qup-spi7_default { - pins = "gpio98", "gpio99", "gpio100", "gpio101"; - function = "qup7"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c8_default: qup-i2c8-default { - mux { - pins = "gpio88", "gpio89"; - function = "qup8"; - }; - - config { - pins = "gpio88", "gpio89"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi8_default: qup-spi8-default { - pins = "gpio88", "gpio89", "gpio90", "gpio91"; - function = "qup8"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c9_default: qup-i2c9-default { - mux { - pins = "gpio39", "gpio40"; - function = "qup9"; - }; - - config { - pins = "gpio39", "gpio40"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi9_default: qup-spi9-default { - pins = "gpio39", "gpio40", "gpio41", "gpio42"; - function = "qup9"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c10_default: qup-i2c10-default { - mux { - pins = "gpio9", "gpio10"; - function = "qup10"; - }; - - config { - pins = "gpio9", "gpio10"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi10_default: qup-spi10-default { - pins = "gpio9", "gpio10", "gpio11", "gpio12"; - function = "qup10"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c11_default: qup-i2c11-default { - mux { - pins = "gpio94", "gpio95"; - function = "qup11"; - }; - - config { - pins = "gpio94", "gpio95"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi11_default: qup-spi11-default { - pins = "gpio92", "gpio93", "gpio94", "gpio95"; - function = "qup11"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c12_default: qup-i2c12-default { - mux { - pins = "gpio83", "gpio84"; - function = "qup12"; - }; - - config { - pins = "gpio83", "gpio84"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi12_default: qup-spi12-default { - pins = "gpio83", "gpio84", "gpio85", "gpio86"; - function = "qup12"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c13_default: qup-i2c13-default { - mux { - pins = "gpio43", "gpio44"; - function = "qup13"; - }; - - config { - pins = "gpio43", "gpio44"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi13_default: qup-spi13-default { - pins = "gpio43", "gpio44", "gpio45", "gpio46"; - function = "qup13"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c14_default: qup-i2c14-default { - mux { - pins = "gpio47", "gpio48"; - function = "qup14"; - }; - - config { - pins = "gpio47", "gpio48"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi14_default: qup-spi14-default { - pins = "gpio47", "gpio48", "gpio49", "gpio50"; - function = "qup14"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c15_default: qup-i2c15-default { - mux { - pins = "gpio27", "gpio28"; - function = "qup15"; - }; - - config { - pins = "gpio27", "gpio28"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi15_default: qup-spi15-default { - pins = "gpio27", "gpio28", "gpio29", "gpio30"; - function = "qup15"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c16_default: qup-i2c16-default { - mux { - pins = "gpio86", "gpio85"; - function = "qup16"; - }; - - config { - pins = "gpio86", "gpio85"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi16_default: qup-spi16-default { - pins = "gpio83", "gpio84", "gpio85", "gpio86"; - function = "qup16"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c17_default: qup-i2c17-default { - mux { - pins = "gpio55", "gpio56"; - function = "qup17"; - }; - - config { - pins = "gpio55", "gpio56"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi17_default: qup-spi17-default { - pins = "gpio55", "gpio56", "gpio57", "gpio58"; - function = "qup17"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c18_default: qup-i2c18-default { - mux { - pins = "gpio23", "gpio24"; - function = "qup18"; - }; - - config { - pins = "gpio23", "gpio24"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi18_default: qup-spi18-default { - pins = "gpio23", "gpio24", "gpio25", "gpio26"; - function = "qup18"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c19_default: qup-i2c19-default { - mux { - pins = "gpio57", "gpio58"; - function = "qup19"; - }; - - config { - pins = "gpio57", "gpio58"; - drive-strength = <0x02>; - bias-disable; - }; - }; - - qup_spi19_default: qup-spi19-default { - pins = "gpio55", "gpio56", "gpio57", "gpio58"; - function = "qup19"; - drive-strength = <6>; - bias-disable; - }; - - ufs_dev_reset_assert: ufs_dev_reset_assert { - config { - pins = "ufs_reset"; - bias-pull-down; /* default: pull down */ - drive-strength = <8>; /* default: 3.1 mA */ - output-low; /* active low reset */ - }; - }; - - ufs_dev_reset_deassert: ufs_dev_reset_deassert { - config { - pins = "ufs_reset"; - bias-pull-down; /* default: pull down */ - /* - * default: 3.1 mA - * check comments under ufs_dev_reset_assert - */ - drive-strength = <8>; - output-high; /* active low reset */ - }; - }; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8150-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>, - <&rpmhpd 0>; - power-domain-names = "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apss_shared 12>; - }; - }; - - stm@6002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x06002000 0 0x1000>, - <0 0x16280000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel0_in7>; - }; - }; - }; - }; - - funnel@6041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06041000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&merge_funnel_in0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - }; - - funnel@6042000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06042000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&merge_funnel_in1>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - funnel1_in4: endpoint { - remote-endpoint = <&swao_replicator_out>; - }; - }; - }; - }; - - funnel@6043000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06043000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel2_out: endpoint { - remote-endpoint = <&merge_funnel_in2>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - reg = <2>; - funnel2_in2: endpoint { - remote-endpoint = <&apss_merge_funnel_out>; - }; - }; - }; - }; - - funnel@6045000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06045000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - merge_funnel_in1: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - - port@2 { - reg = <2>; - merge_funnel_in2: endpoint { - remote-endpoint = <&funnel2_out>; - }; - }; - }; - }; - - replicator@6046000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06046000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&replicator1_in>; - }; - }; - }; - - in-ports { - port { - replicator_in0: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf@6047000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06047000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in0>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&merge_funnel_out>; - }; - }; - }; - }; - - etr@6048000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06048000 0 0x1000>; - iommus = <&apps_smmu 0x05e0 0x0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - replicator@604a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x0604a000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - replicator1_out: endpoint { - remote-endpoint = <&swao_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - replicator1_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - funnel@6b08000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06b08000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - swao_funnel_out: endpoint { - remote-endpoint = <&swao_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - swao_funnel_in: endpoint { - remote-endpoint = <&replicator1_out>; - }; - }; - }; - }; - - etf@6b09000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06b09000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - swao_etf_out: endpoint { - remote-endpoint = <&swao_replicator_in>; - }; - }; - }; - - in-ports { - port { - swao_etf_in: endpoint { - remote-endpoint = <&swao_funnel_out>; - }; - }; - }; - }; - - replicator@6b0a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06b0a000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - qcom,replicator-loses-context; - - out-ports { - port { - swao_replicator_out: endpoint { - remote-endpoint = <&funnel1_in4>; - }; - }; - }; - - in-ports { - port { - swao_replicator_in: endpoint { - remote-endpoint = <&swao_etf_out>; - }; - }; - }; - }; - - etm@7040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07040000 0 0x1000>; - - cpu = <&CPU0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&apss_funnel_in0>; - }; - }; - }; - }; - - etm@7140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07140000 0 0x1000>; - - cpu = <&CPU1>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&apss_funnel_in1>; - }; - }; - }; - }; - - etm@7240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07240000 0 0x1000>; - - cpu = <&CPU2>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&apss_funnel_in2>; - }; - }; - }; - }; - - etm@7340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07340000 0 0x1000>; - - cpu = <&CPU3>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&apss_funnel_in3>; - }; - }; - }; - }; - - etm@7440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07440000 0 0x1000>; - - cpu = <&CPU4>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = <&apss_funnel_in4>; - }; - }; - }; - }; - - etm@7540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07540000 0 0x1000>; - - cpu = <&CPU5>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = <&apss_funnel_in5>; - }; - }; - }; - }; - - etm@7640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07640000 0 0x1000>; - - cpu = <&CPU6>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = <&apss_funnel_in6>; - }; - }; - }; - }; - - etm@7740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07740000 0 0x1000>; - - cpu = <&CPU7>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = <&apss_funnel_in7>; - }; - }; - }; - }; - - funnel@7800000 { /* APSS Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07800000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_funnel_out: endpoint { - remote-endpoint = <&apss_merge_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - apss_funnel_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - apss_funnel_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - apss_funnel_in4: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - apss_funnel_in5: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - apss_funnel_in6: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - apss_funnel_in7: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - funnel@7810000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07810000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = <&funnel2_in2>; - }; - }; - }; - - in-ports { - port { - apss_merge_funnel_in: endpoint { - remote-endpoint = <&apss_funnel_out>; - }; - }; - }; - }; - - remoteproc_cdsp: remoteproc@8300000 { - compatible = "qcom,sm8150-cdsp-pas"; - reg = <0x0 0x08300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "cdsp"; - qcom,remote-pid = <5>; - mboxes = <&apss_shared 4>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x1401 0x2040>, - <&apps_smmu 0x1421 0x0>, - <&apps_smmu 0x2001 0x420>, - <&apps_smmu 0x2041 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2 0x3440>, - <&apps_smmu 0x22 0x3400>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x3 0x3440>, - <&apps_smmu 0x1423 0x0>, - <&apps_smmu 0x2023 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x4 0x3440>, - <&apps_smmu 0x24 0x3400>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x5 0x3440>, - <&apps_smmu 0x25 0x3400>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x6 0x3460>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x7 0x3460>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x8 0x3460>; - }; - - /* note: secure cb9 in downstream */ - }; - }; - }; - - usb_1_hsphy: phy@88e2000 { - compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e2000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_2_hsphy: phy@88e3000 { - compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - }; - - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sm8150-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - usb_2_qmpphy: phy@88eb000 { - compatible = "qcom,sm8150-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: phy@88eb200 { - reg = <0 0x088eb200 0 0x200>, - <0 0x088eb400 0 0x200>, - <0 0x088eb800 0 0x800>, - <0 0x088eb600 0 0x200>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - dc_noc: interconnect@9160000 { - compatible = "qcom,sm8150-dc-noc"; - reg = <0 0x09160000 0 0x3200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9680000 { - compatible = "qcom,sm8150-gem-noc"; - reg = <0 0x09680000 0 0x3e200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x140 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x160 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - camnoc_virt: interconnect@ac00000 { - compatible = "qcom,sm8150-camnoc-virt"; - reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8150-aoss-qmp"; - reg = <0x0 0x0c300000 0x0 0x400>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - }; - - sram@c3f0000 { - compatible = "qcom,rpmh-stats"; - reg = <0 0x0c3f0000 0 0x400>; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c440000 0x0 0x0001100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x0100000>, - <0x0 0x0e700000 0x0 0x00a0000>, - <0x0 0x0c40a000 0x0 0x0026000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - remoteproc_adsp: remoteproc@17300000 { - compatible = "qcom,sm8150-adsp-pas"; - reg = <0x0 0x17300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 7>; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apss_shared 8>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1b23 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1b24 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1b25 0x0>; - }; - }; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; - - apss_shared: mailbox@17c00000 { - compatible = "qcom,sm8150-apss-shared"; - reg = <0x0 0x17c00000 0x0 0x1000>; - #mbox-cells = <1>; - }; - - watchdog@17c10000 { - compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; - clocks = <&sleep_clk>; - interrupts = ; - }; - - timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17c21000{ - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17c23000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17c25000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17c26000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17c29000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x17c2b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x17c2d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - rpmhcc: clock-controller { - compatible = "qcom,sm8150-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8150-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_svs_l2: opp6 { - opp-level = <224>; - }; - - rpmhpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp8 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp10 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp11 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - - osm_l3: interconnect@18321000 { - compatible = "qcom,sm8150-osm-l3"; - reg = <0 0x18321000 0 0x1400>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; - reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, - <0 0x18327800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1", - "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0 0x18800000 0 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_mem>; - clock-names = "cxo_ref_clk_pin", "qdss"; - clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&apps_smmu 0x0640 0x1>; - status = "disabled"; - }; - - cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0 0x01dc4000 0 0x24000>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - iommus = <&apps_smmu 0x504 0x0011>, - <&apps_smmu 0x506 0x0011>, - <&apps_smmu 0x514 0x0011>, - <&apps_smmu 0x516 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - - crypto: crypto@1dfa000 { - compatible = "qcom,sm8150-qce"; - reg = <0 0x01dfa000 0 0x6000>; - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x504 0x0011>, - <&apps_smmu 0x506 0x0011>, - <&apps_smmu 0x514 0x0011>, - <&apps_smmu 0x516 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 14>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 15>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - compute-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - compute_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - npu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 8>; - - trips { - npu_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-vec-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 9>; - - trips { - modem_vec_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-scl-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 10>; - - trips { - modem_scl_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 11>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/rr-cache/711d086cd570801c922946173f057886116282b3/preimage b/rr-cache/711d086cd570801c922946173f057886116282b3/preimage deleted file mode 100644 index 1e1ecde..0000000 --- a/rr-cache/711d086cd570801c922946173f057886116282b3/preimage +++ /dev/null @@ -1,151 +0,0 @@ -<<<<<<< -/* SPDX-License-Identifier: GPL-2.0 */ -======= -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ ->>>>>>> - -#ifndef __QCOM_FASTRPC_H__ -#define __QCOM_FASTRPC_H__ - -#include - -<<<<<<< -#define FASTRPC_IOCTL_ALLOC_DMA_BUFF _IOWR('R', 1, struct fastrpc_alloc_dma_buf) -#define FASTRPC_IOCTL_FREE_DMA_BUFF _IOWR('R', 2, __u32) -#define FASTRPC_IOCTL_INVOKE _IOWR('R', 3, struct fastrpc_invoke) -#define FASTRPC_IOCTL_INIT_ATTACH _IO('R', 4) -#define FASTRPC_IOCTL_INIT_CREATE _IOWR('R', 5, struct fastrpc_init_create) -#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct fastrpc_req_mmap) -#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct fastrpc_req_munmap) -#define FASTRPC_IOCTL_INIT_ATTACH_SNS _IO('R', 8) -#define FASTRPC_IOCTL_MEM_MAP _IOWR('R', 10, struct fastrpc_mem_map) -#define FASTRPC_IOCTL_MEM_UNMAP _IOWR('R', 11, struct fastrpc_mem_unmap) -#define FASTRPC_IOCTL_GET_DSP_INFO _IOWR('R', 13, struct fastrpc_ioctl_capability) - -/** - * enum fastrpc_map_flags - control flags for mapping memory on DSP user process - * @FASTRPC_MAP_STATIC: Map memory pages with RW- permission and CACHE WRITEBACK. - * The driver is responsible for cache maintenance when passed - * the buffer to FastRPC calls. Same virtual address will be - * assigned for subsequent FastRPC calls. - * @FASTRPC_MAP_RESERVED: Reserved - * @FASTRPC_MAP_FD: Map memory pages with RW- permission and CACHE WRITEBACK. - * Mapping tagged with a file descriptor. User is responsible for - * CPU and DSP cache maintenance for the buffer. Get virtual address - * of buffer on DSP using HAP_mmap_get() and HAP_mmap_put() APIs. - * @FASTRPC_MAP_FD_DELAYED: Mapping delayed until user call HAP_mmap() and HAP_munmap() - * functions on DSP. It is useful to map a buffer with cache modes - * other than default modes. User is responsible for CPU and DSP - * cache maintenance for the buffer. - * @FASTRPC_MAP_FD_NOMAP: This flag is used to skip CPU mapping, - * otherwise behaves similar to FASTRPC_MAP_FD_DELAYED flag. - * @FASTRPC_MAP_MAX: max count for flags - * - */ -enum fastrpc_map_flags { - FASTRPC_MAP_STATIC = 0, - FASTRPC_MAP_RESERVED, - FASTRPC_MAP_FD = 2, - FASTRPC_MAP_FD_DELAYED, - FASTRPC_MAP_FD_NOMAP = 16, - FASTRPC_MAP_MAX, -}; - -enum fastrpc_proc_attr { - /* Macro for Debug attr */ - FASTRPC_MODE_DEBUG = (1 << 0), - /* Macro for Ptrace */ - FASTRPC_MODE_PTRACE = (1 << 1), - /* Macro for CRC Check */ - FASTRPC_MODE_CRC = (1 << 2), - /* Macro for Unsigned PD */ - FASTRPC_MODE_UNSIGNED_MODULE = (1 << 3), - /* Macro for Adaptive QoS */ - FASTRPC_MODE_ADAPTIVE_QOS = (1 << 4), - /* Macro for System Process */ - FASTRPC_MODE_SYSTEM_PROCESS = (1 << 5), - /* Macro for Prvileged Process */ - FASTRPC_MODE_PRIVILEGED = (1 << 6), -}; - -/* Fastrpc attribute for memory protection of buffers */ -#define FASTRPC_ATTR_SECUREMAP (1) -======= -#define FASTRPC_IOCTL_INVOKE _IOWR('R', 3, struct fastrpc_invoke) ->>>>>>> - -struct fastrpc_invoke_args { - __u64 ptr; - __u64 length; - __s32 fd; -<<<<<<< - __u32 attr; -======= - __u32 reserved; ->>>>>>> -}; - -struct fastrpc_invoke { - __u32 handle; - __u32 sc; - __u64 args; -}; - -<<<<<<< -======= -struct fastrpc_init_create { - __u32 filelen; /* elf file length */ - __s32 filefd; /* fd for the file */ - __u32 attrs; - __u32 siglen; - __u64 file; /* pointer to elf file */ -}; - -struct fastrpc_alloc_dma_buf { - __s32 fd; /* fd */ - __u32 flags; /* flags to map with */ - __u64 size; /* size */ -}; - -struct fastrpc_req_mmap { - __s32 fd; - __u32 flags; /* flags for dsp to map with */ - __u64 vaddrin; /* optional virtual address */ - __u64 size; /* size */ - __u64 vaddrout; /* dsp virtual address */ -}; - -struct fastrpc_mem_map { - __s32 version; - __s32 fd; /* fd */ - __s32 offset; /* buffer offset */ - __u32 flags; /* flags defined in enum fastrpc_map_flags */ - __u64 vaddrin; /* buffer virtual address */ - __u64 length; /* buffer length */ - __u64 vaddrout; /* [out] remote virtual address */ - __s32 attrs; /* buffer attributes used for SMMU mapping */ - __s32 reserved[4]; -}; - -struct fastrpc_req_munmap { - __u64 vaddrout; /* address to unmap */ - __u64 size; /* size */ -}; - -struct fastrpc_mem_unmap { - __s32 vesion; - __s32 fd; /* fd */ - __u64 vaddr; /* remote process (dsp) virtual address */ - __u64 length; /* buffer size */ - __s32 reserved[5]; -}; - -struct fastrpc_ioctl_capability { - __u32 domain; - __u32 attribute_id; - __u32 capability; /* dsp capability */ - __u32 reserved[4]; -}; - ->>>>>>> -#endif /* __QCOM_FASTRPC_H__ */ diff --git a/rr-cache/747170db197161b1dc7d6279aeabd586cabb01d9/preimage b/rr-cache/747170db197161b1dc7d6279aeabd586cabb01d9/preimage deleted file mode 100644 index aa154f9..0000000 --- a/rr-cache/747170db197161b1dc7d6279aeabd586cabb01d9/preimage +++ /dev/null @@ -1,1243 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SE_I2C_TX_TRANS_LEN 0x26c -#define SE_I2C_RX_TRANS_LEN 0x270 -#define SE_I2C_SCL_COUNTERS 0x278 - -#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\ - M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN) -#define SE_I2C_ABORT BIT(1) - -/* M_CMD OP codes for I2C */ -#define I2C_WRITE 0x1 -#define I2C_READ 0x2 -#define I2C_WRITE_READ 0x3 -#define I2C_ADDR_ONLY 0x4 -#define I2C_BUS_CLEAR 0x6 -#define I2C_STOP_ON_BUS 0x7 -/* M_CMD params for I2C */ -#define PRE_CMD_DELAY BIT(0) -#define TIMESTAMP_BEFORE BIT(1) -#define STOP_STRETCH BIT(2) -#define TIMESTAMP_AFTER BIT(3) -#define POST_COMMAND_DELAY BIT(4) -#define IGNORE_ADD_NACK BIT(6) -#define READ_FINISHED_WITH_ACK BIT(7) -#define BYPASS_ADDR_PHASE BIT(8) -#define SLV_ADDR_MSK GENMASK(15, 9) -#define SLV_ADDR_SHFT 9 -/* I2C SCL COUNTER fields */ -#define HIGH_COUNTER_MSK GENMASK(29, 20) -#define HIGH_COUNTER_SHFT 20 -#define LOW_COUNTER_MSK GENMASK(19, 10) -#define LOW_COUNTER_SHFT 10 -#define CYCLE_COUNTER_MSK GENMASK(9, 0) - -<<<<<<< -#define I2C_PACK_EN (BIT(0) | BIT(1)) -======= -#define I2C_PACK_TX BIT(0) -#define I2C_PACK_RX BIT(1) ->>>>>>> - -enum geni_i2c_err_code { - GP_IRQ0, - NACK, - GP_IRQ2, - BUS_PROTO, - ARB_LOST, - GP_IRQ5, - GENI_OVERRUN, - GENI_ILLEGAL_CMD, - GENI_ABORT_DONE, - GENI_TIMEOUT, -}; - -#define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \ - << 5) - -#define I2C_AUTO_SUSPEND_DELAY 250 -#define KHZ(freq) (1000 * freq) -#define PACKING_BYTES_PW 4 - -#define ABORT_TIMEOUT HZ -#define XFER_TIMEOUT HZ -#define RST_TIMEOUT HZ - -enum i2c_se_mode { - I2C_FIFO_SE_DMA, - I2C_GPI_DMA, -}; - -struct geni_i2c_dev { - struct geni_se se; - u32 tx_wm; - int irq; - int err; - struct i2c_adapter adap; - struct completion done; - struct i2c_msg *cur; - int cur_wr; - int cur_rd; - spinlock_t lock; - u32 clk_freq_out; - const struct geni_i2c_clk_fld *clk_fld; - int suspended; - void *dma_buf; - size_t xfer_len; - dma_addr_t dma_addr; - struct dma_chan *tx_c; - struct dma_chan *rx_c; -<<<<<<< - bool cfg_sent; - enum i2c_se_mode se_mode; -======= - bool gpi_mode; ->>>>>>> -}; - -struct geni_i2c_err_log { - int err; - const char *msg; -}; - -static const struct geni_i2c_err_log gi2c_log[] = { - [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"}, - [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"}, - [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"}, - [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"}, - [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"}, - [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"}, - [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"}, - [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"}, - [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"}, - [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"}, -}; - -struct geni_i2c_clk_fld { - u32 clk_freq_out; - u8 clk_div; - u8 t_high_cnt; - u8 t_low_cnt; - u8 t_cycle_cnt; -}; - -/* - * Hardware uses the underlying formula to calculate time periods of - * SCL clock cycle. Firmware uses some additional cycles excluded from the - * below formula and it is confirmed that the time periods are within - * specification limits. - * - * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock - * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock - * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock - * clk_freq_out = t / t_cycle - * source_clock = 19.2 MHz - */ -static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = { - {KHZ(100), 7, 10, 11, 26}, - {KHZ(400), 2, 5, 12, 24}, - {KHZ(1000), 1, 3, 9, 18}, -}; - -static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) -{ - int i; - const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map; - - for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) { - if (itr->clk_freq_out == gi2c->clk_freq_out) { - gi2c->clk_fld = itr; - return 0; - } - } - return -EINVAL; -} - -static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) -{ - const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; - u32 val; - - writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); - - val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; - writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); - - val = itr->t_high_cnt << HIGH_COUNTER_SHFT; - val |= itr->t_low_cnt << LOW_COUNTER_SHFT; - val |= itr->t_cycle_cnt; - writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); -} - -static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) -{ - u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); - u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); - u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); - u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); - u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); - u32 rx_st, tx_st; - - if (dma) { - rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); - tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); - } else { - rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS); - tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS); - } - dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n", - dma, tx_st, rx_st, m_stat); - dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n", - m_cmd, geni_s, geni_ios); -} - -static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err) -{ - if (!gi2c->err) - gi2c->err = gi2c_log[err].err; - if (gi2c->cur) - dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n", - gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags); - - if (err != NACK && err != GENI_ABORT_DONE) { - dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg); - geni_i2c_err_misc(gi2c); - } -} - -static irqreturn_t geni_i2c_irq(int irq, void *dev) -{ - struct geni_i2c_dev *gi2c = dev; - void __iomem *base = gi2c->se.base; - int j, p; - u32 m_stat; - u32 rx_st; - u32 dm_tx_st; - u32 dm_rx_st; - u32 dma; - u32 val; - struct i2c_msg *cur; - - spin_lock(&gi2c->lock); - m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS); - rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS); - dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT); - dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT); - dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN); - cur = gi2c->cur; - - if (!cur || - m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) || - dm_rx_st & (DM_I2C_CB_ERR)) { - if (m_stat & M_GP_IRQ_1_EN) - geni_i2c_err(gi2c, NACK); - if (m_stat & M_GP_IRQ_3_EN) - geni_i2c_err(gi2c, BUS_PROTO); - if (m_stat & M_GP_IRQ_4_EN) - geni_i2c_err(gi2c, ARB_LOST); - if (m_stat & M_CMD_OVERRUN_EN) - geni_i2c_err(gi2c, GENI_OVERRUN); - if (m_stat & M_ILLEGAL_CMD_EN) - geni_i2c_err(gi2c, GENI_ILLEGAL_CMD); - if (m_stat & M_CMD_ABORT_EN) - geni_i2c_err(gi2c, GENI_ABORT_DONE); - if (m_stat & M_GP_IRQ_0_EN) - geni_i2c_err(gi2c, GP_IRQ0); - - /* Disable the TX Watermark interrupt to stop TX */ - if (!dma) - writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); - } else if (dma) { - dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n", - dm_tx_st, dm_rx_st); - } else if (cur->flags & I2C_M_RD && - m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) { - u32 rxcnt = rx_st & RX_FIFO_WC_MSK; - - for (j = 0; j < rxcnt; j++) { - p = 0; - val = readl_relaxed(base + SE_GENI_RX_FIFOn); - while (gi2c->cur_rd < cur->len && p < sizeof(val)) { - cur->buf[gi2c->cur_rd++] = val & 0xff; - val >>= 8; - p++; - } - if (gi2c->cur_rd == cur->len) - break; - } - } else if (!(cur->flags & I2C_M_RD) && - m_stat & M_TX_FIFO_WATERMARK_EN) { - for (j = 0; j < gi2c->tx_wm; j++) { - u32 temp; - - val = 0; - p = 0; - while (gi2c->cur_wr < cur->len && p < sizeof(val)) { - temp = cur->buf[gi2c->cur_wr++]; - val |= temp << (p * 8); - p++; - } - writel_relaxed(val, base + SE_GENI_TX_FIFOn); - /* TX Complete, Disable the TX Watermark interrupt */ - if (gi2c->cur_wr == cur->len) { - writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); - break; - } - } - } - - if (m_stat) - writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR); - - if (dma && dm_tx_st) - writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR); - if (dma && dm_rx_st) - writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR); - - /* if this is err with done-bit not set, handle that through timeout. */ - if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN || - dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE || - dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE) - complete(&gi2c->done); - - spin_unlock(&gi2c->lock); - - return IRQ_HANDLED; -} - -static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c) -{ - u32 val; - unsigned long time_left = ABORT_TIMEOUT; - unsigned long flags; - - spin_lock_irqsave(&gi2c->lock, flags); - geni_i2c_err(gi2c, GENI_TIMEOUT); - gi2c->cur = NULL; - geni_se_abort_m_cmd(&gi2c->se); - spin_unlock_irqrestore(&gi2c->lock, flags); - do { - time_left = wait_for_completion_timeout(&gi2c->done, time_left); - val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); - } while (!(val & M_CMD_ABORT_EN) && time_left); - - if (!(val & M_CMD_ABORT_EN)) - dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n"); -} - -static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c) -{ - u32 val; - unsigned long time_left = RST_TIMEOUT; - - writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST); - do { - time_left = wait_for_completion_timeout(&gi2c->done, time_left); - val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); - } while (!(val & RX_RESET_DONE) && time_left); - - if (!(val & RX_RESET_DONE)) - dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n"); -} - -static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c) -{ - u32 val; - unsigned long time_left = RST_TIMEOUT; - - writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST); - do { - time_left = wait_for_completion_timeout(&gi2c->done, time_left); - val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); - } while (!(val & TX_RESET_DONE) && time_left); - - if (!(val & TX_RESET_DONE)) - dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n"); -} - -static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c, - struct i2c_msg *cur) -{ - gi2c->cur_rd = 0; - if (gi2c->dma_buf) { - if (gi2c->err) - geni_i2c_rx_fsm_rst(gi2c); - geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); - i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); - } -} - -static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c, - struct i2c_msg *cur) -{ - gi2c->cur_wr = 0; - if (gi2c->dma_buf) { - if (gi2c->err) - geni_i2c_tx_fsm_rst(gi2c); - geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); - i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); - } -} - -static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, - u32 m_param) -{ - dma_addr_t rx_dma = 0; - unsigned long time_left; - void *dma_buf; - struct geni_se *se = &gi2c->se; - size_t len = msg->len; - struct i2c_msg *cur; - - dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); - if (dma_buf) - geni_se_select_mode(se, GENI_SE_DMA); - else - geni_se_select_mode(se, GENI_SE_FIFO); - - writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); - geni_se_setup_m_cmd(se, I2C_READ, m_param); - - if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { - geni_se_select_mode(se, GENI_SE_FIFO); - i2c_put_dma_safe_msg_buf(dma_buf, msg, false); - dma_buf = NULL; - } else { - gi2c->xfer_len = len; - gi2c->dma_addr = rx_dma; - gi2c->dma_buf = dma_buf; - } - - cur = gi2c->cur; - time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); - if (!time_left) - geni_i2c_abort_xfer(gi2c); - - geni_i2c_rx_msg_cleanup(gi2c, cur); - - return gi2c->err; -} - -static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, - u32 m_param) -{ - dma_addr_t tx_dma = 0; - unsigned long time_left; - void *dma_buf; - struct geni_se *se = &gi2c->se; - size_t len = msg->len; - struct i2c_msg *cur; - - dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); - if (dma_buf) - geni_se_select_mode(se, GENI_SE_DMA); - else - geni_se_select_mode(se, GENI_SE_FIFO); - - writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); - geni_se_setup_m_cmd(se, I2C_WRITE, m_param); - - if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { - geni_se_select_mode(se, GENI_SE_FIFO); - i2c_put_dma_safe_msg_buf(dma_buf, msg, false); - dma_buf = NULL; - } else { - gi2c->xfer_len = len; - gi2c->dma_addr = tx_dma; - gi2c->dma_buf = dma_buf; - } - - if (!dma_buf) /* Get FIFO IRQ */ - writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG); - - cur = gi2c->cur; - time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); - if (!time_left) - geni_i2c_abort_xfer(gi2c); - - geni_i2c_tx_msg_cleanup(gi2c, cur); - - return gi2c->err; -} - -<<<<<<< -static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result) -======= -static void i2c_gsi_cb_result(void *cb, const struct dmaengine_result *result) -{ - struct geni_i2c_dev *gi2c = cb; - - if (result->result != DMA_TRANS_NOERROR) { - dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result); - return; - } - - if (result->residue) - dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue); - - complete(&gi2c->done); -} - -static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, - void *tx_buf, dma_addr_t tx_addr, - void *rx_buf, dma_addr_t rx_addr) -{ - if (tx_buf) { - dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE); - i2c_put_dma_safe_msg_buf(tx_buf, msg, false); - } - - if (rx_buf) { - dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE); - i2c_put_dma_safe_msg_buf(rx_buf, msg, false); - } -} - -static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, - struct dma_slave_config *config, dma_addr_t *dma_addr_p, - void **buf, unsigned int op, struct dma_chan *dma_chan) -{ - struct gpi_i2c_config *peripheral; - unsigned int flags; - void *dma_buf = &buf; - dma_addr_t addr; - enum dma_data_direction map_dirn; - enum dma_transfer_direction dma_dirn; - struct dma_async_tx_descriptor *desc; - int ret; - - peripheral = config->peripheral_config; - - dma_buf = i2c_get_dma_safe_msg_buf(msg, 1); - if (!dma_buf) - return -ENOMEM; - - if (op == I2C_WRITE) - map_dirn = DMA_TO_DEVICE; - else - map_dirn = DMA_FROM_DEVICE; - - addr = dma_map_single(gi2c->se.dev->parent, dma_buf, msg->len, map_dirn); - if (dma_mapping_error(gi2c->se.dev->parent, addr)) { - i2c_put_dma_safe_msg_buf(dma_buf, msg, false); - return -ENOMEM; - } - - peripheral->rx_len = msg->len; - peripheral->op = op; - - ret = dmaengine_slave_config(dma_chan, config); - if (ret) { - dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op); - goto err_config; - } - - peripheral->set_config = false; - peripheral->multi_msg = true; - flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; - - if (op == I2C_WRITE) - dma_dirn = DMA_MEM_TO_DEV; - else - dma_dirn = DMA_DEV_TO_MEM; - - desc = dmaengine_prep_slave_single(dma_chan, addr, msg->len, dma_dirn, flags); - if (!desc) { - dev_err(gi2c->se.dev, "prep_slave_sg failed\n"); - ret = -EIO; - goto err_config; - } - - desc->callback_result = i2c_gsi_cb_result; - desc->callback_param = gi2c; - - dmaengine_submit(desc); - *dma_addr_p = addr; - - return 0; - -err_config: - dma_unmap_single(gi2c->se.dev->parent, addr, msg->len, map_dirn); - i2c_put_dma_safe_msg_buf(dma_buf, msg, false); - return ret; -} - -static int geni_i2c_gsi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num) -{ - struct dma_slave_config config = {}; - struct gpi_i2c_config peripheral = {}; - int i, ret = 0, timeout, stretch; - dma_addr_t tx_addr, rx_addr; - void *tx_buf = NULL, *rx_buf = NULL; - - config.peripheral_config = &peripheral; - config.peripheral_size = sizeof(peripheral); - - if (!gi2c->cfg_sent) { - const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; - - gi2c->cfg_sent = true; - peripheral.pack_enable = I2C_PACK_EN; - peripheral.cycle_count = itr->t_cycle_cnt; - peripheral.high_count = itr->t_high_cnt; - peripheral.low_count = itr->t_low_cnt; - peripheral.clk_div = itr->clk_div; - peripheral.set_config = true; - } - peripheral.multi_msg = false; - - for (i = 0; i < num; i++) { - gi2c->cur = &msgs[i]; - dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len); - - stretch = (i < (num - 1)); - peripheral.addr = msgs[i].addr; - peripheral.stretch = stretch; - - if (msgs[i].flags & I2C_M_RD) { - ret = geni_i2c_gpi(gi2c, &msgs[i], &config, &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c); - if (ret) - goto err; - } - - ret = geni_i2c_gpi(gi2c, &msgs[i], &config, &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); - if (ret) - goto err; - - if (msgs[i].flags & I2C_M_RD) - dma_async_issue_pending(gi2c->rx_c); - dma_async_issue_pending(gi2c->tx_c); - - timeout = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); - if (!timeout) { - dev_err(gi2c->se.dev, "I2C timeout gsi flags:%d addr:0x%x\n", - gi2c->cur->flags, gi2c->cur->addr); - gi2c->err = -ETIMEDOUT; - goto err; - } - - geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); - } - - return 0; - -err: - dmaengine_terminate_sync(gi2c->rx_c); - dmaengine_terminate_sync(gi2c->tx_c); - geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); - return ret; -} - -static int geni_i2c_xfer(struct i2c_adapter *adap, - struct i2c_msg msgs[], - int num) ->>>>>>> -{ - struct geni_i2c_dev *gi2c = cb; - - if (result->result != DMA_TRANS_NOERROR) { - dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result); - return; - } - -<<<<<<< - if (result->residue) - dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue); - - complete(&gi2c->done); -} - -static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, - void *tx_buf, dma_addr_t tx_addr, - void *rx_buf, dma_addr_t rx_addr) -{ - if (tx_buf) { - dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE); - i2c_put_dma_safe_msg_buf(tx_buf, msg, false); - } - - if (rx_buf) { - dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE); - i2c_put_dma_safe_msg_buf(rx_buf, msg, false); - } -} - -static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, - struct dma_slave_config *config, dma_addr_t *dma_addr_p, - void **buf, unsigned int op, struct dma_chan *dma_chan) -{ - struct gpi_i2c_config *peripheral; - unsigned int flags; - void *dma_buf; - dma_addr_t addr; - enum dma_data_direction map_dirn; - enum dma_transfer_direction dma_dirn; - struct dma_async_tx_descriptor *desc; - int ret; - - peripheral = config->peripheral_config; - - dma_buf = i2c_get_dma_safe_msg_buf(msg, 1); - if (!dma_buf) - return -ENOMEM; - - if (op == I2C_WRITE) - map_dirn = DMA_TO_DEVICE; - else - map_dirn = DMA_FROM_DEVICE; - - addr = dma_map_single(gi2c->se.dev->parent, dma_buf, msg->len, map_dirn); - if (dma_mapping_error(gi2c->se.dev->parent, addr)) { - i2c_put_dma_safe_msg_buf(dma_buf, msg, false); - return -ENOMEM; - } - - /* set the length as message for rx txn */ - peripheral->rx_len = msg->len; - peripheral->op = op; - - ret = dmaengine_slave_config(dma_chan, config); - if (ret) { - dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op); - goto err_config; - } - - peripheral->set_config = 0; - peripheral->multi_msg = true; - flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; - - if (op == I2C_WRITE) - dma_dirn = DMA_MEM_TO_DEV; - else - dma_dirn = DMA_DEV_TO_MEM; - - desc = dmaengine_prep_slave_single(dma_chan, addr, msg->len, dma_dirn, flags); - if (!desc) { - dev_err(gi2c->se.dev, "prep_slave_sg failed\n"); - ret = -EIO; - goto err_config; - } - - desc->callback_result = i2c_gpi_cb_result; - desc->callback_param = gi2c; - - dmaengine_submit(desc); - *dma_addr_p = addr; - - return 0; - -err_config: - dma_unmap_single(gi2c->se.dev->parent, addr, msg->len, map_dirn); - i2c_put_dma_safe_msg_buf(dma_buf, msg, false); - return ret; -} - -static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num) -{ - struct dma_slave_config config = {}; - struct gpi_i2c_config peripheral = {}; - int i, ret = 0, timeout; - dma_addr_t tx_addr, rx_addr; - void *tx_buf = NULL, *rx_buf = NULL; - const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; - - config.peripheral_config = &peripheral; - config.peripheral_size = sizeof(peripheral); - - peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX; - peripheral.cycle_count = itr->t_cycle_cnt; - peripheral.high_count = itr->t_high_cnt; - peripheral.low_count = itr->t_low_cnt; - peripheral.clk_div = itr->clk_div; - peripheral.set_config = 1; - peripheral.multi_msg = false; - - for (i = 0; i < num; i++) { - gi2c->cur = &msgs[i]; - dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len); - - peripheral.stretch = 0; - if (i < num - 1) - peripheral.stretch = 1; - - peripheral.addr = msgs[i].addr; - - if (msgs[i].flags & I2C_M_RD) { - ret = geni_i2c_gpi(gi2c, &msgs[i], &config, &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c); - if (ret) - goto err; - } - - ret = geni_i2c_gpi(gi2c, &msgs[i], &config, &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); - if (ret) - goto err; - - if (msgs[i].flags & I2C_M_RD) - dma_async_issue_pending(gi2c->rx_c); - dma_async_issue_pending(gi2c->tx_c); - - timeout = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); - if (!timeout) { - dev_err(gi2c->se.dev, "I2C timeout gpi flags:%d addr:0x%x\n", - gi2c->cur->flags, gi2c->cur->addr); - ret = gi2c->err = -ETIMEDOUT; - goto err; - } - - geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); - } - - return 0; - -err: - dmaengine_terminate_sync(gi2c->rx_c); - dmaengine_terminate_sync(gi2c->tx_c); - geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); - return ret; -} - -static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c, - struct i2c_msg msgs[], int num) -{ - int i, ret = 0; - -======= - qcom_geni_i2c_conf(gi2c); - - if (gi2c->se_mode == I2C_GPI_DMA) { - ret = geni_i2c_gsi_xfer(gi2c, msgs, num); - goto geni_i2c_txn_ret; - } - ->>>>>>> - for (i = 0; i < num; i++) { - u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; - - m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); - - gi2c->cur = &msgs[i]; - if (msgs[i].flags & I2C_M_RD) - ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param); - else - ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param); - - if (ret) - break; - } -<<<<<<< - - return ret; -} - -static int geni_i2c_xfer(struct i2c_adapter *adap, - struct i2c_msg msgs[], - int num) -{ - struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap); - int ret; - - gi2c->err = 0; - reinit_completion(&gi2c->done); - ret = pm_runtime_get_sync(gi2c->se.dev); - if (ret < 0) { - dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret); - pm_runtime_put_noidle(gi2c->se.dev); - /* Set device in suspended since resume failed */ - pm_runtime_set_suspended(gi2c->se.dev); - return ret; - } - - qcom_geni_i2c_conf(gi2c); - - if (gi2c->gpi_mode) - ret = geni_i2c_gpi_xfer(gi2c, msgs, num); - else - ret = geni_i2c_fifo_xfer(gi2c, msgs, num); -======= -geni_i2c_txn_ret: - if (ret == 0) - ret = num; ->>>>>>> - - pm_runtime_mark_last_busy(gi2c->se.dev); - pm_runtime_put_autosuspend(gi2c->se.dev); - gi2c->cur = NULL; - gi2c->err = 0; - return ret ?: num; -} - -static u32 geni_i2c_func(struct i2c_adapter *adap) -{ - return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); -} - -static const struct i2c_algorithm geni_i2c_algo = { - .master_xfer = geni_i2c_xfer, - .functionality = geni_i2c_func, -}; - -#ifdef CONFIG_ACPI -static const struct acpi_device_id geni_i2c_acpi_match[] = { - { "QCOM0220"}, - { }, -}; -MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match); -#endif - -static void release_gpi_dma(struct geni_i2c_dev *gi2c) -{ -<<<<<<< - if (gi2c->rx_c) - dma_release_channel(gi2c->rx_c); - - if (gi2c->tx_c) - dma_release_channel(gi2c->tx_c); -======= - if (gi2c->rx_c) { - dma_release_channel(gi2c->rx_c); - gi2c->rx_c = NULL; - } - if (gi2c->tx_c) { - dma_release_channel(gi2c->tx_c); - gi2c->tx_c = NULL; - } ->>>>>>> -} - -static int setup_gpi_dma(struct geni_i2c_dev *gi2c) -{ - int ret; - - geni_se_select_mode(&gi2c->se, GENI_GPI_DMA); - gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx"); -<<<<<<< - if (IS_ERR(gi2c->tx_c)) { - ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c), - "Failed to get tx DMA ch\n"); - if (ret < 0) - goto err_tx; - } - - gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx"); - if (IS_ERR(gi2c->rx_c)) { - ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c), - "Failed to get rx DMA ch\n"); - if (ret < 0) - goto err_rx; - } -======= - ret = dev_err_probe(gi2c->se.dev, IS_ERR(gi2c->tx_c), "Failed to get tx DMA ch\n"); - if (ret < 0) - goto err_tx; - - gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx"); - ret = dev_err_probe(gi2c->se.dev, IS_ERR(gi2c->rx_c), "Failed to get rx DMA ch\n"); - if (ret < 0) - goto err_rx; ->>>>>>> - - dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n"); - return 0; - -err_rx: - dma_release_channel(gi2c->tx_c); - gi2c->tx_c = NULL; -err_tx: - gi2c->rx_c = NULL; - return ret; -} - -static int geni_i2c_probe(struct platform_device *pdev) -{ - struct geni_i2c_dev *gi2c; - struct resource *res; - u32 proto, tx_depth, fifo_disable; - int ret; - struct device *dev = &pdev->dev; - - gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL); - if (!gi2c) - return -ENOMEM; - - gi2c->se.dev = dev; - gi2c->se.wrapper = dev_get_drvdata(dev->parent); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - gi2c->se.base = devm_ioremap_resource(dev, res); - if (IS_ERR(gi2c->se.base)) - return PTR_ERR(gi2c->se.base); - - gi2c->se.clk = devm_clk_get(dev, "se"); - if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev)) - return PTR_ERR(gi2c->se.clk); - - ret = device_property_read_u32(dev, "clock-frequency", - &gi2c->clk_freq_out); - if (ret) { - dev_info(dev, "Bus frequency not specified, default to 100kHz.\n"); - gi2c->clk_freq_out = KHZ(100); - } - - if (has_acpi_companion(dev)) - ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev)); - - gi2c->irq = platform_get_irq(pdev, 0); - if (gi2c->irq < 0) - return gi2c->irq; - - ret = geni_i2c_clk_map_idx(gi2c); - if (ret) { - dev_err(dev, "Invalid clk frequency %d Hz: %d\n", - gi2c->clk_freq_out, ret); - return ret; - } - - gi2c->adap.algo = &geni_i2c_algo; - init_completion(&gi2c->done); - spin_lock_init(&gi2c->lock); - platform_set_drvdata(pdev, gi2c); - ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, 0, - dev_name(dev), gi2c); - if (ret) { - dev_err(dev, "Request_irq failed:%d: err:%d\n", - gi2c->irq, ret); - return ret; - } - /* Disable the interrupt so that the system can enter low-power mode */ - disable_irq(gi2c->irq); - i2c_set_adapdata(&gi2c->adap, gi2c); - gi2c->adap.dev.parent = dev; - gi2c->adap.dev.of_node = dev->of_node; - strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); - - ret = geni_icc_get(&gi2c->se, "qup-memory"); - if (ret) - return ret; - /* - * Set the bus quota for core and cpu to a reasonable value for - * register access. - * Set quota for DDR based on bus speed. - */ - gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; - gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; - gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out); - - ret = geni_icc_set_bw(&gi2c->se); - if (ret) - return ret; - - ret = geni_se_resources_on(&gi2c->se); - if (ret) { - dev_err(dev, "Error turning on resources %d\n", ret); - return ret; - } - proto = geni_se_read_proto(&gi2c->se); - if (proto != GENI_SE_I2C) { - dev_err(dev, "Invalid proto %d\n", proto); - geni_se_resources_off(&gi2c->se); - return -ENXIO; - } - - fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; -<<<<<<< - if (fifo_disable) { - /* FIFO is disabled, so we can only use GPI DMA */ - gi2c->gpi_mode = true; - ret = setup_gpi_dma(gi2c); - if (ret) { - dev_err(dev, "Failed to setup GPI DMA mode:%d ret\n", ret); - return ret; - } - - dev_dbg(dev, "Using GPI DMA mode for I2C\n"); - } else { - gi2c->gpi_mode = false; -======= - - switch (fifo_disable) { - case 1: - ret = setup_gpi_dma(gi2c); - if (!ret) { /* success case */ - gi2c->se_mode = I2C_GPI_DMA; - geni_se_select_mode(&gi2c->se, GENI_GPI_DMA); - dev_dbg(dev, "Using GPI DMA mode for I2C\n"); - break; - } - /* - * in case of failure to get dma channel, we can till do the - * FIFO mode, so fallthrough - */ - dev_warn(dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); - fallthrough; - - case 0: - gi2c->se_mode = I2C_FIFO_SE_DMA; ->>>>>>> - tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); - gi2c->tx_wm = tx_depth - 1; - geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); - geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, - PACKING_BYTES_PW, true, true, true); - - dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); -<<<<<<< -======= - - break; ->>>>>>> - } - - ret = geni_se_resources_off(&gi2c->se); - if (ret) { - dev_err(dev, "Error turning off resources %d\n", ret); - goto err_dma; - } - - ret = geni_icc_disable(&gi2c->se); - if (ret) - goto err_dma; - - gi2c->suspended = 1; - pm_runtime_set_suspended(gi2c->se.dev); - pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY); - pm_runtime_use_autosuspend(gi2c->se.dev); - pm_runtime_enable(gi2c->se.dev); - - ret = i2c_add_adapter(&gi2c->adap); - if (ret) { - dev_err(dev, "Error adding i2c adapter %d\n", ret); - pm_runtime_disable(gi2c->se.dev); - goto err_dma; - } - - dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); - - return 0; - -err_dma: - release_gpi_dma(gi2c); - return ret; -} - -static int geni_i2c_remove(struct platform_device *pdev) -{ - struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); - - release_gpi_dma(gi2c); - i2c_del_adapter(&gi2c->adap); - pm_runtime_disable(gi2c->se.dev); - return 0; -} - -static void geni_i2c_shutdown(struct platform_device *pdev) -{ - struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); - - /* Make client i2c transfers start failing */ - i2c_mark_adapter_suspended(&gi2c->adap); -} - -static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) -{ - int ret; - struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); - - disable_irq(gi2c->irq); - ret = geni_se_resources_off(&gi2c->se); - if (ret) { - enable_irq(gi2c->irq); - return ret; - - } else { - gi2c->suspended = 1; - } - - return geni_icc_disable(&gi2c->se); -} - -static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) -{ - int ret; - struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); - - ret = geni_icc_enable(&gi2c->se); - if (ret) - return ret; - - ret = geni_se_resources_on(&gi2c->se); - if (ret) - return ret; - - enable_irq(gi2c->irq); - gi2c->suspended = 0; - return 0; -} - -static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev) -{ - struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); - - i2c_mark_adapter_suspended(&gi2c->adap); - - if (!gi2c->suspended) { - geni_i2c_runtime_suspend(dev); - pm_runtime_disable(dev); - pm_runtime_set_suspended(dev); - pm_runtime_enable(dev); - } - return 0; -} - -static int __maybe_unused geni_i2c_resume_noirq(struct device *dev) -{ - struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); - - i2c_mark_adapter_resumed(&gi2c->adap); - return 0; -} - -static const struct dev_pm_ops geni_i2c_pm_ops = { - SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq) - SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume, - NULL) -}; - -static const struct of_device_id geni_i2c_dt_match[] = { - { .compatible = "qcom,geni-i2c" }, - {} -}; -MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); - -static struct platform_driver geni_i2c_driver = { - .probe = geni_i2c_probe, - .remove = geni_i2c_remove, - .shutdown = geni_i2c_shutdown, - .driver = { - .name = "geni_i2c", - .pm = &geni_i2c_pm_ops, - .of_match_table = geni_i2c_dt_match, - .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match), - }, -}; - -module_platform_driver(geni_i2c_driver); - -MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores"); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/74a19bbec5aac0cd5a7c5c7fa4b1c74ce3b90099/preimage b/rr-cache/74a19bbec5aac0cd5a7c5c7fa4b1c74ce3b90099/preimage deleted file mode 100644 index 87b7585..0000000 --- a/rr-cache/74a19bbec5aac0cd5a7c5c7fa4b1c74ce3b90099/preimage +++ /dev/null @@ -1,394 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2021, Linaro Ltd. - * - */ -#ifndef _MHI_EP_H_ -#define _MHI_EP_H_ - -#include -#include - -<<<<<<< -#define MHI_EP_DEFAULT_MTU 0x4000 - -struct mhi_ep_chan; -struct mhi_ep_cmd; -struct mhi_ep_event; -struct mhi_cmd_ctxt; -struct mhi_event_ctxt; -struct mhi_chan_ctxt; - -======= -#define MHI_EP_DEFAULT_MTU 0x8000 - -/** - * struct mhi_ep_channel_config - Channel configuration structure for controller - * @name: The name of this channel - * @num: The number assigned to this channel - * @num_elements: The number of elements that can be queued to this channel - * @dir: Direction that data may flow on this channel - */ ->>>>>>> -struct mhi_ep_channel_config { - char *name; - u32 num; - u32 num_elements; - enum dma_data_direction dir; -}; - -<<<<<<< -======= -/** - * struct mhi_ep_cntrl_config - MHI Endpoint controller configuration - * @max_channels: Maximum number of channels supported - * @num_channels: Number of channels defined in @ch_cfg - * @ch_cfg: Array of defined channels - * @mhi_version: MHI spec version supported by the controller - */ ->>>>>>> -struct mhi_ep_cntrl_config { - u32 max_channels; - u32 num_channels; - const struct mhi_ep_channel_config *ch_cfg; - u32 mhi_version; -}; - -<<<<<<< -/** - * struct mhi_ep_db_info - MHI Endpoint doorbell info - * @mask: Mask of the doorbell interrupt - * @status: Status of the doorbell interrupt - */ -struct mhi_ep_db_info { - u32 mask; - u32 status; -}; - -/** - * struct mhi_ep_cntrl - MHI Endpoint controller structure - * @cntrl_dev: Pointer to the struct device of physical bus acting as the MHI - * Endpoint controller - * @mhi_dev: MHI Endpoint device instance for the controller - * @mmio: MMIO region containing the MHI registers - * @mhi_chan: Points to the channel configuration table - * @mhi_event: Points to the event ring configurations table - * @mhi_cmd: Points to the command ring configurations table - * @sm: MHI Endpoint state machine - * @ch_ctx_cache: Cache of host channel context data structure - * @ev_ctx_cache: Cache of host event context data structure - * @cmd_ctx_cache: Cache of host command context data structure - * @ch_ctx_host_pa: Physical address of host channel context data structure - * @ev_ctx_host_pa: Physical address of host event context data structure - * @cmd_ctx_host_pa: Physical address of host command context data structure - * @ch_ctx_cache_phys: Physical address of the host channel context cache - * @ev_ctx_cache_phys: Physical address of the host event context cache - * @cmd_ctx_cache_phys: Physical address of the host command context cache - * @ch_ctx_host_size: Size of the host channel context data structure - * @ev_ctx_host_size: Size of the host event context data structure - * @cmd_ctx_host_size: Size of the host command context data structure - * @state_wq: Dedicated workqueue for handling MHI state transitions - * @ring_wq: Dedicated workqueue for processing MHI rings - * @state_work: State transition worker - * @ring_work: Ring worker - * @reset_work: Worker for MHI Endpoint reset - * @ch_db_list: List of queued channel doorbells - * @st_transition_list: List of state transitions - * @list_lock: Lock for protecting state transition and channel doorbell lists - * @state_lock: Lock for protecting state transitions - * @event_lock: Lock for protecting event rings - * @chdb: Array of channel doorbell interrupt info - * @raise_irq: CB function for raising IRQ to the host - * @alloc_addr: CB function for allocating memory in endpoint for storing host context - * @map_addr: CB function for mapping host context to endpoint - * @free_addr: CB function to free the allocated memory in endpoint for storing host context - * @unmap_addr: CB function to unmap the host context in endpoint - * @read_from_host: CB function for reading from host memory from endpoint - * @write_to_host: CB function for writing to host memory from endpoint - * @mhi_state: MHI Endpoint state - * @max_chan: Maximum channels supported by the endpoint controller - * @mru: MRU (Maximum Receive Unit) value of the endpoint controller - * @event_rings: Number of event rings supported by the endpoint controller - * @hw_event_rings: Number of hardware event rings supported by the endpoint controller - * @chdb_offset: Channel doorbell offset set by the host - * @erdb_offset: Event ring doorbell offset set by the host - * @index: MHI Endpoint controller index - * @irq: IRQ used by the endpoint controller - * @is_enabled: Check if the endpoint controller is enabled or not - */ -======= -struct mhi_ep_interrupt_state { - u32 mask; - u32 status; -}; - ->>>>>>> -struct mhi_ep_cntrl { - struct device *cntrl_dev; - struct mhi_ep_device *mhi_dev; - void __iomem *mmio; - - struct mhi_ep_chan *mhi_chan; -<<<<<<< - struct mhi_ep_cmd *mhi_cmd; - struct mhi_ep_event *mhi_event; - struct mhi_ep_sm *sm; - - /* Host control base information */ - struct mhi_chan_ctxt *ch_ctx_cache; - struct mhi_event_ctxt *ev_ctx_cache; - struct mhi_cmd_ctxt *cmd_ctx_cache; - -======= - struct mhi_ep_event *mhi_event; - struct mhi_ep_cmd *mhi_cmd; - struct mhi_ep_sm *sm; - - struct mhi_chan_ctxt *ch_ctx_cache; - struct mhi_event_ctxt *ev_ctx_cache; - struct mhi_cmd_ctxt *cmd_ctx_cache; ->>>>>>> - u64 ch_ctx_host_pa; - u64 ev_ctx_host_pa; - u64 cmd_ctx_host_pa; - phys_addr_t ch_ctx_cache_phys; - phys_addr_t ev_ctx_cache_phys; - phys_addr_t cmd_ctx_cache_phys; - size_t ch_ctx_host_size; - size_t ev_ctx_host_size; - size_t cmd_ctx_host_size; - - struct workqueue_struct *state_wq; - struct workqueue_struct *ring_wq; - struct work_struct state_work; - struct work_struct ring_work; -<<<<<<< - struct work_struct init_work; - struct work_struct reset_work; - - struct list_head ring_transition_list; - struct list_head st_transition_list; - spinlock_t transition_lock; - spinlock_t state_lock; - - struct mutex event_lock; - - /* CHDB and EVDB device interrupt state */ - struct mhi_ep_interrupt_state chdb[4]; - struct mhi_ep_interrupt_state evdb[4]; - - void (*raise_irq)(struct mhi_ep_cntrl *mhi_cntrl); - void __iomem *(*alloc_addr)(struct mhi_ep_cntrl *mhi_cntrl, - phys_addr_t *phys_addr, size_t size); - void (*free_addr)(struct mhi_ep_cntrl *mhi_cntrl, - phys_addr_t phys_addr, void __iomem *virt_addr, size_t size); - int (*map_addr)(struct mhi_ep_cntrl *mhi_cntrl, - phys_addr_t phys_addr, u64 pci_addr, size_t size); - void (*unmap_addr)(struct mhi_ep_cntrl *mhi_cntrl, - phys_addr_t phys_addr); - - enum mhi_state mhi_state; - - u32 reg_len; - u32 version; - u32 event_rings; - u32 hw_event_rings; - u32 max_chan; - u32 channels; - u32 chdb_offset; - u32 erdb_offset; - - int irq; - int index; - bool is_enabled; -}; - -======= - struct work_struct reset_work; - - struct list_head ch_db_list; - struct list_head st_transition_list; - spinlock_t list_lock; - spinlock_t state_lock; - struct mutex event_lock; - struct mhi_ep_db_info chdb[4]; - - void (*raise_irq)(struct mhi_ep_cntrl *mhi_cntrl, u32 vector); - void __iomem *(*alloc_addr)(struct mhi_ep_cntrl *mhi_cntrl, phys_addr_t *phys_addr, - size_t size); - int (*map_addr)(struct mhi_ep_cntrl *mhi_cntrl, phys_addr_t phys_addr, u64 pci_addr, - size_t size); - void (*free_addr)(struct mhi_ep_cntrl *mhi_cntrl, phys_addr_t phys_addr, - void __iomem *virt_addr, size_t size); - void (*unmap_addr)(struct mhi_ep_cntrl *mhi_cntrl, phys_addr_t phys_addr); - int (*read_from_host)(struct mhi_ep_cntrl *mhi_cntrl, u64 from, void __iomem *to, - size_t size); - int (*write_to_host)(struct mhi_ep_cntrl *mhi_cntrl, void __iomem *from, u64 to, - size_t size); - - enum mhi_state mhi_state; - - u32 max_chan; - u32 mru; - u32 event_rings; - u32 hw_event_rings; - u32 chdb_offset; - u32 erdb_offset; - int index; - int irq; - bool is_enabled; -}; - -/** - * struct mhi_ep_device - Structure representing an MHI Endpoint device that binds - * to channels or is associated with controllers - * @dev: Driver model device node for the MHI Endpoint device - * @mhi_cntrl: Controller the device belongs to - * @id: Pointer to MHI Endpoint device ID struct - * @name: Name of the associated MHI Endpoint device - * @ul_chan: UL channel for the device - * @dl_chan: DL channel for the device - * @dev_type: MHI device type - */ ->>>>>>> -struct mhi_ep_device { - struct device dev; - struct mhi_ep_cntrl *mhi_cntrl; - const struct mhi_device_id *id; - const char *name; - struct mhi_ep_chan *ul_chan; - struct mhi_ep_chan *dl_chan; - enum mhi_device_type dev_type; -<<<<<<< - int ul_chan_id; - int dl_chan_id; -}; - -======= -}; - -/** - * struct mhi_ep_driver - Structure representing a MHI Endpoint client driver - * @id_table: Pointer to MHI Endpoint device ID table - * @driver: Device driver model driver - * @probe: CB function for client driver probe function - * @remove: CB function for client driver remove function - * @ul_xfer_cb: CB function for UL data transfer - * @dl_xfer_cb: CB function for DL data transfer - */ ->>>>>>> -struct mhi_ep_driver { - const struct mhi_device_id *id_table; - struct device_driver driver; - int (*probe)(struct mhi_ep_device *mhi_ep, - const struct mhi_device_id *id); - void (*remove)(struct mhi_ep_device *mhi_ep); - void (*ul_xfer_cb)(struct mhi_ep_device *mhi_dev, - struct mhi_result *result); - void (*dl_xfer_cb)(struct mhi_ep_device *mhi_dev, - struct mhi_result *result); -}; - -#define to_mhi_ep_device(dev) container_of(dev, struct mhi_ep_device, dev) -#define to_mhi_ep_driver(drv) container_of(drv, struct mhi_ep_driver, driver) - -/* - * module_mhi_ep_driver() - Helper macro for drivers that don't do - * anything special other than using default mhi_ep_driver_register() and - * mhi_ep_driver_unregister(). This eliminates a lot of boilerplate. - * Each module may only use this macro once. - */ -#define module_mhi_ep_driver(mhi_drv) \ - module_driver(mhi_drv, mhi_ep_driver_register, \ - mhi_ep_driver_unregister) - -/* - * Macro to avoid include chaining to get THIS_MODULE - */ -#define mhi_ep_driver_register(mhi_drv) \ - __mhi_ep_driver_register(mhi_drv, THIS_MODULE) - -<<<<<<< -/** - * __mhi_ep_driver_register - Register a driver with MHI Endpoint bus - * @mhi_drv: Driver to be associated with the device - * @owner: The module owner - * - * Return: 0 if driver registrations succeeds, a negative error code otherwise. - */ -int __mhi_ep_driver_register(struct mhi_ep_driver *mhi_drv, struct module *owner); - -/** - * mhi_ep_driver_unregister - Unregister a driver from MHI Endpoint bus - * @mhi_drv: Driver associated with the device - */ -void mhi_ep_driver_unregister(struct mhi_ep_driver *mhi_drv); - -/** - * mhi_ep_register_controller - Register MHI Endpoint controller - * @mhi_cntrl: MHI Endpoint controller to register - * @config: Configuration to use for the controller - * - * Return: 0 if controller registrations succeeds, a negative error code otherwise. - */ -int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl, - const struct mhi_ep_cntrl_config *config); - -/** - * mhi_ep_unregister_controller - Unregister MHI Endpoint controller - * @mhi_cntrl: MHI Endpoint controller to unregister - */ -void mhi_ep_unregister_controller(struct mhi_ep_cntrl *mhi_cntrl); - -/** - * mhi_ep_power_up - Power up the MHI endpoint stack - * @mhi_cntrl: MHI Endpoint controller - * - * Return: 0 if power up succeeds, a negative error code otherwise. - */ -int mhi_ep_power_up(struct mhi_ep_cntrl *mhi_cntrl); - -/** - * mhi_ep_power_down - Power down the MHI endpoint stack - * @mhi_cntrl: MHI controller - */ -void mhi_ep_power_down(struct mhi_ep_cntrl *mhi_cntrl); - -/** - * mhi_ep_queue_is_empty - Determine whether the transfer queue is empty - * @mhi_dev: Device associated with the channels - * @dir: DMA direction for the channel - * - * Return: true if the queue is empty, false otherwise. - */ -bool mhi_ep_queue_is_empty(struct mhi_ep_device *mhi_dev, enum dma_data_direction dir); - -/** - * mhi_ep_queue_skb - Send SKBs to host over MHI Endpoint - * @mhi_dev: Device associated with the channels - * @dir: DMA direction for the channel - * @skb: Buffer for holding SKBs - * @len: Buffer length - * @mflags: MHI Endpoint transfer flags used for the transfer - * - * Return: 0 if the SKBs has been sent successfully, a negative error code otherwise. - */ -int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, enum dma_data_direction dir, - struct sk_buff *skb, size_t len, enum mhi_flags mflags); - -======= -int __mhi_ep_driver_register(struct mhi_ep_driver *mhi_drv, struct module *owner); -void mhi_ep_driver_unregister(struct mhi_ep_driver *mhi_drv); - -int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl, - const struct mhi_ep_cntrl_config *config); -void mhi_ep_unregister_controller(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_power_up(struct mhi_ep_cntrl *mhi_cntrl); -void mhi_ep_power_down(struct mhi_ep_cntrl *mhi_cntrl); - -int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, enum dma_data_direction dir, - struct sk_buff *skb, size_t len, enum mhi_flags mflags); -bool mhi_ep_queue_is_empty(struct mhi_ep_device *mhi_dev, enum dma_data_direction dir); - ->>>>>>> -#endif diff --git a/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/postimage.2 b/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/postimage.2 deleted file mode 100644 index b877f94..0000000 --- a/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/postimage.2 +++ /dev/null @@ -1,2822 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <76800000>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 2>; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "silver-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <800>; - exit-latency-us = <750>; - min-residency-us = <4090>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "gold-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <600>; - exit-latency-us = <1550>; - min-residency-us = <4791>; - local-timer-stop; - }; - }; - - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-l3-off"; - arm,psci-suspend-param = <0x41000044>; - entry-latency-us = <1050>; - exit-latency-us = <2500>; - min-residency-us = <5309>; - local-timer-stop; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; - arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <2700>; - exit-latency-us = <3500>; - min-residency-us = <13959>; - local-timer-stop; - }; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8450", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - clk_virt: interconnect@0 { - compatible = "qcom,sm8450-clk-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@1 { - compatible = "qcom,sm8450-mc-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - memory@a0000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0xa0000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: cpu-cluster0 { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; - }; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_dt_log_mem: memory@80600000 { - reg = <0x0 0x80600000 0x0 0x40000>; - no-map; - }; - - xbl_ramdump_mem: memory@80640000 { - reg = <0x0 0x80640000 0x0 0x180000>; - no-map; - }; - - xbl_sc_mem: memory@807c0000 { - reg = <0x0 0x807c0000 0x0 0x40000>; - no-map; - }; - - aop_image_mem: memory@80800000 { - reg = <0x0 0x80800000 0x0 0x60000>; - no-map; - }; - - aop_cmd_db_mem: memory@80860000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x80860000 0x0 0x20000>; - no-map; - }; - - aop_config_mem: memory@80880000 { - reg = <0x0 0x80880000 0x0 0x20000>; - no-map; - }; - - tme_crash_dump_mem: memory@808a0000 { - reg = <0x0 0x808a0000 0x0 0x40000>; - no-map; - }; - - tme_log_mem: memory@808e0000 { - reg = <0x0 0x808e0000 0x0 0x4000>; - no-map; - }; - - uefi_log_mem: memory@808e4000 { - reg = <0x0 0x808e4000 0x0 0x10000>; - no-map; - }; - - /* secdata region can be reused by apps */ - smem: memory@80900000 { - compatible = "qcom,smem"; - reg = <0x0 0x80900000 0x0 0x200000>; - hwlocks = <&tcsr_mutex 3>; - no-map; - }; - - cpucp_fw_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x100000>; - no-map; - }; - - cdsp_secure_heap: memory@80c00000 { - reg = <0x0 0x80c00000 0x0 0x4600000>; - no-map; - }; - - camera_mem: memory@85200000 { - reg = <0x0 0x85200000 0x0 0x500000>; - no-map; - }; - - video_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x700000>; - no-map; - }; - - adsp_mem: memory@85e00000 { - reg = <0x0 0x85e00000 0x0 0x2100000>; - no-map; - }; - - slpi_mem: memory@88000000 { - reg = <0x0 0x88000000 0x0 0x1900000>; - no-map; - }; - - cdsp_mem: memory@89900000 { - reg = <0x0 0x89900000 0x0 0x2000000>; - no-map; - }; - - ipa_fw_mem: memory@8b900000 { - reg = <0x0 0x8b900000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@8b910000 { - reg = <0x0 0x8b910000 0x0 0xa000>; - no-map; - }; - - gpu_micro_code_mem: memory@8b91a000 { - reg = <0x0 0x8b91a000 0x0 0x2000>; - no-map; - }; - - spss_region_mem: memory@8ba00000 { - reg = <0x0 0x8ba00000 0x0 0x180000>; - no-map; - }; - - /* First part of the "SPU secure shared memory" region */ - spu_tz_shared_mem: memory@8bb80000 { - reg = <0x0 0x8bb80000 0x0 0x60000>; - no-map; - }; - - /* Second part of the "SPU secure shared memory" region */ - spu_modem_shared_mem: memory@8bbe0000 { - reg = <0x0 0x8bbe0000 0x0 0x20000>; - no-map; - }; - - mpss_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x13200000>; - no-map; - }; - - cvp_mem: memory@9ee00000 { - reg = <0x0 0x9ee00000 0x0 0x700000>; - no-map; - }; - - rmtfs_mem: memory@9fd00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x9fd00000 0x0 0x280000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - global_sync_mem: memory@a6f00000 { - reg = <0x0 0xa6f00000 0x0 0x100000>; - no-map; - }; - - /* uefi region can be reused by APPS */ - - /* Linux kernel image is loaded at 0xa0000000 */ - - oem_vm_mem: memory@bb000000 { - reg = <0x0 0xbb000000 0x0 0x5000000>; - no-map; - }; - - mte_mem: memory@c0000000 { - reg = <0x0 0xc0000000 0x0 0x20000000>; - no-map; - }; - - qheebsp_reserved_mem: memory@e0000000 { - reg = <0x0 0xe0000000 0x0 0x600000>; - no-map; - }; - - cpusys_vm_mem: memory@e0600000 { - reg = <0x0 0xe0600000 0x0 0x400000>; - no-map; - }; - - hyp_reserved_mem: memory@e0a00000 { - reg = <0x0 0xe0a00000 0x0 0x100000>; - no-map; - }; - - trust_ui_vm_mem: memory@e0b00000 { - reg = <0x0 0xe0b00000 0x0 0x4af3000>; - no-map; - }; - - trust_ui_vm_qrtr: memory@e55f3000 { - reg = <0x0 0xe55f3000 0x0 0x9000>; - no-map; - }; - - trust_ui_vm_vblk0_ring: memory@e55fc000 { - reg = <0x0 0xe55fc000 0x0 0x4000>; - no-map; - }; - - trust_ui_vm_swiotlb: memory@e5600000 { - reg = <0x0 0xe5600000 0x0 0x100000>; - no-map; - }; - - tz_stat_mem: memory@e8800000 { - reg = <0x0 0xe8800000 0x0 0x100000>; - no-map; - }; - - tags_mem: memory@e8900000 { - reg = <0x0 0xe8900000 0x0 0x1200000>; - no-map; - }; - - qtee_mem: memory@e9b00000 { - reg = <0x0 0xe9b00000 0x0 0x500000>; - no-map; - }; - - trusted_apps_mem: memory@ea000000 { - reg = <0x0 0xea000000 0x0 0x3900000>; - no-map; - }; - - trusted_apps_ext_mem: memory@ed900000 { - reg = <0x0 0xed900000 0x0 0x3b00000>; - no-map; - }; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - smp2p_cdsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_cdsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - smp2p_modem_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_modem_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8450"; - reg = <0x0 0x00100000 0x0 0x1f4200>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; - }; - - qupv3_id_0: geniqup@9c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x009c0000 0x0 0x2000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - uart7: serial@99c000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x0099c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_data_clk>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c14: i2c@a98000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_data_clk>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8450-config-noc"; - reg = <0 0x01500000 0 0x1c000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1680000 { - compatible = "qcom,sm8450-system-noc"; - reg = <0 0x01680000 0 0x1e200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - pcie_noc: interconnect@16c0000 { - compatible = "qcom,sm8450-pcie-anoc"; - reg = <0 0x016c0000 0 0xe280>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8450-aggre1-noc"; - reg = <0 0x016e0000 0 0x1c080>; - #interconnect-cells = <2>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8450-aggre2-noc"; - reg = <0 0x01700000 0 0x31080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&rpmhcc RPMH_IPA_CLK>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8450-mmss-noc"; - reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x01f40000 0x0 0x40000>; - #hwlock-cells = <1>; - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8450-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8450-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8450-slpi-pas"; - reg = <0 0x02400000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "slpi"; - qcom,remote-pid = <3>; - }; - }; - - remoteproc_adsp: remoteproc@30000000 { - compatible = "qcom,sm8450-adsp-pas"; - reg = <0 0x030000000 0 0x100>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - remoteproc_adsp_glink: glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <2>; - }; - }; - - remoteproc_cdsp: remoteproc@32300000 { - compatible = "qcom,sm8450-cdsp-pas"; - reg = <0 0x032300000 0 0x1400000>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_CX>, - <&rpmhpd SM8450_MXC>; - power-domain-names = "cx", "mxc"; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_cdsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "cdsp"; - qcom,remote-pid = <5>; - }; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8450-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 0>, - <&rpmhpd 12>; - power-domain-names = "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_modem_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - }; - }; - - cci0: cci@ac15000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac15000 0 0x1000>; - interrupts = ; - power-domains = <&camcc TITAN_TOP_GDSC>; - - clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_0_CLK>, - <&camcc CAM_CC_CCI_0_CLK_SRC>; - clock-names = "camnoc_axi", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - pinctrl-0 = <&cci0_default &cci1_default>; - pinctrl-1 = <&cci0_sleep &cci1_sleep>; - pinctrl-names = "default", "sleep"; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - cci0_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci0_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cci1: cci@ac16000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac16000 0 0x1000>; - interrupts = ; - power-domains = <&camcc TITAN_TOP_GDSC>; - - clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_1_CLK>, - <&camcc CAM_CC_CCI_1_CLK_SRC>; - clock-names = "camnoc_axi", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - pinctrl-0 = <&cci2_default &cci2_default>; - pinctrl-1 = <&cci3_sleep &cci3_sleep>; - pinctrl-names = "default", "sleep"; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - cci1_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci1_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - camcc: clock-controller@ade0000 { - compatible = "qcom,sm8450-camcc"; - reg = <0 0x0ade0000 0 0x20000>; - status = "disabled"; - clocks = <&gcc GCC_CAMERA_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - clock-names = "iface", - "bi_tcxo", - "bi_tcxo_ao", - "sleep_clk"; - power-domains = <&rpmhpd SM8450_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8450-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; - qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, - <94 609 31>, <125 63 1>, <126 716 12>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1000>, /* TM */ - <0 0x0c222000 0 0x1000>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1000>, /* TM */ - <0 0x0c223000 0 0x1000>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; - reg = <0 0x0c300000 0 0x400>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - }; - - ipcc: mailbox@ed18000 { - compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; - reg = <0 0x0ed18000 0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8450-tlmm"; - reg = <0 0x0f100000 0 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 211>; - wakeup-parent = <&pdc>; - - cam_sensor_mclk0_default: cam-sensor-mclk0-default-state { - pins = "gpio100"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk0_sleep: cam-sensor-mclk0-sleep-state { - pins = "gpio100"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk1_default: cam-sensor-mclk1-default-state { - pins = "gpio101"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk1_sleep: cam-sensor-mclk1-sleep-state { - pins = "gpio101"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk2_default: cam-sensor-mclk2-default-state { - pins = "gpio102"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk2_sleep: cam-sensor-mclk2-sleep-state { - pins = "gpio102"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk3_default: cam-sensor-mclk3-default-state { - pins = "gpio103"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk3_sleep: cam-sensor-mclk3-sleep-state { - pins = "gpio103"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk4_default: cam-sensor-mclk4-default-state { - pins = "gpio104"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk4_sleep: cam-sensor-mclk4-sleep-state { - pins = "gpio104"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk5_default: cam-sensor-mclk5-default-state { - pins = "gpio105"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk5_sleep: cam-sensor-mclk5-sleep-state { - pins = "gpio105"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk6_default: cam-sensor-mclk6-default-state { - pins = "gpio106"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk6_sleep: cam-sensor-mclk6-sleep-state { - pins = "gpio106"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cci0_default: cci0-default-state { - /* SDA, SCL */ - pins = "gpio110", "gpio111"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci0_sleep: cci0-sleep-state { - /* SDA, SCL */ - pins = "gpio110", "gpio111"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci1_default: cci1-default-state { - /* SDA, SCL */ - pins = "gpio112", "gpio113"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci1_sleep: cci1-sleep-state { - /* SDA, SCL */ - pins = "gpio112", "gpio113"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci2_default: cci2-default-state { - /* SDA, SCL */ - pins = "gpio114", "gpio115"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci2_sleep: cci2-sleep-state { - /* SDA, SCL */ - pins = "gpio114", "gpio115"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci3_default: cci3-default-state { - /* SDA, SCL */ - pins = "gpio208", "gpio209"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci3_sleep: cci3-sleep-state { - /* SDA, SCL */ - pins = "gpio208", "gpio209"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - qup_i2c13_data_clk: qup-i2c13-data-clk { - pins = "gpio48", "gpio49"; - function = "qup13"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c14_data_clk: qup-i2c14-data-clk { - pins = "gpio52", "gpio53"; - function = "qup14"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_uart7_rx: qup-uart7-rx { - pins = "gpio26"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart7_tx: qup-uart7-tx { - pins = "gpio27"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - intc: interrupt-controller@17100000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x40000>; - reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ - <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ - interrupts = ; - }; - - timer@17420000 { - compatible = "arm,armv7-timer-mem"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - reg = <0x0 0x17420000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17421000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17421000 0x0 0x1000>, - <0x0 0x17422000 0x0 0x1000>; - }; - - frame@17423000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17423000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17425000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17425000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17427000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17427000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17429000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17429000 0x0 0x1000>; - status = "disabled"; - }; - - frame@1742b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x1742b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@1742d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x1742d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@17a00000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x17a00000 0x0 0x10000>, - <0x0 0x17a10000 0x0 0x10000>, - <0x0 0x17a20000 0x0 0x10000>, - <0x0 0x17a30000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , , - , ; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sm8450-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8450-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - }; - - cpufreq_hw: cpufreq@17d91000 { - compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0 0x17d91000 0 0x1000>, - <0 0x17d92000 0 0x1000>, - <0 0x17d93000 0 0x1000>; - reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - interrupts = , - , - ; - interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; - #freq-domain-cells = <1>; - }; - - gem_noc: interconnect@19100000 { - compatible = "qcom,sm8450-gem-noc"; - reg = <0 0x19100000 0 0xbb800>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@19200000 { - compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8450-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0xe0 0x0>; - - interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; - interconnect-names = "ufs-ddr", "cpu-ufs"; - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>; - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8450-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0xe10>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", "ref_aux", "qref"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, - <&gcc GCC_UFS_0_CLKREF_EN>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - #clock-cells = <0>; - }; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_0_CLKREF_EN>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, - <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - nsp_noc: interconnect@320c0000 { - compatible = "qcom,sm8450-nsp-noc"; - reg = <0 0x320c0000 0 0x10000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - lpass_ag_noc: interconnect@3c40000 { - compatible = "qcom,sm8450-lpass-ag-noc"; - reg = <0 0x3c40000 0 0x17200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - }; - - thermal-zones { - aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 1>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 2>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 3>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 5>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 6>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 12>; - - trips { - cpu7_middle_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_middle_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_middle_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_middle_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_middle_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 13>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-top-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens0 14>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu0_tj_cfg: tj_cfg { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - gpu-bottom-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens0 15>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu1_tj_cfg: tj_cfg { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cdsp0-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_0_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cdsp1-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 6>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_1_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cdsp2-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_2_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - ddr_config0: ddr0-config { - temperature = <90000>; - hysteresis = <5000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss0_config0: mdmss0-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss0_config1: mdmss0-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss1_config0: mdmss1-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss1_config1: mdmss1-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 12>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss2_config0: mdmss2-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss2_config1: mdmss2-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 13>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss3_config0: mdmss3-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss3_config1: mdmss3-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 14>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 15>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <19200000>; - }; -}; diff --git a/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/preimage b/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/preimage deleted file mode 100644 index 2e7bde7..0000000 --- a/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/preimage +++ /dev/null @@ -1,3309 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <76800000>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 2>; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "silver-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <800>; - exit-latency-us = <750>; - min-residency-us = <4090>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "gold-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <600>; - exit-latency-us = <1550>; - min-residency-us = <4791>; - local-timer-stop; - }; - }; - - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-l3-off"; - arm,psci-suspend-param = <0x41000044>; - entry-latency-us = <1050>; - exit-latency-us = <2500>; - min-residency-us = <5309>; - local-timer-stop; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; - arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <2700>; - exit-latency-us = <3500>; - min-residency-us = <13959>; - local-timer-stop; - }; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8450", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - clk_virt: interconnect@0 { - compatible = "qcom,sm8450-clk-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@1 { - compatible = "qcom,sm8450-mc-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - memory@a0000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0xa0000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: cpu-cluster0 { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; - }; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_dt_log_mem: memory@80600000 { - reg = <0x0 0x80600000 0x0 0x40000>; - no-map; - }; - - xbl_ramdump_mem: memory@80640000 { - reg = <0x0 0x80640000 0x0 0x180000>; - no-map; - }; - - xbl_sc_mem: memory@807c0000 { - reg = <0x0 0x807c0000 0x0 0x40000>; - no-map; - }; - - aop_image_mem: memory@80800000 { - reg = <0x0 0x80800000 0x0 0x60000>; - no-map; - }; - - aop_cmd_db_mem: memory@80860000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x80860000 0x0 0x20000>; - no-map; - }; - - aop_config_mem: memory@80880000 { - reg = <0x0 0x80880000 0x0 0x20000>; - no-map; - }; - - tme_crash_dump_mem: memory@808a0000 { - reg = <0x0 0x808a0000 0x0 0x40000>; - no-map; - }; - - tme_log_mem: memory@808e0000 { - reg = <0x0 0x808e0000 0x0 0x4000>; - no-map; - }; - - uefi_log_mem: memory@808e4000 { - reg = <0x0 0x808e4000 0x0 0x10000>; - no-map; - }; - - /* secdata region can be reused by apps */ - smem: memory@80900000 { - compatible = "qcom,smem"; - reg = <0x0 0x80900000 0x0 0x200000>; - hwlocks = <&tcsr_mutex 3>; - no-map; - }; - - cpucp_fw_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x100000>; - no-map; - }; - - cdsp_secure_heap: memory@80c00000 { - reg = <0x0 0x80c00000 0x0 0x4600000>; - no-map; - }; - - camera_mem: memory@85200000 { - reg = <0x0 0x85200000 0x0 0x500000>; - no-map; - }; - - video_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x700000>; - no-map; - }; - - adsp_mem: memory@85e00000 { - reg = <0x0 0x85e00000 0x0 0x2100000>; - no-map; - }; - - slpi_mem: memory@88000000 { - reg = <0x0 0x88000000 0x0 0x1900000>; - no-map; - }; - - cdsp_mem: memory@89900000 { - reg = <0x0 0x89900000 0x0 0x2000000>; - no-map; - }; - - ipa_fw_mem: memory@8b900000 { - reg = <0x0 0x8b900000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@8b910000 { - reg = <0x0 0x8b910000 0x0 0xa000>; - no-map; - }; - - gpu_micro_code_mem: memory@8b91a000 { - reg = <0x0 0x8b91a000 0x0 0x2000>; - no-map; - }; - - spss_region_mem: memory@8ba00000 { - reg = <0x0 0x8ba00000 0x0 0x180000>; - no-map; - }; - - /* First part of the "SPU secure shared memory" region */ - spu_tz_shared_mem: memory@8bb80000 { - reg = <0x0 0x8bb80000 0x0 0x60000>; - no-map; - }; - - /* Second part of the "SPU secure shared memory" region */ - spu_modem_shared_mem: memory@8bbe0000 { - reg = <0x0 0x8bbe0000 0x0 0x20000>; - no-map; - }; - - mpss_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x13200000>; - no-map; - }; - - cvp_mem: memory@9ee00000 { - reg = <0x0 0x9ee00000 0x0 0x700000>; - no-map; - }; - - rmtfs_mem: memory@9fd00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x9fd00000 0x0 0x280000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - global_sync_mem: memory@a6f00000 { - reg = <0x0 0xa6f00000 0x0 0x100000>; - no-map; - }; - - /* uefi region can be reused by APPS */ - - /* Linux kernel image is loaded at 0xa0000000 */ - - oem_vm_mem: memory@bb000000 { - reg = <0x0 0xbb000000 0x0 0x5000000>; - no-map; - }; - - mte_mem: memory@c0000000 { - reg = <0x0 0xc0000000 0x0 0x20000000>; - no-map; - }; - - qheebsp_reserved_mem: memory@e0000000 { - reg = <0x0 0xe0000000 0x0 0x600000>; - no-map; - }; - - cpusys_vm_mem: memory@e0600000 { - reg = <0x0 0xe0600000 0x0 0x400000>; - no-map; - }; - - hyp_reserved_mem: memory@e0a00000 { - reg = <0x0 0xe0a00000 0x0 0x100000>; - no-map; - }; - - trust_ui_vm_mem: memory@e0b00000 { - reg = <0x0 0xe0b00000 0x0 0x4af3000>; - no-map; - }; - - trust_ui_vm_qrtr: memory@e55f3000 { - reg = <0x0 0xe55f3000 0x0 0x9000>; - no-map; - }; - - trust_ui_vm_vblk0_ring: memory@e55fc000 { - reg = <0x0 0xe55fc000 0x0 0x4000>; - no-map; - }; - - trust_ui_vm_swiotlb: memory@e5600000 { - reg = <0x0 0xe5600000 0x0 0x100000>; - no-map; - }; - - tz_stat_mem: memory@e8800000 { - reg = <0x0 0xe8800000 0x0 0x100000>; - no-map; - }; - - tags_mem: memory@e8900000 { - reg = <0x0 0xe8900000 0x0 0x1200000>; - no-map; - }; - - qtee_mem: memory@e9b00000 { - reg = <0x0 0xe9b00000 0x0 0x500000>; - no-map; - }; - - trusted_apps_mem: memory@ea000000 { - reg = <0x0 0xea000000 0x0 0x3900000>; - no-map; - }; - - trusted_apps_ext_mem: memory@ed900000 { - reg = <0x0 0xed900000 0x0 0x3b00000>; - no-map; - }; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - smp2p_cdsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_cdsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - smp2p_modem_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_modem_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8450"; - reg = <0x0 0x00100000 0x0 0x1f4200>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&pcie0_lane>, - <&pcie1_lane>, - <&sleep_clk>; - clock-names = "bi_tcxo", - "pcie_0_pipe_clk", - "pcie_1_pipe_clk", - "sleep_clk"; - }; - - qupv3_id_2: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - uart20: serial@894000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart20_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qupv3_id_0: geniqup@9c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x009c0000 0x0 0x2000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c6: i2c@998000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00998000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_data_clk>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart7: serial@99c000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x0099c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_data_clk>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c14: i2c@a98000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_data_clk>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - pcie0: pci@1c00000 { - compatible = "qcom,pcie-sm8450-pcie0"; - reg = <0 0x01c00000 0 0x3000>, - <0 0x60000000 0 0xf1d>, - <0 0x60000f20 0 0xa8>, - <0 0x60001000 0 0x1000>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, - <&pcie0_lane>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; - clock-names = "pipe", - "pipe_mux", - "phy_pipe", - "ref", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ddrss_sf_tbu", - "aggre0", - "aggre1"; - - iommus = <&apps_smmu 0x1c00 0x7f>; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; - - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_0_GDSC>; - power-domain-names = "gdsc"; - - phys = <&pcie0_lane>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; - - interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "pci"; - - status = "disabled"; - }; - - pcie0_phy: phy@1c06000 { - compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; - reg = <0 0x01c06000 0 0x200>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_CLKREF_EN>, - <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie0_lane: lanes@1c06200 { - reg = <0 0x1c06e00 0 0x200>, /* tx */ - <0 0x1c07000 0 0x200>, /* rx */ - <0 0x1c06200 0 0x200>, /* pcs */ - <0 0x1c06600 0 0x200>; /* pcs_pcie */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; - }; - - pcie1: pci@1c08000 { - compatible = "qcom,pcie-sm8450-pcie1"; - reg = <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <2>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_lane>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; - clock-names = "pipe", - "pipe_mux", - "phy_pipe", - "ref", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ddrss_sf_tbu", - "aggre1"; - - iommus = <&apps_smmu 0x1c80 0x7f>; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; - - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_1_GDSC>; - power-domain-names = "gdsc"; - - phys = <&pcie1_lane>; - phy-names = "pciephy"; - - perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; - - interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "pci"; - - status = "disabled"; - }; - - pcie1_phy: phy@1c0f000 { - compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; - reg = <0 0x01c0f000 0 0x200>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_CLKREF_EN>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie1_lane: lanes@1c0e000 { - reg = <0 0x1c0e000 0 0x200>, /* tx */ - <0 0x1c0e200 0 0x300>, /* rx */ - <0 0x1c0f200 0 0x200>, /* pcs */ - <0 0x1c0e800 0 0x200>, /* tx */ - <0 0x1c0ea00 0 0x300>, /* rx */ - <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8450-config-noc"; - reg = <0 0x01500000 0 0x1c000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1680000 { - compatible = "qcom,sm8450-system-noc"; - reg = <0 0x01680000 0 0x1e200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - pcie_noc: interconnect@16c0000 { - compatible = "qcom,sm8450-pcie-anoc"; - reg = <0 0x016c0000 0 0xe280>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8450-aggre1-noc"; - reg = <0 0x016e0000 0 0x1c080>; - #interconnect-cells = <2>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8450-aggre2-noc"; - reg = <0 0x01700000 0 0x31080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&rpmhcc RPMH_IPA_CLK>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8450-mmss-noc"; - reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x01f40000 0x0 0x40000>; - #hwlock-cells = <1>; - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8450-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8450-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8450-slpi-pas"; - reg = <0 0x02400000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "slpi"; - qcom,remote-pid = <3>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0541 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0542 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0543 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - - remoteproc_adsp: remoteproc@30000000 { - compatible = "qcom,sm8450-adsp-pas"; - reg = <0 0x030000000 0 0x100>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - remoteproc_adsp_glink: glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <2>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1803 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1804 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1805 0x0>; - }; - }; - }; - }; - - remoteproc_cdsp: remoteproc@32300000 { - compatible = "qcom,sm8450-cdsp-pas"; - reg = <0 0x032300000 0 0x1400000>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_CX>, - <&rpmhpd SM8450_MXC>; - power-domain-names = "cx", "mxc"; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_cdsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "cdsp"; - qcom,remote-pid = <5>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x2161 0x0400>, - <&apps_smmu 0x1021 0x1420>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2162 0x0400>, - <&apps_smmu 0x1022 0x1420>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x2163 0x0400>, - <&apps_smmu 0x1023 0x1420>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x2164 0x0400>, - <&apps_smmu 0x1024 0x1420>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x2165 0x0400>, - <&apps_smmu 0x1025 0x1420>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x2166 0x0400>, - <&apps_smmu 0x1026 0x1420>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x2167 0x0400>, - <&apps_smmu 0x1027 0x1420>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x2168 0x0400>, - <&apps_smmu 0x1028 0x1420>; - }; - - /* note: secure cb9 in downstream */ - }; - }; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8450-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 0>, - <&rpmhpd 12>; - power-domain-names = "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_modem_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - }; - }; - - cci0: cci@ac15000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac15000 0 0x1000>; - interrupts = ; - power-domains = <&camcc TITAN_TOP_GDSC>; - - clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_0_CLK>, - <&camcc CAM_CC_CCI_0_CLK_SRC>; - clock-names = "camnoc_axi", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - pinctrl-0 = <&cci0_default &cci1_default>; - pinctrl-1 = <&cci0_sleep &cci1_sleep>; - pinctrl-names = "default", "sleep"; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - cci0_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci0_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cci1: cci@ac16000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac16000 0 0x1000>; - interrupts = ; - power-domains = <&camcc TITAN_TOP_GDSC>; - - clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_1_CLK>, - <&camcc CAM_CC_CCI_1_CLK_SRC>; - clock-names = "camnoc_axi", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - pinctrl-0 = <&cci2_default &cci2_default>; - pinctrl-1 = <&cci3_sleep &cci3_sleep>; - pinctrl-names = "default", "sleep"; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - cci1_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci1_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - camcc: clock-controller@ade0000 { - compatible = "qcom,camcc-sm8450"; - reg = <0 0x0ade0000 0 0x20000>; - status = "disabled"; - clocks = <&gcc GCC_CAMERA_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - clock-names = "iface", - "bi_tcxo", - "bi_tcxo_ao", - "sleep_clk"; - power-domains = <&rpmhpd SM8450_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8450-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; - qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, - <94 609 31>, <125 63 1>, <126 716 12>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1000>, /* TM */ - <0 0x0c222000 0 0x1000>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1000>, /* TM */ - <0 0x0c223000 0 0x1000>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; - reg = <0 0x0c300000 0 0x400>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - }; - - spmi_bus: spmi@c42d000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c400000 0x0 0x00003000>, - <0x0 0x0c500000 0x0 0x00400000>, - <0x0 0x0c440000 0x0 0x00080000>, - <0x0 0x0c4c0000 0x0 0x00010000>, - <0x0 0x0c42d000 0x0 0x00010000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - qcom,bus-id = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - ipcc: mailbox@ed18000 { - compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; - reg = <0 0x0ed18000 0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8450-tlmm"; - reg = <0 0x0f100000 0 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 211>; - wakeup-parent = <&pdc>; - -<<<<<<< - cam_sensor_mclk0_default: cam-sensor-mclk0-default-state { - pins = "gpio100"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk0_sleep: cam-sensor-mclk0-sleep-state { - pins = "gpio100"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk1_default: cam-sensor-mclk1-default-state { - pins = "gpio101"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk1_sleep: cam-sensor-mclk1-sleep-state { - pins = "gpio101"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk2_default: cam-sensor-mclk2-default-state { - pins = "gpio102"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk2_sleep: cam-sensor-mclk2-sleep-state { - pins = "gpio102"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk3_default: cam-sensor-mclk3-default-state { - pins = "gpio103"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk3_sleep: cam-sensor-mclk3-sleep-state { - pins = "gpio103"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk4_default: cam-sensor-mclk4-default-state { - pins = "gpio104"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk4_sleep: cam-sensor-mclk4-sleep-state { - pins = "gpio104"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk5_default: cam-sensor-mclk5-default-state { - pins = "gpio105"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk5_sleep: cam-sensor-mclk5-sleep-state { - pins = "gpio105"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk6_default: cam-sensor-mclk6-default-state { - pins = "gpio106"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk6_sleep: cam-sensor-mclk6-sleep-state { - pins = "gpio106"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cci0_default: cci0-default-state { - /* SDA, SCL */ - pins = "gpio110", "gpio111"; - function = "cci_i2c"; -======= - pcie0_default_state: pcie0-default-state { - perst { - pins = "gpio94"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq { - pins = "gpio95"; - function = "pcie0_clkreqn"; - drive-strength = <2>; - bias-pull-up; - }; - - wake { - pins = "gpio96"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_default_state: pcie1-default-state { - perst { - pins = "gpio97"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq { - pins = "gpio98"; - function = "pcie1_clkreqn"; - drive-strength = <2>; - bias-pull-up; - }; - - wake { - pins = "gpio99"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - qup_i2c6_data_clk: qup-i2c6-data-clk { - pins = "gpio20", "gpio21"; - function = "qup6"; ->>>>>>> - drive-strength = <2>; - bias-pull-up; - }; - -<<<<<<< -======= - cci0_sleep: cci0-sleep-state { - /* SDA, SCL */ - pins = "gpio110", "gpio111"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci1_default: cci1-default-state { - /* SDA, SCL */ - pins = "gpio112", "gpio113"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci1_sleep: cci1-sleep-state { - /* SDA, SCL */ - pins = "gpio112", "gpio113"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci2_default: cci2-default-state { - /* SDA, SCL */ - pins = "gpio114", "gpio115"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci2_sleep: cci2-sleep-state { - /* SDA, SCL */ - pins = "gpio114", "gpio115"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci3_default: cci3-default-state { - /* SDA, SCL */ - pins = "gpio208", "gpio209"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci3_sleep: cci3-sleep-state { - /* SDA, SCL */ - pins = "gpio208", "gpio209"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - ->>>>>>> - qup_i2c13_data_clk: qup-i2c13-data-clk { - pins = "gpio48", "gpio49"; - function = "qup13"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c14_data_clk: qup-i2c14-data-clk { - pins = "gpio52", "gpio53"; - function = "qup14"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_uart7_rx: qup-uart7-rx { - pins = "gpio26"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart7_tx: qup-uart7-tx { - pins = "gpio27"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart20_default: qup-uart20-default { - mux { - pins = "gpio76", "gpio77", - "gpio78", "gpio79"; - function = "qup20"; - }; - }; - - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - intc: interrupt-controller@17100000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x40000>; - reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ - <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ - interrupts = ; - - gic_its: msi-controller@17140000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x17140000 0x0 0x20000>; - }; - }; - - timer@17420000 { - compatible = "arm,armv7-timer-mem"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - reg = <0x0 0x17420000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17421000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17421000 0x0 0x1000>, - <0x0 0x17422000 0x0 0x1000>; - }; - - frame@17423000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17423000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17425000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17425000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17427000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17427000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17429000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17429000 0x0 0x1000>; - status = "disabled"; - }; - - frame@1742b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x1742b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@1742d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x1742d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@17a00000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x17a00000 0x0 0x10000>, - <0x0 0x17a10000 0x0 0x10000>, - <0x0 0x17a20000 0x0 0x10000>, - <0x0 0x17a30000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , , - , ; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sm8450-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8450-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - }; - - cpufreq_hw: cpufreq@17d91000 { - compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0 0x17d91000 0 0x1000>, - <0 0x17d92000 0 0x1000>, - <0 0x17d93000 0 0x1000>; - reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - interrupts = , - , - ; - interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; - #freq-domain-cells = <1>; - }; - - gem_noc: interconnect@19100000 { - compatible = "qcom,sm8450-gem-noc"; - reg = <0 0x19100000 0 0xbb800>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@19200000 { - compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8450-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0xe0 0x0>; - - interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; - interconnect-names = "ufs-ddr", "cpu-ufs"; - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>; - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8450-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0xe10>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", "ref_aux", "qref"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, - <&gcc GCC_UFS_0_CLKREF_EN>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - #clock-cells = <0>; - }; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_0_CLKREF_EN>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, - <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - nsp_noc: interconnect@320c0000 { - compatible = "qcom,sm8450-nsp-noc"; - reg = <0 0x320c0000 0 0x10000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - lpass_ag_noc: interconnect@3c40000 { - compatible = "qcom,sm8450-lpass-ag-noc"; - reg = <0 0x3c40000 0 0x17200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - }; - - thermal-zones { - aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 1>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 2>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 3>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 5>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 6>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 12>; - - trips { - cpu7_middle_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_middle_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_middle_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_middle_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_middle_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 13>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-top-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens0 14>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu0_tj_cfg: tj_cfg { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - gpu-bottom-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens0 15>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu1_tj_cfg: tj_cfg { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cdsp0-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_0_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cdsp1-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 6>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_1_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cdsp2-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_2_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - ddr_config0: ddr0-config { - temperature = <90000>; - hysteresis = <5000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss0_config0: mdmss0-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss0_config1: mdmss0-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss1_config0: mdmss1-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss1_config1: mdmss1-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 12>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss2_config0: mdmss2-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss2_config1: mdmss2-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 13>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss3_config0: mdmss3-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss3_config1: mdmss3-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 14>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 15>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <19200000>; - }; -}; diff --git a/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/preimage.1 b/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/preimage.1 deleted file mode 100644 index ab009fe..0000000 --- a/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/preimage.1 +++ /dev/null @@ -1,3309 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <76800000>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 2>; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "silver-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <800>; - exit-latency-us = <750>; - min-residency-us = <4090>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "gold-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <600>; - exit-latency-us = <1550>; - min-residency-us = <4791>; - local-timer-stop; - }; - }; - - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-l3-off"; - arm,psci-suspend-param = <0x41000044>; - entry-latency-us = <1050>; - exit-latency-us = <2500>; - min-residency-us = <5309>; - local-timer-stop; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; - arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <2700>; - exit-latency-us = <3500>; - min-residency-us = <13959>; - local-timer-stop; - }; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8450", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - clk_virt: interconnect@0 { - compatible = "qcom,sm8450-clk-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@1 { - compatible = "qcom,sm8450-mc-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - memory@a0000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0xa0000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: cpu-cluster0 { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; - }; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_dt_log_mem: memory@80600000 { - reg = <0x0 0x80600000 0x0 0x40000>; - no-map; - }; - - xbl_ramdump_mem: memory@80640000 { - reg = <0x0 0x80640000 0x0 0x180000>; - no-map; - }; - - xbl_sc_mem: memory@807c0000 { - reg = <0x0 0x807c0000 0x0 0x40000>; - no-map; - }; - - aop_image_mem: memory@80800000 { - reg = <0x0 0x80800000 0x0 0x60000>; - no-map; - }; - - aop_cmd_db_mem: memory@80860000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x80860000 0x0 0x20000>; - no-map; - }; - - aop_config_mem: memory@80880000 { - reg = <0x0 0x80880000 0x0 0x20000>; - no-map; - }; - - tme_crash_dump_mem: memory@808a0000 { - reg = <0x0 0x808a0000 0x0 0x40000>; - no-map; - }; - - tme_log_mem: memory@808e0000 { - reg = <0x0 0x808e0000 0x0 0x4000>; - no-map; - }; - - uefi_log_mem: memory@808e4000 { - reg = <0x0 0x808e4000 0x0 0x10000>; - no-map; - }; - - /* secdata region can be reused by apps */ - smem: memory@80900000 { - compatible = "qcom,smem"; - reg = <0x0 0x80900000 0x0 0x200000>; - hwlocks = <&tcsr_mutex 3>; - no-map; - }; - - cpucp_fw_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x100000>; - no-map; - }; - - cdsp_secure_heap: memory@80c00000 { - reg = <0x0 0x80c00000 0x0 0x4600000>; - no-map; - }; - - camera_mem: memory@85200000 { - reg = <0x0 0x85200000 0x0 0x500000>; - no-map; - }; - - video_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x700000>; - no-map; - }; - - adsp_mem: memory@85e00000 { - reg = <0x0 0x85e00000 0x0 0x2100000>; - no-map; - }; - - slpi_mem: memory@88000000 { - reg = <0x0 0x88000000 0x0 0x1900000>; - no-map; - }; - - cdsp_mem: memory@89900000 { - reg = <0x0 0x89900000 0x0 0x2000000>; - no-map; - }; - - ipa_fw_mem: memory@8b900000 { - reg = <0x0 0x8b900000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@8b910000 { - reg = <0x0 0x8b910000 0x0 0xa000>; - no-map; - }; - - gpu_micro_code_mem: memory@8b91a000 { - reg = <0x0 0x8b91a000 0x0 0x2000>; - no-map; - }; - - spss_region_mem: memory@8ba00000 { - reg = <0x0 0x8ba00000 0x0 0x180000>; - no-map; - }; - - /* First part of the "SPU secure shared memory" region */ - spu_tz_shared_mem: memory@8bb80000 { - reg = <0x0 0x8bb80000 0x0 0x60000>; - no-map; - }; - - /* Second part of the "SPU secure shared memory" region */ - spu_modem_shared_mem: memory@8bbe0000 { - reg = <0x0 0x8bbe0000 0x0 0x20000>; - no-map; - }; - - mpss_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x13200000>; - no-map; - }; - - cvp_mem: memory@9ee00000 { - reg = <0x0 0x9ee00000 0x0 0x700000>; - no-map; - }; - - rmtfs_mem: memory@9fd00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x9fd00000 0x0 0x280000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - global_sync_mem: memory@a6f00000 { - reg = <0x0 0xa6f00000 0x0 0x100000>; - no-map; - }; - - /* uefi region can be reused by APPS */ - - /* Linux kernel image is loaded at 0xa0000000 */ - - oem_vm_mem: memory@bb000000 { - reg = <0x0 0xbb000000 0x0 0x5000000>; - no-map; - }; - - mte_mem: memory@c0000000 { - reg = <0x0 0xc0000000 0x0 0x20000000>; - no-map; - }; - - qheebsp_reserved_mem: memory@e0000000 { - reg = <0x0 0xe0000000 0x0 0x600000>; - no-map; - }; - - cpusys_vm_mem: memory@e0600000 { - reg = <0x0 0xe0600000 0x0 0x400000>; - no-map; - }; - - hyp_reserved_mem: memory@e0a00000 { - reg = <0x0 0xe0a00000 0x0 0x100000>; - no-map; - }; - - trust_ui_vm_mem: memory@e0b00000 { - reg = <0x0 0xe0b00000 0x0 0x4af3000>; - no-map; - }; - - trust_ui_vm_qrtr: memory@e55f3000 { - reg = <0x0 0xe55f3000 0x0 0x9000>; - no-map; - }; - - trust_ui_vm_vblk0_ring: memory@e55fc000 { - reg = <0x0 0xe55fc000 0x0 0x4000>; - no-map; - }; - - trust_ui_vm_swiotlb: memory@e5600000 { - reg = <0x0 0xe5600000 0x0 0x100000>; - no-map; - }; - - tz_stat_mem: memory@e8800000 { - reg = <0x0 0xe8800000 0x0 0x100000>; - no-map; - }; - - tags_mem: memory@e8900000 { - reg = <0x0 0xe8900000 0x0 0x1200000>; - no-map; - }; - - qtee_mem: memory@e9b00000 { - reg = <0x0 0xe9b00000 0x0 0x500000>; - no-map; - }; - - trusted_apps_mem: memory@ea000000 { - reg = <0x0 0xea000000 0x0 0x3900000>; - no-map; - }; - - trusted_apps_ext_mem: memory@ed900000 { - reg = <0x0 0xed900000 0x0 0x3b00000>; - no-map; - }; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - smp2p_cdsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_cdsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - smp2p_modem_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_modem_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8450"; - reg = <0x0 0x00100000 0x0 0x1f4200>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&pcie0_lane>, - <&pcie1_lane>, - <&sleep_clk>; - clock-names = "bi_tcxo", - "pcie_0_pipe_clk", - "pcie_1_pipe_clk", - "sleep_clk"; - }; - - qupv3_id_2: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - uart20: serial@894000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart20_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qupv3_id_0: geniqup@9c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x009c0000 0x0 0x2000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c6: i2c@998000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00998000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_data_clk>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart7: serial@99c000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x0099c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_data_clk>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c14: i2c@a98000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_data_clk>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - pcie0: pci@1c00000 { - compatible = "qcom,pcie-sm8450-pcie0"; - reg = <0 0x01c00000 0 0x3000>, - <0 0x60000000 0 0xf1d>, - <0 0x60000f20 0 0xa8>, - <0 0x60001000 0 0x1000>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, - <&pcie0_lane>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; - clock-names = "pipe", - "pipe_mux", - "phy_pipe", - "ref", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ddrss_sf_tbu", - "aggre0", - "aggre1"; - - iommus = <&apps_smmu 0x1c00 0x7f>; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; - - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_0_GDSC>; - power-domain-names = "gdsc"; - - phys = <&pcie0_lane>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; - - interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "pci"; - - status = "disabled"; - }; - - pcie0_phy: phy@1c06000 { - compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; - reg = <0 0x01c06000 0 0x200>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_CLKREF_EN>, - <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie0_lane: lanes@1c06200 { - reg = <0 0x1c06e00 0 0x200>, /* tx */ - <0 0x1c07000 0 0x200>, /* rx */ - <0 0x1c06200 0 0x200>, /* pcs */ - <0 0x1c06600 0 0x200>; /* pcs_pcie */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; - }; - - pcie1: pci@1c08000 { - compatible = "qcom,pcie-sm8450-pcie1"; - reg = <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <2>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_lane>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; - clock-names = "pipe", - "pipe_mux", - "phy_pipe", - "ref", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ddrss_sf_tbu", - "aggre1"; - - iommus = <&apps_smmu 0x1c80 0x7f>; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; - - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_1_GDSC>; - power-domain-names = "gdsc"; - - phys = <&pcie1_lane>; - phy-names = "pciephy"; - - perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; - - interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "pci"; - - status = "disabled"; - }; - - pcie1_phy: phy@1c0f000 { - compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; - reg = <0 0x01c0f000 0 0x200>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_CLKREF_EN>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie1_lane: lanes@1c0e000 { - reg = <0 0x1c0e000 0 0x200>, /* tx */ - <0 0x1c0e200 0 0x300>, /* rx */ - <0 0x1c0f200 0 0x200>, /* pcs */ - <0 0x1c0e800 0 0x200>, /* tx */ - <0 0x1c0ea00 0 0x300>, /* rx */ - <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8450-config-noc"; - reg = <0 0x01500000 0 0x1c000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1680000 { - compatible = "qcom,sm8450-system-noc"; - reg = <0 0x01680000 0 0x1e200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - pcie_noc: interconnect@16c0000 { - compatible = "qcom,sm8450-pcie-anoc"; - reg = <0 0x016c0000 0 0xe280>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8450-aggre1-noc"; - reg = <0 0x016e0000 0 0x1c080>; - #interconnect-cells = <2>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8450-aggre2-noc"; - reg = <0 0x01700000 0 0x31080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&rpmhcc RPMH_IPA_CLK>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8450-mmss-noc"; - reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x01f40000 0x0 0x40000>; - #hwlock-cells = <1>; - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8450-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8450-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8450-slpi-pas"; - reg = <0 0x02400000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "slpi"; - qcom,remote-pid = <3>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0541 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0542 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0543 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - - remoteproc_adsp: remoteproc@30000000 { - compatible = "qcom,sm8450-adsp-pas"; - reg = <0 0x030000000 0 0x100>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - remoteproc_adsp_glink: glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <2>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1803 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1804 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1805 0x0>; - }; - }; - }; - }; - - remoteproc_cdsp: remoteproc@32300000 { - compatible = "qcom,sm8450-cdsp-pas"; - reg = <0 0x032300000 0 0x1400000>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_CX>, - <&rpmhpd SM8450_MXC>; - power-domain-names = "cx", "mxc"; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_cdsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "cdsp"; - qcom,remote-pid = <5>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x2161 0x0400>, - <&apps_smmu 0x1021 0x1420>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2162 0x0400>, - <&apps_smmu 0x1022 0x1420>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x2163 0x0400>, - <&apps_smmu 0x1023 0x1420>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x2164 0x0400>, - <&apps_smmu 0x1024 0x1420>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x2165 0x0400>, - <&apps_smmu 0x1025 0x1420>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x2166 0x0400>, - <&apps_smmu 0x1026 0x1420>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x2167 0x0400>, - <&apps_smmu 0x1027 0x1420>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x2168 0x0400>, - <&apps_smmu 0x1028 0x1420>; - }; - - /* note: secure cb9 in downstream */ - }; - }; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8450-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 0>, - <&rpmhpd 12>; - power-domain-names = "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_modem_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - }; - }; - - cci0: cci@ac15000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac15000 0 0x1000>; - interrupts = ; - power-domains = <&camcc TITAN_TOP_GDSC>; - - clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_0_CLK>, - <&camcc CAM_CC_CCI_0_CLK_SRC>; - clock-names = "camnoc_axi", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - pinctrl-0 = <&cci0_default &cci1_default>; - pinctrl-1 = <&cci0_sleep &cci1_sleep>; - pinctrl-names = "default", "sleep"; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - cci0_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci0_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cci1: cci@ac16000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac16000 0 0x1000>; - interrupts = ; - power-domains = <&camcc TITAN_TOP_GDSC>; - - clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_1_CLK>, - <&camcc CAM_CC_CCI_1_CLK_SRC>; - clock-names = "camnoc_axi", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - pinctrl-0 = <&cci2_default &cci2_default>; - pinctrl-1 = <&cci3_sleep &cci3_sleep>; - pinctrl-names = "default", "sleep"; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - cci1_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci1_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - camcc: clock-controller@ade0000 { - compatible = "qcom,sm8450-camcc"; - reg = <0 0x0ade0000 0 0x20000>; - status = "disabled"; - clocks = <&gcc GCC_CAMERA_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - clock-names = "iface", - "bi_tcxo", - "bi_tcxo_ao", - "sleep_clk"; - power-domains = <&rpmhpd SM8450_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8450-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; - qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, - <94 609 31>, <125 63 1>, <126 716 12>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1000>, /* TM */ - <0 0x0c222000 0 0x1000>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1000>, /* TM */ - <0 0x0c223000 0 0x1000>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; - reg = <0 0x0c300000 0 0x400>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - }; - - spmi_bus: spmi@c42d000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c400000 0x0 0x00003000>, - <0x0 0x0c500000 0x0 0x00400000>, - <0x0 0x0c440000 0x0 0x00080000>, - <0x0 0x0c4c0000 0x0 0x00010000>, - <0x0 0x0c42d000 0x0 0x00010000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - qcom,bus-id = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - ipcc: mailbox@ed18000 { - compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; - reg = <0 0x0ed18000 0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8450-tlmm"; - reg = <0 0x0f100000 0 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 211>; - wakeup-parent = <&pdc>; - -<<<<<<< - cam_sensor_mclk0_default: cam-sensor-mclk0-default-state { - pins = "gpio100"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk0_sleep: cam-sensor-mclk0-sleep-state { - pins = "gpio100"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk1_default: cam-sensor-mclk1-default-state { - pins = "gpio101"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk1_sleep: cam-sensor-mclk1-sleep-state { - pins = "gpio101"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk2_default: cam-sensor-mclk2-default-state { - pins = "gpio102"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk2_sleep: cam-sensor-mclk2-sleep-state { - pins = "gpio102"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk3_default: cam-sensor-mclk3-default-state { - pins = "gpio103"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk3_sleep: cam-sensor-mclk3-sleep-state { - pins = "gpio103"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk4_default: cam-sensor-mclk4-default-state { - pins = "gpio104"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk4_sleep: cam-sensor-mclk4-sleep-state { - pins = "gpio104"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk5_default: cam-sensor-mclk5-default-state { - pins = "gpio105"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk5_sleep: cam-sensor-mclk5-sleep-state { - pins = "gpio105"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk6_default: cam-sensor-mclk6-default-state { - pins = "gpio106"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk6_sleep: cam-sensor-mclk6-sleep-state { - pins = "gpio106"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cci0_default: cci0-default-state { - /* SDA, SCL */ - pins = "gpio110", "gpio111"; - function = "cci_i2c"; -======= - pcie0_default_state: pcie0-default-state { - perst { - pins = "gpio94"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq { - pins = "gpio95"; - function = "pcie0_clkreqn"; - drive-strength = <2>; - bias-pull-up; - }; - - wake { - pins = "gpio96"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_default_state: pcie1-default-state { - perst { - pins = "gpio97"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq { - pins = "gpio98"; - function = "pcie1_clkreqn"; - drive-strength = <2>; - bias-pull-up; - }; - - wake { - pins = "gpio99"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - qup_i2c6_data_clk: qup-i2c6-data-clk { - pins = "gpio20", "gpio21"; - function = "qup6"; ->>>>>>> - drive-strength = <2>; - bias-pull-up; - }; - -<<<<<<< -======= - cci0_sleep: cci0-sleep-state { - /* SDA, SCL */ - pins = "gpio110", "gpio111"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci1_default: cci1-default-state { - /* SDA, SCL */ - pins = "gpio112", "gpio113"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci1_sleep: cci1-sleep-state { - /* SDA, SCL */ - pins = "gpio112", "gpio113"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci2_default: cci2-default-state { - /* SDA, SCL */ - pins = "gpio114", "gpio115"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci2_sleep: cci2-sleep-state { - /* SDA, SCL */ - pins = "gpio114", "gpio115"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci3_default: cci3-default-state { - /* SDA, SCL */ - pins = "gpio208", "gpio209"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci3_sleep: cci3-sleep-state { - /* SDA, SCL */ - pins = "gpio208", "gpio209"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - ->>>>>>> - qup_i2c13_data_clk: qup-i2c13-data-clk { - pins = "gpio48", "gpio49"; - function = "qup13"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c14_data_clk: qup-i2c14-data-clk { - pins = "gpio52", "gpio53"; - function = "qup14"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_uart7_rx: qup-uart7-rx { - pins = "gpio26"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart7_tx: qup-uart7-tx { - pins = "gpio27"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart20_default: qup-uart20-default { - mux { - pins = "gpio76", "gpio77", - "gpio78", "gpio79"; - function = "qup20"; - }; - }; - - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - intc: interrupt-controller@17100000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x40000>; - reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ - <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ - interrupts = ; - - gic_its: msi-controller@17140000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x17140000 0x0 0x20000>; - }; - }; - - timer@17420000 { - compatible = "arm,armv7-timer-mem"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - reg = <0x0 0x17420000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17421000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17421000 0x0 0x1000>, - <0x0 0x17422000 0x0 0x1000>; - }; - - frame@17423000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17423000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17425000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17425000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17427000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17427000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17429000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17429000 0x0 0x1000>; - status = "disabled"; - }; - - frame@1742b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x1742b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@1742d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x1742d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@17a00000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x17a00000 0x0 0x10000>, - <0x0 0x17a10000 0x0 0x10000>, - <0x0 0x17a20000 0x0 0x10000>, - <0x0 0x17a30000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , , - , ; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sm8450-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8450-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - }; - - cpufreq_hw: cpufreq@17d91000 { - compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0 0x17d91000 0 0x1000>, - <0 0x17d92000 0 0x1000>, - <0 0x17d93000 0 0x1000>; - reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - interrupts = , - , - ; - interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; - #freq-domain-cells = <1>; - }; - - gem_noc: interconnect@19100000 { - compatible = "qcom,sm8450-gem-noc"; - reg = <0 0x19100000 0 0xbb800>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@19200000 { - compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8450-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0xe0 0x0>; - - interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; - interconnect-names = "ufs-ddr", "cpu-ufs"; - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>; - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8450-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0xe10>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", "ref_aux", "qref"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, - <&gcc GCC_UFS_0_CLKREF_EN>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - #clock-cells = <0>; - }; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_0_CLKREF_EN>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, - <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - nsp_noc: interconnect@320c0000 { - compatible = "qcom,sm8450-nsp-noc"; - reg = <0 0x320c0000 0 0x10000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - lpass_ag_noc: interconnect@3c40000 { - compatible = "qcom,sm8450-lpass-ag-noc"; - reg = <0 0x3c40000 0 0x17200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - }; - - thermal-zones { - aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 1>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 2>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 3>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 5>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 6>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 12>; - - trips { - cpu7_middle_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_middle_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_middle_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_middle_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_middle_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 13>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-top-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens0 14>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu0_tj_cfg: tj_cfg { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - gpu-bottom-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens0 15>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu1_tj_cfg: tj_cfg { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cdsp0-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_0_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cdsp1-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 6>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_1_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cdsp2-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_2_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - ddr_config0: ddr0-config { - temperature = <90000>; - hysteresis = <5000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss0_config0: mdmss0-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss0_config1: mdmss0-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss1_config0: mdmss1-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss1_config1: mdmss1-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 12>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss2_config0: mdmss2-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss2_config1: mdmss2-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 13>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss3_config0: mdmss3-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss3_config1: mdmss3-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 14>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 15>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <19200000>; - }; -}; diff --git a/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/preimage.2 b/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/preimage.2 deleted file mode 100644 index ab009fe..0000000 --- a/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/preimage.2 +++ /dev/null @@ -1,3309 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <76800000>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 2>; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "silver-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <800>; - exit-latency-us = <750>; - min-residency-us = <4090>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "gold-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <600>; - exit-latency-us = <1550>; - min-residency-us = <4791>; - local-timer-stop; - }; - }; - - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-l3-off"; - arm,psci-suspend-param = <0x41000044>; - entry-latency-us = <1050>; - exit-latency-us = <2500>; - min-residency-us = <5309>; - local-timer-stop; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; - arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <2700>; - exit-latency-us = <3500>; - min-residency-us = <13959>; - local-timer-stop; - }; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8450", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - clk_virt: interconnect@0 { - compatible = "qcom,sm8450-clk-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@1 { - compatible = "qcom,sm8450-mc-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - memory@a0000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0xa0000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: cpu-cluster0 { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; - }; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_dt_log_mem: memory@80600000 { - reg = <0x0 0x80600000 0x0 0x40000>; - no-map; - }; - - xbl_ramdump_mem: memory@80640000 { - reg = <0x0 0x80640000 0x0 0x180000>; - no-map; - }; - - xbl_sc_mem: memory@807c0000 { - reg = <0x0 0x807c0000 0x0 0x40000>; - no-map; - }; - - aop_image_mem: memory@80800000 { - reg = <0x0 0x80800000 0x0 0x60000>; - no-map; - }; - - aop_cmd_db_mem: memory@80860000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x80860000 0x0 0x20000>; - no-map; - }; - - aop_config_mem: memory@80880000 { - reg = <0x0 0x80880000 0x0 0x20000>; - no-map; - }; - - tme_crash_dump_mem: memory@808a0000 { - reg = <0x0 0x808a0000 0x0 0x40000>; - no-map; - }; - - tme_log_mem: memory@808e0000 { - reg = <0x0 0x808e0000 0x0 0x4000>; - no-map; - }; - - uefi_log_mem: memory@808e4000 { - reg = <0x0 0x808e4000 0x0 0x10000>; - no-map; - }; - - /* secdata region can be reused by apps */ - smem: memory@80900000 { - compatible = "qcom,smem"; - reg = <0x0 0x80900000 0x0 0x200000>; - hwlocks = <&tcsr_mutex 3>; - no-map; - }; - - cpucp_fw_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x100000>; - no-map; - }; - - cdsp_secure_heap: memory@80c00000 { - reg = <0x0 0x80c00000 0x0 0x4600000>; - no-map; - }; - - camera_mem: memory@85200000 { - reg = <0x0 0x85200000 0x0 0x500000>; - no-map; - }; - - video_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x700000>; - no-map; - }; - - adsp_mem: memory@85e00000 { - reg = <0x0 0x85e00000 0x0 0x2100000>; - no-map; - }; - - slpi_mem: memory@88000000 { - reg = <0x0 0x88000000 0x0 0x1900000>; - no-map; - }; - - cdsp_mem: memory@89900000 { - reg = <0x0 0x89900000 0x0 0x2000000>; - no-map; - }; - - ipa_fw_mem: memory@8b900000 { - reg = <0x0 0x8b900000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@8b910000 { - reg = <0x0 0x8b910000 0x0 0xa000>; - no-map; - }; - - gpu_micro_code_mem: memory@8b91a000 { - reg = <0x0 0x8b91a000 0x0 0x2000>; - no-map; - }; - - spss_region_mem: memory@8ba00000 { - reg = <0x0 0x8ba00000 0x0 0x180000>; - no-map; - }; - - /* First part of the "SPU secure shared memory" region */ - spu_tz_shared_mem: memory@8bb80000 { - reg = <0x0 0x8bb80000 0x0 0x60000>; - no-map; - }; - - /* Second part of the "SPU secure shared memory" region */ - spu_modem_shared_mem: memory@8bbe0000 { - reg = <0x0 0x8bbe0000 0x0 0x20000>; - no-map; - }; - - mpss_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x13200000>; - no-map; - }; - - cvp_mem: memory@9ee00000 { - reg = <0x0 0x9ee00000 0x0 0x700000>; - no-map; - }; - - rmtfs_mem: memory@9fd00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x9fd00000 0x0 0x280000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - global_sync_mem: memory@a6f00000 { - reg = <0x0 0xa6f00000 0x0 0x100000>; - no-map; - }; - - /* uefi region can be reused by APPS */ - - /* Linux kernel image is loaded at 0xa0000000 */ - - oem_vm_mem: memory@bb000000 { - reg = <0x0 0xbb000000 0x0 0x5000000>; - no-map; - }; - - mte_mem: memory@c0000000 { - reg = <0x0 0xc0000000 0x0 0x20000000>; - no-map; - }; - - qheebsp_reserved_mem: memory@e0000000 { - reg = <0x0 0xe0000000 0x0 0x600000>; - no-map; - }; - - cpusys_vm_mem: memory@e0600000 { - reg = <0x0 0xe0600000 0x0 0x400000>; - no-map; - }; - - hyp_reserved_mem: memory@e0a00000 { - reg = <0x0 0xe0a00000 0x0 0x100000>; - no-map; - }; - - trust_ui_vm_mem: memory@e0b00000 { - reg = <0x0 0xe0b00000 0x0 0x4af3000>; - no-map; - }; - - trust_ui_vm_qrtr: memory@e55f3000 { - reg = <0x0 0xe55f3000 0x0 0x9000>; - no-map; - }; - - trust_ui_vm_vblk0_ring: memory@e55fc000 { - reg = <0x0 0xe55fc000 0x0 0x4000>; - no-map; - }; - - trust_ui_vm_swiotlb: memory@e5600000 { - reg = <0x0 0xe5600000 0x0 0x100000>; - no-map; - }; - - tz_stat_mem: memory@e8800000 { - reg = <0x0 0xe8800000 0x0 0x100000>; - no-map; - }; - - tags_mem: memory@e8900000 { - reg = <0x0 0xe8900000 0x0 0x1200000>; - no-map; - }; - - qtee_mem: memory@e9b00000 { - reg = <0x0 0xe9b00000 0x0 0x500000>; - no-map; - }; - - trusted_apps_mem: memory@ea000000 { - reg = <0x0 0xea000000 0x0 0x3900000>; - no-map; - }; - - trusted_apps_ext_mem: memory@ed900000 { - reg = <0x0 0xed900000 0x0 0x3b00000>; - no-map; - }; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - smp2p_cdsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_cdsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - smp2p_modem_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_modem_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8450"; - reg = <0x0 0x00100000 0x0 0x1f4200>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&pcie0_lane>, - <&pcie1_lane>, - <&sleep_clk>; - clock-names = "bi_tcxo", - "pcie_0_pipe_clk", - "pcie_1_pipe_clk", - "sleep_clk"; - }; - - qupv3_id_2: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - uart20: serial@894000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart20_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qupv3_id_0: geniqup@9c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x009c0000 0x0 0x2000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c6: i2c@998000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00998000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_data_clk>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart7: serial@99c000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x0099c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_data_clk>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c14: i2c@a98000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_data_clk>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - pcie0: pci@1c00000 { - compatible = "qcom,pcie-sm8450-pcie0"; - reg = <0 0x01c00000 0 0x3000>, - <0 0x60000000 0 0xf1d>, - <0 0x60000f20 0 0xa8>, - <0 0x60001000 0 0x1000>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, - <&pcie0_lane>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; - clock-names = "pipe", - "pipe_mux", - "phy_pipe", - "ref", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ddrss_sf_tbu", - "aggre0", - "aggre1"; - - iommus = <&apps_smmu 0x1c00 0x7f>; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; - - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_0_GDSC>; - power-domain-names = "gdsc"; - - phys = <&pcie0_lane>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; - - interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "pci"; - - status = "disabled"; - }; - - pcie0_phy: phy@1c06000 { - compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; - reg = <0 0x01c06000 0 0x200>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_CLKREF_EN>, - <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie0_lane: lanes@1c06200 { - reg = <0 0x1c06e00 0 0x200>, /* tx */ - <0 0x1c07000 0 0x200>, /* rx */ - <0 0x1c06200 0 0x200>, /* pcs */ - <0 0x1c06600 0 0x200>; /* pcs_pcie */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; - }; - - pcie1: pci@1c08000 { - compatible = "qcom,pcie-sm8450-pcie1"; - reg = <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <2>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_lane>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; - clock-names = "pipe", - "pipe_mux", - "phy_pipe", - "ref", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ddrss_sf_tbu", - "aggre1"; - - iommus = <&apps_smmu 0x1c80 0x7f>; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; - - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_1_GDSC>; - power-domain-names = "gdsc"; - - phys = <&pcie1_lane>; - phy-names = "pciephy"; - - perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; - - interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "pci"; - - status = "disabled"; - }; - - pcie1_phy: phy@1c0f000 { - compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; - reg = <0 0x01c0f000 0 0x200>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_CLKREF_EN>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie1_lane: lanes@1c0e000 { - reg = <0 0x1c0e000 0 0x200>, /* tx */ - <0 0x1c0e200 0 0x300>, /* rx */ - <0 0x1c0f200 0 0x200>, /* pcs */ - <0 0x1c0e800 0 0x200>, /* tx */ - <0 0x1c0ea00 0 0x300>, /* rx */ - <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8450-config-noc"; - reg = <0 0x01500000 0 0x1c000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1680000 { - compatible = "qcom,sm8450-system-noc"; - reg = <0 0x01680000 0 0x1e200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - pcie_noc: interconnect@16c0000 { - compatible = "qcom,sm8450-pcie-anoc"; - reg = <0 0x016c0000 0 0xe280>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8450-aggre1-noc"; - reg = <0 0x016e0000 0 0x1c080>; - #interconnect-cells = <2>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8450-aggre2-noc"; - reg = <0 0x01700000 0 0x31080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&rpmhcc RPMH_IPA_CLK>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8450-mmss-noc"; - reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x01f40000 0x0 0x40000>; - #hwlock-cells = <1>; - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8450-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8450-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8450-slpi-pas"; - reg = <0 0x02400000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "slpi"; - qcom,remote-pid = <3>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0541 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0542 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0543 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - - remoteproc_adsp: remoteproc@30000000 { - compatible = "qcom,sm8450-adsp-pas"; - reg = <0 0x030000000 0 0x100>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - remoteproc_adsp_glink: glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <2>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1803 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1804 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1805 0x0>; - }; - }; - }; - }; - - remoteproc_cdsp: remoteproc@32300000 { - compatible = "qcom,sm8450-cdsp-pas"; - reg = <0 0x032300000 0 0x1400000>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_CX>, - <&rpmhpd SM8450_MXC>; - power-domain-names = "cx", "mxc"; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_cdsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "cdsp"; - qcom,remote-pid = <5>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x2161 0x0400>, - <&apps_smmu 0x1021 0x1420>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2162 0x0400>, - <&apps_smmu 0x1022 0x1420>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x2163 0x0400>, - <&apps_smmu 0x1023 0x1420>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x2164 0x0400>, - <&apps_smmu 0x1024 0x1420>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x2165 0x0400>, - <&apps_smmu 0x1025 0x1420>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x2166 0x0400>, - <&apps_smmu 0x1026 0x1420>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x2167 0x0400>, - <&apps_smmu 0x1027 0x1420>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x2168 0x0400>, - <&apps_smmu 0x1028 0x1420>; - }; - - /* note: secure cb9 in downstream */ - }; - }; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8450-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 0>, - <&rpmhpd 12>; - power-domain-names = "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_modem_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - }; - }; - - cci0: cci@ac15000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac15000 0 0x1000>; - interrupts = ; - power-domains = <&camcc TITAN_TOP_GDSC>; - - clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_0_CLK>, - <&camcc CAM_CC_CCI_0_CLK_SRC>; - clock-names = "camnoc_axi", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - pinctrl-0 = <&cci0_default &cci1_default>; - pinctrl-1 = <&cci0_sleep &cci1_sleep>; - pinctrl-names = "default", "sleep"; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - cci0_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci0_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cci1: cci@ac16000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac16000 0 0x1000>; - interrupts = ; - power-domains = <&camcc TITAN_TOP_GDSC>; - - clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_1_CLK>, - <&camcc CAM_CC_CCI_1_CLK_SRC>; - clock-names = "camnoc_axi", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - pinctrl-0 = <&cci2_default &cci2_default>; - pinctrl-1 = <&cci3_sleep &cci3_sleep>; - pinctrl-names = "default", "sleep"; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - cci1_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci1_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - camcc: clock-controller@ade0000 { - compatible = "qcom,sm8450-camcc"; - reg = <0 0x0ade0000 0 0x20000>; - status = "disabled"; - clocks = <&gcc GCC_CAMERA_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - clock-names = "iface", - "bi_tcxo", - "bi_tcxo_ao", - "sleep_clk"; - power-domains = <&rpmhpd SM8450_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8450-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; - qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, - <94 609 31>, <125 63 1>, <126 716 12>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1000>, /* TM */ - <0 0x0c222000 0 0x1000>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1000>, /* TM */ - <0 0x0c223000 0 0x1000>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; - reg = <0 0x0c300000 0 0x400>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - }; - - spmi_bus: spmi@c42d000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c400000 0x0 0x00003000>, - <0x0 0x0c500000 0x0 0x00400000>, - <0x0 0x0c440000 0x0 0x00080000>, - <0x0 0x0c4c0000 0x0 0x00010000>, - <0x0 0x0c42d000 0x0 0x00010000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - qcom,bus-id = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - ipcc: mailbox@ed18000 { - compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; - reg = <0 0x0ed18000 0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8450-tlmm"; - reg = <0 0x0f100000 0 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 211>; - wakeup-parent = <&pdc>; - -<<<<<<< - cam_sensor_mclk0_default: cam-sensor-mclk0-default-state { - pins = "gpio100"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk0_sleep: cam-sensor-mclk0-sleep-state { - pins = "gpio100"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk1_default: cam-sensor-mclk1-default-state { - pins = "gpio101"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk1_sleep: cam-sensor-mclk1-sleep-state { - pins = "gpio101"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk2_default: cam-sensor-mclk2-default-state { - pins = "gpio102"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk2_sleep: cam-sensor-mclk2-sleep-state { - pins = "gpio102"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk3_default: cam-sensor-mclk3-default-state { - pins = "gpio103"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk3_sleep: cam-sensor-mclk3-sleep-state { - pins = "gpio103"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk4_default: cam-sensor-mclk4-default-state { - pins = "gpio104"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk4_sleep: cam-sensor-mclk4-sleep-state { - pins = "gpio104"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk5_default: cam-sensor-mclk5-default-state { - pins = "gpio105"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk5_sleep: cam-sensor-mclk5-sleep-state { - pins = "gpio105"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk6_default: cam-sensor-mclk6-default-state { - pins = "gpio106"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk6_sleep: cam-sensor-mclk6-sleep-state { - pins = "gpio106"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cci0_default: cci0-default-state { - /* SDA, SCL */ - pins = "gpio110", "gpio111"; - function = "cci_i2c"; -======= - pcie0_default_state: pcie0-default-state { - perst { - pins = "gpio94"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq { - pins = "gpio95"; - function = "pcie0_clkreqn"; - drive-strength = <2>; - bias-pull-up; - }; - - wake { - pins = "gpio96"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_default_state: pcie1-default-state { - perst { - pins = "gpio97"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq { - pins = "gpio98"; - function = "pcie1_clkreqn"; - drive-strength = <2>; - bias-pull-up; - }; - - wake { - pins = "gpio99"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - qup_i2c6_data_clk: qup-i2c6-data-clk { - pins = "gpio20", "gpio21"; - function = "qup6"; ->>>>>>> - drive-strength = <2>; - bias-pull-up; - }; - -<<<<<<< -======= - cci0_sleep: cci0-sleep-state { - /* SDA, SCL */ - pins = "gpio110", "gpio111"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci1_default: cci1-default-state { - /* SDA, SCL */ - pins = "gpio112", "gpio113"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci1_sleep: cci1-sleep-state { - /* SDA, SCL */ - pins = "gpio112", "gpio113"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci2_default: cci2-default-state { - /* SDA, SCL */ - pins = "gpio114", "gpio115"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci2_sleep: cci2-sleep-state { - /* SDA, SCL */ - pins = "gpio114", "gpio115"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci3_default: cci3-default-state { - /* SDA, SCL */ - pins = "gpio208", "gpio209"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci3_sleep: cci3-sleep-state { - /* SDA, SCL */ - pins = "gpio208", "gpio209"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - ->>>>>>> - qup_i2c13_data_clk: qup-i2c13-data-clk { - pins = "gpio48", "gpio49"; - function = "qup13"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c14_data_clk: qup-i2c14-data-clk { - pins = "gpio52", "gpio53"; - function = "qup14"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_uart7_rx: qup-uart7-rx { - pins = "gpio26"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart7_tx: qup-uart7-tx { - pins = "gpio27"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart20_default: qup-uart20-default { - mux { - pins = "gpio76", "gpio77", - "gpio78", "gpio79"; - function = "qup20"; - }; - }; - - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - intc: interrupt-controller@17100000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x40000>; - reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ - <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ - interrupts = ; - - gic_its: msi-controller@17140000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x17140000 0x0 0x20000>; - }; - }; - - timer@17420000 { - compatible = "arm,armv7-timer-mem"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - reg = <0x0 0x17420000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17421000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17421000 0x0 0x1000>, - <0x0 0x17422000 0x0 0x1000>; - }; - - frame@17423000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17423000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17425000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17425000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17427000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17427000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17429000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17429000 0x0 0x1000>; - status = "disabled"; - }; - - frame@1742b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x1742b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@1742d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x1742d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@17a00000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x17a00000 0x0 0x10000>, - <0x0 0x17a10000 0x0 0x10000>, - <0x0 0x17a20000 0x0 0x10000>, - <0x0 0x17a30000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , , - , ; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sm8450-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8450-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - }; - - cpufreq_hw: cpufreq@17d91000 { - compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0 0x17d91000 0 0x1000>, - <0 0x17d92000 0 0x1000>, - <0 0x17d93000 0 0x1000>; - reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - interrupts = , - , - ; - interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; - #freq-domain-cells = <1>; - }; - - gem_noc: interconnect@19100000 { - compatible = "qcom,sm8450-gem-noc"; - reg = <0 0x19100000 0 0xbb800>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@19200000 { - compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8450-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0xe0 0x0>; - - interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; - interconnect-names = "ufs-ddr", "cpu-ufs"; - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>; - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8450-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0xe10>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", "ref_aux", "qref"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, - <&gcc GCC_UFS_0_CLKREF_EN>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - #clock-cells = <0>; - }; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_0_CLKREF_EN>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, - <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - nsp_noc: interconnect@320c0000 { - compatible = "qcom,sm8450-nsp-noc"; - reg = <0 0x320c0000 0 0x10000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - lpass_ag_noc: interconnect@3c40000 { - compatible = "qcom,sm8450-lpass-ag-noc"; - reg = <0 0x3c40000 0 0x17200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - }; - - thermal-zones { - aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 1>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 2>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 3>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 5>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 6>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 12>; - - trips { - cpu7_middle_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_middle_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_middle_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_middle_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_middle_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 13>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-top-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens0 14>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu0_tj_cfg: tj_cfg { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - gpu-bottom-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens0 15>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu1_tj_cfg: tj_cfg { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cdsp0-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_0_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cdsp1-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 6>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_1_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cdsp2-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_2_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - ddr_config0: ddr0-config { - temperature = <90000>; - hysteresis = <5000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss0_config0: mdmss0-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss0_config1: mdmss0-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss1_config0: mdmss1-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss1_config1: mdmss1-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 12>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss2_config0: mdmss2-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss2_config1: mdmss2-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 13>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss3_config0: mdmss3-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss3_config1: mdmss3-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 14>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 15>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <19200000>; - }; -}; diff --git a/rr-cache/8c2b8bf507854aaf7c7a64fde16df892d508760f/preimage.1 b/rr-cache/8c2b8bf507854aaf7c7a64fde16df892d508760f/preimage.1 deleted file mode 100644 index 29042c4..0000000 --- a/rr-cache/8c2b8bf507854aaf7c7a64fde16df892d508760f/preimage.1 +++ /dev/null @@ -1,7545 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/******************************************************************************* - This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. - ST Ethernet IPs are built around a Synopsys IP Core. - - Copyright(C) 2007-2011 STMicroelectronics Ltd - - - Author: Giuseppe Cavallaro - - Documentation available at: - http://www.stlinux.com - Support available at: - https://bugzilla.stlinux.com/ -*******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_DEBUG_FS -#include -#include -#endif /* CONFIG_DEBUG_FS */ -#include -#include -#include -#include -#include -#include -#include "stmmac_ptp.h" -#include "stmmac.h" -#include "stmmac_xdp.h" -#include -#include -#include "dwmac1000.h" -#include "dwxgmac2.h" -#include "hwif.h" - -/* As long as the interface is active, we keep the timestamping counter enabled - * with fine resolution and binary rollover. This avoid non-monotonic behavior - * (clock jumps) when changing timestamping settings at runtime. - */ -#define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ - PTP_TCR_TSCTRLSSR) - -#define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) -#define TSO_MAX_BUFF_SIZE (SZ_16K - 1) - -/* Module parameters */ -#define TX_TIMEO 5000 -static int watchdog = TX_TIMEO; -module_param(watchdog, int, 0644); -MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); - -static int debug = -1; -module_param(debug, int, 0644); -MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); - -static int phyaddr = -1; -module_param(phyaddr, int, 0444); -MODULE_PARM_DESC(phyaddr, "Physical device address"); - -#define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4) -#define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4) - -/* Limit to make sure XDP TX and slow path can coexist */ -#define STMMAC_XSK_TX_BUDGET_MAX 256 -#define STMMAC_TX_XSK_AVAIL 16 -#define STMMAC_RX_FILL_BATCH 16 - -#define STMMAC_XDP_PASS 0 -#define STMMAC_XDP_CONSUMED BIT(0) -#define STMMAC_XDP_TX BIT(1) -#define STMMAC_XDP_REDIRECT BIT(2) - -static int flow_ctrl = FLOW_AUTO; -module_param(flow_ctrl, int, 0644); -MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); - -static int pause = PAUSE_TIME; -module_param(pause, int, 0644); -MODULE_PARM_DESC(pause, "Flow Control Pause Time"); - -#define TC_DEFAULT 64 -static int tc = TC_DEFAULT; -module_param(tc, int, 0644); -MODULE_PARM_DESC(tc, "DMA threshold control value"); - -#define DEFAULT_BUFSIZE 1536 -static int buf_sz = DEFAULT_BUFSIZE; -module_param(buf_sz, int, 0644); -MODULE_PARM_DESC(buf_sz, "DMA buffer size"); - -#define STMMAC_RX_COPYBREAK 256 - -static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | - NETIF_MSG_LINK | NETIF_MSG_IFUP | - NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); - -#define STMMAC_DEFAULT_LPI_TIMER 1000 -static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; -module_param(eee_timer, int, 0644); -MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); -#define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) - -/* By default the driver will use the ring mode to manage tx and rx descriptors, - * but allow user to force to use the chain instead of the ring - */ -static unsigned int chain_mode; -module_param(chain_mode, int, 0444); -MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); - -static irqreturn_t stmmac_interrupt(int irq, void *dev_id); -/* For MSI interrupts handling */ -static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); -static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); -static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); -static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); -static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); -static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); -static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, - u32 rxmode, u32 chan); - -#ifdef CONFIG_DEBUG_FS -static const struct net_device_ops stmmac_netdev_ops; -static void stmmac_init_fs(struct net_device *dev); -static void stmmac_exit_fs(struct net_device *dev); -#endif - -#define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) - -int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) -{ - int ret = 0; - - if (enabled) { - ret = clk_prepare_enable(priv->plat->stmmac_clk); - if (ret) - return ret; - ret = clk_prepare_enable(priv->plat->pclk); - if (ret) { - clk_disable_unprepare(priv->plat->stmmac_clk); - return ret; - } - if (priv->plat->clks_config) { - ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); - if (ret) { - clk_disable_unprepare(priv->plat->stmmac_clk); - clk_disable_unprepare(priv->plat->pclk); - return ret; - } - } - } else { - clk_disable_unprepare(priv->plat->stmmac_clk); - clk_disable_unprepare(priv->plat->pclk); - if (priv->plat->clks_config) - priv->plat->clks_config(priv->plat->bsp_priv, enabled); - } - - return ret; -} -EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); - -/** - * stmmac_verify_args - verify the driver parameters. - * Description: it checks the driver parameters and set a default in case of - * errors. - */ -static void stmmac_verify_args(void) -{ - if (unlikely(watchdog < 0)) - watchdog = TX_TIMEO; - if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) - buf_sz = DEFAULT_BUFSIZE; - if (unlikely(flow_ctrl > 1)) - flow_ctrl = FLOW_AUTO; - else if (likely(flow_ctrl < 0)) - flow_ctrl = FLOW_OFF; - if (unlikely((pause < 0) || (pause > 0xffff))) - pause = PAUSE_TIME; - if (eee_timer < 0) - eee_timer = STMMAC_DEFAULT_LPI_TIMER; -} - -static void __stmmac_disable_all_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_cnt = priv->plat->rx_queues_to_use; - u32 tx_queues_cnt = priv->plat->tx_queues_to_use; - u32 maxq = max(rx_queues_cnt, tx_queues_cnt); - u32 queue; - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - if (stmmac_xdp_is_enabled(priv) && - test_bit(queue, priv->af_xdp_zc_qps)) { - napi_disable(&ch->rxtx_napi); - continue; - } - - if (queue < rx_queues_cnt) - napi_disable(&ch->rx_napi); - if (queue < tx_queues_cnt) - napi_disable(&ch->tx_napi); - } -} - -/** - * stmmac_disable_all_queues - Disable all queues - * @priv: driver private structure - */ -static void stmmac_disable_all_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_cnt = priv->plat->rx_queues_to_use; - struct stmmac_rx_queue *rx_q; - u32 queue; - - /* synchronize_rcu() needed for pending XDP buffers to drain */ - for (queue = 0; queue < rx_queues_cnt; queue++) { - rx_q = &priv->rx_queue[queue]; - if (rx_q->xsk_pool) { - synchronize_rcu(); - break; - } - } - - __stmmac_disable_all_queues(priv); -} - -/** - * stmmac_enable_all_queues - Enable all queues - * @priv: driver private structure - */ -static void stmmac_enable_all_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_cnt = priv->plat->rx_queues_to_use; - u32 tx_queues_cnt = priv->plat->tx_queues_to_use; - u32 maxq = max(rx_queues_cnt, tx_queues_cnt); - u32 queue; - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - if (stmmac_xdp_is_enabled(priv) && - test_bit(queue, priv->af_xdp_zc_qps)) { - napi_enable(&ch->rxtx_napi); - continue; - } - - if (queue < rx_queues_cnt) - napi_enable(&ch->rx_napi); - if (queue < tx_queues_cnt) - napi_enable(&ch->tx_napi); - } -} - -static void stmmac_service_event_schedule(struct stmmac_priv *priv) -{ - if (!test_bit(STMMAC_DOWN, &priv->state) && - !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) - queue_work(priv->wq, &priv->service_task); -} - -static void stmmac_global_err(struct stmmac_priv *priv) -{ - netif_carrier_off(priv->dev); - set_bit(STMMAC_RESET_REQUESTED, &priv->state); - stmmac_service_event_schedule(priv); -} - -/** - * stmmac_clk_csr_set - dynamically set the MDC clock - * @priv: driver private structure - * Description: this is to dynamically set the MDC clock according to the csr - * clock input. - * Note: - * If a specific clk_csr value is passed from the platform - * this means that the CSR Clock Range selection cannot be - * changed at run-time and it is fixed (as reported in the driver - * documentation). Viceversa the driver will try to set the MDC - * clock dynamically according to the actual clock input. - */ -static void stmmac_clk_csr_set(struct stmmac_priv *priv) -{ - u32 clk_rate; - - clk_rate = clk_get_rate(priv->plat->stmmac_clk); - - /* Platform provided default clk_csr would be assumed valid - * for all other cases except for the below mentioned ones. - * For values higher than the IEEE 802.3 specified frequency - * we can not estimate the proper divider as it is not known - * the frequency of clk_csr_i. So we do not change the default - * divider. - */ - if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { - if (clk_rate < CSR_F_35M) - priv->clk_csr = STMMAC_CSR_20_35M; - else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) - priv->clk_csr = STMMAC_CSR_35_60M; - else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) - priv->clk_csr = STMMAC_CSR_60_100M; - else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) - priv->clk_csr = STMMAC_CSR_100_150M; - else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) - priv->clk_csr = STMMAC_CSR_150_250M; - else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) - priv->clk_csr = STMMAC_CSR_250_300M; - } - - if (priv->plat->has_sun8i) { - if (clk_rate > 160000000) - priv->clk_csr = 0x03; - else if (clk_rate > 80000000) - priv->clk_csr = 0x02; - else if (clk_rate > 40000000) - priv->clk_csr = 0x01; - else - priv->clk_csr = 0; - } - - if (priv->plat->has_xgmac) { - if (clk_rate > 400000000) - priv->clk_csr = 0x5; - else if (clk_rate > 350000000) - priv->clk_csr = 0x4; - else if (clk_rate > 300000000) - priv->clk_csr = 0x3; - else if (clk_rate > 250000000) - priv->clk_csr = 0x2; - else if (clk_rate > 150000000) - priv->clk_csr = 0x1; - else - priv->clk_csr = 0x0; - } -} - -static void print_pkt(unsigned char *buf, int len) -{ - pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); - print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); -} - -static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - u32 avail; - - if (tx_q->dirty_tx > tx_q->cur_tx) - avail = tx_q->dirty_tx - tx_q->cur_tx - 1; - else - avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; - - return avail; -} - -/** - * stmmac_rx_dirty - Get RX queue dirty - * @priv: driver private structure - * @queue: RX queue index - */ -static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - u32 dirty; - - if (rx_q->dirty_rx <= rx_q->cur_rx) - dirty = rx_q->cur_rx - rx_q->dirty_rx; - else - dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; - - return dirty; -} - -static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) -{ - int tx_lpi_timer; - - /* Clear/set the SW EEE timer flag based on LPI ET enablement */ - priv->eee_sw_timer_en = en ? 0 : 1; - tx_lpi_timer = en ? priv->tx_lpi_timer : 0; - stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); -} - -/** - * stmmac_enable_eee_mode - check and enter in LPI mode - * @priv: driver private structure - * Description: this function is to verify and enter in LPI mode in case of - * EEE. - */ -static int stmmac_enable_eee_mode(struct stmmac_priv *priv) -{ - u32 tx_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - /* check if all TX queues have the work finished */ - for (queue = 0; queue < tx_cnt; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - if (tx_q->dirty_tx != tx_q->cur_tx) - return -EBUSY; /* still unfinished work */ - } - - /* Check and enter in LPI mode */ - if (!priv->tx_path_in_lpi_mode) - stmmac_set_eee_mode(priv, priv->hw, - priv->plat->en_tx_lpi_clockgating); - return 0; -} - -/** - * stmmac_disable_eee_mode - disable and exit from LPI mode - * @priv: driver private structure - * Description: this function is to exit and disable EEE in case of - * LPI state is true. This is called by the xmit. - */ -void stmmac_disable_eee_mode(struct stmmac_priv *priv) -{ - if (!priv->eee_sw_timer_en) { - stmmac_lpi_entry_timer_config(priv, 0); - return; - } - - stmmac_reset_eee_mode(priv, priv->hw); - del_timer_sync(&priv->eee_ctrl_timer); - priv->tx_path_in_lpi_mode = false; -} - -/** - * stmmac_eee_ctrl_timer - EEE TX SW timer. - * @t: timer_list struct containing private info - * Description: - * if there is no data transfer and if we are not in LPI state, - * then MAC Transmitter can be moved to LPI state. - */ -static void stmmac_eee_ctrl_timer(struct timer_list *t) -{ - struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); - - if (stmmac_enable_eee_mode(priv)) - mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); -} - -/** - * stmmac_eee_init - init EEE - * @priv: driver private structure - * Description: - * if the GMAC supports the EEE (from the HW cap reg) and the phy device - * can also manage EEE, this function enable the LPI state and start related - * timer. - */ -bool stmmac_eee_init(struct stmmac_priv *priv) -{ - int eee_tw_timer = priv->eee_tw_timer; - - /* Using PCS we cannot dial with the phy registers at this stage - * so we do not support extra feature like EEE. - */ - if (priv->hw->pcs == STMMAC_PCS_TBI || - priv->hw->pcs == STMMAC_PCS_RTBI) - return false; - - /* Check if MAC core supports the EEE feature. */ - if (!priv->dma_cap.eee) - return false; - - mutex_lock(&priv->lock); - - /* Check if it needs to be deactivated */ - if (!priv->eee_active) { - if (priv->eee_enabled) { - netdev_dbg(priv->dev, "disable EEE\n"); - stmmac_lpi_entry_timer_config(priv, 0); - del_timer_sync(&priv->eee_ctrl_timer); - stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); - if (priv->hw->xpcs) - xpcs_config_eee(priv->hw->xpcs, - priv->plat->mult_fact_100ns, - false); - } - mutex_unlock(&priv->lock); - return false; - } - - if (priv->eee_active && !priv->eee_enabled) { - timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); - stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, - eee_tw_timer); - if (priv->hw->xpcs) - xpcs_config_eee(priv->hw->xpcs, - priv->plat->mult_fact_100ns, - true); - } - - if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { - del_timer_sync(&priv->eee_ctrl_timer); - priv->tx_path_in_lpi_mode = false; - stmmac_lpi_entry_timer_config(priv, 1); - } else { - stmmac_lpi_entry_timer_config(priv, 0); - mod_timer(&priv->eee_ctrl_timer, - STMMAC_LPI_T(priv->tx_lpi_timer)); - } - - mutex_unlock(&priv->lock); - netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); - return true; -} - -/* stmmac_get_tx_hwtstamp - get HW TX timestamps - * @priv: driver private structure - * @p : descriptor pointer - * @skb : the socket buffer - * Description : - * This function will read timestamp from the descriptor & pass it to stack. - * and also perform some sanity checks. - */ -static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, - struct dma_desc *p, struct sk_buff *skb) -{ - struct skb_shared_hwtstamps shhwtstamp; - bool found = false; - u64 ns = 0; - - if (!priv->hwts_tx_en) - return; - - /* exit if skb doesn't support hw tstamp */ - if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) - return; - - /* check tx tstamp status */ - if (stmmac_get_tx_timestamp_status(priv, p)) { - stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); - found = true; - } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { - found = true; - } - - if (found) { - ns -= priv->plat->cdc_error_adj; - - memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); - shhwtstamp.hwtstamp = ns_to_ktime(ns); - - netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); - /* pass tstamp to stack */ - skb_tstamp_tx(skb, &shhwtstamp); - } -} - -/* stmmac_get_rx_hwtstamp - get HW RX timestamps - * @priv: driver private structure - * @p : descriptor pointer - * @np : next descriptor pointer - * @skb : the socket buffer - * Description : - * This function will read received packet's timestamp from the descriptor - * and pass it to stack. It also perform some sanity checks. - */ -static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, - struct dma_desc *np, struct sk_buff *skb) -{ - struct skb_shared_hwtstamps *shhwtstamp = NULL; - struct dma_desc *desc = p; - u64 ns = 0; - - if (!priv->hwts_rx_en) - return; - /* For GMAC4, the valid timestamp is from CTX next desc. */ - if (priv->plat->has_gmac4 || priv->plat->has_xgmac) - desc = np; - - /* Check if timestamp is available */ - if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { - stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); - - ns -= priv->plat->cdc_error_adj; - - netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); - shhwtstamp = skb_hwtstamps(skb); - memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); - shhwtstamp->hwtstamp = ns_to_ktime(ns); - } else { - netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); - } -} - -/** - * stmmac_hwtstamp_set - control hardware timestamping. - * @dev: device pointer. - * @ifr: An IOCTL specific structure, that can contain a pointer to - * a proprietary structure used to pass information to the driver. - * Description: - * This function configures the MAC to enable/disable both outgoing(TX) - * and incoming(RX) packets time stamping based on user input. - * Return Value: - * 0 on success and an appropriate -ve integer on failure. - */ -static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct hwtstamp_config config; - u32 ptp_v2 = 0; - u32 tstamp_all = 0; - u32 ptp_over_ipv4_udp = 0; - u32 ptp_over_ipv6_udp = 0; - u32 ptp_over_ethernet = 0; - u32 snap_type_sel = 0; - u32 ts_master_en = 0; - u32 ts_event_en = 0; - - if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { - netdev_alert(priv->dev, "No support for HW time stamping\n"); - priv->hwts_tx_en = 0; - priv->hwts_rx_en = 0; - - return -EOPNOTSUPP; - } - - if (copy_from_user(&config, ifr->ifr_data, - sizeof(config))) - return -EFAULT; - - netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", - __func__, config.flags, config.tx_type, config.rx_filter); - - if (config.tx_type != HWTSTAMP_TX_OFF && - config.tx_type != HWTSTAMP_TX_ON) - return -ERANGE; - - if (priv->adv_ts) { - switch (config.rx_filter) { - case HWTSTAMP_FILTER_NONE: - /* time stamp no incoming packet at all */ - config.rx_filter = HWTSTAMP_FILTER_NONE; - break; - - case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: - /* PTP v1, UDP, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; - /* 'xmac' hardware can support Sync, Pdelay_Req and - * Pdelay_resp by setting bit14 and bits17/16 to 01 - * This leaves Delay_Req timestamps out. - * Enable all events *and* general purpose message - * timestamping - */ - snap_type_sel = PTP_TCR_SNAPTYPSEL_1; - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: - /* PTP v1, UDP, Sync packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; - /* take time stamp for SYNC messages only */ - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: - /* PTP v1, UDP, Delay_req packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; - /* take time stamp for Delay_Req messages only */ - ts_master_en = PTP_TCR_TSMSTRENA; - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: - /* PTP v2, UDP, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for all event messages */ - snap_type_sel = PTP_TCR_SNAPTYPSEL_1; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: - /* PTP v2, UDP, Sync packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for SYNC messages only */ - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: - /* PTP v2, UDP, Delay_req packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for Delay_Req messages only */ - ts_master_en = PTP_TCR_TSMSTRENA; - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_EVENT: - /* PTP v2/802.AS1 any layer, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; - ptp_v2 = PTP_TCR_TSVER2ENA; - snap_type_sel = PTP_TCR_SNAPTYPSEL_1; - if (priv->synopsys_id < DWMAC_CORE_4_10) - ts_event_en = PTP_TCR_TSEVNTENA; - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - ptp_over_ethernet = PTP_TCR_TSIPENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_SYNC: - /* PTP v2/802.AS1, any layer, Sync packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for SYNC messages only */ - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - ptp_over_ethernet = PTP_TCR_TSIPENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: - /* PTP v2/802.AS1, any layer, Delay_req packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for Delay_Req messages only */ - ts_master_en = PTP_TCR_TSMSTRENA; - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - ptp_over_ethernet = PTP_TCR_TSIPENA; - break; - - case HWTSTAMP_FILTER_NTP_ALL: - case HWTSTAMP_FILTER_ALL: - /* time stamp any incoming packet */ - config.rx_filter = HWTSTAMP_FILTER_ALL; - tstamp_all = PTP_TCR_TSENALL; - break; - - default: - return -ERANGE; - } - } else { - switch (config.rx_filter) { - case HWTSTAMP_FILTER_NONE: - config.rx_filter = HWTSTAMP_FILTER_NONE; - break; - default: - /* PTP v1, UDP, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; - break; - } - } - priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); - priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; - - priv->systime_flags = STMMAC_HWTS_ACTIVE; - - if (priv->hwts_tx_en || priv->hwts_rx_en) { - priv->systime_flags |= tstamp_all | ptp_v2 | - ptp_over_ethernet | ptp_over_ipv6_udp | - ptp_over_ipv4_udp | ts_event_en | - ts_master_en | snap_type_sel; - } - - stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); - - memcpy(&priv->tstamp_config, &config, sizeof(config)); - - return copy_to_user(ifr->ifr_data, &config, - sizeof(config)) ? -EFAULT : 0; -} - -/** - * stmmac_hwtstamp_get - read hardware timestamping. - * @dev: device pointer. - * @ifr: An IOCTL specific structure, that can contain a pointer to - * a proprietary structure used to pass information to the driver. - * Description: - * This function obtain the current hardware timestamping settings - * as requested. - */ -static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct hwtstamp_config *config = &priv->tstamp_config; - - if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) - return -EOPNOTSUPP; - - return copy_to_user(ifr->ifr_data, config, - sizeof(*config)) ? -EFAULT : 0; -} - -/** - * stmmac_init_tstamp_counter - init hardware timestamping counter - * @priv: driver private structure - * @systime_flags: timestamping flags - * Description: - * Initialize hardware counter for packet timestamping. - * This is valid as long as the interface is open and not suspended. - * Will be rerun after resuming from suspend, case in which the timestamping - * flags updated by stmmac_hwtstamp_set() also need to be restored. - */ -int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) -{ - bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; - struct timespec64 now; - u32 sec_inc = 0; - u64 temp = 0; - int ret; - - if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) - return -EOPNOTSUPP; - - ret = clk_prepare_enable(priv->plat->clk_ptp_ref); - if (ret < 0) { - netdev_warn(priv->dev, - "failed to enable PTP reference clock: %pe\n", - ERR_PTR(ret)); - return ret; - } - - stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); - priv->systime_flags = systime_flags; - - /* program Sub Second Increment reg */ - stmmac_config_sub_second_increment(priv, priv->ptpaddr, - priv->plat->clk_ptp_rate, - xmac, &sec_inc); - temp = div_u64(1000000000ULL, sec_inc); - - /* Store sub second increment for later use */ - priv->sub_second_inc = sec_inc; - - /* calculate default added value: - * formula is : - * addend = (2^32)/freq_div_ratio; - * where, freq_div_ratio = 1e9ns/sec_inc - */ - temp = (u64)(temp << 32); - priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); - stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); - - /* initialize system time */ - ktime_get_real_ts64(&now); - - /* lower 32 bits of tv_sec are safe until y2106 */ - stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); - - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); - -/** - * stmmac_init_ptp - init PTP - * @priv: driver private structure - * Description: this is to verify if the HW supports the PTPv1 or PTPv2. - * This is done by looking at the HW cap. register. - * This function also registers the ptp driver. - */ -static int stmmac_init_ptp(struct stmmac_priv *priv) -{ - bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; - int ret; - - if (priv->plat->ptp_clk_freq_config) - priv->plat->ptp_clk_freq_config(priv); - - ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); - if (ret) - return ret; - - priv->adv_ts = 0; - /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ - if (xmac && priv->dma_cap.atime_stamp) - priv->adv_ts = 1; - /* Dwmac 3.x core with extend_desc can support adv_ts */ - else if (priv->extend_desc && priv->dma_cap.atime_stamp) - priv->adv_ts = 1; - - if (priv->dma_cap.time_stamp) - netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); - - if (priv->adv_ts) - netdev_info(priv->dev, - "IEEE 1588-2008 Advanced Timestamp supported\n"); - - priv->hwts_tx_en = 0; - priv->hwts_rx_en = 0; - - return 0; -} - -static void stmmac_release_ptp(struct stmmac_priv *priv) -{ - clk_disable_unprepare(priv->plat->clk_ptp_ref); - stmmac_ptp_unregister(priv); -} - -/** - * stmmac_mac_flow_ctrl - Configure flow control in all queues - * @priv: driver private structure - * @duplex: duplex passed to the next function - * Description: It is used for configuring the flow control in all queues - */ -static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) -{ - u32 tx_cnt = priv->plat->tx_queues_to_use; - - stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, - priv->pause, tx_cnt); -} - -static void stmmac_validate(struct phylink_config *config, - unsigned long *supported, - struct phylink_link_state *state) -{ - struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); - __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - int tx_cnt = priv->plat->tx_queues_to_use; - int max_speed = priv->plat->max_speed; - - phylink_set(mac_supported, 10baseT_Half); - phylink_set(mac_supported, 10baseT_Full); - phylink_set(mac_supported, 100baseT_Half); - phylink_set(mac_supported, 100baseT_Full); - phylink_set(mac_supported, 1000baseT_Half); - phylink_set(mac_supported, 1000baseT_Full); - phylink_set(mac_supported, 1000baseKX_Full); - - phylink_set(mac_supported, Autoneg); - phylink_set(mac_supported, Pause); - phylink_set(mac_supported, Asym_Pause); - phylink_set_port_modes(mac_supported); - - /* Cut down 1G if asked to */ - if ((max_speed > 0) && (max_speed < 1000)) { - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseX_Full); - } else if (priv->plat->has_gmac4) { - if (!max_speed || max_speed >= 2500) { - phylink_set(mac_supported, 2500baseT_Full); - phylink_set(mac_supported, 2500baseX_Full); - } - } else if (priv->plat->has_xgmac) { - if (!max_speed || (max_speed >= 2500)) { - phylink_set(mac_supported, 2500baseT_Full); - phylink_set(mac_supported, 2500baseX_Full); - } - if (!max_speed || (max_speed >= 5000)) { - phylink_set(mac_supported, 5000baseT_Full); - } - if (!max_speed || (max_speed >= 10000)) { - phylink_set(mac_supported, 10000baseSR_Full); - phylink_set(mac_supported, 10000baseLR_Full); - phylink_set(mac_supported, 10000baseER_Full); - phylink_set(mac_supported, 10000baseLRM_Full); - phylink_set(mac_supported, 10000baseT_Full); - phylink_set(mac_supported, 10000baseKX4_Full); - phylink_set(mac_supported, 10000baseKR_Full); - } - if (!max_speed || (max_speed >= 25000)) { - phylink_set(mac_supported, 25000baseCR_Full); - phylink_set(mac_supported, 25000baseKR_Full); - phylink_set(mac_supported, 25000baseSR_Full); - } - if (!max_speed || (max_speed >= 40000)) { - phylink_set(mac_supported, 40000baseKR4_Full); - phylink_set(mac_supported, 40000baseCR4_Full); - phylink_set(mac_supported, 40000baseSR4_Full); - phylink_set(mac_supported, 40000baseLR4_Full); - } - if (!max_speed || (max_speed >= 50000)) { - phylink_set(mac_supported, 50000baseCR2_Full); - phylink_set(mac_supported, 50000baseKR2_Full); - phylink_set(mac_supported, 50000baseSR2_Full); - phylink_set(mac_supported, 50000baseKR_Full); - phylink_set(mac_supported, 50000baseSR_Full); - phylink_set(mac_supported, 50000baseCR_Full); - phylink_set(mac_supported, 50000baseLR_ER_FR_Full); - phylink_set(mac_supported, 50000baseDR_Full); - } - if (!max_speed || (max_speed >= 100000)) { - phylink_set(mac_supported, 100000baseKR4_Full); - phylink_set(mac_supported, 100000baseSR4_Full); - phylink_set(mac_supported, 100000baseCR4_Full); - phylink_set(mac_supported, 100000baseLR4_ER4_Full); - phylink_set(mac_supported, 100000baseKR2_Full); - phylink_set(mac_supported, 100000baseSR2_Full); - phylink_set(mac_supported, 100000baseCR2_Full); - phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); - phylink_set(mac_supported, 100000baseDR2_Full); - } - } - - /* Half-Duplex can only work with single queue */ - if (tx_cnt > 1) { - phylink_set(mask, 10baseT_Half); - phylink_set(mask, 100baseT_Half); - phylink_set(mask, 1000baseT_Half); - } - - linkmode_and(supported, supported, mac_supported); - linkmode_andnot(supported, supported, mask); - - linkmode_and(state->advertising, state->advertising, mac_supported); - linkmode_andnot(state->advertising, state->advertising, mask); - - /* If PCS is supported, check which modes it supports. */ - if (priv->hw->xpcs) - xpcs_validate(priv->hw->xpcs, supported, state); -} - -static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, - const struct phylink_link_state *state) -{ - /* Nothing to do, xpcs_config() handles everything */ -} - -static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) -{ - struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; - enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; - enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; - bool *hs_enable = &fpe_cfg->hs_enable; - - if (is_up && *hs_enable) { - stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); - } else { - *lo_state = FPE_STATE_OFF; - *lp_state = FPE_STATE_OFF; - } -} - -static void stmmac_mac_link_down(struct phylink_config *config, - unsigned int mode, phy_interface_t interface) -{ - struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); - - stmmac_mac_set(priv, priv->ioaddr, false); - priv->eee_active = false; - priv->tx_lpi_enabled = false; - priv->eee_enabled = stmmac_eee_init(priv); - stmmac_set_eee_pls(priv, priv->hw, false); - - if (priv->dma_cap.fpesel) - stmmac_fpe_link_state_handle(priv, false); -} - -static void stmmac_mac_link_up(struct phylink_config *config, - struct phy_device *phy, - unsigned int mode, phy_interface_t interface, - int speed, int duplex, - bool tx_pause, bool rx_pause) -{ - struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); - u32 ctrl; - - ctrl = readl(priv->ioaddr + MAC_CTRL_REG); - ctrl &= ~priv->hw->link.speed_mask; - - if (interface == PHY_INTERFACE_MODE_USXGMII) { - switch (speed) { - case SPEED_10000: - ctrl |= priv->hw->link.xgmii.speed10000; - break; - case SPEED_5000: - ctrl |= priv->hw->link.xgmii.speed5000; - break; - case SPEED_2500: - ctrl |= priv->hw->link.xgmii.speed2500; - break; - default: - return; - } - } else if (interface == PHY_INTERFACE_MODE_XLGMII) { - switch (speed) { - case SPEED_100000: - ctrl |= priv->hw->link.xlgmii.speed100000; - break; - case SPEED_50000: - ctrl |= priv->hw->link.xlgmii.speed50000; - break; - case SPEED_40000: - ctrl |= priv->hw->link.xlgmii.speed40000; - break; - case SPEED_25000: - ctrl |= priv->hw->link.xlgmii.speed25000; - break; - case SPEED_10000: - ctrl |= priv->hw->link.xgmii.speed10000; - break; - case SPEED_2500: - ctrl |= priv->hw->link.speed2500; - break; - case SPEED_1000: - ctrl |= priv->hw->link.speed1000; - break; - default: - return; - } - } else { - switch (speed) { - case SPEED_2500: - ctrl |= priv->hw->link.speed2500; - break; - case SPEED_1000: - ctrl |= priv->hw->link.speed1000; - break; - case SPEED_100: - ctrl |= priv->hw->link.speed100; - break; - case SPEED_10: - ctrl |= priv->hw->link.speed10; - break; - default: - return; - } - } - - priv->speed = speed; - - if (priv->plat->fix_mac_speed) - priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); - - if (!duplex) - ctrl &= ~priv->hw->link.duplex; - else - ctrl |= priv->hw->link.duplex; - - /* Flow Control operation */ - if (tx_pause && rx_pause) - stmmac_mac_flow_ctrl(priv, duplex); - - writel(ctrl, priv->ioaddr + MAC_CTRL_REG); - - stmmac_mac_set(priv, priv->ioaddr, true); - if (phy && priv->dma_cap.eee) { - priv->eee_active = phy_init_eee(phy, 1) >= 0; - priv->eee_enabled = stmmac_eee_init(priv); - priv->tx_lpi_enabled = priv->eee_enabled; - stmmac_set_eee_pls(priv, priv->hw, true); - } - - if (priv->dma_cap.fpesel) - stmmac_fpe_link_state_handle(priv, true); -} - -static const struct phylink_mac_ops stmmac_phylink_mac_ops = { - .validate = stmmac_validate, - .mac_config = stmmac_mac_config, - .mac_link_down = stmmac_mac_link_down, - .mac_link_up = stmmac_mac_link_up, -}; - -/** - * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported - * @priv: driver private structure - * Description: this is to verify if the HW supports the PCS. - * Physical Coding Sublayer (PCS) interface that can be used when the MAC is - * configured for the TBI, RTBI, or SGMII PHY interface. - */ -static void stmmac_check_pcs_mode(struct stmmac_priv *priv) -{ - int interface = priv->plat->interface; - - if (priv->dma_cap.pcs) { - if ((interface == PHY_INTERFACE_MODE_RGMII) || - (interface == PHY_INTERFACE_MODE_RGMII_ID) || - (interface == PHY_INTERFACE_MODE_RGMII_RXID) || - (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { - netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); - priv->hw->pcs = STMMAC_PCS_RGMII; - } else if (interface == PHY_INTERFACE_MODE_SGMII) { - netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); - priv->hw->pcs = STMMAC_PCS_SGMII; - } - } -} - -/** - * stmmac_init_phy - PHY initialization - * @dev: net device structure - * Description: it initializes the driver's PHY state, and attaches the PHY - * to the mac driver. - * Return value: - * 0 on success - */ -static int stmmac_init_phy(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct device_node *node; - int ret; - - node = priv->plat->phylink_node; - - if (node) - ret = phylink_of_phy_connect(priv->phylink, node, 0); - - /* Some DT bindings do not set-up the PHY handle. Let's try to - * manually parse it - */ - if (!node || ret) { - int addr = priv->plat->phy_addr; - struct phy_device *phydev; - - phydev = mdiobus_get_phy(priv->mii, addr); - if (!phydev) { - netdev_err(priv->dev, "no phy at addr %d\n", addr); - return -ENODEV; - } - - ret = phylink_connect_phy(priv->phylink, phydev); - } - - if (!priv->plat->pmt) { - struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; - - phylink_ethtool_get_wol(priv->phylink, &wol); - device_set_wakeup_capable(priv->device, !!wol.supported); - } - - return ret; -} - -static int stmmac_phy_setup(struct stmmac_priv *priv) -{ - struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; - struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); - int mode = priv->plat->phy_interface; - struct phylink *phylink; - - priv->phylink_config.dev = &priv->dev->dev; - priv->phylink_config.type = PHYLINK_NETDEV; - priv->phylink_config.pcs_poll = true; - if (priv->plat->mdio_bus_data) - priv->phylink_config.ovr_an_inband = - mdio_bus_data->xpcs_an_inband; - - if (!fwnode) - fwnode = dev_fwnode(priv->device); - - phylink = phylink_create(&priv->phylink_config, fwnode, - mode, &stmmac_phylink_mac_ops); - if (IS_ERR(phylink)) - return PTR_ERR(phylink); - - if (priv->hw->xpcs) - phylink_set_pcs(phylink, &priv->hw->xpcs->pcs); - - priv->phylink = phylink; - return 0; -} - -static void stmmac_display_rx_rings(struct stmmac_priv *priv) -{ - u32 rx_cnt = priv->plat->rx_queues_to_use; - unsigned int desc_size; - void *head_rx; - u32 queue; - - /* Display RX rings */ - for (queue = 0; queue < rx_cnt; queue++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - pr_info("\tRX Queue %u rings\n", queue); - - if (priv->extend_desc) { - head_rx = (void *)rx_q->dma_erx; - desc_size = sizeof(struct dma_extended_desc); - } else { - head_rx = (void *)rx_q->dma_rx; - desc_size = sizeof(struct dma_desc); - } - - /* Display RX ring */ - stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true, - rx_q->dma_rx_phy, desc_size); - } -} - -static void stmmac_display_tx_rings(struct stmmac_priv *priv) -{ - u32 tx_cnt = priv->plat->tx_queues_to_use; - unsigned int desc_size; - void *head_tx; - u32 queue; - - /* Display TX rings */ - for (queue = 0; queue < tx_cnt; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - pr_info("\tTX Queue %d rings\n", queue); - - if (priv->extend_desc) { - head_tx = (void *)tx_q->dma_etx; - desc_size = sizeof(struct dma_extended_desc); - } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { - head_tx = (void *)tx_q->dma_entx; - desc_size = sizeof(struct dma_edesc); - } else { - head_tx = (void *)tx_q->dma_tx; - desc_size = sizeof(struct dma_desc); - } - - stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false, - tx_q->dma_tx_phy, desc_size); - } -} - -static void stmmac_display_rings(struct stmmac_priv *priv) -{ - /* Display RX ring */ - stmmac_display_rx_rings(priv); - - /* Display TX ring */ - stmmac_display_tx_rings(priv); -} - -static int stmmac_set_bfsize(int mtu, int bufsize) -{ - int ret = bufsize; - - if (mtu >= BUF_SIZE_8KiB) - ret = BUF_SIZE_16KiB; - else if (mtu >= BUF_SIZE_4KiB) - ret = BUF_SIZE_8KiB; - else if (mtu >= BUF_SIZE_2KiB) - ret = BUF_SIZE_4KiB; - else if (mtu > DEFAULT_BUFSIZE) - ret = BUF_SIZE_2KiB; - else - ret = DEFAULT_BUFSIZE; - - return ret; -} - -/** - * stmmac_clear_rx_descriptors - clear RX descriptors - * @priv: driver private structure - * @queue: RX queue index - * Description: this function is called to clear the RX descriptors - * in case of both basic and extended descriptors are used. - */ -static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - /* Clear the RX descriptors */ - for (i = 0; i < priv->dma_rx_size; i++) - if (priv->extend_desc) - stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, - priv->use_riwt, priv->mode, - (i == priv->dma_rx_size - 1), - priv->dma_buf_sz); - else - stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], - priv->use_riwt, priv->mode, - (i == priv->dma_rx_size - 1), - priv->dma_buf_sz); -} - -/** - * stmmac_clear_tx_descriptors - clear tx descriptors - * @priv: driver private structure - * @queue: TX queue index. - * Description: this function is called to clear the TX descriptors - * in case of both basic and extended descriptors are used. - */ -static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int i; - - /* Clear the TX descriptors */ - for (i = 0; i < priv->dma_tx_size; i++) { - int last = (i == (priv->dma_tx_size - 1)); - struct dma_desc *p; - - if (priv->extend_desc) - p = &tx_q->dma_etx[i].basic; - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &tx_q->dma_entx[i].basic; - else - p = &tx_q->dma_tx[i]; - - stmmac_init_tx_desc(priv, p, priv->mode, last); - } -} - -/** - * stmmac_clear_descriptors - clear descriptors - * @priv: driver private structure - * Description: this function is called to clear the TX and RX descriptors - * in case of both basic and extended descriptors are used. - */ -static void stmmac_clear_descriptors(struct stmmac_priv *priv) -{ - u32 rx_queue_cnt = priv->plat->rx_queues_to_use; - u32 tx_queue_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - /* Clear the RX descriptors */ - for (queue = 0; queue < rx_queue_cnt; queue++) - stmmac_clear_rx_descriptors(priv, queue); - - /* Clear the TX descriptors */ - for (queue = 0; queue < tx_queue_cnt; queue++) - stmmac_clear_tx_descriptors(priv, queue); -} - -/** - * stmmac_init_rx_buffers - init the RX descriptor buffer. - * @priv: driver private structure - * @p: descriptor pointer - * @i: descriptor index - * @flags: gfp flag - * @queue: RX queue index - * Description: this function is called to allocate a receive buffer, perform - * the DMA mapping and init the descriptor. - */ -static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, - int i, gfp_t flags, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; - gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); - - if (priv->dma_cap.addr64 <= 32) - gfp |= GFP_DMA32; - - if (!buf->page) { - buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); - if (!buf->page) - return -ENOMEM; - buf->page_offset = stmmac_rx_offset(priv); - } - - if (priv->sph && !buf->sec_page) { - buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); - if (!buf->sec_page) - return -ENOMEM; - - buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); - } else { - buf->sec_page = NULL; - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); - } - - buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; - - stmmac_set_desc_addr(priv, p, buf->addr); - if (priv->dma_buf_sz == BUF_SIZE_16KiB) - stmmac_init_desc3(priv, p); - - return 0; -} - -/** - * stmmac_free_rx_buffer - free RX dma buffers - * @priv: private structure - * @queue: RX queue index - * @i: buffer index. - */ -static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; - - if (buf->page) - page_pool_put_full_page(rx_q->page_pool, buf->page, false); - buf->page = NULL; - - if (buf->sec_page) - page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); - buf->sec_page = NULL; -} - -/** - * stmmac_free_tx_buffer - free RX dma buffers - * @priv: private structure - * @queue: RX queue index - * @i: buffer index. - */ -static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - if (tx_q->tx_skbuff_dma[i].buf && - tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { - if (tx_q->tx_skbuff_dma[i].map_as_page) - dma_unmap_page(priv->device, - tx_q->tx_skbuff_dma[i].buf, - tx_q->tx_skbuff_dma[i].len, - DMA_TO_DEVICE); - else - dma_unmap_single(priv->device, - tx_q->tx_skbuff_dma[i].buf, - tx_q->tx_skbuff_dma[i].len, - DMA_TO_DEVICE); - } - - if (tx_q->xdpf[i] && - (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || - tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { - xdp_return_frame(tx_q->xdpf[i]); - tx_q->xdpf[i] = NULL; - } - - if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) - tx_q->xsk_frames_done++; - - if (tx_q->tx_skbuff[i] && - tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { - dev_kfree_skb_any(tx_q->tx_skbuff[i]); - tx_q->tx_skbuff[i] = NULL; - } - - tx_q->tx_skbuff_dma[i].buf = 0; - tx_q->tx_skbuff_dma[i].map_as_page = false; -} - -/** - * dma_free_rx_skbufs - free RX dma buffers - * @priv: private structure - * @queue: RX queue index - */ -static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) -{ - int i; - - for (i = 0; i < priv->dma_rx_size; i++) - stmmac_free_rx_buffer(priv, queue, i); -} - -static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue, - gfp_t flags) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - for (i = 0; i < priv->dma_rx_size; i++) { - struct dma_desc *p; - int ret; - - if (priv->extend_desc) - p = &((rx_q->dma_erx + i)->basic); - else - p = rx_q->dma_rx + i; - - ret = stmmac_init_rx_buffers(priv, p, i, flags, - queue); - if (ret) - return ret; - - rx_q->buf_alloc_num++; - } - - return 0; -} - -/** - * dma_free_rx_xskbufs - free RX dma buffers from XSK pool - * @priv: private structure - * @queue: RX queue index - */ -static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - for (i = 0; i < priv->dma_rx_size; i++) { - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; - - if (!buf->xdp) - continue; - - xsk_buff_free(buf->xdp); - buf->xdp = NULL; - } -} - -static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - for (i = 0; i < priv->dma_rx_size; i++) { - struct stmmac_rx_buffer *buf; - dma_addr_t dma_addr; - struct dma_desc *p; - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + i); - else - p = rx_q->dma_rx + i; - - buf = &rx_q->buf_pool[i]; - - buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); - if (!buf->xdp) - return -ENOMEM; - - dma_addr = xsk_buff_xdp_get_dma(buf->xdp); - stmmac_set_desc_addr(priv, p, dma_addr); - rx_q->buf_alloc_num++; - } - - return 0; -} - -static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) -{ - if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) - return NULL; - - return xsk_get_pool_from_qid(priv->dev, queue); -} - -/** - * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) - * @priv: driver private structure - * @queue: RX queue index - * @flags: gfp flag. - * Description: this function initializes the DMA RX descriptors - * and allocates the socket buffers. It supports the chained and ring - * modes. - */ -static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int ret; - - netif_dbg(priv, probe, priv->dev, - "(%s) dma_rx_phy=0x%08x\n", __func__, - (u32)rx_q->dma_rx_phy); - - stmmac_clear_rx_descriptors(priv, queue); - - xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); - - rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); - - if (rx_q->xsk_pool) { - WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, - MEM_TYPE_XSK_BUFF_POOL, - NULL)); - netdev_info(priv->dev, - "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", - rx_q->queue_index); - xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); - } else { - WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, - MEM_TYPE_PAGE_POOL, - rx_q->page_pool)); - netdev_info(priv->dev, - "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", - rx_q->queue_index); - } - - if (rx_q->xsk_pool) { - /* RX XDP ZC buffer pool may not be populated, e.g. - * xdpsock TX-only. - */ - stmmac_alloc_rx_buffers_zc(priv, queue); - } else { - ret = stmmac_alloc_rx_buffers(priv, queue, flags); - if (ret < 0) - return -ENOMEM; - } - - rx_q->cur_rx = 0; - rx_q->dirty_rx = 0; - - /* Setup the chained descriptor addresses */ - if (priv->mode == STMMAC_CHAIN_MODE) { - if (priv->extend_desc) - stmmac_mode_init(priv, rx_q->dma_erx, - rx_q->dma_rx_phy, - priv->dma_rx_size, 1); - else - stmmac_mode_init(priv, rx_q->dma_rx, - rx_q->dma_rx_phy, - priv->dma_rx_size, 0); - } - - return 0; -} - -static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 rx_count = priv->plat->rx_queues_to_use; - u32 queue; - int ret; - - /* RX INITIALIZATION */ - netif_dbg(priv, probe, priv->dev, - "SKB addresses:\nskb\t\tskb data\tdma data\n"); - - for (queue = 0; queue < rx_count; queue++) { - ret = __init_dma_rx_desc_rings(priv, queue, flags); - if (ret) - goto err_init_rx_buffers; - } - - return 0; - -err_init_rx_buffers: - while (queue >= 0) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - if (rx_q->xsk_pool) - dma_free_rx_xskbufs(priv, queue); - else - dma_free_rx_skbufs(priv, queue); - - rx_q->buf_alloc_num = 0; - rx_q->xsk_pool = NULL; - - if (queue == 0) - break; - - queue--; - } - - return ret; -} - -/** - * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) - * @priv: driver private structure - * @queue : TX queue index - * Description: this function initializes the DMA TX descriptors - * and allocates the socket buffers. It supports the chained and ring - * modes. - */ -static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int i; - - netif_dbg(priv, probe, priv->dev, - "(%s) dma_tx_phy=0x%08x\n", __func__, - (u32)tx_q->dma_tx_phy); - - /* Setup the chained descriptor addresses */ - if (priv->mode == STMMAC_CHAIN_MODE) { - if (priv->extend_desc) - stmmac_mode_init(priv, tx_q->dma_etx, - tx_q->dma_tx_phy, - priv->dma_tx_size, 1); - else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) - stmmac_mode_init(priv, tx_q->dma_tx, - tx_q->dma_tx_phy, - priv->dma_tx_size, 0); - } - - tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); - - for (i = 0; i < priv->dma_tx_size; i++) { - struct dma_desc *p; - - if (priv->extend_desc) - p = &((tx_q->dma_etx + i)->basic); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &((tx_q->dma_entx + i)->basic); - else - p = tx_q->dma_tx + i; - - stmmac_clear_desc(priv, p); - - tx_q->tx_skbuff_dma[i].buf = 0; - tx_q->tx_skbuff_dma[i].map_as_page = false; - tx_q->tx_skbuff_dma[i].len = 0; - tx_q->tx_skbuff_dma[i].last_segment = false; - tx_q->tx_skbuff[i] = NULL; - } - - tx_q->dirty_tx = 0; - tx_q->cur_tx = 0; - tx_q->mss = 0; - - netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); - - return 0; -} - -static int init_dma_tx_desc_rings(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 tx_queue_cnt; - u32 queue; - - tx_queue_cnt = priv->plat->tx_queues_to_use; - - for (queue = 0; queue < tx_queue_cnt; queue++) - __init_dma_tx_desc_rings(priv, queue); - - return 0; -} - -/** - * init_dma_desc_rings - init the RX/TX descriptor rings - * @dev: net device structure - * @flags: gfp flag. - * Description: this function initializes the DMA RX/TX descriptors - * and allocates the socket buffers. It supports the chained and ring - * modes. - */ -static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret; - - ret = init_dma_rx_desc_rings(dev, flags); - if (ret) - return ret; - - ret = init_dma_tx_desc_rings(dev); - - stmmac_clear_descriptors(priv); - - if (netif_msg_hw(priv)) - stmmac_display_rings(priv); - - return ret; -} - -/** - * dma_free_tx_skbufs - free TX dma buffers - * @priv: private structure - * @queue: TX queue index - */ -static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int i; - - tx_q->xsk_frames_done = 0; - - for (i = 0; i < priv->dma_tx_size; i++) - stmmac_free_tx_buffer(priv, queue, i); - - if (tx_q->xsk_pool && tx_q->xsk_frames_done) { - xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); - tx_q->xsk_frames_done = 0; - tx_q->xsk_pool = NULL; - } -} - -/** - * stmmac_free_tx_skbufs - free TX skb buffers - * @priv: private structure - */ -static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) -{ - u32 tx_queue_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - for (queue = 0; queue < tx_queue_cnt; queue++) - dma_free_tx_skbufs(priv, queue); -} - -/** - * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) - * @priv: private structure - * @queue: RX queue index - */ -static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - /* Release the DMA RX socket buffers */ - if (rx_q->xsk_pool) - dma_free_rx_xskbufs(priv, queue); - else - dma_free_rx_skbufs(priv, queue); - - rx_q->buf_alloc_num = 0; - rx_q->xsk_pool = NULL; - - /* Free DMA regions of consistent memory previously allocated */ - if (!priv->extend_desc) - dma_free_coherent(priv->device, priv->dma_rx_size * - sizeof(struct dma_desc), - rx_q->dma_rx, rx_q->dma_rx_phy); - else - dma_free_coherent(priv->device, priv->dma_rx_size * - sizeof(struct dma_extended_desc), - rx_q->dma_erx, rx_q->dma_rx_phy); - - if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) - xdp_rxq_info_unreg(&rx_q->xdp_rxq); - - kfree(rx_q->buf_pool); - if (rx_q->page_pool) - page_pool_destroy(rx_q->page_pool); -} - -static void free_dma_rx_desc_resources(struct stmmac_priv *priv) -{ - u32 rx_count = priv->plat->rx_queues_to_use; - u32 queue; - - /* Free RX queue resources */ - for (queue = 0; queue < rx_count; queue++) - __free_dma_rx_desc_resources(priv, queue); -} - -/** - * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) - * @priv: private structure - * @queue: TX queue index - */ -static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - size_t size; - void *addr; - - /* Release the DMA TX socket buffers */ - dma_free_tx_skbufs(priv, queue); - - if (priv->extend_desc) { - size = sizeof(struct dma_extended_desc); - addr = tx_q->dma_etx; - } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { - size = sizeof(struct dma_edesc); - addr = tx_q->dma_entx; - } else { - size = sizeof(struct dma_desc); - addr = tx_q->dma_tx; - } - - size *= priv->dma_tx_size; - - dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); - - kfree(tx_q->tx_skbuff_dma); - kfree(tx_q->tx_skbuff); -} - -static void free_dma_tx_desc_resources(struct stmmac_priv *priv) -{ - u32 tx_count = priv->plat->tx_queues_to_use; - u32 queue; - - /* Free TX queue resources */ - for (queue = 0; queue < tx_count; queue++) - __free_dma_tx_desc_resources(priv, queue); -} - -/** - * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). - * @priv: private structure - * @queue: RX queue index - * Description: according to which descriptor can be used (extend or basic) - * this function allocates the resources for TX and RX paths. In case of - * reception, for example, it pre-allocated the RX socket buffer in order to - * allow zero-copy mechanism. - */ -static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - bool xdp_prog = stmmac_xdp_is_enabled(priv); - struct page_pool_params pp_params = { 0 }; - unsigned int num_pages; - unsigned int napi_id; - int ret; - - rx_q->queue_index = queue; - rx_q->priv_data = priv; - - pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; - pp_params.pool_size = priv->dma_rx_size; - num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); - pp_params.order = ilog2(num_pages); - pp_params.nid = dev_to_node(priv->device); - pp_params.dev = priv->device; - pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; - pp_params.offset = stmmac_rx_offset(priv); - pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); - - rx_q->page_pool = page_pool_create(&pp_params); - if (IS_ERR(rx_q->page_pool)) { - ret = PTR_ERR(rx_q->page_pool); - rx_q->page_pool = NULL; - return ret; - } - - rx_q->buf_pool = kcalloc(priv->dma_rx_size, - sizeof(*rx_q->buf_pool), - GFP_KERNEL); - if (!rx_q->buf_pool) - return -ENOMEM; - - if (priv->extend_desc) { - rx_q->dma_erx = dma_alloc_coherent(priv->device, - priv->dma_rx_size * - sizeof(struct dma_extended_desc), - &rx_q->dma_rx_phy, - GFP_KERNEL); - if (!rx_q->dma_erx) - return -ENOMEM; - - } else { - rx_q->dma_rx = dma_alloc_coherent(priv->device, - priv->dma_rx_size * - sizeof(struct dma_desc), - &rx_q->dma_rx_phy, - GFP_KERNEL); - if (!rx_q->dma_rx) - return -ENOMEM; - } - - if (stmmac_xdp_is_enabled(priv) && - test_bit(queue, priv->af_xdp_zc_qps)) - napi_id = ch->rxtx_napi.napi_id; - else - napi_id = ch->rx_napi.napi_id; - - ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, - rx_q->queue_index, - napi_id); - if (ret) { - netdev_err(priv->dev, "Failed to register xdp rxq info\n"); - return -EINVAL; - } - - return 0; -} - -static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) -{ - u32 rx_count = priv->plat->rx_queues_to_use; - u32 queue; - int ret; - - /* RX queues buffers and DMA */ - for (queue = 0; queue < rx_count; queue++) { - ret = __alloc_dma_rx_desc_resources(priv, queue); - if (ret) - goto err_dma; - } - - return 0; - -err_dma: - free_dma_rx_desc_resources(priv); - - return ret; -} - -/** - * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). - * @priv: private structure - * @queue: TX queue index - * Description: according to which descriptor can be used (extend or basic) - * this function allocates the resources for TX and RX paths. In case of - * reception, for example, it pre-allocated the RX socket buffer in order to - * allow zero-copy mechanism. - */ -static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - size_t size; - void *addr; - - tx_q->queue_index = queue; - tx_q->priv_data = priv; - - tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size, - sizeof(*tx_q->tx_skbuff_dma), - GFP_KERNEL); - if (!tx_q->tx_skbuff_dma) - return -ENOMEM; - - tx_q->tx_skbuff = kcalloc(priv->dma_tx_size, - sizeof(struct sk_buff *), - GFP_KERNEL); - if (!tx_q->tx_skbuff) - return -ENOMEM; - - if (priv->extend_desc) - size = sizeof(struct dma_extended_desc); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - size = sizeof(struct dma_edesc); - else - size = sizeof(struct dma_desc); - - size *= priv->dma_tx_size; - - addr = dma_alloc_coherent(priv->device, size, - &tx_q->dma_tx_phy, GFP_KERNEL); - if (!addr) - return -ENOMEM; - - if (priv->extend_desc) - tx_q->dma_etx = addr; - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - tx_q->dma_entx = addr; - else - tx_q->dma_tx = addr; - - return 0; -} - -static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) -{ - u32 tx_count = priv->plat->tx_queues_to_use; - u32 queue; - int ret; - - /* TX queues buffers and DMA */ - for (queue = 0; queue < tx_count; queue++) { - ret = __alloc_dma_tx_desc_resources(priv, queue); - if (ret) - goto err_dma; - } - - return 0; - -err_dma: - free_dma_tx_desc_resources(priv); - return ret; -} - -/** - * alloc_dma_desc_resources - alloc TX/RX resources. - * @priv: private structure - * Description: according to which descriptor can be used (extend or basic) - * this function allocates the resources for TX and RX paths. In case of - * reception, for example, it pre-allocated the RX socket buffer in order to - * allow zero-copy mechanism. - */ -static int alloc_dma_desc_resources(struct stmmac_priv *priv) -{ - /* RX Allocation */ - int ret = alloc_dma_rx_desc_resources(priv); - - if (ret) - return ret; - - ret = alloc_dma_tx_desc_resources(priv); - - return ret; -} - -/** - * free_dma_desc_resources - free dma desc resources - * @priv: private structure - */ -static void free_dma_desc_resources(struct stmmac_priv *priv) -{ - /* Release the DMA TX socket buffers */ - free_dma_tx_desc_resources(priv); - - /* Release the DMA RX socket buffers later - * to ensure all pending XDP_TX buffers are returned. - */ - free_dma_rx_desc_resources(priv); -} - -/** - * stmmac_mac_enable_rx_queues - Enable MAC rx queues - * @priv: driver private structure - * Description: It is used for enabling the rx queues in the MAC - */ -static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - int queue; - u8 mode; - - for (queue = 0; queue < rx_queues_count; queue++) { - mode = priv->plat->rx_queues_cfg[queue].mode_to_use; - stmmac_rx_queue_enable(priv, priv->hw, mode, queue); - } -} - -/** - * stmmac_start_rx_dma - start RX DMA channel - * @priv: driver private structure - * @chan: RX channel index - * Description: - * This starts a RX DMA channel - */ -static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); - stmmac_start_rx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_start_tx_dma - start TX DMA channel - * @priv: driver private structure - * @chan: TX channel index - * Description: - * This starts a TX DMA channel - */ -static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); - stmmac_start_tx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_stop_rx_dma - stop RX DMA channel - * @priv: driver private structure - * @chan: RX channel index - * Description: - * This stops a RX DMA channel - */ -static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); - stmmac_stop_rx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_stop_tx_dma - stop TX DMA channel - * @priv: driver private structure - * @chan: TX channel index - * Description: - * This stops a TX DMA channel - */ -static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); - stmmac_stop_tx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_start_all_dma - start all RX and TX DMA channels - * @priv: driver private structure - * Description: - * This starts all the RX and TX DMA channels - */ -static void stmmac_start_all_dma(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 chan = 0; - - for (chan = 0; chan < rx_channels_count; chan++) - stmmac_start_rx_dma(priv, chan); - - for (chan = 0; chan < tx_channels_count; chan++) - stmmac_start_tx_dma(priv, chan); -} - -/** - * stmmac_stop_all_dma - stop all RX and TX DMA channels - * @priv: driver private structure - * Description: - * This stops the RX and TX DMA channels - */ -static void stmmac_stop_all_dma(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 chan = 0; - - for (chan = 0; chan < rx_channels_count; chan++) - stmmac_stop_rx_dma(priv, chan); - - for (chan = 0; chan < tx_channels_count; chan++) - stmmac_stop_tx_dma(priv, chan); -} - -/** - * stmmac_dma_operation_mode - HW DMA operation mode - * @priv: driver private structure - * Description: it is used for configuring the DMA operation mode register in - * order to program the tx/rx DMA thresholds or Store-And-Forward mode. - */ -static void stmmac_dma_operation_mode(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - int rxfifosz = priv->plat->rx_fifo_size; - int txfifosz = priv->plat->tx_fifo_size; - u32 txmode = 0; - u32 rxmode = 0; - u32 chan = 0; - u8 qmode = 0; - - if (rxfifosz == 0) - rxfifosz = priv->dma_cap.rx_fifo_size; - if (txfifosz == 0) - txfifosz = priv->dma_cap.tx_fifo_size; - - /* Adjust for real per queue fifo size */ - rxfifosz /= rx_channels_count; - txfifosz /= tx_channels_count; - - if (priv->plat->force_thresh_dma_mode) { - txmode = tc; - rxmode = tc; - } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { - /* - * In case of GMAC, SF mode can be enabled - * to perform the TX COE in HW. This depends on: - * 1) TX COE if actually supported - * 2) There is no bugged Jumbo frame support - * that needs to not insert csum in the TDES. - */ - txmode = SF_DMA_MODE; - rxmode = SF_DMA_MODE; - priv->xstats.threshold = SF_DMA_MODE; - } else { - txmode = tc; - rxmode = SF_DMA_MODE; - } - - /* configure all channels */ - for (chan = 0; chan < rx_channels_count; chan++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; - u32 buf_size; - - qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; - - stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, - rxfifosz, qmode); - - if (rx_q->xsk_pool) { - buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); - stmmac_set_dma_bfsize(priv, priv->ioaddr, - buf_size, - chan); - } else { - stmmac_set_dma_bfsize(priv, priv->ioaddr, - priv->dma_buf_sz, - chan); - } - } - - for (chan = 0; chan < tx_channels_count; chan++) { - qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; - - stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, - txfifosz, qmode); - } -} - -static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) -{ - struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - struct xsk_buff_pool *pool = tx_q->xsk_pool; - unsigned int entry = tx_q->cur_tx; - struct dma_desc *tx_desc = NULL; - struct xdp_desc xdp_desc; - bool work_done = true; - - /* Avoids TX time-out as we are sharing with slow path */ - txq_trans_cond_update(nq); - - budget = min(budget, stmmac_tx_avail(priv, queue)); - - while (budget-- > 0) { - dma_addr_t dma_addr; - bool set_ic; - - /* We are sharing with slow path and stop XSK TX desc submission when - * available TX ring is less than threshold. - */ - if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || - !netif_carrier_ok(priv->dev)) { - work_done = false; - break; - } - - if (!xsk_tx_peek_desc(pool, &xdp_desc)) - break; - - if (likely(priv->extend_desc)) - tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - tx_desc = &tx_q->dma_entx[entry].basic; - else - tx_desc = tx_q->dma_tx + entry; - - dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); - xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); - - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; - - /* To return XDP buffer to XSK pool, we simple call - * xsk_tx_completed(), so we don't need to fill up - * 'buf' and 'xdpf'. - */ - tx_q->tx_skbuff_dma[entry].buf = 0; - tx_q->xdpf[entry] = NULL; - - tx_q->tx_skbuff_dma[entry].map_as_page = false; - tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; - tx_q->tx_skbuff_dma[entry].last_segment = true; - tx_q->tx_skbuff_dma[entry].is_jumbo = false; - - stmmac_set_desc_addr(priv, tx_desc, dma_addr); - - tx_q->tx_count_frames++; - - if (!priv->tx_coal_frames[queue]) - set_ic = false; - else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, tx_desc); - priv->xstats.tx_set_ic_bit++; - } - - stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, - true, priv->mode, true, true, - xdp_desc.len); - - stmmac_enable_dma_transmission(priv, priv->ioaddr); - - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); - entry = tx_q->cur_tx; - } - - if (tx_desc) { - stmmac_flush_tx_descriptors(priv, queue); - xsk_tx_release(pool); - } - - /* Return true if all of the 3 conditions are met - * a) TX Budget is still available - * b) work_done = true when XSK TX desc peek is empty (no more - * pending XSK TX for transmission) - */ - return !!budget && work_done; -} - -static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) -{ - if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { - tc += 64; - - if (priv->plat->force_thresh_dma_mode) - stmmac_set_dma_operation_mode(priv, tc, tc, chan); - else - stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, - chan); - - priv->xstats.threshold = tc; - } -} - -/** - * stmmac_tx_clean - to manage the transmission completion - * @priv: driver private structure - * @budget: napi budget limiting this functions packet handling - * @queue: TX queue index - * Description: it reclaims the transmit resources after transmission completes. - */ -static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - unsigned int bytes_compl = 0, pkts_compl = 0; - unsigned int entry, xmits = 0, count = 0; - - __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); - - priv->xstats.tx_clean++; - - tx_q->xsk_frames_done = 0; - - entry = tx_q->dirty_tx; - - /* Try to clean all TX complete frame in 1 shot */ - while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) { - struct xdp_frame *xdpf; - struct sk_buff *skb; - struct dma_desc *p; - int status; - - if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || - tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { - xdpf = tx_q->xdpf[entry]; - skb = NULL; - } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { - xdpf = NULL; - skb = tx_q->tx_skbuff[entry]; - } else { - xdpf = NULL; - skb = NULL; - } - - if (priv->extend_desc) - p = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &tx_q->dma_entx[entry].basic; - else - p = tx_q->dma_tx + entry; - - status = stmmac_tx_status(priv, &priv->dev->stats, - &priv->xstats, p, priv->ioaddr); - /* Check if the descriptor is owned by the DMA */ - if (unlikely(status & tx_dma_own)) - break; - - count++; - - /* Make sure descriptor fields are read after reading - * the own bit. - */ - dma_rmb(); - - /* Just consider the last segment and ...*/ - if (likely(!(status & tx_not_ls))) { - /* ... verify the status error condition */ - if (unlikely(status & tx_err)) { - priv->dev->stats.tx_errors++; - if (unlikely(status & tx_err_bump_tc)) - stmmac_bump_dma_threshold(priv, queue); - } else { - priv->dev->stats.tx_packets++; - priv->xstats.tx_pkt_n++; - priv->xstats.txq_stats[queue].tx_pkt_n++; - } - if (skb) - stmmac_get_tx_hwtstamp(priv, p, skb); - } - - if (likely(tx_q->tx_skbuff_dma[entry].buf && - tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { - if (tx_q->tx_skbuff_dma[entry].map_as_page) - dma_unmap_page(priv->device, - tx_q->tx_skbuff_dma[entry].buf, - tx_q->tx_skbuff_dma[entry].len, - DMA_TO_DEVICE); - else - dma_unmap_single(priv->device, - tx_q->tx_skbuff_dma[entry].buf, - tx_q->tx_skbuff_dma[entry].len, - DMA_TO_DEVICE); - tx_q->tx_skbuff_dma[entry].buf = 0; - tx_q->tx_skbuff_dma[entry].len = 0; - tx_q->tx_skbuff_dma[entry].map_as_page = false; - } - - stmmac_clean_desc3(priv, tx_q, p); - - tx_q->tx_skbuff_dma[entry].last_segment = false; - tx_q->tx_skbuff_dma[entry].is_jumbo = false; - - if (xdpf && - tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { - xdp_return_frame_rx_napi(xdpf); - tx_q->xdpf[entry] = NULL; - } - - if (xdpf && - tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { - xdp_return_frame(xdpf); - tx_q->xdpf[entry] = NULL; - } - - if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) - tx_q->xsk_frames_done++; - - if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { - if (likely(skb)) { - pkts_compl++; - bytes_compl += skb->len; - dev_consume_skb_any(skb); - tx_q->tx_skbuff[entry] = NULL; - } - } - - stmmac_release_tx_desc(priv, p, priv->mode); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - } - tx_q->dirty_tx = entry; - - netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), - pkts_compl, bytes_compl); - - if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, - queue))) && - stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { - - netif_dbg(priv, tx_done, priv->dev, - "%s: restart transmit\n", __func__); - netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); - } - - if (tx_q->xsk_pool) { - bool work_done; - - if (tx_q->xsk_frames_done) - xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); - - if (xsk_uses_need_wakeup(tx_q->xsk_pool)) - xsk_set_tx_need_wakeup(tx_q->xsk_pool); - - /* For XSK TX, we try to send as many as possible. - * If XSK work done (XSK TX desc empty and budget still - * available), return "budget - 1" to reenable TX IRQ. - * Else, return "budget" to make NAPI continue polling. - */ - work_done = stmmac_xdp_xmit_zc(priv, queue, - STMMAC_XSK_TX_BUDGET_MAX); - if (work_done) - xmits = budget - 1; - else - xmits = budget; - } - - if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && - priv->eee_sw_timer_en) { - if (stmmac_enable_eee_mode(priv)) - mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); - } - - /* We still have pending packets, let's call for a new scheduling */ - if (tx_q->dirty_tx != tx_q->cur_tx) - hrtimer_start(&tx_q->txtimer, - STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), - HRTIMER_MODE_REL); - - __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); - - /* Combine decisions from TX clean and XSK TX */ - return max(count, xmits); -} - -/** - * stmmac_tx_err - to manage the tx error - * @priv: driver private structure - * @chan: channel index - * Description: it cleans the descriptors and restarts the transmission - * in case of transmission errors. - */ -static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); - - stmmac_stop_tx_dma(priv, chan); - dma_free_tx_skbufs(priv, chan); - stmmac_clear_tx_descriptors(priv, chan); - tx_q->dirty_tx = 0; - tx_q->cur_tx = 0; - tx_q->mss = 0; - netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); - stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - tx_q->dma_tx_phy, chan); - stmmac_start_tx_dma(priv, chan); - - priv->dev->stats.tx_errors++; - netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); -} - -/** - * stmmac_set_dma_operation_mode - Set DMA operation mode by channel - * @priv: driver private structure - * @txmode: TX operating mode - * @rxmode: RX operating mode - * @chan: channel index - * Description: it is used for configuring of the DMA operation mode in - * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward - * mode. - */ -static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, - u32 rxmode, u32 chan) -{ - u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; - u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - int rxfifosz = priv->plat->rx_fifo_size; - int txfifosz = priv->plat->tx_fifo_size; - - if (rxfifosz == 0) - rxfifosz = priv->dma_cap.rx_fifo_size; - if (txfifosz == 0) - txfifosz = priv->dma_cap.tx_fifo_size; - - /* Adjust for real per queue fifo size */ - rxfifosz /= rx_channels_count; - txfifosz /= tx_channels_count; - - stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); - stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); -} - -static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) -{ - int ret; - - ret = stmmac_safety_feat_irq_status(priv, priv->dev, - priv->ioaddr, priv->dma_cap.asp, &priv->sstats); - if (ret && (ret != -EINVAL)) { - stmmac_global_err(priv); - return true; - } - - return false; -} - -static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) -{ - int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, - &priv->xstats, chan, dir); - struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - struct stmmac_channel *ch = &priv->channel[chan]; - struct napi_struct *rx_napi; - struct napi_struct *tx_napi; - unsigned long flags; - - rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; - tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; - - if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { - if (napi_schedule_prep(rx_napi)) { - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); - __napi_schedule(rx_napi); - } - } - - if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { - if (napi_schedule_prep(tx_napi)) { - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - __napi_schedule(tx_napi); - } - } - - return status; -} - -/** - * stmmac_dma_interrupt - DMA ISR - * @priv: driver private structure - * Description: this is the DMA ISR. It is called by the main ISR. - * It calls the dwmac dma routine and schedule poll method in case of some - * work can be done. - */ -static void stmmac_dma_interrupt(struct stmmac_priv *priv) -{ - u32 tx_channel_count = priv->plat->tx_queues_to_use; - u32 rx_channel_count = priv->plat->rx_queues_to_use; - u32 channels_to_check = tx_channel_count > rx_channel_count ? - tx_channel_count : rx_channel_count; - u32 chan; - int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; - - /* Make sure we never check beyond our status buffer. */ - if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) - channels_to_check = ARRAY_SIZE(status); - - for (chan = 0; chan < channels_to_check; chan++) - status[chan] = stmmac_napi_check(priv, chan, - DMA_DIR_RXTX); - - for (chan = 0; chan < tx_channel_count; chan++) { - if (unlikely(status[chan] & tx_hard_error_bump_tc)) { - /* Try to bump up the dma threshold on this failure */ - stmmac_bump_dma_threshold(priv, chan); - } else if (unlikely(status[chan] == tx_hard_error)) { - stmmac_tx_err(priv, chan); - } - } -} - -/** - * stmmac_mmc_setup: setup the Mac Management Counters (MMC) - * @priv: driver private structure - * Description: this masks the MMC irq, in fact, the counters are managed in SW. - */ -static void stmmac_mmc_setup(struct stmmac_priv *priv) -{ - unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | - MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; - - stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); - - if (priv->dma_cap.rmon) { - stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); - memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); - } else - netdev_info(priv->dev, "No MAC Management Counters available\n"); -} - -/** - * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. - * @priv: driver private structure - * Description: - * new GMAC chip generations have a new register to indicate the - * presence of the optional feature/functions. - * This can be also used to override the value passed through the - * platform and necessary for old MAC10/100 and GMAC chips. - */ -static int stmmac_get_hw_features(struct stmmac_priv *priv) -{ - return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; -} - -/** - * stmmac_check_ether_addr - check if the MAC addr is valid - * @priv: driver private structure - * Description: - * it is to verify if the MAC address is valid, in case of failures it - * generates a random MAC address - */ -static void stmmac_check_ether_addr(struct stmmac_priv *priv) -{ - u8 addr[ETH_ALEN]; - - if (!is_valid_ether_addr(priv->dev->dev_addr)) { - stmmac_get_umac_addr(priv, priv->hw, addr, 0); - if (is_valid_ether_addr(addr)) - eth_hw_addr_set(priv->dev, addr); - else - eth_hw_addr_random(priv->dev); - dev_info(priv->device, "device MAC address %pM\n", - priv->dev->dev_addr); - } -} - -/** - * stmmac_init_dma_engine - DMA init. - * @priv: driver private structure - * Description: - * It inits the DMA invoking the specific MAC/GMAC callback. - * Some DMA parameters can be passed from the platform; - * in case of these are not passed a default is kept for the MAC or GMAC. - */ -static int stmmac_init_dma_engine(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); - struct stmmac_rx_queue *rx_q; - struct stmmac_tx_queue *tx_q; - u32 chan = 0; - int atds = 0; - int ret = 0; - - if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { - dev_err(priv->device, "Invalid DMA configuration\n"); - return -EINVAL; - } - - if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) - atds = 1; - - ret = stmmac_reset(priv, priv->ioaddr); - if (ret) { - dev_err(priv->device, "Failed to reset the dma\n"); - return ret; - } - - /* DMA Configuration */ - stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); - - if (priv->plat->axi) - stmmac_axi(priv, priv->ioaddr, priv->plat->axi); - - /* DMA CSR Channel configuration */ - for (chan = 0; chan < dma_csr_ch; chan++) - stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); - - /* DMA RX Channel Configuration */ - for (chan = 0; chan < rx_channels_count; chan++) { - rx_q = &priv->rx_queue[chan]; - - stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - rx_q->dma_rx_phy, chan); - - rx_q->rx_tail_addr = rx_q->dma_rx_phy + - (rx_q->buf_alloc_num * - sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, - rx_q->rx_tail_addr, chan); - } - - /* DMA TX Channel Configuration */ - for (chan = 0; chan < tx_channels_count; chan++) { - tx_q = &priv->tx_queue[chan]; - - stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - tx_q->dma_tx_phy, chan); - - tx_q->tx_tail_addr = tx_q->dma_tx_phy; - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, - tx_q->tx_tail_addr, chan); - } - - return ret; -} - -static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - hrtimer_start(&tx_q->txtimer, - STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), - HRTIMER_MODE_REL); -} - -/** - * stmmac_tx_timer - mitigation sw timer for tx. - * @t: data pointer - * Description: - * This is the timer handler to directly invoke the stmmac_tx_clean. - */ -static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) -{ - struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); - struct stmmac_priv *priv = tx_q->priv_data; - struct stmmac_channel *ch; - struct napi_struct *napi; - - ch = &priv->channel[tx_q->queue_index]; - napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; - - if (likely(napi_schedule_prep(napi))) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - __napi_schedule(napi); - } - - return HRTIMER_NORESTART; -} - -/** - * stmmac_init_coalesce - init mitigation options. - * @priv: driver private structure - * Description: - * This inits the coalesce parameters: i.e. timer rate, - * timer handler and default threshold used for enabling the - * interrupt on completion bit. - */ -static void stmmac_init_coalesce(struct stmmac_priv *priv) -{ - u32 tx_channel_count = priv->plat->tx_queues_to_use; - u32 rx_channel_count = priv->plat->rx_queues_to_use; - u32 chan; - - for (chan = 0; chan < tx_channel_count; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - - priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; - priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; - - hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - tx_q->txtimer.function = stmmac_tx_timer; - } - - for (chan = 0; chan < rx_channel_count; chan++) - priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; -} - -static void stmmac_set_rings_length(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 chan; - - /* set TX ring length */ - for (chan = 0; chan < tx_channels_count; chan++) - stmmac_set_tx_ring_len(priv, priv->ioaddr, - (priv->dma_tx_size - 1), chan); - - /* set RX ring length */ - for (chan = 0; chan < rx_channels_count; chan++) - stmmac_set_rx_ring_len(priv, priv->ioaddr, - (priv->dma_rx_size - 1), chan); -} - -/** - * stmmac_set_tx_queue_weight - Set TX queue weight - * @priv: driver private structure - * Description: It is used for setting TX queues weight - */ -static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) -{ - u32 tx_queues_count = priv->plat->tx_queues_to_use; - u32 weight; - u32 queue; - - for (queue = 0; queue < tx_queues_count; queue++) { - weight = priv->plat->tx_queues_cfg[queue].weight; - stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); - } -} - -/** - * stmmac_configure_cbs - Configure CBS in TX queue - * @priv: driver private structure - * Description: It is used for configuring CBS in AVB TX queues - */ -static void stmmac_configure_cbs(struct stmmac_priv *priv) -{ - u32 tx_queues_count = priv->plat->tx_queues_to_use; - u32 mode_to_use; - u32 queue; - - /* queue 0 is reserved for legacy traffic */ - for (queue = 1; queue < tx_queues_count; queue++) { - mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; - if (mode_to_use == MTL_QUEUE_DCB) - continue; - - stmmac_config_cbs(priv, priv->hw, - priv->plat->tx_queues_cfg[queue].send_slope, - priv->plat->tx_queues_cfg[queue].idle_slope, - priv->plat->tx_queues_cfg[queue].high_credit, - priv->plat->tx_queues_cfg[queue].low_credit, - queue); - } -} - -/** - * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel - * @priv: driver private structure - * Description: It is used for mapping RX queues to RX dma channels - */ -static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 queue; - u32 chan; - - for (queue = 0; queue < rx_queues_count; queue++) { - chan = priv->plat->rx_queues_cfg[queue].chan; - stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); - } -} - -/** - * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority - * @priv: driver private structure - * Description: It is used for configuring the RX Queue Priority - */ -static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 queue; - u32 prio; - - for (queue = 0; queue < rx_queues_count; queue++) { - if (!priv->plat->rx_queues_cfg[queue].use_prio) - continue; - - prio = priv->plat->rx_queues_cfg[queue].prio; - stmmac_rx_queue_prio(priv, priv->hw, prio, queue); - } -} - -/** - * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority - * @priv: driver private structure - * Description: It is used for configuring the TX Queue Priority - */ -static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) -{ - u32 tx_queues_count = priv->plat->tx_queues_to_use; - u32 queue; - u32 prio; - - for (queue = 0; queue < tx_queues_count; queue++) { - if (!priv->plat->tx_queues_cfg[queue].use_prio) - continue; - - prio = priv->plat->tx_queues_cfg[queue].prio; - stmmac_tx_queue_prio(priv, priv->hw, prio, queue); - } -} - -/** - * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing - * @priv: driver private structure - * Description: It is used for configuring the RX queue routing - */ -static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 queue; - u8 packet; - - for (queue = 0; queue < rx_queues_count; queue++) { - /* no specific packet type routing specified for the queue */ - if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) - continue; - - packet = priv->plat->rx_queues_cfg[queue].pkt_route; - stmmac_rx_queue_routing(priv, priv->hw, packet, queue); - } -} - -static void stmmac_mac_config_rss(struct stmmac_priv *priv) -{ - if (!priv->dma_cap.rssen || !priv->plat->rss_en) { - priv->rss.enable = false; - return; - } - - if (priv->dev->features & NETIF_F_RXHASH) - priv->rss.enable = true; - else - priv->rss.enable = false; - - stmmac_rss_configure(priv, priv->hw, &priv->rss, - priv->plat->rx_queues_to_use); -} - -/** - * stmmac_mtl_configuration - Configure MTL - * @priv: driver private structure - * Description: It is used for configurring MTL - */ -static void stmmac_mtl_configuration(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 tx_queues_count = priv->plat->tx_queues_to_use; - - if (tx_queues_count > 1) - stmmac_set_tx_queue_weight(priv); - - /* Configure MTL RX algorithms */ - if (rx_queues_count > 1) - stmmac_prog_mtl_rx_algorithms(priv, priv->hw, - priv->plat->rx_sched_algorithm); - - /* Configure MTL TX algorithms */ - if (tx_queues_count > 1) - stmmac_prog_mtl_tx_algorithms(priv, priv->hw, - priv->plat->tx_sched_algorithm); - - /* Configure CBS in AVB TX queues */ - if (tx_queues_count > 1) - stmmac_configure_cbs(priv); - - /* Map RX MTL to DMA channels */ - stmmac_rx_queue_dma_chan_map(priv); - - /* Enable MAC RX Queues */ - stmmac_mac_enable_rx_queues(priv); - - /* Set RX priorities */ - if (rx_queues_count > 1) - stmmac_mac_config_rx_queues_prio(priv); - - /* Set TX priorities */ - if (tx_queues_count > 1) - stmmac_mac_config_tx_queues_prio(priv); - - /* Set RX routing */ - if (rx_queues_count > 1) - stmmac_mac_config_rx_queues_routing(priv); - - /* Receive Side Scaling */ - if (rx_queues_count > 1) - stmmac_mac_config_rss(priv); -} - -static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) -{ - if (priv->dma_cap.asp) { - netdev_info(priv->dev, "Enabling Safety Features\n"); - stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, - priv->plat->safety_feat_cfg); - } else { - netdev_info(priv->dev, "No Safety Features support found\n"); - } -} - -static int stmmac_fpe_start_wq(struct stmmac_priv *priv) -{ - char *name; - - clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); - clear_bit(__FPE_REMOVING, &priv->fpe_task_state); - - name = priv->wq_name; - sprintf(name, "%s-fpe", priv->dev->name); - - priv->fpe_wq = create_singlethread_workqueue(name); - if (!priv->fpe_wq) { - netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); - - return -ENOMEM; - } - netdev_info(priv->dev, "FPE workqueue start"); - - return 0; -} - -/** - * stmmac_hw_setup - setup mac in a usable state. - * @dev : pointer to the device structure. - * @ptp_register: register PTP if set - * Description: - * this is the main function to setup the HW in a usable state because the - * dma engine is reset, the core registers are configured (e.g. AXI, - * Checksum features, timers). The DMA is ready to start receiving and - * transmitting. - * Return value: - * 0 on success and an appropriate (-)ve integer as defined in errno.h - * file on failure. - */ -static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 rx_cnt = priv->plat->rx_queues_to_use; - u32 tx_cnt = priv->plat->tx_queues_to_use; - bool sph_en; - u32 chan; - int ret; - - /* DMA initialization and SW reset */ - ret = stmmac_init_dma_engine(priv); - if (ret < 0) { - netdev_err(priv->dev, "%s: DMA engine initialization failed\n", - __func__); - return ret; - } - - /* Copy the MAC addr into the HW */ - stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); - - /* PS and related bits will be programmed according to the speed */ - if (priv->hw->pcs) { - int speed = priv->plat->mac_port_sel_speed; - - if ((speed == SPEED_10) || (speed == SPEED_100) || - (speed == SPEED_1000)) { - priv->hw->ps = speed; - } else { - dev_warn(priv->device, "invalid port speed\n"); - priv->hw->ps = 0; - } - } - - /* Initialize the MAC Core */ - stmmac_core_init(priv, priv->hw, dev); - - /* Initialize MTL*/ - stmmac_mtl_configuration(priv); - - /* Initialize Safety Features */ - stmmac_safety_feat_configuration(priv); - - ret = stmmac_rx_ipc(priv, priv->hw); - if (!ret) { - netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); - priv->plat->rx_coe = STMMAC_RX_COE_NONE; - priv->hw->rx_csum = 0; - } - - /* Enable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, true); - - /* Set the HW DMA mode and the COE */ - stmmac_dma_operation_mode(priv); - - stmmac_mmc_setup(priv); - - ret = stmmac_init_ptp(priv); - if (ret == -EOPNOTSUPP) - netdev_warn(priv->dev, "PTP not supported by HW\n"); - else if (ret) - netdev_warn(priv->dev, "PTP init failed\n"); - else if (ptp_register) - stmmac_ptp_register(priv); - - priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; - - /* Convert the timer from msec to usec */ - if (!priv->tx_lpi_timer) - priv->tx_lpi_timer = eee_timer * 1000; - - if (priv->use_riwt) { - u32 queue; - - for (queue = 0; queue < rx_cnt; queue++) { - if (!priv->rx_riwt[queue]) - priv->rx_riwt[queue] = DEF_DMA_RIWT; - - stmmac_rx_watchdog(priv, priv->ioaddr, - priv->rx_riwt[queue], queue); - } - } - - if (priv->hw->pcs) - stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); - - /* set TX and RX rings length */ - stmmac_set_rings_length(priv); - - /* Enable TSO */ - if (priv->tso) { - for (chan = 0; chan < tx_cnt; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - - /* TSO and TBS cannot co-exist */ - if (tx_q->tbs & STMMAC_TBS_AVAIL) - continue; - - stmmac_enable_tso(priv, priv->ioaddr, 1, chan); - } - } - - /* Enable Split Header */ - sph_en = (priv->hw->rx_csum > 0) && priv->sph; - for (chan = 0; chan < rx_cnt; chan++) - stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); - - - /* VLAN Tag Insertion */ - if (priv->dma_cap.vlins) - stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); - - /* TBS */ - for (chan = 0; chan < tx_cnt; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - int enable = tx_q->tbs & STMMAC_TBS_AVAIL; - - stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); - } - - /* Configure real RX and TX queues */ - netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); - netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); - - /* Start the ball rolling... */ - stmmac_start_all_dma(priv); - - if (priv->dma_cap.fpesel) { - stmmac_fpe_start_wq(priv); - - if (priv->plat->fpe_cfg->enable) - stmmac_fpe_handshake(priv, true); - } - - return 0; -} - -static void stmmac_hw_teardown(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - clk_disable_unprepare(priv->plat->clk_ptp_ref); -} - -static void stmmac_free_irq(struct net_device *dev, - enum request_irq_err irq_err, int irq_idx) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int j; - - switch (irq_err) { - case REQ_IRQ_ERR_ALL: - irq_idx = priv->plat->tx_queues_to_use; - fallthrough; - case REQ_IRQ_ERR_TX: - for (j = irq_idx - 1; j >= 0; j--) { - if (priv->tx_irq[j] > 0) { - irq_set_affinity_hint(priv->tx_irq[j], NULL); - free_irq(priv->tx_irq[j], &priv->tx_queue[j]); - } - } - irq_idx = priv->plat->rx_queues_to_use; - fallthrough; - case REQ_IRQ_ERR_RX: - for (j = irq_idx - 1; j >= 0; j--) { - if (priv->rx_irq[j] > 0) { - irq_set_affinity_hint(priv->rx_irq[j], NULL); - free_irq(priv->rx_irq[j], &priv->rx_queue[j]); - } - } - - if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) - free_irq(priv->sfty_ue_irq, dev); - fallthrough; - case REQ_IRQ_ERR_SFTY_UE: - if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) - free_irq(priv->sfty_ce_irq, dev); - fallthrough; - case REQ_IRQ_ERR_SFTY_CE: - if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) - free_irq(priv->lpi_irq, dev); - fallthrough; - case REQ_IRQ_ERR_LPI: - if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) - free_irq(priv->wol_irq, dev); - fallthrough; - case REQ_IRQ_ERR_WOL: - free_irq(dev->irq, dev); - fallthrough; - case REQ_IRQ_ERR_MAC: - case REQ_IRQ_ERR_NO: - /* If MAC IRQ request error, no more IRQ to free */ - break; - } -} - -static int stmmac_request_irq_multi_msi(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - enum request_irq_err irq_err; - cpumask_t cpu_mask; - int irq_idx = 0; - char *int_name; - int ret; - int i; - - /* For common interrupt */ - int_name = priv->int_name_mac; - sprintf(int_name, "%s:%s", dev->name, "mac"); - ret = request_irq(dev->irq, stmmac_mac_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc mac MSI %d (error: %d)\n", - __func__, dev->irq, ret); - irq_err = REQ_IRQ_ERR_MAC; - goto irq_error; - } - - /* Request the Wake IRQ in case of another line - * is used for WoL - */ - if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { - int_name = priv->int_name_wol; - sprintf(int_name, "%s:%s", dev->name, "wol"); - ret = request_irq(priv->wol_irq, - stmmac_mac_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc wol MSI %d (error: %d)\n", - __func__, priv->wol_irq, ret); - irq_err = REQ_IRQ_ERR_WOL; - goto irq_error; - } - } - - /* Request the LPI IRQ in case of another line - * is used for LPI - */ - if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { - int_name = priv->int_name_lpi; - sprintf(int_name, "%s:%s", dev->name, "lpi"); - ret = request_irq(priv->lpi_irq, - stmmac_mac_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc lpi MSI %d (error: %d)\n", - __func__, priv->lpi_irq, ret); - irq_err = REQ_IRQ_ERR_LPI; - goto irq_error; - } - } - - /* Request the Safety Feature Correctible Error line in - * case of another line is used - */ - if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { - int_name = priv->int_name_sfty_ce; - sprintf(int_name, "%s:%s", dev->name, "safety-ce"); - ret = request_irq(priv->sfty_ce_irq, - stmmac_safety_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc sfty ce MSI %d (error: %d)\n", - __func__, priv->sfty_ce_irq, ret); - irq_err = REQ_IRQ_ERR_SFTY_CE; - goto irq_error; - } - } - - /* Request the Safety Feature Uncorrectible Error line in - * case of another line is used - */ - if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { - int_name = priv->int_name_sfty_ue; - sprintf(int_name, "%s:%s", dev->name, "safety-ue"); - ret = request_irq(priv->sfty_ue_irq, - stmmac_safety_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc sfty ue MSI %d (error: %d)\n", - __func__, priv->sfty_ue_irq, ret); - irq_err = REQ_IRQ_ERR_SFTY_UE; - goto irq_error; - } - } - - /* Request Rx MSI irq */ - for (i = 0; i < priv->plat->rx_queues_to_use; i++) { - if (i >= MTL_MAX_RX_QUEUES) - break; - if (priv->rx_irq[i] == 0) - continue; - - int_name = priv->int_name_rx_irq[i]; - sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); - ret = request_irq(priv->rx_irq[i], - stmmac_msi_intr_rx, - 0, int_name, &priv->rx_queue[i]); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc rx-%d MSI %d (error: %d)\n", - __func__, i, priv->rx_irq[i], ret); - irq_err = REQ_IRQ_ERR_RX; - irq_idx = i; - goto irq_error; - } - cpumask_clear(&cpu_mask); - cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); - irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); - } - - /* Request Tx MSI irq */ - for (i = 0; i < priv->plat->tx_queues_to_use; i++) { - if (i >= MTL_MAX_TX_QUEUES) - break; - if (priv->tx_irq[i] == 0) - continue; - - int_name = priv->int_name_tx_irq[i]; - sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); - ret = request_irq(priv->tx_irq[i], - stmmac_msi_intr_tx, - 0, int_name, &priv->tx_queue[i]); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc tx-%d MSI %d (error: %d)\n", - __func__, i, priv->tx_irq[i], ret); - irq_err = REQ_IRQ_ERR_TX; - irq_idx = i; - goto irq_error; - } - cpumask_clear(&cpu_mask); - cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); - irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); - } - - return 0; - -irq_error: - stmmac_free_irq(dev, irq_err, irq_idx); - return ret; -} - -static int stmmac_request_irq_single(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - enum request_irq_err irq_err; - int ret; - - ret = request_irq(dev->irq, stmmac_interrupt, - IRQF_SHARED, dev->name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: ERROR: allocating the IRQ %d (error: %d)\n", - __func__, dev->irq, ret); - irq_err = REQ_IRQ_ERR_MAC; - goto irq_error; - } - - /* Request the Wake IRQ in case of another line - * is used for WoL - */ - if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { - ret = request_irq(priv->wol_irq, stmmac_interrupt, - IRQF_SHARED, dev->name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: ERROR: allocating the WoL IRQ %d (%d)\n", - __func__, priv->wol_irq, ret); - irq_err = REQ_IRQ_ERR_WOL; - goto irq_error; - } - } - - /* Request the IRQ lines */ - if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { - ret = request_irq(priv->lpi_irq, stmmac_interrupt, - IRQF_SHARED, dev->name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: ERROR: allocating the LPI IRQ %d (%d)\n", - __func__, priv->lpi_irq, ret); - irq_err = REQ_IRQ_ERR_LPI; - goto irq_error; - } - } - - return 0; - -irq_error: - stmmac_free_irq(dev, irq_err, 0); - return ret; -} - -static int stmmac_request_irq(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret; - - /* Request the IRQ lines */ - if (priv->plat->multi_msi_en) - ret = stmmac_request_irq_multi_msi(dev); - else - ret = stmmac_request_irq_single(dev); - - return ret; -} - -/** - * stmmac_open - open entry point of the driver - * @dev : pointer to the device structure. - * Description: - * This function is the open entry point of the driver. - * Return value: - * 0 on success and an appropriate (-)ve integer as defined in errno.h - * file on failure. - */ -static int stmmac_open(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int mode = priv->plat->phy_interface; - int bfsize = 0; - u32 chan; - int ret; - - ret = pm_runtime_get_sync(priv->device); - if (ret < 0) { - pm_runtime_put_noidle(priv->device); - return ret; - } - - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI && - (!priv->hw->xpcs || - xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { - ret = stmmac_init_phy(dev); - if (ret) { - netdev_err(priv->dev, - "%s: Cannot attach to PHY (error: %d)\n", - __func__, ret); - goto init_phy_error; - } - } - - /* Extra statistics */ - memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); - priv->xstats.threshold = tc; - - bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); - if (bfsize < 0) - bfsize = 0; - - if (bfsize < BUF_SIZE_16KiB) - bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); - - priv->dma_buf_sz = bfsize; - buf_sz = bfsize; - - priv->rx_copybreak = STMMAC_RX_COPYBREAK; - - if (!priv->dma_tx_size) - priv->dma_tx_size = DMA_DEFAULT_TX_SIZE; - if (!priv->dma_rx_size) - priv->dma_rx_size = DMA_DEFAULT_RX_SIZE; - - /* Earlier check for TBS */ - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; - - /* Setup per-TXQ tbs flag before TX descriptor alloc */ - tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; - } - - ret = alloc_dma_desc_resources(priv); - if (ret < 0) { - netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", - __func__); - goto dma_desc_error; - } - - ret = init_dma_desc_rings(dev, GFP_KERNEL); - if (ret < 0) { - netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", - __func__); - goto init_error; - } - - ret = stmmac_hw_setup(dev, true); - if (ret < 0) { - netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); - goto init_error; - } - - stmmac_init_coalesce(priv); - - phylink_start(priv->phylink); - /* We may have called phylink_speed_down before */ - phylink_speed_up(priv->phylink); - - ret = stmmac_request_irq(dev); - if (ret) - goto irq_error; - - stmmac_enable_all_queues(priv); - netif_tx_start_all_queues(priv->dev); - - return 0; - -irq_error: - phylink_stop(priv->phylink); - - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - stmmac_hw_teardown(dev); -init_error: - free_dma_desc_resources(priv); -dma_desc_error: - phylink_disconnect_phy(priv->phylink); -init_phy_error: - pm_runtime_put(priv->device); - return ret; -} - -static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) -{ - set_bit(__FPE_REMOVING, &priv->fpe_task_state); - - if (priv->fpe_wq) - destroy_workqueue(priv->fpe_wq); - - netdev_info(priv->dev, "FPE workqueue stop"); -} - -/** - * stmmac_release - close entry point of the driver - * @dev : device pointer. - * Description: - * This is the stop entry point of the driver. - */ -static int stmmac_release(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 chan; - - netif_tx_disable(dev); - - if (device_may_wakeup(priv->device)) - phylink_speed_down(priv->phylink, false); - /* Stop and disconnect the PHY */ - phylink_stop(priv->phylink); - phylink_disconnect_phy(priv->phylink); - - stmmac_disable_all_queues(priv); - - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - /* Free the IRQ lines */ - stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); - - if (priv->eee_enabled) { - priv->tx_path_in_lpi_mode = false; - del_timer_sync(&priv->eee_ctrl_timer); - } - - /* Stop TX/RX DMA and clear the descriptors */ - stmmac_stop_all_dma(priv); - - /* Release and free the Rx/Tx resources */ - free_dma_desc_resources(priv); - - /* Disable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, false); - - netif_carrier_off(dev); - - stmmac_release_ptp(priv); - - pm_runtime_put(priv->device); - - if (priv->dma_cap.fpesel) - stmmac_fpe_stop_wq(priv); - - return 0; -} - -static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, - struct stmmac_tx_queue *tx_q) -{ - u16 tag = 0x0, inner_tag = 0x0; - u32 inner_type = 0x0; - struct dma_desc *p; - - if (!priv->dma_cap.vlins) - return false; - if (!skb_vlan_tag_present(skb)) - return false; - if (skb->vlan_proto == htons(ETH_P_8021AD)) { - inner_tag = skb_vlan_tag_get(skb); - inner_type = STMMAC_VLAN_INSERT; - } - - tag = skb_vlan_tag_get(skb); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - p = &tx_q->dma_tx[tx_q->cur_tx]; - - if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) - return false; - - stmmac_set_tx_owner(priv, p); - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); - return true; -} - -/** - * stmmac_tso_allocator - close entry point of the driver - * @priv: driver private structure - * @des: buffer start address - * @total_len: total length to fill in descriptors - * @last_segment: condition for the last descriptor - * @queue: TX queue index - * Description: - * This function fills descriptor and request new descriptors according to - * buffer length to fill - */ -static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, - int total_len, bool last_segment, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - struct dma_desc *desc; - u32 buff_size; - int tmp_len; - - tmp_len = total_len; - - while (tmp_len > 0) { - dma_addr_t curr_addr; - - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, - priv->dma_tx_size); - WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - desc = &tx_q->dma_tx[tx_q->cur_tx]; - - curr_addr = des + (total_len - tmp_len); - if (priv->dma_cap.addr64 <= 32) - desc->des0 = cpu_to_le32(curr_addr); - else - stmmac_set_desc_addr(priv, desc, curr_addr); - - buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? - TSO_MAX_BUFF_SIZE : tmp_len; - - stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, - 0, 1, - (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), - 0, 0); - - tmp_len -= TSO_MAX_BUFF_SIZE; - } -} - -static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int desc_size; - - if (likely(priv->extend_desc)) - desc_size = sizeof(struct dma_extended_desc); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc_size = sizeof(struct dma_edesc); - else - desc_size = sizeof(struct dma_desc); - - /* The own bit must be the latest setting done when prepare the - * descriptor and then barrier is needed to make sure that - * all is coherent before granting the DMA engine. - */ - wmb(); - - tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); -} - -/** - * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) - * @skb : the socket buffer - * @dev : device pointer - * Description: this is the transmit function that is called on TSO frames - * (support available on GMAC4 and newer chips). - * Diagram below show the ring programming in case of TSO frames: - * - * First Descriptor - * -------- - * | DES0 |---> buffer1 = L2/L3/L4 header - * | DES1 |---> TCP Payload (can continue on next descr...) - * | DES2 |---> buffer 1 and 2 len - * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] - * -------- - * | - * ... - * | - * -------- - * | DES0 | --| Split TCP Payload on Buffers 1 and 2 - * | DES1 | --| - * | DES2 | --> buffer 1 and 2 len - * | DES3 | - * -------- - * - * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. - */ -static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct dma_desc *desc, *first, *mss_desc = NULL; - struct stmmac_priv *priv = netdev_priv(dev); - int nfrags = skb_shinfo(skb)->nr_frags; - u32 queue = skb_get_queue_mapping(skb); - unsigned int first_entry, tx_packets; - int tmp_pay_len = 0, first_tx; - struct stmmac_tx_queue *tx_q; - bool has_vlan, set_ic; - u8 proto_hdr_len, hdr; - u32 pay_len, mss; - dma_addr_t des; - int i; - - tx_q = &priv->tx_queue[queue]; - first_tx = tx_q->cur_tx; - - /* Compute header lengths */ - if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { - proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); - hdr = sizeof(struct udphdr); - } else { - proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); - hdr = tcp_hdrlen(skb); - } - - /* Desc availability based on threshold should be enough safe */ - if (unlikely(stmmac_tx_avail(priv, queue) < - (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { - if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, - queue)); - /* This is a hard error, log it. */ - netdev_err(priv->dev, - "%s: Tx Ring full when queue awake\n", - __func__); - } - return NETDEV_TX_BUSY; - } - - pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ - - mss = skb_shinfo(skb)->gso_size; - - /* set new MSS value if needed */ - if (mss != tx_q->mss) { - if (tx_q->tbs & STMMAC_TBS_AVAIL) - mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; - - stmmac_set_mss(priv, mss_desc, mss); - tx_q->mss = mss; - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, - priv->dma_tx_size); - WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); - } - - if (netif_msg_tx_queued(priv)) { - pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", - __func__, hdr, proto_hdr_len, pay_len, mss); - pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, - skb->data_len); - } - - /* Check if VLAN can be inserted by HW */ - has_vlan = stmmac_vlan_insert(priv, skb, tx_q); - - first_entry = tx_q->cur_tx; - WARN_ON(tx_q->tx_skbuff[first_entry]); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[first_entry].basic; - else - desc = &tx_q->dma_tx[first_entry]; - first = desc; - - if (has_vlan) - stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); - - /* first descriptor: fill Headers on Buf1 */ - des = dma_map_single(priv->device, skb->data, skb_headlen(skb), - DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; - - tx_q->tx_skbuff_dma[first_entry].buf = des; - tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); - tx_q->tx_skbuff_dma[first_entry].map_as_page = false; - tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; - - if (priv->dma_cap.addr64 <= 32) { - first->des0 = cpu_to_le32(des); - - /* Fill start of payload in buff2 of first descriptor */ - if (pay_len) - first->des1 = cpu_to_le32(des + proto_hdr_len); - - /* If needed take extra descriptors to fill the remaining payload */ - tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; - } else { - stmmac_set_desc_addr(priv, first, des); - tmp_pay_len = pay_len; - des += proto_hdr_len; - pay_len = 0; - } - - stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); - - /* Prepare fragments */ - for (i = 0; i < nfrags; i++) { - const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; - - des = skb_frag_dma_map(priv->device, frag, 0, - skb_frag_size(frag), - DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; - - stmmac_tso_allocator(priv, des, skb_frag_size(frag), - (i == nfrags - 1), queue); - - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; - tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); - tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; - } - - tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; - - /* Only the last descriptor gets to point to the skb. */ - tx_q->tx_skbuff[tx_q->cur_tx] = skb; - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; - - /* Manage tx mitigation */ - tx_packets = (tx_q->cur_tx + 1) - first_tx; - tx_q->tx_count_frames += tx_packets; - - if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) - set_ic = true; - else if (!priv->tx_coal_frames[queue]) - set_ic = false; - else if (tx_packets > priv->tx_coal_frames[queue]) - set_ic = true; - else if ((tx_q->tx_count_frames % - priv->tx_coal_frames[queue]) < tx_packets) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - desc = &tx_q->dma_tx[tx_q->cur_tx]; - - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, desc); - priv->xstats.tx_set_ic_bit++; - } - - /* We've used all descriptors we need for this skb, however, - * advance cur_tx so that it references a fresh descriptor. - * ndo_start_xmit will fill this descriptor the next time it's - * called and stmmac_tx_clean may clean up to this descriptor. - */ - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); - - if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { - netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", - __func__); - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); - } - - dev->stats.tx_bytes += skb->len; - priv->xstats.tx_tso_frames++; - priv->xstats.tx_tso_nfrags += nfrags; - - if (priv->sarc_type) - stmmac_set_desc_sarc(priv, first, priv->sarc_type); - - skb_tx_timestamp(skb); - - if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && - priv->hwts_tx_en)) { - /* declare that device is doing timestamping */ - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - stmmac_enable_tx_timestamp(priv, first); - } - - /* Complete the first descriptor before granting the DMA */ - stmmac_prepare_tso_tx_desc(priv, first, 1, - proto_hdr_len, - pay_len, - 1, tx_q->tx_skbuff_dma[first_entry].last_segment, - hdr / 4, (skb->len - proto_hdr_len)); - - /* If context desc is used to change MSS */ - if (mss_desc) { - /* Make sure that first descriptor has been completely - * written, including its own bit. This is because MSS is - * actually before first descriptor, so we need to make - * sure that MSS's own bit is the last thing written. - */ - dma_wmb(); - stmmac_set_tx_owner(priv, mss_desc); - } - - if (netif_msg_pktdata(priv)) { - pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", - __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, - tx_q->cur_tx, first, nfrags); - pr_info(">>> frame to be transmitted: "); - print_pkt(skb->data, skb_headlen(skb)); - } - - netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); - - stmmac_flush_tx_descriptors(priv, queue); - stmmac_tx_timer_arm(priv, queue); - - return NETDEV_TX_OK; - -dma_map_err: - dev_err(priv->device, "Tx dma map failed\n"); - dev_kfree_skb(skb); - priv->dev->stats.tx_dropped++; - return NETDEV_TX_OK; -} - -/** - * stmmac_xmit - Tx entry point of the driver - * @skb : the socket buffer - * @dev : device pointer - * Description : this is the tx entry point of the driver. - * It programs the chain or the ring and supports oversized frames - * and SG feature. - */ -static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) -{ - unsigned int first_entry, tx_packets, enh_desc; - struct stmmac_priv *priv = netdev_priv(dev); - unsigned int nopaged_len = skb_headlen(skb); - int i, csum_insertion = 0, is_jumbo = 0; - u32 queue = skb_get_queue_mapping(skb); - int nfrags = skb_shinfo(skb)->nr_frags; - int gso = skb_shinfo(skb)->gso_type; - struct dma_edesc *tbs_desc = NULL; - struct dma_desc *desc, *first; - struct stmmac_tx_queue *tx_q; - bool has_vlan, set_ic; - int entry, first_tx; - dma_addr_t des; - - tx_q = &priv->tx_queue[queue]; - first_tx = tx_q->cur_tx; - - if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) - stmmac_disable_eee_mode(priv); - - /* Manage oversized TCP frames for GMAC4 device */ - if (skb_is_gso(skb) && priv->tso) { - if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) - return stmmac_tso_xmit(skb, dev); - if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) - return stmmac_tso_xmit(skb, dev); - } - - if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { - if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, - queue)); - /* This is a hard error, log it. */ - netdev_err(priv->dev, - "%s: Tx Ring full when queue awake\n", - __func__); - } - return NETDEV_TX_BUSY; - } - - /* Check if VLAN can be inserted by HW */ - has_vlan = stmmac_vlan_insert(priv, skb, tx_q); - - entry = tx_q->cur_tx; - first_entry = entry; - WARN_ON(tx_q->tx_skbuff[first_entry]); - - csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); - - if (likely(priv->extend_desc)) - desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[entry].basic; - else - desc = tx_q->dma_tx + entry; - - first = desc; - - if (has_vlan) - stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); - - enh_desc = priv->plat->enh_desc; - /* To program the descriptors according to the size of the frame */ - if (enh_desc) - is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); - - if (unlikely(is_jumbo)) { - entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); - if (unlikely(entry < 0) && (entry != -EINVAL)) - goto dma_map_err; - } - - for (i = 0; i < nfrags; i++) { - const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; - int len = skb_frag_size(frag); - bool last_segment = (i == (nfrags - 1)); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - WARN_ON(tx_q->tx_skbuff[entry]); - - if (likely(priv->extend_desc)) - desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[entry].basic; - else - desc = tx_q->dma_tx + entry; - - des = skb_frag_dma_map(priv->device, frag, 0, len, - DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; /* should reuse desc w/o issues */ - - tx_q->tx_skbuff_dma[entry].buf = des; - - stmmac_set_desc_addr(priv, desc, des); - - tx_q->tx_skbuff_dma[entry].map_as_page = true; - tx_q->tx_skbuff_dma[entry].len = len; - tx_q->tx_skbuff_dma[entry].last_segment = last_segment; - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; - - /* Prepare the descriptor and set the own bit too */ - stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, - priv->mode, 1, last_segment, skb->len); - } - - /* Only the last descriptor gets to point to the skb. */ - tx_q->tx_skbuff[entry] = skb; - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; - - /* According to the coalesce parameter the IC bit for the latest - * segment is reset and the timer re-started to clean the tx status. - * This approach takes care about the fragments: desc is the first - * element in case of no SG. - */ - tx_packets = (entry + 1) - first_tx; - tx_q->tx_count_frames += tx_packets; - - if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) - set_ic = true; - else if (!priv->tx_coal_frames[queue]) - set_ic = false; - else if (tx_packets > priv->tx_coal_frames[queue]) - set_ic = true; - else if ((tx_q->tx_count_frames % - priv->tx_coal_frames[queue]) < tx_packets) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - if (likely(priv->extend_desc)) - desc = &tx_q->dma_etx[entry].basic; - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[entry].basic; - else - desc = &tx_q->dma_tx[entry]; - - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, desc); - priv->xstats.tx_set_ic_bit++; - } - - /* We've used all descriptors we need for this skb, however, - * advance cur_tx so that it references a fresh descriptor. - * ndo_start_xmit will fill this descriptor the next time it's - * called and stmmac_tx_clean may clean up to this descriptor. - */ - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - tx_q->cur_tx = entry; - - if (netif_msg_pktdata(priv)) { - netdev_dbg(priv->dev, - "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", - __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, - entry, first, nfrags); - - netdev_dbg(priv->dev, ">>> frame to be transmitted: "); - print_pkt(skb->data, skb->len); - } - - if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { - netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", - __func__); - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); - } - - dev->stats.tx_bytes += skb->len; - - if (priv->sarc_type) - stmmac_set_desc_sarc(priv, first, priv->sarc_type); - - skb_tx_timestamp(skb); - - /* Ready to fill the first descriptor and set the OWN bit w/o any - * problems because all the descriptors are actually ready to be - * passed to the DMA engine. - */ - if (likely(!is_jumbo)) { - bool last_segment = (nfrags == 0); - - des = dma_map_single(priv->device, skb->data, - nopaged_len, DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; - - tx_q->tx_skbuff_dma[first_entry].buf = des; - tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; - tx_q->tx_skbuff_dma[first_entry].map_as_page = false; - - stmmac_set_desc_addr(priv, first, des); - - tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; - tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; - - if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && - priv->hwts_tx_en)) { - /* declare that device is doing timestamping */ - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - stmmac_enable_tx_timestamp(priv, first); - } - - /* Prepare the first descriptor setting the OWN bit too */ - stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, - csum_insertion, priv->mode, 0, last_segment, - skb->len); - } - - if (tx_q->tbs & STMMAC_TBS_EN) { - struct timespec64 ts = ns_to_timespec64(skb->tstamp); - - tbs_desc = &tx_q->dma_entx[first_entry]; - stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); - } - - stmmac_set_tx_owner(priv, first); - - netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); - - stmmac_enable_dma_transmission(priv, priv->ioaddr); - - stmmac_flush_tx_descriptors(priv, queue); - stmmac_tx_timer_arm(priv, queue); - - return NETDEV_TX_OK; - -dma_map_err: - netdev_err(priv->dev, "Tx DMA map failed\n"); - dev_kfree_skb(skb); - priv->dev->stats.tx_dropped++; - return NETDEV_TX_OK; -} - -static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) -{ - struct vlan_ethhdr *veth; - __be16 vlan_proto; - u16 vlanid; - - veth = (struct vlan_ethhdr *)skb->data; - vlan_proto = veth->h_vlan_proto; - - if ((vlan_proto == htons(ETH_P_8021Q) && - dev->features & NETIF_F_HW_VLAN_CTAG_RX) || - (vlan_proto == htons(ETH_P_8021AD) && - dev->features & NETIF_F_HW_VLAN_STAG_RX)) { - /* pop the vlan tag */ - vlanid = ntohs(veth->h_vlan_TCI); - memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); - skb_pull(skb, VLAN_HLEN); - __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); - } -} - -/** - * stmmac_rx_refill - refill used skb preallocated buffers - * @priv: driver private structure - * @queue: RX queue index - * Description : this is to reallocate the skb for the reception process - * that is based on zero-copy. - */ -static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int dirty = stmmac_rx_dirty(priv, queue); - unsigned int entry = rx_q->dirty_rx; - gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); - - if (priv->dma_cap.addr64 <= 32) - gfp |= GFP_DMA32; - - while (dirty-- > 0) { - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; - struct dma_desc *p; - bool use_rx_wd; - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + entry); - else - p = rx_q->dma_rx + entry; - - if (!buf->page) { - buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); - if (!buf->page) - break; - } - - if (priv->sph && !buf->sec_page) { - buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); - if (!buf->sec_page) - break; - - buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); - } - - buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; - - stmmac_set_desc_addr(priv, p, buf->addr); - if (priv->sph) - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); - else - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); - stmmac_refill_desc3(priv, rx_q, p); - - rx_q->rx_count_frames++; - rx_q->rx_count_frames += priv->rx_coal_frames[queue]; - if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) - rx_q->rx_count_frames = 0; - - use_rx_wd = !priv->rx_coal_frames[queue]; - use_rx_wd |= rx_q->rx_count_frames > 0; - if (!priv->use_riwt) - use_rx_wd = false; - - dma_wmb(); - stmmac_set_rx_owner(priv, p, use_rx_wd); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); - } - rx_q->dirty_rx = entry; - rx_q->rx_tail_addr = rx_q->dma_rx_phy + - (rx_q->dirty_rx * sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); -} - -static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, - struct dma_desc *p, - int status, unsigned int len) -{ - unsigned int plen = 0, hlen = 0; - int coe = priv->hw->rx_csum; - - /* Not first descriptor, buffer is always zero */ - if (priv->sph && len) - return 0; - - /* First descriptor, get split header length */ - stmmac_get_rx_header_len(priv, p, &hlen); - if (priv->sph && hlen) { - priv->xstats.rx_split_hdr_pkt_n++; - return hlen; - } - - /* First descriptor, not last descriptor and not split header */ - if (status & rx_not_ls) - return priv->dma_buf_sz; - - plen = stmmac_get_rx_frame_len(priv, p, coe); - - /* First descriptor and last descriptor and not split header */ - return min_t(unsigned int, priv->dma_buf_sz, plen); -} - -static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, - struct dma_desc *p, - int status, unsigned int len) -{ - int coe = priv->hw->rx_csum; - unsigned int plen = 0; - - /* Not split header, buffer is not available */ - if (!priv->sph) - return 0; - - /* Not last descriptor */ - if (status & rx_not_ls) - return priv->dma_buf_sz; - - plen = stmmac_get_rx_frame_len(priv, p, coe); - - /* Last descriptor */ - return plen - len; -} - -static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, - struct xdp_frame *xdpf, bool dma_map) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - unsigned int entry = tx_q->cur_tx; - struct dma_desc *tx_desc; - dma_addr_t dma_addr; - bool set_ic; - - if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) - return STMMAC_XDP_CONSUMED; - - if (likely(priv->extend_desc)) - tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - tx_desc = &tx_q->dma_entx[entry].basic; - else - tx_desc = tx_q->dma_tx + entry; - - if (dma_map) { - dma_addr = dma_map_single(priv->device, xdpf->data, - xdpf->len, DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, dma_addr)) - return STMMAC_XDP_CONSUMED; - - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; - } else { - struct page *page = virt_to_page(xdpf->data); - - dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + - xdpf->headroom; - dma_sync_single_for_device(priv->device, dma_addr, - xdpf->len, DMA_BIDIRECTIONAL); - - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; - } - - tx_q->tx_skbuff_dma[entry].buf = dma_addr; - tx_q->tx_skbuff_dma[entry].map_as_page = false; - tx_q->tx_skbuff_dma[entry].len = xdpf->len; - tx_q->tx_skbuff_dma[entry].last_segment = true; - tx_q->tx_skbuff_dma[entry].is_jumbo = false; - - tx_q->xdpf[entry] = xdpf; - - stmmac_set_desc_addr(priv, tx_desc, dma_addr); - - stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, - true, priv->mode, true, true, - xdpf->len); - - tx_q->tx_count_frames++; - - if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, tx_desc); - priv->xstats.tx_set_ic_bit++; - } - - stmmac_enable_dma_transmission(priv, priv->ioaddr); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - tx_q->cur_tx = entry; - - return STMMAC_XDP_TX; -} - -static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, - int cpu) -{ - int index = cpu; - - if (unlikely(index < 0)) - index = 0; - - while (index >= priv->plat->tx_queues_to_use) - index -= priv->plat->tx_queues_to_use; - - return index; -} - -static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, - struct xdp_buff *xdp) -{ - struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); - int cpu = smp_processor_id(); - struct netdev_queue *nq; - int queue; - int res; - - if (unlikely(!xdpf)) - return STMMAC_XDP_CONSUMED; - - queue = stmmac_xdp_get_tx_queue(priv, cpu); - nq = netdev_get_tx_queue(priv->dev, queue); - - __netif_tx_lock(nq, cpu); - /* Avoids TX time-out as we are sharing with slow path */ - txq_trans_cond_update(nq); - - res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); - if (res == STMMAC_XDP_TX) - stmmac_flush_tx_descriptors(priv, queue); - - __netif_tx_unlock(nq); - - return res; -} - -static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, - struct bpf_prog *prog, - struct xdp_buff *xdp) -{ - u32 act; - int res; - - act = bpf_prog_run_xdp(prog, xdp); - switch (act) { - case XDP_PASS: - res = STMMAC_XDP_PASS; - break; - case XDP_TX: - res = stmmac_xdp_xmit_back(priv, xdp); - break; - case XDP_REDIRECT: - if (xdp_do_redirect(priv->dev, xdp, prog) < 0) - res = STMMAC_XDP_CONSUMED; - else - res = STMMAC_XDP_REDIRECT; - break; - default: - bpf_warn_invalid_xdp_action(priv->dev, prog, act); - fallthrough; - case XDP_ABORTED: - trace_xdp_exception(priv->dev, prog, act); - fallthrough; - case XDP_DROP: - res = STMMAC_XDP_CONSUMED; - break; - } - - return res; -} - -static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, - struct xdp_buff *xdp) -{ - struct bpf_prog *prog; - int res; - - prog = READ_ONCE(priv->xdp_prog); - if (!prog) { - res = STMMAC_XDP_PASS; - goto out; - } - - res = __stmmac_xdp_run_prog(priv, prog, xdp); -out: - return ERR_PTR(-res); -} - -static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, - int xdp_status) -{ - int cpu = smp_processor_id(); - int queue; - - queue = stmmac_xdp_get_tx_queue(priv, cpu); - - if (xdp_status & STMMAC_XDP_TX) - stmmac_tx_timer_arm(priv, queue); - - if (xdp_status & STMMAC_XDP_REDIRECT) - xdp_do_flush(); -} - -static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, - struct xdp_buff *xdp) -{ - unsigned int metasize = xdp->data - xdp->data_meta; - unsigned int datasize = xdp->data_end - xdp->data; - struct sk_buff *skb; - - skb = __napi_alloc_skb(&ch->rxtx_napi, - xdp->data_end - xdp->data_hard_start, - GFP_ATOMIC | __GFP_NOWARN); - if (unlikely(!skb)) - return NULL; - - skb_reserve(skb, xdp->data - xdp->data_hard_start); - memcpy(__skb_put(skb, datasize), xdp->data, datasize); - if (metasize) - skb_metadata_set(skb, metasize); - - return skb; -} - -static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, - struct dma_desc *p, struct dma_desc *np, - struct xdp_buff *xdp) -{ - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned int len = xdp->data_end - xdp->data; - enum pkt_hash_types hash_type; - int coe = priv->hw->rx_csum; - struct sk_buff *skb; - u32 hash; - - skb = stmmac_construct_skb_zc(ch, xdp); - if (!skb) { - priv->dev->stats.rx_dropped++; - return; - } - - stmmac_get_rx_hwtstamp(priv, p, np, skb); - stmmac_rx_vlan(priv->dev, skb); - skb->protocol = eth_type_trans(skb, priv->dev); - - if (unlikely(!coe)) - skb_checksum_none_assert(skb); - else - skb->ip_summed = CHECKSUM_UNNECESSARY; - - if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) - skb_set_hash(skb, hash, hash_type); - - skb_record_rx_queue(skb, queue); - napi_gro_receive(&ch->rxtx_napi, skb); - - priv->dev->stats.rx_packets++; - priv->dev->stats.rx_bytes += len; -} - -static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - unsigned int entry = rx_q->dirty_rx; - struct dma_desc *rx_desc = NULL; - bool ret = true; - - budget = min(budget, stmmac_rx_dirty(priv, queue)); - - while (budget-- > 0 && entry != rx_q->cur_rx) { - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; - dma_addr_t dma_addr; - bool use_rx_wd; - - if (!buf->xdp) { - buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); - if (!buf->xdp) { - ret = false; - break; - } - } - - if (priv->extend_desc) - rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); - else - rx_desc = rx_q->dma_rx + entry; - - dma_addr = xsk_buff_xdp_get_dma(buf->xdp); - stmmac_set_desc_addr(priv, rx_desc, dma_addr); - stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); - stmmac_refill_desc3(priv, rx_q, rx_desc); - - rx_q->rx_count_frames++; - rx_q->rx_count_frames += priv->rx_coal_frames[queue]; - if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) - rx_q->rx_count_frames = 0; - - use_rx_wd = !priv->rx_coal_frames[queue]; - use_rx_wd |= rx_q->rx_count_frames > 0; - if (!priv->use_riwt) - use_rx_wd = false; - - dma_wmb(); - stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); - } - - if (rx_desc) { - rx_q->dirty_rx = entry; - rx_q->rx_tail_addr = rx_q->dma_rx_phy + - (rx_q->dirty_rx * sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); - } - - return ret; -} - -static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - unsigned int count = 0, error = 0, len = 0; - int dirty = stmmac_rx_dirty(priv, queue); - unsigned int next_entry = rx_q->cur_rx; - unsigned int desc_size; - struct bpf_prog *prog; - bool failure = false; - int xdp_status = 0; - int status = 0; - - if (netif_msg_rx_status(priv)) { - void *rx_head; - - netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); - if (priv->extend_desc) { - rx_head = (void *)rx_q->dma_erx; - desc_size = sizeof(struct dma_extended_desc); - } else { - rx_head = (void *)rx_q->dma_rx; - desc_size = sizeof(struct dma_desc); - } - - stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, - rx_q->dma_rx_phy, desc_size); - } - while (count < limit) { - struct stmmac_rx_buffer *buf; - unsigned int buf1_len = 0; - struct dma_desc *np, *p; - int entry; - int res; - - if (!count && rx_q->state_saved) { - error = rx_q->state.error; - len = rx_q->state.len; - } else { - rx_q->state_saved = false; - error = 0; - len = 0; - } - - if (count >= limit) - break; - -read_again: - buf1_len = 0; - entry = next_entry; - buf = &rx_q->buf_pool[entry]; - - if (dirty >= STMMAC_RX_FILL_BATCH) { - failure = failure || - !stmmac_rx_refill_zc(priv, queue, dirty); - dirty = 0; - } - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + entry); - else - p = rx_q->dma_rx + entry; - - /* read the status of the incoming frame */ - status = stmmac_rx_status(priv, &priv->dev->stats, - &priv->xstats, p); - /* check if managed by the DMA otherwise go ahead */ - if (unlikely(status & dma_own)) - break; - - /* Prefetch the next RX descriptor */ - rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, - priv->dma_rx_size); - next_entry = rx_q->cur_rx; - - if (priv->extend_desc) - np = (struct dma_desc *)(rx_q->dma_erx + next_entry); - else - np = rx_q->dma_rx + next_entry; - - prefetch(np); - - /* Ensure a valid XSK buffer before proceed */ - if (!buf->xdp) - break; - - if (priv->extend_desc) - stmmac_rx_extended_status(priv, &priv->dev->stats, - &priv->xstats, - rx_q->dma_erx + entry); - if (unlikely(status == discard_frame)) { - xsk_buff_free(buf->xdp); - buf->xdp = NULL; - dirty++; - error = 1; - if (!priv->hwts_rx_en) - priv->dev->stats.rx_errors++; - } - - if (unlikely(error && (status & rx_not_ls))) - goto read_again; - if (unlikely(error)) { - count++; - continue; - } - - /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ - if (likely(status & rx_not_ls)) { - xsk_buff_free(buf->xdp); - buf->xdp = NULL; - dirty++; - count++; - goto read_again; - } - - /* XDP ZC Frame only support primary buffers for now */ - buf1_len = stmmac_rx_buf1_len(priv, p, status, len); - len += buf1_len; - - /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 - * Type frames (LLC/LLC-SNAP) - * - * llc_snap is never checked in GMAC >= 4, so this ACS - * feature is always disabled and packets need to be - * stripped manually. - */ - if (likely(!(status & rx_not_ls)) && - (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || - unlikely(status != llc_snap))) { - buf1_len -= ETH_FCS_LEN; - len -= ETH_FCS_LEN; - } - - /* RX buffer is good and fit into a XSK pool buffer */ - buf->xdp->data_end = buf->xdp->data + buf1_len; - xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); - - prog = READ_ONCE(priv->xdp_prog); - res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); - - switch (res) { - case STMMAC_XDP_PASS: - stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); - xsk_buff_free(buf->xdp); - break; - case STMMAC_XDP_CONSUMED: - xsk_buff_free(buf->xdp); - priv->dev->stats.rx_dropped++; - break; - case STMMAC_XDP_TX: - case STMMAC_XDP_REDIRECT: - xdp_status |= res; - break; - } - - buf->xdp = NULL; - dirty++; - count++; - } - - if (status & rx_not_ls) { - rx_q->state_saved = true; - rx_q->state.error = error; - rx_q->state.len = len; - } - - stmmac_finalize_xdp_rx(priv, xdp_status); - - priv->xstats.rx_pkt_n += count; - priv->xstats.rxq_stats[queue].rx_pkt_n += count; - - if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { - if (failure || stmmac_rx_dirty(priv, queue) > 0) - xsk_set_rx_need_wakeup(rx_q->xsk_pool); - else - xsk_clear_rx_need_wakeup(rx_q->xsk_pool); - - return (int)count; - } - - return failure ? limit : (int)count; -} - -/** - * stmmac_rx - manage the receive process - * @priv: driver private structure - * @limit: napi bugget - * @queue: RX queue index. - * Description : this the function called by the napi poll method. - * It gets all the frames inside the ring. - */ -static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned int count = 0, error = 0, len = 0; - int status = 0, coe = priv->hw->rx_csum; - unsigned int next_entry = rx_q->cur_rx; - enum dma_data_direction dma_dir; - unsigned int desc_size; - struct sk_buff *skb = NULL; - struct xdp_buff xdp; - int xdp_status = 0; - int buf_sz; - - dma_dir = page_pool_get_dma_dir(rx_q->page_pool); - buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; - - if (netif_msg_rx_status(priv)) { - void *rx_head; - - netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); - if (priv->extend_desc) { - rx_head = (void *)rx_q->dma_erx; - desc_size = sizeof(struct dma_extended_desc); - } else { - rx_head = (void *)rx_q->dma_rx; - desc_size = sizeof(struct dma_desc); - } - - stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, - rx_q->dma_rx_phy, desc_size); - } - while (count < limit) { - unsigned int buf1_len = 0, buf2_len = 0; - enum pkt_hash_types hash_type; - struct stmmac_rx_buffer *buf; - struct dma_desc *np, *p; - int entry; - u32 hash; - - if (!count && rx_q->state_saved) { - skb = rx_q->state.skb; - error = rx_q->state.error; - len = rx_q->state.len; - } else { - rx_q->state_saved = false; - skb = NULL; - error = 0; - len = 0; - } - - if (count >= limit) - break; - -read_again: - buf1_len = 0; - buf2_len = 0; - entry = next_entry; - buf = &rx_q->buf_pool[entry]; - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + entry); - else - p = rx_q->dma_rx + entry; - - /* read the status of the incoming frame */ - status = stmmac_rx_status(priv, &priv->dev->stats, - &priv->xstats, p); - /* check if managed by the DMA otherwise go ahead */ - if (unlikely(status & dma_own)) - break; - - rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, - priv->dma_rx_size); - next_entry = rx_q->cur_rx; - - if (priv->extend_desc) - np = (struct dma_desc *)(rx_q->dma_erx + next_entry); - else - np = rx_q->dma_rx + next_entry; - - prefetch(np); - - if (priv->extend_desc) - stmmac_rx_extended_status(priv, &priv->dev->stats, - &priv->xstats, rx_q->dma_erx + entry); - if (unlikely(status == discard_frame)) { - page_pool_recycle_direct(rx_q->page_pool, buf->page); - buf->page = NULL; - error = 1; - if (!priv->hwts_rx_en) - priv->dev->stats.rx_errors++; - } - - if (unlikely(error && (status & rx_not_ls))) - goto read_again; - if (unlikely(error)) { - dev_kfree_skb(skb); - skb = NULL; - count++; - continue; - } - - /* Buffer is good. Go on. */ - - prefetch(page_address(buf->page) + buf->page_offset); - if (buf->sec_page) - prefetch(page_address(buf->sec_page)); - - buf1_len = stmmac_rx_buf1_len(priv, p, status, len); - len += buf1_len; - buf2_len = stmmac_rx_buf2_len(priv, p, status, len); - len += buf2_len; - - /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 - * Type frames (LLC/LLC-SNAP) - * - * llc_snap is never checked in GMAC >= 4, so this ACS - * feature is always disabled and packets need to be - * stripped manually. - */ - if (likely(!(status & rx_not_ls)) && - (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || - unlikely(status != llc_snap))) { - if (buf2_len) { - buf2_len -= ETH_FCS_LEN; - len -= ETH_FCS_LEN; - } else if (buf1_len) { - buf1_len -= ETH_FCS_LEN; - len -= ETH_FCS_LEN; - } - } - - if (!skb) { - unsigned int pre_len, sync_len; - - dma_sync_single_for_cpu(priv->device, buf->addr, - buf1_len, dma_dir); - - xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); - xdp_prepare_buff(&xdp, page_address(buf->page), - buf->page_offset, buf1_len, false); - - pre_len = xdp.data_end - xdp.data_hard_start - - buf->page_offset; - skb = stmmac_xdp_run_prog(priv, &xdp); - /* Due xdp_adjust_tail: DMA sync for_device - * cover max len CPU touch - */ - sync_len = xdp.data_end - xdp.data_hard_start - - buf->page_offset; - sync_len = max(sync_len, pre_len); - - /* For Not XDP_PASS verdict */ - if (IS_ERR(skb)) { - unsigned int xdp_res = -PTR_ERR(skb); - - if (xdp_res & STMMAC_XDP_CONSUMED) { - page_pool_put_page(rx_q->page_pool, - virt_to_head_page(xdp.data), - sync_len, true); - buf->page = NULL; - priv->dev->stats.rx_dropped++; - - /* Clear skb as it was set as - * status by XDP program. - */ - skb = NULL; - - if (unlikely((status & rx_not_ls))) - goto read_again; - - count++; - continue; - } else if (xdp_res & (STMMAC_XDP_TX | - STMMAC_XDP_REDIRECT)) { - xdp_status |= xdp_res; - buf->page = NULL; - skb = NULL; - count++; - continue; - } - } - } - - if (!skb) { - /* XDP program may expand or reduce tail */ - buf1_len = xdp.data_end - xdp.data; - - skb = napi_alloc_skb(&ch->rx_napi, buf1_len); - if (!skb) { - priv->dev->stats.rx_dropped++; - count++; - goto drain_data; - } - - /* XDP program may adjust header */ - skb_copy_to_linear_data(skb, xdp.data, buf1_len); - skb_put(skb, buf1_len); - - /* Data payload copied into SKB, page ready for recycle */ - page_pool_recycle_direct(rx_q->page_pool, buf->page); - buf->page = NULL; - } else if (buf1_len) { - dma_sync_single_for_cpu(priv->device, buf->addr, - buf1_len, dma_dir); - skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, - buf->page, buf->page_offset, buf1_len, - priv->dma_buf_sz); - - /* Data payload appended into SKB */ - page_pool_release_page(rx_q->page_pool, buf->page); - buf->page = NULL; - } - - if (buf2_len) { - dma_sync_single_for_cpu(priv->device, buf->sec_addr, - buf2_len, dma_dir); - skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, - buf->sec_page, 0, buf2_len, - priv->dma_buf_sz); - - /* Data payload appended into SKB */ - page_pool_release_page(rx_q->page_pool, buf->sec_page); - buf->sec_page = NULL; - } - -drain_data: - if (likely(status & rx_not_ls)) - goto read_again; - if (!skb) - continue; - - /* Got entire packet into SKB. Finish it. */ - - stmmac_get_rx_hwtstamp(priv, p, np, skb); - stmmac_rx_vlan(priv->dev, skb); - skb->protocol = eth_type_trans(skb, priv->dev); - - if (unlikely(!coe)) - skb_checksum_none_assert(skb); - else - skb->ip_summed = CHECKSUM_UNNECESSARY; - - if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) - skb_set_hash(skb, hash, hash_type); - - skb_record_rx_queue(skb, queue); - napi_gro_receive(&ch->rx_napi, skb); - skb = NULL; - - priv->dev->stats.rx_packets++; - priv->dev->stats.rx_bytes += len; - count++; - } - - if (status & rx_not_ls || skb) { - rx_q->state_saved = true; - rx_q->state.skb = skb; - rx_q->state.error = error; - rx_q->state.len = len; - } - - stmmac_finalize_xdp_rx(priv, xdp_status); - - stmmac_rx_refill(priv, queue); - - priv->xstats.rx_pkt_n += count; - priv->xstats.rxq_stats[queue].rx_pkt_n += count; - - return count; -} - -static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) -{ - struct stmmac_channel *ch = - container_of(napi, struct stmmac_channel, rx_napi); - struct stmmac_priv *priv = ch->priv_data; - u32 chan = ch->index; - int work_done; - - priv->xstats.napi_poll++; - - work_done = stmmac_rx(priv, budget, chan); - if (work_done < budget && napi_complete_done(napi, work_done)) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); - } - - return work_done; -} - -static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) -{ - struct stmmac_channel *ch = - container_of(napi, struct stmmac_channel, tx_napi); - struct stmmac_priv *priv = ch->priv_data; - u32 chan = ch->index; - int work_done; - - priv->xstats.napi_poll++; - - work_done = stmmac_tx_clean(priv, budget, chan); - work_done = min(work_done, budget); - - if (work_done < budget && napi_complete_done(napi, work_done)) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - } - - return work_done; -} - -static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) -{ - struct stmmac_channel *ch = - container_of(napi, struct stmmac_channel, rxtx_napi); - struct stmmac_priv *priv = ch->priv_data; - int rx_done, tx_done, rxtx_done; - u32 chan = ch->index; - - priv->xstats.napi_poll++; - - tx_done = stmmac_tx_clean(priv, budget, chan); - tx_done = min(tx_done, budget); - - rx_done = stmmac_rx_zc(priv, budget, chan); - - rxtx_done = max(tx_done, rx_done); - - /* If either TX or RX work is not complete, return budget - * and keep pooling - */ - if (rxtx_done >= budget) - return budget; - - /* all work done, exit the polling mode */ - if (napi_complete_done(napi, rxtx_done)) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - /* Both RX and TX work done are compelte, - * so enable both RX & TX IRQs. - */ - stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); - spin_unlock_irqrestore(&ch->lock, flags); - } - - return min(rxtx_done, budget - 1); -} - -/** - * stmmac_tx_timeout - * @dev : Pointer to net device structure - * @txqueue: the index of the hanging transmit queue - * Description: this function is called when a packet transmission fails to - * complete within a reasonable time. The driver will mark the error in the - * netdev structure and arrange for the device to be reset to a sane state - * in order to transmit a new packet. - */ -static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - stmmac_global_err(priv); -} - -/** - * stmmac_set_rx_mode - entry point for multicast addressing - * @dev : pointer to the device structure - * Description: - * This function is a driver entry point which gets called by the kernel - * whenever multicast addresses must be enabled/disabled. - * Return value: - * void. - */ -static void stmmac_set_rx_mode(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - stmmac_set_filter(priv, priv->hw, dev); -} - -/** - * stmmac_change_mtu - entry point to change MTU size for the device. - * @dev : device pointer. - * @new_mtu : the new MTU size for the device. - * Description: the Maximum Transfer Unit (MTU) is used by the network layer - * to drive packet transmission. Ethernet has an MTU of 1500 octets - * (ETH_DATA_LEN). This value can be changed with ifconfig. - * Return value: - * 0 on success and an appropriate (-)ve integer as defined in errno.h - * file on failure. - */ -static int stmmac_change_mtu(struct net_device *dev, int new_mtu) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int txfifosz = priv->plat->tx_fifo_size; - const int mtu = new_mtu; - - if (txfifosz == 0) - txfifosz = priv->dma_cap.tx_fifo_size; - - txfifosz /= priv->plat->tx_queues_to_use; - - if (netif_running(dev)) { - netdev_err(priv->dev, "must be stopped to change its MTU\n"); - return -EBUSY; - } - - if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { - netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); - return -EINVAL; - } - - new_mtu = STMMAC_ALIGN(new_mtu); - - /* If condition true, FIFO is too small or MTU too large */ - if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) - return -EINVAL; - - dev->mtu = mtu; - - netdev_update_features(dev); - - return 0; -} - -static netdev_features_t stmmac_fix_features(struct net_device *dev, - netdev_features_t features) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) - features &= ~NETIF_F_RXCSUM; - - if (!priv->plat->tx_coe) - features &= ~NETIF_F_CSUM_MASK; - - /* Some GMAC devices have a bugged Jumbo frame support that - * needs to have the Tx COE disabled for oversized frames - * (due to limited buffer sizes). In this case we disable - * the TX csum insertion in the TDES and not use SF. - */ - if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) - features &= ~NETIF_F_CSUM_MASK; - - /* Disable tso if asked by ethtool */ - if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { - if (features & NETIF_F_TSO) - priv->tso = true; - else - priv->tso = false; - } - - return features; -} - -static int stmmac_set_features(struct net_device *netdev, - netdev_features_t features) -{ - struct stmmac_priv *priv = netdev_priv(netdev); - - /* Keep the COE Type in case of csum is supporting */ - if (features & NETIF_F_RXCSUM) - priv->hw->rx_csum = priv->plat->rx_coe; - else - priv->hw->rx_csum = 0; - /* No check needed because rx_coe has been set before and it will be - * fixed in case of issue. - */ - stmmac_rx_ipc(priv, priv->hw); - - if (priv->sph_cap) { - bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; - u32 chan; - - for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) - stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); - } - - return 0; -} - -static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) -{ - struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; - enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; - enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; - bool *hs_enable = &fpe_cfg->hs_enable; - - if (status == FPE_EVENT_UNKNOWN || !*hs_enable) - return; - - /* If LP has sent verify mPacket, LP is FPE capable */ - if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { - if (*lp_state < FPE_STATE_CAPABLE) - *lp_state = FPE_STATE_CAPABLE; - - /* If user has requested FPE enable, quickly response */ - if (*hs_enable) - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - MPACKET_RESPONSE); - } - - /* If Local has sent verify mPacket, Local is FPE capable */ - if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { - if (*lo_state < FPE_STATE_CAPABLE) - *lo_state = FPE_STATE_CAPABLE; - } - - /* If LP has sent response mPacket, LP is entering FPE ON */ - if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) - *lp_state = FPE_STATE_ENTERING_ON; - - /* If Local has sent response mPacket, Local is entering FPE ON */ - if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) - *lo_state = FPE_STATE_ENTERING_ON; - - if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && - !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && - priv->fpe_wq) { - queue_work(priv->fpe_wq, &priv->fpe_task); - } -} - -static void stmmac_common_interrupt(struct stmmac_priv *priv) -{ - u32 rx_cnt = priv->plat->rx_queues_to_use; - u32 tx_cnt = priv->plat->tx_queues_to_use; - u32 queues_count; - u32 queue; - bool xmac; - - xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; - queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; - - if (priv->irq_wake) - pm_wakeup_event(priv->device, 0); - - if (priv->dma_cap.estsel) - stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, - &priv->xstats, tx_cnt); - - if (priv->dma_cap.fpesel) { - int status = stmmac_fpe_irq_status(priv, priv->ioaddr, - priv->dev); - - stmmac_fpe_event_status(priv, status); - } - - /* To handle GMAC own interrupts */ - if ((priv->plat->has_gmac) || xmac) { - int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); - - if (unlikely(status)) { - /* For LPI we need to save the tx status */ - if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) - priv->tx_path_in_lpi_mode = true; - if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) - priv->tx_path_in_lpi_mode = false; - } - - for (queue = 0; queue < queues_count; queue++) { - status = stmmac_host_mtl_irq_status(priv, priv->hw, - queue); - } - - /* PCS link status */ - if (priv->hw->pcs) { - if (priv->xstats.pcs_link) - netif_carrier_on(priv->dev); - else - netif_carrier_off(priv->dev); - } - - stmmac_timestamp_interrupt(priv, priv); - } -} - -/** - * stmmac_interrupt - main ISR - * @irq: interrupt number. - * @dev_id: to pass the net device pointer. - * Description: this is the main driver interrupt service routine. - * It can call: - * o DMA service routine (to manage incoming frame reception and transmission - * status) - * o Core interrupts to manage: remote wake-up, management counter, LPI - * interrupts. - */ -static irqreturn_t stmmac_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *)dev_id; - struct stmmac_priv *priv = netdev_priv(dev); - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - /* Check if a fatal error happened */ - if (stmmac_safety_feat_interrupt(priv)) - return IRQ_HANDLED; - - /* To handle Common interrupts */ - stmmac_common_interrupt(priv); - - /* To handle DMA interrupts */ - stmmac_dma_interrupt(priv); - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *)dev_id; - struct stmmac_priv *priv = netdev_priv(dev); - - if (unlikely(!dev)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - /* To handle Common interrupts */ - stmmac_common_interrupt(priv); - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *)dev_id; - struct stmmac_priv *priv = netdev_priv(dev); - - if (unlikely(!dev)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - /* Check if a fatal error happened */ - stmmac_safety_feat_interrupt(priv); - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) -{ - struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; - int chan = tx_q->queue_index; - struct stmmac_priv *priv; - int status; - - priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]); - - if (unlikely(!data)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - status = stmmac_napi_check(priv, chan, DMA_DIR_TX); - - if (unlikely(status & tx_hard_error_bump_tc)) { - /* Try to bump up the dma threshold on this failure */ - stmmac_bump_dma_threshold(priv, chan); - } else if (unlikely(status == tx_hard_error)) { - stmmac_tx_err(priv, chan); - } - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) -{ - struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; - int chan = rx_q->queue_index; - struct stmmac_priv *priv; - - priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]); - - if (unlikely(!data)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - stmmac_napi_check(priv, chan, DMA_DIR_RX); - - return IRQ_HANDLED; -} - -#ifdef CONFIG_NET_POLL_CONTROLLER -/* Polling receive - used by NETCONSOLE and other diagnostic tools - * to allow network I/O with interrupts disabled. - */ -static void stmmac_poll_controller(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int i; - - /* If adapter is down, do nothing */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return; - - if (priv->plat->multi_msi_en) { - for (i = 0; i < priv->plat->rx_queues_to_use; i++) - stmmac_msi_intr_rx(0, &priv->rx_queue[i]); - - for (i = 0; i < priv->plat->tx_queues_to_use; i++) - stmmac_msi_intr_tx(0, &priv->tx_queue[i]); - } else { - disable_irq(dev->irq); - stmmac_interrupt(dev->irq, dev); - enable_irq(dev->irq); - } -} -#endif - -/** - * stmmac_ioctl - Entry point for the Ioctl - * @dev: Device pointer. - * @rq: An IOCTL specefic structure, that can contain a pointer to - * a proprietary structure used to pass information to the driver. - * @cmd: IOCTL command - * Description: - * Currently it supports the phy_mii_ioctl(...) and HW time stamping. - */ -static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -{ - struct stmmac_priv *priv = netdev_priv (dev); - int ret = -EOPNOTSUPP; - - if (!netif_running(dev)) - return -EINVAL; - - switch (cmd) { - case SIOCGMIIPHY: - case SIOCGMIIREG: - case SIOCSMIIREG: - ret = phylink_mii_ioctl(priv->phylink, rq, cmd); - break; - case SIOCSHWTSTAMP: - ret = stmmac_hwtstamp_set(dev, rq); - break; - case SIOCGHWTSTAMP: - ret = stmmac_hwtstamp_get(dev, rq); - break; - default: - break; - } - - return ret; -} - -static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, - void *cb_priv) -{ - struct stmmac_priv *priv = cb_priv; - int ret = -EOPNOTSUPP; - - if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) - return ret; - - __stmmac_disable_all_queues(priv); - - switch (type) { - case TC_SETUP_CLSU32: - ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); - break; - case TC_SETUP_CLSFLOWER: - ret = stmmac_tc_setup_cls(priv, priv, type_data); - break; - default: - break; - } - - stmmac_enable_all_queues(priv); - return ret; -} - -static LIST_HEAD(stmmac_block_cb_list); - -static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, - void *type_data) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - - switch (type) { - case TC_SETUP_BLOCK: - return flow_block_cb_setup_simple(type_data, - &stmmac_block_cb_list, - stmmac_setup_tc_block_cb, - priv, priv, true); - case TC_SETUP_QDISC_CBS: - return stmmac_tc_setup_cbs(priv, priv, type_data); - case TC_SETUP_QDISC_TAPRIO: - return stmmac_tc_setup_taprio(priv, priv, type_data); - case TC_SETUP_QDISC_ETF: - return stmmac_tc_setup_etf(priv, priv, type_data); - default: - return -EOPNOTSUPP; - } -} - -static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, - struct net_device *sb_dev) -{ - int gso = skb_shinfo(skb)->gso_type; - - if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { - /* - * There is no way to determine the number of TSO/USO - * capable Queues. Let's use always the Queue 0 - * because if TSO/USO is supported then at least this - * one will be capable. - */ - return 0; - } - - return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; -} - -static int stmmac_set_mac_address(struct net_device *ndev, void *addr) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - int ret = 0; - - ret = pm_runtime_get_sync(priv->device); - if (ret < 0) { - pm_runtime_put_noidle(priv->device); - return ret; - } - - ret = eth_mac_addr(ndev, addr); - if (ret) - goto set_mac_error; - - stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); - -set_mac_error: - pm_runtime_put(priv->device); - - return ret; -} - -#ifdef CONFIG_DEBUG_FS -static struct dentry *stmmac_fs_dir; - -static void sysfs_display_ring(void *head, int size, int extend_desc, - struct seq_file *seq, dma_addr_t dma_phy_addr) -{ - int i; - struct dma_extended_desc *ep = (struct dma_extended_desc *)head; - struct dma_desc *p = (struct dma_desc *)head; - dma_addr_t dma_addr; - - for (i = 0; i < size; i++) { - if (extend_desc) { - dma_addr = dma_phy_addr + i * sizeof(*ep); - seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", - i, &dma_addr, - le32_to_cpu(ep->basic.des0), - le32_to_cpu(ep->basic.des1), - le32_to_cpu(ep->basic.des2), - le32_to_cpu(ep->basic.des3)); - ep++; - } else { - dma_addr = dma_phy_addr + i * sizeof(*p); - seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", - i, &dma_addr, - le32_to_cpu(p->des0), le32_to_cpu(p->des1), - le32_to_cpu(p->des2), le32_to_cpu(p->des3)); - p++; - } - seq_printf(seq, "\n"); - } -} - -static int stmmac_rings_status_show(struct seq_file *seq, void *v) -{ - struct net_device *dev = seq->private; - struct stmmac_priv *priv = netdev_priv(dev); - u32 rx_count = priv->plat->rx_queues_to_use; - u32 tx_count = priv->plat->tx_queues_to_use; - u32 queue; - - if ((dev->flags & IFF_UP) == 0) - return 0; - - for (queue = 0; queue < rx_count; queue++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - seq_printf(seq, "RX Queue %d:\n", queue); - - if (priv->extend_desc) { - seq_printf(seq, "Extended descriptor ring:\n"); - sysfs_display_ring((void *)rx_q->dma_erx, - priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy); - } else { - seq_printf(seq, "Descriptor ring:\n"); - sysfs_display_ring((void *)rx_q->dma_rx, - priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy); - } - } - - for (queue = 0; queue < tx_count; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - seq_printf(seq, "TX Queue %d:\n", queue); - - if (priv->extend_desc) { - seq_printf(seq, "Extended descriptor ring:\n"); - sysfs_display_ring((void *)tx_q->dma_etx, - priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy); - } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { - seq_printf(seq, "Descriptor ring:\n"); - sysfs_display_ring((void *)tx_q->dma_tx, - priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy); - } - } - - return 0; -} -DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); - -static int stmmac_dma_cap_show(struct seq_file *seq, void *v) -{ - struct net_device *dev = seq->private; - struct stmmac_priv *priv = netdev_priv(dev); - - if (!priv->hw_cap_support) { - seq_printf(seq, "DMA HW features not supported\n"); - return 0; - } - - seq_printf(seq, "==============================\n"); - seq_printf(seq, "\tDMA HW features\n"); - seq_printf(seq, "==============================\n"); - - seq_printf(seq, "\t10/100 Mbps: %s\n", - (priv->dma_cap.mbps_10_100) ? "Y" : "N"); - seq_printf(seq, "\t1000 Mbps: %s\n", - (priv->dma_cap.mbps_1000) ? "Y" : "N"); - seq_printf(seq, "\tHalf duplex: %s\n", - (priv->dma_cap.half_duplex) ? "Y" : "N"); - seq_printf(seq, "\tHash Filter: %s\n", - (priv->dma_cap.hash_filter) ? "Y" : "N"); - seq_printf(seq, "\tMultiple MAC address registers: %s\n", - (priv->dma_cap.multi_addr) ? "Y" : "N"); - seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", - (priv->dma_cap.pcs) ? "Y" : "N"); - seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", - (priv->dma_cap.sma_mdio) ? "Y" : "N"); - seq_printf(seq, "\tPMT Remote wake up: %s\n", - (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); - seq_printf(seq, "\tPMT Magic Frame: %s\n", - (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); - seq_printf(seq, "\tRMON module: %s\n", - (priv->dma_cap.rmon) ? "Y" : "N"); - seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", - (priv->dma_cap.time_stamp) ? "Y" : "N"); - seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", - (priv->dma_cap.atime_stamp) ? "Y" : "N"); - seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", - (priv->dma_cap.eee) ? "Y" : "N"); - seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); - seq_printf(seq, "\tChecksum Offload in TX: %s\n", - (priv->dma_cap.tx_coe) ? "Y" : "N"); - if (priv->synopsys_id >= DWMAC_CORE_4_00) { - seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", - (priv->dma_cap.rx_coe) ? "Y" : "N"); - } else { - seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", - (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); - seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", - (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); - } - seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", - (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); - seq_printf(seq, "\tNumber of Additional RX channel: %d\n", - priv->dma_cap.number_rx_channel); - seq_printf(seq, "\tNumber of Additional TX channel: %d\n", - priv->dma_cap.number_tx_channel); - seq_printf(seq, "\tNumber of Additional RX queues: %d\n", - priv->dma_cap.number_rx_queues); - seq_printf(seq, "\tNumber of Additional TX queues: %d\n", - priv->dma_cap.number_tx_queues); - seq_printf(seq, "\tEnhanced descriptors: %s\n", - (priv->dma_cap.enh_desc) ? "Y" : "N"); - seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); - seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); - seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); - seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); - seq_printf(seq, "\tNumber of PPS Outputs: %d\n", - priv->dma_cap.pps_out_num); - seq_printf(seq, "\tSafety Features: %s\n", - priv->dma_cap.asp ? "Y" : "N"); - seq_printf(seq, "\tFlexible RX Parser: %s\n", - priv->dma_cap.frpsel ? "Y" : "N"); - seq_printf(seq, "\tEnhanced Addressing: %d\n", - priv->dma_cap.addr64); - seq_printf(seq, "\tReceive Side Scaling: %s\n", - priv->dma_cap.rssen ? "Y" : "N"); - seq_printf(seq, "\tVLAN Hash Filtering: %s\n", - priv->dma_cap.vlhash ? "Y" : "N"); - seq_printf(seq, "\tSplit Header: %s\n", - priv->dma_cap.sphen ? "Y" : "N"); - seq_printf(seq, "\tVLAN TX Insertion: %s\n", - priv->dma_cap.vlins ? "Y" : "N"); - seq_printf(seq, "\tDouble VLAN: %s\n", - priv->dma_cap.dvlan ? "Y" : "N"); - seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", - priv->dma_cap.l3l4fnum); - seq_printf(seq, "\tARP Offloading: %s\n", - priv->dma_cap.arpoffsel ? "Y" : "N"); - seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", - priv->dma_cap.estsel ? "Y" : "N"); - seq_printf(seq, "\tFrame Preemption (FPE): %s\n", - priv->dma_cap.fpesel ? "Y" : "N"); - seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", - priv->dma_cap.tbssel ? "Y" : "N"); - return 0; -} -DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); - -/* Use network device events to rename debugfs file entries. - */ -static int stmmac_device_event(struct notifier_block *unused, - unsigned long event, void *ptr) -{ - struct net_device *dev = netdev_notifier_info_to_dev(ptr); - struct stmmac_priv *priv = netdev_priv(dev); - - if (dev->netdev_ops != &stmmac_netdev_ops) - goto done; - - switch (event) { - case NETDEV_CHANGENAME: - if (priv->dbgfs_dir) - priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, - priv->dbgfs_dir, - stmmac_fs_dir, - dev->name); - break; - } -done: - return NOTIFY_DONE; -} - -static struct notifier_block stmmac_notifier = { - .notifier_call = stmmac_device_event, -}; - -static void stmmac_init_fs(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - rtnl_lock(); - - /* Create per netdev entries */ - priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); - - /* Entry to report DMA RX/TX rings */ - debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, - &stmmac_rings_status_fops); - - /* Entry to report the DMA HW features */ - debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, - &stmmac_dma_cap_fops); - - rtnl_unlock(); -} - -static void stmmac_exit_fs(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - debugfs_remove_recursive(priv->dbgfs_dir); -} -#endif /* CONFIG_DEBUG_FS */ - -static u32 stmmac_vid_crc32_le(__le16 vid_le) -{ - unsigned char *data = (unsigned char *)&vid_le; - unsigned char data_byte = 0; - u32 crc = ~0x0; - u32 temp = 0; - int i, bits; - - bits = get_bitmask_order(VLAN_VID_MASK); - for (i = 0; i < bits; i++) { - if ((i % 8) == 0) - data_byte = data[i / 8]; - - temp = ((crc & 1) ^ data_byte) & 1; - crc >>= 1; - data_byte >>= 1; - - if (temp) - crc ^= 0xedb88320; - } - - return crc; -} - -static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) -{ - u32 crc, hash = 0; - __le16 pmatch = 0; - int count = 0; - u16 vid = 0; - - for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { - __le16 vid_le = cpu_to_le16(vid); - crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; - hash |= (1 << crc); - count++; - } - - if (!priv->dma_cap.vlhash) { - if (count > 2) /* VID = 0 always passes filter */ - return -EOPNOTSUPP; - - pmatch = cpu_to_le16(vid); - hash = 0; - } - - return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); -} - -static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - bool is_double = false; - int ret; - - if (be16_to_cpu(proto) == ETH_P_8021AD) - is_double = true; - - set_bit(vid, priv->active_vlans); - ret = stmmac_vlan_update(priv, is_double); - if (ret) { - clear_bit(vid, priv->active_vlans); - return ret; - } - - if (priv->hw->num_vlan) { - ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); - if (ret) - return ret; - } - - return 0; -} - -static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - bool is_double = false; - int ret; - - ret = pm_runtime_get_sync(priv->device); - if (ret < 0) { - pm_runtime_put_noidle(priv->device); - return ret; - } - - if (be16_to_cpu(proto) == ETH_P_8021AD) - is_double = true; - - clear_bit(vid, priv->active_vlans); - - if (priv->hw->num_vlan) { - ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); - if (ret) - goto del_vlan_error; - } - - ret = stmmac_vlan_update(priv, is_double); - -del_vlan_error: - pm_runtime_put(priv->device); - - return ret; -} - -static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - switch (bpf->command) { - case XDP_SETUP_PROG: - return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); - case XDP_SETUP_XSK_POOL: - return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, - bpf->xsk.queue_id); - default: - return -EOPNOTSUPP; - } -} - -static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, - struct xdp_frame **frames, u32 flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int cpu = smp_processor_id(); - struct netdev_queue *nq; - int i, nxmit = 0; - int queue; - - if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) - return -ENETDOWN; - - if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) - return -EINVAL; - - queue = stmmac_xdp_get_tx_queue(priv, cpu); - nq = netdev_get_tx_queue(priv->dev, queue); - - __netif_tx_lock(nq, cpu); - /* Avoids TX time-out as we are sharing with slow path */ - txq_trans_cond_update(nq); - - for (i = 0; i < num_frames; i++) { - int res; - - res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); - if (res == STMMAC_XDP_CONSUMED) - break; - - nxmit++; - } - - if (flags & XDP_XMIT_FLUSH) { - stmmac_flush_tx_descriptors(priv, queue); - stmmac_tx_timer_arm(priv, queue); - } - - __netif_tx_unlock(nq); - - return nxmit; -} - -void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); - - stmmac_stop_rx_dma(priv, queue); - __free_dma_rx_desc_resources(priv, queue); -} - -void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - u32 buf_size; - int ret; - - ret = __alloc_dma_rx_desc_resources(priv, queue); - if (ret) { - netdev_err(priv->dev, "Failed to alloc RX desc.\n"); - return; - } - - ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL); - if (ret) { - __free_dma_rx_desc_resources(priv, queue); - netdev_err(priv->dev, "Failed to init RX desc.\n"); - return; - } - - stmmac_clear_rx_descriptors(priv, queue); - - stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - rx_q->dma_rx_phy, rx_q->queue_index); - - rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * - sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, - rx_q->rx_tail_addr, rx_q->queue_index); - - if (rx_q->xsk_pool && rx_q->buf_alloc_num) { - buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); - stmmac_set_dma_bfsize(priv, priv->ioaddr, - buf_size, - rx_q->queue_index); - } else { - stmmac_set_dma_bfsize(priv, priv->ioaddr, - priv->dma_buf_sz, - rx_q->queue_index); - } - - stmmac_start_rx_dma(priv, queue); - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); -} - -void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - - stmmac_stop_tx_dma(priv, queue); - __free_dma_tx_desc_resources(priv, queue); -} - -void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - int ret; - - ret = __alloc_dma_tx_desc_resources(priv, queue); - if (ret) { - netdev_err(priv->dev, "Failed to alloc TX desc.\n"); - return; - } - - ret = __init_dma_tx_desc_rings(priv, queue); - if (ret) { - __free_dma_tx_desc_resources(priv, queue); - netdev_err(priv->dev, "Failed to init TX desc.\n"); - return; - } - - stmmac_clear_tx_descriptors(priv, queue); - - stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - tx_q->dma_tx_phy, tx_q->queue_index); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); - - tx_q->tx_tail_addr = tx_q->dma_tx_phy; - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, - tx_q->tx_tail_addr, tx_q->queue_index); - - stmmac_start_tx_dma(priv, queue); - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); -} - -void stmmac_xdp_release(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 chan; - - /* Disable NAPI process */ - stmmac_disable_all_queues(priv); - - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - /* Free the IRQ lines */ - stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); - - /* Stop TX/RX DMA channels */ - stmmac_stop_all_dma(priv); - - /* Release and free the Rx/Tx resources */ - free_dma_desc_resources(priv); - - /* Disable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, false); - - /* set trans_start so we don't get spurious - * watchdogs during reset - */ - netif_trans_update(dev); - netif_carrier_off(dev); -} - -int stmmac_xdp_open(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 rx_cnt = priv->plat->rx_queues_to_use; - u32 tx_cnt = priv->plat->tx_queues_to_use; - u32 dma_csr_ch = max(rx_cnt, tx_cnt); - struct stmmac_rx_queue *rx_q; - struct stmmac_tx_queue *tx_q; - u32 buf_size; - bool sph_en; - u32 chan; - int ret; - - ret = alloc_dma_desc_resources(priv); - if (ret < 0) { - netdev_err(dev, "%s: DMA descriptors allocation failed\n", - __func__); - goto dma_desc_error; - } - - ret = init_dma_desc_rings(dev, GFP_KERNEL); - if (ret < 0) { - netdev_err(dev, "%s: DMA descriptors initialization failed\n", - __func__); - goto init_error; - } - - /* DMA CSR Channel configuration */ - for (chan = 0; chan < dma_csr_ch; chan++) - stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); - - /* Adjust Split header */ - sph_en = (priv->hw->rx_csum > 0) && priv->sph; - - /* DMA RX Channel Configuration */ - for (chan = 0; chan < rx_cnt; chan++) { - rx_q = &priv->rx_queue[chan]; - - stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - rx_q->dma_rx_phy, chan); - - rx_q->rx_tail_addr = rx_q->dma_rx_phy + - (rx_q->buf_alloc_num * - sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, - rx_q->rx_tail_addr, chan); - - if (rx_q->xsk_pool && rx_q->buf_alloc_num) { - buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); - stmmac_set_dma_bfsize(priv, priv->ioaddr, - buf_size, - rx_q->queue_index); - } else { - stmmac_set_dma_bfsize(priv, priv->ioaddr, - priv->dma_buf_sz, - rx_q->queue_index); - } - - stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); - } - - /* DMA TX Channel Configuration */ - for (chan = 0; chan < tx_cnt; chan++) { - tx_q = &priv->tx_queue[chan]; - - stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - tx_q->dma_tx_phy, chan); - - tx_q->tx_tail_addr = tx_q->dma_tx_phy; - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, - tx_q->tx_tail_addr, chan); - - hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - tx_q->txtimer.function = stmmac_tx_timer; - } - - /* Enable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, true); - - /* Start Rx & Tx DMA Channels */ - stmmac_start_all_dma(priv); - - ret = stmmac_request_irq(dev); - if (ret) - goto irq_error; - - /* Enable NAPI process*/ - stmmac_enable_all_queues(priv); - netif_carrier_on(dev); - netif_tx_start_all_queues(dev); - - return 0; - -irq_error: - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - stmmac_hw_teardown(dev); -init_error: - free_dma_desc_resources(priv); -dma_desc_error: - return ret; -} - -int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct stmmac_rx_queue *rx_q; - struct stmmac_tx_queue *tx_q; - struct stmmac_channel *ch; - - if (test_bit(STMMAC_DOWN, &priv->state) || - !netif_carrier_ok(priv->dev)) - return -ENETDOWN; - - if (!stmmac_xdp_is_enabled(priv)) - return -ENXIO; - - if (queue >= priv->plat->rx_queues_to_use || - queue >= priv->plat->tx_queues_to_use) - return -EINVAL; - - rx_q = &priv->rx_queue[queue]; - tx_q = &priv->tx_queue[queue]; - ch = &priv->channel[queue]; - - if (!rx_q->xsk_pool && !tx_q->xsk_pool) - return -ENXIO; - - if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { - /* EQoS does not have per-DMA channel SW interrupt, - * so we schedule RX Napi straight-away. - */ - if (likely(napi_schedule_prep(&ch->rxtx_napi))) - __napi_schedule(&ch->rxtx_napi); - } - - return 0; -} - -static const struct net_device_ops stmmac_netdev_ops = { - .ndo_open = stmmac_open, - .ndo_start_xmit = stmmac_xmit, - .ndo_stop = stmmac_release, - .ndo_change_mtu = stmmac_change_mtu, - .ndo_fix_features = stmmac_fix_features, - .ndo_set_features = stmmac_set_features, - .ndo_set_rx_mode = stmmac_set_rx_mode, - .ndo_tx_timeout = stmmac_tx_timeout, - .ndo_eth_ioctl = stmmac_ioctl, - .ndo_setup_tc = stmmac_setup_tc, - .ndo_select_queue = stmmac_select_queue, -#ifdef CONFIG_NET_POLL_CONTROLLER - .ndo_poll_controller = stmmac_poll_controller, -#endif - .ndo_set_mac_address = stmmac_set_mac_address, - .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, - .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, - .ndo_bpf = stmmac_bpf, - .ndo_xdp_xmit = stmmac_xdp_xmit, - .ndo_xsk_wakeup = stmmac_xsk_wakeup, -}; - -static void stmmac_reset_subtask(struct stmmac_priv *priv) -{ - if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) - return; - if (test_bit(STMMAC_DOWN, &priv->state)) - return; - - netdev_err(priv->dev, "Reset adapter.\n"); - - rtnl_lock(); - netif_trans_update(priv->dev); - while (test_and_set_bit(STMMAC_RESETING, &priv->state)) - usleep_range(1000, 2000); - - set_bit(STMMAC_DOWN, &priv->state); - dev_close(priv->dev); - dev_open(priv->dev, NULL); - clear_bit(STMMAC_DOWN, &priv->state); - clear_bit(STMMAC_RESETING, &priv->state); - rtnl_unlock(); -} - -static void stmmac_service_task(struct work_struct *work) -{ - struct stmmac_priv *priv = container_of(work, struct stmmac_priv, - service_task); - - stmmac_reset_subtask(priv); - clear_bit(STMMAC_SERVICE_SCHED, &priv->state); -} - -/** - * stmmac_hw_init - Init the MAC device - * @priv: driver private structure - * Description: this function is to configure the MAC device according to - * some platform parameters or the HW capability register. It prepares the - * driver to use either ring or chain modes and to setup either enhanced or - * normal descriptors. - */ -static int stmmac_hw_init(struct stmmac_priv *priv) -{ - int ret; - - /* dwmac-sun8i only work in chain mode */ - if (priv->plat->has_sun8i) - chain_mode = 1; - priv->chain_mode = chain_mode; - - /* Initialize HW Interface */ - ret = stmmac_hwif_init(priv); - if (ret) - return ret; - - /* Get the HW capability (new GMAC newer than 3.50a) */ - priv->hw_cap_support = stmmac_get_hw_features(priv); - if (priv->hw_cap_support) { - dev_info(priv->device, "DMA HW capability register supported\n"); - - /* We can override some gmac/dma configuration fields: e.g. - * enh_desc, tx_coe (e.g. that are passed through the - * platform) with the values from the HW capability - * register (if supported). - */ - priv->plat->enh_desc = priv->dma_cap.enh_desc; - priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && - !priv->plat->use_phy_wol; - priv->hw->pmt = priv->plat->pmt; - if (priv->dma_cap.hash_tb_sz) { - priv->hw->multicast_filter_bins = - (BIT(priv->dma_cap.hash_tb_sz) << 5); - priv->hw->mcast_bits_log2 = - ilog2(priv->hw->multicast_filter_bins); - } - - /* TXCOE doesn't work in thresh DMA mode */ - if (priv->plat->force_thresh_dma_mode) - priv->plat->tx_coe = 0; - else - priv->plat->tx_coe = priv->dma_cap.tx_coe; - - /* In case of GMAC4 rx_coe is from HW cap register. */ - priv->plat->rx_coe = priv->dma_cap.rx_coe; - - if (priv->dma_cap.rx_coe_type2) - priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; - else if (priv->dma_cap.rx_coe_type1) - priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; - - } else { - dev_info(priv->device, "No HW DMA feature register supported\n"); - } - - if (priv->plat->rx_coe) { - priv->hw->rx_csum = priv->plat->rx_coe; - dev_info(priv->device, "RX Checksum Offload Engine supported\n"); - if (priv->synopsys_id < DWMAC_CORE_4_00) - dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); - } - if (priv->plat->tx_coe) - dev_info(priv->device, "TX Checksum insertion supported\n"); - - if (priv->plat->pmt) { - dev_info(priv->device, "Wake-Up On Lan supported\n"); - device_set_wakeup_capable(priv->device, 1); - } - - if (priv->dma_cap.tsoen) - dev_info(priv->device, "TSO supported\n"); - - priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; - priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; - - /* Run HW quirks, if any */ - if (priv->hwif_quirks) { - ret = priv->hwif_quirks(priv); - if (ret) - return ret; - } - - /* Rx Watchdog is available in the COREs newer than the 3.40. - * In some case, for example on bugged HW this feature - * has to be disable and this can be done by passing the - * riwt_off field from the platform. - */ - if (((priv->synopsys_id >= DWMAC_CORE_3_50) || - (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { - priv->use_riwt = 1; - dev_info(priv->device, - "Enable RX Mitigation via HW Watchdog Timer\n"); - } - - return 0; -} - -static void stmmac_napi_add(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 queue, maxq; - - maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - ch->priv_data = priv; - ch->index = queue; - spin_lock_init(&ch->lock); - - if (queue < priv->plat->rx_queues_to_use) { - netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, - NAPI_POLL_WEIGHT); - } - if (queue < priv->plat->tx_queues_to_use) { - netif_tx_napi_add(dev, &ch->tx_napi, - stmmac_napi_poll_tx, - NAPI_POLL_WEIGHT); - } - if (queue < priv->plat->rx_queues_to_use && - queue < priv->plat->tx_queues_to_use) { - netif_napi_add(dev, &ch->rxtx_napi, - stmmac_napi_poll_rxtx, - NAPI_POLL_WEIGHT); - } - } -} - -static void stmmac_napi_del(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 queue, maxq; - - maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - if (queue < priv->plat->rx_queues_to_use) - netif_napi_del(&ch->rx_napi); - if (queue < priv->plat->tx_queues_to_use) - netif_napi_del(&ch->tx_napi); - if (queue < priv->plat->rx_queues_to_use && - queue < priv->plat->tx_queues_to_use) { - netif_napi_del(&ch->rxtx_napi); - } - } -} - -int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret = 0; - - if (netif_running(dev)) - stmmac_release(dev); - - stmmac_napi_del(dev); - - priv->plat->rx_queues_to_use = rx_cnt; - priv->plat->tx_queues_to_use = tx_cnt; - - stmmac_napi_add(dev); - - if (netif_running(dev)) - ret = stmmac_open(dev); - - return ret; -} - -int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret = 0; - - if (netif_running(dev)) - stmmac_release(dev); - - priv->dma_rx_size = rx_size; - priv->dma_tx_size = tx_size; - - if (netif_running(dev)) - ret = stmmac_open(dev); - - return ret; -} - -#define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" -static void stmmac_fpe_lp_task(struct work_struct *work) -{ - struct stmmac_priv *priv = container_of(work, struct stmmac_priv, - fpe_task); - struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; - enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; - enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; - bool *hs_enable = &fpe_cfg->hs_enable; - bool *enable = &fpe_cfg->enable; - int retries = 20; - - while (retries-- > 0) { - /* Bail out immediately if FPE handshake is OFF */ - if (*lo_state == FPE_STATE_OFF || !*hs_enable) - break; - - if (*lo_state == FPE_STATE_ENTERING_ON && - *lp_state == FPE_STATE_ENTERING_ON) { - stmmac_fpe_configure(priv, priv->ioaddr, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, - *enable); - - netdev_info(priv->dev, "configured FPE\n"); - - *lo_state = FPE_STATE_ON; - *lp_state = FPE_STATE_ON; - netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); - break; - } - - if ((*lo_state == FPE_STATE_CAPABLE || - *lo_state == FPE_STATE_ENTERING_ON) && - *lp_state != FPE_STATE_ON) { - netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, - *lo_state, *lp_state); - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - MPACKET_VERIFY); - } - /* Sleep then retry */ - msleep(500); - } - - clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); -} - -void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) -{ - if (priv->plat->fpe_cfg->hs_enable != enable) { - if (enable) { - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - MPACKET_VERIFY); - } else { - priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; - priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; - } - - priv->plat->fpe_cfg->hs_enable = enable; - } -} - -/** - * stmmac_dvr_probe - * @device: device pointer - * @plat_dat: platform data pointer - * @res: stmmac resource pointer - * Description: this is the main probe function used to - * call the alloc_etherdev, allocate the priv structure. - * Return: - * returns 0 on success, otherwise errno. - */ -int stmmac_dvr_probe(struct device *device, - struct plat_stmmacenet_data *plat_dat, - struct stmmac_resources *res) -{ - struct net_device *ndev = NULL; - struct stmmac_priv *priv; - u32 rxq; - int i, ret = 0; - - ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), - MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); - if (!ndev) - return -ENOMEM; - - SET_NETDEV_DEV(ndev, device); - - priv = netdev_priv(ndev); - priv->device = device; - priv->dev = ndev; - - stmmac_set_ethtool_ops(ndev); - priv->pause = pause; - priv->plat = plat_dat; - priv->ioaddr = res->addr; - priv->dev->base_addr = (unsigned long)res->addr; - priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; - - priv->dev->irq = res->irq; - priv->wol_irq = res->wol_irq; - priv->lpi_irq = res->lpi_irq; - priv->sfty_ce_irq = res->sfty_ce_irq; - priv->sfty_ue_irq = res->sfty_ue_irq; - for (i = 0; i < MTL_MAX_RX_QUEUES; i++) - priv->rx_irq[i] = res->rx_irq[i]; - for (i = 0; i < MTL_MAX_TX_QUEUES; i++) - priv->tx_irq[i] = res->tx_irq[i]; - - if (!is_zero_ether_addr(res->mac)) - eth_hw_addr_set(priv->dev, res->mac); - - dev_set_drvdata(device, priv->dev); - - /* Verify driver arguments */ - stmmac_verify_args(); - - priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); - if (!priv->af_xdp_zc_qps) - return -ENOMEM; - - /* Allocate workqueue */ - priv->wq = create_singlethread_workqueue("stmmac_wq"); - if (!priv->wq) { - dev_err(priv->device, "failed to create workqueue\n"); - return -ENOMEM; - } - - INIT_WORK(&priv->service_task, stmmac_service_task); - - /* Initialize Link Partner FPE workqueue */ - INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); - - /* Override with kernel parameters if supplied XXX CRS XXX - * this needs to have multiple instances - */ - if ((phyaddr >= 0) && (phyaddr <= 31)) - priv->plat->phy_addr = phyaddr; - - if (priv->plat->stmmac_rst) { - ret = reset_control_assert(priv->plat->stmmac_rst); - reset_control_deassert(priv->plat->stmmac_rst); - /* Some reset controllers have only reset callback instead of - * assert + deassert callbacks pair. - */ - if (ret == -ENOTSUPP) - reset_control_reset(priv->plat->stmmac_rst); - } - - ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); - if (ret == -ENOTSUPP) - dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", - ERR_PTR(ret)); - - /* Init MAC and get the capabilities */ - ret = stmmac_hw_init(priv); - if (ret) - goto error_hw_init; - - /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. - */ - if (priv->synopsys_id < DWMAC_CORE_5_20) - priv->plat->dma_cfg->dche = false; - - stmmac_check_ether_addr(priv); - - ndev->netdev_ops = &stmmac_netdev_ops; - - ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | - NETIF_F_RXCSUM; - - ret = stmmac_tc_init(priv, priv); - if (!ret) { - ndev->hw_features |= NETIF_F_HW_TC; - } - - if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { - ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; - if (priv->plat->has_gmac4) - ndev->hw_features |= NETIF_F_GSO_UDP_L4; - priv->tso = true; - dev_info(priv->device, "TSO feature enabled\n"); - } - - if (priv->dma_cap.sphen) { - ndev->hw_features |= NETIF_F_GRO; - priv->sph_cap = true; - priv->sph = priv->sph_cap; - dev_info(priv->device, "SPH feature enabled\n"); - } - - /* The current IP register MAC_HW_Feature1[ADDR64] only define - * 32/40/64 bit width, but some SOC support others like i.MX8MP - * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. - * So overwrite dma_cap.addr64 according to HW real design. - */ - if (priv->plat->addr64) - priv->dma_cap.addr64 = priv->plat->addr64; - - if (priv->dma_cap.addr64) { - ret = dma_set_mask_and_coherent(device, - DMA_BIT_MASK(priv->dma_cap.addr64)); - if (!ret) { - dev_info(priv->device, "Using %d bits DMA width\n", - priv->dma_cap.addr64); - - /* - * If more than 32 bits can be addressed, make sure to - * enable enhanced addressing mode. - */ - if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) - priv->plat->dma_cfg->eame = true; - } else { - ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); - if (ret) { - dev_err(priv->device, "Failed to set DMA Mask\n"); - goto error_hw_init; - } - - priv->dma_cap.addr64 = 32; - } - } - - ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; - ndev->watchdog_timeo = msecs_to_jiffies(watchdog); -#ifdef STMMAC_VLAN_TAG_USED - /* Both mac100 and gmac support receive VLAN tag detection */ - ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; - if (priv->dma_cap.vlhash) { - ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; - ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; - } - if (priv->dma_cap.vlins) { - ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; - if (priv->dma_cap.dvlan) - ndev->features |= NETIF_F_HW_VLAN_STAG_TX; - } -#endif - priv->msg_enable = netif_msg_init(debug, default_msg_level); - - /* Initialize RSS */ - rxq = priv->plat->rx_queues_to_use; - netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); - for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) - priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); - - if (priv->dma_cap.rssen && priv->plat->rss_en) - ndev->features |= NETIF_F_RXHASH; - - /* MTU range: 46 - hw-specific max */ - ndev->min_mtu = ETH_ZLEN - ETH_HLEN; - if (priv->plat->has_xgmac) - ndev->max_mtu = XGMAC_JUMBO_LEN; - else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) - ndev->max_mtu = JUMBO_LEN; - else - ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); - /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu - * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. - */ - if ((priv->plat->maxmtu < ndev->max_mtu) && - (priv->plat->maxmtu >= ndev->min_mtu)) - ndev->max_mtu = priv->plat->maxmtu; - else if (priv->plat->maxmtu < ndev->min_mtu) - dev_warn(priv->device, - "%s: warning: maxmtu having invalid value (%d)\n", - __func__, priv->plat->maxmtu); - - if (flow_ctrl) - priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ - - /* Setup channels NAPI */ - stmmac_napi_add(ndev); - - mutex_init(&priv->lock); - - /* If a specific clk_csr value is passed from the platform - * this means that the CSR Clock Range selection cannot be - * changed at run-time and it is fixed. Viceversa the driver'll try to - * set the MDC clock dynamically according to the csr actual - * clock input. - */ - if (priv->plat->clk_csr >= 0) - priv->clk_csr = priv->plat->clk_csr; - else - stmmac_clk_csr_set(priv); - - stmmac_check_pcs_mode(priv); - - pm_runtime_get_noresume(device); - pm_runtime_set_active(device); -<<<<<<< - if (!pm_runtime_enabled(device)) - pm_runtime_enable(device); -======= - pm_runtime_enable(device); - /* - * Prevent runtime pm from being ON by default. Users can enable - * it using power/control in sysfs. - */ - pm_runtime_forbid(device); ->>>>>>> - - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI) { - /* MDIO bus Registration */ - ret = stmmac_mdio_register(ndev); - if (ret < 0) { - dev_err(priv->device, - "%s: MDIO bus (id: %d) registration failed", - __func__, priv->plat->bus_id); - goto error_mdio_register; - } - } - - if (priv->plat->speed_mode_2500) - priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); - - if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { - ret = stmmac_xpcs_setup(priv->mii); - if (ret) - goto error_xpcs_setup; - } - - ret = stmmac_phy_setup(priv); - if (ret) { - netdev_err(ndev, "failed to setup phy (%d)\n", ret); - goto error_phy_setup; - } - - ret = register_netdev(ndev); - if (ret) { - dev_err(priv->device, "%s: ERROR %i registering the device\n", - __func__, ret); - goto error_netdev_register; - } - - if (priv->plat->serdes_powerup) { - ret = priv->plat->serdes_powerup(ndev, - priv->plat->bsp_priv); - - if (ret < 0) - goto error_serdes_powerup; - } - -#ifdef CONFIG_DEBUG_FS - stmmac_init_fs(ndev); -#endif - - if (priv->plat->dump_debug_regs) - priv->plat->dump_debug_regs(priv->plat->bsp_priv); - - /* Let pm_runtime_put() disable the clocks. - * If CONFIG_PM is not enabled, the clocks will stay powered. - */ - pm_runtime_put(device); - - return ret; - -error_serdes_powerup: - unregister_netdev(ndev); -error_netdev_register: - phylink_destroy(priv->phylink); -error_xpcs_setup: -error_phy_setup: - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI) - stmmac_mdio_unregister(ndev); -error_mdio_register: - stmmac_napi_del(ndev); -error_hw_init: - destroy_workqueue(priv->wq); - bitmap_free(priv->af_xdp_zc_qps); - - return ret; -} -EXPORT_SYMBOL_GPL(stmmac_dvr_probe); - -/** - * stmmac_dvr_remove - * @dev: device pointer - * Description: this function resets the TX/RX processes, disables the MAC RX/TX - * changes the link status, releases the DMA descriptor rings. - */ -int stmmac_dvr_remove(struct device *dev) -{ - struct net_device *ndev = dev_get_drvdata(dev); - struct stmmac_priv *priv = netdev_priv(ndev); - - netdev_info(priv->dev, "%s: removing driver", __func__); - - pm_runtime_get_sync(dev); - pm_runtime_disable(dev); - pm_runtime_put_noidle(dev); - - stmmac_stop_all_dma(priv); - stmmac_mac_set(priv, priv->ioaddr, false); - netif_carrier_off(ndev); - unregister_netdev(ndev); - - /* Serdes power down needs to happen after VLAN filter - * is deleted that is triggered by unregister_netdev(). - */ - if (priv->plat->serdes_powerdown) - priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); - -#ifdef CONFIG_DEBUG_FS - stmmac_exit_fs(ndev); -#endif - phylink_destroy(priv->phylink); - if (priv->plat->stmmac_rst) - reset_control_assert(priv->plat->stmmac_rst); - reset_control_assert(priv->plat->stmmac_ahb_rst); - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI) - stmmac_mdio_unregister(ndev); - destroy_workqueue(priv->wq); - mutex_destroy(&priv->lock); - bitmap_free(priv->af_xdp_zc_qps); - - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_dvr_remove); - -/** - * stmmac_suspend - suspend callback - * @dev: device pointer - * Description: this is the function to suspend the device and it is called - * by the platform driver to stop the network queue, release the resources, - * program the PMT register (for WoL), clean and release driver resources. - */ -int stmmac_suspend(struct device *dev) -{ - struct net_device *ndev = dev_get_drvdata(dev); - struct stmmac_priv *priv = netdev_priv(ndev); - u32 chan; - - if (!ndev || !netif_running(ndev)) - return 0; - - mutex_lock(&priv->lock); - - netif_device_detach(ndev); - - stmmac_disable_all_queues(priv); - - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - if (priv->eee_enabled) { - priv->tx_path_in_lpi_mode = false; - del_timer_sync(&priv->eee_ctrl_timer); - } - - /* Stop TX/RX DMA */ - stmmac_stop_all_dma(priv); - - if (priv->plat->serdes_powerdown) - priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); - - /* Enable Power down mode by programming the PMT regs */ - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - stmmac_pmt(priv, priv->hw, priv->wolopts); - priv->irq_wake = 1; - } else { - stmmac_mac_set(priv, priv->ioaddr, false); - pinctrl_pm_select_sleep_state(priv->device); - } - - mutex_unlock(&priv->lock); - - rtnl_lock(); - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - phylink_suspend(priv->phylink, true); - } else { - if (device_may_wakeup(priv->device)) - phylink_speed_down(priv->phylink, false); - phylink_suspend(priv->phylink, false); - } - rtnl_unlock(); - - if (priv->dma_cap.fpesel) { - /* Disable FPE */ - stmmac_fpe_configure(priv, priv->ioaddr, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, false); - - stmmac_fpe_handshake(priv, false); - stmmac_fpe_stop_wq(priv); - } - - priv->speed = SPEED_UNKNOWN; - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_suspend); - -/** - * stmmac_reset_queues_param - reset queue parameters - * @priv: device pointer - */ -static void stmmac_reset_queues_param(struct stmmac_priv *priv) -{ - u32 rx_cnt = priv->plat->rx_queues_to_use; - u32 tx_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - for (queue = 0; queue < rx_cnt; queue++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - rx_q->cur_rx = 0; - rx_q->dirty_rx = 0; - } - - for (queue = 0; queue < tx_cnt; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - tx_q->cur_tx = 0; - tx_q->dirty_tx = 0; - tx_q->mss = 0; - - netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); - } -} - -/** - * stmmac_resume - resume callback - * @dev: device pointer - * Description: when resume this function is invoked to setup the DMA and CORE - * in a usable state. - */ -int stmmac_resume(struct device *dev) -{ - struct net_device *ndev = dev_get_drvdata(dev); - struct stmmac_priv *priv = netdev_priv(ndev); - int ret; - - if (!netif_running(ndev)) - return 0; - - /* Power Down bit, into the PM register, is cleared - * automatically as soon as a magic packet or a Wake-up frame - * is received. Anyway, it's better to manually clear - * this bit because it can generate problems while resuming - * from another devices (e.g. serial console). - */ - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - mutex_lock(&priv->lock); - stmmac_pmt(priv, priv->hw, 0); - mutex_unlock(&priv->lock); - priv->irq_wake = 0; - } else { - pinctrl_pm_select_default_state(priv->device); - /* reset the phy so that it's ready */ - if (priv->mii) - stmmac_mdio_reset(priv->mii); - } - - if (priv->plat->serdes_powerup) { - ret = priv->plat->serdes_powerup(ndev, - priv->plat->bsp_priv); - - if (ret < 0) - return ret; - } - - rtnl_lock(); - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - phylink_resume(priv->phylink); - } else { - phylink_resume(priv->phylink); - if (device_may_wakeup(priv->device)) - phylink_speed_up(priv->phylink); - } - rtnl_unlock(); - - rtnl_lock(); - mutex_lock(&priv->lock); - - stmmac_reset_queues_param(priv); - - stmmac_free_tx_skbufs(priv); - stmmac_clear_descriptors(priv); - - stmmac_hw_setup(ndev, false); - stmmac_init_coalesce(priv); - stmmac_set_rx_mode(ndev); - - stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); - - stmmac_enable_all_queues(priv); - - mutex_unlock(&priv->lock); - rtnl_unlock(); - - netif_device_attach(ndev); - - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_resume); - -#ifndef MODULE -static int __init stmmac_cmdline_opt(char *str) -{ - char *opt; - - if (!str || !*str) - return -EINVAL; - while ((opt = strsep(&str, ",")) != NULL) { - if (!strncmp(opt, "debug:", 6)) { - if (kstrtoint(opt + 6, 0, &debug)) - goto err; - } else if (!strncmp(opt, "phyaddr:", 8)) { - if (kstrtoint(opt + 8, 0, &phyaddr)) - goto err; - } else if (!strncmp(opt, "buf_sz:", 7)) { - if (kstrtoint(opt + 7, 0, &buf_sz)) - goto err; - } else if (!strncmp(opt, "tc:", 3)) { - if (kstrtoint(opt + 3, 0, &tc)) - goto err; - } else if (!strncmp(opt, "watchdog:", 9)) { - if (kstrtoint(opt + 9, 0, &watchdog)) - goto err; - } else if (!strncmp(opt, "flow_ctrl:", 10)) { - if (kstrtoint(opt + 10, 0, &flow_ctrl)) - goto err; - } else if (!strncmp(opt, "pause:", 6)) { - if (kstrtoint(opt + 6, 0, &pause)) - goto err; - } else if (!strncmp(opt, "eee_timer:", 10)) { - if (kstrtoint(opt + 10, 0, &eee_timer)) - goto err; - } else if (!strncmp(opt, "chain_mode:", 11)) { - if (kstrtoint(opt + 11, 0, &chain_mode)) - goto err; - } - } - return 0; - -err: - pr_err("%s: ERROR broken module parameter conversion", __func__); - return -EINVAL; -} - -__setup("stmmaceth=", stmmac_cmdline_opt); -#endif /* MODULE */ - -static int __init stmmac_init(void) -{ -#ifdef CONFIG_DEBUG_FS - /* Create debugfs main directory if it doesn't exist yet */ - if (!stmmac_fs_dir) - stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); - register_netdevice_notifier(&stmmac_notifier); -#endif - - return 0; -} - -static void __exit stmmac_exit(void) -{ -#ifdef CONFIG_DEBUG_FS - unregister_netdevice_notifier(&stmmac_notifier); - debugfs_remove_recursive(stmmac_fs_dir); -#endif -} - -module_init(stmmac_init) -module_exit(stmmac_exit) - -MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); -MODULE_AUTHOR("Giuseppe Cavallaro "); -MODULE_LICENSE("GPL"); diff --git a/rr-cache/8c2b8bf507854aaf7c7a64fde16df892d508760f/preimage.2 b/rr-cache/8c2b8bf507854aaf7c7a64fde16df892d508760f/preimage.2 deleted file mode 100644 index eea2954..0000000 --- a/rr-cache/8c2b8bf507854aaf7c7a64fde16df892d508760f/preimage.2 +++ /dev/null @@ -1,7541 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/******************************************************************************* - This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. - ST Ethernet IPs are built around a Synopsys IP Core. - - Copyright(C) 2007-2011 STMicroelectronics Ltd - - - Author: Giuseppe Cavallaro - - Documentation available at: - http://www.stlinux.com - Support available at: - https://bugzilla.stlinux.com/ -*******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_DEBUG_FS -#include -#include -#endif /* CONFIG_DEBUG_FS */ -#include -#include -#include -#include -#include -#include -#include "stmmac_ptp.h" -#include "stmmac.h" -#include "stmmac_xdp.h" -#include -#include -#include "dwmac1000.h" -#include "dwxgmac2.h" -#include "hwif.h" - -/* As long as the interface is active, we keep the timestamping counter enabled - * with fine resolution and binary rollover. This avoid non-monotonic behavior - * (clock jumps) when changing timestamping settings at runtime. - */ -#define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ - PTP_TCR_TSCTRLSSR) - -#define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) -#define TSO_MAX_BUFF_SIZE (SZ_16K - 1) - -/* Module parameters */ -#define TX_TIMEO 5000 -static int watchdog = TX_TIMEO; -module_param(watchdog, int, 0644); -MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); - -static int debug = -1; -module_param(debug, int, 0644); -MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); - -static int phyaddr = -1; -module_param(phyaddr, int, 0444); -MODULE_PARM_DESC(phyaddr, "Physical device address"); - -#define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4) -#define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4) - -/* Limit to make sure XDP TX and slow path can coexist */ -#define STMMAC_XSK_TX_BUDGET_MAX 256 -#define STMMAC_TX_XSK_AVAIL 16 -#define STMMAC_RX_FILL_BATCH 16 - -#define STMMAC_XDP_PASS 0 -#define STMMAC_XDP_CONSUMED BIT(0) -#define STMMAC_XDP_TX BIT(1) -#define STMMAC_XDP_REDIRECT BIT(2) - -static int flow_ctrl = FLOW_AUTO; -module_param(flow_ctrl, int, 0644); -MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); - -static int pause = PAUSE_TIME; -module_param(pause, int, 0644); -MODULE_PARM_DESC(pause, "Flow Control Pause Time"); - -#define TC_DEFAULT 64 -static int tc = TC_DEFAULT; -module_param(tc, int, 0644); -MODULE_PARM_DESC(tc, "DMA threshold control value"); - -#define DEFAULT_BUFSIZE 1536 -static int buf_sz = DEFAULT_BUFSIZE; -module_param(buf_sz, int, 0644); -MODULE_PARM_DESC(buf_sz, "DMA buffer size"); - -#define STMMAC_RX_COPYBREAK 256 - -static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | - NETIF_MSG_LINK | NETIF_MSG_IFUP | - NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); - -#define STMMAC_DEFAULT_LPI_TIMER 1000 -static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; -module_param(eee_timer, int, 0644); -MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); -#define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) - -/* By default the driver will use the ring mode to manage tx and rx descriptors, - * but allow user to force to use the chain instead of the ring - */ -static unsigned int chain_mode; -module_param(chain_mode, int, 0444); -MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); - -static irqreturn_t stmmac_interrupt(int irq, void *dev_id); -/* For MSI interrupts handling */ -static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); -static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); -static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); -static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); -static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); -static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); -static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, - u32 rxmode, u32 chan); - -#ifdef CONFIG_DEBUG_FS -static const struct net_device_ops stmmac_netdev_ops; -static void stmmac_init_fs(struct net_device *dev); -static void stmmac_exit_fs(struct net_device *dev); -#endif - -#define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) - -int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) -{ - int ret = 0; - - if (enabled) { - ret = clk_prepare_enable(priv->plat->stmmac_clk); - if (ret) - return ret; - ret = clk_prepare_enable(priv->plat->pclk); - if (ret) { - clk_disable_unprepare(priv->plat->stmmac_clk); - return ret; - } - if (priv->plat->clks_config) { - ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); - if (ret) { - clk_disable_unprepare(priv->plat->stmmac_clk); - clk_disable_unprepare(priv->plat->pclk); - return ret; - } - } - } else { - clk_disable_unprepare(priv->plat->stmmac_clk); - clk_disable_unprepare(priv->plat->pclk); - if (priv->plat->clks_config) - priv->plat->clks_config(priv->plat->bsp_priv, enabled); - } - - return ret; -} -EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); - -/** - * stmmac_verify_args - verify the driver parameters. - * Description: it checks the driver parameters and set a default in case of - * errors. - */ -static void stmmac_verify_args(void) -{ - if (unlikely(watchdog < 0)) - watchdog = TX_TIMEO; - if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) - buf_sz = DEFAULT_BUFSIZE; - if (unlikely(flow_ctrl > 1)) - flow_ctrl = FLOW_AUTO; - else if (likely(flow_ctrl < 0)) - flow_ctrl = FLOW_OFF; - if (unlikely((pause < 0) || (pause > 0xffff))) - pause = PAUSE_TIME; - if (eee_timer < 0) - eee_timer = STMMAC_DEFAULT_LPI_TIMER; -} - -static void __stmmac_disable_all_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_cnt = priv->plat->rx_queues_to_use; - u32 tx_queues_cnt = priv->plat->tx_queues_to_use; - u32 maxq = max(rx_queues_cnt, tx_queues_cnt); - u32 queue; - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - if (stmmac_xdp_is_enabled(priv) && - test_bit(queue, priv->af_xdp_zc_qps)) { - napi_disable(&ch->rxtx_napi); - continue; - } - - if (queue < rx_queues_cnt) - napi_disable(&ch->rx_napi); - if (queue < tx_queues_cnt) - napi_disable(&ch->tx_napi); - } -} - -/** - * stmmac_disable_all_queues - Disable all queues - * @priv: driver private structure - */ -static void stmmac_disable_all_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_cnt = priv->plat->rx_queues_to_use; - struct stmmac_rx_queue *rx_q; - u32 queue; - - /* synchronize_rcu() needed for pending XDP buffers to drain */ - for (queue = 0; queue < rx_queues_cnt; queue++) { - rx_q = &priv->rx_queue[queue]; - if (rx_q->xsk_pool) { - synchronize_rcu(); - break; - } - } - - __stmmac_disable_all_queues(priv); -} - -/** - * stmmac_enable_all_queues - Enable all queues - * @priv: driver private structure - */ -static void stmmac_enable_all_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_cnt = priv->plat->rx_queues_to_use; - u32 tx_queues_cnt = priv->plat->tx_queues_to_use; - u32 maxq = max(rx_queues_cnt, tx_queues_cnt); - u32 queue; - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - if (stmmac_xdp_is_enabled(priv) && - test_bit(queue, priv->af_xdp_zc_qps)) { - napi_enable(&ch->rxtx_napi); - continue; - } - - if (queue < rx_queues_cnt) - napi_enable(&ch->rx_napi); - if (queue < tx_queues_cnt) - napi_enable(&ch->tx_napi); - } -} - -static void stmmac_service_event_schedule(struct stmmac_priv *priv) -{ - if (!test_bit(STMMAC_DOWN, &priv->state) && - !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) - queue_work(priv->wq, &priv->service_task); -} - -static void stmmac_global_err(struct stmmac_priv *priv) -{ - netif_carrier_off(priv->dev); - set_bit(STMMAC_RESET_REQUESTED, &priv->state); - stmmac_service_event_schedule(priv); -} - -/** - * stmmac_clk_csr_set - dynamically set the MDC clock - * @priv: driver private structure - * Description: this is to dynamically set the MDC clock according to the csr - * clock input. - * Note: - * If a specific clk_csr value is passed from the platform - * this means that the CSR Clock Range selection cannot be - * changed at run-time and it is fixed (as reported in the driver - * documentation). Viceversa the driver will try to set the MDC - * clock dynamically according to the actual clock input. - */ -static void stmmac_clk_csr_set(struct stmmac_priv *priv) -{ - u32 clk_rate; - - clk_rate = clk_get_rate(priv->plat->stmmac_clk); - - /* Platform provided default clk_csr would be assumed valid - * for all other cases except for the below mentioned ones. - * For values higher than the IEEE 802.3 specified frequency - * we can not estimate the proper divider as it is not known - * the frequency of clk_csr_i. So we do not change the default - * divider. - */ - if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { - if (clk_rate < CSR_F_35M) - priv->clk_csr = STMMAC_CSR_20_35M; - else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) - priv->clk_csr = STMMAC_CSR_35_60M; - else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) - priv->clk_csr = STMMAC_CSR_60_100M; - else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) - priv->clk_csr = STMMAC_CSR_100_150M; - else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) - priv->clk_csr = STMMAC_CSR_150_250M; - else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) - priv->clk_csr = STMMAC_CSR_250_300M; - } - - if (priv->plat->has_sun8i) { - if (clk_rate > 160000000) - priv->clk_csr = 0x03; - else if (clk_rate > 80000000) - priv->clk_csr = 0x02; - else if (clk_rate > 40000000) - priv->clk_csr = 0x01; - else - priv->clk_csr = 0; - } - - if (priv->plat->has_xgmac) { - if (clk_rate > 400000000) - priv->clk_csr = 0x5; - else if (clk_rate > 350000000) - priv->clk_csr = 0x4; - else if (clk_rate > 300000000) - priv->clk_csr = 0x3; - else if (clk_rate > 250000000) - priv->clk_csr = 0x2; - else if (clk_rate > 150000000) - priv->clk_csr = 0x1; - else - priv->clk_csr = 0x0; - } -} - -static void print_pkt(unsigned char *buf, int len) -{ - pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); - print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); -} - -static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - u32 avail; - - if (tx_q->dirty_tx > tx_q->cur_tx) - avail = tx_q->dirty_tx - tx_q->cur_tx - 1; - else - avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; - - return avail; -} - -/** - * stmmac_rx_dirty - Get RX queue dirty - * @priv: driver private structure - * @queue: RX queue index - */ -static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - u32 dirty; - - if (rx_q->dirty_rx <= rx_q->cur_rx) - dirty = rx_q->cur_rx - rx_q->dirty_rx; - else - dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; - - return dirty; -} - -static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) -{ - int tx_lpi_timer; - - /* Clear/set the SW EEE timer flag based on LPI ET enablement */ - priv->eee_sw_timer_en = en ? 0 : 1; - tx_lpi_timer = en ? priv->tx_lpi_timer : 0; - stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); -} - -/** - * stmmac_enable_eee_mode - check and enter in LPI mode - * @priv: driver private structure - * Description: this function is to verify and enter in LPI mode in case of - * EEE. - */ -static void stmmac_enable_eee_mode(struct stmmac_priv *priv) -{ - u32 tx_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - /* check if all TX queues have the work finished */ - for (queue = 0; queue < tx_cnt; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - if (tx_q->dirty_tx != tx_q->cur_tx) - return; /* still unfinished work */ - } - - /* Check and enter in LPI mode */ - if (!priv->tx_path_in_lpi_mode) - stmmac_set_eee_mode(priv, priv->hw, - priv->plat->en_tx_lpi_clockgating); -} - -/** - * stmmac_disable_eee_mode - disable and exit from LPI mode - * @priv: driver private structure - * Description: this function is to exit and disable EEE in case of - * LPI state is true. This is called by the xmit. - */ -void stmmac_disable_eee_mode(struct stmmac_priv *priv) -{ - if (!priv->eee_sw_timer_en) { - stmmac_lpi_entry_timer_config(priv, 0); - return; - } - - stmmac_reset_eee_mode(priv, priv->hw); - del_timer_sync(&priv->eee_ctrl_timer); - priv->tx_path_in_lpi_mode = false; -} - -/** - * stmmac_eee_ctrl_timer - EEE TX SW timer. - * @t: timer_list struct containing private info - * Description: - * if there is no data transfer and if we are not in LPI state, - * then MAC Transmitter can be moved to LPI state. - */ -static void stmmac_eee_ctrl_timer(struct timer_list *t) -{ - struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); - - stmmac_enable_eee_mode(priv); - mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); -} - -/** - * stmmac_eee_init - init EEE - * @priv: driver private structure - * Description: - * if the GMAC supports the EEE (from the HW cap reg) and the phy device - * can also manage EEE, this function enable the LPI state and start related - * timer. - */ -bool stmmac_eee_init(struct stmmac_priv *priv) -{ - int eee_tw_timer = priv->eee_tw_timer; - - /* Using PCS we cannot dial with the phy registers at this stage - * so we do not support extra feature like EEE. - */ - if (priv->hw->pcs == STMMAC_PCS_TBI || - priv->hw->pcs == STMMAC_PCS_RTBI) - return false; - - /* Check if MAC core supports the EEE feature. */ - if (!priv->dma_cap.eee) - return false; - - mutex_lock(&priv->lock); - - /* Check if it needs to be deactivated */ - if (!priv->eee_active) { - if (priv->eee_enabled) { - netdev_dbg(priv->dev, "disable EEE\n"); - stmmac_lpi_entry_timer_config(priv, 0); - del_timer_sync(&priv->eee_ctrl_timer); - stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); - if (priv->hw->xpcs) - xpcs_config_eee(priv->hw->xpcs, - priv->plat->mult_fact_100ns, - false); - } - mutex_unlock(&priv->lock); - return false; - } - - if (priv->eee_active && !priv->eee_enabled) { - timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); - stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, - eee_tw_timer); - if (priv->hw->xpcs) - xpcs_config_eee(priv->hw->xpcs, - priv->plat->mult_fact_100ns, - true); - } - - if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { - del_timer_sync(&priv->eee_ctrl_timer); - priv->tx_path_in_lpi_mode = false; - stmmac_lpi_entry_timer_config(priv, 1); - } else { - stmmac_lpi_entry_timer_config(priv, 0); - mod_timer(&priv->eee_ctrl_timer, - STMMAC_LPI_T(priv->tx_lpi_timer)); - } - - mutex_unlock(&priv->lock); - netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); - return true; -} - -/* stmmac_get_tx_hwtstamp - get HW TX timestamps - * @priv: driver private structure - * @p : descriptor pointer - * @skb : the socket buffer - * Description : - * This function will read timestamp from the descriptor & pass it to stack. - * and also perform some sanity checks. - */ -static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, - struct dma_desc *p, struct sk_buff *skb) -{ - struct skb_shared_hwtstamps shhwtstamp; - bool found = false; - u64 ns = 0; - - if (!priv->hwts_tx_en) - return; - - /* exit if skb doesn't support hw tstamp */ - if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) - return; - - /* check tx tstamp status */ - if (stmmac_get_tx_timestamp_status(priv, p)) { - stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); - found = true; - } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { - found = true; - } - - if (found) { - ns -= priv->plat->cdc_error_adj; - - memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); - shhwtstamp.hwtstamp = ns_to_ktime(ns); - - netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); - /* pass tstamp to stack */ - skb_tstamp_tx(skb, &shhwtstamp); - } -} - -/* stmmac_get_rx_hwtstamp - get HW RX timestamps - * @priv: driver private structure - * @p : descriptor pointer - * @np : next descriptor pointer - * @skb : the socket buffer - * Description : - * This function will read received packet's timestamp from the descriptor - * and pass it to stack. It also perform some sanity checks. - */ -static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, - struct dma_desc *np, struct sk_buff *skb) -{ - struct skb_shared_hwtstamps *shhwtstamp = NULL; - struct dma_desc *desc = p; - u64 ns = 0; - - if (!priv->hwts_rx_en) - return; - /* For GMAC4, the valid timestamp is from CTX next desc. */ - if (priv->plat->has_gmac4 || priv->plat->has_xgmac) - desc = np; - - /* Check if timestamp is available */ - if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { - stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); - - ns -= priv->plat->cdc_error_adj; - - netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); - shhwtstamp = skb_hwtstamps(skb); - memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); - shhwtstamp->hwtstamp = ns_to_ktime(ns); - } else { - netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); - } -} - -/** - * stmmac_hwtstamp_set - control hardware timestamping. - * @dev: device pointer. - * @ifr: An IOCTL specific structure, that can contain a pointer to - * a proprietary structure used to pass information to the driver. - * Description: - * This function configures the MAC to enable/disable both outgoing(TX) - * and incoming(RX) packets time stamping based on user input. - * Return Value: - * 0 on success and an appropriate -ve integer on failure. - */ -static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct hwtstamp_config config; - u32 ptp_v2 = 0; - u32 tstamp_all = 0; - u32 ptp_over_ipv4_udp = 0; - u32 ptp_over_ipv6_udp = 0; - u32 ptp_over_ethernet = 0; - u32 snap_type_sel = 0; - u32 ts_master_en = 0; - u32 ts_event_en = 0; - - if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { - netdev_alert(priv->dev, "No support for HW time stamping\n"); - priv->hwts_tx_en = 0; - priv->hwts_rx_en = 0; - - return -EOPNOTSUPP; - } - - if (copy_from_user(&config, ifr->ifr_data, - sizeof(config))) - return -EFAULT; - - netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", - __func__, config.flags, config.tx_type, config.rx_filter); - - if (config.tx_type != HWTSTAMP_TX_OFF && - config.tx_type != HWTSTAMP_TX_ON) - return -ERANGE; - - if (priv->adv_ts) { - switch (config.rx_filter) { - case HWTSTAMP_FILTER_NONE: - /* time stamp no incoming packet at all */ - config.rx_filter = HWTSTAMP_FILTER_NONE; - break; - - case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: - /* PTP v1, UDP, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; - /* 'xmac' hardware can support Sync, Pdelay_Req and - * Pdelay_resp by setting bit14 and bits17/16 to 01 - * This leaves Delay_Req timestamps out. - * Enable all events *and* general purpose message - * timestamping - */ - snap_type_sel = PTP_TCR_SNAPTYPSEL_1; - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: - /* PTP v1, UDP, Sync packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; - /* take time stamp for SYNC messages only */ - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: - /* PTP v1, UDP, Delay_req packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; - /* take time stamp for Delay_Req messages only */ - ts_master_en = PTP_TCR_TSMSTRENA; - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: - /* PTP v2, UDP, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for all event messages */ - snap_type_sel = PTP_TCR_SNAPTYPSEL_1; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: - /* PTP v2, UDP, Sync packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for SYNC messages only */ - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: - /* PTP v2, UDP, Delay_req packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for Delay_Req messages only */ - ts_master_en = PTP_TCR_TSMSTRENA; - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_EVENT: - /* PTP v2/802.AS1 any layer, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; - ptp_v2 = PTP_TCR_TSVER2ENA; - snap_type_sel = PTP_TCR_SNAPTYPSEL_1; - if (priv->synopsys_id < DWMAC_CORE_4_10) - ts_event_en = PTP_TCR_TSEVNTENA; - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - ptp_over_ethernet = PTP_TCR_TSIPENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_SYNC: - /* PTP v2/802.AS1, any layer, Sync packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for SYNC messages only */ - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - ptp_over_ethernet = PTP_TCR_TSIPENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: - /* PTP v2/802.AS1, any layer, Delay_req packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for Delay_Req messages only */ - ts_master_en = PTP_TCR_TSMSTRENA; - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - ptp_over_ethernet = PTP_TCR_TSIPENA; - break; - - case HWTSTAMP_FILTER_NTP_ALL: - case HWTSTAMP_FILTER_ALL: - /* time stamp any incoming packet */ - config.rx_filter = HWTSTAMP_FILTER_ALL; - tstamp_all = PTP_TCR_TSENALL; - break; - - default: - return -ERANGE; - } - } else { - switch (config.rx_filter) { - case HWTSTAMP_FILTER_NONE: - config.rx_filter = HWTSTAMP_FILTER_NONE; - break; - default: - /* PTP v1, UDP, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; - break; - } - } - priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); - priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; - - priv->systime_flags = STMMAC_HWTS_ACTIVE; - - if (priv->hwts_tx_en || priv->hwts_rx_en) { - priv->systime_flags |= tstamp_all | ptp_v2 | - ptp_over_ethernet | ptp_over_ipv6_udp | - ptp_over_ipv4_udp | ts_event_en | - ts_master_en | snap_type_sel; - } - - stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); - - memcpy(&priv->tstamp_config, &config, sizeof(config)); - - return copy_to_user(ifr->ifr_data, &config, - sizeof(config)) ? -EFAULT : 0; -} - -/** - * stmmac_hwtstamp_get - read hardware timestamping. - * @dev: device pointer. - * @ifr: An IOCTL specific structure, that can contain a pointer to - * a proprietary structure used to pass information to the driver. - * Description: - * This function obtain the current hardware timestamping settings - * as requested. - */ -static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct hwtstamp_config *config = &priv->tstamp_config; - - if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) - return -EOPNOTSUPP; - - return copy_to_user(ifr->ifr_data, config, - sizeof(*config)) ? -EFAULT : 0; -} - -/** - * stmmac_init_tstamp_counter - init hardware timestamping counter - * @priv: driver private structure - * @systime_flags: timestamping flags - * Description: - * Initialize hardware counter for packet timestamping. - * This is valid as long as the interface is open and not suspended. - * Will be rerun after resuming from suspend, case in which the timestamping - * flags updated by stmmac_hwtstamp_set() also need to be restored. - */ -int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) -{ - bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; - struct timespec64 now; - u32 sec_inc = 0; - u64 temp = 0; - int ret; - - if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) - return -EOPNOTSUPP; - - ret = clk_prepare_enable(priv->plat->clk_ptp_ref); - if (ret < 0) { - netdev_warn(priv->dev, - "failed to enable PTP reference clock: %pe\n", - ERR_PTR(ret)); - return ret; - } - - stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); - priv->systime_flags = systime_flags; - - /* program Sub Second Increment reg */ - stmmac_config_sub_second_increment(priv, priv->ptpaddr, - priv->plat->clk_ptp_rate, - xmac, &sec_inc); - temp = div_u64(1000000000ULL, sec_inc); - - /* Store sub second increment for later use */ - priv->sub_second_inc = sec_inc; - - /* calculate default added value: - * formula is : - * addend = (2^32)/freq_div_ratio; - * where, freq_div_ratio = 1e9ns/sec_inc - */ - temp = (u64)(temp << 32); - priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); - stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); - - /* initialize system time */ - ktime_get_real_ts64(&now); - - /* lower 32 bits of tv_sec are safe until y2106 */ - stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); - - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); - -/** - * stmmac_init_ptp - init PTP - * @priv: driver private structure - * Description: this is to verify if the HW supports the PTPv1 or PTPv2. - * This is done by looking at the HW cap. register. - * This function also registers the ptp driver. - */ -static int stmmac_init_ptp(struct stmmac_priv *priv) -{ - bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; - int ret; - - ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); - if (ret) - return ret; - - priv->adv_ts = 0; - /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ - if (xmac && priv->dma_cap.atime_stamp) - priv->adv_ts = 1; - /* Dwmac 3.x core with extend_desc can support adv_ts */ - else if (priv->extend_desc && priv->dma_cap.atime_stamp) - priv->adv_ts = 1; - - if (priv->dma_cap.time_stamp) - netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); - - if (priv->adv_ts) - netdev_info(priv->dev, - "IEEE 1588-2008 Advanced Timestamp supported\n"); - - priv->hwts_tx_en = 0; - priv->hwts_rx_en = 0; - - stmmac_ptp_register(priv); - - return 0; -} - -static void stmmac_release_ptp(struct stmmac_priv *priv) -{ - clk_disable_unprepare(priv->plat->clk_ptp_ref); - stmmac_ptp_unregister(priv); -} - -/** - * stmmac_mac_flow_ctrl - Configure flow control in all queues - * @priv: driver private structure - * @duplex: duplex passed to the next function - * Description: It is used for configuring the flow control in all queues - */ -static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) -{ - u32 tx_cnt = priv->plat->tx_queues_to_use; - - stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, - priv->pause, tx_cnt); -} - -static void stmmac_validate(struct phylink_config *config, - unsigned long *supported, - struct phylink_link_state *state) -{ - struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); - __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - int tx_cnt = priv->plat->tx_queues_to_use; - int max_speed = priv->plat->max_speed; - - phylink_set(mac_supported, 10baseT_Half); - phylink_set(mac_supported, 10baseT_Full); - phylink_set(mac_supported, 100baseT_Half); - phylink_set(mac_supported, 100baseT_Full); - phylink_set(mac_supported, 1000baseT_Half); - phylink_set(mac_supported, 1000baseT_Full); - phylink_set(mac_supported, 1000baseKX_Full); - - phylink_set(mac_supported, Autoneg); - phylink_set(mac_supported, Pause); - phylink_set(mac_supported, Asym_Pause); - phylink_set_port_modes(mac_supported); - - /* Cut down 1G if asked to */ - if ((max_speed > 0) && (max_speed < 1000)) { - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseX_Full); - } else if (priv->plat->has_gmac4) { - if (!max_speed || max_speed >= 2500) { - phylink_set(mac_supported, 2500baseT_Full); - phylink_set(mac_supported, 2500baseX_Full); - } - } else if (priv->plat->has_xgmac) { - if (!max_speed || (max_speed >= 2500)) { - phylink_set(mac_supported, 2500baseT_Full); - phylink_set(mac_supported, 2500baseX_Full); - } - if (!max_speed || (max_speed >= 5000)) { - phylink_set(mac_supported, 5000baseT_Full); - } - if (!max_speed || (max_speed >= 10000)) { - phylink_set(mac_supported, 10000baseSR_Full); - phylink_set(mac_supported, 10000baseLR_Full); - phylink_set(mac_supported, 10000baseER_Full); - phylink_set(mac_supported, 10000baseLRM_Full); - phylink_set(mac_supported, 10000baseT_Full); - phylink_set(mac_supported, 10000baseKX4_Full); - phylink_set(mac_supported, 10000baseKR_Full); - } - if (!max_speed || (max_speed >= 25000)) { - phylink_set(mac_supported, 25000baseCR_Full); - phylink_set(mac_supported, 25000baseKR_Full); - phylink_set(mac_supported, 25000baseSR_Full); - } - if (!max_speed || (max_speed >= 40000)) { - phylink_set(mac_supported, 40000baseKR4_Full); - phylink_set(mac_supported, 40000baseCR4_Full); - phylink_set(mac_supported, 40000baseSR4_Full); - phylink_set(mac_supported, 40000baseLR4_Full); - } - if (!max_speed || (max_speed >= 50000)) { - phylink_set(mac_supported, 50000baseCR2_Full); - phylink_set(mac_supported, 50000baseKR2_Full); - phylink_set(mac_supported, 50000baseSR2_Full); - phylink_set(mac_supported, 50000baseKR_Full); - phylink_set(mac_supported, 50000baseSR_Full); - phylink_set(mac_supported, 50000baseCR_Full); - phylink_set(mac_supported, 50000baseLR_ER_FR_Full); - phylink_set(mac_supported, 50000baseDR_Full); - } - if (!max_speed || (max_speed >= 100000)) { - phylink_set(mac_supported, 100000baseKR4_Full); - phylink_set(mac_supported, 100000baseSR4_Full); - phylink_set(mac_supported, 100000baseCR4_Full); - phylink_set(mac_supported, 100000baseLR4_ER4_Full); - phylink_set(mac_supported, 100000baseKR2_Full); - phylink_set(mac_supported, 100000baseSR2_Full); - phylink_set(mac_supported, 100000baseCR2_Full); - phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); - phylink_set(mac_supported, 100000baseDR2_Full); - } - } - - /* Half-Duplex can only work with single queue */ - if (tx_cnt > 1) { - phylink_set(mask, 10baseT_Half); - phylink_set(mask, 100baseT_Half); - phylink_set(mask, 1000baseT_Half); - } - - linkmode_and(supported, supported, mac_supported); - linkmode_andnot(supported, supported, mask); - - linkmode_and(state->advertising, state->advertising, mac_supported); - linkmode_andnot(state->advertising, state->advertising, mask); - - /* If PCS is supported, check which modes it supports. */ - if (priv->hw->xpcs) - xpcs_validate(priv->hw->xpcs, supported, state); -} - -static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, - const struct phylink_link_state *state) -{ - /* Nothing to do, xpcs_config() handles everything */ -} - -static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) -{ - struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; - enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; - enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; - bool *hs_enable = &fpe_cfg->hs_enable; - - if (is_up && *hs_enable) { - stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); - } else { - *lo_state = FPE_STATE_OFF; - *lp_state = FPE_STATE_OFF; - } -} - -static void stmmac_mac_link_down(struct phylink_config *config, - unsigned int mode, phy_interface_t interface) -{ - struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); - - stmmac_mac_set(priv, priv->ioaddr, false); - priv->eee_active = false; - priv->tx_lpi_enabled = false; - priv->eee_enabled = stmmac_eee_init(priv); - stmmac_set_eee_pls(priv, priv->hw, false); - - if (priv->dma_cap.fpesel) - stmmac_fpe_link_state_handle(priv, false); -} - -static void stmmac_mac_link_up(struct phylink_config *config, - struct phy_device *phy, - unsigned int mode, phy_interface_t interface, - int speed, int duplex, - bool tx_pause, bool rx_pause) -{ - struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); - u32 ctrl; - - ctrl = readl(priv->ioaddr + MAC_CTRL_REG); - ctrl &= ~priv->hw->link.speed_mask; - - if (interface == PHY_INTERFACE_MODE_USXGMII) { - switch (speed) { - case SPEED_10000: - ctrl |= priv->hw->link.xgmii.speed10000; - break; - case SPEED_5000: - ctrl |= priv->hw->link.xgmii.speed5000; - break; - case SPEED_2500: - ctrl |= priv->hw->link.xgmii.speed2500; - break; - default: - return; - } - } else if (interface == PHY_INTERFACE_MODE_XLGMII) { - switch (speed) { - case SPEED_100000: - ctrl |= priv->hw->link.xlgmii.speed100000; - break; - case SPEED_50000: - ctrl |= priv->hw->link.xlgmii.speed50000; - break; - case SPEED_40000: - ctrl |= priv->hw->link.xlgmii.speed40000; - break; - case SPEED_25000: - ctrl |= priv->hw->link.xlgmii.speed25000; - break; - case SPEED_10000: - ctrl |= priv->hw->link.xgmii.speed10000; - break; - case SPEED_2500: - ctrl |= priv->hw->link.speed2500; - break; - case SPEED_1000: - ctrl |= priv->hw->link.speed1000; - break; - default: - return; - } - } else { - switch (speed) { - case SPEED_2500: - ctrl |= priv->hw->link.speed2500; - break; - case SPEED_1000: - ctrl |= priv->hw->link.speed1000; - break; - case SPEED_100: - ctrl |= priv->hw->link.speed100; - break; - case SPEED_10: - ctrl |= priv->hw->link.speed10; - break; - default: - return; - } - } - - priv->speed = speed; - - if (priv->plat->fix_mac_speed) - priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); - - if (!duplex) - ctrl &= ~priv->hw->link.duplex; - else - ctrl |= priv->hw->link.duplex; - - /* Flow Control operation */ - if (tx_pause && rx_pause) - stmmac_mac_flow_ctrl(priv, duplex); - - writel(ctrl, priv->ioaddr + MAC_CTRL_REG); - - stmmac_mac_set(priv, priv->ioaddr, true); - if (phy && priv->dma_cap.eee) { - priv->eee_active = phy_init_eee(phy, 1) >= 0; - priv->eee_enabled = stmmac_eee_init(priv); - priv->tx_lpi_enabled = priv->eee_enabled; - stmmac_set_eee_pls(priv, priv->hw, true); - } - - if (priv->dma_cap.fpesel) - stmmac_fpe_link_state_handle(priv, true); -} - -static const struct phylink_mac_ops stmmac_phylink_mac_ops = { - .validate = stmmac_validate, - .mac_config = stmmac_mac_config, - .mac_link_down = stmmac_mac_link_down, - .mac_link_up = stmmac_mac_link_up, -}; - -/** - * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported - * @priv: driver private structure - * Description: this is to verify if the HW supports the PCS. - * Physical Coding Sublayer (PCS) interface that can be used when the MAC is - * configured for the TBI, RTBI, or SGMII PHY interface. - */ -static void stmmac_check_pcs_mode(struct stmmac_priv *priv) -{ - int interface = priv->plat->interface; - - if (priv->dma_cap.pcs) { - if ((interface == PHY_INTERFACE_MODE_RGMII) || - (interface == PHY_INTERFACE_MODE_RGMII_ID) || - (interface == PHY_INTERFACE_MODE_RGMII_RXID) || - (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { - netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); - priv->hw->pcs = STMMAC_PCS_RGMII; - } else if (interface == PHY_INTERFACE_MODE_SGMII) { - netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); - priv->hw->pcs = STMMAC_PCS_SGMII; - } - } -} - -/** - * stmmac_init_phy - PHY initialization - * @dev: net device structure - * Description: it initializes the driver's PHY state, and attaches the PHY - * to the mac driver. - * Return value: - * 0 on success - */ -static int stmmac_init_phy(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct device_node *node; - int ret; - - node = priv->plat->phylink_node; - - if (node) - ret = phylink_of_phy_connect(priv->phylink, node, 0); - - /* Some DT bindings do not set-up the PHY handle. Let's try to - * manually parse it - */ - if (!node || ret) { - int addr = priv->plat->phy_addr; - struct phy_device *phydev; - - phydev = mdiobus_get_phy(priv->mii, addr); - if (!phydev) { - netdev_err(priv->dev, "no phy at addr %d\n", addr); - return -ENODEV; - } - - ret = phylink_connect_phy(priv->phylink, phydev); - } - - if (!priv->plat->pmt) { - struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; - - phylink_ethtool_get_wol(priv->phylink, &wol); - device_set_wakeup_capable(priv->device, !!wol.supported); - } - - return ret; -} - -static int stmmac_phy_setup(struct stmmac_priv *priv) -{ - struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; - struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); - int mode = priv->plat->phy_interface; - struct phylink *phylink; - - priv->phylink_config.dev = &priv->dev->dev; - priv->phylink_config.type = PHYLINK_NETDEV; - priv->phylink_config.pcs_poll = true; - if (priv->plat->mdio_bus_data) - priv->phylink_config.ovr_an_inband = - mdio_bus_data->xpcs_an_inband; - - if (!fwnode) - fwnode = dev_fwnode(priv->device); - - phylink = phylink_create(&priv->phylink_config, fwnode, - mode, &stmmac_phylink_mac_ops); - if (IS_ERR(phylink)) - return PTR_ERR(phylink); - - if (priv->hw->xpcs) - phylink_set_pcs(phylink, &priv->hw->xpcs->pcs); - - priv->phylink = phylink; - return 0; -} - -static void stmmac_display_rx_rings(struct stmmac_priv *priv) -{ - u32 rx_cnt = priv->plat->rx_queues_to_use; - unsigned int desc_size; - void *head_rx; - u32 queue; - - /* Display RX rings */ - for (queue = 0; queue < rx_cnt; queue++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - pr_info("\tRX Queue %u rings\n", queue); - - if (priv->extend_desc) { - head_rx = (void *)rx_q->dma_erx; - desc_size = sizeof(struct dma_extended_desc); - } else { - head_rx = (void *)rx_q->dma_rx; - desc_size = sizeof(struct dma_desc); - } - - /* Display RX ring */ - stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true, - rx_q->dma_rx_phy, desc_size); - } -} - -static void stmmac_display_tx_rings(struct stmmac_priv *priv) -{ - u32 tx_cnt = priv->plat->tx_queues_to_use; - unsigned int desc_size; - void *head_tx; - u32 queue; - - /* Display TX rings */ - for (queue = 0; queue < tx_cnt; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - pr_info("\tTX Queue %d rings\n", queue); - - if (priv->extend_desc) { - head_tx = (void *)tx_q->dma_etx; - desc_size = sizeof(struct dma_extended_desc); - } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { - head_tx = (void *)tx_q->dma_entx; - desc_size = sizeof(struct dma_edesc); - } else { - head_tx = (void *)tx_q->dma_tx; - desc_size = sizeof(struct dma_desc); - } - - stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false, - tx_q->dma_tx_phy, desc_size); - } -} - -static void stmmac_display_rings(struct stmmac_priv *priv) -{ - /* Display RX ring */ - stmmac_display_rx_rings(priv); - - /* Display TX ring */ - stmmac_display_tx_rings(priv); -} - -static int stmmac_set_bfsize(int mtu, int bufsize) -{ - int ret = bufsize; - - if (mtu >= BUF_SIZE_8KiB) - ret = BUF_SIZE_16KiB; - else if (mtu >= BUF_SIZE_4KiB) - ret = BUF_SIZE_8KiB; - else if (mtu >= BUF_SIZE_2KiB) - ret = BUF_SIZE_4KiB; - else if (mtu > DEFAULT_BUFSIZE) - ret = BUF_SIZE_2KiB; - else - ret = DEFAULT_BUFSIZE; - - return ret; -} - -/** - * stmmac_clear_rx_descriptors - clear RX descriptors - * @priv: driver private structure - * @queue: RX queue index - * Description: this function is called to clear the RX descriptors - * in case of both basic and extended descriptors are used. - */ -static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - /* Clear the RX descriptors */ - for (i = 0; i < priv->dma_rx_size; i++) - if (priv->extend_desc) - stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, - priv->use_riwt, priv->mode, - (i == priv->dma_rx_size - 1), - priv->dma_buf_sz); - else - stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], - priv->use_riwt, priv->mode, - (i == priv->dma_rx_size - 1), - priv->dma_buf_sz); -} - -/** - * stmmac_clear_tx_descriptors - clear tx descriptors - * @priv: driver private structure - * @queue: TX queue index. - * Description: this function is called to clear the TX descriptors - * in case of both basic and extended descriptors are used. - */ -static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int i; - - /* Clear the TX descriptors */ - for (i = 0; i < priv->dma_tx_size; i++) { - int last = (i == (priv->dma_tx_size - 1)); - struct dma_desc *p; - - if (priv->extend_desc) - p = &tx_q->dma_etx[i].basic; - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &tx_q->dma_entx[i].basic; - else - p = &tx_q->dma_tx[i]; - - stmmac_init_tx_desc(priv, p, priv->mode, last); - } -} - -/** - * stmmac_clear_descriptors - clear descriptors - * @priv: driver private structure - * Description: this function is called to clear the TX and RX descriptors - * in case of both basic and extended descriptors are used. - */ -static void stmmac_clear_descriptors(struct stmmac_priv *priv) -{ - u32 rx_queue_cnt = priv->plat->rx_queues_to_use; - u32 tx_queue_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - /* Clear the RX descriptors */ - for (queue = 0; queue < rx_queue_cnt; queue++) - stmmac_clear_rx_descriptors(priv, queue); - - /* Clear the TX descriptors */ - for (queue = 0; queue < tx_queue_cnt; queue++) - stmmac_clear_tx_descriptors(priv, queue); -} - -/** - * stmmac_init_rx_buffers - init the RX descriptor buffer. - * @priv: driver private structure - * @p: descriptor pointer - * @i: descriptor index - * @flags: gfp flag - * @queue: RX queue index - * Description: this function is called to allocate a receive buffer, perform - * the DMA mapping and init the descriptor. - */ -static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, - int i, gfp_t flags, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; - gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); - - if (priv->dma_cap.addr64 <= 32) - gfp |= GFP_DMA32; - - if (!buf->page) { - buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); - if (!buf->page) - return -ENOMEM; - buf->page_offset = stmmac_rx_offset(priv); - } - - if (priv->sph && !buf->sec_page) { - buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); - if (!buf->sec_page) - return -ENOMEM; - - buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); - } else { - buf->sec_page = NULL; - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); - } - - buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; - - stmmac_set_desc_addr(priv, p, buf->addr); - if (priv->dma_buf_sz == BUF_SIZE_16KiB) - stmmac_init_desc3(priv, p); - - return 0; -} - -/** - * stmmac_free_rx_buffer - free RX dma buffers - * @priv: private structure - * @queue: RX queue index - * @i: buffer index. - */ -static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; - - if (buf->page) - page_pool_put_full_page(rx_q->page_pool, buf->page, false); - buf->page = NULL; - - if (buf->sec_page) - page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); - buf->sec_page = NULL; -} - -/** - * stmmac_free_tx_buffer - free RX dma buffers - * @priv: private structure - * @queue: RX queue index - * @i: buffer index. - */ -static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - if (tx_q->tx_skbuff_dma[i].buf && - tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { - if (tx_q->tx_skbuff_dma[i].map_as_page) - dma_unmap_page(priv->device, - tx_q->tx_skbuff_dma[i].buf, - tx_q->tx_skbuff_dma[i].len, - DMA_TO_DEVICE); - else - dma_unmap_single(priv->device, - tx_q->tx_skbuff_dma[i].buf, - tx_q->tx_skbuff_dma[i].len, - DMA_TO_DEVICE); - } - - if (tx_q->xdpf[i] && - (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || - tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { - xdp_return_frame(tx_q->xdpf[i]); - tx_q->xdpf[i] = NULL; - } - - if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) - tx_q->xsk_frames_done++; - - if (tx_q->tx_skbuff[i] && - tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { - dev_kfree_skb_any(tx_q->tx_skbuff[i]); - tx_q->tx_skbuff[i] = NULL; - } - - tx_q->tx_skbuff_dma[i].buf = 0; - tx_q->tx_skbuff_dma[i].map_as_page = false; -} - -/** - * dma_free_rx_skbufs - free RX dma buffers - * @priv: private structure - * @queue: RX queue index - */ -static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) -{ - int i; - - for (i = 0; i < priv->dma_rx_size; i++) - stmmac_free_rx_buffer(priv, queue, i); -} - -static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue, - gfp_t flags) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - for (i = 0; i < priv->dma_rx_size; i++) { - struct dma_desc *p; - int ret; - - if (priv->extend_desc) - p = &((rx_q->dma_erx + i)->basic); - else - p = rx_q->dma_rx + i; - - ret = stmmac_init_rx_buffers(priv, p, i, flags, - queue); - if (ret) - return ret; - - rx_q->buf_alloc_num++; - } - - return 0; -} - -/** - * dma_free_rx_xskbufs - free RX dma buffers from XSK pool - * @priv: private structure - * @queue: RX queue index - */ -static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - for (i = 0; i < priv->dma_rx_size; i++) { - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; - - if (!buf->xdp) - continue; - - xsk_buff_free(buf->xdp); - buf->xdp = NULL; - } -} - -static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - for (i = 0; i < priv->dma_rx_size; i++) { - struct stmmac_rx_buffer *buf; - dma_addr_t dma_addr; - struct dma_desc *p; - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + i); - else - p = rx_q->dma_rx + i; - - buf = &rx_q->buf_pool[i]; - - buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); - if (!buf->xdp) - return -ENOMEM; - - dma_addr = xsk_buff_xdp_get_dma(buf->xdp); - stmmac_set_desc_addr(priv, p, dma_addr); - rx_q->buf_alloc_num++; - } - - return 0; -} - -static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) -{ - if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) - return NULL; - - return xsk_get_pool_from_qid(priv->dev, queue); -} - -/** - * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) - * @priv: driver private structure - * @queue: RX queue index - * @flags: gfp flag. - * Description: this function initializes the DMA RX descriptors - * and allocates the socket buffers. It supports the chained and ring - * modes. - */ -static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int ret; - - netif_dbg(priv, probe, priv->dev, - "(%s) dma_rx_phy=0x%08x\n", __func__, - (u32)rx_q->dma_rx_phy); - - stmmac_clear_rx_descriptors(priv, queue); - - xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); - - rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); - - if (rx_q->xsk_pool) { - WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, - MEM_TYPE_XSK_BUFF_POOL, - NULL)); - netdev_info(priv->dev, - "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", - rx_q->queue_index); - xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); - } else { - WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, - MEM_TYPE_PAGE_POOL, - rx_q->page_pool)); - netdev_info(priv->dev, - "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", - rx_q->queue_index); - } - - if (rx_q->xsk_pool) { - /* RX XDP ZC buffer pool may not be populated, e.g. - * xdpsock TX-only. - */ - stmmac_alloc_rx_buffers_zc(priv, queue); - } else { - ret = stmmac_alloc_rx_buffers(priv, queue, flags); - if (ret < 0) - return -ENOMEM; - } - - rx_q->cur_rx = 0; - rx_q->dirty_rx = 0; - - /* Setup the chained descriptor addresses */ - if (priv->mode == STMMAC_CHAIN_MODE) { - if (priv->extend_desc) - stmmac_mode_init(priv, rx_q->dma_erx, - rx_q->dma_rx_phy, - priv->dma_rx_size, 1); - else - stmmac_mode_init(priv, rx_q->dma_rx, - rx_q->dma_rx_phy, - priv->dma_rx_size, 0); - } - - return 0; -} - -static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 rx_count = priv->plat->rx_queues_to_use; - u32 queue; - int ret; - - /* RX INITIALIZATION */ - netif_dbg(priv, probe, priv->dev, - "SKB addresses:\nskb\t\tskb data\tdma data\n"); - - for (queue = 0; queue < rx_count; queue++) { - ret = __init_dma_rx_desc_rings(priv, queue, flags); - if (ret) - goto err_init_rx_buffers; - } - - return 0; - -err_init_rx_buffers: - while (queue >= 0) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - if (rx_q->xsk_pool) - dma_free_rx_xskbufs(priv, queue); - else - dma_free_rx_skbufs(priv, queue); - - rx_q->buf_alloc_num = 0; - rx_q->xsk_pool = NULL; - - if (queue == 0) - break; - - queue--; - } - - return ret; -} - -/** - * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) - * @priv: driver private structure - * @queue : TX queue index - * Description: this function initializes the DMA TX descriptors - * and allocates the socket buffers. It supports the chained and ring - * modes. - */ -static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int i; - - netif_dbg(priv, probe, priv->dev, - "(%s) dma_tx_phy=0x%08x\n", __func__, - (u32)tx_q->dma_tx_phy); - - /* Setup the chained descriptor addresses */ - if (priv->mode == STMMAC_CHAIN_MODE) { - if (priv->extend_desc) - stmmac_mode_init(priv, tx_q->dma_etx, - tx_q->dma_tx_phy, - priv->dma_tx_size, 1); - else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) - stmmac_mode_init(priv, tx_q->dma_tx, - tx_q->dma_tx_phy, - priv->dma_tx_size, 0); - } - - tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); - - for (i = 0; i < priv->dma_tx_size; i++) { - struct dma_desc *p; - - if (priv->extend_desc) - p = &((tx_q->dma_etx + i)->basic); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &((tx_q->dma_entx + i)->basic); - else - p = tx_q->dma_tx + i; - - stmmac_clear_desc(priv, p); - - tx_q->tx_skbuff_dma[i].buf = 0; - tx_q->tx_skbuff_dma[i].map_as_page = false; - tx_q->tx_skbuff_dma[i].len = 0; - tx_q->tx_skbuff_dma[i].last_segment = false; - tx_q->tx_skbuff[i] = NULL; - } - - tx_q->dirty_tx = 0; - tx_q->cur_tx = 0; - tx_q->mss = 0; - - netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); - - return 0; -} - -static int init_dma_tx_desc_rings(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 tx_queue_cnt; - u32 queue; - - tx_queue_cnt = priv->plat->tx_queues_to_use; - - for (queue = 0; queue < tx_queue_cnt; queue++) - __init_dma_tx_desc_rings(priv, queue); - - return 0; -} - -/** - * init_dma_desc_rings - init the RX/TX descriptor rings - * @dev: net device structure - * @flags: gfp flag. - * Description: this function initializes the DMA RX/TX descriptors - * and allocates the socket buffers. It supports the chained and ring - * modes. - */ -static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret; - - ret = init_dma_rx_desc_rings(dev, flags); - if (ret) - return ret; - - ret = init_dma_tx_desc_rings(dev); - - stmmac_clear_descriptors(priv); - - if (netif_msg_hw(priv)) - stmmac_display_rings(priv); - - return ret; -} - -/** - * dma_free_tx_skbufs - free TX dma buffers - * @priv: private structure - * @queue: TX queue index - */ -static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int i; - - tx_q->xsk_frames_done = 0; - - for (i = 0; i < priv->dma_tx_size; i++) - stmmac_free_tx_buffer(priv, queue, i); - - if (tx_q->xsk_pool && tx_q->xsk_frames_done) { - xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); - tx_q->xsk_frames_done = 0; - tx_q->xsk_pool = NULL; - } -} - -/** - * stmmac_free_tx_skbufs - free TX skb buffers - * @priv: private structure - */ -static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) -{ - u32 tx_queue_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - for (queue = 0; queue < tx_queue_cnt; queue++) - dma_free_tx_skbufs(priv, queue); -} - -/** - * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) - * @priv: private structure - * @queue: RX queue index - */ -static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - /* Release the DMA RX socket buffers */ - if (rx_q->xsk_pool) - dma_free_rx_xskbufs(priv, queue); - else - dma_free_rx_skbufs(priv, queue); - - rx_q->buf_alloc_num = 0; - rx_q->xsk_pool = NULL; - - /* Free DMA regions of consistent memory previously allocated */ - if (!priv->extend_desc) - dma_free_coherent(priv->device, priv->dma_rx_size * - sizeof(struct dma_desc), - rx_q->dma_rx, rx_q->dma_rx_phy); - else - dma_free_coherent(priv->device, priv->dma_rx_size * - sizeof(struct dma_extended_desc), - rx_q->dma_erx, rx_q->dma_rx_phy); - - if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) - xdp_rxq_info_unreg(&rx_q->xdp_rxq); - - kfree(rx_q->buf_pool); - if (rx_q->page_pool) - page_pool_destroy(rx_q->page_pool); -} - -static void free_dma_rx_desc_resources(struct stmmac_priv *priv) -{ - u32 rx_count = priv->plat->rx_queues_to_use; - u32 queue; - - /* Free RX queue resources */ - for (queue = 0; queue < rx_count; queue++) - __free_dma_rx_desc_resources(priv, queue); -} - -/** - * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) - * @priv: private structure - * @queue: TX queue index - */ -static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - size_t size; - void *addr; - - /* Release the DMA TX socket buffers */ - dma_free_tx_skbufs(priv, queue); - - if (priv->extend_desc) { - size = sizeof(struct dma_extended_desc); - addr = tx_q->dma_etx; - } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { - size = sizeof(struct dma_edesc); - addr = tx_q->dma_entx; - } else { - size = sizeof(struct dma_desc); - addr = tx_q->dma_tx; - } - - size *= priv->dma_tx_size; - - dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); - - kfree(tx_q->tx_skbuff_dma); - kfree(tx_q->tx_skbuff); -} - -static void free_dma_tx_desc_resources(struct stmmac_priv *priv) -{ - u32 tx_count = priv->plat->tx_queues_to_use; - u32 queue; - - /* Free TX queue resources */ - for (queue = 0; queue < tx_count; queue++) - __free_dma_tx_desc_resources(priv, queue); -} - -/** - * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). - * @priv: private structure - * @queue: RX queue index - * Description: according to which descriptor can be used (extend or basic) - * this function allocates the resources for TX and RX paths. In case of - * reception, for example, it pre-allocated the RX socket buffer in order to - * allow zero-copy mechanism. - */ -static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - bool xdp_prog = stmmac_xdp_is_enabled(priv); - struct page_pool_params pp_params = { 0 }; - unsigned int num_pages; - unsigned int napi_id; - int ret; - - rx_q->queue_index = queue; - rx_q->priv_data = priv; - - pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; - pp_params.pool_size = priv->dma_rx_size; - num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); - pp_params.order = ilog2(num_pages); - pp_params.nid = dev_to_node(priv->device); - pp_params.dev = priv->device; - pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; - pp_params.offset = stmmac_rx_offset(priv); - pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); - - rx_q->page_pool = page_pool_create(&pp_params); - if (IS_ERR(rx_q->page_pool)) { - ret = PTR_ERR(rx_q->page_pool); - rx_q->page_pool = NULL; - return ret; - } - - rx_q->buf_pool = kcalloc(priv->dma_rx_size, - sizeof(*rx_q->buf_pool), - GFP_KERNEL); - if (!rx_q->buf_pool) - return -ENOMEM; - - if (priv->extend_desc) { - rx_q->dma_erx = dma_alloc_coherent(priv->device, - priv->dma_rx_size * - sizeof(struct dma_extended_desc), - &rx_q->dma_rx_phy, - GFP_KERNEL); - if (!rx_q->dma_erx) - return -ENOMEM; - - } else { - rx_q->dma_rx = dma_alloc_coherent(priv->device, - priv->dma_rx_size * - sizeof(struct dma_desc), - &rx_q->dma_rx_phy, - GFP_KERNEL); - if (!rx_q->dma_rx) - return -ENOMEM; - } - - if (stmmac_xdp_is_enabled(priv) && - test_bit(queue, priv->af_xdp_zc_qps)) - napi_id = ch->rxtx_napi.napi_id; - else - napi_id = ch->rx_napi.napi_id; - - ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, - rx_q->queue_index, - napi_id); - if (ret) { - netdev_err(priv->dev, "Failed to register xdp rxq info\n"); - return -EINVAL; - } - - return 0; -} - -static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) -{ - u32 rx_count = priv->plat->rx_queues_to_use; - u32 queue; - int ret; - - /* RX queues buffers and DMA */ - for (queue = 0; queue < rx_count; queue++) { - ret = __alloc_dma_rx_desc_resources(priv, queue); - if (ret) - goto err_dma; - } - - return 0; - -err_dma: - free_dma_rx_desc_resources(priv); - - return ret; -} - -/** - * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). - * @priv: private structure - * @queue: TX queue index - * Description: according to which descriptor can be used (extend or basic) - * this function allocates the resources for TX and RX paths. In case of - * reception, for example, it pre-allocated the RX socket buffer in order to - * allow zero-copy mechanism. - */ -static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - size_t size; - void *addr; - - tx_q->queue_index = queue; - tx_q->priv_data = priv; - - tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size, - sizeof(*tx_q->tx_skbuff_dma), - GFP_KERNEL); - if (!tx_q->tx_skbuff_dma) - return -ENOMEM; - - tx_q->tx_skbuff = kcalloc(priv->dma_tx_size, - sizeof(struct sk_buff *), - GFP_KERNEL); - if (!tx_q->tx_skbuff) - return -ENOMEM; - - if (priv->extend_desc) - size = sizeof(struct dma_extended_desc); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - size = sizeof(struct dma_edesc); - else - size = sizeof(struct dma_desc); - - size *= priv->dma_tx_size; - - addr = dma_alloc_coherent(priv->device, size, - &tx_q->dma_tx_phy, GFP_KERNEL); - if (!addr) - return -ENOMEM; - - if (priv->extend_desc) - tx_q->dma_etx = addr; - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - tx_q->dma_entx = addr; - else - tx_q->dma_tx = addr; - - return 0; -} - -static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) -{ - u32 tx_count = priv->plat->tx_queues_to_use; - u32 queue; - int ret; - - /* TX queues buffers and DMA */ - for (queue = 0; queue < tx_count; queue++) { - ret = __alloc_dma_tx_desc_resources(priv, queue); - if (ret) - goto err_dma; - } - - return 0; - -err_dma: - free_dma_tx_desc_resources(priv); - return ret; -} - -/** - * alloc_dma_desc_resources - alloc TX/RX resources. - * @priv: private structure - * Description: according to which descriptor can be used (extend or basic) - * this function allocates the resources for TX and RX paths. In case of - * reception, for example, it pre-allocated the RX socket buffer in order to - * allow zero-copy mechanism. - */ -static int alloc_dma_desc_resources(struct stmmac_priv *priv) -{ - /* RX Allocation */ - int ret = alloc_dma_rx_desc_resources(priv); - - if (ret) - return ret; - - ret = alloc_dma_tx_desc_resources(priv); - - return ret; -} - -/** - * free_dma_desc_resources - free dma desc resources - * @priv: private structure - */ -static void free_dma_desc_resources(struct stmmac_priv *priv) -{ - /* Release the DMA TX socket buffers */ - free_dma_tx_desc_resources(priv); - - /* Release the DMA RX socket buffers later - * to ensure all pending XDP_TX buffers are returned. - */ - free_dma_rx_desc_resources(priv); -} - -/** - * stmmac_mac_enable_rx_queues - Enable MAC rx queues - * @priv: driver private structure - * Description: It is used for enabling the rx queues in the MAC - */ -static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - int queue; - u8 mode; - - for (queue = 0; queue < rx_queues_count; queue++) { - mode = priv->plat->rx_queues_cfg[queue].mode_to_use; - stmmac_rx_queue_enable(priv, priv->hw, mode, queue); - } -} - -/** - * stmmac_start_rx_dma - start RX DMA channel - * @priv: driver private structure - * @chan: RX channel index - * Description: - * This starts a RX DMA channel - */ -static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); - stmmac_start_rx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_start_tx_dma - start TX DMA channel - * @priv: driver private structure - * @chan: TX channel index - * Description: - * This starts a TX DMA channel - */ -static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); - stmmac_start_tx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_stop_rx_dma - stop RX DMA channel - * @priv: driver private structure - * @chan: RX channel index - * Description: - * This stops a RX DMA channel - */ -static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); - stmmac_stop_rx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_stop_tx_dma - stop TX DMA channel - * @priv: driver private structure - * @chan: TX channel index - * Description: - * This stops a TX DMA channel - */ -static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); - stmmac_stop_tx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_start_all_dma - start all RX and TX DMA channels - * @priv: driver private structure - * Description: - * This starts all the RX and TX DMA channels - */ -static void stmmac_start_all_dma(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 chan = 0; - - for (chan = 0; chan < rx_channels_count; chan++) - stmmac_start_rx_dma(priv, chan); - - for (chan = 0; chan < tx_channels_count; chan++) - stmmac_start_tx_dma(priv, chan); -} - -/** - * stmmac_stop_all_dma - stop all RX and TX DMA channels - * @priv: driver private structure - * Description: - * This stops the RX and TX DMA channels - */ -static void stmmac_stop_all_dma(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 chan = 0; - - for (chan = 0; chan < rx_channels_count; chan++) - stmmac_stop_rx_dma(priv, chan); - - for (chan = 0; chan < tx_channels_count; chan++) - stmmac_stop_tx_dma(priv, chan); -} - -/** - * stmmac_dma_operation_mode - HW DMA operation mode - * @priv: driver private structure - * Description: it is used for configuring the DMA operation mode register in - * order to program the tx/rx DMA thresholds or Store-And-Forward mode. - */ -static void stmmac_dma_operation_mode(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - int rxfifosz = priv->plat->rx_fifo_size; - int txfifosz = priv->plat->tx_fifo_size; - u32 txmode = 0; - u32 rxmode = 0; - u32 chan = 0; - u8 qmode = 0; - - if (rxfifosz == 0) - rxfifosz = priv->dma_cap.rx_fifo_size; - if (txfifosz == 0) - txfifosz = priv->dma_cap.tx_fifo_size; - - /* Adjust for real per queue fifo size */ - rxfifosz /= rx_channels_count; - txfifosz /= tx_channels_count; - - if (priv->plat->force_thresh_dma_mode) { - txmode = tc; - rxmode = tc; - } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { - /* - * In case of GMAC, SF mode can be enabled - * to perform the TX COE in HW. This depends on: - * 1) TX COE if actually supported - * 2) There is no bugged Jumbo frame support - * that needs to not insert csum in the TDES. - */ - txmode = SF_DMA_MODE; - rxmode = SF_DMA_MODE; - priv->xstats.threshold = SF_DMA_MODE; - } else { - txmode = tc; - rxmode = SF_DMA_MODE; - } - - /* configure all channels */ - for (chan = 0; chan < rx_channels_count; chan++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; - u32 buf_size; - - qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; - - stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, - rxfifosz, qmode); - - if (rx_q->xsk_pool) { - buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); - stmmac_set_dma_bfsize(priv, priv->ioaddr, - buf_size, - chan); - } else { - stmmac_set_dma_bfsize(priv, priv->ioaddr, - priv->dma_buf_sz, - chan); - } - } - - for (chan = 0; chan < tx_channels_count; chan++) { - qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; - - stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, - txfifosz, qmode); - } -} - -static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) -{ - struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - struct xsk_buff_pool *pool = tx_q->xsk_pool; - unsigned int entry = tx_q->cur_tx; - struct dma_desc *tx_desc = NULL; - struct xdp_desc xdp_desc; - bool work_done = true; - - /* Avoids TX time-out as we are sharing with slow path */ - txq_trans_cond_update(nq); - - budget = min(budget, stmmac_tx_avail(priv, queue)); - - while (budget-- > 0) { - dma_addr_t dma_addr; - bool set_ic; - - /* We are sharing with slow path and stop XSK TX desc submission when - * available TX ring is less than threshold. - */ - if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || - !netif_carrier_ok(priv->dev)) { - work_done = false; - break; - } - - if (!xsk_tx_peek_desc(pool, &xdp_desc)) - break; - - if (likely(priv->extend_desc)) - tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - tx_desc = &tx_q->dma_entx[entry].basic; - else - tx_desc = tx_q->dma_tx + entry; - - dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); - xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); - - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; - - /* To return XDP buffer to XSK pool, we simple call - * xsk_tx_completed(), so we don't need to fill up - * 'buf' and 'xdpf'. - */ - tx_q->tx_skbuff_dma[entry].buf = 0; - tx_q->xdpf[entry] = NULL; - - tx_q->tx_skbuff_dma[entry].map_as_page = false; - tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; - tx_q->tx_skbuff_dma[entry].last_segment = true; - tx_q->tx_skbuff_dma[entry].is_jumbo = false; - - stmmac_set_desc_addr(priv, tx_desc, dma_addr); - - tx_q->tx_count_frames++; - - if (!priv->tx_coal_frames[queue]) - set_ic = false; - else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, tx_desc); - priv->xstats.tx_set_ic_bit++; - } - - stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, - true, priv->mode, true, true, - xdp_desc.len); - - stmmac_enable_dma_transmission(priv, priv->ioaddr); - - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); - entry = tx_q->cur_tx; - } - - if (tx_desc) { - stmmac_flush_tx_descriptors(priv, queue); - xsk_tx_release(pool); - } - - /* Return true if all of the 3 conditions are met - * a) TX Budget is still available - * b) work_done = true when XSK TX desc peek is empty (no more - * pending XSK TX for transmission) - */ - return !!budget && work_done; -} - -static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) -{ - if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { - tc += 64; - - if (priv->plat->force_thresh_dma_mode) - stmmac_set_dma_operation_mode(priv, tc, tc, chan); - else - stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, - chan); - - priv->xstats.threshold = tc; - } -} - -/** - * stmmac_tx_clean - to manage the transmission completion - * @priv: driver private structure - * @budget: napi budget limiting this functions packet handling - * @queue: TX queue index - * Description: it reclaims the transmit resources after transmission completes. - */ -static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - unsigned int bytes_compl = 0, pkts_compl = 0; - unsigned int entry, xmits = 0, count = 0; - - __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); - - priv->xstats.tx_clean++; - - tx_q->xsk_frames_done = 0; - - entry = tx_q->dirty_tx; - - /* Try to clean all TX complete frame in 1 shot */ - while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) { - struct xdp_frame *xdpf; - struct sk_buff *skb; - struct dma_desc *p; - int status; - - if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || - tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { - xdpf = tx_q->xdpf[entry]; - skb = NULL; - } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { - xdpf = NULL; - skb = tx_q->tx_skbuff[entry]; - } else { - xdpf = NULL; - skb = NULL; - } - - if (priv->extend_desc) - p = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &tx_q->dma_entx[entry].basic; - else - p = tx_q->dma_tx + entry; - - status = stmmac_tx_status(priv, &priv->dev->stats, - &priv->xstats, p, priv->ioaddr); - /* Check if the descriptor is owned by the DMA */ - if (unlikely(status & tx_dma_own)) - break; - - count++; - - /* Make sure descriptor fields are read after reading - * the own bit. - */ - dma_rmb(); - - /* Just consider the last segment and ...*/ - if (likely(!(status & tx_not_ls))) { - /* ... verify the status error condition */ - if (unlikely(status & tx_err)) { - priv->dev->stats.tx_errors++; - if (unlikely(status & tx_err_bump_tc)) - stmmac_bump_dma_threshold(priv, queue); - } else { - priv->dev->stats.tx_packets++; - priv->xstats.tx_pkt_n++; - priv->xstats.txq_stats[queue].tx_pkt_n++; - } - if (skb) - stmmac_get_tx_hwtstamp(priv, p, skb); - } - - if (likely(tx_q->tx_skbuff_dma[entry].buf && - tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { - if (tx_q->tx_skbuff_dma[entry].map_as_page) - dma_unmap_page(priv->device, - tx_q->tx_skbuff_dma[entry].buf, - tx_q->tx_skbuff_dma[entry].len, - DMA_TO_DEVICE); - else - dma_unmap_single(priv->device, - tx_q->tx_skbuff_dma[entry].buf, - tx_q->tx_skbuff_dma[entry].len, - DMA_TO_DEVICE); - tx_q->tx_skbuff_dma[entry].buf = 0; - tx_q->tx_skbuff_dma[entry].len = 0; - tx_q->tx_skbuff_dma[entry].map_as_page = false; - } - - stmmac_clean_desc3(priv, tx_q, p); - - tx_q->tx_skbuff_dma[entry].last_segment = false; - tx_q->tx_skbuff_dma[entry].is_jumbo = false; - - if (xdpf && - tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { - xdp_return_frame_rx_napi(xdpf); - tx_q->xdpf[entry] = NULL; - } - - if (xdpf && - tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { - xdp_return_frame(xdpf); - tx_q->xdpf[entry] = NULL; - } - - if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) - tx_q->xsk_frames_done++; - - if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { - if (likely(skb)) { - pkts_compl++; - bytes_compl += skb->len; - dev_consume_skb_any(skb); - tx_q->tx_skbuff[entry] = NULL; - } - } - - stmmac_release_tx_desc(priv, p, priv->mode); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - } - tx_q->dirty_tx = entry; - - netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), - pkts_compl, bytes_compl); - - if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, - queue))) && - stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { - - netif_dbg(priv, tx_done, priv->dev, - "%s: restart transmit\n", __func__); - netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); - } - - if (tx_q->xsk_pool) { - bool work_done; - - if (tx_q->xsk_frames_done) - xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); - - if (xsk_uses_need_wakeup(tx_q->xsk_pool)) - xsk_set_tx_need_wakeup(tx_q->xsk_pool); - - /* For XSK TX, we try to send as many as possible. - * If XSK work done (XSK TX desc empty and budget still - * available), return "budget - 1" to reenable TX IRQ. - * Else, return "budget" to make NAPI continue polling. - */ - work_done = stmmac_xdp_xmit_zc(priv, queue, - STMMAC_XSK_TX_BUDGET_MAX); - if (work_done) - xmits = budget - 1; - else - xmits = budget; - } - - if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && - priv->eee_sw_timer_en) { - stmmac_enable_eee_mode(priv); - mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); - } - - /* We still have pending packets, let's call for a new scheduling */ - if (tx_q->dirty_tx != tx_q->cur_tx) - hrtimer_start(&tx_q->txtimer, - STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), - HRTIMER_MODE_REL); - - __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); - - /* Combine decisions from TX clean and XSK TX */ - return max(count, xmits); -} - -/** - * stmmac_tx_err - to manage the tx error - * @priv: driver private structure - * @chan: channel index - * Description: it cleans the descriptors and restarts the transmission - * in case of transmission errors. - */ -static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); - - stmmac_stop_tx_dma(priv, chan); - dma_free_tx_skbufs(priv, chan); - stmmac_clear_tx_descriptors(priv, chan); - tx_q->dirty_tx = 0; - tx_q->cur_tx = 0; - tx_q->mss = 0; - netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); - stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - tx_q->dma_tx_phy, chan); - stmmac_start_tx_dma(priv, chan); - - priv->dev->stats.tx_errors++; - netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); -} - -/** - * stmmac_set_dma_operation_mode - Set DMA operation mode by channel - * @priv: driver private structure - * @txmode: TX operating mode - * @rxmode: RX operating mode - * @chan: channel index - * Description: it is used for configuring of the DMA operation mode in - * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward - * mode. - */ -static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, - u32 rxmode, u32 chan) -{ - u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; - u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - int rxfifosz = priv->plat->rx_fifo_size; - int txfifosz = priv->plat->tx_fifo_size; - - if (rxfifosz == 0) - rxfifosz = priv->dma_cap.rx_fifo_size; - if (txfifosz == 0) - txfifosz = priv->dma_cap.tx_fifo_size; - - /* Adjust for real per queue fifo size */ - rxfifosz /= rx_channels_count; - txfifosz /= tx_channels_count; - - stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); - stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); -} - -static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) -{ - int ret; - - ret = stmmac_safety_feat_irq_status(priv, priv->dev, - priv->ioaddr, priv->dma_cap.asp, &priv->sstats); - if (ret && (ret != -EINVAL)) { - stmmac_global_err(priv); - return true; - } - - return false; -} - -static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) -{ - int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, - &priv->xstats, chan, dir); - struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - struct stmmac_channel *ch = &priv->channel[chan]; - struct napi_struct *rx_napi; - struct napi_struct *tx_napi; - unsigned long flags; - - rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; - tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; - - if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { - if (napi_schedule_prep(rx_napi)) { - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); - __napi_schedule(rx_napi); - } - } - - if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { - if (napi_schedule_prep(tx_napi)) { - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - __napi_schedule(tx_napi); - } - } - - return status; -} - -/** - * stmmac_dma_interrupt - DMA ISR - * @priv: driver private structure - * Description: this is the DMA ISR. It is called by the main ISR. - * It calls the dwmac dma routine and schedule poll method in case of some - * work can be done. - */ -static void stmmac_dma_interrupt(struct stmmac_priv *priv) -{ - u32 tx_channel_count = priv->plat->tx_queues_to_use; - u32 rx_channel_count = priv->plat->rx_queues_to_use; - u32 channels_to_check = tx_channel_count > rx_channel_count ? - tx_channel_count : rx_channel_count; - u32 chan; - int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; - - /* Make sure we never check beyond our status buffer. */ - if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) - channels_to_check = ARRAY_SIZE(status); - - for (chan = 0; chan < channels_to_check; chan++) - status[chan] = stmmac_napi_check(priv, chan, - DMA_DIR_RXTX); - - for (chan = 0; chan < tx_channel_count; chan++) { - if (unlikely(status[chan] & tx_hard_error_bump_tc)) { - /* Try to bump up the dma threshold on this failure */ - stmmac_bump_dma_threshold(priv, chan); - } else if (unlikely(status[chan] == tx_hard_error)) { - stmmac_tx_err(priv, chan); - } - } -} - -/** - * stmmac_mmc_setup: setup the Mac Management Counters (MMC) - * @priv: driver private structure - * Description: this masks the MMC irq, in fact, the counters are managed in SW. - */ -static void stmmac_mmc_setup(struct stmmac_priv *priv) -{ - unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | - MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; - - stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); - - if (priv->dma_cap.rmon) { - stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); - memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); - } else - netdev_info(priv->dev, "No MAC Management Counters available\n"); -} - -/** - * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. - * @priv: driver private structure - * Description: - * new GMAC chip generations have a new register to indicate the - * presence of the optional feature/functions. - * This can be also used to override the value passed through the - * platform and necessary for old MAC10/100 and GMAC chips. - */ -static int stmmac_get_hw_features(struct stmmac_priv *priv) -{ - return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; -} - -/** - * stmmac_check_ether_addr - check if the MAC addr is valid - * @priv: driver private structure - * Description: - * it is to verify if the MAC address is valid, in case of failures it - * generates a random MAC address - */ -static void stmmac_check_ether_addr(struct stmmac_priv *priv) -{ - u8 addr[ETH_ALEN]; - - if (!is_valid_ether_addr(priv->dev->dev_addr)) { - stmmac_get_umac_addr(priv, priv->hw, addr, 0); - if (is_valid_ether_addr(addr)) - eth_hw_addr_set(priv->dev, addr); - else - eth_hw_addr_random(priv->dev); - dev_info(priv->device, "device MAC address %pM\n", - priv->dev->dev_addr); - } -} - -/** - * stmmac_init_dma_engine - DMA init. - * @priv: driver private structure - * Description: - * It inits the DMA invoking the specific MAC/GMAC callback. - * Some DMA parameters can be passed from the platform; - * in case of these are not passed a default is kept for the MAC or GMAC. - */ -static int stmmac_init_dma_engine(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); - struct stmmac_rx_queue *rx_q; - struct stmmac_tx_queue *tx_q; - u32 chan = 0; - int atds = 0; - int ret = 0; - - if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { - dev_err(priv->device, "Invalid DMA configuration\n"); - return -EINVAL; - } - - if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) - atds = 1; - - ret = stmmac_reset(priv, priv->ioaddr); - if (ret) { - dev_err(priv->device, "Failed to reset the dma\n"); - return ret; - } - - /* DMA Configuration */ - stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); - - if (priv->plat->axi) - stmmac_axi(priv, priv->ioaddr, priv->plat->axi); - - /* DMA CSR Channel configuration */ - for (chan = 0; chan < dma_csr_ch; chan++) - stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); - - /* DMA RX Channel Configuration */ - for (chan = 0; chan < rx_channels_count; chan++) { - rx_q = &priv->rx_queue[chan]; - - stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - rx_q->dma_rx_phy, chan); - - rx_q->rx_tail_addr = rx_q->dma_rx_phy + - (rx_q->buf_alloc_num * - sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, - rx_q->rx_tail_addr, chan); - } - - /* DMA TX Channel Configuration */ - for (chan = 0; chan < tx_channels_count; chan++) { - tx_q = &priv->tx_queue[chan]; - - stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - tx_q->dma_tx_phy, chan); - - tx_q->tx_tail_addr = tx_q->dma_tx_phy; - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, - tx_q->tx_tail_addr, chan); - } - - return ret; -} - -static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - hrtimer_start(&tx_q->txtimer, - STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), - HRTIMER_MODE_REL); -} - -/** - * stmmac_tx_timer - mitigation sw timer for tx. - * @t: data pointer - * Description: - * This is the timer handler to directly invoke the stmmac_tx_clean. - */ -static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) -{ - struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); - struct stmmac_priv *priv = tx_q->priv_data; - struct stmmac_channel *ch; - struct napi_struct *napi; - - ch = &priv->channel[tx_q->queue_index]; - napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; - - if (likely(napi_schedule_prep(napi))) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - __napi_schedule(napi); - } - - return HRTIMER_NORESTART; -} - -/** - * stmmac_init_coalesce - init mitigation options. - * @priv: driver private structure - * Description: - * This inits the coalesce parameters: i.e. timer rate, - * timer handler and default threshold used for enabling the - * interrupt on completion bit. - */ -static void stmmac_init_coalesce(struct stmmac_priv *priv) -{ - u32 tx_channel_count = priv->plat->tx_queues_to_use; - u32 rx_channel_count = priv->plat->rx_queues_to_use; - u32 chan; - - for (chan = 0; chan < tx_channel_count; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - - priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; - priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; - - hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - tx_q->txtimer.function = stmmac_tx_timer; - } - - for (chan = 0; chan < rx_channel_count; chan++) - priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; -} - -static void stmmac_set_rings_length(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 chan; - - /* set TX ring length */ - for (chan = 0; chan < tx_channels_count; chan++) - stmmac_set_tx_ring_len(priv, priv->ioaddr, - (priv->dma_tx_size - 1), chan); - - /* set RX ring length */ - for (chan = 0; chan < rx_channels_count; chan++) - stmmac_set_rx_ring_len(priv, priv->ioaddr, - (priv->dma_rx_size - 1), chan); -} - -/** - * stmmac_set_tx_queue_weight - Set TX queue weight - * @priv: driver private structure - * Description: It is used for setting TX queues weight - */ -static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) -{ - u32 tx_queues_count = priv->plat->tx_queues_to_use; - u32 weight; - u32 queue; - - for (queue = 0; queue < tx_queues_count; queue++) { - weight = priv->plat->tx_queues_cfg[queue].weight; - stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); - } -} - -/** - * stmmac_configure_cbs - Configure CBS in TX queue - * @priv: driver private structure - * Description: It is used for configuring CBS in AVB TX queues - */ -static void stmmac_configure_cbs(struct stmmac_priv *priv) -{ - u32 tx_queues_count = priv->plat->tx_queues_to_use; - u32 mode_to_use; - u32 queue; - - /* queue 0 is reserved for legacy traffic */ - for (queue = 1; queue < tx_queues_count; queue++) { - mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; - if (mode_to_use == MTL_QUEUE_DCB) - continue; - - stmmac_config_cbs(priv, priv->hw, - priv->plat->tx_queues_cfg[queue].send_slope, - priv->plat->tx_queues_cfg[queue].idle_slope, - priv->plat->tx_queues_cfg[queue].high_credit, - priv->plat->tx_queues_cfg[queue].low_credit, - queue); - } -} - -/** - * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel - * @priv: driver private structure - * Description: It is used for mapping RX queues to RX dma channels - */ -static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 queue; - u32 chan; - - for (queue = 0; queue < rx_queues_count; queue++) { - chan = priv->plat->rx_queues_cfg[queue].chan; - stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); - } -} - -/** - * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority - * @priv: driver private structure - * Description: It is used for configuring the RX Queue Priority - */ -static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 queue; - u32 prio; - - for (queue = 0; queue < rx_queues_count; queue++) { - if (!priv->plat->rx_queues_cfg[queue].use_prio) - continue; - - prio = priv->plat->rx_queues_cfg[queue].prio; - stmmac_rx_queue_prio(priv, priv->hw, prio, queue); - } -} - -/** - * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority - * @priv: driver private structure - * Description: It is used for configuring the TX Queue Priority - */ -static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) -{ - u32 tx_queues_count = priv->plat->tx_queues_to_use; - u32 queue; - u32 prio; - - for (queue = 0; queue < tx_queues_count; queue++) { - if (!priv->plat->tx_queues_cfg[queue].use_prio) - continue; - - prio = priv->plat->tx_queues_cfg[queue].prio; - stmmac_tx_queue_prio(priv, priv->hw, prio, queue); - } -} - -/** - * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing - * @priv: driver private structure - * Description: It is used for configuring the RX queue routing - */ -static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 queue; - u8 packet; - - for (queue = 0; queue < rx_queues_count; queue++) { - /* no specific packet type routing specified for the queue */ - if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) - continue; - - packet = priv->plat->rx_queues_cfg[queue].pkt_route; - stmmac_rx_queue_routing(priv, priv->hw, packet, queue); - } -} - -static void stmmac_mac_config_rss(struct stmmac_priv *priv) -{ - if (!priv->dma_cap.rssen || !priv->plat->rss_en) { - priv->rss.enable = false; - return; - } - - if (priv->dev->features & NETIF_F_RXHASH) - priv->rss.enable = true; - else - priv->rss.enable = false; - - stmmac_rss_configure(priv, priv->hw, &priv->rss, - priv->plat->rx_queues_to_use); -} - -/** - * stmmac_mtl_configuration - Configure MTL - * @priv: driver private structure - * Description: It is used for configurring MTL - */ -static void stmmac_mtl_configuration(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 tx_queues_count = priv->plat->tx_queues_to_use; - - if (tx_queues_count > 1) - stmmac_set_tx_queue_weight(priv); - - /* Configure MTL RX algorithms */ - if (rx_queues_count > 1) - stmmac_prog_mtl_rx_algorithms(priv, priv->hw, - priv->plat->rx_sched_algorithm); - - /* Configure MTL TX algorithms */ - if (tx_queues_count > 1) - stmmac_prog_mtl_tx_algorithms(priv, priv->hw, - priv->plat->tx_sched_algorithm); - - /* Configure CBS in AVB TX queues */ - if (tx_queues_count > 1) - stmmac_configure_cbs(priv); - - /* Map RX MTL to DMA channels */ - stmmac_rx_queue_dma_chan_map(priv); - - /* Enable MAC RX Queues */ - stmmac_mac_enable_rx_queues(priv); - - /* Set RX priorities */ - if (rx_queues_count > 1) - stmmac_mac_config_rx_queues_prio(priv); - - /* Set TX priorities */ - if (tx_queues_count > 1) - stmmac_mac_config_tx_queues_prio(priv); - - /* Set RX routing */ - if (rx_queues_count > 1) - stmmac_mac_config_rx_queues_routing(priv); - - /* Receive Side Scaling */ - if (rx_queues_count > 1) - stmmac_mac_config_rss(priv); -} - -static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) -{ - if (priv->dma_cap.asp) { - netdev_info(priv->dev, "Enabling Safety Features\n"); - stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, - priv->plat->safety_feat_cfg); - } else { - netdev_info(priv->dev, "No Safety Features support found\n"); - } -} - -static int stmmac_fpe_start_wq(struct stmmac_priv *priv) -{ - char *name; - - clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); - clear_bit(__FPE_REMOVING, &priv->fpe_task_state); - - name = priv->wq_name; - sprintf(name, "%s-fpe", priv->dev->name); - - priv->fpe_wq = create_singlethread_workqueue(name); - if (!priv->fpe_wq) { - netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); - - return -ENOMEM; - } - netdev_info(priv->dev, "FPE workqueue start"); - - return 0; -} - -/** - * stmmac_hw_setup - setup mac in a usable state. - * @dev : pointer to the device structure. - * @init_ptp: initialize PTP if set - * Description: - * this is the main function to setup the HW in a usable state because the - * dma engine is reset, the core registers are configured (e.g. AXI, - * Checksum features, timers). The DMA is ready to start receiving and - * transmitting. - * Return value: - * 0 on success and an appropriate (-)ve integer as defined in errno.h - * file on failure. - */ -static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 rx_cnt = priv->plat->rx_queues_to_use; - u32 tx_cnt = priv->plat->tx_queues_to_use; - bool sph_en; - u32 chan; - int ret; - - /* DMA initialization and SW reset */ - ret = stmmac_init_dma_engine(priv); - if (ret < 0) { - netdev_err(priv->dev, "%s: DMA engine initialization failed\n", - __func__); - return ret; - } - - /* Copy the MAC addr into the HW */ - stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); - - /* PS and related bits will be programmed according to the speed */ - if (priv->hw->pcs) { - int speed = priv->plat->mac_port_sel_speed; - - if ((speed == SPEED_10) || (speed == SPEED_100) || - (speed == SPEED_1000)) { - priv->hw->ps = speed; - } else { - dev_warn(priv->device, "invalid port speed\n"); - priv->hw->ps = 0; - } - } - - /* Initialize the MAC Core */ - stmmac_core_init(priv, priv->hw, dev); - - /* Initialize MTL*/ - stmmac_mtl_configuration(priv); - - /* Initialize Safety Features */ - stmmac_safety_feat_configuration(priv); - - ret = stmmac_rx_ipc(priv, priv->hw); - if (!ret) { - netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); - priv->plat->rx_coe = STMMAC_RX_COE_NONE; - priv->hw->rx_csum = 0; - } - - /* Enable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, true); - - /* Set the HW DMA mode and the COE */ - stmmac_dma_operation_mode(priv); - - stmmac_mmc_setup(priv); - - if (init_ptp) { - ret = stmmac_init_ptp(priv); - if (ret == -EOPNOTSUPP) - netdev_warn(priv->dev, "PTP not supported by HW\n"); - else if (ret) - netdev_warn(priv->dev, "PTP init failed\n"); - } - - priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; - - /* Convert the timer from msec to usec */ - if (!priv->tx_lpi_timer) - priv->tx_lpi_timer = eee_timer * 1000; - - if (priv->use_riwt) { - u32 queue; - - for (queue = 0; queue < rx_cnt; queue++) { - if (!priv->rx_riwt[queue]) - priv->rx_riwt[queue] = DEF_DMA_RIWT; - - stmmac_rx_watchdog(priv, priv->ioaddr, - priv->rx_riwt[queue], queue); - } - } - - if (priv->hw->pcs) - stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); - - /* set TX and RX rings length */ - stmmac_set_rings_length(priv); - - /* Enable TSO */ - if (priv->tso) { - for (chan = 0; chan < tx_cnt; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - - /* TSO and TBS cannot co-exist */ - if (tx_q->tbs & STMMAC_TBS_AVAIL) - continue; - - stmmac_enable_tso(priv, priv->ioaddr, 1, chan); - } - } - - /* Enable Split Header */ - sph_en = (priv->hw->rx_csum > 0) && priv->sph; - for (chan = 0; chan < rx_cnt; chan++) - stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); - - - /* VLAN Tag Insertion */ - if (priv->dma_cap.vlins) - stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); - - /* TBS */ - for (chan = 0; chan < tx_cnt; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - int enable = tx_q->tbs & STMMAC_TBS_AVAIL; - - stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); - } - - /* Configure real RX and TX queues */ - netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); - netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); - - /* Start the ball rolling... */ - stmmac_start_all_dma(priv); - - if (priv->dma_cap.fpesel) { - stmmac_fpe_start_wq(priv); - - if (priv->plat->fpe_cfg->enable) - stmmac_fpe_handshake(priv, true); - } - - return 0; -} - -static void stmmac_hw_teardown(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - clk_disable_unprepare(priv->plat->clk_ptp_ref); -} - -static void stmmac_free_irq(struct net_device *dev, - enum request_irq_err irq_err, int irq_idx) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int j; - - switch (irq_err) { - case REQ_IRQ_ERR_ALL: - irq_idx = priv->plat->tx_queues_to_use; - fallthrough; - case REQ_IRQ_ERR_TX: - for (j = irq_idx - 1; j >= 0; j--) { - if (priv->tx_irq[j] > 0) { - irq_set_affinity_hint(priv->tx_irq[j], NULL); - free_irq(priv->tx_irq[j], &priv->tx_queue[j]); - } - } - irq_idx = priv->plat->rx_queues_to_use; - fallthrough; - case REQ_IRQ_ERR_RX: - for (j = irq_idx - 1; j >= 0; j--) { - if (priv->rx_irq[j] > 0) { - irq_set_affinity_hint(priv->rx_irq[j], NULL); - free_irq(priv->rx_irq[j], &priv->rx_queue[j]); - } - } - - if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) - free_irq(priv->sfty_ue_irq, dev); - fallthrough; - case REQ_IRQ_ERR_SFTY_UE: - if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) - free_irq(priv->sfty_ce_irq, dev); - fallthrough; - case REQ_IRQ_ERR_SFTY_CE: - if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) - free_irq(priv->lpi_irq, dev); - fallthrough; - case REQ_IRQ_ERR_LPI: - if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) - free_irq(priv->wol_irq, dev); - fallthrough; - case REQ_IRQ_ERR_WOL: - free_irq(dev->irq, dev); - fallthrough; - case REQ_IRQ_ERR_MAC: - case REQ_IRQ_ERR_NO: - /* If MAC IRQ request error, no more IRQ to free */ - break; - } -} - -static int stmmac_request_irq_multi_msi(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - enum request_irq_err irq_err; - cpumask_t cpu_mask; - int irq_idx = 0; - char *int_name; - int ret; - int i; - - /* For common interrupt */ - int_name = priv->int_name_mac; - sprintf(int_name, "%s:%s", dev->name, "mac"); - ret = request_irq(dev->irq, stmmac_mac_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc mac MSI %d (error: %d)\n", - __func__, dev->irq, ret); - irq_err = REQ_IRQ_ERR_MAC; - goto irq_error; - } - - /* Request the Wake IRQ in case of another line - * is used for WoL - */ - if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { - int_name = priv->int_name_wol; - sprintf(int_name, "%s:%s", dev->name, "wol"); - ret = request_irq(priv->wol_irq, - stmmac_mac_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc wol MSI %d (error: %d)\n", - __func__, priv->wol_irq, ret); - irq_err = REQ_IRQ_ERR_WOL; - goto irq_error; - } - } - - /* Request the LPI IRQ in case of another line - * is used for LPI - */ - if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { - int_name = priv->int_name_lpi; - sprintf(int_name, "%s:%s", dev->name, "lpi"); - ret = request_irq(priv->lpi_irq, - stmmac_mac_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc lpi MSI %d (error: %d)\n", - __func__, priv->lpi_irq, ret); - irq_err = REQ_IRQ_ERR_LPI; - goto irq_error; - } - } - - /* Request the Safety Feature Correctible Error line in - * case of another line is used - */ - if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { - int_name = priv->int_name_sfty_ce; - sprintf(int_name, "%s:%s", dev->name, "safety-ce"); - ret = request_irq(priv->sfty_ce_irq, - stmmac_safety_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc sfty ce MSI %d (error: %d)\n", - __func__, priv->sfty_ce_irq, ret); - irq_err = REQ_IRQ_ERR_SFTY_CE; - goto irq_error; - } - } - - /* Request the Safety Feature Uncorrectible Error line in - * case of another line is used - */ - if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { - int_name = priv->int_name_sfty_ue; - sprintf(int_name, "%s:%s", dev->name, "safety-ue"); - ret = request_irq(priv->sfty_ue_irq, - stmmac_safety_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc sfty ue MSI %d (error: %d)\n", - __func__, priv->sfty_ue_irq, ret); - irq_err = REQ_IRQ_ERR_SFTY_UE; - goto irq_error; - } - } - - /* Request Rx MSI irq */ - for (i = 0; i < priv->plat->rx_queues_to_use; i++) { - if (i >= MTL_MAX_RX_QUEUES) - break; - if (priv->rx_irq[i] == 0) - continue; - - int_name = priv->int_name_rx_irq[i]; - sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); - ret = request_irq(priv->rx_irq[i], - stmmac_msi_intr_rx, - 0, int_name, &priv->rx_queue[i]); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc rx-%d MSI %d (error: %d)\n", - __func__, i, priv->rx_irq[i], ret); - irq_err = REQ_IRQ_ERR_RX; - irq_idx = i; - goto irq_error; - } - cpumask_clear(&cpu_mask); - cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); - irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); - } - - /* Request Tx MSI irq */ - for (i = 0; i < priv->plat->tx_queues_to_use; i++) { - if (i >= MTL_MAX_TX_QUEUES) - break; - if (priv->tx_irq[i] == 0) - continue; - - int_name = priv->int_name_tx_irq[i]; - sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); - ret = request_irq(priv->tx_irq[i], - stmmac_msi_intr_tx, - 0, int_name, &priv->tx_queue[i]); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc tx-%d MSI %d (error: %d)\n", - __func__, i, priv->tx_irq[i], ret); - irq_err = REQ_IRQ_ERR_TX; - irq_idx = i; - goto irq_error; - } - cpumask_clear(&cpu_mask); - cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); - irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); - } - - return 0; - -irq_error: - stmmac_free_irq(dev, irq_err, irq_idx); - return ret; -} - -static int stmmac_request_irq_single(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - enum request_irq_err irq_err; - int ret; - - ret = request_irq(dev->irq, stmmac_interrupt, - IRQF_SHARED, dev->name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: ERROR: allocating the IRQ %d (error: %d)\n", - __func__, dev->irq, ret); - irq_err = REQ_IRQ_ERR_MAC; - goto irq_error; - } - - /* Request the Wake IRQ in case of another line - * is used for WoL - */ - if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { - ret = request_irq(priv->wol_irq, stmmac_interrupt, - IRQF_SHARED, dev->name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: ERROR: allocating the WoL IRQ %d (%d)\n", - __func__, priv->wol_irq, ret); - irq_err = REQ_IRQ_ERR_WOL; - goto irq_error; - } - } - - /* Request the IRQ lines */ - if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { - ret = request_irq(priv->lpi_irq, stmmac_interrupt, - IRQF_SHARED, dev->name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: ERROR: allocating the LPI IRQ %d (%d)\n", - __func__, priv->lpi_irq, ret); - irq_err = REQ_IRQ_ERR_LPI; - goto irq_error; - } - } - - return 0; - -irq_error: - stmmac_free_irq(dev, irq_err, 0); - return ret; -} - -static int stmmac_request_irq(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret; - - /* Request the IRQ lines */ - if (priv->plat->multi_msi_en) - ret = stmmac_request_irq_multi_msi(dev); - else - ret = stmmac_request_irq_single(dev); - - return ret; -} - -/** - * stmmac_open - open entry point of the driver - * @dev : pointer to the device structure. - * Description: - * This function is the open entry point of the driver. - * Return value: - * 0 on success and an appropriate (-)ve integer as defined in errno.h - * file on failure. - */ -static int stmmac_open(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int mode = priv->plat->phy_interface; - int bfsize = 0; - u32 chan; - int ret; - - ret = pm_runtime_get_sync(priv->device); - if (ret < 0) { - pm_runtime_put_noidle(priv->device); - return ret; - } - - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI && - (!priv->hw->xpcs || - xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { - ret = stmmac_init_phy(dev); - if (ret) { - netdev_err(priv->dev, - "%s: Cannot attach to PHY (error: %d)\n", - __func__, ret); - goto init_phy_error; - } - } - - /* Extra statistics */ - memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); - priv->xstats.threshold = tc; - - bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); - if (bfsize < 0) - bfsize = 0; - - if (bfsize < BUF_SIZE_16KiB) - bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); - - priv->dma_buf_sz = bfsize; - buf_sz = bfsize; - - priv->rx_copybreak = STMMAC_RX_COPYBREAK; - - if (!priv->dma_tx_size) - priv->dma_tx_size = DMA_DEFAULT_TX_SIZE; - if (!priv->dma_rx_size) - priv->dma_rx_size = DMA_DEFAULT_RX_SIZE; - - /* Earlier check for TBS */ - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; - - /* Setup per-TXQ tbs flag before TX descriptor alloc */ - tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; - } - - ret = alloc_dma_desc_resources(priv); - if (ret < 0) { - netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", - __func__); - goto dma_desc_error; - } - - ret = init_dma_desc_rings(dev, GFP_KERNEL); - if (ret < 0) { - netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", - __func__); - goto init_error; - } - - ret = stmmac_hw_setup(dev, true); - if (ret < 0) { - netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); - goto init_error; - } - - stmmac_init_coalesce(priv); - - phylink_start(priv->phylink); - /* We may have called phylink_speed_down before */ - phylink_speed_up(priv->phylink); - - ret = stmmac_request_irq(dev); - if (ret) - goto irq_error; - - stmmac_enable_all_queues(priv); - netif_tx_start_all_queues(priv->dev); - - return 0; - -irq_error: - phylink_stop(priv->phylink); - - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - stmmac_hw_teardown(dev); -init_error: - free_dma_desc_resources(priv); -dma_desc_error: - phylink_disconnect_phy(priv->phylink); -init_phy_error: - pm_runtime_put(priv->device); - return ret; -} - -static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) -{ - set_bit(__FPE_REMOVING, &priv->fpe_task_state); - - if (priv->fpe_wq) - destroy_workqueue(priv->fpe_wq); - - netdev_info(priv->dev, "FPE workqueue stop"); -} - -/** - * stmmac_release - close entry point of the driver - * @dev : device pointer. - * Description: - * This is the stop entry point of the driver. - */ -static int stmmac_release(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 chan; - - netif_tx_disable(dev); - - if (device_may_wakeup(priv->device)) - phylink_speed_down(priv->phylink, false); - /* Stop and disconnect the PHY */ - phylink_stop(priv->phylink); - phylink_disconnect_phy(priv->phylink); - - stmmac_disable_all_queues(priv); - - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - /* Free the IRQ lines */ - stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); - - if (priv->eee_enabled) { - priv->tx_path_in_lpi_mode = false; - del_timer_sync(&priv->eee_ctrl_timer); - } - - /* Stop TX/RX DMA and clear the descriptors */ - stmmac_stop_all_dma(priv); - - /* Release and free the Rx/Tx resources */ - free_dma_desc_resources(priv); - - /* Disable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, false); - - netif_carrier_off(dev); - - stmmac_release_ptp(priv); - - pm_runtime_put(priv->device); - - if (priv->dma_cap.fpesel) - stmmac_fpe_stop_wq(priv); - - return 0; -} - -static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, - struct stmmac_tx_queue *tx_q) -{ - u16 tag = 0x0, inner_tag = 0x0; - u32 inner_type = 0x0; - struct dma_desc *p; - - if (!priv->dma_cap.vlins) - return false; - if (!skb_vlan_tag_present(skb)) - return false; - if (skb->vlan_proto == htons(ETH_P_8021AD)) { - inner_tag = skb_vlan_tag_get(skb); - inner_type = STMMAC_VLAN_INSERT; - } - - tag = skb_vlan_tag_get(skb); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - p = &tx_q->dma_tx[tx_q->cur_tx]; - - if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) - return false; - - stmmac_set_tx_owner(priv, p); - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); - return true; -} - -/** - * stmmac_tso_allocator - close entry point of the driver - * @priv: driver private structure - * @des: buffer start address - * @total_len: total length to fill in descriptors - * @last_segment: condition for the last descriptor - * @queue: TX queue index - * Description: - * This function fills descriptor and request new descriptors according to - * buffer length to fill - */ -static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, - int total_len, bool last_segment, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - struct dma_desc *desc; - u32 buff_size; - int tmp_len; - - tmp_len = total_len; - - while (tmp_len > 0) { - dma_addr_t curr_addr; - - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, - priv->dma_tx_size); - WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - desc = &tx_q->dma_tx[tx_q->cur_tx]; - - curr_addr = des + (total_len - tmp_len); - if (priv->dma_cap.addr64 <= 32) - desc->des0 = cpu_to_le32(curr_addr); - else - stmmac_set_desc_addr(priv, desc, curr_addr); - - buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? - TSO_MAX_BUFF_SIZE : tmp_len; - - stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, - 0, 1, - (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), - 0, 0); - - tmp_len -= TSO_MAX_BUFF_SIZE; - } -} - -static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int desc_size; - - if (likely(priv->extend_desc)) - desc_size = sizeof(struct dma_extended_desc); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc_size = sizeof(struct dma_edesc); - else - desc_size = sizeof(struct dma_desc); - - /* The own bit must be the latest setting done when prepare the - * descriptor and then barrier is needed to make sure that - * all is coherent before granting the DMA engine. - */ - wmb(); - - tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); -} - -/** - * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) - * @skb : the socket buffer - * @dev : device pointer - * Description: this is the transmit function that is called on TSO frames - * (support available on GMAC4 and newer chips). - * Diagram below show the ring programming in case of TSO frames: - * - * First Descriptor - * -------- - * | DES0 |---> buffer1 = L2/L3/L4 header - * | DES1 |---> TCP Payload (can continue on next descr...) - * | DES2 |---> buffer 1 and 2 len - * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] - * -------- - * | - * ... - * | - * -------- - * | DES0 | --| Split TCP Payload on Buffers 1 and 2 - * | DES1 | --| - * | DES2 | --> buffer 1 and 2 len - * | DES3 | - * -------- - * - * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. - */ -static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct dma_desc *desc, *first, *mss_desc = NULL; - struct stmmac_priv *priv = netdev_priv(dev); - int nfrags = skb_shinfo(skb)->nr_frags; - u32 queue = skb_get_queue_mapping(skb); - unsigned int first_entry, tx_packets; - int tmp_pay_len = 0, first_tx; - struct stmmac_tx_queue *tx_q; - bool has_vlan, set_ic; - u8 proto_hdr_len, hdr; - u32 pay_len, mss; - dma_addr_t des; - int i; - - tx_q = &priv->tx_queue[queue]; - first_tx = tx_q->cur_tx; - - /* Compute header lengths */ - if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { - proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); - hdr = sizeof(struct udphdr); - } else { - proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); - hdr = tcp_hdrlen(skb); - } - - /* Desc availability based on threshold should be enough safe */ - if (unlikely(stmmac_tx_avail(priv, queue) < - (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { - if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, - queue)); - /* This is a hard error, log it. */ - netdev_err(priv->dev, - "%s: Tx Ring full when queue awake\n", - __func__); - } - return NETDEV_TX_BUSY; - } - - pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ - - mss = skb_shinfo(skb)->gso_size; - - /* set new MSS value if needed */ - if (mss != tx_q->mss) { - if (tx_q->tbs & STMMAC_TBS_AVAIL) - mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; - - stmmac_set_mss(priv, mss_desc, mss); - tx_q->mss = mss; - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, - priv->dma_tx_size); - WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); - } - - if (netif_msg_tx_queued(priv)) { - pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", - __func__, hdr, proto_hdr_len, pay_len, mss); - pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, - skb->data_len); - } - - /* Check if VLAN can be inserted by HW */ - has_vlan = stmmac_vlan_insert(priv, skb, tx_q); - - first_entry = tx_q->cur_tx; - WARN_ON(tx_q->tx_skbuff[first_entry]); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[first_entry].basic; - else - desc = &tx_q->dma_tx[first_entry]; - first = desc; - - if (has_vlan) - stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); - - /* first descriptor: fill Headers on Buf1 */ - des = dma_map_single(priv->device, skb->data, skb_headlen(skb), - DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; - - tx_q->tx_skbuff_dma[first_entry].buf = des; - tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); - tx_q->tx_skbuff_dma[first_entry].map_as_page = false; - tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; - - if (priv->dma_cap.addr64 <= 32) { - first->des0 = cpu_to_le32(des); - - /* Fill start of payload in buff2 of first descriptor */ - if (pay_len) - first->des1 = cpu_to_le32(des + proto_hdr_len); - - /* If needed take extra descriptors to fill the remaining payload */ - tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; - } else { - stmmac_set_desc_addr(priv, first, des); - tmp_pay_len = pay_len; - des += proto_hdr_len; - pay_len = 0; - } - - stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); - - /* Prepare fragments */ - for (i = 0; i < nfrags; i++) { - const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; - - des = skb_frag_dma_map(priv->device, frag, 0, - skb_frag_size(frag), - DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; - - stmmac_tso_allocator(priv, des, skb_frag_size(frag), - (i == nfrags - 1), queue); - - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; - tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); - tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; - } - - tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; - - /* Only the last descriptor gets to point to the skb. */ - tx_q->tx_skbuff[tx_q->cur_tx] = skb; - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; - - /* Manage tx mitigation */ - tx_packets = (tx_q->cur_tx + 1) - first_tx; - tx_q->tx_count_frames += tx_packets; - - if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) - set_ic = true; - else if (!priv->tx_coal_frames[queue]) - set_ic = false; - else if (tx_packets > priv->tx_coal_frames[queue]) - set_ic = true; - else if ((tx_q->tx_count_frames % - priv->tx_coal_frames[queue]) < tx_packets) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - desc = &tx_q->dma_tx[tx_q->cur_tx]; - - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, desc); - priv->xstats.tx_set_ic_bit++; - } - - /* We've used all descriptors we need for this skb, however, - * advance cur_tx so that it references a fresh descriptor. - * ndo_start_xmit will fill this descriptor the next time it's - * called and stmmac_tx_clean may clean up to this descriptor. - */ - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); - - if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { - netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", - __func__); - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); - } - - dev->stats.tx_bytes += skb->len; - priv->xstats.tx_tso_frames++; - priv->xstats.tx_tso_nfrags += nfrags; - - if (priv->sarc_type) - stmmac_set_desc_sarc(priv, first, priv->sarc_type); - - skb_tx_timestamp(skb); - - if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && - priv->hwts_tx_en)) { - /* declare that device is doing timestamping */ - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - stmmac_enable_tx_timestamp(priv, first); - } - - /* Complete the first descriptor before granting the DMA */ - stmmac_prepare_tso_tx_desc(priv, first, 1, - proto_hdr_len, - pay_len, - 1, tx_q->tx_skbuff_dma[first_entry].last_segment, - hdr / 4, (skb->len - proto_hdr_len)); - - /* If context desc is used to change MSS */ - if (mss_desc) { - /* Make sure that first descriptor has been completely - * written, including its own bit. This is because MSS is - * actually before first descriptor, so we need to make - * sure that MSS's own bit is the last thing written. - */ - dma_wmb(); - stmmac_set_tx_owner(priv, mss_desc); - } - - if (netif_msg_pktdata(priv)) { - pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", - __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, - tx_q->cur_tx, first, nfrags); - pr_info(">>> frame to be transmitted: "); - print_pkt(skb->data, skb_headlen(skb)); - } - - netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); - - stmmac_flush_tx_descriptors(priv, queue); - stmmac_tx_timer_arm(priv, queue); - - return NETDEV_TX_OK; - -dma_map_err: - dev_err(priv->device, "Tx dma map failed\n"); - dev_kfree_skb(skb); - priv->dev->stats.tx_dropped++; - return NETDEV_TX_OK; -} - -/** - * stmmac_xmit - Tx entry point of the driver - * @skb : the socket buffer - * @dev : device pointer - * Description : this is the tx entry point of the driver. - * It programs the chain or the ring and supports oversized frames - * and SG feature. - */ -static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) -{ - unsigned int first_entry, tx_packets, enh_desc; - struct stmmac_priv *priv = netdev_priv(dev); - unsigned int nopaged_len = skb_headlen(skb); - int i, csum_insertion = 0, is_jumbo = 0; - u32 queue = skb_get_queue_mapping(skb); - int nfrags = skb_shinfo(skb)->nr_frags; - int gso = skb_shinfo(skb)->gso_type; - struct dma_edesc *tbs_desc = NULL; - struct dma_desc *desc, *first; - struct stmmac_tx_queue *tx_q; - bool has_vlan, set_ic; - int entry, first_tx; - dma_addr_t des; - - tx_q = &priv->tx_queue[queue]; - first_tx = tx_q->cur_tx; - - if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) - stmmac_disable_eee_mode(priv); - - /* Manage oversized TCP frames for GMAC4 device */ - if (skb_is_gso(skb) && priv->tso) { - if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) - return stmmac_tso_xmit(skb, dev); - if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) - return stmmac_tso_xmit(skb, dev); - } - - if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { - if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, - queue)); - /* This is a hard error, log it. */ - netdev_err(priv->dev, - "%s: Tx Ring full when queue awake\n", - __func__); - } - return NETDEV_TX_BUSY; - } - - /* Check if VLAN can be inserted by HW */ - has_vlan = stmmac_vlan_insert(priv, skb, tx_q); - - entry = tx_q->cur_tx; - first_entry = entry; - WARN_ON(tx_q->tx_skbuff[first_entry]); - - csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); - - if (likely(priv->extend_desc)) - desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[entry].basic; - else - desc = tx_q->dma_tx + entry; - - first = desc; - - if (has_vlan) - stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); - - enh_desc = priv->plat->enh_desc; - /* To program the descriptors according to the size of the frame */ - if (enh_desc) - is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); - - if (unlikely(is_jumbo)) { - entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); - if (unlikely(entry < 0) && (entry != -EINVAL)) - goto dma_map_err; - } - - for (i = 0; i < nfrags; i++) { - const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; - int len = skb_frag_size(frag); - bool last_segment = (i == (nfrags - 1)); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - WARN_ON(tx_q->tx_skbuff[entry]); - - if (likely(priv->extend_desc)) - desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[entry].basic; - else - desc = tx_q->dma_tx + entry; - - des = skb_frag_dma_map(priv->device, frag, 0, len, - DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; /* should reuse desc w/o issues */ - - tx_q->tx_skbuff_dma[entry].buf = des; - - stmmac_set_desc_addr(priv, desc, des); - - tx_q->tx_skbuff_dma[entry].map_as_page = true; - tx_q->tx_skbuff_dma[entry].len = len; - tx_q->tx_skbuff_dma[entry].last_segment = last_segment; - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; - - /* Prepare the descriptor and set the own bit too */ - stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, - priv->mode, 1, last_segment, skb->len); - } - - /* Only the last descriptor gets to point to the skb. */ - tx_q->tx_skbuff[entry] = skb; - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; - - /* According to the coalesce parameter the IC bit for the latest - * segment is reset and the timer re-started to clean the tx status. - * This approach takes care about the fragments: desc is the first - * element in case of no SG. - */ - tx_packets = (entry + 1) - first_tx; - tx_q->tx_count_frames += tx_packets; - - if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) - set_ic = true; - else if (!priv->tx_coal_frames[queue]) - set_ic = false; - else if (tx_packets > priv->tx_coal_frames[queue]) - set_ic = true; - else if ((tx_q->tx_count_frames % - priv->tx_coal_frames[queue]) < tx_packets) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - if (likely(priv->extend_desc)) - desc = &tx_q->dma_etx[entry].basic; - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[entry].basic; - else - desc = &tx_q->dma_tx[entry]; - - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, desc); - priv->xstats.tx_set_ic_bit++; - } - - /* We've used all descriptors we need for this skb, however, - * advance cur_tx so that it references a fresh descriptor. - * ndo_start_xmit will fill this descriptor the next time it's - * called and stmmac_tx_clean may clean up to this descriptor. - */ - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - tx_q->cur_tx = entry; - - if (netif_msg_pktdata(priv)) { - netdev_dbg(priv->dev, - "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", - __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, - entry, first, nfrags); - - netdev_dbg(priv->dev, ">>> frame to be transmitted: "); - print_pkt(skb->data, skb->len); - } - - if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { - netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", - __func__); - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); - } - - dev->stats.tx_bytes += skb->len; - - if (priv->sarc_type) - stmmac_set_desc_sarc(priv, first, priv->sarc_type); - - skb_tx_timestamp(skb); - - /* Ready to fill the first descriptor and set the OWN bit w/o any - * problems because all the descriptors are actually ready to be - * passed to the DMA engine. - */ - if (likely(!is_jumbo)) { - bool last_segment = (nfrags == 0); - - des = dma_map_single(priv->device, skb->data, - nopaged_len, DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; - - tx_q->tx_skbuff_dma[first_entry].buf = des; - tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; - tx_q->tx_skbuff_dma[first_entry].map_as_page = false; - - stmmac_set_desc_addr(priv, first, des); - - tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; - tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; - - if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && - priv->hwts_tx_en)) { - /* declare that device is doing timestamping */ - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - stmmac_enable_tx_timestamp(priv, first); - } - - /* Prepare the first descriptor setting the OWN bit too */ - stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, - csum_insertion, priv->mode, 0, last_segment, - skb->len); - } - - if (tx_q->tbs & STMMAC_TBS_EN) { - struct timespec64 ts = ns_to_timespec64(skb->tstamp); - - tbs_desc = &tx_q->dma_entx[first_entry]; - stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); - } - - stmmac_set_tx_owner(priv, first); - - netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); - - stmmac_enable_dma_transmission(priv, priv->ioaddr); - - stmmac_flush_tx_descriptors(priv, queue); - stmmac_tx_timer_arm(priv, queue); - - return NETDEV_TX_OK; - -dma_map_err: - netdev_err(priv->dev, "Tx DMA map failed\n"); - dev_kfree_skb(skb); - priv->dev->stats.tx_dropped++; - return NETDEV_TX_OK; -} - -static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) -{ - struct vlan_ethhdr *veth; - __be16 vlan_proto; - u16 vlanid; - - veth = (struct vlan_ethhdr *)skb->data; - vlan_proto = veth->h_vlan_proto; - - if ((vlan_proto == htons(ETH_P_8021Q) && - dev->features & NETIF_F_HW_VLAN_CTAG_RX) || - (vlan_proto == htons(ETH_P_8021AD) && - dev->features & NETIF_F_HW_VLAN_STAG_RX)) { - /* pop the vlan tag */ - vlanid = ntohs(veth->h_vlan_TCI); - memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); - skb_pull(skb, VLAN_HLEN); - __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); - } -} - -/** - * stmmac_rx_refill - refill used skb preallocated buffers - * @priv: driver private structure - * @queue: RX queue index - * Description : this is to reallocate the skb for the reception process - * that is based on zero-copy. - */ -static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int dirty = stmmac_rx_dirty(priv, queue); - unsigned int entry = rx_q->dirty_rx; - gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); - - if (priv->dma_cap.addr64 <= 32) - gfp |= GFP_DMA32; - - while (dirty-- > 0) { - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; - struct dma_desc *p; - bool use_rx_wd; - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + entry); - else - p = rx_q->dma_rx + entry; - - if (!buf->page) { - buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); - if (!buf->page) - break; - } - - if (priv->sph && !buf->sec_page) { - buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); - if (!buf->sec_page) - break; - - buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); - } - - buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; - - stmmac_set_desc_addr(priv, p, buf->addr); - if (priv->sph) - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); - else - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); - stmmac_refill_desc3(priv, rx_q, p); - - rx_q->rx_count_frames++; - rx_q->rx_count_frames += priv->rx_coal_frames[queue]; - if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) - rx_q->rx_count_frames = 0; - - use_rx_wd = !priv->rx_coal_frames[queue]; - use_rx_wd |= rx_q->rx_count_frames > 0; - if (!priv->use_riwt) - use_rx_wd = false; - - dma_wmb(); - stmmac_set_rx_owner(priv, p, use_rx_wd); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); - } - rx_q->dirty_rx = entry; - rx_q->rx_tail_addr = rx_q->dma_rx_phy + - (rx_q->dirty_rx * sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); -} - -static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, - struct dma_desc *p, - int status, unsigned int len) -{ - unsigned int plen = 0, hlen = 0; - int coe = priv->hw->rx_csum; - - /* Not first descriptor, buffer is always zero */ - if (priv->sph && len) - return 0; - - /* First descriptor, get split header length */ - stmmac_get_rx_header_len(priv, p, &hlen); - if (priv->sph && hlen) { - priv->xstats.rx_split_hdr_pkt_n++; - return hlen; - } - - /* First descriptor, not last descriptor and not split header */ - if (status & rx_not_ls) - return priv->dma_buf_sz; - - plen = stmmac_get_rx_frame_len(priv, p, coe); - - /* First descriptor and last descriptor and not split header */ - return min_t(unsigned int, priv->dma_buf_sz, plen); -} - -static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, - struct dma_desc *p, - int status, unsigned int len) -{ - int coe = priv->hw->rx_csum; - unsigned int plen = 0; - - /* Not split header, buffer is not available */ - if (!priv->sph) - return 0; - - /* Not last descriptor */ - if (status & rx_not_ls) - return priv->dma_buf_sz; - - plen = stmmac_get_rx_frame_len(priv, p, coe); - - /* Last descriptor */ - return plen - len; -} - -static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, - struct xdp_frame *xdpf, bool dma_map) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - unsigned int entry = tx_q->cur_tx; - struct dma_desc *tx_desc; - dma_addr_t dma_addr; - bool set_ic; - - if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) - return STMMAC_XDP_CONSUMED; - - if (likely(priv->extend_desc)) - tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - tx_desc = &tx_q->dma_entx[entry].basic; - else - tx_desc = tx_q->dma_tx + entry; - - if (dma_map) { - dma_addr = dma_map_single(priv->device, xdpf->data, - xdpf->len, DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, dma_addr)) - return STMMAC_XDP_CONSUMED; - - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; - } else { - struct page *page = virt_to_page(xdpf->data); - - dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + - xdpf->headroom; - dma_sync_single_for_device(priv->device, dma_addr, - xdpf->len, DMA_BIDIRECTIONAL); - - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; - } - - tx_q->tx_skbuff_dma[entry].buf = dma_addr; - tx_q->tx_skbuff_dma[entry].map_as_page = false; - tx_q->tx_skbuff_dma[entry].len = xdpf->len; - tx_q->tx_skbuff_dma[entry].last_segment = true; - tx_q->tx_skbuff_dma[entry].is_jumbo = false; - - tx_q->xdpf[entry] = xdpf; - - stmmac_set_desc_addr(priv, tx_desc, dma_addr); - - stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, - true, priv->mode, true, true, - xdpf->len); - - tx_q->tx_count_frames++; - - if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, tx_desc); - priv->xstats.tx_set_ic_bit++; - } - - stmmac_enable_dma_transmission(priv, priv->ioaddr); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - tx_q->cur_tx = entry; - - return STMMAC_XDP_TX; -} - -static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, - int cpu) -{ - int index = cpu; - - if (unlikely(index < 0)) - index = 0; - - while (index >= priv->plat->tx_queues_to_use) - index -= priv->plat->tx_queues_to_use; - - return index; -} - -static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, - struct xdp_buff *xdp) -{ - struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); - int cpu = smp_processor_id(); - struct netdev_queue *nq; - int queue; - int res; - - if (unlikely(!xdpf)) - return STMMAC_XDP_CONSUMED; - - queue = stmmac_xdp_get_tx_queue(priv, cpu); - nq = netdev_get_tx_queue(priv->dev, queue); - - __netif_tx_lock(nq, cpu); - /* Avoids TX time-out as we are sharing with slow path */ - txq_trans_cond_update(nq); - - res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); - if (res == STMMAC_XDP_TX) - stmmac_flush_tx_descriptors(priv, queue); - - __netif_tx_unlock(nq); - - return res; -} - -static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, - struct bpf_prog *prog, - struct xdp_buff *xdp) -{ - u32 act; - int res; - - act = bpf_prog_run_xdp(prog, xdp); - switch (act) { - case XDP_PASS: - res = STMMAC_XDP_PASS; - break; - case XDP_TX: - res = stmmac_xdp_xmit_back(priv, xdp); - break; - case XDP_REDIRECT: - if (xdp_do_redirect(priv->dev, xdp, prog) < 0) - res = STMMAC_XDP_CONSUMED; - else - res = STMMAC_XDP_REDIRECT; - break; - default: - bpf_warn_invalid_xdp_action(priv->dev, prog, act); - fallthrough; - case XDP_ABORTED: - trace_xdp_exception(priv->dev, prog, act); - fallthrough; - case XDP_DROP: - res = STMMAC_XDP_CONSUMED; - break; - } - - return res; -} - -static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, - struct xdp_buff *xdp) -{ - struct bpf_prog *prog; - int res; - - prog = READ_ONCE(priv->xdp_prog); - if (!prog) { - res = STMMAC_XDP_PASS; - goto out; - } - - res = __stmmac_xdp_run_prog(priv, prog, xdp); -out: - return ERR_PTR(-res); -} - -static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, - int xdp_status) -{ - int cpu = smp_processor_id(); - int queue; - - queue = stmmac_xdp_get_tx_queue(priv, cpu); - - if (xdp_status & STMMAC_XDP_TX) - stmmac_tx_timer_arm(priv, queue); - - if (xdp_status & STMMAC_XDP_REDIRECT) - xdp_do_flush(); -} - -static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, - struct xdp_buff *xdp) -{ - unsigned int metasize = xdp->data - xdp->data_meta; - unsigned int datasize = xdp->data_end - xdp->data; - struct sk_buff *skb; - - skb = __napi_alloc_skb(&ch->rxtx_napi, - xdp->data_end - xdp->data_hard_start, - GFP_ATOMIC | __GFP_NOWARN); - if (unlikely(!skb)) - return NULL; - - skb_reserve(skb, xdp->data - xdp->data_hard_start); - memcpy(__skb_put(skb, datasize), xdp->data, datasize); - if (metasize) - skb_metadata_set(skb, metasize); - - return skb; -} - -static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, - struct dma_desc *p, struct dma_desc *np, - struct xdp_buff *xdp) -{ - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned int len = xdp->data_end - xdp->data; - enum pkt_hash_types hash_type; - int coe = priv->hw->rx_csum; - struct sk_buff *skb; - u32 hash; - - skb = stmmac_construct_skb_zc(ch, xdp); - if (!skb) { - priv->dev->stats.rx_dropped++; - return; - } - - stmmac_get_rx_hwtstamp(priv, p, np, skb); - stmmac_rx_vlan(priv->dev, skb); - skb->protocol = eth_type_trans(skb, priv->dev); - - if (unlikely(!coe)) - skb_checksum_none_assert(skb); - else - skb->ip_summed = CHECKSUM_UNNECESSARY; - - if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) - skb_set_hash(skb, hash, hash_type); - - skb_record_rx_queue(skb, queue); - napi_gro_receive(&ch->rxtx_napi, skb); - - priv->dev->stats.rx_packets++; - priv->dev->stats.rx_bytes += len; -} - -static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - unsigned int entry = rx_q->dirty_rx; - struct dma_desc *rx_desc = NULL; - bool ret = true; - - budget = min(budget, stmmac_rx_dirty(priv, queue)); - - while (budget-- > 0 && entry != rx_q->cur_rx) { - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; - dma_addr_t dma_addr; - bool use_rx_wd; - - if (!buf->xdp) { - buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); - if (!buf->xdp) { - ret = false; - break; - } - } - - if (priv->extend_desc) - rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); - else - rx_desc = rx_q->dma_rx + entry; - - dma_addr = xsk_buff_xdp_get_dma(buf->xdp); - stmmac_set_desc_addr(priv, rx_desc, dma_addr); - stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); - stmmac_refill_desc3(priv, rx_q, rx_desc); - - rx_q->rx_count_frames++; - rx_q->rx_count_frames += priv->rx_coal_frames[queue]; - if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) - rx_q->rx_count_frames = 0; - - use_rx_wd = !priv->rx_coal_frames[queue]; - use_rx_wd |= rx_q->rx_count_frames > 0; - if (!priv->use_riwt) - use_rx_wd = false; - - dma_wmb(); - stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); - } - - if (rx_desc) { - rx_q->dirty_rx = entry; - rx_q->rx_tail_addr = rx_q->dma_rx_phy + - (rx_q->dirty_rx * sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); - } - - return ret; -} - -static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - unsigned int count = 0, error = 0, len = 0; - int dirty = stmmac_rx_dirty(priv, queue); - unsigned int next_entry = rx_q->cur_rx; - unsigned int desc_size; - struct bpf_prog *prog; - bool failure = false; - int xdp_status = 0; - int status = 0; - - if (netif_msg_rx_status(priv)) { - void *rx_head; - - netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); - if (priv->extend_desc) { - rx_head = (void *)rx_q->dma_erx; - desc_size = sizeof(struct dma_extended_desc); - } else { - rx_head = (void *)rx_q->dma_rx; - desc_size = sizeof(struct dma_desc); - } - - stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, - rx_q->dma_rx_phy, desc_size); - } - while (count < limit) { - struct stmmac_rx_buffer *buf; - unsigned int buf1_len = 0; - struct dma_desc *np, *p; - int entry; - int res; - - if (!count && rx_q->state_saved) { - error = rx_q->state.error; - len = rx_q->state.len; - } else { - rx_q->state_saved = false; - error = 0; - len = 0; - } - - if (count >= limit) - break; - -read_again: - buf1_len = 0; - entry = next_entry; - buf = &rx_q->buf_pool[entry]; - - if (dirty >= STMMAC_RX_FILL_BATCH) { - failure = failure || - !stmmac_rx_refill_zc(priv, queue, dirty); - dirty = 0; - } - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + entry); - else - p = rx_q->dma_rx + entry; - - /* read the status of the incoming frame */ - status = stmmac_rx_status(priv, &priv->dev->stats, - &priv->xstats, p); - /* check if managed by the DMA otherwise go ahead */ - if (unlikely(status & dma_own)) - break; - - /* Prefetch the next RX descriptor */ - rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, - priv->dma_rx_size); - next_entry = rx_q->cur_rx; - - if (priv->extend_desc) - np = (struct dma_desc *)(rx_q->dma_erx + next_entry); - else - np = rx_q->dma_rx + next_entry; - - prefetch(np); - - /* Ensure a valid XSK buffer before proceed */ - if (!buf->xdp) - break; - - if (priv->extend_desc) - stmmac_rx_extended_status(priv, &priv->dev->stats, - &priv->xstats, - rx_q->dma_erx + entry); - if (unlikely(status == discard_frame)) { - xsk_buff_free(buf->xdp); - buf->xdp = NULL; - dirty++; - error = 1; - if (!priv->hwts_rx_en) - priv->dev->stats.rx_errors++; - } - - if (unlikely(error && (status & rx_not_ls))) - goto read_again; - if (unlikely(error)) { - count++; - continue; - } - - /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ - if (likely(status & rx_not_ls)) { - xsk_buff_free(buf->xdp); - buf->xdp = NULL; - dirty++; - count++; - goto read_again; - } - - /* XDP ZC Frame only support primary buffers for now */ - buf1_len = stmmac_rx_buf1_len(priv, p, status, len); - len += buf1_len; - - /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 - * Type frames (LLC/LLC-SNAP) - * - * llc_snap is never checked in GMAC >= 4, so this ACS - * feature is always disabled and packets need to be - * stripped manually. - */ - if (likely(!(status & rx_not_ls)) && - (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || - unlikely(status != llc_snap))) { - buf1_len -= ETH_FCS_LEN; - len -= ETH_FCS_LEN; - } - - /* RX buffer is good and fit into a XSK pool buffer */ - buf->xdp->data_end = buf->xdp->data + buf1_len; - xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); - - prog = READ_ONCE(priv->xdp_prog); - res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); - - switch (res) { - case STMMAC_XDP_PASS: - stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); - xsk_buff_free(buf->xdp); - break; - case STMMAC_XDP_CONSUMED: - xsk_buff_free(buf->xdp); - priv->dev->stats.rx_dropped++; - break; - case STMMAC_XDP_TX: - case STMMAC_XDP_REDIRECT: - xdp_status |= res; - break; - } - - buf->xdp = NULL; - dirty++; - count++; - } - - if (status & rx_not_ls) { - rx_q->state_saved = true; - rx_q->state.error = error; - rx_q->state.len = len; - } - - stmmac_finalize_xdp_rx(priv, xdp_status); - - priv->xstats.rx_pkt_n += count; - priv->xstats.rxq_stats[queue].rx_pkt_n += count; - - if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { - if (failure || stmmac_rx_dirty(priv, queue) > 0) - xsk_set_rx_need_wakeup(rx_q->xsk_pool); - else - xsk_clear_rx_need_wakeup(rx_q->xsk_pool); - - return (int)count; - } - - return failure ? limit : (int)count; -} - -/** - * stmmac_rx - manage the receive process - * @priv: driver private structure - * @limit: napi bugget - * @queue: RX queue index. - * Description : this the function called by the napi poll method. - * It gets all the frames inside the ring. - */ -static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned int count = 0, error = 0, len = 0; - int status = 0, coe = priv->hw->rx_csum; - unsigned int next_entry = rx_q->cur_rx; - enum dma_data_direction dma_dir; - unsigned int desc_size; - struct sk_buff *skb = NULL; - struct xdp_buff xdp; - int xdp_status = 0; - int buf_sz; - - dma_dir = page_pool_get_dma_dir(rx_q->page_pool); - buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; - - if (netif_msg_rx_status(priv)) { - void *rx_head; - - netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); - if (priv->extend_desc) { - rx_head = (void *)rx_q->dma_erx; - desc_size = sizeof(struct dma_extended_desc); - } else { - rx_head = (void *)rx_q->dma_rx; - desc_size = sizeof(struct dma_desc); - } - - stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, - rx_q->dma_rx_phy, desc_size); - } - while (count < limit) { - unsigned int buf1_len = 0, buf2_len = 0; - enum pkt_hash_types hash_type; - struct stmmac_rx_buffer *buf; - struct dma_desc *np, *p; - int entry; - u32 hash; - - if (!count && rx_q->state_saved) { - skb = rx_q->state.skb; - error = rx_q->state.error; - len = rx_q->state.len; - } else { - rx_q->state_saved = false; - skb = NULL; - error = 0; - len = 0; - } - - if (count >= limit) - break; - -read_again: - buf1_len = 0; - buf2_len = 0; - entry = next_entry; - buf = &rx_q->buf_pool[entry]; - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + entry); - else - p = rx_q->dma_rx + entry; - - /* read the status of the incoming frame */ - status = stmmac_rx_status(priv, &priv->dev->stats, - &priv->xstats, p); - /* check if managed by the DMA otherwise go ahead */ - if (unlikely(status & dma_own)) - break; - - rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, - priv->dma_rx_size); - next_entry = rx_q->cur_rx; - - if (priv->extend_desc) - np = (struct dma_desc *)(rx_q->dma_erx + next_entry); - else - np = rx_q->dma_rx + next_entry; - - prefetch(np); - - if (priv->extend_desc) - stmmac_rx_extended_status(priv, &priv->dev->stats, - &priv->xstats, rx_q->dma_erx + entry); - if (unlikely(status == discard_frame)) { - page_pool_recycle_direct(rx_q->page_pool, buf->page); - buf->page = NULL; - error = 1; - if (!priv->hwts_rx_en) - priv->dev->stats.rx_errors++; - } - - if (unlikely(error && (status & rx_not_ls))) - goto read_again; - if (unlikely(error)) { - dev_kfree_skb(skb); - skb = NULL; - count++; - continue; - } - - /* Buffer is good. Go on. */ - - prefetch(page_address(buf->page) + buf->page_offset); - if (buf->sec_page) - prefetch(page_address(buf->sec_page)); - - buf1_len = stmmac_rx_buf1_len(priv, p, status, len); - len += buf1_len; - buf2_len = stmmac_rx_buf2_len(priv, p, status, len); - len += buf2_len; - - /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 - * Type frames (LLC/LLC-SNAP) - * - * llc_snap is never checked in GMAC >= 4, so this ACS - * feature is always disabled and packets need to be - * stripped manually. - */ - if (likely(!(status & rx_not_ls)) && - (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || - unlikely(status != llc_snap))) { - if (buf2_len) { - buf2_len -= ETH_FCS_LEN; - len -= ETH_FCS_LEN; - } else if (buf1_len) { - buf1_len -= ETH_FCS_LEN; - len -= ETH_FCS_LEN; - } - } - - if (!skb) { - unsigned int pre_len, sync_len; - - dma_sync_single_for_cpu(priv->device, buf->addr, - buf1_len, dma_dir); - - xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); - xdp_prepare_buff(&xdp, page_address(buf->page), - buf->page_offset, buf1_len, false); - - pre_len = xdp.data_end - xdp.data_hard_start - - buf->page_offset; - skb = stmmac_xdp_run_prog(priv, &xdp); - /* Due xdp_adjust_tail: DMA sync for_device - * cover max len CPU touch - */ - sync_len = xdp.data_end - xdp.data_hard_start - - buf->page_offset; - sync_len = max(sync_len, pre_len); - - /* For Not XDP_PASS verdict */ - if (IS_ERR(skb)) { - unsigned int xdp_res = -PTR_ERR(skb); - - if (xdp_res & STMMAC_XDP_CONSUMED) { - page_pool_put_page(rx_q->page_pool, - virt_to_head_page(xdp.data), - sync_len, true); - buf->page = NULL; - priv->dev->stats.rx_dropped++; - - /* Clear skb as it was set as - * status by XDP program. - */ - skb = NULL; - - if (unlikely((status & rx_not_ls))) - goto read_again; - - count++; - continue; - } else if (xdp_res & (STMMAC_XDP_TX | - STMMAC_XDP_REDIRECT)) { - xdp_status |= xdp_res; - buf->page = NULL; - skb = NULL; - count++; - continue; - } - } - } - - if (!skb) { - /* XDP program may expand or reduce tail */ - buf1_len = xdp.data_end - xdp.data; - - skb = napi_alloc_skb(&ch->rx_napi, buf1_len); - if (!skb) { - priv->dev->stats.rx_dropped++; - count++; - goto drain_data; - } - - /* XDP program may adjust header */ - skb_copy_to_linear_data(skb, xdp.data, buf1_len); - skb_put(skb, buf1_len); - - /* Data payload copied into SKB, page ready for recycle */ - page_pool_recycle_direct(rx_q->page_pool, buf->page); - buf->page = NULL; - } else if (buf1_len) { - dma_sync_single_for_cpu(priv->device, buf->addr, - buf1_len, dma_dir); - skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, - buf->page, buf->page_offset, buf1_len, - priv->dma_buf_sz); - - /* Data payload appended into SKB */ - page_pool_release_page(rx_q->page_pool, buf->page); - buf->page = NULL; - } - - if (buf2_len) { - dma_sync_single_for_cpu(priv->device, buf->sec_addr, - buf2_len, dma_dir); - skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, - buf->sec_page, 0, buf2_len, - priv->dma_buf_sz); - - /* Data payload appended into SKB */ - page_pool_release_page(rx_q->page_pool, buf->sec_page); - buf->sec_page = NULL; - } - -drain_data: - if (likely(status & rx_not_ls)) - goto read_again; - if (!skb) - continue; - - /* Got entire packet into SKB. Finish it. */ - - stmmac_get_rx_hwtstamp(priv, p, np, skb); - stmmac_rx_vlan(priv->dev, skb); - skb->protocol = eth_type_trans(skb, priv->dev); - - if (unlikely(!coe)) - skb_checksum_none_assert(skb); - else - skb->ip_summed = CHECKSUM_UNNECESSARY; - - if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) - skb_set_hash(skb, hash, hash_type); - - skb_record_rx_queue(skb, queue); - napi_gro_receive(&ch->rx_napi, skb); - skb = NULL; - - priv->dev->stats.rx_packets++; - priv->dev->stats.rx_bytes += len; - count++; - } - - if (status & rx_not_ls || skb) { - rx_q->state_saved = true; - rx_q->state.skb = skb; - rx_q->state.error = error; - rx_q->state.len = len; - } - - stmmac_finalize_xdp_rx(priv, xdp_status); - - stmmac_rx_refill(priv, queue); - - priv->xstats.rx_pkt_n += count; - priv->xstats.rxq_stats[queue].rx_pkt_n += count; - - return count; -} - -static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) -{ - struct stmmac_channel *ch = - container_of(napi, struct stmmac_channel, rx_napi); - struct stmmac_priv *priv = ch->priv_data; - u32 chan = ch->index; - int work_done; - - priv->xstats.napi_poll++; - - work_done = stmmac_rx(priv, budget, chan); - if (work_done < budget && napi_complete_done(napi, work_done)) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); - } - - return work_done; -} - -static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) -{ - struct stmmac_channel *ch = - container_of(napi, struct stmmac_channel, tx_napi); - struct stmmac_priv *priv = ch->priv_data; - u32 chan = ch->index; - int work_done; - - priv->xstats.napi_poll++; - - work_done = stmmac_tx_clean(priv, budget, chan); - work_done = min(work_done, budget); - - if (work_done < budget && napi_complete_done(napi, work_done)) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - } - - return work_done; -} - -static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) -{ - struct stmmac_channel *ch = - container_of(napi, struct stmmac_channel, rxtx_napi); - struct stmmac_priv *priv = ch->priv_data; - int rx_done, tx_done, rxtx_done; - u32 chan = ch->index; - - priv->xstats.napi_poll++; - - tx_done = stmmac_tx_clean(priv, budget, chan); - tx_done = min(tx_done, budget); - - rx_done = stmmac_rx_zc(priv, budget, chan); - - rxtx_done = max(tx_done, rx_done); - - /* If either TX or RX work is not complete, return budget - * and keep pooling - */ - if (rxtx_done >= budget) - return budget; - - /* all work done, exit the polling mode */ - if (napi_complete_done(napi, rxtx_done)) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - /* Both RX and TX work done are compelte, - * so enable both RX & TX IRQs. - */ - stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); - spin_unlock_irqrestore(&ch->lock, flags); - } - - return min(rxtx_done, budget - 1); -} - -/** - * stmmac_tx_timeout - * @dev : Pointer to net device structure - * @txqueue: the index of the hanging transmit queue - * Description: this function is called when a packet transmission fails to - * complete within a reasonable time. The driver will mark the error in the - * netdev structure and arrange for the device to be reset to a sane state - * in order to transmit a new packet. - */ -static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - stmmac_global_err(priv); -} - -/** - * stmmac_set_rx_mode - entry point for multicast addressing - * @dev : pointer to the device structure - * Description: - * This function is a driver entry point which gets called by the kernel - * whenever multicast addresses must be enabled/disabled. - * Return value: - * void. - */ -static void stmmac_set_rx_mode(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - stmmac_set_filter(priv, priv->hw, dev); -} - -/** - * stmmac_change_mtu - entry point to change MTU size for the device. - * @dev : device pointer. - * @new_mtu : the new MTU size for the device. - * Description: the Maximum Transfer Unit (MTU) is used by the network layer - * to drive packet transmission. Ethernet has an MTU of 1500 octets - * (ETH_DATA_LEN). This value can be changed with ifconfig. - * Return value: - * 0 on success and an appropriate (-)ve integer as defined in errno.h - * file on failure. - */ -static int stmmac_change_mtu(struct net_device *dev, int new_mtu) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int txfifosz = priv->plat->tx_fifo_size; - const int mtu = new_mtu; - - if (txfifosz == 0) - txfifosz = priv->dma_cap.tx_fifo_size; - - txfifosz /= priv->plat->tx_queues_to_use; - - if (netif_running(dev)) { - netdev_err(priv->dev, "must be stopped to change its MTU\n"); - return -EBUSY; - } - - if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { - netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); - return -EINVAL; - } - - new_mtu = STMMAC_ALIGN(new_mtu); - - /* If condition true, FIFO is too small or MTU too large */ - if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) - return -EINVAL; - - dev->mtu = mtu; - - netdev_update_features(dev); - - return 0; -} - -static netdev_features_t stmmac_fix_features(struct net_device *dev, - netdev_features_t features) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) - features &= ~NETIF_F_RXCSUM; - - if (!priv->plat->tx_coe) - features &= ~NETIF_F_CSUM_MASK; - - /* Some GMAC devices have a bugged Jumbo frame support that - * needs to have the Tx COE disabled for oversized frames - * (due to limited buffer sizes). In this case we disable - * the TX csum insertion in the TDES and not use SF. - */ - if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) - features &= ~NETIF_F_CSUM_MASK; - - /* Disable tso if asked by ethtool */ - if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { - if (features & NETIF_F_TSO) - priv->tso = true; - else - priv->tso = false; - } - - return features; -} - -static int stmmac_set_features(struct net_device *netdev, - netdev_features_t features) -{ - struct stmmac_priv *priv = netdev_priv(netdev); - - /* Keep the COE Type in case of csum is supporting */ - if (features & NETIF_F_RXCSUM) - priv->hw->rx_csum = priv->plat->rx_coe; - else - priv->hw->rx_csum = 0; - /* No check needed because rx_coe has been set before and it will be - * fixed in case of issue. - */ - stmmac_rx_ipc(priv, priv->hw); - - if (priv->sph_cap) { - bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; - u32 chan; - - for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) - stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); - } - - return 0; -} - -static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) -{ - struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; - enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; - enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; - bool *hs_enable = &fpe_cfg->hs_enable; - - if (status == FPE_EVENT_UNKNOWN || !*hs_enable) - return; - - /* If LP has sent verify mPacket, LP is FPE capable */ - if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { - if (*lp_state < FPE_STATE_CAPABLE) - *lp_state = FPE_STATE_CAPABLE; - - /* If user has requested FPE enable, quickly response */ - if (*hs_enable) - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - MPACKET_RESPONSE); - } - - /* If Local has sent verify mPacket, Local is FPE capable */ - if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { - if (*lo_state < FPE_STATE_CAPABLE) - *lo_state = FPE_STATE_CAPABLE; - } - - /* If LP has sent response mPacket, LP is entering FPE ON */ - if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) - *lp_state = FPE_STATE_ENTERING_ON; - - /* If Local has sent response mPacket, Local is entering FPE ON */ - if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) - *lo_state = FPE_STATE_ENTERING_ON; - - if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && - !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && - priv->fpe_wq) { - queue_work(priv->fpe_wq, &priv->fpe_task); - } -} - -static void stmmac_common_interrupt(struct stmmac_priv *priv) -{ - u32 rx_cnt = priv->plat->rx_queues_to_use; - u32 tx_cnt = priv->plat->tx_queues_to_use; - u32 queues_count; - u32 queue; - bool xmac; - - xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; - queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; - - if (priv->irq_wake) - pm_wakeup_event(priv->device, 0); - - if (priv->dma_cap.estsel) - stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, - &priv->xstats, tx_cnt); - - if (priv->dma_cap.fpesel) { - int status = stmmac_fpe_irq_status(priv, priv->ioaddr, - priv->dev); - - stmmac_fpe_event_status(priv, status); - } - - /* To handle GMAC own interrupts */ - if ((priv->plat->has_gmac) || xmac) { - int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); - - if (unlikely(status)) { - /* For LPI we need to save the tx status */ - if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) - priv->tx_path_in_lpi_mode = true; - if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) - priv->tx_path_in_lpi_mode = false; - } - - for (queue = 0; queue < queues_count; queue++) { - status = stmmac_host_mtl_irq_status(priv, priv->hw, - queue); - } - - /* PCS link status */ - if (priv->hw->pcs) { - if (priv->xstats.pcs_link) - netif_carrier_on(priv->dev); - else - netif_carrier_off(priv->dev); - } - - stmmac_timestamp_interrupt(priv, priv); - } -} - -/** - * stmmac_interrupt - main ISR - * @irq: interrupt number. - * @dev_id: to pass the net device pointer. - * Description: this is the main driver interrupt service routine. - * It can call: - * o DMA service routine (to manage incoming frame reception and transmission - * status) - * o Core interrupts to manage: remote wake-up, management counter, LPI - * interrupts. - */ -static irqreturn_t stmmac_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *)dev_id; - struct stmmac_priv *priv = netdev_priv(dev); - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - /* Check if a fatal error happened */ - if (stmmac_safety_feat_interrupt(priv)) - return IRQ_HANDLED; - - /* To handle Common interrupts */ - stmmac_common_interrupt(priv); - - /* To handle DMA interrupts */ - stmmac_dma_interrupt(priv); - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *)dev_id; - struct stmmac_priv *priv = netdev_priv(dev); - - if (unlikely(!dev)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - /* To handle Common interrupts */ - stmmac_common_interrupt(priv); - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *)dev_id; - struct stmmac_priv *priv = netdev_priv(dev); - - if (unlikely(!dev)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - /* Check if a fatal error happened */ - stmmac_safety_feat_interrupt(priv); - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) -{ - struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; - int chan = tx_q->queue_index; - struct stmmac_priv *priv; - int status; - - priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]); - - if (unlikely(!data)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - status = stmmac_napi_check(priv, chan, DMA_DIR_TX); - - if (unlikely(status & tx_hard_error_bump_tc)) { - /* Try to bump up the dma threshold on this failure */ - stmmac_bump_dma_threshold(priv, chan); - } else if (unlikely(status == tx_hard_error)) { - stmmac_tx_err(priv, chan); - } - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) -{ - struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; - int chan = rx_q->queue_index; - struct stmmac_priv *priv; - - priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]); - - if (unlikely(!data)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - stmmac_napi_check(priv, chan, DMA_DIR_RX); - - return IRQ_HANDLED; -} - -#ifdef CONFIG_NET_POLL_CONTROLLER -/* Polling receive - used by NETCONSOLE and other diagnostic tools - * to allow network I/O with interrupts disabled. - */ -static void stmmac_poll_controller(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int i; - - /* If adapter is down, do nothing */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return; - - if (priv->plat->multi_msi_en) { - for (i = 0; i < priv->plat->rx_queues_to_use; i++) - stmmac_msi_intr_rx(0, &priv->rx_queue[i]); - - for (i = 0; i < priv->plat->tx_queues_to_use; i++) - stmmac_msi_intr_tx(0, &priv->tx_queue[i]); - } else { - disable_irq(dev->irq); - stmmac_interrupt(dev->irq, dev); - enable_irq(dev->irq); - } -} -#endif - -/** - * stmmac_ioctl - Entry point for the Ioctl - * @dev: Device pointer. - * @rq: An IOCTL specefic structure, that can contain a pointer to - * a proprietary structure used to pass information to the driver. - * @cmd: IOCTL command - * Description: - * Currently it supports the phy_mii_ioctl(...) and HW time stamping. - */ -static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -{ - struct stmmac_priv *priv = netdev_priv (dev); - int ret = -EOPNOTSUPP; - - if (!netif_running(dev)) - return -EINVAL; - - switch (cmd) { - case SIOCGMIIPHY: - case SIOCGMIIREG: - case SIOCSMIIREG: - ret = phylink_mii_ioctl(priv->phylink, rq, cmd); - break; - case SIOCSHWTSTAMP: - ret = stmmac_hwtstamp_set(dev, rq); - break; - case SIOCGHWTSTAMP: - ret = stmmac_hwtstamp_get(dev, rq); - break; - default: - break; - } - - return ret; -} - -static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, - void *cb_priv) -{ - struct stmmac_priv *priv = cb_priv; - int ret = -EOPNOTSUPP; - - if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) - return ret; - - __stmmac_disable_all_queues(priv); - - switch (type) { - case TC_SETUP_CLSU32: - ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); - break; - case TC_SETUP_CLSFLOWER: - ret = stmmac_tc_setup_cls(priv, priv, type_data); - break; - default: - break; - } - - stmmac_enable_all_queues(priv); - return ret; -} - -static LIST_HEAD(stmmac_block_cb_list); - -static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, - void *type_data) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - - switch (type) { - case TC_SETUP_BLOCK: - return flow_block_cb_setup_simple(type_data, - &stmmac_block_cb_list, - stmmac_setup_tc_block_cb, - priv, priv, true); - case TC_SETUP_QDISC_CBS: - return stmmac_tc_setup_cbs(priv, priv, type_data); - case TC_SETUP_QDISC_TAPRIO: - return stmmac_tc_setup_taprio(priv, priv, type_data); - case TC_SETUP_QDISC_ETF: - return stmmac_tc_setup_etf(priv, priv, type_data); - default: - return -EOPNOTSUPP; - } -} - -static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, - struct net_device *sb_dev) -{ - int gso = skb_shinfo(skb)->gso_type; - - if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { - /* - * There is no way to determine the number of TSO/USO - * capable Queues. Let's use always the Queue 0 - * because if TSO/USO is supported then at least this - * one will be capable. - */ - return 0; - } - - return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; -} - -static int stmmac_set_mac_address(struct net_device *ndev, void *addr) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - int ret = 0; - - ret = pm_runtime_get_sync(priv->device); - if (ret < 0) { - pm_runtime_put_noidle(priv->device); - return ret; - } - - ret = eth_mac_addr(ndev, addr); - if (ret) - goto set_mac_error; - - stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); - -set_mac_error: - pm_runtime_put(priv->device); - - return ret; -} - -#ifdef CONFIG_DEBUG_FS -static struct dentry *stmmac_fs_dir; - -static void sysfs_display_ring(void *head, int size, int extend_desc, - struct seq_file *seq, dma_addr_t dma_phy_addr) -{ - int i; - struct dma_extended_desc *ep = (struct dma_extended_desc *)head; - struct dma_desc *p = (struct dma_desc *)head; - dma_addr_t dma_addr; - - for (i = 0; i < size; i++) { - if (extend_desc) { - dma_addr = dma_phy_addr + i * sizeof(*ep); - seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", - i, &dma_addr, - le32_to_cpu(ep->basic.des0), - le32_to_cpu(ep->basic.des1), - le32_to_cpu(ep->basic.des2), - le32_to_cpu(ep->basic.des3)); - ep++; - } else { - dma_addr = dma_phy_addr + i * sizeof(*p); - seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", - i, &dma_addr, - le32_to_cpu(p->des0), le32_to_cpu(p->des1), - le32_to_cpu(p->des2), le32_to_cpu(p->des3)); - p++; - } - seq_printf(seq, "\n"); - } -} - -static int stmmac_rings_status_show(struct seq_file *seq, void *v) -{ - struct net_device *dev = seq->private; - struct stmmac_priv *priv = netdev_priv(dev); - u32 rx_count = priv->plat->rx_queues_to_use; - u32 tx_count = priv->plat->tx_queues_to_use; - u32 queue; - - if ((dev->flags & IFF_UP) == 0) - return 0; - - for (queue = 0; queue < rx_count; queue++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - seq_printf(seq, "RX Queue %d:\n", queue); - - if (priv->extend_desc) { - seq_printf(seq, "Extended descriptor ring:\n"); - sysfs_display_ring((void *)rx_q->dma_erx, - priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy); - } else { - seq_printf(seq, "Descriptor ring:\n"); - sysfs_display_ring((void *)rx_q->dma_rx, - priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy); - } - } - - for (queue = 0; queue < tx_count; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - seq_printf(seq, "TX Queue %d:\n", queue); - - if (priv->extend_desc) { - seq_printf(seq, "Extended descriptor ring:\n"); - sysfs_display_ring((void *)tx_q->dma_etx, - priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy); - } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { - seq_printf(seq, "Descriptor ring:\n"); - sysfs_display_ring((void *)tx_q->dma_tx, - priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy); - } - } - - return 0; -} -DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); - -static int stmmac_dma_cap_show(struct seq_file *seq, void *v) -{ - struct net_device *dev = seq->private; - struct stmmac_priv *priv = netdev_priv(dev); - - if (!priv->hw_cap_support) { - seq_printf(seq, "DMA HW features not supported\n"); - return 0; - } - - seq_printf(seq, "==============================\n"); - seq_printf(seq, "\tDMA HW features\n"); - seq_printf(seq, "==============================\n"); - - seq_printf(seq, "\t10/100 Mbps: %s\n", - (priv->dma_cap.mbps_10_100) ? "Y" : "N"); - seq_printf(seq, "\t1000 Mbps: %s\n", - (priv->dma_cap.mbps_1000) ? "Y" : "N"); - seq_printf(seq, "\tHalf duplex: %s\n", - (priv->dma_cap.half_duplex) ? "Y" : "N"); - seq_printf(seq, "\tHash Filter: %s\n", - (priv->dma_cap.hash_filter) ? "Y" : "N"); - seq_printf(seq, "\tMultiple MAC address registers: %s\n", - (priv->dma_cap.multi_addr) ? "Y" : "N"); - seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", - (priv->dma_cap.pcs) ? "Y" : "N"); - seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", - (priv->dma_cap.sma_mdio) ? "Y" : "N"); - seq_printf(seq, "\tPMT Remote wake up: %s\n", - (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); - seq_printf(seq, "\tPMT Magic Frame: %s\n", - (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); - seq_printf(seq, "\tRMON module: %s\n", - (priv->dma_cap.rmon) ? "Y" : "N"); - seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", - (priv->dma_cap.time_stamp) ? "Y" : "N"); - seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", - (priv->dma_cap.atime_stamp) ? "Y" : "N"); - seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", - (priv->dma_cap.eee) ? "Y" : "N"); - seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); - seq_printf(seq, "\tChecksum Offload in TX: %s\n", - (priv->dma_cap.tx_coe) ? "Y" : "N"); - if (priv->synopsys_id >= DWMAC_CORE_4_00) { - seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", - (priv->dma_cap.rx_coe) ? "Y" : "N"); - } else { - seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", - (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); - seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", - (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); - } - seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", - (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); - seq_printf(seq, "\tNumber of Additional RX channel: %d\n", - priv->dma_cap.number_rx_channel); - seq_printf(seq, "\tNumber of Additional TX channel: %d\n", - priv->dma_cap.number_tx_channel); - seq_printf(seq, "\tNumber of Additional RX queues: %d\n", - priv->dma_cap.number_rx_queues); - seq_printf(seq, "\tNumber of Additional TX queues: %d\n", - priv->dma_cap.number_tx_queues); - seq_printf(seq, "\tEnhanced descriptors: %s\n", - (priv->dma_cap.enh_desc) ? "Y" : "N"); - seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); - seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); - seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); - seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); - seq_printf(seq, "\tNumber of PPS Outputs: %d\n", - priv->dma_cap.pps_out_num); - seq_printf(seq, "\tSafety Features: %s\n", - priv->dma_cap.asp ? "Y" : "N"); - seq_printf(seq, "\tFlexible RX Parser: %s\n", - priv->dma_cap.frpsel ? "Y" : "N"); - seq_printf(seq, "\tEnhanced Addressing: %d\n", - priv->dma_cap.addr64); - seq_printf(seq, "\tReceive Side Scaling: %s\n", - priv->dma_cap.rssen ? "Y" : "N"); - seq_printf(seq, "\tVLAN Hash Filtering: %s\n", - priv->dma_cap.vlhash ? "Y" : "N"); - seq_printf(seq, "\tSplit Header: %s\n", - priv->dma_cap.sphen ? "Y" : "N"); - seq_printf(seq, "\tVLAN TX Insertion: %s\n", - priv->dma_cap.vlins ? "Y" : "N"); - seq_printf(seq, "\tDouble VLAN: %s\n", - priv->dma_cap.dvlan ? "Y" : "N"); - seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", - priv->dma_cap.l3l4fnum); - seq_printf(seq, "\tARP Offloading: %s\n", - priv->dma_cap.arpoffsel ? "Y" : "N"); - seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", - priv->dma_cap.estsel ? "Y" : "N"); - seq_printf(seq, "\tFrame Preemption (FPE): %s\n", - priv->dma_cap.fpesel ? "Y" : "N"); - seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", - priv->dma_cap.tbssel ? "Y" : "N"); - return 0; -} -DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); - -/* Use network device events to rename debugfs file entries. - */ -static int stmmac_device_event(struct notifier_block *unused, - unsigned long event, void *ptr) -{ - struct net_device *dev = netdev_notifier_info_to_dev(ptr); - struct stmmac_priv *priv = netdev_priv(dev); - - if (dev->netdev_ops != &stmmac_netdev_ops) - goto done; - - switch (event) { - case NETDEV_CHANGENAME: - if (priv->dbgfs_dir) - priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, - priv->dbgfs_dir, - stmmac_fs_dir, - dev->name); - break; - } -done: - return NOTIFY_DONE; -} - -static struct notifier_block stmmac_notifier = { - .notifier_call = stmmac_device_event, -}; - -static void stmmac_init_fs(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - rtnl_lock(); - - /* Create per netdev entries */ - priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); - - /* Entry to report DMA RX/TX rings */ - debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, - &stmmac_rings_status_fops); - - /* Entry to report the DMA HW features */ - debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, - &stmmac_dma_cap_fops); - - rtnl_unlock(); -} - -static void stmmac_exit_fs(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - debugfs_remove_recursive(priv->dbgfs_dir); -} -#endif /* CONFIG_DEBUG_FS */ - -static u32 stmmac_vid_crc32_le(__le16 vid_le) -{ - unsigned char *data = (unsigned char *)&vid_le; - unsigned char data_byte = 0; - u32 crc = ~0x0; - u32 temp = 0; - int i, bits; - - bits = get_bitmask_order(VLAN_VID_MASK); - for (i = 0; i < bits; i++) { - if ((i % 8) == 0) - data_byte = data[i / 8]; - - temp = ((crc & 1) ^ data_byte) & 1; - crc >>= 1; - data_byte >>= 1; - - if (temp) - crc ^= 0xedb88320; - } - - return crc; -} - -static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) -{ - u32 crc, hash = 0; - __le16 pmatch = 0; - int count = 0; - u16 vid = 0; - - for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { - __le16 vid_le = cpu_to_le16(vid); - crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; - hash |= (1 << crc); - count++; - } - - if (!priv->dma_cap.vlhash) { - if (count > 2) /* VID = 0 always passes filter */ - return -EOPNOTSUPP; - - pmatch = cpu_to_le16(vid); - hash = 0; - } - - return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); -} - -static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - bool is_double = false; - int ret; - - if (be16_to_cpu(proto) == ETH_P_8021AD) - is_double = true; - - set_bit(vid, priv->active_vlans); - ret = stmmac_vlan_update(priv, is_double); - if (ret) { - clear_bit(vid, priv->active_vlans); - return ret; - } - - if (priv->hw->num_vlan) { - ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); - if (ret) - return ret; - } - - return 0; -} - -static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - bool is_double = false; - int ret; - - ret = pm_runtime_get_sync(priv->device); - if (ret < 0) { - pm_runtime_put_noidle(priv->device); - return ret; - } - - if (be16_to_cpu(proto) == ETH_P_8021AD) - is_double = true; - - clear_bit(vid, priv->active_vlans); - - if (priv->hw->num_vlan) { - ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); - if (ret) - goto del_vlan_error; - } - - ret = stmmac_vlan_update(priv, is_double); - -del_vlan_error: - pm_runtime_put(priv->device); - - return ret; -} - -static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - switch (bpf->command) { - case XDP_SETUP_PROG: - return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); - case XDP_SETUP_XSK_POOL: - return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, - bpf->xsk.queue_id); - default: - return -EOPNOTSUPP; - } -} - -static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, - struct xdp_frame **frames, u32 flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int cpu = smp_processor_id(); - struct netdev_queue *nq; - int i, nxmit = 0; - int queue; - - if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) - return -ENETDOWN; - - if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) - return -EINVAL; - - queue = stmmac_xdp_get_tx_queue(priv, cpu); - nq = netdev_get_tx_queue(priv->dev, queue); - - __netif_tx_lock(nq, cpu); - /* Avoids TX time-out as we are sharing with slow path */ - txq_trans_cond_update(nq); - - for (i = 0; i < num_frames; i++) { - int res; - - res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); - if (res == STMMAC_XDP_CONSUMED) - break; - - nxmit++; - } - - if (flags & XDP_XMIT_FLUSH) { - stmmac_flush_tx_descriptors(priv, queue); - stmmac_tx_timer_arm(priv, queue); - } - - __netif_tx_unlock(nq); - - return nxmit; -} - -void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); - - stmmac_stop_rx_dma(priv, queue); - __free_dma_rx_desc_resources(priv, queue); -} - -void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - u32 buf_size; - int ret; - - ret = __alloc_dma_rx_desc_resources(priv, queue); - if (ret) { - netdev_err(priv->dev, "Failed to alloc RX desc.\n"); - return; - } - - ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL); - if (ret) { - __free_dma_rx_desc_resources(priv, queue); - netdev_err(priv->dev, "Failed to init RX desc.\n"); - return; - } - - stmmac_clear_rx_descriptors(priv, queue); - - stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - rx_q->dma_rx_phy, rx_q->queue_index); - - rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * - sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, - rx_q->rx_tail_addr, rx_q->queue_index); - - if (rx_q->xsk_pool && rx_q->buf_alloc_num) { - buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); - stmmac_set_dma_bfsize(priv, priv->ioaddr, - buf_size, - rx_q->queue_index); - } else { - stmmac_set_dma_bfsize(priv, priv->ioaddr, - priv->dma_buf_sz, - rx_q->queue_index); - } - - stmmac_start_rx_dma(priv, queue); - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); -} - -void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - - stmmac_stop_tx_dma(priv, queue); - __free_dma_tx_desc_resources(priv, queue); -} - -void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - int ret; - - ret = __alloc_dma_tx_desc_resources(priv, queue); - if (ret) { - netdev_err(priv->dev, "Failed to alloc TX desc.\n"); - return; - } - - ret = __init_dma_tx_desc_rings(priv, queue); - if (ret) { - __free_dma_tx_desc_resources(priv, queue); - netdev_err(priv->dev, "Failed to init TX desc.\n"); - return; - } - - stmmac_clear_tx_descriptors(priv, queue); - - stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - tx_q->dma_tx_phy, tx_q->queue_index); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); - - tx_q->tx_tail_addr = tx_q->dma_tx_phy; - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, - tx_q->tx_tail_addr, tx_q->queue_index); - - stmmac_start_tx_dma(priv, queue); - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); -} - -void stmmac_xdp_release(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 chan; - - /* Disable NAPI process */ - stmmac_disable_all_queues(priv); - - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - /* Free the IRQ lines */ - stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); - - /* Stop TX/RX DMA channels */ - stmmac_stop_all_dma(priv); - - /* Release and free the Rx/Tx resources */ - free_dma_desc_resources(priv); - - /* Disable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, false); - - /* set trans_start so we don't get spurious - * watchdogs during reset - */ - netif_trans_update(dev); - netif_carrier_off(dev); -} - -int stmmac_xdp_open(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 rx_cnt = priv->plat->rx_queues_to_use; - u32 tx_cnt = priv->plat->tx_queues_to_use; - u32 dma_csr_ch = max(rx_cnt, tx_cnt); - struct stmmac_rx_queue *rx_q; - struct stmmac_tx_queue *tx_q; - u32 buf_size; - bool sph_en; - u32 chan; - int ret; - - ret = alloc_dma_desc_resources(priv); - if (ret < 0) { - netdev_err(dev, "%s: DMA descriptors allocation failed\n", - __func__); - goto dma_desc_error; - } - - ret = init_dma_desc_rings(dev, GFP_KERNEL); - if (ret < 0) { - netdev_err(dev, "%s: DMA descriptors initialization failed\n", - __func__); - goto init_error; - } - - /* DMA CSR Channel configuration */ - for (chan = 0; chan < dma_csr_ch; chan++) - stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); - - /* Adjust Split header */ - sph_en = (priv->hw->rx_csum > 0) && priv->sph; - - /* DMA RX Channel Configuration */ - for (chan = 0; chan < rx_cnt; chan++) { - rx_q = &priv->rx_queue[chan]; - - stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - rx_q->dma_rx_phy, chan); - - rx_q->rx_tail_addr = rx_q->dma_rx_phy + - (rx_q->buf_alloc_num * - sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, - rx_q->rx_tail_addr, chan); - - if (rx_q->xsk_pool && rx_q->buf_alloc_num) { - buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); - stmmac_set_dma_bfsize(priv, priv->ioaddr, - buf_size, - rx_q->queue_index); - } else { - stmmac_set_dma_bfsize(priv, priv->ioaddr, - priv->dma_buf_sz, - rx_q->queue_index); - } - - stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); - } - - /* DMA TX Channel Configuration */ - for (chan = 0; chan < tx_cnt; chan++) { - tx_q = &priv->tx_queue[chan]; - - stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - tx_q->dma_tx_phy, chan); - - tx_q->tx_tail_addr = tx_q->dma_tx_phy; - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, - tx_q->tx_tail_addr, chan); - - hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - tx_q->txtimer.function = stmmac_tx_timer; - } - - /* Enable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, true); - - /* Start Rx & Tx DMA Channels */ - stmmac_start_all_dma(priv); - - ret = stmmac_request_irq(dev); - if (ret) - goto irq_error; - - /* Enable NAPI process*/ - stmmac_enable_all_queues(priv); - netif_carrier_on(dev); - netif_tx_start_all_queues(dev); - - return 0; - -irq_error: - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - stmmac_hw_teardown(dev); -init_error: - free_dma_desc_resources(priv); -dma_desc_error: - return ret; -} - -int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct stmmac_rx_queue *rx_q; - struct stmmac_tx_queue *tx_q; - struct stmmac_channel *ch; - - if (test_bit(STMMAC_DOWN, &priv->state) || - !netif_carrier_ok(priv->dev)) - return -ENETDOWN; - - if (!stmmac_xdp_is_enabled(priv)) - return -ENXIO; - - if (queue >= priv->plat->rx_queues_to_use || - queue >= priv->plat->tx_queues_to_use) - return -EINVAL; - - rx_q = &priv->rx_queue[queue]; - tx_q = &priv->tx_queue[queue]; - ch = &priv->channel[queue]; - - if (!rx_q->xsk_pool && !tx_q->xsk_pool) - return -ENXIO; - - if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { - /* EQoS does not have per-DMA channel SW interrupt, - * so we schedule RX Napi straight-away. - */ - if (likely(napi_schedule_prep(&ch->rxtx_napi))) - __napi_schedule(&ch->rxtx_napi); - } - - return 0; -} - -static const struct net_device_ops stmmac_netdev_ops = { - .ndo_open = stmmac_open, - .ndo_start_xmit = stmmac_xmit, - .ndo_stop = stmmac_release, - .ndo_change_mtu = stmmac_change_mtu, - .ndo_fix_features = stmmac_fix_features, - .ndo_set_features = stmmac_set_features, - .ndo_set_rx_mode = stmmac_set_rx_mode, - .ndo_tx_timeout = stmmac_tx_timeout, - .ndo_eth_ioctl = stmmac_ioctl, - .ndo_setup_tc = stmmac_setup_tc, - .ndo_select_queue = stmmac_select_queue, -#ifdef CONFIG_NET_POLL_CONTROLLER - .ndo_poll_controller = stmmac_poll_controller, -#endif - .ndo_set_mac_address = stmmac_set_mac_address, - .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, - .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, - .ndo_bpf = stmmac_bpf, - .ndo_xdp_xmit = stmmac_xdp_xmit, - .ndo_xsk_wakeup = stmmac_xsk_wakeup, -}; - -static void stmmac_reset_subtask(struct stmmac_priv *priv) -{ - if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) - return; - if (test_bit(STMMAC_DOWN, &priv->state)) - return; - - netdev_err(priv->dev, "Reset adapter.\n"); - - rtnl_lock(); - netif_trans_update(priv->dev); - while (test_and_set_bit(STMMAC_RESETING, &priv->state)) - usleep_range(1000, 2000); - - set_bit(STMMAC_DOWN, &priv->state); - dev_close(priv->dev); - dev_open(priv->dev, NULL); - clear_bit(STMMAC_DOWN, &priv->state); - clear_bit(STMMAC_RESETING, &priv->state); - rtnl_unlock(); -} - -static void stmmac_service_task(struct work_struct *work) -{ - struct stmmac_priv *priv = container_of(work, struct stmmac_priv, - service_task); - - stmmac_reset_subtask(priv); - clear_bit(STMMAC_SERVICE_SCHED, &priv->state); -} - -/** - * stmmac_hw_init - Init the MAC device - * @priv: driver private structure - * Description: this function is to configure the MAC device according to - * some platform parameters or the HW capability register. It prepares the - * driver to use either ring or chain modes and to setup either enhanced or - * normal descriptors. - */ -static int stmmac_hw_init(struct stmmac_priv *priv) -{ - int ret; - - /* dwmac-sun8i only work in chain mode */ - if (priv->plat->has_sun8i) - chain_mode = 1; - priv->chain_mode = chain_mode; - - /* Initialize HW Interface */ - ret = stmmac_hwif_init(priv); - if (ret) - return ret; - - /* Get the HW capability (new GMAC newer than 3.50a) */ - priv->hw_cap_support = stmmac_get_hw_features(priv); - if (priv->hw_cap_support) { - dev_info(priv->device, "DMA HW capability register supported\n"); - - /* We can override some gmac/dma configuration fields: e.g. - * enh_desc, tx_coe (e.g. that are passed through the - * platform) with the values from the HW capability - * register (if supported). - */ - priv->plat->enh_desc = priv->dma_cap.enh_desc; - priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && - !priv->plat->use_phy_wol; - priv->hw->pmt = priv->plat->pmt; - if (priv->dma_cap.hash_tb_sz) { - priv->hw->multicast_filter_bins = - (BIT(priv->dma_cap.hash_tb_sz) << 5); - priv->hw->mcast_bits_log2 = - ilog2(priv->hw->multicast_filter_bins); - } - - /* TXCOE doesn't work in thresh DMA mode */ - if (priv->plat->force_thresh_dma_mode) - priv->plat->tx_coe = 0; - else - priv->plat->tx_coe = priv->dma_cap.tx_coe; - - /* In case of GMAC4 rx_coe is from HW cap register. */ - priv->plat->rx_coe = priv->dma_cap.rx_coe; - - if (priv->dma_cap.rx_coe_type2) - priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; - else if (priv->dma_cap.rx_coe_type1) - priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; - - } else { - dev_info(priv->device, "No HW DMA feature register supported\n"); - } - - if (priv->plat->rx_coe) { - priv->hw->rx_csum = priv->plat->rx_coe; - dev_info(priv->device, "RX Checksum Offload Engine supported\n"); - if (priv->synopsys_id < DWMAC_CORE_4_00) - dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); - } - if (priv->plat->tx_coe) - dev_info(priv->device, "TX Checksum insertion supported\n"); - - if (priv->plat->pmt) { - dev_info(priv->device, "Wake-Up On Lan supported\n"); - device_set_wakeup_capable(priv->device, 1); - } - - if (priv->dma_cap.tsoen) - dev_info(priv->device, "TSO supported\n"); - - priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; - priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; - - /* Run HW quirks, if any */ - if (priv->hwif_quirks) { - ret = priv->hwif_quirks(priv); - if (ret) - return ret; - } - - /* Rx Watchdog is available in the COREs newer than the 3.40. - * In some case, for example on bugged HW this feature - * has to be disable and this can be done by passing the - * riwt_off field from the platform. - */ - if (((priv->synopsys_id >= DWMAC_CORE_3_50) || - (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { - priv->use_riwt = 1; - dev_info(priv->device, - "Enable RX Mitigation via HW Watchdog Timer\n"); - } - - return 0; -} - -static void stmmac_napi_add(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 queue, maxq; - - maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - ch->priv_data = priv; - ch->index = queue; - spin_lock_init(&ch->lock); - - if (queue < priv->plat->rx_queues_to_use) { - netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, - NAPI_POLL_WEIGHT); - } - if (queue < priv->plat->tx_queues_to_use) { - netif_tx_napi_add(dev, &ch->tx_napi, - stmmac_napi_poll_tx, - NAPI_POLL_WEIGHT); - } - if (queue < priv->plat->rx_queues_to_use && - queue < priv->plat->tx_queues_to_use) { - netif_napi_add(dev, &ch->rxtx_napi, - stmmac_napi_poll_rxtx, - NAPI_POLL_WEIGHT); - } - } -} - -static void stmmac_napi_del(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 queue, maxq; - - maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - if (queue < priv->plat->rx_queues_to_use) - netif_napi_del(&ch->rx_napi); - if (queue < priv->plat->tx_queues_to_use) - netif_napi_del(&ch->tx_napi); - if (queue < priv->plat->rx_queues_to_use && - queue < priv->plat->tx_queues_to_use) { - netif_napi_del(&ch->rxtx_napi); - } - } -} - -int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret = 0; - - if (netif_running(dev)) - stmmac_release(dev); - - stmmac_napi_del(dev); - - priv->plat->rx_queues_to_use = rx_cnt; - priv->plat->tx_queues_to_use = tx_cnt; - - stmmac_napi_add(dev); - - if (netif_running(dev)) - ret = stmmac_open(dev); - - return ret; -} - -int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret = 0; - - if (netif_running(dev)) - stmmac_release(dev); - - priv->dma_rx_size = rx_size; - priv->dma_tx_size = tx_size; - - if (netif_running(dev)) - ret = stmmac_open(dev); - - return ret; -} - -#define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" -static void stmmac_fpe_lp_task(struct work_struct *work) -{ - struct stmmac_priv *priv = container_of(work, struct stmmac_priv, - fpe_task); - struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; - enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; - enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; - bool *hs_enable = &fpe_cfg->hs_enable; - bool *enable = &fpe_cfg->enable; - int retries = 20; - - while (retries-- > 0) { - /* Bail out immediately if FPE handshake is OFF */ - if (*lo_state == FPE_STATE_OFF || !*hs_enable) - break; - - if (*lo_state == FPE_STATE_ENTERING_ON && - *lp_state == FPE_STATE_ENTERING_ON) { - stmmac_fpe_configure(priv, priv->ioaddr, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, - *enable); - - netdev_info(priv->dev, "configured FPE\n"); - - *lo_state = FPE_STATE_ON; - *lp_state = FPE_STATE_ON; - netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); - break; - } - - if ((*lo_state == FPE_STATE_CAPABLE || - *lo_state == FPE_STATE_ENTERING_ON) && - *lp_state != FPE_STATE_ON) { - netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, - *lo_state, *lp_state); - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - MPACKET_VERIFY); - } - /* Sleep then retry */ - msleep(500); - } - - clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); -} - -void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) -{ - if (priv->plat->fpe_cfg->hs_enable != enable) { - if (enable) { - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - MPACKET_VERIFY); - } else { - priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; - priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; - } - - priv->plat->fpe_cfg->hs_enable = enable; - } -} - -/** - * stmmac_dvr_probe - * @device: device pointer - * @plat_dat: platform data pointer - * @res: stmmac resource pointer - * Description: this is the main probe function used to - * call the alloc_etherdev, allocate the priv structure. - * Return: - * returns 0 on success, otherwise errno. - */ -int stmmac_dvr_probe(struct device *device, - struct plat_stmmacenet_data *plat_dat, - struct stmmac_resources *res) -{ - struct net_device *ndev = NULL; - struct stmmac_priv *priv; - u32 rxq; - int i, ret = 0; - - ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), - MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); - if (!ndev) - return -ENOMEM; - - SET_NETDEV_DEV(ndev, device); - - priv = netdev_priv(ndev); - priv->device = device; - priv->dev = ndev; - - stmmac_set_ethtool_ops(ndev); - priv->pause = pause; - priv->plat = plat_dat; - priv->ioaddr = res->addr; - priv->dev->base_addr = (unsigned long)res->addr; - priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; - - priv->dev->irq = res->irq; - priv->wol_irq = res->wol_irq; - priv->lpi_irq = res->lpi_irq; - priv->sfty_ce_irq = res->sfty_ce_irq; - priv->sfty_ue_irq = res->sfty_ue_irq; - for (i = 0; i < MTL_MAX_RX_QUEUES; i++) - priv->rx_irq[i] = res->rx_irq[i]; - for (i = 0; i < MTL_MAX_TX_QUEUES; i++) - priv->tx_irq[i] = res->tx_irq[i]; - - if (!is_zero_ether_addr(res->mac)) - eth_hw_addr_set(priv->dev, res->mac); - - dev_set_drvdata(device, priv->dev); - - /* Verify driver arguments */ - stmmac_verify_args(); - - priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); - if (!priv->af_xdp_zc_qps) - return -ENOMEM; - - /* Allocate workqueue */ - priv->wq = create_singlethread_workqueue("stmmac_wq"); - if (!priv->wq) { - dev_err(priv->device, "failed to create workqueue\n"); - return -ENOMEM; - } - - INIT_WORK(&priv->service_task, stmmac_service_task); - - /* Initialize Link Partner FPE workqueue */ - INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); - - /* Override with kernel parameters if supplied XXX CRS XXX - * this needs to have multiple instances - */ - if ((phyaddr >= 0) && (phyaddr <= 31)) - priv->plat->phy_addr = phyaddr; - - if (priv->plat->stmmac_rst) { - ret = reset_control_assert(priv->plat->stmmac_rst); - reset_control_deassert(priv->plat->stmmac_rst); - /* Some reset controllers have only reset callback instead of - * assert + deassert callbacks pair. - */ - if (ret == -ENOTSUPP) - reset_control_reset(priv->plat->stmmac_rst); - } - - ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); - if (ret == -ENOTSUPP) - dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", - ERR_PTR(ret)); - - /* Init MAC and get the capabilities */ - ret = stmmac_hw_init(priv); - if (ret) - goto error_hw_init; - - /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. - */ - if (priv->synopsys_id < DWMAC_CORE_5_20) - priv->plat->dma_cfg->dche = false; - - stmmac_check_ether_addr(priv); - - ndev->netdev_ops = &stmmac_netdev_ops; - - ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | - NETIF_F_RXCSUM; - - ret = stmmac_tc_init(priv, priv); - if (!ret) { - ndev->hw_features |= NETIF_F_HW_TC; - } - - if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { - ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; - if (priv->plat->has_gmac4) - ndev->hw_features |= NETIF_F_GSO_UDP_L4; - priv->tso = true; - dev_info(priv->device, "TSO feature enabled\n"); - } - - if (priv->dma_cap.sphen) { - ndev->hw_features |= NETIF_F_GRO; - priv->sph_cap = true; - priv->sph = priv->sph_cap; - dev_info(priv->device, "SPH feature enabled\n"); - } - - /* The current IP register MAC_HW_Feature1[ADDR64] only define - * 32/40/64 bit width, but some SOC support others like i.MX8MP - * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. - * So overwrite dma_cap.addr64 according to HW real design. - */ - if (priv->plat->addr64) - priv->dma_cap.addr64 = priv->plat->addr64; - - if (priv->dma_cap.addr64) { - ret = dma_set_mask_and_coherent(device, - DMA_BIT_MASK(priv->dma_cap.addr64)); - if (!ret) { - dev_info(priv->device, "Using %d bits DMA width\n", - priv->dma_cap.addr64); - - /* - * If more than 32 bits can be addressed, make sure to - * enable enhanced addressing mode. - */ - if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) - priv->plat->dma_cfg->eame = true; - } else { - ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); - if (ret) { - dev_err(priv->device, "Failed to set DMA Mask\n"); - goto error_hw_init; - } - - priv->dma_cap.addr64 = 32; - } - } - - ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; - ndev->watchdog_timeo = msecs_to_jiffies(watchdog); -#ifdef STMMAC_VLAN_TAG_USED - /* Both mac100 and gmac support receive VLAN tag detection */ - ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; - if (priv->dma_cap.vlhash) { - ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; - ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; - } - if (priv->dma_cap.vlins) { - ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; - if (priv->dma_cap.dvlan) - ndev->features |= NETIF_F_HW_VLAN_STAG_TX; - } -#endif - priv->msg_enable = netif_msg_init(debug, default_msg_level); - - /* Initialize RSS */ - rxq = priv->plat->rx_queues_to_use; - netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); - for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) - priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); - - if (priv->dma_cap.rssen && priv->plat->rss_en) - ndev->features |= NETIF_F_RXHASH; - - /* MTU range: 46 - hw-specific max */ - ndev->min_mtu = ETH_ZLEN - ETH_HLEN; - if (priv->plat->has_xgmac) - ndev->max_mtu = XGMAC_JUMBO_LEN; - else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) - ndev->max_mtu = JUMBO_LEN; - else - ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); - /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu - * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. - */ - if ((priv->plat->maxmtu < ndev->max_mtu) && - (priv->plat->maxmtu >= ndev->min_mtu)) - ndev->max_mtu = priv->plat->maxmtu; - else if (priv->plat->maxmtu < ndev->min_mtu) - dev_warn(priv->device, - "%s: warning: maxmtu having invalid value (%d)\n", - __func__, priv->plat->maxmtu); - - if (flow_ctrl) - priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ - - /* Setup channels NAPI */ - stmmac_napi_add(ndev); - - mutex_init(&priv->lock); - - /* If a specific clk_csr value is passed from the platform - * this means that the CSR Clock Range selection cannot be - * changed at run-time and it is fixed. Viceversa the driver'll try to - * set the MDC clock dynamically according to the csr actual - * clock input. - */ - if (priv->plat->clk_csr >= 0) - priv->clk_csr = priv->plat->clk_csr; - else - stmmac_clk_csr_set(priv); - - stmmac_check_pcs_mode(priv); - - pm_runtime_get_noresume(device); - pm_runtime_set_active(device); -<<<<<<< - if (!pm_runtime_enabled(device)) - pm_runtime_enable(device); -======= - pm_runtime_enable(device); - /* - * Prevent runtime pm from being ON by default. Users can enable - * it using power/control in sysfs. - */ - pm_runtime_forbid(device); ->>>>>>> - - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI) { - /* MDIO bus Registration */ - ret = stmmac_mdio_register(ndev); - if (ret < 0) { - dev_err(priv->device, - "%s: MDIO bus (id: %d) registration failed", - __func__, priv->plat->bus_id); - goto error_mdio_register; - } - } - - if (priv->plat->speed_mode_2500) - priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); - - if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { - ret = stmmac_xpcs_setup(priv->mii); - if (ret) - goto error_xpcs_setup; - } - - ret = stmmac_phy_setup(priv); - if (ret) { - netdev_err(ndev, "failed to setup phy (%d)\n", ret); - goto error_phy_setup; - } - - ret = register_netdev(ndev); - if (ret) { - dev_err(priv->device, "%s: ERROR %i registering the device\n", - __func__, ret); - goto error_netdev_register; - } - - if (priv->plat->serdes_powerup) { - ret = priv->plat->serdes_powerup(ndev, - priv->plat->bsp_priv); - - if (ret < 0) - goto error_serdes_powerup; - } - -#ifdef CONFIG_DEBUG_FS - stmmac_init_fs(ndev); -#endif - - if (priv->plat->dump_debug_regs) - priv->plat->dump_debug_regs(priv->plat->bsp_priv); - - /* Let pm_runtime_put() disable the clocks. - * If CONFIG_PM is not enabled, the clocks will stay powered. - */ - pm_runtime_put(device); - - return ret; - -error_serdes_powerup: - unregister_netdev(ndev); -error_netdev_register: - phylink_destroy(priv->phylink); -error_xpcs_setup: -error_phy_setup: - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI) - stmmac_mdio_unregister(ndev); -error_mdio_register: - stmmac_napi_del(ndev); -error_hw_init: - destroy_workqueue(priv->wq); - bitmap_free(priv->af_xdp_zc_qps); - - return ret; -} -EXPORT_SYMBOL_GPL(stmmac_dvr_probe); - -/** - * stmmac_dvr_remove - * @dev: device pointer - * Description: this function resets the TX/RX processes, disables the MAC RX/TX - * changes the link status, releases the DMA descriptor rings. - */ -int stmmac_dvr_remove(struct device *dev) -{ - struct net_device *ndev = dev_get_drvdata(dev); - struct stmmac_priv *priv = netdev_priv(ndev); - - netdev_info(priv->dev, "%s: removing driver", __func__); - - stmmac_stop_all_dma(priv); - stmmac_mac_set(priv, priv->ioaddr, false); - netif_carrier_off(ndev); - unregister_netdev(ndev); - - /* Serdes power down needs to happen after VLAN filter - * is deleted that is triggered by unregister_netdev(). - */ - if (priv->plat->serdes_powerdown) - priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); - -#ifdef CONFIG_DEBUG_FS - stmmac_exit_fs(ndev); -#endif - phylink_destroy(priv->phylink); - if (priv->plat->stmmac_rst) - reset_control_assert(priv->plat->stmmac_rst); - reset_control_assert(priv->plat->stmmac_ahb_rst); - pm_runtime_put(dev); - pm_runtime_disable(dev); - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI) - stmmac_mdio_unregister(ndev); - destroy_workqueue(priv->wq); - mutex_destroy(&priv->lock); - bitmap_free(priv->af_xdp_zc_qps); - - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_dvr_remove); - -/** - * stmmac_suspend - suspend callback - * @dev: device pointer - * Description: this is the function to suspend the device and it is called - * by the platform driver to stop the network queue, release the resources, - * program the PMT register (for WoL), clean and release driver resources. - */ -int stmmac_suspend(struct device *dev) -{ - struct net_device *ndev = dev_get_drvdata(dev); - struct stmmac_priv *priv = netdev_priv(ndev); - u32 chan; - - if (!ndev || !netif_running(ndev)) - return 0; - - mutex_lock(&priv->lock); - - netif_device_detach(ndev); - - stmmac_disable_all_queues(priv); - - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - if (priv->eee_enabled) { - priv->tx_path_in_lpi_mode = false; - del_timer_sync(&priv->eee_ctrl_timer); - } - - /* Stop TX/RX DMA */ - stmmac_stop_all_dma(priv); - - if (priv->plat->serdes_powerdown) - priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); - - /* Enable Power down mode by programming the PMT regs */ - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - stmmac_pmt(priv, priv->hw, priv->wolopts); - priv->irq_wake = 1; - } else { - stmmac_mac_set(priv, priv->ioaddr, false); - pinctrl_pm_select_sleep_state(priv->device); - } - - mutex_unlock(&priv->lock); - - rtnl_lock(); - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - phylink_suspend(priv->phylink, true); - } else { - if (device_may_wakeup(priv->device)) - phylink_speed_down(priv->phylink, false); - phylink_suspend(priv->phylink, false); - } - rtnl_unlock(); - - if (priv->dma_cap.fpesel) { - /* Disable FPE */ - stmmac_fpe_configure(priv, priv->ioaddr, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, false); - - stmmac_fpe_handshake(priv, false); - stmmac_fpe_stop_wq(priv); - } - - priv->speed = SPEED_UNKNOWN; - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_suspend); - -/** - * stmmac_reset_queues_param - reset queue parameters - * @priv: device pointer - */ -static void stmmac_reset_queues_param(struct stmmac_priv *priv) -{ - u32 rx_cnt = priv->plat->rx_queues_to_use; - u32 tx_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - for (queue = 0; queue < rx_cnt; queue++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - rx_q->cur_rx = 0; - rx_q->dirty_rx = 0; - } - - for (queue = 0; queue < tx_cnt; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - tx_q->cur_tx = 0; - tx_q->dirty_tx = 0; - tx_q->mss = 0; - - netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); - } -} - -/** - * stmmac_resume - resume callback - * @dev: device pointer - * Description: when resume this function is invoked to setup the DMA and CORE - * in a usable state. - */ -int stmmac_resume(struct device *dev) -{ - struct net_device *ndev = dev_get_drvdata(dev); - struct stmmac_priv *priv = netdev_priv(ndev); - int ret; - - if (!netif_running(ndev)) - return 0; - - /* Power Down bit, into the PM register, is cleared - * automatically as soon as a magic packet or a Wake-up frame - * is received. Anyway, it's better to manually clear - * this bit because it can generate problems while resuming - * from another devices (e.g. serial console). - */ - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - mutex_lock(&priv->lock); - stmmac_pmt(priv, priv->hw, 0); - mutex_unlock(&priv->lock); - priv->irq_wake = 0; - } else { - pinctrl_pm_select_default_state(priv->device); - /* reset the phy so that it's ready */ - if (priv->mii) - stmmac_mdio_reset(priv->mii); - } - - if (priv->plat->serdes_powerup) { - ret = priv->plat->serdes_powerup(ndev, - priv->plat->bsp_priv); - - if (ret < 0) - return ret; - } - - rtnl_lock(); - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - phylink_resume(priv->phylink); - } else { - phylink_resume(priv->phylink); - if (device_may_wakeup(priv->device)) - phylink_speed_up(priv->phylink); - } - rtnl_unlock(); - - rtnl_lock(); - mutex_lock(&priv->lock); - - stmmac_reset_queues_param(priv); - - stmmac_free_tx_skbufs(priv); - stmmac_clear_descriptors(priv); - - stmmac_hw_setup(ndev, false); - stmmac_init_coalesce(priv); - stmmac_set_rx_mode(ndev); - - stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); - - stmmac_enable_all_queues(priv); - - mutex_unlock(&priv->lock); - rtnl_unlock(); - - netif_device_attach(ndev); - - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_resume); - -#ifndef MODULE -static int __init stmmac_cmdline_opt(char *str) -{ - char *opt; - - if (!str || !*str) - return -EINVAL; - while ((opt = strsep(&str, ",")) != NULL) { - if (!strncmp(opt, "debug:", 6)) { - if (kstrtoint(opt + 6, 0, &debug)) - goto err; - } else if (!strncmp(opt, "phyaddr:", 8)) { - if (kstrtoint(opt + 8, 0, &phyaddr)) - goto err; - } else if (!strncmp(opt, "buf_sz:", 7)) { - if (kstrtoint(opt + 7, 0, &buf_sz)) - goto err; - } else if (!strncmp(opt, "tc:", 3)) { - if (kstrtoint(opt + 3, 0, &tc)) - goto err; - } else if (!strncmp(opt, "watchdog:", 9)) { - if (kstrtoint(opt + 9, 0, &watchdog)) - goto err; - } else if (!strncmp(opt, "flow_ctrl:", 10)) { - if (kstrtoint(opt + 10, 0, &flow_ctrl)) - goto err; - } else if (!strncmp(opt, "pause:", 6)) { - if (kstrtoint(opt + 6, 0, &pause)) - goto err; - } else if (!strncmp(opt, "eee_timer:", 10)) { - if (kstrtoint(opt + 10, 0, &eee_timer)) - goto err; - } else if (!strncmp(opt, "chain_mode:", 11)) { - if (kstrtoint(opt + 11, 0, &chain_mode)) - goto err; - } - } - return 0; - -err: - pr_err("%s: ERROR broken module parameter conversion", __func__); - return -EINVAL; -} - -__setup("stmmaceth=", stmmac_cmdline_opt); -#endif /* MODULE */ - -static int __init stmmac_init(void) -{ -#ifdef CONFIG_DEBUG_FS - /* Create debugfs main directory if it doesn't exist yet */ - if (!stmmac_fs_dir) - stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); - register_netdevice_notifier(&stmmac_notifier); -#endif - - return 0; -} - -static void __exit stmmac_exit(void) -{ -#ifdef CONFIG_DEBUG_FS - unregister_netdevice_notifier(&stmmac_notifier); - debugfs_remove_recursive(stmmac_fs_dir); -#endif -} - -module_init(stmmac_init) -module_exit(stmmac_exit) - -MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); -MODULE_AUTHOR("Giuseppe Cavallaro "); -MODULE_LICENSE("GPL"); diff --git a/rr-cache/8e9ab0176bfe82b41ee4b8e0aabb3ea1eb2cb191/preimage b/rr-cache/8e9ab0176bfe82b41ee4b8e0aabb3ea1eb2cb191/preimage deleted file mode 100644 index 354840d..0000000 --- a/rr-cache/8e9ab0176bfe82b41ee4b8e0aabb3ea1eb2cb191/preimage +++ /dev/null @@ -1,457 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Linaro Ltd. - * Author: Manivannan Sadhasivam - */ - -#include -#include -#include - -#include "internal.h" - -<<<<<<< -u32 mhi_ep_mmio_read(struct mhi_ep_cntrl *mhi_cntrl, u32 offset) -{ - return readl(mhi_cntrl->mmio + offset); -======= -void mhi_ep_mmio_read(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 *regval) -{ - *regval = readl(mhi_cntrl->mmio + offset); ->>>>>>> -} - -void mhi_ep_mmio_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 val) -{ - writel(val, mhi_cntrl->mmio + offset); -} - -<<<<<<< -void mhi_ep_mmio_masked_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 mask, - u32 shift, u32 val) -{ - u32 regval; - - mhi_ep_mmio_read(mhi_cntrl, offset, ®val); - regval &= ~mask; - regval |= ((val << shift) & mask); - mhi_ep_mmio_write(mhi_cntrl, offset, regval); -} - -int mhi_ep_mmio_masked_read(struct mhi_ep_cntrl *dev, u32 offset, - u32 mask, u32 shift, u32 *regval) -{ - mhi_ep_mmio_read(dev, offset, regval); - *regval &= mask; - *regval >>= shift; - - return 0; -======= -void mhi_ep_mmio_masked_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 mask, u32 val) -{ - u32 regval; - - regval = mhi_ep_mmio_read(mhi_cntrl, offset); - regval &= ~mask; - regval |= ((val << __ffs(mask)) & mask); - mhi_ep_mmio_write(mhi_cntrl, offset, regval); -} - -u32 mhi_ep_mmio_masked_read(struct mhi_ep_cntrl *dev, u32 offset, u32 mask) -{ - u32 regval; - - regval = mhi_ep_mmio_read(dev, offset); - regval &= mask; - regval >>= __ffs(mask); - - return regval; ->>>>>>> -} - -void mhi_ep_mmio_get_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state *state, - bool *mhi_reset) -{ - u32 regval; - -<<<<<<< - mhi_ep_mmio_read(mhi_cntrl, MHICTRL, ®val); -======= - regval = mhi_ep_mmio_read(mhi_cntrl, MHICTRL); ->>>>>>> - *state = FIELD_GET(MHICTRL_MHISTATE_MASK, regval); - *mhi_reset = !!FIELD_GET(MHICTRL_RESET_MASK, regval); -} - -static void mhi_ep_mmio_mask_set_chdb_int_a7(struct mhi_ep_cntrl *mhi_cntrl, - u32 chdb_id, bool enable) -{ -<<<<<<< - u32 chid_mask, chid_idx, chid_shft, val = 0; - - chid_shft = chdb_id % 32; - chid_mask = BIT(chid_shft); - chid_idx = chdb_id / 32; - - if (chid_idx >= MHI_MASK_ROWS_CH_EV_DB) - return; -======= - u32 chid_mask, chid_idx, chid_shift, val = 0; - - chid_shift = chdb_id % 32; - chid_mask = BIT(chid_shift); - chid_idx = chdb_id / 32; - - WARN_ON(chid_idx >= MHI_MASK_ROWS_CH_EV_DB); ->>>>>>> - - if (enable) - val = 1; - - mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CHDB_INT_MASK_A7_n(chid_idx), -<<<<<<< - chid_mask, chid_shft, val); - mhi_ep_mmio_read(mhi_cntrl, MHI_CHDB_INT_MASK_A7_n(chid_idx), - &mhi_cntrl->chdb[chid_idx].mask); -======= - chid_mask, val); - - /* Update the local copy of the channel mask */ - mhi_cntrl->chdb[chid_idx].mask &= ~chid_mask; - mhi_cntrl->chdb[chid_idx].mask |= val << chid_shift; ->>>>>>> -} - -void mhi_ep_mmio_enable_chdb_a7(struct mhi_ep_cntrl *mhi_cntrl, u32 chdb_id) -{ - mhi_ep_mmio_mask_set_chdb_int_a7(mhi_cntrl, chdb_id, true); -} - -void mhi_ep_mmio_disable_chdb_a7(struct mhi_ep_cntrl *mhi_cntrl, u32 chdb_id) -{ - mhi_ep_mmio_mask_set_chdb_int_a7(mhi_cntrl, chdb_id, false); -} - -static void mhi_ep_mmio_set_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl, bool enable) -{ -<<<<<<< - u32 val = 0, i = 0; -======= - u32 val = 0, i; ->>>>>>> - - if (enable) - val = MHI_CHDB_INT_MASK_A7_n_EN_ALL; - - for (i = 0; i < MHI_MASK_ROWS_CH_EV_DB; i++) { - mhi_ep_mmio_write(mhi_cntrl, MHI_CHDB_INT_MASK_A7_n(i), val); - mhi_cntrl->chdb[i].mask = val; - } -} - -void mhi_ep_mmio_enable_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl) -{ - mhi_ep_mmio_set_chdb_interrupts(mhi_cntrl, true); -} - -<<<<<<< -static void mhi_ep_mmio_mask_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl) -======= -void mhi_ep_mmio_mask_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl) ->>>>>>> -{ - mhi_ep_mmio_set_chdb_interrupts(mhi_cntrl, false); -} - -void mhi_ep_mmio_read_chdb_status_interrupts(struct mhi_ep_cntrl *mhi_cntrl) -{ - u32 i; - - for (i = 0; i < MHI_MASK_ROWS_CH_EV_DB; i++) -<<<<<<< - mhi_cntrl->chdb[i].status = mhi_ep_mmio_read(mhi_cntrl, - MHI_CHDB_INT_STATUS_A7_n(i)); -======= - mhi_ep_mmio_read(mhi_cntrl, MHI_CHDB_INT_STATUS_A7_n(i), - &mhi_cntrl->chdb[i].status); ->>>>>>> -} - -static void mhi_ep_mmio_set_erdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl, bool enable) -{ - u32 val = 0, i; - - if (enable) - val = MHI_ERDB_INT_MASK_A7_n_EN_ALL; - - for (i = 0; i < MHI_MASK_ROWS_CH_EV_DB; i++) - mhi_ep_mmio_write(mhi_cntrl, MHI_ERDB_INT_MASK_A7_n(i), val); -} - -<<<<<<< -static void mhi_ep_mmio_mask_erdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl) -======= -void mhi_ep_mmio_mask_erdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl) ->>>>>>> -{ - mhi_ep_mmio_set_erdb_interrupts(mhi_cntrl, false); -} - -void mhi_ep_mmio_enable_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl) -{ - mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK_A7, -<<<<<<< - MHI_CTRL_MHICTRL_MASK, - MHI_CTRL_MHICTRL_SHFT, 1); -======= - MHI_CTRL_MHICTRL_MASK, 1); ->>>>>>> -} - -void mhi_ep_mmio_disable_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl) -{ - mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK_A7, -<<<<<<< - MHI_CTRL_MHICTRL_MASK, - MHI_CTRL_MHICTRL_SHFT, 0); -======= - MHI_CTRL_MHICTRL_MASK, 0); ->>>>>>> -} - -void mhi_ep_mmio_enable_cmdb_interrupt(struct mhi_ep_cntrl *mhi_cntrl) -{ - mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK_A7, -<<<<<<< - MHI_CTRL_CRDB_MASK, - MHI_CTRL_CRDB_SHFT, 1); -======= - MHI_CTRL_CRDB_MASK, 1); ->>>>>>> -} - -void mhi_ep_mmio_disable_cmdb_interrupt(struct mhi_ep_cntrl *mhi_cntrl) -{ - mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK_A7, -<<<<<<< - MHI_CTRL_CRDB_MASK, - MHI_CTRL_CRDB_SHFT, 0); -======= - MHI_CTRL_CRDB_MASK, 0); ->>>>>>> -} - -void mhi_ep_mmio_mask_interrupts(struct mhi_ep_cntrl *mhi_cntrl) -{ - mhi_ep_mmio_disable_ctrl_interrupt(mhi_cntrl); - mhi_ep_mmio_disable_cmdb_interrupt(mhi_cntrl); - mhi_ep_mmio_mask_chdb_interrupts(mhi_cntrl); - mhi_ep_mmio_mask_erdb_interrupts(mhi_cntrl); -} - -<<<<<<< -static void mhi_ep_mmio_clear_interrupts(struct mhi_ep_cntrl *mhi_cntrl) -======= -void mhi_ep_mmio_clear_interrupts(struct mhi_ep_cntrl *mhi_cntrl) ->>>>>>> -{ - u32 i = 0; - - for (i = 0; i < MHI_MASK_ROWS_CH_EV_DB; i++) - mhi_ep_mmio_write(mhi_cntrl, MHI_CHDB_INT_CLEAR_A7_n(i), - MHI_CHDB_INT_CLEAR_A7_n_CLEAR_ALL); - - for (i = 0; i < MHI_MASK_ROWS_CH_EV_DB; i++) - mhi_ep_mmio_write(mhi_cntrl, MHI_ERDB_INT_CLEAR_A7_n(i), - MHI_ERDB_INT_CLEAR_A7_n_CLEAR_ALL); - - mhi_ep_mmio_write(mhi_cntrl, MHI_CTRL_INT_CLEAR_A7, - MHI_CTRL_INT_MMIO_WR_CLEAR | - MHI_CTRL_INT_CRDB_CLEAR | - MHI_CTRL_INT_CRDB_MHICTRL_CLEAR); -} - -void mhi_ep_mmio_get_chc_base(struct mhi_ep_cntrl *mhi_cntrl) -{ -<<<<<<< - u32 ccabap_value = 0; - - mhi_ep_mmio_read(mhi_cntrl, CCABAP_HIGHER, &ccabap_value); - mhi_cntrl->ch_ctx_host_pa = ccabap_value; - mhi_cntrl->ch_ctx_host_pa <<= 32; - - mhi_ep_mmio_read(mhi_cntrl, CCABAP_LOWER, &ccabap_value); -======= - u32 ccabap_value; - - ccabap_value = mhi_ep_mmio_read(mhi_cntrl, CCABAP_HIGHER); - mhi_cntrl->ch_ctx_host_pa = ccabap_value; - mhi_cntrl->ch_ctx_host_pa <<= 32; - - ccabap_value = mhi_ep_mmio_read(mhi_cntrl, CCABAP_LOWER); ->>>>>>> - mhi_cntrl->ch_ctx_host_pa |= ccabap_value; -} - -void mhi_ep_mmio_get_erc_base(struct mhi_ep_cntrl *mhi_cntrl) -{ -<<<<<<< - u32 ecabap_value = 0; - - mhi_ep_mmio_read(mhi_cntrl, ECABAP_HIGHER, &ecabap_value); - mhi_cntrl->ev_ctx_host_pa = ecabap_value; - mhi_cntrl->ev_ctx_host_pa <<= 32; - - mhi_ep_mmio_read(mhi_cntrl, ECABAP_LOWER, &ecabap_value); -======= - u32 ecabap_value; - - ecabap_value = mhi_ep_mmio_read(mhi_cntrl, ECABAP_HIGHER); - mhi_cntrl->ev_ctx_host_pa = ecabap_value; - mhi_cntrl->ev_ctx_host_pa <<= 32; - - ecabap_value = mhi_ep_mmio_read(mhi_cntrl, ECABAP_LOWER); ->>>>>>> - mhi_cntrl->ev_ctx_host_pa |= ecabap_value; -} - -void mhi_ep_mmio_get_crc_base(struct mhi_ep_cntrl *mhi_cntrl) -{ -<<<<<<< - u32 crcbap_value = 0; - - mhi_ep_mmio_read(mhi_cntrl, CRCBAP_HIGHER, &crcbap_value); - mhi_cntrl->cmd_ctx_host_pa = crcbap_value; - mhi_cntrl->cmd_ctx_host_pa <<= 32; - - mhi_ep_mmio_read(mhi_cntrl, CRCBAP_LOWER, &crcbap_value); - mhi_cntrl->cmd_ctx_host_pa |= crcbap_value; -} - -void mhi_ep_mmio_get_ch_db(struct mhi_ep_ring *ring, u64 *wr_ptr) -{ - struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl; - u32 value = 0; - - mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_h, &value); - *wr_ptr = value; - *wr_ptr <<= 32; - - mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_l, &value); - - *wr_ptr |= value; -} - -void mhi_ep_mmio_get_er_db(struct mhi_ep_ring *ring, u64 *wr_ptr) -{ - struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl; - u32 value = 0; - - mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_h, &value); - *wr_ptr = value; - *wr_ptr <<= 32; - - mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_l, &value); - - *wr_ptr |= value; -} - -void mhi_ep_mmio_get_cmd_db(struct mhi_ep_ring *ring, u64 *wr_ptr) -{ - struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl; - u32 value = 0; - - mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_h, &value); - *wr_ptr = value; - *wr_ptr <<= 32; - - mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_l, &value); - *wr_ptr |= value; -======= - u32 crcbap_value; - - crcbap_value = mhi_ep_mmio_read(mhi_cntrl, CRCBAP_HIGHER); - mhi_cntrl->cmd_ctx_host_pa = crcbap_value; - mhi_cntrl->cmd_ctx_host_pa <<= 32; - - crcbap_value = mhi_ep_mmio_read(mhi_cntrl, CRCBAP_LOWER); - mhi_cntrl->cmd_ctx_host_pa |= crcbap_value; -} - -u64 mhi_ep_mmio_get_db(struct mhi_ep_ring *ring) -{ - struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl; - u64 db_offset; - u32 regval; - - regval = mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_h); - db_offset = regval; - db_offset <<= 32; - - regval = mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_l); - db_offset |= regval; - - return db_offset; ->>>>>>> -} - -void mhi_ep_mmio_set_env(struct mhi_ep_cntrl *mhi_cntrl, u32 value) -{ - mhi_ep_mmio_write(mhi_cntrl, BHI_EXECENV, value); -} - -void mhi_ep_mmio_clear_reset(struct mhi_ep_cntrl *mhi_cntrl) -{ -<<<<<<< - mhi_ep_mmio_masked_write(mhi_cntrl, MHICTRL, MHICTRL_RESET_MASK, - MHICTRL_RESET_SHIFT, 0); -======= - mhi_ep_mmio_masked_write(mhi_cntrl, MHICTRL, MHICTRL_RESET_MASK, 0); ->>>>>>> -} - -void mhi_ep_mmio_reset(struct mhi_ep_cntrl *mhi_cntrl) -{ - mhi_ep_mmio_write(mhi_cntrl, MHICTRL, 0); - mhi_ep_mmio_write(mhi_cntrl, MHISTATUS, 0); - mhi_ep_mmio_clear_interrupts(mhi_cntrl); -} - -void mhi_ep_mmio_init(struct mhi_ep_cntrl *mhi_cntrl) -{ -<<<<<<< - int mhi_cfg = 0; - - mhi_ep_mmio_read(mhi_cntrl, MHIREGLEN, &mhi_cntrl->reg_len); - mhi_ep_mmio_read(mhi_cntrl, CHDBOFF, &mhi_cntrl->chdb_offset); - mhi_ep_mmio_read(mhi_cntrl, ERDBOFF, &mhi_cntrl->erdb_offset); - - mhi_ep_mmio_read(mhi_cntrl, MHICFG, &mhi_cfg); -======= - int mhi_cfg; - - mhi_cntrl->chdb_offset = mhi_ep_mmio_read(mhi_cntrl, CHDBOFF); - mhi_cntrl->erdb_offset = mhi_ep_mmio_read(mhi_cntrl, ERDBOFF); - - mhi_cfg = mhi_ep_mmio_read(mhi_cntrl, MHICFG); ->>>>>>> - mhi_cntrl->event_rings = FIELD_GET(MHICFG_NER_MASK, mhi_cfg); - mhi_cntrl->hw_event_rings = FIELD_GET(MHICFG_NHWER_MASK, mhi_cfg); - - mhi_ep_mmio_reset(mhi_cntrl); -} - -void mhi_ep_mmio_update_ner(struct mhi_ep_cntrl *mhi_cntrl) -{ -<<<<<<< - int mhi_cfg = 0; - - mhi_ep_mmio_read(mhi_cntrl, MHICFG, &mhi_cfg); -======= - int mhi_cfg; - - mhi_cfg = mhi_ep_mmio_read(mhi_cntrl, MHICFG); ->>>>>>> - mhi_cntrl->event_rings = FIELD_GET(MHICFG_NER_MASK, mhi_cfg); - mhi_cntrl->hw_event_rings = FIELD_GET(MHICFG_NHWER_MASK, mhi_cfg); -} diff --git a/rr-cache/9304cf403e433f623fc9b674a050258c4b4b216c/preimage.1 b/rr-cache/9304cf403e433f623fc9b674a050258c4b4b216c/preimage.1 deleted file mode 100644 index 8589c95..0000000 --- a/rr-cache/9304cf403e433f623fc9b674a050258c4b4b216c/preimage.1 +++ /dev/null @@ -1,1510 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * drivers/of/property.c - Procedures for accessing and interpreting - * Devicetree properties and graphs. - * - * Initially created by copying procedures from drivers/of/base.c. This - * file contains the OF property as well as the OF graph interface - * functions. - * - * Paul Mackerras August 1996. - * Copyright (C) 1996-2005 Paul Mackerras. - * - * Adapted for 64bit PowerPC by Dave Engebretsen and Peter Bergner. - * {engebret|bergner}@us.ibm.com - * - * Adapted for sparc and sparc64 by David S. Miller davem@davemloft.net - * - * Reconsolidated from arch/x/kernel/prom.c by Stephen Rothwell and - * Grant Likely. - */ - -#define pr_fmt(fmt) "OF: " fmt - -#include -#include -#include -#include -#include -#include - -#include "of_private.h" - -/** - * of_graph_is_present() - check graph's presence - * @node: pointer to device_node containing graph port - * - * Return: True if @node has a port or ports (with a port) sub-node, - * false otherwise. - */ -bool of_graph_is_present(const struct device_node *node) -{ - struct device_node *ports, *port; - - ports = of_get_child_by_name(node, "ports"); - if (ports) - node = ports; - - port = of_get_child_by_name(node, "port"); - of_node_put(ports); - of_node_put(port); - - return !!port; -} -EXPORT_SYMBOL(of_graph_is_present); - -/** - * of_property_count_elems_of_size - Count the number of elements in a property - * - * @np: device node from which the property value is to be read. - * @propname: name of the property to be searched. - * @elem_size: size of the individual element - * - * Search for a property in a device node and count the number of elements of - * size elem_size in it. - * - * Return: The number of elements on sucess, -EINVAL if the property does not - * exist or its length does not match a multiple of elem_size and -ENODATA if - * the property does not have a value. - */ -int of_property_count_elems_of_size(const struct device_node *np, - const char *propname, int elem_size) -{ - struct property *prop = of_find_property(np, propname, NULL); - - if (!prop) - return -EINVAL; - if (!prop->value) - return -ENODATA; - - if (prop->length % elem_size != 0) { - pr_err("size of %s in node %pOF is not a multiple of %d\n", - propname, np, elem_size); - return -EINVAL; - } - - return prop->length / elem_size; -} -EXPORT_SYMBOL_GPL(of_property_count_elems_of_size); - -/** - * of_find_property_value_of_size - * - * @np: device node from which the property value is to be read. - * @propname: name of the property to be searched. - * @min: minimum allowed length of property value - * @max: maximum allowed length of property value (0 means unlimited) - * @len: if !=NULL, actual length is written to here - * - * Search for a property in a device node and valid the requested size. - * - * Return: The property value on success, -EINVAL if the property does not - * exist, -ENODATA if property does not have a value, and -EOVERFLOW if the - * property data is too small or too large. - * - */ -static void *of_find_property_value_of_size(const struct device_node *np, - const char *propname, u32 min, u32 max, size_t *len) -{ - struct property *prop = of_find_property(np, propname, NULL); - - if (!prop) - return ERR_PTR(-EINVAL); - if (!prop->value) - return ERR_PTR(-ENODATA); - if (prop->length < min) - return ERR_PTR(-EOVERFLOW); - if (max && prop->length > max) - return ERR_PTR(-EOVERFLOW); - - if (len) - *len = prop->length; - - return prop->value; -} - -/** - * of_property_read_u32_index - Find and read a u32 from a multi-value property. - * - * @np: device node from which the property value is to be read. - * @propname: name of the property to be searched. - * @index: index of the u32 in the list of values - * @out_value: pointer to return value, modified only if no error. - * - * Search for a property in a device node and read nth 32-bit value from - * it. - * - * Return: 0 on success, -EINVAL if the property does not exist, - * -ENODATA if property does not have a value, and -EOVERFLOW if the - * property data isn't large enough. - * - * The out_value is modified only if a valid u32 value can be decoded. - */ -int of_property_read_u32_index(const struct device_node *np, - const char *propname, - u32 index, u32 *out_value) -{ - const u32 *val = of_find_property_value_of_size(np, propname, - ((index + 1) * sizeof(*out_value)), - 0, - NULL); - - if (IS_ERR(val)) - return PTR_ERR(val); - - *out_value = be32_to_cpup(((__be32 *)val) + index); - return 0; -} -EXPORT_SYMBOL_GPL(of_property_read_u32_index); - -/** - * of_property_read_u64_index - Find and read a u64 from a multi-value property. - * - * @np: device node from which the property value is to be read. - * @propname: name of the property to be searched. - * @index: index of the u64 in the list of values - * @out_value: pointer to return value, modified only if no error. - * - * Search for a property in a device node and read nth 64-bit value from - * it. - * - * Return: 0 on success, -EINVAL if the property does not exist, - * -ENODATA if property does not have a value, and -EOVERFLOW if the - * property data isn't large enough. - * - * The out_value is modified only if a valid u64 value can be decoded. - */ -int of_property_read_u64_index(const struct device_node *np, - const char *propname, - u32 index, u64 *out_value) -{ - const u64 *val = of_find_property_value_of_size(np, propname, - ((index + 1) * sizeof(*out_value)), - 0, NULL); - - if (IS_ERR(val)) - return PTR_ERR(val); - - *out_value = be64_to_cpup(((__be64 *)val) + index); - return 0; -} -EXPORT_SYMBOL_GPL(of_property_read_u64_index); - -/** - * of_property_read_variable_u8_array - Find and read an array of u8 from a - * property, with bounds on the minimum and maximum array size. - * - * @np: device node from which the property value is to be read. - * @propname: name of the property to be searched. - * @out_values: pointer to found values. - * @sz_min: minimum number of array elements to read - * @sz_max: maximum number of array elements to read, if zero there is no - * upper limit on the number of elements in the dts entry but only - * sz_min will be read. - * - * Search for a property in a device node and read 8-bit value(s) from - * it. - * - * dts entry of array should be like: - * ``property = /bits/ 8 <0x50 0x60 0x70>;`` - * - * Return: The number of elements read on success, -EINVAL if the property - * does not exist, -ENODATA if property does not have a value, and -EOVERFLOW - * if the property data is smaller than sz_min or longer than sz_max. - * - * The out_values is modified only if a valid u8 value can be decoded. - */ -int of_property_read_variable_u8_array(const struct device_node *np, - const char *propname, u8 *out_values, - size_t sz_min, size_t sz_max) -{ - size_t sz, count; - const u8 *val = of_find_property_value_of_size(np, propname, - (sz_min * sizeof(*out_values)), - (sz_max * sizeof(*out_values)), - &sz); - - if (IS_ERR(val)) - return PTR_ERR(val); - - if (!sz_max) - sz = sz_min; - else - sz /= sizeof(*out_values); - - count = sz; - while (count--) - *out_values++ = *val++; - - return sz; -} -EXPORT_SYMBOL_GPL(of_property_read_variable_u8_array); - -/** - * of_property_read_variable_u16_array - Find and read an array of u16 from a - * property, with bounds on the minimum and maximum array size. - * - * @np: device node from which the property value is to be read. - * @propname: name of the property to be searched. - * @out_values: pointer to found values. - * @sz_min: minimum number of array elements to read - * @sz_max: maximum number of array elements to read, if zero there is no - * upper limit on the number of elements in the dts entry but only - * sz_min will be read. - * - * Search for a property in a device node and read 16-bit value(s) from - * it. - * - * dts entry of array should be like: - * ``property = /bits/ 16 <0x5000 0x6000 0x7000>;`` - * - * Return: The number of elements read on success, -EINVAL if the property - * does not exist, -ENODATA if property does not have a value, and -EOVERFLOW - * if the property data is smaller than sz_min or longer than sz_max. - * - * The out_values is modified only if a valid u16 value can be decoded. - */ -int of_property_read_variable_u16_array(const struct device_node *np, - const char *propname, u16 *out_values, - size_t sz_min, size_t sz_max) -{ - size_t sz, count; - const __be16 *val = of_find_property_value_of_size(np, propname, - (sz_min * sizeof(*out_values)), - (sz_max * sizeof(*out_values)), - &sz); - - if (IS_ERR(val)) - return PTR_ERR(val); - - if (!sz_max) - sz = sz_min; - else - sz /= sizeof(*out_values); - - count = sz; - while (count--) - *out_values++ = be16_to_cpup(val++); - - return sz; -} -EXPORT_SYMBOL_GPL(of_property_read_variable_u16_array); - -/** - * of_property_read_variable_u32_array - Find and read an array of 32 bit - * integers from a property, with bounds on the minimum and maximum array size. - * - * @np: device node from which the property value is to be read. - * @propname: name of the property to be searched. - * @out_values: pointer to return found values. - * @sz_min: minimum number of array elements to read - * @sz_max: maximum number of array elements to read, if zero there is no - * upper limit on the number of elements in the dts entry but only - * sz_min will be read. - * - * Search for a property in a device node and read 32-bit value(s) from - * it. - * - * Return: The number of elements read on success, -EINVAL if the property - * does not exist, -ENODATA if property does not have a value, and -EOVERFLOW - * if the property data is smaller than sz_min or longer than sz_max. - * - * The out_values is modified only if a valid u32 value can be decoded. - */ -int of_property_read_variable_u32_array(const struct device_node *np, - const char *propname, u32 *out_values, - size_t sz_min, size_t sz_max) -{ - size_t sz, count; - const __be32 *val = of_find_property_value_of_size(np, propname, - (sz_min * sizeof(*out_values)), - (sz_max * sizeof(*out_values)), - &sz); - - if (IS_ERR(val)) - return PTR_ERR(val); - - if (!sz_max) - sz = sz_min; - else - sz /= sizeof(*out_values); - - count = sz; - while (count--) - *out_values++ = be32_to_cpup(val++); - - return sz; -} -EXPORT_SYMBOL_GPL(of_property_read_variable_u32_array); - -/** - * of_property_read_u64 - Find and read a 64 bit integer from a property - * @np: device node from which the property value is to be read. - * @propname: name of the property to be searched. - * @out_value: pointer to return value, modified only if return value is 0. - * - * Search for a property in a device node and read a 64-bit value from - * it. - * - * Return: 0 on success, -EINVAL if the property does not exist, - * -ENODATA if property does not have a value, and -EOVERFLOW if the - * property data isn't large enough. - * - * The out_value is modified only if a valid u64 value can be decoded. - */ -int of_property_read_u64(const struct device_node *np, const char *propname, - u64 *out_value) -{ - const __be32 *val = of_find_property_value_of_size(np, propname, - sizeof(*out_value), - 0, - NULL); - - if (IS_ERR(val)) - return PTR_ERR(val); - - *out_value = of_read_number(val, 2); - return 0; -} -EXPORT_SYMBOL_GPL(of_property_read_u64); - -/** - * of_property_read_variable_u64_array - Find and read an array of 64 bit - * integers from a property, with bounds on the minimum and maximum array size. - * - * @np: device node from which the property value is to be read. - * @propname: name of the property to be searched. - * @out_values: pointer to found values. - * @sz_min: minimum number of array elements to read - * @sz_max: maximum number of array elements to read, if zero there is no - * upper limit on the number of elements in the dts entry but only - * sz_min will be read. - * - * Search for a property in a device node and read 64-bit value(s) from - * it. - * - * Return: The number of elements read on success, -EINVAL if the property - * does not exist, -ENODATA if property does not have a value, and -EOVERFLOW - * if the property data is smaller than sz_min or longer than sz_max. - * - * The out_values is modified only if a valid u64 value can be decoded. - */ -int of_property_read_variable_u64_array(const struct device_node *np, - const char *propname, u64 *out_values, - size_t sz_min, size_t sz_max) -{ - size_t sz, count; - const __be32 *val = of_find_property_value_of_size(np, propname, - (sz_min * sizeof(*out_values)), - (sz_max * sizeof(*out_values)), - &sz); - - if (IS_ERR(val)) - return PTR_ERR(val); - - if (!sz_max) - sz = sz_min; - else - sz /= sizeof(*out_values); - - count = sz; - while (count--) { - *out_values++ = of_read_number(val, 2); - val += 2; - } - - return sz; -} -EXPORT_SYMBOL_GPL(of_property_read_variable_u64_array); - -/** - * of_property_read_string - Find and read a string from a property - * @np: device node from which the property value is to be read. - * @propname: name of the property to be searched. - * @out_string: pointer to null terminated return string, modified only if - * return value is 0. - * - * Search for a property in a device tree node and retrieve a null - * terminated string value (pointer to data, not a copy). - * - * Return: 0 on success, -EINVAL if the property does not exist, -ENODATA if - * property does not have a value, and -EILSEQ if the string is not - * null-terminated within the length of the property data. - * - * The out_string pointer is modified only if a valid string can be decoded. - */ -int of_property_read_string(const struct device_node *np, const char *propname, - const char **out_string) -{ - const struct property *prop = of_find_property(np, propname, NULL); - if (!prop) - return -EINVAL; - if (!prop->value) - return -ENODATA; - if (strnlen(prop->value, prop->length) >= prop->length) - return -EILSEQ; - *out_string = prop->value; - return 0; -} -EXPORT_SYMBOL_GPL(of_property_read_string); - -/** - * of_property_match_string() - Find string in a list and return index - * @np: pointer to node containing string list property - * @propname: string list property name - * @string: pointer to string to search for in string list - * - * This function searches a string list property and returns the index - * of a specific string value. - */ -int of_property_match_string(const struct device_node *np, const char *propname, - const char *string) -{ - const struct property *prop = of_find_property(np, propname, NULL); - size_t l; - int i; - const char *p, *end; - - if (!prop) - return -EINVAL; - if (!prop->value) - return -ENODATA; - - p = prop->value; - end = p + prop->length; - - for (i = 0; p < end; i++, p += l) { - l = strnlen(p, end - p) + 1; - if (p + l > end) - return -EILSEQ; - pr_debug("comparing %s with %s\n", string, p); - if (strcmp(string, p) == 0) - return i; /* Found it; return index */ - } - return -ENODATA; -} -EXPORT_SYMBOL_GPL(of_property_match_string); - -/** - * of_property_read_string_helper() - Utility helper for parsing string properties - * @np: device node from which the property value is to be read. - * @propname: name of the property to be searched. - * @out_strs: output array of string pointers. - * @sz: number of array elements to read. - * @skip: Number of strings to skip over at beginning of list. - * - * Don't call this function directly. It is a utility helper for the - * of_property_read_string*() family of functions. - */ -int of_property_read_string_helper(const struct device_node *np, - const char *propname, const char **out_strs, - size_t sz, int skip) -{ - const struct property *prop = of_find_property(np, propname, NULL); - int l = 0, i = 0; - const char *p, *end; - - if (!prop) - return -EINVAL; - if (!prop->value) - return -ENODATA; - p = prop->value; - end = p + prop->length; - - for (i = 0; p < end && (!out_strs || i < skip + sz); i++, p += l) { - l = strnlen(p, end - p) + 1; - if (p + l > end) - return -EILSEQ; - if (out_strs && i >= skip) - *out_strs++ = p; - } - i -= skip; - return i <= 0 ? -ENODATA : i; -} -EXPORT_SYMBOL_GPL(of_property_read_string_helper); - -const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur, - u32 *pu) -{ - const void *curv = cur; - - if (!prop) - return NULL; - - if (!cur) { - curv = prop->value; - goto out_val; - } - - curv += sizeof(*cur); - if (curv >= prop->value + prop->length) - return NULL; - -out_val: - *pu = be32_to_cpup(curv); - return curv; -} -EXPORT_SYMBOL_GPL(of_prop_next_u32); - -const char *of_prop_next_string(struct property *prop, const char *cur) -{ - const void *curv = cur; - - if (!prop) - return NULL; - - if (!cur) - return prop->value; - - curv += strlen(cur) + 1; - if (curv >= prop->value + prop->length) - return NULL; - - return curv; -} -EXPORT_SYMBOL_GPL(of_prop_next_string); - -/** - * of_graph_parse_endpoint() - parse common endpoint node properties - * @node: pointer to endpoint device_node - * @endpoint: pointer to the OF endpoint data structure - * - * The caller should hold a reference to @node. - */ -int of_graph_parse_endpoint(const struct device_node *node, - struct of_endpoint *endpoint) -{ - struct device_node *port_node = of_get_parent(node); - - WARN_ONCE(!port_node, "%s(): endpoint %pOF has no parent node\n", - __func__, node); - - memset(endpoint, 0, sizeof(*endpoint)); - - endpoint->local_node = node; - /* - * It doesn't matter whether the two calls below succeed. - * If they don't then the default value 0 is used. - */ - of_property_read_u32(port_node, "reg", &endpoint->port); - of_property_read_u32(node, "reg", &endpoint->id); - - of_node_put(port_node); - - return 0; -} -EXPORT_SYMBOL(of_graph_parse_endpoint); - -/** - * of_graph_get_port_by_id() - get the port matching a given id - * @parent: pointer to the parent device node - * @id: id of the port - * - * Return: A 'port' node pointer with refcount incremented. The caller - * has to use of_node_put() on it when done. - */ -struct device_node *of_graph_get_port_by_id(struct device_node *parent, u32 id) -{ - struct device_node *node, *port; - - node = of_get_child_by_name(parent, "ports"); - if (node) - parent = node; - - for_each_child_of_node(parent, port) { - u32 port_id = 0; - - if (!of_node_name_eq(port, "port")) - continue; - of_property_read_u32(port, "reg", &port_id); - if (id == port_id) - break; - } - - of_node_put(node); - - return port; -} -EXPORT_SYMBOL(of_graph_get_port_by_id); - -/** - * of_graph_get_next_endpoint() - get next endpoint node - * @parent: pointer to the parent device node - * @prev: previous endpoint node, or NULL to get first - * - * Return: An 'endpoint' node pointer with refcount incremented. Refcount - * of the passed @prev node is decremented. - */ -struct device_node *of_graph_get_next_endpoint(const struct device_node *parent, - struct device_node *prev) -{ - struct device_node *endpoint; - struct device_node *port; - - if (!parent) - return NULL; - - /* - * Start by locating the port node. If no previous endpoint is specified - * search for the first port node, otherwise get the previous endpoint - * parent port node. - */ - if (!prev) { - struct device_node *node; - - node = of_get_child_by_name(parent, "ports"); - if (node) - parent = node; - - port = of_get_child_by_name(parent, "port"); - of_node_put(node); - - if (!port) { - pr_err("graph: no port node found in %pOF\n", parent); - return NULL; - } - } else { - port = of_get_parent(prev); - if (WARN_ONCE(!port, "%s(): endpoint %pOF has no parent node\n", - __func__, prev)) - return NULL; - } - - while (1) { - /* - * Now that we have a port node, get the next endpoint by - * getting the next child. If the previous endpoint is NULL this - * will return the first child. - */ - endpoint = of_get_next_child(port, prev); - if (endpoint) { - of_node_put(port); - return endpoint; - } - - /* No more endpoints under this port, try the next one. */ - prev = NULL; - - do { - port = of_get_next_child(parent, port); - if (!port) - return NULL; - } while (!of_node_name_eq(port, "port")); - } -} -EXPORT_SYMBOL(of_graph_get_next_endpoint); - -/** - * of_graph_get_endpoint_by_regs() - get endpoint node of specific identifiers - * @parent: pointer to the parent device node - * @port_reg: identifier (value of reg property) of the parent port node - * @reg: identifier (value of reg property) of the endpoint node - * - * Return: An 'endpoint' node pointer which is identified by reg and at the same - * is the child of a port node identified by port_reg. reg and port_reg are - * ignored when they are -1. Use of_node_put() on the pointer when done. - */ -struct device_node *of_graph_get_endpoint_by_regs( - const struct device_node *parent, int port_reg, int reg) -{ - struct of_endpoint endpoint; - struct device_node *node = NULL; - - for_each_endpoint_of_node(parent, node) { - of_graph_parse_endpoint(node, &endpoint); - if (((port_reg == -1) || (endpoint.port == port_reg)) && - ((reg == -1) || (endpoint.id == reg))) - return node; - } - - return NULL; -} -EXPORT_SYMBOL(of_graph_get_endpoint_by_regs); - -/** - * of_graph_get_remote_endpoint() - get remote endpoint node - * @node: pointer to a local endpoint device_node - * - * Return: Remote endpoint node associated with remote endpoint node linked - * to @node. Use of_node_put() on it when done. - */ -struct device_node *of_graph_get_remote_endpoint(const struct device_node *node) -{ - /* Get remote endpoint node. */ - return of_parse_phandle(node, "remote-endpoint", 0); -} -EXPORT_SYMBOL(of_graph_get_remote_endpoint); - -/** - * of_graph_get_port_parent() - get port's parent node - * @node: pointer to a local endpoint device_node - * - * Return: device node associated with endpoint node linked - * to @node. Use of_node_put() on it when done. - */ -struct device_node *of_graph_get_port_parent(struct device_node *node) -{ - unsigned int depth; - - if (!node) - return NULL; - - /* - * Preserve usecount for passed in node as of_get_next_parent() - * will do of_node_put() on it. - */ - of_node_get(node); - - /* Walk 3 levels up only if there is 'ports' node. */ - for (depth = 3; depth && node; depth--) { - node = of_get_next_parent(node); - if (depth == 2 && !of_node_name_eq(node, "ports")) - break; - } - return node; -} -EXPORT_SYMBOL(of_graph_get_port_parent); - -/** - * of_graph_get_remote_port_parent() - get remote port's parent node - * @node: pointer to a local endpoint device_node - * - * Return: Remote device node associated with remote endpoint node linked - * to @node. Use of_node_put() on it when done. - */ -struct device_node *of_graph_get_remote_port_parent( - const struct device_node *node) -{ - struct device_node *np, *pp; - - /* Get remote endpoint node. */ - np = of_graph_get_remote_endpoint(node); - - pp = of_graph_get_port_parent(np); - - of_node_put(np); - - return pp; -} -EXPORT_SYMBOL(of_graph_get_remote_port_parent); - -/** - * of_graph_get_remote_port() - get remote port node - * @node: pointer to a local endpoint device_node - * - * Return: Remote port node associated with remote endpoint node linked - * to @node. Use of_node_put() on it when done. - */ -struct device_node *of_graph_get_remote_port(const struct device_node *node) -{ - struct device_node *np; - - /* Get remote endpoint node. */ - np = of_graph_get_remote_endpoint(node); - if (!np) - return NULL; - return of_get_next_parent(np); -} -EXPORT_SYMBOL(of_graph_get_remote_port); - -int of_graph_get_endpoint_count(const struct device_node *np) -{ - struct device_node *endpoint; - int num = 0; - - for_each_endpoint_of_node(np, endpoint) - num++; - - return num; -} -EXPORT_SYMBOL(of_graph_get_endpoint_count); - -/** - * of_graph_get_remote_node() - get remote parent device_node for given port/endpoint - * @node: pointer to parent device_node containing graph port/endpoint - * @port: identifier (value of reg property) of the parent port node - * @endpoint: identifier (value of reg property) of the endpoint node - * - * Return: Remote device node associated with remote endpoint node linked - * to @node. Use of_node_put() on it when done. - */ -struct device_node *of_graph_get_remote_node(const struct device_node *node, - u32 port, u32 endpoint) -{ - struct device_node *endpoint_node, *remote; - - endpoint_node = of_graph_get_endpoint_by_regs(node, port, endpoint); - if (!endpoint_node) { - pr_debug("no valid endpoint (%d, %d) for node %pOF\n", - port, endpoint, node); - return NULL; - } - - remote = of_graph_get_remote_port_parent(endpoint_node); - of_node_put(endpoint_node); - if (!remote) { - pr_debug("no valid remote node\n"); - return NULL; - } - - if (!of_device_is_available(remote)) { - pr_debug("not available for remote node\n"); - of_node_put(remote); - return NULL; - } - - return remote; -} -EXPORT_SYMBOL(of_graph_get_remote_node); - -static struct fwnode_handle *of_fwnode_get(struct fwnode_handle *fwnode) -{ - return of_fwnode_handle(of_node_get(to_of_node(fwnode))); -} - -static void of_fwnode_put(struct fwnode_handle *fwnode) -{ - of_node_put(to_of_node(fwnode)); -} - -static bool of_fwnode_device_is_available(const struct fwnode_handle *fwnode) -{ - return of_device_is_available(to_of_node(fwnode)); -} - -static bool of_fwnode_property_present(const struct fwnode_handle *fwnode, - const char *propname) -{ - return of_property_read_bool(to_of_node(fwnode), propname); -} - -static int of_fwnode_property_read_int_array(const struct fwnode_handle *fwnode, - const char *propname, - unsigned int elem_size, void *val, - size_t nval) -{ - const struct device_node *node = to_of_node(fwnode); - - if (!val) - return of_property_count_elems_of_size(node, propname, - elem_size); - - switch (elem_size) { - case sizeof(u8): - return of_property_read_u8_array(node, propname, val, nval); - case sizeof(u16): - return of_property_read_u16_array(node, propname, val, nval); - case sizeof(u32): - return of_property_read_u32_array(node, propname, val, nval); - case sizeof(u64): - return of_property_read_u64_array(node, propname, val, nval); - } - - return -ENXIO; -} - -static int -of_fwnode_property_read_string_array(const struct fwnode_handle *fwnode, - const char *propname, const char **val, - size_t nval) -{ - const struct device_node *node = to_of_node(fwnode); - - return val ? - of_property_read_string_array(node, propname, val, nval) : - of_property_count_strings(node, propname); -} - -static const char *of_fwnode_get_name(const struct fwnode_handle *fwnode) -{ - return kbasename(to_of_node(fwnode)->full_name); -} - -static const char *of_fwnode_get_name_prefix(const struct fwnode_handle *fwnode) -{ - /* Root needs no prefix here (its name is "/"). */ - if (!to_of_node(fwnode)->parent) - return ""; - - return "/"; -} - -static struct fwnode_handle * -of_fwnode_get_parent(const struct fwnode_handle *fwnode) -{ - return of_fwnode_handle(of_get_parent(to_of_node(fwnode))); -} - -static struct fwnode_handle * -of_fwnode_get_next_child_node(const struct fwnode_handle *fwnode, - struct fwnode_handle *child) -{ - return of_fwnode_handle(of_get_next_available_child(to_of_node(fwnode), - to_of_node(child))); -} - -static struct fwnode_handle * -of_fwnode_get_named_child_node(const struct fwnode_handle *fwnode, - const char *childname) -{ - const struct device_node *node = to_of_node(fwnode); - struct device_node *child; - - for_each_available_child_of_node(node, child) - if (of_node_name_eq(child, childname)) - return of_fwnode_handle(child); - - return NULL; -} - -static int -of_fwnode_get_reference_args(const struct fwnode_handle *fwnode, - const char *prop, const char *nargs_prop, - unsigned int nargs, unsigned int index, - struct fwnode_reference_args *args) -{ - struct of_phandle_args of_args; - unsigned int i; - int ret; - - if (nargs_prop) - ret = of_parse_phandle_with_args(to_of_node(fwnode), prop, - nargs_prop, index, &of_args); - else - ret = of_parse_phandle_with_fixed_args(to_of_node(fwnode), prop, - nargs, index, &of_args); - if (ret < 0) - return ret; - if (!args) - return 0; - - args->nargs = of_args.args_count; - args->fwnode = of_fwnode_handle(of_args.np); - - for (i = 0; i < NR_FWNODE_REFERENCE_ARGS; i++) - args->args[i] = i < of_args.args_count ? of_args.args[i] : 0; - - return 0; -} - -static struct fwnode_handle * -of_fwnode_graph_get_next_endpoint(const struct fwnode_handle *fwnode, - struct fwnode_handle *prev) -{ - return of_fwnode_handle(of_graph_get_next_endpoint(to_of_node(fwnode), - to_of_node(prev))); -} - -static struct fwnode_handle * -of_fwnode_graph_get_remote_endpoint(const struct fwnode_handle *fwnode) -{ - return of_fwnode_handle( - of_graph_get_remote_endpoint(to_of_node(fwnode))); -} - -static struct fwnode_handle * -of_fwnode_graph_get_port_parent(struct fwnode_handle *fwnode) -{ - struct device_node *np; - - /* Get the parent of the port */ - np = of_get_parent(to_of_node(fwnode)); - if (!np) - return NULL; - - /* Is this the "ports" node? If not, it's the port parent. */ - if (!of_node_name_eq(np, "ports")) - return of_fwnode_handle(np); - - return of_fwnode_handle(of_get_next_parent(np)); -} - -static int of_fwnode_graph_parse_endpoint(const struct fwnode_handle *fwnode, - struct fwnode_endpoint *endpoint) -{ - const struct device_node *node = to_of_node(fwnode); - struct device_node *port_node = of_get_parent(node); - - endpoint->local_fwnode = fwnode; - - of_property_read_u32(port_node, "reg", &endpoint->port); - of_property_read_u32(node, "reg", &endpoint->id); - - of_node_put(port_node); - - return 0; -} - -static const void * -of_fwnode_device_get_match_data(const struct fwnode_handle *fwnode, - const struct device *dev) -{ - return of_device_get_match_data(dev); -} - -static bool of_is_ancestor_of(struct device_node *test_ancestor, - struct device_node *child) -{ - of_node_get(child); - while (child) { - if (child == test_ancestor) { - of_node_put(child); - return true; - } - child = of_get_next_parent(child); - } - return false; -} - -<<<<<<< -======= -static struct device_node *of_get_compat_node(struct device_node *np) -{ - of_node_get(np); - - while (np) { - if (!of_device_is_available(np)) { - of_node_put(np); - np = NULL; - } - - if (of_find_property(np, "compatible", NULL)) - break; - - np = of_get_next_parent(np); - } - - return np; -} - -static struct device_node *of_get_compat_node_parent(struct device_node *np) -{ - struct device_node *parent, *node; - - parent = of_get_parent(np); - node = of_get_compat_node(parent); - of_node_put(parent); - - return node; -} - ->>>>>>> -/** - * of_link_to_phandle - Add fwnode link to supplier from supplier phandle - * @con_np: consumer device tree node - * @sup_np: supplier device tree node - * - * Given a phandle to a supplier device tree node (@sup_np), this function - * finds the device that owns the supplier device tree node and creates a - * device link from @dev consumer device to the supplier device. This function - * doesn't create device links for invalid scenarios such as trying to create a - * link with a parent device as the consumer of its child device. In such - * cases, it returns an error. - * - * Returns: - * - 0 if fwnode link successfully created to supplier - * - -EINVAL if the supplier link is invalid and should not be created - * - -ENODEV if struct device will never be create for supplier - */ -static int of_link_to_phandle(struct device_node *con_np, - struct device_node *sup_np) -{ - struct device *sup_dev; - struct device_node *tmp_np = sup_np; - - of_node_get(sup_np); - /* - * Find the device node that contains the supplier phandle. It may be - * @sup_np or it may be an ancestor of @sup_np. - */ - while (sup_np) { - - /* Don't allow linking to a disabled supplier */ - if (!of_device_is_available(sup_np)) { - of_node_put(sup_np); - sup_np = NULL; - } - - if (of_find_property(sup_np, "compatible", NULL)) - break; - - sup_np = of_get_next_parent(sup_np); - } - - if (!sup_np) { - pr_debug("Not linking %pOFP to %pOFP - No device\n", - con_np, tmp_np); - return -ENODEV; - } - - /* - * Don't allow linking a device node as a consumer of one of its - * descendant nodes. By definition, a child node can't be a functional - * dependency for the parent node. - */ - if (of_is_ancestor_of(con_np, sup_np)) { - pr_debug("Not linking %pOFP to %pOFP - is descendant\n", - con_np, sup_np); - of_node_put(sup_np); - return -EINVAL; - } - - /* - * Don't create links to "early devices" that won't have struct devices - * created for them. - */ - sup_dev = get_dev_from_fwnode(&sup_np->fwnode); - if (!sup_dev && - (of_node_check_flag(sup_np, OF_POPULATED) || - sup_np->fwnode.flags & FWNODE_FLAG_NOT_DEVICE)) { - pr_debug("Not linking %pOFP to %pOFP - No struct device\n", - con_np, sup_np); - of_node_put(sup_np); - return -ENODEV; - } - put_device(sup_dev); - - fwnode_link_add(of_fwnode_handle(con_np), of_fwnode_handle(sup_np)); - of_node_put(sup_np); - - return 0; -} - -/** - * parse_prop_cells - Property parsing function for suppliers - * - * @np: Pointer to device tree node containing a list - * @prop_name: Name of property to be parsed. Expected to hold phandle values - * @index: For properties holding a list of phandles, this is the index - * into the list. - * @list_name: Property name that is known to contain list of phandle(s) to - * supplier(s) - * @cells_name: property name that specifies phandles' arguments count - * - * This is a helper function to parse properties that have a known fixed name - * and are a list of phandles and phandle arguments. - * - * Returns: - * - phandle node pointer with refcount incremented. Caller must of_node_put() - * on it when done. - * - NULL if no phandle found at index - */ -static struct device_node *parse_prop_cells(struct device_node *np, - const char *prop_name, int index, - const char *list_name, - const char *cells_name) -{ - struct of_phandle_args sup_args; - - if (strcmp(prop_name, list_name)) - return NULL; - - if (of_parse_phandle_with_args(np, list_name, cells_name, index, - &sup_args)) - return NULL; - - return sup_args.np; -} - -#define DEFINE_SIMPLE_PROP(fname, name, cells) \ -static struct device_node *parse_##fname(struct device_node *np, \ - const char *prop_name, int index) \ -{ \ - return parse_prop_cells(np, prop_name, index, name, cells); \ -} - -static int strcmp_suffix(const char *str, const char *suffix) -{ - unsigned int len, suffix_len; - - len = strlen(str); - suffix_len = strlen(suffix); - if (len <= suffix_len) - return -1; - return strcmp(str + len - suffix_len, suffix); -} - -/** - * parse_suffix_prop_cells - Suffix property parsing function for suppliers - * - * @np: Pointer to device tree node containing a list - * @prop_name: Name of property to be parsed. Expected to hold phandle values - * @index: For properties holding a list of phandles, this is the index - * into the list. - * @suffix: Property suffix that is known to contain list of phandle(s) to - * supplier(s) - * @cells_name: property name that specifies phandles' arguments count - * - * This is a helper function to parse properties that have a known fixed suffix - * and are a list of phandles and phandle arguments. - * - * Returns: - * - phandle node pointer with refcount incremented. Caller must of_node_put() - * on it when done. - * - NULL if no phandle found at index - */ -static struct device_node *parse_suffix_prop_cells(struct device_node *np, - const char *prop_name, int index, - const char *suffix, - const char *cells_name) -{ - struct of_phandle_args sup_args; - - if (strcmp_suffix(prop_name, suffix)) - return NULL; - - if (of_parse_phandle_with_args(np, prop_name, cells_name, index, - &sup_args)) - return NULL; - - return sup_args.np; -} - -#define DEFINE_SUFFIX_PROP(fname, suffix, cells) \ -static struct device_node *parse_##fname(struct device_node *np, \ - const char *prop_name, int index) \ -{ \ - return parse_suffix_prop_cells(np, prop_name, index, suffix, cells); \ -} - -/** - * struct supplier_bindings - Property parsing functions for suppliers - * - * @parse_prop: function name - * parse_prop() finds the node corresponding to a supplier phandle - * @parse_prop.np: Pointer to device node holding supplier phandle property - * @parse_prop.prop_name: Name of property holding a phandle value - * @parse_prop.index: For properties holding a list of phandles, this is the - * index into the list -<<<<<<< -======= - * @optional: Describes whether a supplier is mandatory or not - * @node_not_dev: The consumer node containing the property is never converted - * to a struct device. Instead, parse ancestor nodes for the - * compatible property to find a node corresponding to a device. ->>>>>>> - * - * Returns: - * parse_prop() return values are - * - phandle node pointer with refcount incremented. Caller must of_node_put() - * on it when done. - * - NULL if no phandle found at index - */ -struct supplier_bindings { - struct device_node *(*parse_prop)(struct device_node *np, - const char *prop_name, int index); - bool optional; -}; - -DEFINE_SIMPLE_PROP(clocks, "clocks", "#clock-cells") -DEFINE_SIMPLE_PROP(interconnects, "interconnects", "#interconnect-cells") -DEFINE_SIMPLE_PROP(iommus, "iommus", "#iommu-cells") -DEFINE_SIMPLE_PROP(mboxes, "mboxes", "#mbox-cells") -DEFINE_SIMPLE_PROP(io_channels, "io-channel", "#io-channel-cells") -DEFINE_SIMPLE_PROP(interrupt_parent, "interrupt-parent", NULL) -DEFINE_SIMPLE_PROP(dmas, "dmas", "#dma-cells") -DEFINE_SIMPLE_PROP(power_domains, "power-domains", "#power-domain-cells") -DEFINE_SIMPLE_PROP(hwlocks, "hwlocks", "#hwlock-cells") -DEFINE_SIMPLE_PROP(extcon, "extcon", NULL) -DEFINE_SIMPLE_PROP(nvmem_cells, "nvmem-cells", NULL) -DEFINE_SIMPLE_PROP(phys, "phys", "#phy-cells") -DEFINE_SIMPLE_PROP(wakeup_parent, "wakeup-parent", NULL) -DEFINE_SIMPLE_PROP(pinctrl0, "pinctrl-0", NULL) -DEFINE_SIMPLE_PROP(pinctrl1, "pinctrl-1", NULL) -DEFINE_SIMPLE_PROP(pinctrl2, "pinctrl-2", NULL) -DEFINE_SIMPLE_PROP(pinctrl3, "pinctrl-3", NULL) -DEFINE_SIMPLE_PROP(pinctrl4, "pinctrl-4", NULL) -DEFINE_SIMPLE_PROP(pinctrl5, "pinctrl-5", NULL) -DEFINE_SIMPLE_PROP(pinctrl6, "pinctrl-6", NULL) -DEFINE_SIMPLE_PROP(pinctrl7, "pinctrl-7", NULL) -DEFINE_SIMPLE_PROP(pinctrl8, "pinctrl-8", NULL) -DEFINE_SIMPLE_PROP(remote_endpoint, "remote-endpoint", NULL) -DEFINE_SIMPLE_PROP(pwms, "pwms", "#pwm-cells") -DEFINE_SIMPLE_PROP(resets, "resets", "#reset-cells") -DEFINE_SIMPLE_PROP(leds, "leds", NULL) -DEFINE_SIMPLE_PROP(backlight, "backlight", NULL) -DEFINE_SUFFIX_PROP(regulators, "-supply", NULL) -DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells") - -static struct device_node *parse_gpios(struct device_node *np, - const char *prop_name, int index) -{ - if (!strcmp_suffix(prop_name, ",nr-gpios")) - return NULL; - - return parse_suffix_prop_cells(np, prop_name, index, "-gpios", - "#gpio-cells"); -} - -static struct device_node *parse_iommu_maps(struct device_node *np, - const char *prop_name, int index) -{ - if (strcmp(prop_name, "iommu-map")) - return NULL; - - return of_parse_phandle(np, prop_name, (index * 4) + 1); -} - -static struct device_node *parse_gpio_compat(struct device_node *np, - const char *prop_name, int index) -{ - struct of_phandle_args sup_args; - - if (strcmp(prop_name, "gpio") && strcmp(prop_name, "gpios")) - return NULL; - - /* - * Ignore node with gpio-hog property since its gpios are all provided - * by its parent. - */ - if (of_find_property(np, "gpio-hog", NULL)) - return NULL; - - if (of_parse_phandle_with_args(np, prop_name, "#gpio-cells", index, - &sup_args)) - return NULL; - - return sup_args.np; -} - -static struct device_node *parse_interrupts(struct device_node *np, - const char *prop_name, int index) -{ - struct of_phandle_args sup_args; - - if (!IS_ENABLED(CONFIG_OF_IRQ) || IS_ENABLED(CONFIG_PPC)) - return NULL; - - if (strcmp(prop_name, "interrupts") && - strcmp(prop_name, "interrupts-extended")) - return NULL; - - return of_irq_parse_one(np, index, &sup_args) ? NULL : sup_args.np; -} - -static const struct supplier_bindings of_supplier_bindings[] = { - { .parse_prop = parse_clocks, }, - { .parse_prop = parse_interconnects, }, - { .parse_prop = parse_iommus, .optional = true, }, - { .parse_prop = parse_iommu_maps, .optional = true, }, - { .parse_prop = parse_mboxes, }, - { .parse_prop = parse_io_channels, }, - { .parse_prop = parse_interrupt_parent, }, - { .parse_prop = parse_dmas, .optional = true, }, - { .parse_prop = parse_power_domains, }, - { .parse_prop = parse_hwlocks, }, - { .parse_prop = parse_extcon, }, - { .parse_prop = parse_nvmem_cells, }, - { .parse_prop = parse_phys, }, - { .parse_prop = parse_wakeup_parent, }, - { .parse_prop = parse_pinctrl0, }, - { .parse_prop = parse_pinctrl1, }, - { .parse_prop = parse_pinctrl2, }, - { .parse_prop = parse_pinctrl3, }, - { .parse_prop = parse_pinctrl4, }, - { .parse_prop = parse_pinctrl5, }, - { .parse_prop = parse_pinctrl6, }, - { .parse_prop = parse_pinctrl7, }, - { .parse_prop = parse_pinctrl8, }, - { .parse_prop = parse_pwms, }, - { .parse_prop = parse_resets, }, - { .parse_prop = parse_leds, }, - { .parse_prop = parse_backlight, }, - { .parse_prop = parse_gpio_compat, }, - { .parse_prop = parse_interrupts, }, - { .parse_prop = parse_regulators, }, - { .parse_prop = parse_gpio, }, - { .parse_prop = parse_gpios, }, - {} -}; - -/** - * of_link_property - Create device links to suppliers listed in a property - * @con_np: The consumer device tree node which contains the property - * @prop_name: Name of property to be parsed - * - * This function checks if the property @prop_name that is present in the - * @con_np device tree node is one of the known common device tree bindings - * that list phandles to suppliers. If @prop_name isn't one, this function - * doesn't do anything. - * - * If @prop_name is one, this function attempts to create fwnode links from the - * consumer device tree node @con_np to all the suppliers device tree nodes - * listed in @prop_name. - * - * Any failed attempt to create a fwnode link will NOT result in an immediate - * return. of_link_property() must create links to all the available supplier - * device tree nodes even when attempts to create a link to one or more - * suppliers fail. - */ -static int of_link_property(struct device_node *con_np, const char *prop_name) -{ - struct device_node *phandle; - const struct supplier_bindings *s = of_supplier_bindings; - unsigned int i = 0; - bool matched = false; - - /* Do not stop at first failed link, link all available suppliers. */ - while (!matched && s->parse_prop) { - if (s->optional && !fw_devlink_is_strict()) { - s++; - continue; - } - - while ((phandle = s->parse_prop(con_np, prop_name, i))) { -<<<<<<< -======= - struct device_node *con_dev_np; - - con_dev_np = s->node_not_dev - ? of_get_compat_node_parent(con_np) - : of_node_get(con_np); ->>>>>>> - matched = true; - i++; - of_link_to_phandle(con_np, phandle); - of_node_put(phandle); - } - s++; - } - return 0; -} - -static int of_fwnode_add_links(struct fwnode_handle *fwnode) -{ - struct property *p; - struct device_node *con_np = to_of_node(fwnode); - - if (IS_ENABLED(CONFIG_X86)) - return 0; - - if (!con_np) - return -EINVAL; - - for_each_property_of_node(con_np, p) - of_link_property(con_np, p->name); - - return 0; -} - -const struct fwnode_operations of_fwnode_ops = { - .get = of_fwnode_get, - .put = of_fwnode_put, - .device_is_available = of_fwnode_device_is_available, - .device_get_match_data = of_fwnode_device_get_match_data, - .property_present = of_fwnode_property_present, - .property_read_int_array = of_fwnode_property_read_int_array, - .property_read_string_array = of_fwnode_property_read_string_array, - .get_name = of_fwnode_get_name, - .get_name_prefix = of_fwnode_get_name_prefix, - .get_parent = of_fwnode_get_parent, - .get_next_child_node = of_fwnode_get_next_child_node, - .get_named_child_node = of_fwnode_get_named_child_node, - .get_reference_args = of_fwnode_get_reference_args, - .graph_get_next_endpoint = of_fwnode_graph_get_next_endpoint, - .graph_get_remote_endpoint = of_fwnode_graph_get_remote_endpoint, - .graph_get_port_parent = of_fwnode_graph_get_port_parent, - .graph_parse_endpoint = of_fwnode_graph_parse_endpoint, - .add_links = of_fwnode_add_links, -}; -EXPORT_SYMBOL_GPL(of_fwnode_ops); diff --git a/rr-cache/a82e5fbaccd86e1578210a46632d6112af4146ea/preimage b/rr-cache/a82e5fbaccd86e1578210a46632d6112af4146ea/preimage deleted file mode 100644 index 8649027..0000000 --- a/rr-cache/a82e5fbaccd86e1578210a46632d6112af4146ea/preimage +++ /dev/null @@ -1,556 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * - */ - -#ifndef _MHI_INT_H -#define _MHI_INT_H - -#include "../common.h" - -extern struct bus_type mhi_bus_type; - -/* MHI registers */ -<<<<<<< -#define MHIREGLEN 0x0 -#define MHIVER 0x8 -#define MHICFG 0x10 -#define CHDBOFF 0x18 -#define ERDBOFF 0x20 -#define BHIOFF 0x28 -#define BHIEOFF 0x2c -#define DEBUGOFF 0x30 -#define MHICTRL 0x38 -#define MHISTATUS 0x48 -#define CCABAP_LOWER 0x58 -#define CCABAP_HIGHER 0x5c -#define ECABAP_LOWER 0x60 -#define ECABAP_HIGHER 0x64 -#define CRCBAP_LOWER 0x68 -#define CRCBAP_HIGHER 0x6c -#define CRDB_LOWER 0x70 -#define CRDB_HIGHER 0x74 -#define MHICTRLBASE_LOWER 0x80 -#define MHICTRLBASE_HIGHER 0x84 -#define MHICTRLLIMIT_LOWER 0x88 -#define MHICTRLLIMIT_HIGHER 0x8c -#define MHIDATABASE_LOWER 0x98 -#define MHIDATABASE_HIGHER 0x9c -#define MHIDATALIMIT_LOWER 0xa0 -#define MHIDATALIMIT_HIGHER 0xa4 -======= -#define MHIREGLEN REG_MHIREGLEN -#define MHIVER REG_MHIVER -#define MHICFG REG_MHICFG -#define CHDBOFF REG_CHDBOFF -#define ERDBOFF REG_ERDBOFF -#define BHIOFF REG_BHIOFF -#define BHIEOFF REG_BHIEOFF -#define DEBUGOFF REG_DEBUGOFF -#define MHICTRL REG_MHICTRL -#define MHISTATUS REG_MHISTATUS -#define CCABAP_LOWER REG_CCABAP_LOWER -#define CCABAP_HIGHER REG_CCABAP_HIGHER -#define ECABAP_LOWER REG_ECABAP_LOWER -#define ECABAP_HIGHER REG_ECABAP_HIGHER -#define CRCBAP_LOWER REG_CRCBAP_LOWER -#define CRCBAP_HIGHER REG_CRCBAP_HIGHER -#define CRDB_LOWER REG_CRDB_LOWER -#define CRDB_HIGHER REG_CRDB_HIGHER -#define MHICTRLBASE_LOWER REG_MHICTRLBASE_LOWER -#define MHICTRLBASE_HIGHER REG_MHICTRLBASE_HIGHER -#define MHICTRLLIMIT_LOWER REG_MHICTRLLIMIT_LOWER -#define MHICTRLLIMIT_HIGHER REG_MHICTRLLIMIT_HIGHER -#define MHIDATABASE_LOWER REG_MHIDATABASE_LOWER -#define MHIDATABASE_HIGHER REG_MHIDATABASE_HIGHER -#define MHIDATALIMIT_LOWER REG_MHIDATALIMIT_LOWER -#define MHIDATALIMIT_HIGHER REG_MHIDATALIMIT_HIGHER ->>>>>>> - -/* Host request register */ -#define MHI_SOC_RESET_REQ_OFFSET 0xb0 -#define MHI_SOC_RESET_REQ BIT(0) - -<<<<<<< -/* MHI BHI offfsets */ -#define BHI_BHIVERSION_MINOR 0x00 -#define BHI_BHIVERSION_MAJOR 0x04 -#define BHI_IMGADDR_LOW 0x08 -#define BHI_IMGADDR_HIGH 0x0c -#define BHI_IMGSIZE 0x10 -#define BHI_RSVD1 0x14 -#define BHI_IMGTXDB 0x18 -#define BHI_TXDB_SEQNUM_BMSK GENMASK(29, 0) -#define BHI_TXDB_SEQNUM_SHFT 0 -#define BHI_RSVD2 0x1c -#define BHI_INTVEC 0x20 -#define BHI_RSVD3 0x24 -#define BHI_EXECENV 0x28 -#define BHI_STATUS 0x2c -#define BHI_ERRCODE 0x30 -#define BHI_ERRDBG1 0x34 -#define BHI_ERRDBG2 0x38 -#define BHI_ERRDBG3 0x3c -#define BHI_SERIALNU 0x40 -#define BHI_SBLANTIROLLVER 0x44 -#define BHI_NUMSEG 0x48 -#define BHI_MSMHWID(n) (0x4c + (0x4 * (n))) -#define BHI_OEMPKHASH(n) (0x64 + (0x4 * (n))) -#define BHI_RSVD5 0xc4 -#define BHI_STATUS_MASK GENMASK(31, 30) -#define BHI_STATUS_SHIFT 30 -#define BHI_STATUS_ERROR 3 -#define BHI_STATUS_SUCCESS 2 -#define BHI_STATUS_RESET 0 - -/* MHI BHIE offsets */ -#define BHIE_MSMSOCID_OFFS 0x0000 -#define BHIE_TXVECADDR_LOW_OFFS 0x002c -#define BHIE_TXVECADDR_HIGH_OFFS 0x0030 -#define BHIE_TXVECSIZE_OFFS 0x0034 -#define BHIE_TXVECDB_OFFS 0x003c -#define BHIE_TXVECDB_SEQNUM_BMSK GENMASK(29, 0) -#define BHIE_TXVECDB_SEQNUM_SHFT 0 -#define BHIE_TXVECSTATUS_OFFS 0x0044 -#define BHIE_TXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0) -#define BHIE_TXVECSTATUS_SEQNUM_SHFT 0 -#define BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30) -#define BHIE_TXVECSTATUS_STATUS_SHFT 30 -#define BHIE_TXVECSTATUS_STATUS_RESET 0x00 -#define BHIE_TXVECSTATUS_STATUS_XFER_COMPL 0x02 -#define BHIE_TXVECSTATUS_STATUS_ERROR 0x03 -#define BHIE_RXVECADDR_LOW_OFFS 0x0060 -#define BHIE_RXVECADDR_HIGH_OFFS 0x0064 -#define BHIE_RXVECSIZE_OFFS 0x0068 -#define BHIE_RXVECDB_OFFS 0x0070 -#define BHIE_RXVECDB_SEQNUM_BMSK GENMASK(29, 0) -#define BHIE_RXVECDB_SEQNUM_SHFT 0 -#define BHIE_RXVECSTATUS_OFFS 0x0078 -#define BHIE_RXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0) -#define BHIE_RXVECSTATUS_SEQNUM_SHFT 0 -#define BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30) -#define BHIE_RXVECSTATUS_STATUS_SHFT 30 -#define BHIE_RXVECSTATUS_STATUS_RESET 0x00 -#define BHIE_RXVECSTATUS_STATUS_XFER_COMPL 0x02 -#define BHIE_RXVECSTATUS_STATUS_ERROR 0x03 - -#define SOC_HW_VERSION_OFFS 0x224 -#define SOC_HW_VERSION_FAM_NUM_BMSK GENMASK(31, 28) -#define SOC_HW_VERSION_FAM_NUM_SHFT 28 -#define SOC_HW_VERSION_DEV_NUM_BMSK GENMASK(27, 16) -#define SOC_HW_VERSION_DEV_NUM_SHFT 16 -#define SOC_HW_VERSION_MAJOR_VER_BMSK GENMASK(15, 8) -#define SOC_HW_VERSION_MAJOR_VER_SHFT 8 -#define SOC_HW_VERSION_MINOR_VER_BMSK GENMASK(7, 0) -#define SOC_HW_VERSION_MINOR_VER_SHFT 0 -======= -/* MHI BHI registers */ -#define BHI_BHIVERSION_MINOR REG_BHI_BHIVERSION_MINOR -#define BHI_BHIVERSION_MAJOR REG_BHI_BHIVERSION_MAJOR -#define BHI_IMGADDR_LOW REG_BHI_IMGADDR_LOW -#define BHI_IMGADDR_HIGH REG_BHI_IMGADDR_HIGH -#define BHI_IMGSIZE REG_BHI_IMGSIZE -#define BHI_RSVD1 REG_BHI_RSVD1 -#define BHI_IMGTXDB REG_BHI_IMGTXDB -#define BHI_RSVD2 REG_BHI_RSVD2 -#define BHI_INTVEC REG_BHI_INTVEC -#define BHI_RSVD3 REG_BHI_RSVD3 -#define BHI_EXECENV REG_BHI_EXECENV -#define BHI_STATUS REG_BHI_STATUS -#define BHI_ERRCODE REG_BHI_ERRCODE -#define BHI_ERRDBG1 REG_BHI_ERRDBG1 -#define BHI_ERRDBG2 REG_BHI_ERRDBG2 -#define BHI_ERRDBG3 REG_BHI_ERRDBG3 -#define BHI_SERIALNU REG_BHI_SERIALNU -#define BHI_SBLANTIROLLVER REG_BHI_SBLANTIROLLVER -#define BHI_NUMSEG REG_BHI_NUMSEG -#define BHI_MSMHWID(n) REG_BHI_MSMHWID(n) -#define BHI_OEMPKHASH(n) REG_BHI_OEMPKHASH(n) -#define BHI_RSVD5 REG_BHI_RSVD5 - -/* MHI BHIE registers */ -#define BHIE_MSMSOCID_OFFS REG_BHIE_MSMSOCID_OFFS -#define BHIE_TXVECADDR_LOW_OFFS REG_BHIE_TXVECADDR_LOW_OFFS -#define BHIE_TXVECADDR_HIGH_OFFS REG_BHIE_TXVECADDR_HIGH_OFFS -#define BHIE_TXVECSIZE_OFFS REG_BHIE_TXVECSIZE_OFFS -#define BHIE_TXVECDB_OFFS REG_BHIE_TXVECDB_OFFS -#define BHIE_TXVECSTATUS_OFFS REG_BHIE_TXVECSTATUS_OFFS -#define BHIE_RXVECADDR_LOW_OFFS REG_BHIE_RXVECADDR_LOW_OFFS -#define BHIE_RXVECADDR_HIGH_OFFS REG_BHIE_RXVECADDR_HIGH_OFFS -#define BHIE_RXVECSIZE_OFFS REG_BHIE_RXVECSIZE_OFFS -#define BHIE_RXVECDB_OFFS REG_BHIE_RXVECDB_OFFS -#define BHIE_RXVECSTATUS_OFFS REG_BHIE_RXVECSTATUS_OFFS - -#define SOC_HW_VERSION_OFFS 0x224 -#define SOC_HW_VERSION_FAM_NUM_BMSK GENMASK(31, 28) -#define SOC_HW_VERSION_DEV_NUM_BMSK GENMASK(27, 16) -#define SOC_HW_VERSION_MAJOR_VER_BMSK GENMASK(15, 8) -#define SOC_HW_VERSION_MINOR_VER_BMSK GENMASK(7, 0) ->>>>>>> - -struct mhi_ctxt { - struct mhi_event_ctxt *er_ctxt; - struct mhi_chan_ctxt *chan_ctxt; - struct mhi_cmd_ctxt *cmd_ctxt; - dma_addr_t er_ctxt_addr; - dma_addr_t chan_ctxt_addr; - dma_addr_t cmd_ctxt_addr; -}; - -struct mhi_tre { - __le64 ptr; - __le32 dword[2]; -}; - -struct bhi_vec_entry { - u64 dma_addr; - u64 size; -}; - -enum mhi_ch_state_type { - MHI_CH_STATE_TYPE_RESET, - MHI_CH_STATE_TYPE_STOP, - MHI_CH_STATE_TYPE_START, - MHI_CH_STATE_TYPE_MAX, -}; - -extern const char * const mhi_ch_state_type_str[MHI_CH_STATE_TYPE_MAX]; -#define TO_CH_STATE_TYPE_STR(state) (((state) >= MHI_CH_STATE_TYPE_MAX) ? \ - "INVALID_STATE" : \ - mhi_ch_state_type_str[(state)]) - -#define MHI_INVALID_BRSTMODE(mode) (mode != MHI_DB_BRST_DISABLE && \ - mode != MHI_DB_BRST_ENABLE) - -extern const char * const mhi_ee_str[MHI_EE_MAX]; -#define TO_MHI_EXEC_STR(ee) (((ee) >= MHI_EE_MAX) ? \ - "INVALID_EE" : mhi_ee_str[ee]) - -#define MHI_IN_PBL(ee) (ee == MHI_EE_PBL || ee == MHI_EE_PTHRU || \ - ee == MHI_EE_EDL) -#define MHI_POWER_UP_CAPABLE(ee) (MHI_IN_PBL(ee) || ee == MHI_EE_AMSS) -#define MHI_FW_LOAD_CAPABLE(ee) (ee == MHI_EE_PBL || ee == MHI_EE_EDL) -#define MHI_IN_MISSION_MODE(ee) (ee == MHI_EE_AMSS || ee == MHI_EE_WFW || \ - ee == MHI_EE_FP) - -enum dev_st_transition { - DEV_ST_TRANSITION_PBL, - DEV_ST_TRANSITION_READY, - DEV_ST_TRANSITION_SBL, - DEV_ST_TRANSITION_MISSION_MODE, - DEV_ST_TRANSITION_FP, - DEV_ST_TRANSITION_SYS_ERR, - DEV_ST_TRANSITION_DISABLE, - DEV_ST_TRANSITION_MAX, -}; - -extern const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX]; -#define TO_DEV_STATE_TRANS_STR(state) (((state) >= DEV_ST_TRANSITION_MAX) ? \ - "INVALID_STATE" : dev_state_tran_str[state]) - -/* internal power states */ -enum mhi_pm_state { - MHI_PM_STATE_DISABLE, - MHI_PM_STATE_POR, - MHI_PM_STATE_M0, - MHI_PM_STATE_M2, - MHI_PM_STATE_M3_ENTER, - MHI_PM_STATE_M3, - MHI_PM_STATE_M3_EXIT, - MHI_PM_STATE_FW_DL_ERR, - MHI_PM_STATE_SYS_ERR_DETECT, - MHI_PM_STATE_SYS_ERR_PROCESS, - MHI_PM_STATE_SHUTDOWN_PROCESS, - MHI_PM_STATE_LD_ERR_FATAL_DETECT, - MHI_PM_STATE_MAX -}; - -#define MHI_PM_DISABLE BIT(0) -#define MHI_PM_POR BIT(1) -#define MHI_PM_M0 BIT(2) -#define MHI_PM_M2 BIT(3) -#define MHI_PM_M3_ENTER BIT(4) -#define MHI_PM_M3 BIT(5) -#define MHI_PM_M3_EXIT BIT(6) -/* firmware download failure state */ -#define MHI_PM_FW_DL_ERR BIT(7) -#define MHI_PM_SYS_ERR_DETECT BIT(8) -#define MHI_PM_SYS_ERR_PROCESS BIT(9) -#define MHI_PM_SHUTDOWN_PROCESS BIT(10) -/* link not accessible */ -#define MHI_PM_LD_ERR_FATAL_DETECT BIT(11) - -#define MHI_REG_ACCESS_VALID(pm_state) ((pm_state & (MHI_PM_POR | MHI_PM_M0 | \ - MHI_PM_M2 | MHI_PM_M3_ENTER | MHI_PM_M3_EXIT | \ - MHI_PM_SYS_ERR_DETECT | MHI_PM_SYS_ERR_PROCESS | \ - MHI_PM_SHUTDOWN_PROCESS | MHI_PM_FW_DL_ERR))) -#define MHI_PM_IN_ERROR_STATE(pm_state) (pm_state >= MHI_PM_FW_DL_ERR) -#define MHI_PM_IN_FATAL_STATE(pm_state) (pm_state == MHI_PM_LD_ERR_FATAL_DETECT) -#define MHI_DB_ACCESS_VALID(mhi_cntrl) (mhi_cntrl->pm_state & \ - mhi_cntrl->db_access) -#define MHI_WAKE_DB_CLEAR_VALID(pm_state) (pm_state & (MHI_PM_M0 | \ - MHI_PM_M2 | MHI_PM_M3_EXIT)) -#define MHI_WAKE_DB_SET_VALID(pm_state) (pm_state & MHI_PM_M2) -#define MHI_WAKE_DB_FORCE_SET_VALID(pm_state) MHI_WAKE_DB_CLEAR_VALID(pm_state) -#define MHI_EVENT_ACCESS_INVALID(pm_state) (pm_state == MHI_PM_DISABLE || \ - MHI_PM_IN_ERROR_STATE(pm_state)) -#define MHI_PM_IN_SUSPEND_STATE(pm_state) (pm_state & \ - (MHI_PM_M3_ENTER | MHI_PM_M3)) - -#define NR_OF_CMD_RINGS 1 -#define CMD_EL_PER_RING 128 -#define PRIMARY_CMD_RING 0 -#define MHI_DEV_WAKE_DB 127 -#define MHI_MAX_MTU 0xffff -#define MHI_RANDOM_U32_NONZERO(bmsk) (prandom_u32_max(bmsk) + 1) - -enum mhi_er_type { - MHI_ER_TYPE_INVALID = 0x0, - MHI_ER_TYPE_VALID = 0x1, -}; - -struct db_cfg { - bool reset_req; - bool db_mode; - u32 pollcfg; - enum mhi_db_brst_mode brstmode; - dma_addr_t db_val; - void (*process_db)(struct mhi_controller *mhi_cntrl, - struct db_cfg *db_cfg, void __iomem *io_addr, - dma_addr_t db_val); -}; - -struct mhi_pm_transitions { - enum mhi_pm_state from_state; - u32 to_states; -}; - -struct state_transition { - struct list_head node; - enum dev_st_transition state; -}; - -struct mhi_ring { - dma_addr_t dma_handle; - dma_addr_t iommu_base; - __le64 *ctxt_wp; /* point to ctxt wp */ - void *pre_aligned; - void *base; - void *rp; - void *wp; - size_t el_size; - size_t len; - size_t elements; - size_t alloc_size; - void __iomem *db_addr; -}; - -struct mhi_cmd { - struct mhi_ring ring; - spinlock_t lock; -}; - -struct mhi_buf_info { - void *v_addr; - void *bb_addr; - void *wp; - void *cb_buf; - dma_addr_t p_addr; - size_t len; - enum dma_data_direction dir; - bool used; /* Indicates whether the buffer is used or not */ - bool pre_mapped; /* Already pre-mapped by client */ -}; - -struct mhi_event { - struct mhi_controller *mhi_cntrl; - struct mhi_chan *mhi_chan; /* dedicated to channel */ - u32 er_index; - u32 intmod; - u32 irq; - int chan; /* this event ring is dedicated to a channel (optional) */ - u32 priority; - enum mhi_er_data_type data_type; - struct mhi_ring ring; - struct db_cfg db_cfg; - struct tasklet_struct task; - spinlock_t lock; - int (*process_event)(struct mhi_controller *mhi_cntrl, - struct mhi_event *mhi_event, - u32 event_quota); - bool hw_ring; - bool cl_manage; - bool offload_ev; /* managed by a device driver */ -}; - -struct mhi_chan { - const char *name; - /* - * Important: When consuming, increment tre_ring first and when - * releasing, decrement buf_ring first. If tre_ring has space, buf_ring - * is guranteed to have space so we do not need to check both rings. - */ - struct mhi_ring buf_ring; - struct mhi_ring tre_ring; - u32 chan; - u32 er_index; - u32 intmod; - enum mhi_ch_type type; - enum dma_data_direction dir; - struct db_cfg db_cfg; - enum mhi_ch_ee_mask ee_mask; - enum mhi_ch_state ch_state; - enum mhi_ev_ccs ccs; - struct mhi_device *mhi_dev; - void (*xfer_cb)(struct mhi_device *mhi_dev, struct mhi_result *result); - struct mutex mutex; - struct completion completion; - rwlock_t lock; - struct list_head node; - bool lpm_notify; - bool configured; - bool offload_ch; - bool pre_alloc; - bool wake_capable; -}; - -/* Default MHI timeout */ -#define MHI_TIMEOUT_MS (1000) - -/* debugfs related functions */ -#ifdef CONFIG_MHI_BUS_DEBUG -void mhi_create_debugfs(struct mhi_controller *mhi_cntrl); -void mhi_destroy_debugfs(struct mhi_controller *mhi_cntrl); -void mhi_debugfs_init(void); -void mhi_debugfs_exit(void); -#else -static inline void mhi_create_debugfs(struct mhi_controller *mhi_cntrl) -{ -} - -static inline void mhi_destroy_debugfs(struct mhi_controller *mhi_cntrl) -{ -} - -static inline void mhi_debugfs_init(void) -{ -} - -static inline void mhi_debugfs_exit(void) -{ -} -#endif - -struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl); - -int mhi_destroy_device(struct device *dev, void *data); -void mhi_create_devices(struct mhi_controller *mhi_cntrl); - -int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, - struct image_info **image_info, size_t alloc_size); -void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl, - struct image_info *image_info); - -/* Power management APIs */ -enum mhi_pm_state __must_check mhi_tryset_pm_state( - struct mhi_controller *mhi_cntrl, - enum mhi_pm_state state); -const char *to_mhi_pm_state_str(enum mhi_pm_state state); -int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl, - enum dev_st_transition state); -void mhi_pm_st_worker(struct work_struct *work); -void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl); -int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl); -int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl); -void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl); -int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl); -int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl); -int mhi_send_cmd(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, - enum mhi_cmd_type cmd); -int mhi_download_amss_image(struct mhi_controller *mhi_cntrl); -static inline bool mhi_is_active(struct mhi_controller *mhi_cntrl) -{ - return (mhi_cntrl->dev_state >= MHI_STATE_M0 && - mhi_cntrl->dev_state <= MHI_STATE_M3_FAST); -} - -static inline void mhi_trigger_resume(struct mhi_controller *mhi_cntrl) -{ - pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0); - mhi_cntrl->runtime_get(mhi_cntrl); - mhi_cntrl->runtime_put(mhi_cntrl); -} - -/* Register access methods */ -void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, struct db_cfg *db_cfg, - void __iomem *db_addr, dma_addr_t db_val); -void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl, - struct db_cfg *db_mode, void __iomem *db_addr, - dma_addr_t db_val); -int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl, - void __iomem *base, u32 offset, u32 *out); -int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl, - void __iomem *base, u32 offset, u32 mask, - u32 *out); -int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl, - void __iomem *base, u32 offset, u32 mask, - u32 val, u32 delayus); -void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base, - u32 offset, u32 val); -void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base, - u32 offset, u32 mask, u32 val); -void mhi_ring_er_db(struct mhi_event *mhi_event); -void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr, - dma_addr_t db_val); -void mhi_ring_cmd_db(struct mhi_controller *mhi_cntrl, struct mhi_cmd *mhi_cmd); -void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl, - struct mhi_chan *mhi_chan); - -/* Initialization methods */ -int mhi_init_mmio(struct mhi_controller *mhi_cntrl); -int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl); -void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl); -int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl); -void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl); -void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, - struct image_info *img_info); -void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl); - -/* Automatically allocate and queue inbound buffers */ -#define MHI_CH_INBOUND_ALLOC_BUFS BIT(0) -int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, - struct mhi_chan *mhi_chan, unsigned int flags); - -int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl, - struct mhi_chan *mhi_chan); -void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl, - struct mhi_chan *mhi_chan); -void mhi_reset_chan(struct mhi_controller *mhi_cntrl, - struct mhi_chan *mhi_chan); - -/* Event processing methods */ -void mhi_ctrl_ev_task(unsigned long data); -void mhi_ev_task(unsigned long data); -int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl, - struct mhi_event *mhi_event, u32 event_quota); -int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, - struct mhi_event *mhi_event, u32 event_quota); - -/* ISR handlers */ -irqreturn_t mhi_irq_handler(int irq_number, void *dev); -irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev); -irqreturn_t mhi_intvec_handler(int irq_number, void *dev); - -int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, - struct mhi_buf_info *info, enum mhi_flags flags); -int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, - struct mhi_buf_info *buf_info); -int mhi_map_single_use_bb(struct mhi_controller *mhi_cntrl, - struct mhi_buf_info *buf_info); -void mhi_unmap_single_no_bb(struct mhi_controller *mhi_cntrl, - struct mhi_buf_info *buf_info); -void mhi_unmap_single_use_bb(struct mhi_controller *mhi_cntrl, - struct mhi_buf_info *buf_info); - -#endif /* _MHI_INT_H */ diff --git a/rr-cache/b012cdb52162daf746bef83d824b648ac42cabc0/thisimage b/rr-cache/b012cdb52162daf746bef83d824b648ac42cabc0/thisimage index becfab5..750d913 100644 --- a/rr-cache/b012cdb52162daf746bef83d824b648ac42cabc0/thisimage +++ b/rr-cache/b012cdb52162daf746bef83d824b648ac42cabc0/thisimage @@ -1267,7 +1267,6 @@ CONFIG_INTERCONNECT_QCOM_OSM_L3=m CONFIG_INTERCONNECT_QCOM_QCS404=m CONFIG_INTERCONNECT_QCOM_SC7180=m CONFIG_INTERCONNECT_QCOM_SC7280=y -CONFIG_INTERCONNECT_QCOM_QCS404=m CONFIG_INTERCONNECT_QCOM_SDM845=y CONFIG_INTERCONNECT_QCOM_SM8150=m CONFIG_INTERCONNECT_QCOM_SM8250=m diff --git a/rr-cache/b42f7c232a68fe3a2a83a0d9b5bf92a639ec1865/preimage b/rr-cache/b42f7c232a68fe3a2a83a0d9b5bf92a639ec1865/preimage deleted file mode 100644 index e0641cd..0000000 --- a/rr-cache/b42f7c232a68fe3a2a83a0d9b5bf92a639ec1865/preimage +++ /dev/null @@ -1,2245 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2011-2018, The Linux Foundation. All rights reserved. -// Copyright (c) 2018, Linaro Limited - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define ADSP_DOMAIN_ID (0) -#define MDSP_DOMAIN_ID (1) -#define SDSP_DOMAIN_ID (2) -#define CDSP_DOMAIN_ID (3) -#define FASTRPC_DEV_MAX 4 /* adsp, mdsp, slpi, cdsp*/ -#define FASTRPC_MAX_SESSIONS 13 /*12 compute, 1 cpz*/ -#define FASTRPC_MAX_VMIDS 16 -#define FASTRPC_ALIGN 128 -#define FASTRPC_MAX_FDLIST 16 -#define FASTRPC_MAX_CRCLIST 64 -#define FASTRPC_PHYS(p) ((p) & 0xffffffff) -#define FASTRPC_CTX_MAX (256) -#define FASTRPC_INIT_HANDLE 1 -#define FASTRPC_DSP_UTILITIES_HANDLE 2 -#define FASTRPC_CTXID_MASK (0xFF0) -#define INIT_FILELEN_MAX (2 * 1024 * 1024) -#define FASTRPC_DEVICE_NAME "fastrpc" -#define ADSP_MMAP_ADD_PAGES 0x1000 -#define DSP_UNSUPPORTED_API (0x80000414) -/* MAX NUMBER of DSP ATTRIBUTES SUPPORTED */ -#define FASTRPC_MAX_DSP_ATTRIBUTES (256) -#define FASTRPC_MAX_DSP_ATTRIBUTES_LEN (sizeof(u32) * FASTRPC_MAX_DSP_ATTRIBUTES) - -/* Retrives number of input buffers from the scalars parameter */ -#define REMOTE_SCALARS_INBUFS(sc) (((sc) >> 16) & 0x0ff) - -/* Retrives number of output buffers from the scalars parameter */ -#define REMOTE_SCALARS_OUTBUFS(sc) (((sc) >> 8) & 0x0ff) - -/* Retrives number of input handles from the scalars parameter */ -#define REMOTE_SCALARS_INHANDLES(sc) (((sc) >> 4) & 0x0f) - -/* Retrives number of output handles from the scalars parameter */ -#define REMOTE_SCALARS_OUTHANDLES(sc) ((sc) & 0x0f) - -#define REMOTE_SCALARS_LENGTH(sc) (REMOTE_SCALARS_INBUFS(sc) + \ - REMOTE_SCALARS_OUTBUFS(sc) + \ - REMOTE_SCALARS_INHANDLES(sc)+ \ - REMOTE_SCALARS_OUTHANDLES(sc)) -#define FASTRPC_BUILD_SCALARS(attr, method, in, out, oin, oout) \ - (((attr & 0x07) << 29) | \ - ((method & 0x1f) << 24) | \ - ((in & 0xff) << 16) | \ - ((out & 0xff) << 8) | \ - ((oin & 0x0f) << 4) | \ - (oout & 0x0f)) - -#define FASTRPC_SCALARS(method, in, out) \ - FASTRPC_BUILD_SCALARS(0, method, in, out, 0, 0) - -#define FASTRPC_CREATE_PROCESS_NARGS 6 -/* Remote Method id table */ -#define FASTRPC_RMID_INIT_ATTACH 0 -#define FASTRPC_RMID_INIT_RELEASE 1 -#define FASTRPC_RMID_INIT_MMAP 4 -#define FASTRPC_RMID_INIT_MUNMAP 5 -#define FASTRPC_RMID_INIT_CREATE 6 -#define FASTRPC_RMID_INIT_CREATE_ATTR 7 -#define FASTRPC_RMID_INIT_CREATE_STATIC 8 -#define FASTRPC_RMID_INIT_MEM_MAP 10 -#define FASTRPC_RMID_INIT_MEM_UNMAP 11 - -/* Protection Domain(PD) ids */ -#define AUDIO_PD (0) /* also GUEST_OS PD? */ -#define USER_PD (1) -#define SENSORS_PD (2) - -#define miscdev_to_fdevice(d) container_of(d, struct fastrpc_device, miscdev) - -static const char *domains[FASTRPC_DEV_MAX] = { "adsp", "mdsp", - "sdsp", "cdsp"}; -struct fastrpc_phy_page { - u64 addr; /* physical address */ - u64 size; /* size of contiguous region */ -}; - -struct fastrpc_invoke_buf { - u32 num; /* number of contiguous regions */ - u32 pgidx; /* index to start of contiguous region */ -}; - -struct fastrpc_remote_dmahandle { - s32 fd; /* dma handle fd */ - u32 offset; /* dma handle offset */ - u32 len; /* dma handle length */ -}; - -struct fastrpc_remote_buf { - u64 pv; /* buffer pointer */ - u64 len; /* length of buffer */ -}; - -union fastrpc_remote_arg { - struct fastrpc_remote_buf buf; - struct fastrpc_remote_dmahandle dma; -}; - -struct fastrpc_mmap_rsp_msg { - u64 vaddr; -}; - -struct fastrpc_mmap_req_msg { - s32 pgid; - u32 flags; - u64 vaddr; - s32 num; -}; - -struct fastrpc_mem_map_req_msg { - s32 pgid; - s32 fd; - s32 offset; - u32 flags; - u64 vaddrin; - s32 num; - s32 data_len; -}; - -struct fastrpc_munmap_req_msg { - s32 pgid; - u64 vaddr; - u64 size; -}; - -struct fastrpc_mem_unmap_req_msg { - s32 pgid; - s32 fd; - u64 vaddrin; - u64 len; -}; - -struct fastrpc_msg { - int pid; /* process group id */ - int tid; /* thread id */ - u64 ctx; /* invoke caller context */ - u32 handle; /* handle to invoke */ - u32 sc; /* scalars structure describing the data */ - u64 addr; /* physical address */ - u64 size; /* size of contiguous region */ -}; - -struct fastrpc_invoke_rsp { - u64 ctx; /* invoke caller context */ - int retval; /* invoke return value */ -}; - -struct fastrpc_buf_overlap { - u64 start; - u64 end; - int raix; - u64 mstart; - u64 mend; - u64 offset; -}; - -struct fastrpc_buf { - struct fastrpc_user *fl; - struct dma_buf *dmabuf; - struct device *dev; - void *virt; - u64 phys; - u64 size; - /* Lock for dma buf attachments */ - struct mutex lock; - struct list_head attachments; - /* mmap support */ - struct list_head node; /* list of user requested mmaps */ - uintptr_t raddr; -}; - -struct fastrpc_dma_buf_attachment { - struct device *dev; - struct sg_table sgt; - struct list_head node; -}; - -struct fastrpc_map { - struct list_head node; - struct fastrpc_user *fl; - int fd; - struct dma_buf *buf; - struct sg_table *table; - struct dma_buf_attachment *attach; - u64 phys; - u64 size; - void *va; - u64 len; - u64 raddr; - u32 attr; - struct kref refcount; -}; - -struct fastrpc_invoke_ctx { - int nscalars; - int nbufs; - int retval; - int pid; - int tgid; - u32 sc; - u32 *crc; - u64 ctxid; - u64 msg_sz; - struct kref refcount; - struct list_head node; /* list of ctxs */ - struct completion work; - struct work_struct put_work; - struct fastrpc_msg msg; - struct fastrpc_user *fl; - union fastrpc_remote_arg *rpra; - struct fastrpc_map **maps; - struct fastrpc_buf *buf; - struct fastrpc_invoke_args *args; - struct fastrpc_buf_overlap *olaps; - struct fastrpc_channel_ctx *cctx; -}; - -struct fastrpc_session_ctx { - struct device *dev; - int sid; - bool used; - bool valid; -}; - -struct fastrpc_channel_ctx { - int domain_id; - int sesscount; - int vmcount; - u32 perms; - struct qcom_scm_vmperm vmperms[FASTRPC_MAX_VMIDS]; - struct rpmsg_device *rpdev; - struct fastrpc_session_ctx session[FASTRPC_MAX_SESSIONS]; - spinlock_t lock; - struct idr ctx_idr; - struct list_head users; - struct kref refcount; - /* Flag if dsp attributes are cached */ - bool valid_attributes; - u32 dsp_attributes[FASTRPC_MAX_DSP_ATTRIBUTES]; - struct fastrpc_device *secure_fdevice; - struct fastrpc_device *fdevice; - bool secure; - bool unsigned_support; -}; - -struct fastrpc_device { - struct fastrpc_channel_ctx *cctx; - struct miscdevice miscdev; - bool secure; -}; - -struct fastrpc_user { - struct list_head user; - struct list_head maps; - struct list_head pending; - struct list_head mmaps; - - struct fastrpc_channel_ctx *cctx; - struct fastrpc_session_ctx *sctx; - struct fastrpc_buf *init_mem; - - int tgid; - int pd; - bool is_secure_dev; - /* Lock for lists */ - spinlock_t lock; - /* lock for allocations */ - struct mutex mutex; -}; - -static void fastrpc_free_map(struct kref *ref) -{ - struct fastrpc_map *map; - - map = container_of(ref, struct fastrpc_map, refcount); - - if (map->table) { - if (map->attr & FASTRPC_ATTR_SECUREMAP) { - struct qcom_scm_vmperm perm; - int err = 0; - - perm.vmid = QCOM_SCM_VMID_HLOS; - perm.perm = QCOM_SCM_PERM_RWX; - err = qcom_scm_assign_mem(map->phys, map->size, - &(map->fl->cctx->vmperms[0].vmid), &perm, 1); - if (err) { - dev_err(map->fl->sctx->dev, "Failed to assign memory phys 0x%llx size 0x%llx err %d", - map->phys, map->size, err); - return; - } - } - dma_buf_unmap_attachment(map->attach, map->table, - DMA_BIDIRECTIONAL); - dma_buf_detach(map->buf, map->attach); - dma_buf_put(map->buf); - } - - kfree(map); -} - -static void fastrpc_map_put(struct fastrpc_map *map) -{ - if (map) - kref_put(&map->refcount, fastrpc_free_map); -} - -static void fastrpc_map_get(struct fastrpc_map *map) -{ - if (map) - kref_get(&map->refcount); -} - - -static int fastrpc_map_lookup(struct fastrpc_user *fl, int fd, - struct fastrpc_map **ppmap) -{ - struct fastrpc_map *map = NULL; - - mutex_lock(&fl->mutex); - list_for_each_entry(map, &fl->maps, node) { - if (map->fd == fd) { - *ppmap = map; - mutex_unlock(&fl->mutex); - return 0; - } - } - mutex_unlock(&fl->mutex); - - return -ENOENT; -} - -static int fastrpc_map_find(struct fastrpc_user *fl, int fd, - struct fastrpc_map **ppmap) -{ - int ret = fastrpc_map_lookup(fl, fd, ppmap); - - if (!ret) - fastrpc_map_get(*ppmap); - - return ret; -} - -static void fastrpc_buf_free(struct fastrpc_buf *buf) -{ - dma_free_coherent(buf->dev, buf->size, buf->virt, - FASTRPC_PHYS(buf->phys)); - kfree(buf); -} - -static int fastrpc_buf_alloc(struct fastrpc_user *fl, struct device *dev, - u64 size, struct fastrpc_buf **obuf) -{ - struct fastrpc_buf *buf; - - buf = kzalloc(sizeof(*buf), GFP_KERNEL); - if (!buf) - return -ENOMEM; - - INIT_LIST_HEAD(&buf->attachments); - INIT_LIST_HEAD(&buf->node); - mutex_init(&buf->lock); - - buf->fl = fl; - buf->virt = NULL; - buf->phys = 0; - buf->size = size; - buf->dev = dev; - buf->raddr = 0; - - buf->virt = dma_alloc_coherent(dev, buf->size, (dma_addr_t *)&buf->phys, - GFP_KERNEL); - if (!buf->virt) { - mutex_destroy(&buf->lock); - kfree(buf); - return -ENOMEM; - } - - if (fl->sctx && fl->sctx->sid) - buf->phys += ((u64)fl->sctx->sid << 32); - - *obuf = buf; - - return 0; -} - -static void fastrpc_channel_ctx_free(struct kref *ref) -{ - struct fastrpc_channel_ctx *cctx; - - cctx = container_of(ref, struct fastrpc_channel_ctx, refcount); - - kfree(cctx); -} - -static void fastrpc_channel_ctx_get(struct fastrpc_channel_ctx *cctx) -{ - kref_get(&cctx->refcount); -} - -static void fastrpc_channel_ctx_put(struct fastrpc_channel_ctx *cctx) -{ - kref_put(&cctx->refcount, fastrpc_channel_ctx_free); -} - -static void fastrpc_context_free(struct kref *ref) -{ - struct fastrpc_invoke_ctx *ctx; - struct fastrpc_channel_ctx *cctx; - unsigned long flags; - int i; - - ctx = container_of(ref, struct fastrpc_invoke_ctx, refcount); - cctx = ctx->cctx; - - for (i = 0; i < ctx->nbufs; i++) - fastrpc_map_put(ctx->maps[i]); - - if (ctx->buf) - fastrpc_buf_free(ctx->buf); - - spin_lock_irqsave(&cctx->lock, flags); - idr_remove(&cctx->ctx_idr, ctx->ctxid >> 4); - spin_unlock_irqrestore(&cctx->lock, flags); - - kfree(ctx->maps); - kfree(ctx->olaps); - kfree(ctx); - - fastrpc_channel_ctx_put(cctx); -} - -static void fastrpc_context_get(struct fastrpc_invoke_ctx *ctx) -{ - kref_get(&ctx->refcount); -} - -static void fastrpc_context_put(struct fastrpc_invoke_ctx *ctx) -{ - kref_put(&ctx->refcount, fastrpc_context_free); -} - -static void fastrpc_context_put_wq(struct work_struct *work) -{ - struct fastrpc_invoke_ctx *ctx = - container_of(work, struct fastrpc_invoke_ctx, put_work); - - fastrpc_context_put(ctx); -} - -#define CMP(aa, bb) ((aa) == (bb) ? 0 : (aa) < (bb) ? -1 : 1) -static int olaps_cmp(const void *a, const void *b) -{ - struct fastrpc_buf_overlap *pa = (struct fastrpc_buf_overlap *)a; - struct fastrpc_buf_overlap *pb = (struct fastrpc_buf_overlap *)b; - /* sort with lowest starting buffer first */ - int st = CMP(pa->start, pb->start); - /* sort with highest ending buffer first */ - int ed = CMP(pb->end, pa->end); - - return st == 0 ? ed : st; -} - -static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) -{ - u64 max_end = 0; - int i; - - for (i = 0; i < ctx->nbufs; ++i) { - ctx->olaps[i].start = ctx->args[i].ptr; - ctx->olaps[i].end = ctx->olaps[i].start + ctx->args[i].length; - ctx->olaps[i].raix = i; - } - - sort(ctx->olaps, ctx->nbufs, sizeof(*ctx->olaps), olaps_cmp, NULL); - - for (i = 0; i < ctx->nbufs; ++i) { - /* Falling inside previous range */ - if (ctx->olaps[i].start < max_end) { - ctx->olaps[i].mstart = max_end; - ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].offset = max_end - ctx->olaps[i].start; - - if (ctx->olaps[i].end > max_end) { - max_end = ctx->olaps[i].end; - } else { - ctx->olaps[i].mend = 0; - ctx->olaps[i].mstart = 0; - } - - } else { - ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].mstart = ctx->olaps[i].start; - ctx->olaps[i].offset = 0; - max_end = ctx->olaps[i].end; - } - } -} - -static struct fastrpc_invoke_ctx *fastrpc_context_alloc( - struct fastrpc_user *user, u32 kernel, u32 sc, - struct fastrpc_invoke_args *args) -{ - struct fastrpc_channel_ctx *cctx = user->cctx; - struct fastrpc_invoke_ctx *ctx = NULL; - unsigned long flags; - int ret; - - ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return ERR_PTR(-ENOMEM); - - INIT_LIST_HEAD(&ctx->node); - ctx->fl = user; - ctx->nscalars = REMOTE_SCALARS_LENGTH(sc); - ctx->nbufs = REMOTE_SCALARS_INBUFS(sc) + - REMOTE_SCALARS_OUTBUFS(sc); - - if (ctx->nscalars) { - ctx->maps = kcalloc(ctx->nscalars, - sizeof(*ctx->maps), GFP_KERNEL); - if (!ctx->maps) { - kfree(ctx); - return ERR_PTR(-ENOMEM); - } - ctx->olaps = kcalloc(ctx->nscalars, - sizeof(*ctx->olaps), GFP_KERNEL); - if (!ctx->olaps) { - kfree(ctx->maps); - kfree(ctx); - return ERR_PTR(-ENOMEM); - } - ctx->args = args; - fastrpc_get_buff_overlaps(ctx); - } - - /* Released in fastrpc_context_put() */ - fastrpc_channel_ctx_get(cctx); - - ctx->sc = sc; - ctx->retval = -1; - ctx->pid = current->pid; - ctx->tgid = user->tgid; - ctx->cctx = cctx; - init_completion(&ctx->work); - INIT_WORK(&ctx->put_work, fastrpc_context_put_wq); - - spin_lock(&user->lock); - list_add_tail(&ctx->node, &user->pending); - spin_unlock(&user->lock); - - spin_lock_irqsave(&cctx->lock, flags); - ret = idr_alloc_cyclic(&cctx->ctx_idr, ctx, 1, - FASTRPC_CTX_MAX, GFP_ATOMIC); - if (ret < 0) { - spin_unlock_irqrestore(&cctx->lock, flags); - goto err_idr; - } - ctx->ctxid = ret << 4; - spin_unlock_irqrestore(&cctx->lock, flags); - - kref_init(&ctx->refcount); - - return ctx; -err_idr: - spin_lock(&user->lock); - list_del(&ctx->node); - spin_unlock(&user->lock); - fastrpc_channel_ctx_put(cctx); - kfree(ctx->maps); - kfree(ctx->olaps); - kfree(ctx); - - return ERR_PTR(ret); -} - -static struct sg_table * -fastrpc_map_dma_buf(struct dma_buf_attachment *attachment, - enum dma_data_direction dir) -{ - struct fastrpc_dma_buf_attachment *a = attachment->priv; - struct sg_table *table; - int ret; - - table = &a->sgt; - - ret = dma_map_sgtable(attachment->dev, table, dir, 0); - if (ret) - table = ERR_PTR(ret); - return table; -} - -static void fastrpc_unmap_dma_buf(struct dma_buf_attachment *attach, - struct sg_table *table, - enum dma_data_direction dir) -{ - dma_unmap_sgtable(attach->dev, table, dir, 0); -} - -static void fastrpc_release(struct dma_buf *dmabuf) -{ - struct fastrpc_buf *buffer = dmabuf->priv; - - fastrpc_buf_free(buffer); -} - -static int fastrpc_dma_buf_attach(struct dma_buf *dmabuf, - struct dma_buf_attachment *attachment) -{ - struct fastrpc_dma_buf_attachment *a; - struct fastrpc_buf *buffer = dmabuf->priv; - int ret; - - a = kzalloc(sizeof(*a), GFP_KERNEL); - if (!a) - return -ENOMEM; - - ret = dma_get_sgtable(buffer->dev, &a->sgt, buffer->virt, - FASTRPC_PHYS(buffer->phys), buffer->size); - if (ret < 0) { - dev_err(buffer->dev, "failed to get scatterlist from DMA API\n"); - kfree(a); - return -EINVAL; - } - - a->dev = attachment->dev; - INIT_LIST_HEAD(&a->node); - attachment->priv = a; - - mutex_lock(&buffer->lock); - list_add(&a->node, &buffer->attachments); - mutex_unlock(&buffer->lock); - - return 0; -} - -static void fastrpc_dma_buf_detatch(struct dma_buf *dmabuf, - struct dma_buf_attachment *attachment) -{ - struct fastrpc_dma_buf_attachment *a = attachment->priv; - struct fastrpc_buf *buffer = dmabuf->priv; - - mutex_lock(&buffer->lock); - list_del(&a->node); - mutex_unlock(&buffer->lock); - sg_free_table(&a->sgt); - kfree(a); -} - -static int fastrpc_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) -{ - struct fastrpc_buf *buf = dmabuf->priv; - - dma_buf_map_set_vaddr(map, buf->virt); - - return 0; -} - -static int fastrpc_mmap(struct dma_buf *dmabuf, - struct vm_area_struct *vma) -{ - struct fastrpc_buf *buf = dmabuf->priv; - size_t size = vma->vm_end - vma->vm_start; - - return dma_mmap_coherent(buf->dev, vma, buf->virt, - FASTRPC_PHYS(buf->phys), size); -} - -static const struct dma_buf_ops fastrpc_dma_buf_ops = { - .attach = fastrpc_dma_buf_attach, - .detach = fastrpc_dma_buf_detatch, - .map_dma_buf = fastrpc_map_dma_buf, - .unmap_dma_buf = fastrpc_unmap_dma_buf, - .mmap = fastrpc_mmap, - .vmap = fastrpc_vmap, - .release = fastrpc_release, -}; - -static int fastrpc_map_create(struct fastrpc_user *fl, int fd, - u64 len, u32 attr, struct fastrpc_map **ppmap) -{ - struct fastrpc_session_ctx *sess = fl->sctx; - struct fastrpc_map *map = NULL; - int err = 0; - - if (!fastrpc_map_find(fl, fd, ppmap)) - return 0; - - map = kzalloc(sizeof(*map), GFP_KERNEL); - if (!map) - return -ENOMEM; - - INIT_LIST_HEAD(&map->node); - map->fl = fl; - map->fd = fd; - map->buf = dma_buf_get(fd); - if (IS_ERR(map->buf)) { - err = PTR_ERR(map->buf); - goto get_err; - } - - map->attach = dma_buf_attach(map->buf, sess->dev); - if (IS_ERR(map->attach)) { - dev_err(sess->dev, "Failed to attach dmabuf\n"); - err = PTR_ERR(map->attach); - goto attach_err; - } - - map->table = dma_buf_map_attachment(map->attach, DMA_BIDIRECTIONAL); - if (IS_ERR(map->table)) { - err = PTR_ERR(map->table); - goto map_err; - } - - map->phys = sg_dma_address(map->table->sgl); - map->phys += ((u64)fl->sctx->sid << 32); - map->size = len; - map->va = sg_virt(map->table->sgl); - map->len = len; - kref_init(&map->refcount); - - if (attr & FASTRPC_ATTR_SECUREMAP) { - /* - * If subsystem VMIDs are defined in DTSI, then do - * hyp_assign from HLOS to those VM(s) - */ - unsigned int perms = BIT(QCOM_SCM_VMID_HLOS); - - map->attr = attr; - err = qcom_scm_assign_mem(map->phys, (u64)map->size, &perms, - fl->cctx->vmperms, fl->cctx->vmcount); - if (err) { - dev_err(sess->dev, "Failed to assign memory with phys 0x%llx size 0x%llx err %d", - map->phys, map->size, err); - goto map_err; - } - } - spin_lock(&fl->lock); - list_add_tail(&map->node, &fl->maps); - spin_unlock(&fl->lock); - *ppmap = map; - - return 0; - -map_err: - dma_buf_detach(map->buf, map->attach); -attach_err: - dma_buf_put(map->buf); -get_err: - kfree(map); - - return err; -} - -/* - * Fastrpc payload buffer with metadata looks like: - * - * >>>>>> START of METADATA <<<<<<<<< - * +---------------------------------+ - * | Arguments | - * | type:(union fastrpc_remote_arg)| - * | (0 - N) | - * +---------------------------------+ - * | Invoke Buffer list | - * | type:(struct fastrpc_invoke_buf)| - * | (0 - N) | - * +---------------------------------+ - * | Page info list | - * | type:(struct fastrpc_phy_page) | - * | (0 - N) | - * +---------------------------------+ - * | Optional info | - * |(can be specific to SoC/Firmware)| - * +---------------------------------+ - * >>>>>>>> END of METADATA <<<<<<<<< - * +---------------------------------+ - * | Inline ARGS | - * | (0-N) | - * +---------------------------------+ - */ - -static int fastrpc_get_meta_size(struct fastrpc_invoke_ctx *ctx) -{ - int size = 0; - - size = (sizeof(struct fastrpc_remote_buf) + - sizeof(struct fastrpc_invoke_buf) + - sizeof(struct fastrpc_phy_page)) * ctx->nscalars + - sizeof(u64) * FASTRPC_MAX_FDLIST + - sizeof(u32) * FASTRPC_MAX_CRCLIST; - - return size; -} - -static u64 fastrpc_get_payload_size(struct fastrpc_invoke_ctx *ctx, int metalen) -{ - u64 size = 0; - int oix; - - size = ALIGN(metalen, FASTRPC_ALIGN); - for (oix = 0; oix < ctx->nbufs; oix++) { - int i = ctx->olaps[oix].raix; - - if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1) { - - if (ctx->olaps[oix].offset == 0) - size = ALIGN(size, FASTRPC_ALIGN); - - size += (ctx->olaps[oix].mend - ctx->olaps[oix].mstart); - } - } - - return size; -} - -static int fastrpc_create_maps(struct fastrpc_invoke_ctx *ctx) -{ - struct device *dev = ctx->fl->sctx->dev; - int i, err; - - for (i = 0; i < ctx->nscalars; ++i) { - - if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1 || - ctx->args[i].length == 0) - continue; - - err = fastrpc_map_create(ctx->fl, ctx->args[i].fd, - ctx->args[i].length, ctx->args[i].attr, &ctx->maps[i]); - if (err) { - dev_err(dev, "Error Creating map %d\n", err); - return -EINVAL; - } - - } - return 0; -} - -static struct fastrpc_invoke_buf *fastrpc_invoke_buf_start(union fastrpc_remote_arg *pra, int len) -{ - return (struct fastrpc_invoke_buf *)(&pra[len]); -} - -static struct fastrpc_phy_page *fastrpc_phy_page_start(struct fastrpc_invoke_buf *buf, int len) -{ - return (struct fastrpc_phy_page *)(&buf[len]); -} - -static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) -{ - struct device *dev = ctx->fl->sctx->dev; - union fastrpc_remote_arg *rpra; - struct fastrpc_invoke_buf *list; - struct fastrpc_phy_page *pages; - int inbufs, i, oix, err = 0; - u64 len, rlen, pkt_size; - u64 pg_start, pg_end; - uintptr_t args; - int metalen; - - inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); - metalen = fastrpc_get_meta_size(ctx); - pkt_size = fastrpc_get_payload_size(ctx, metalen); - - err = fastrpc_create_maps(ctx); - if (err) - return err; - - ctx->msg_sz = pkt_size; - - err = fastrpc_buf_alloc(ctx->fl, dev, pkt_size, &ctx->buf); - if (err) - return err; - - rpra = ctx->buf->virt; - list = fastrpc_invoke_buf_start(rpra, ctx->nscalars); - pages = fastrpc_phy_page_start(list, ctx->nscalars); - args = (uintptr_t)ctx->buf->virt + metalen; - rlen = pkt_size - metalen; - ctx->rpra = rpra; - - for (oix = 0; oix < ctx->nbufs; ++oix) { - int mlen; - - i = ctx->olaps[oix].raix; - len = ctx->args[i].length; - - rpra[i].buf.pv = 0; - rpra[i].buf.len = len; - list[i].num = len ? 1 : 0; - list[i].pgidx = i; - - if (!len) - continue; - - if (ctx->maps[i]) { - struct vm_area_struct *vma = NULL; - - rpra[i].buf.pv = (u64) ctx->args[i].ptr; - pages[i].addr = ctx->maps[i]->phys; - - mmap_read_lock(current->mm); - vma = find_vma(current->mm, ctx->args[i].ptr); - if (vma) - pages[i].addr += ctx->args[i].ptr - - vma->vm_start; - mmap_read_unlock(current->mm); - - pg_start = (ctx->args[i].ptr & PAGE_MASK) >> PAGE_SHIFT; - pg_end = ((ctx->args[i].ptr + len - 1) & PAGE_MASK) >> - PAGE_SHIFT; - pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - - } else { - - if (ctx->olaps[oix].offset == 0) { - rlen -= ALIGN(args, FASTRPC_ALIGN) - args; - args = ALIGN(args, FASTRPC_ALIGN); - } - - mlen = ctx->olaps[oix].mend - ctx->olaps[oix].mstart; - - if (rlen < mlen) - goto bail; - - rpra[i].buf.pv = args - ctx->olaps[oix].offset; - pages[i].addr = ctx->buf->phys - - ctx->olaps[oix].offset + - (pkt_size - rlen); - pages[i].addr = pages[i].addr & PAGE_MASK; - - pg_start = (args & PAGE_MASK) >> PAGE_SHIFT; - pg_end = ((args + len - 1) & PAGE_MASK) >> PAGE_SHIFT; - pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - args = args + mlen; - rlen -= mlen; - } - - if (i < inbufs && !ctx->maps[i]) { - void *dst = (void *)(uintptr_t)rpra[i].buf.pv; - void *src = (void *)(uintptr_t)ctx->args[i].ptr; - - if (!kernel) { - if (copy_from_user(dst, (void __user *)src, - len)) { - err = -EFAULT; - goto bail; - } - } else { - memcpy(dst, src, len); - } - } - } - - for (i = ctx->nbufs; i < ctx->nscalars; ++i) { - list[i].num = ctx->args[i].length ? 1 : 0; - list[i].pgidx = i; - if (ctx->maps[i]) { - pages[i].addr = ctx->maps[i]->phys; - pages[i].size = ctx->maps[i]->size; - } - rpra[i].dma.fd = ctx->args[i].fd; - rpra[i].dma.len = ctx->args[i].length; - rpra[i].dma.offset = (u64) ctx->args[i].ptr; - } - -bail: - if (err) - dev_err(dev, "Error: get invoke args failed:%d\n", err); - - return err; -} - -static int fastrpc_put_args(struct fastrpc_invoke_ctx *ctx, - u32 kernel) -{ - union fastrpc_remote_arg *rpra = ctx->rpra; - struct fastrpc_user *fl = ctx->fl; - struct fastrpc_map *mmap = NULL; - struct fastrpc_invoke_buf *list; - struct fastrpc_phy_page *pages; - u64 *fdlist; - int i, inbufs, outbufs, handles; - - inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); - outbufs = REMOTE_SCALARS_OUTBUFS(ctx->sc); - handles = REMOTE_SCALARS_INHANDLES(ctx->sc) + REMOTE_SCALARS_OUTHANDLES(ctx->sc); - list = fastrpc_invoke_buf_start(rpra, ctx->nscalars); - pages = fastrpc_phy_page_start(list, ctx->nscalars); - fdlist = (uint64_t *)(pages + inbufs + outbufs + handles); - - for (i = inbufs; i < ctx->nbufs; ++i) { -<<<<<<< - if (!ctx->maps[i]) { - void *src = (void *)(uintptr_t)rpra[i].buf.pv; - void *dst = (void *)(uintptr_t)ctx->args[i].ptr; - u64 len = rpra[i].buf.len; -======= - void *src = (void *)(uintptr_t)rpra[i].pv; - void *dst = (void *)(uintptr_t)ctx->args[i].ptr; - u64 len = rpra[i].len; ->>>>>>> - - if (!kernel) { - if (copy_to_user((void __user *)dst, src, len)) - return -EFAULT; - } else { - memcpy(dst, src, len); - } - } - - for (i = 0; i < FASTRPC_MAX_FDLIST; i++) { - if (!fdlist[i]) - break; - if (!fastrpc_map_lookup(fl, (int)fdlist[i], &mmap)) - fastrpc_map_put(mmap); - } - - return 0; -} - -static int fastrpc_invoke_send(struct fastrpc_session_ctx *sctx, - struct fastrpc_invoke_ctx *ctx, - u32 kernel, uint32_t handle) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_user *fl = ctx->fl; - struct fastrpc_msg *msg = &ctx->msg; - int ret; - - cctx = fl->cctx; - msg->pid = fl->tgid; - msg->tid = current->pid; - - if (kernel) - msg->pid = 0; - - msg->ctx = ctx->ctxid | fl->pd; - msg->handle = handle; - msg->sc = ctx->sc; - msg->addr = ctx->buf ? ctx->buf->phys : 0; - msg->size = roundup(ctx->msg_sz, PAGE_SIZE); - fastrpc_context_get(ctx); - - ret = rpmsg_send(cctx->rpdev->ept, (void *)msg, sizeof(*msg)); - - if (ret) - fastrpc_context_put(ctx); - - return ret; - -} - -static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel, - u32 handle, u32 sc, - struct fastrpc_invoke_args *args) -{ - struct fastrpc_invoke_ctx *ctx = NULL; - int err = 0; - - if (!fl->sctx) - return -EINVAL; - - if (!fl->cctx->rpdev) - return -EPIPE; - - if (handle == FASTRPC_INIT_HANDLE && !kernel) { - dev_warn_ratelimited(fl->sctx->dev, "user app trying to send a kernel RPC message (%d)\n", handle); - return -EPERM; - } - - ctx = fastrpc_context_alloc(fl, kernel, sc, args); - if (IS_ERR(ctx)) - return PTR_ERR(ctx); - - if (ctx->nscalars) { - err = fastrpc_get_args(kernel, ctx); - if (err) - goto bail; - } - - /* make sure that all CPU memory writes are seen by DSP */ - dma_wmb(); - /* Send invoke buffer to remote dsp */ - err = fastrpc_invoke_send(fl->sctx, ctx, kernel, handle); - if (err) - goto bail; - - if (kernel) { - if (!wait_for_completion_timeout(&ctx->work, 10 * HZ)) - err = -ETIMEDOUT; - } else { - err = wait_for_completion_interruptible(&ctx->work); - } - - if (err) - goto bail; - - /* Check the response from remote dsp */ - err = ctx->retval; - if (err) - goto bail; - - if (ctx->nscalars) { - /* make sure that all memory writes by DSP are seen by CPU */ - dma_rmb(); - /* populate all the output buffers with results */ - err = fastrpc_put_args(ctx, kernel); - if (err) - goto bail; - } - -bail: - if (err != -ERESTARTSYS && err != -ETIMEDOUT) { - /* We are done with this compute context */ - spin_lock(&fl->lock); - list_del(&ctx->node); - spin_unlock(&fl->lock); - fastrpc_context_put(ctx); - } - if (err) - dev_dbg(fl->sctx->dev, "Error: Invoke Failed %d\n", err); - - return err; -} - -static bool is_session_rejected(struct fastrpc_user *fl, bool unsigned_pd_request) -{ - /* Check if the device node is non-secure and channel is secure*/ - if (!fl->is_secure_dev && fl->cctx->secure) { - /* - * Allow untrusted applications to offload only to Unsigned PD when - * channel is configured as secure and block untrusted apps on channel - * that does not support unsigned PD offload - */ - if (!fl->cctx->unsigned_support || !unsigned_pd_request) { - dev_err(&fl->cctx->rpdev->dev, "Error: Untrusted application trying to offload to signed PD"); - return true; - } - } - - return false; -} - -static int fastrpc_init_create_process(struct fastrpc_user *fl, - char __user *argp) -{ - struct fastrpc_init_create init; - struct fastrpc_invoke_args *args; - struct fastrpc_phy_page pages[1]; - struct fastrpc_map *map = NULL; - struct fastrpc_buf *imem = NULL; - int memlen; - int err; - struct { - int pgid; - u32 namelen; - u32 filelen; - u32 pageslen; - u32 attrs; - u32 siglen; - } inbuf; - u32 sc; - bool unsigned_module = false; - - args = kcalloc(FASTRPC_CREATE_PROCESS_NARGS, sizeof(*args), GFP_KERNEL); - if (!args) - return -ENOMEM; - - if (copy_from_user(&init, argp, sizeof(init))) { - err = -EFAULT; - goto err; - } - - if (init.attrs & FASTRPC_MODE_UNSIGNED_MODULE) - unsigned_module = true; - - if (is_session_rejected(fl, unsigned_module)) { - err = -ECONNREFUSED; - goto err; - } - - if (init.filelen > INIT_FILELEN_MAX) { - err = -EINVAL; - goto err; - } - - inbuf.pgid = fl->tgid; - inbuf.namelen = strlen(current->comm) + 1; - inbuf.filelen = init.filelen; - inbuf.pageslen = 1; - inbuf.attrs = init.attrs; - inbuf.siglen = init.siglen; - fl->pd = USER_PD; - - if (init.filelen && init.filefd) { - err = fastrpc_map_create(fl, init.filefd, init.filelen, 0, &map); - if (err) - goto err; - } - - memlen = ALIGN(max(INIT_FILELEN_MAX, (int)init.filelen * 4), - 1024 * 1024); - err = fastrpc_buf_alloc(fl, fl->sctx->dev, memlen, - &imem); - if (err) - goto err_alloc; - - fl->init_mem = imem; - args[0].ptr = (u64)(uintptr_t)&inbuf; - args[0].length = sizeof(inbuf); - args[0].fd = -1; - - args[1].ptr = (u64)(uintptr_t)current->comm; - args[1].length = inbuf.namelen; - args[1].fd = -1; - - args[2].ptr = (u64) init.file; - args[2].length = inbuf.filelen; - args[2].fd = init.filefd; - - pages[0].addr = imem->phys; - pages[0].size = imem->size; - - args[3].ptr = (u64)(uintptr_t) pages; - args[3].length = 1 * sizeof(*pages); - args[3].fd = -1; - - args[4].ptr = (u64)(uintptr_t)&inbuf.attrs; - args[4].length = sizeof(inbuf.attrs); - args[4].fd = -1; - - args[5].ptr = (u64)(uintptr_t) &inbuf.siglen; - args[5].length = sizeof(inbuf.siglen); - args[5].fd = -1; - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE, 4, 0); - if (init.attrs) - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE_ATTR, 6, 0); - - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, args); - if (err) - goto err_invoke; - - kfree(args); - - return 0; - -err_invoke: - fl->init_mem = NULL; - fastrpc_buf_free(imem); -err_alloc: - if (map) { - spin_lock(&fl->lock); - list_del(&map->node); - spin_unlock(&fl->lock); - fastrpc_map_put(map); - } -err: - kfree(args); - - return err; -} - -static struct fastrpc_session_ctx *fastrpc_session_alloc( - struct fastrpc_channel_ctx *cctx) -{ - struct fastrpc_session_ctx *session = NULL; - unsigned long flags; - int i; - - spin_lock_irqsave(&cctx->lock, flags); - for (i = 0; i < cctx->sesscount; i++) { - if (!cctx->session[i].used && cctx->session[i].valid) { - cctx->session[i].used = true; - session = &cctx->session[i]; - break; - } - } - spin_unlock_irqrestore(&cctx->lock, flags); - - return session; -} - -static void fastrpc_session_free(struct fastrpc_channel_ctx *cctx, - struct fastrpc_session_ctx *session) -{ - unsigned long flags; - - spin_lock_irqsave(&cctx->lock, flags); - session->used = false; - spin_unlock_irqrestore(&cctx->lock, flags); -} - -static int fastrpc_release_current_dsp_process(struct fastrpc_user *fl) -{ - struct fastrpc_invoke_args args[1]; - int tgid = 0; - u32 sc; - - tgid = fl->tgid; - args[0].ptr = (u64)(uintptr_t) &tgid; - args[0].length = sizeof(tgid); - args[0].fd = -1; - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_RELEASE, 1, 0); - - return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, &args[0]); -} - -static int fastrpc_device_release(struct inode *inode, struct file *file) -{ - struct fastrpc_user *fl = (struct fastrpc_user *)file->private_data; - struct fastrpc_channel_ctx *cctx = fl->cctx; - struct fastrpc_invoke_ctx *ctx, *n; - struct fastrpc_map *map, *m; - struct fastrpc_buf *buf, *b; - unsigned long flags; - - fastrpc_release_current_dsp_process(fl); - - spin_lock_irqsave(&cctx->lock, flags); - list_del(&fl->user); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (fl->init_mem) - fastrpc_buf_free(fl->init_mem); - - list_for_each_entry_safe(ctx, n, &fl->pending, node) { - list_del(&ctx->node); - fastrpc_context_put(ctx); - } - - list_for_each_entry_safe(map, m, &fl->maps, node) { - list_del(&map->node); - fastrpc_map_put(map); - } - - list_for_each_entry_safe(buf, b, &fl->mmaps, node) { - list_del(&buf->node); - fastrpc_buf_free(buf); - } - - fastrpc_session_free(cctx, fl->sctx); - fastrpc_channel_ctx_put(cctx); - - mutex_destroy(&fl->mutex); - kfree(fl); - file->private_data = NULL; - - return 0; -} - -static int fastrpc_device_open(struct inode *inode, struct file *filp) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_device *fdevice; - struct fastrpc_user *fl = NULL; - unsigned long flags; - - fdevice = miscdev_to_fdevice(filp->private_data); - cctx = fdevice->cctx; - - fl = kzalloc(sizeof(*fl), GFP_KERNEL); - if (!fl) - return -ENOMEM; - - /* Released in fastrpc_device_release() */ - fastrpc_channel_ctx_get(cctx); - - filp->private_data = fl; - spin_lock_init(&fl->lock); - mutex_init(&fl->mutex); - INIT_LIST_HEAD(&fl->pending); - INIT_LIST_HEAD(&fl->maps); - INIT_LIST_HEAD(&fl->mmaps); - INIT_LIST_HEAD(&fl->user); - fl->tgid = current->tgid; - fl->cctx = cctx; - fl->is_secure_dev = fdevice->secure; - - fl->sctx = fastrpc_session_alloc(cctx); - if (!fl->sctx) { - dev_err(&cctx->rpdev->dev, "No session available\n"); - mutex_destroy(&fl->mutex); - kfree(fl); - - return -EBUSY; - } - - spin_lock_irqsave(&cctx->lock, flags); - list_add_tail(&fl->user, &cctx->users); - spin_unlock_irqrestore(&cctx->lock, flags); - - return 0; -} - -static int fastrpc_dmabuf_alloc(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_alloc_dma_buf bp; - DEFINE_DMA_BUF_EXPORT_INFO(exp_info); - struct fastrpc_buf *buf = NULL; - int err; - - if (copy_from_user(&bp, argp, sizeof(bp))) - return -EFAULT; - - err = fastrpc_buf_alloc(fl, fl->sctx->dev, bp.size, &buf); - if (err) - return err; - exp_info.ops = &fastrpc_dma_buf_ops; - exp_info.size = bp.size; - exp_info.flags = O_RDWR; - exp_info.priv = buf; - buf->dmabuf = dma_buf_export(&exp_info); - if (IS_ERR(buf->dmabuf)) { - err = PTR_ERR(buf->dmabuf); - fastrpc_buf_free(buf); - return err; - } - - bp.fd = dma_buf_fd(buf->dmabuf, O_ACCMODE); - if (bp.fd < 0) { - dma_buf_put(buf->dmabuf); - return -EINVAL; - } - - if (copy_to_user(argp, &bp, sizeof(bp))) { - /* - * The usercopy failed, but we can't do much about it, as - * dma_buf_fd() already called fd_install() and made the - * file descriptor accessible for the current process. It - * might already be closed and dmabuf no longer valid when - * we reach this point. Therefore "leak" the fd and rely on - * the process exit path to do any required cleanup. - */ - return -EFAULT; - } - - return 0; -} - -static int fastrpc_init_attach(struct fastrpc_user *fl, int pd) -{ - struct fastrpc_invoke_args args[1]; - int tgid = fl->tgid; - u32 sc; - - args[0].ptr = (u64)(uintptr_t) &tgid; - args[0].length = sizeof(tgid); - args[0].fd = -1; - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_ATTACH, 1, 0); - fl->pd = pd; - - return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, &args[0]); -} - -static int fastrpc_invoke(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args *args = NULL; - struct fastrpc_invoke inv; - u32 nscalars; - int err; - - if (copy_from_user(&inv, argp, sizeof(inv))) - return -EFAULT; - - /* nscalars is truncated here to max supported value */ - nscalars = REMOTE_SCALARS_LENGTH(inv.sc); - if (nscalars) { - args = kcalloc(nscalars, sizeof(*args), GFP_KERNEL); - if (!args) - return -ENOMEM; - - if (copy_from_user(args, (void __user *)(uintptr_t)inv.args, - nscalars * sizeof(*args))) { - kfree(args); - return -EFAULT; - } - } - - err = fastrpc_internal_invoke(fl, false, inv.handle, inv.sc, args); - kfree(args); - - return err; -} - -static int fastrpc_get_info_from_dsp(struct fastrpc_user *fl, uint32_t *dsp_attr_buf, - uint32_t dsp_attr_buf_len) -{ - struct fastrpc_invoke_args args[2] = { 0 }; - - /* Capability filled in userspace */ - dsp_attr_buf[0] = 0; - - args[0].ptr = (u64)(uintptr_t)&dsp_attr_buf_len; - args[0].length = sizeof(dsp_attr_buf_len); - args[0].fd = -1; - args[1].ptr = (u64)(uintptr_t)&dsp_attr_buf[1]; - args[1].length = dsp_attr_buf_len; - args[1].fd = -1; - fl->pd = 1; - - return fastrpc_internal_invoke(fl, true, FASTRPC_DSP_UTILITIES_HANDLE, - FASTRPC_SCALARS(0, 1, 1), args); -} - -static int fastrpc_get_info_from_kernel(struct fastrpc_ioctl_capability *cap, - struct fastrpc_user *fl) -{ - struct fastrpc_channel_ctx *cctx = fl->cctx; - uint32_t attribute_id = cap->attribute_id; - uint32_t *dsp_attributes; - unsigned long flags; - uint32_t domain = cap->domain; - int err; - - spin_lock_irqsave(&cctx->lock, flags); - /* check if we already have queried dsp for attributes */ - if (cctx->valid_attributes) { - spin_unlock_irqrestore(&cctx->lock, flags); - goto done; - } - spin_unlock_irqrestore(&cctx->lock, flags); - - dsp_attributes = kzalloc(FASTRPC_MAX_DSP_ATTRIBUTES_LEN, GFP_KERNEL); - if (!dsp_attributes) - return -ENOMEM; - - err = fastrpc_get_info_from_dsp(fl, dsp_attributes, FASTRPC_MAX_DSP_ATTRIBUTES_LEN); - if (err == DSP_UNSUPPORTED_API) { - dev_info(&cctx->rpdev->dev, - "Warning: DSP capabilities not supported on domain: %d\n", domain); - kfree(dsp_attributes); - return -EOPNOTSUPP; - } else if (err) { - dev_err(&cctx->rpdev->dev, "Error: dsp information is incorrect err: %d\n", err); - kfree(dsp_attributes); - return err; - } - - spin_lock_irqsave(&cctx->lock, flags); - memcpy(cctx->dsp_attributes, dsp_attributes, FASTRPC_MAX_DSP_ATTRIBUTES_LEN); - cctx->valid_attributes = true; - spin_unlock_irqrestore(&cctx->lock, flags); - kfree(dsp_attributes); -done: - cap->capability = cctx->dsp_attributes[attribute_id]; - return 0; -} - -static int fastrpc_get_dsp_info(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_ioctl_capability cap = {0}; - int err = 0; - - if (copy_from_user(&cap, argp, sizeof(cap))) - return -EFAULT; - - cap.capability = 0; - if (cap.domain >= FASTRPC_DEV_MAX) { - dev_err(&fl->cctx->rpdev->dev, "Error: Invalid domain id:%d, err:%d\n", - cap.domain, err); - return -ECHRNG; - } - - /* Fastrpc Capablities does not support modem domain */ - if (cap.domain == MDSP_DOMAIN_ID) { - dev_err(&fl->cctx->rpdev->dev, "Error: modem not supported %d\n", err); - return -ECHRNG; - } - - if (cap.attribute_id >= FASTRPC_MAX_DSP_ATTRIBUTES) { - dev_err(&fl->cctx->rpdev->dev, "Error: invalid attribute: %d, err: %d\n", - cap.attribute_id, err); - return -EOVERFLOW; - } - - err = fastrpc_get_info_from_kernel(&cap, fl); - if (err) - return err; - - if (copy_to_user(argp, &cap.capability, sizeof(cap.capability))) - return -EFAULT; - - return 0; -} - -static int fastrpc_req_munmap_impl(struct fastrpc_user *fl, - struct fastrpc_req_munmap *req) -{ - struct fastrpc_invoke_args args[1] = { [0] = { 0 } }; - struct fastrpc_buf *buf, *b; - struct fastrpc_munmap_req_msg req_msg; - struct device *dev = fl->sctx->dev; - int err; - u32 sc; - - spin_lock(&fl->lock); - list_for_each_entry_safe(buf, b, &fl->mmaps, node) { - if ((buf->raddr == req->vaddrout) && (buf->size == req->size)) - break; - buf = NULL; - } - spin_unlock(&fl->lock); - - if (!buf) { - dev_err(dev, "mmap not in list\n"); - return -EINVAL; - } - - req_msg.pgid = fl->tgid; - req_msg.size = buf->size; - req_msg.vaddr = buf->raddr; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MUNMAP, 1, 0); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - if (!err) { - dev_dbg(dev, "unmmap\tpt 0x%09lx OK\n", buf->raddr); - spin_lock(&fl->lock); - list_del(&buf->node); - spin_unlock(&fl->lock); - fastrpc_buf_free(buf); - } else { - dev_err(dev, "unmmap\tpt 0x%09lx ERROR\n", buf->raddr); - } - - return err; -} - -static int fastrpc_req_munmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_req_munmap req; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - return fastrpc_req_munmap_impl(fl, &req); -} - -static int fastrpc_req_mmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args args[3] = { [0 ... 2] = { 0 } }; - struct fastrpc_buf *buf = NULL; - struct fastrpc_mmap_req_msg req_msg; - struct fastrpc_mmap_rsp_msg rsp_msg; - struct fastrpc_req_munmap req_unmap; - struct fastrpc_phy_page pages; - struct fastrpc_req_mmap req; - struct device *dev = fl->sctx->dev; - int err; - u32 sc; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - if (req.flags != ADSP_MMAP_ADD_PAGES) { - dev_err(dev, "flag not supported 0x%x\n", req.flags); - return -EINVAL; - } - - if (req.vaddrin) { - dev_err(dev, "adding user allocated pages is not supported\n"); - return -EINVAL; - } - - err = fastrpc_buf_alloc(fl, fl->sctx->dev, req.size, &buf); - if (err) { - dev_err(dev, "failed to allocate buffer\n"); - return err; - } - - req_msg.pgid = fl->tgid; - req_msg.flags = req.flags; - req_msg.vaddr = req.vaddrin; - req_msg.num = sizeof(pages); - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - pages.addr = buf->phys; - pages.size = buf->size; - - args[1].ptr = (u64) (uintptr_t) &pages; - args[1].length = sizeof(pages); - - args[2].ptr = (u64) (uintptr_t) &rsp_msg; - args[2].length = sizeof(rsp_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MMAP, 2, 1); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - if (err) { - dev_err(dev, "mmap error (len 0x%08llx)\n", buf->size); - goto err_invoke; - } - - /* update the buffer to be able to deallocate the memory on the DSP */ - buf->raddr = (uintptr_t) rsp_msg.vaddr; - - /* let the client know the address to use */ - req.vaddrout = rsp_msg.vaddr; - - spin_lock(&fl->lock); - list_add_tail(&buf->node, &fl->mmaps); - spin_unlock(&fl->lock); - - if (copy_to_user((void __user *)argp, &req, sizeof(req))) { - /* unmap the memory and release the buffer */ - req_unmap.vaddrout = buf->raddr; - req_unmap.size = buf->size; - fastrpc_req_munmap_impl(fl, &req_unmap); - return -EFAULT; - } - - dev_dbg(dev, "mmap\t\tpt 0x%09lx OK [len 0x%08llx]\n", - buf->raddr, buf->size); - - return 0; - -err_invoke: - fastrpc_buf_free(buf); - - return err; -} - -static int fastrpc_req_mem_unmap_impl(struct fastrpc_user *fl, struct fastrpc_mem_unmap *req) -{ - struct fastrpc_invoke_args args[1] = { [0] = { 0 } }; - struct fastrpc_map *map = NULL, *m; - struct fastrpc_mem_unmap_req_msg req_msg = { 0 }; - int err = 0; - u32 sc; - struct device *dev = fl->sctx->dev; - - spin_lock(&fl->lock); - list_for_each_entry_safe(map, m, &fl->maps, node) { - if ((req->fd < 0 || map->fd == req->fd) && (map->raddr == req->vaddr)) - break; - map = NULL; - } - - spin_unlock(&fl->lock); - - if (!map) { - dev_err(dev, "map not in list\n"); - return -EINVAL; - } - - req_msg.pgid = fl->tgid; - req_msg.len = map->len; - req_msg.vaddrin = map->raddr; - req_msg.fd = map->fd; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_UNMAP, 1, 0); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - fastrpc_map_put(map); - if (err) - dev_err(dev, "unmmap\tpt fd = %d, 0x%09llx error\n", map->fd, map->raddr); - - return err; -} - -static int fastrpc_req_mem_unmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_mem_unmap req; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - return fastrpc_req_mem_unmap_impl(fl, &req); -} - -static int fastrpc_req_mem_map(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args args[4] = { [0 ... 3] = { 0 } }; - struct fastrpc_mem_map_req_msg req_msg = { 0 }; - struct fastrpc_mmap_rsp_msg rsp_msg = { 0 }; - struct fastrpc_mem_unmap req_unmap = { 0 }; - struct fastrpc_phy_page pages = { 0 }; - struct fastrpc_mem_map req; - struct device *dev = fl->sctx->dev; - struct fastrpc_map *map = NULL; - int err; - u32 sc; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - /* create SMMU mapping */ - err = fastrpc_map_create(fl, req.fd, req.length, 0, &map); - if (err) { - dev_err(dev, "failed to map buffer, fd = %d\n", req.fd); - return err; - } - - req_msg.pgid = fl->tgid; - req_msg.fd = req.fd; - req_msg.offset = req.offset; - req_msg.vaddrin = req.vaddrin; - map->va = (void *) (uintptr_t) req.vaddrin; - req_msg.flags = req.flags; - req_msg.num = sizeof(pages); - req_msg.data_len = 0; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - pages.addr = map->phys; - pages.size = map->size; - - args[1].ptr = (u64) (uintptr_t) &pages; - args[1].length = sizeof(pages); - - args[2].ptr = (u64) (uintptr_t) &pages; - args[2].length = 0; - - args[3].ptr = (u64) (uintptr_t) &rsp_msg; - args[3].length = sizeof(rsp_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_MAP, 3, 1); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, &args[0]); - if (err) { - dev_err(dev, "mem mmap error, fd %d, vaddr %llx, size %lld\n", - req.fd, req.vaddrin, map->size); - goto err_invoke; - } - - /* update the buffer to be able to deallocate the memory on the DSP */ - map->raddr = rsp_msg.vaddr; - - /* let the client know the address to use */ - req.vaddrout = rsp_msg.vaddr; - - if (copy_to_user((void __user *)argp, &req, sizeof(req))) { - /* unmap the memory and release the buffer */ - req_unmap.vaddr = (uintptr_t) rsp_msg.vaddr; - req_unmap.length = map->size; - fastrpc_req_mem_unmap_impl(fl, &req_unmap); - return -EFAULT; - } - - return 0; - -err_invoke: - fastrpc_map_put(map); - - return err; -} - -static long fastrpc_device_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - struct fastrpc_user *fl = (struct fastrpc_user *)file->private_data; - char __user *argp = (char __user *)arg; - int err; - - switch (cmd) { - case FASTRPC_IOCTL_INVOKE: - err = fastrpc_invoke(fl, argp); - break; - case FASTRPC_IOCTL_INIT_ATTACH: - err = fastrpc_init_attach(fl, AUDIO_PD); - break; - case FASTRPC_IOCTL_INIT_ATTACH_SNS: - err = fastrpc_init_attach(fl, SENSORS_PD); - break; - case FASTRPC_IOCTL_INIT_CREATE: - err = fastrpc_init_create_process(fl, argp); - break; - case FASTRPC_IOCTL_ALLOC_DMA_BUFF: - err = fastrpc_dmabuf_alloc(fl, argp); - break; - case FASTRPC_IOCTL_MMAP: - err = fastrpc_req_mmap(fl, argp); - break; - case FASTRPC_IOCTL_MUNMAP: - err = fastrpc_req_munmap(fl, argp); - break; - case FASTRPC_IOCTL_MEM_MAP: - err = fastrpc_req_mem_map(fl, argp); - break; - case FASTRPC_IOCTL_MEM_UNMAP: - err = fastrpc_req_mem_unmap(fl, argp); - break; - case FASTRPC_IOCTL_GET_DSP_INFO: - err = fastrpc_get_dsp_info(fl, argp); - break; - default: - err = -ENOTTY; - break; - } - - return err; -} - -static const struct file_operations fastrpc_fops = { - .open = fastrpc_device_open, - .release = fastrpc_device_release, - .unlocked_ioctl = fastrpc_device_ioctl, - .compat_ioctl = fastrpc_device_ioctl, -}; - -static int fastrpc_cb_probe(struct platform_device *pdev) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_session_ctx *sess; - struct device *dev = &pdev->dev; - int i, sessions = 0; - unsigned long flags; - int rc; - - cctx = dev_get_drvdata(dev->parent); - if (!cctx) - return -EINVAL; - - of_property_read_u32(dev->of_node, "qcom,nsessions", &sessions); - - spin_lock_irqsave(&cctx->lock, flags); - sess = &cctx->session[cctx->sesscount]; - sess->used = false; - sess->valid = true; - sess->dev = dev; - dev_set_drvdata(dev, sess); - - if (of_property_read_u32(dev->of_node, "reg", &sess->sid)) - dev_info(dev, "FastRPC Session ID not specified in DT\n"); - - if (sessions > 0) { - struct fastrpc_session_ctx *dup_sess; - - for (i = 1; i < sessions; i++) { - if (cctx->sesscount++ >= FASTRPC_MAX_SESSIONS) - break; - dup_sess = &cctx->session[cctx->sesscount]; - memcpy(dup_sess, sess, sizeof(*dup_sess)); - } - } - cctx->sesscount++; - spin_unlock_irqrestore(&cctx->lock, flags); - rc = dma_set_mask(dev, DMA_BIT_MASK(32)); - if (rc) { - dev_err(dev, "32-bit DMA enable failed\n"); - return rc; - } - - return 0; -} - -static int fastrpc_cb_remove(struct platform_device *pdev) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(pdev->dev.parent); - struct fastrpc_session_ctx *sess = dev_get_drvdata(&pdev->dev); - unsigned long flags; - int i; - - spin_lock_irqsave(&cctx->lock, flags); - for (i = 1; i < FASTRPC_MAX_SESSIONS; i++) { - if (cctx->session[i].sid == sess->sid) { - cctx->session[i].valid = false; - cctx->sesscount--; - } - } - spin_unlock_irqrestore(&cctx->lock, flags); - - return 0; -} - -static const struct of_device_id fastrpc_match_table[] = { - { .compatible = "qcom,fastrpc-compute-cb", }, - {} -}; - -static struct platform_driver fastrpc_cb_driver = { - .probe = fastrpc_cb_probe, - .remove = fastrpc_cb_remove, - .driver = { - .name = "qcom,fastrpc-cb", - .of_match_table = fastrpc_match_table, - .suppress_bind_attrs = true, - }, -}; - -static int fastrpc_device_register(struct device *dev, struct fastrpc_channel_ctx *cctx, - bool is_secured, const char *domain) -{ - struct fastrpc_device *fdev; - int err; - - fdev = devm_kzalloc(dev, sizeof(*fdev), GFP_KERNEL); - if (!fdev) - return -ENOMEM; - - fdev->secure = is_secured; - fdev->cctx = cctx; - fdev->miscdev.minor = MISC_DYNAMIC_MINOR; - fdev->miscdev.fops = &fastrpc_fops; - fdev->miscdev.name = devm_kasprintf(dev, GFP_KERNEL, "fastrpc-%s%s", - domain, is_secured ? "-secure" : ""); - err = misc_register(&fdev->miscdev); - if (!err) { - if (is_secured) - cctx->secure_fdevice = fdev; - else - cctx->fdevice = fdev; - } - - return err; -} - -static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) -{ - struct device *rdev = &rpdev->dev; - struct fastrpc_channel_ctx *data; - int i, err, domain_id = -1, vmcount; - const char *domain; - bool secure_dsp; - unsigned int vmids[FASTRPC_MAX_VMIDS]; - - err = of_property_read_string(rdev->of_node, "label", &domain); - if (err) { - dev_info(rdev, "FastRPC Domain not specified in DT\n"); - return err; - } - - for (i = 0; i <= CDSP_DOMAIN_ID; i++) { - if (!strcmp(domains[i], domain)) { - domain_id = i; - break; - } - } - - if (domain_id < 0) { - dev_info(rdev, "FastRPC Invalid Domain ID %d\n", domain_id); - return -EINVAL; - } - - vmcount = of_property_read_variable_u32_array(rdev->of_node, - "qcom,vmids", &vmids[0], 0, FASTRPC_MAX_VMIDS); - if (vmcount < 0) - vmcount = 0; - else if (!qcom_scm_is_available()) - return -EPROBE_DEFER; - - data = kzalloc(sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - if (vmcount) { - data->vmcount = vmcount; - data->perms = BIT(QCOM_SCM_VMID_HLOS); - for (i = 0; i < data->vmcount; i++) { - data->vmperms[i].vmid = vmids[i]; - data->vmperms[i].perm = QCOM_SCM_PERM_RWX; - } - } - - secure_dsp = !(of_property_read_bool(rdev->of_node, "qcom,non-secure-domain")); - data->secure = secure_dsp; - - switch (domain_id) { - case ADSP_DOMAIN_ID: - case MDSP_DOMAIN_ID: - case SDSP_DOMAIN_ID: - /* Unsigned PD offloading is only supported on CDSP*/ - data->unsigned_support = false; - err = fastrpc_device_register(rdev, data, secure_dsp, domains[domain_id]); - if (err) - goto fdev_error; - break; - case CDSP_DOMAIN_ID: - data->unsigned_support = true; - /* Create both device nodes so that we can allow both Signed and Unsigned PD */ - err = fastrpc_device_register(rdev, data, true, domains[domain_id]); - if (err) - goto fdev_error; - - err = fastrpc_device_register(rdev, data, false, domains[domain_id]); - if (err) - goto fdev_error; - break; - default: - err = -EINVAL; - goto fdev_error; - } - - kref_init(&data->refcount); - - dev_set_drvdata(&rpdev->dev, data); - dma_set_mask_and_coherent(rdev, DMA_BIT_MASK(32)); - INIT_LIST_HEAD(&data->users); - spin_lock_init(&data->lock); - idr_init(&data->ctx_idr); - data->domain_id = domain_id; - data->rpdev = rpdev; - - return of_platform_populate(rdev->of_node, NULL, NULL, rdev); -fdev_error: - kfree(data); - return err; -} - -static void fastrpc_notify_users(struct fastrpc_user *user) -{ - struct fastrpc_invoke_ctx *ctx; - - spin_lock(&user->lock); - list_for_each_entry(ctx, &user->pending, node) - complete(&ctx->work); - spin_unlock(&user->lock); -} - -static void fastrpc_rpmsg_remove(struct rpmsg_device *rpdev) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(&rpdev->dev); - struct fastrpc_user *user; - unsigned long flags; - - spin_lock_irqsave(&cctx->lock, flags); - list_for_each_entry(user, &cctx->users, user) - fastrpc_notify_users(user); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (cctx->fdevice) - misc_deregister(&cctx->fdevice->miscdev); - - if (cctx->secure_fdevice) - misc_deregister(&cctx->secure_fdevice->miscdev); - - of_platform_depopulate(&rpdev->dev); - - cctx->rpdev = NULL; - fastrpc_channel_ctx_put(cctx); -} - -static int fastrpc_rpmsg_callback(struct rpmsg_device *rpdev, void *data, - int len, void *priv, u32 addr) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(&rpdev->dev); - struct fastrpc_invoke_rsp *rsp = data; - struct fastrpc_invoke_ctx *ctx; - unsigned long flags; - unsigned long ctxid; - - if (len < sizeof(*rsp)) - return -EINVAL; - - ctxid = ((rsp->ctx & FASTRPC_CTXID_MASK) >> 4); - - spin_lock_irqsave(&cctx->lock, flags); - ctx = idr_find(&cctx->ctx_idr, ctxid); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (!ctx) { - dev_err(&rpdev->dev, "No context ID matches response\n"); - return -ENOENT; - } - - ctx->retval = rsp->retval; - complete(&ctx->work); - - /* - * The DMA buffer associated with the context cannot be freed in - * interrupt context so schedule it through a worker thread to - * avoid a kernel BUG. - */ - schedule_work(&ctx->put_work); - - return 0; -} - -static const struct of_device_id fastrpc_rpmsg_of_match[] = { - { .compatible = "qcom,fastrpc" }, - { }, -}; -MODULE_DEVICE_TABLE(of, fastrpc_rpmsg_of_match); - -static struct rpmsg_driver fastrpc_driver = { - .probe = fastrpc_rpmsg_probe, - .remove = fastrpc_rpmsg_remove, - .callback = fastrpc_rpmsg_callback, - .drv = { - .name = "qcom,fastrpc", - .of_match_table = fastrpc_rpmsg_of_match, - }, -}; - -static int fastrpc_init(void) -{ - int ret; - - ret = platform_driver_register(&fastrpc_cb_driver); - if (ret < 0) { - pr_err("fastrpc: failed to register cb driver\n"); - return ret; - } - - ret = register_rpmsg_driver(&fastrpc_driver); - if (ret < 0) { - pr_err("fastrpc: failed to register rpmsg driver\n"); - platform_driver_unregister(&fastrpc_cb_driver); - return ret; - } - - return 0; -} -module_init(fastrpc_init); - -static void fastrpc_exit(void) -{ - platform_driver_unregister(&fastrpc_cb_driver); - unregister_rpmsg_driver(&fastrpc_driver); -} -module_exit(fastrpc_exit); - -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/b42f7c232a68fe3a2a83a0d9b5bf92a639ec1865/preimage.1 b/rr-cache/b42f7c232a68fe3a2a83a0d9b5bf92a639ec1865/preimage.1 deleted file mode 100644 index e0641cd..0000000 --- a/rr-cache/b42f7c232a68fe3a2a83a0d9b5bf92a639ec1865/preimage.1 +++ /dev/null @@ -1,2245 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2011-2018, The Linux Foundation. All rights reserved. -// Copyright (c) 2018, Linaro Limited - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define ADSP_DOMAIN_ID (0) -#define MDSP_DOMAIN_ID (1) -#define SDSP_DOMAIN_ID (2) -#define CDSP_DOMAIN_ID (3) -#define FASTRPC_DEV_MAX 4 /* adsp, mdsp, slpi, cdsp*/ -#define FASTRPC_MAX_SESSIONS 13 /*12 compute, 1 cpz*/ -#define FASTRPC_MAX_VMIDS 16 -#define FASTRPC_ALIGN 128 -#define FASTRPC_MAX_FDLIST 16 -#define FASTRPC_MAX_CRCLIST 64 -#define FASTRPC_PHYS(p) ((p) & 0xffffffff) -#define FASTRPC_CTX_MAX (256) -#define FASTRPC_INIT_HANDLE 1 -#define FASTRPC_DSP_UTILITIES_HANDLE 2 -#define FASTRPC_CTXID_MASK (0xFF0) -#define INIT_FILELEN_MAX (2 * 1024 * 1024) -#define FASTRPC_DEVICE_NAME "fastrpc" -#define ADSP_MMAP_ADD_PAGES 0x1000 -#define DSP_UNSUPPORTED_API (0x80000414) -/* MAX NUMBER of DSP ATTRIBUTES SUPPORTED */ -#define FASTRPC_MAX_DSP_ATTRIBUTES (256) -#define FASTRPC_MAX_DSP_ATTRIBUTES_LEN (sizeof(u32) * FASTRPC_MAX_DSP_ATTRIBUTES) - -/* Retrives number of input buffers from the scalars parameter */ -#define REMOTE_SCALARS_INBUFS(sc) (((sc) >> 16) & 0x0ff) - -/* Retrives number of output buffers from the scalars parameter */ -#define REMOTE_SCALARS_OUTBUFS(sc) (((sc) >> 8) & 0x0ff) - -/* Retrives number of input handles from the scalars parameter */ -#define REMOTE_SCALARS_INHANDLES(sc) (((sc) >> 4) & 0x0f) - -/* Retrives number of output handles from the scalars parameter */ -#define REMOTE_SCALARS_OUTHANDLES(sc) ((sc) & 0x0f) - -#define REMOTE_SCALARS_LENGTH(sc) (REMOTE_SCALARS_INBUFS(sc) + \ - REMOTE_SCALARS_OUTBUFS(sc) + \ - REMOTE_SCALARS_INHANDLES(sc)+ \ - REMOTE_SCALARS_OUTHANDLES(sc)) -#define FASTRPC_BUILD_SCALARS(attr, method, in, out, oin, oout) \ - (((attr & 0x07) << 29) | \ - ((method & 0x1f) << 24) | \ - ((in & 0xff) << 16) | \ - ((out & 0xff) << 8) | \ - ((oin & 0x0f) << 4) | \ - (oout & 0x0f)) - -#define FASTRPC_SCALARS(method, in, out) \ - FASTRPC_BUILD_SCALARS(0, method, in, out, 0, 0) - -#define FASTRPC_CREATE_PROCESS_NARGS 6 -/* Remote Method id table */ -#define FASTRPC_RMID_INIT_ATTACH 0 -#define FASTRPC_RMID_INIT_RELEASE 1 -#define FASTRPC_RMID_INIT_MMAP 4 -#define FASTRPC_RMID_INIT_MUNMAP 5 -#define FASTRPC_RMID_INIT_CREATE 6 -#define FASTRPC_RMID_INIT_CREATE_ATTR 7 -#define FASTRPC_RMID_INIT_CREATE_STATIC 8 -#define FASTRPC_RMID_INIT_MEM_MAP 10 -#define FASTRPC_RMID_INIT_MEM_UNMAP 11 - -/* Protection Domain(PD) ids */ -#define AUDIO_PD (0) /* also GUEST_OS PD? */ -#define USER_PD (1) -#define SENSORS_PD (2) - -#define miscdev_to_fdevice(d) container_of(d, struct fastrpc_device, miscdev) - -static const char *domains[FASTRPC_DEV_MAX] = { "adsp", "mdsp", - "sdsp", "cdsp"}; -struct fastrpc_phy_page { - u64 addr; /* physical address */ - u64 size; /* size of contiguous region */ -}; - -struct fastrpc_invoke_buf { - u32 num; /* number of contiguous regions */ - u32 pgidx; /* index to start of contiguous region */ -}; - -struct fastrpc_remote_dmahandle { - s32 fd; /* dma handle fd */ - u32 offset; /* dma handle offset */ - u32 len; /* dma handle length */ -}; - -struct fastrpc_remote_buf { - u64 pv; /* buffer pointer */ - u64 len; /* length of buffer */ -}; - -union fastrpc_remote_arg { - struct fastrpc_remote_buf buf; - struct fastrpc_remote_dmahandle dma; -}; - -struct fastrpc_mmap_rsp_msg { - u64 vaddr; -}; - -struct fastrpc_mmap_req_msg { - s32 pgid; - u32 flags; - u64 vaddr; - s32 num; -}; - -struct fastrpc_mem_map_req_msg { - s32 pgid; - s32 fd; - s32 offset; - u32 flags; - u64 vaddrin; - s32 num; - s32 data_len; -}; - -struct fastrpc_munmap_req_msg { - s32 pgid; - u64 vaddr; - u64 size; -}; - -struct fastrpc_mem_unmap_req_msg { - s32 pgid; - s32 fd; - u64 vaddrin; - u64 len; -}; - -struct fastrpc_msg { - int pid; /* process group id */ - int tid; /* thread id */ - u64 ctx; /* invoke caller context */ - u32 handle; /* handle to invoke */ - u32 sc; /* scalars structure describing the data */ - u64 addr; /* physical address */ - u64 size; /* size of contiguous region */ -}; - -struct fastrpc_invoke_rsp { - u64 ctx; /* invoke caller context */ - int retval; /* invoke return value */ -}; - -struct fastrpc_buf_overlap { - u64 start; - u64 end; - int raix; - u64 mstart; - u64 mend; - u64 offset; -}; - -struct fastrpc_buf { - struct fastrpc_user *fl; - struct dma_buf *dmabuf; - struct device *dev; - void *virt; - u64 phys; - u64 size; - /* Lock for dma buf attachments */ - struct mutex lock; - struct list_head attachments; - /* mmap support */ - struct list_head node; /* list of user requested mmaps */ - uintptr_t raddr; -}; - -struct fastrpc_dma_buf_attachment { - struct device *dev; - struct sg_table sgt; - struct list_head node; -}; - -struct fastrpc_map { - struct list_head node; - struct fastrpc_user *fl; - int fd; - struct dma_buf *buf; - struct sg_table *table; - struct dma_buf_attachment *attach; - u64 phys; - u64 size; - void *va; - u64 len; - u64 raddr; - u32 attr; - struct kref refcount; -}; - -struct fastrpc_invoke_ctx { - int nscalars; - int nbufs; - int retval; - int pid; - int tgid; - u32 sc; - u32 *crc; - u64 ctxid; - u64 msg_sz; - struct kref refcount; - struct list_head node; /* list of ctxs */ - struct completion work; - struct work_struct put_work; - struct fastrpc_msg msg; - struct fastrpc_user *fl; - union fastrpc_remote_arg *rpra; - struct fastrpc_map **maps; - struct fastrpc_buf *buf; - struct fastrpc_invoke_args *args; - struct fastrpc_buf_overlap *olaps; - struct fastrpc_channel_ctx *cctx; -}; - -struct fastrpc_session_ctx { - struct device *dev; - int sid; - bool used; - bool valid; -}; - -struct fastrpc_channel_ctx { - int domain_id; - int sesscount; - int vmcount; - u32 perms; - struct qcom_scm_vmperm vmperms[FASTRPC_MAX_VMIDS]; - struct rpmsg_device *rpdev; - struct fastrpc_session_ctx session[FASTRPC_MAX_SESSIONS]; - spinlock_t lock; - struct idr ctx_idr; - struct list_head users; - struct kref refcount; - /* Flag if dsp attributes are cached */ - bool valid_attributes; - u32 dsp_attributes[FASTRPC_MAX_DSP_ATTRIBUTES]; - struct fastrpc_device *secure_fdevice; - struct fastrpc_device *fdevice; - bool secure; - bool unsigned_support; -}; - -struct fastrpc_device { - struct fastrpc_channel_ctx *cctx; - struct miscdevice miscdev; - bool secure; -}; - -struct fastrpc_user { - struct list_head user; - struct list_head maps; - struct list_head pending; - struct list_head mmaps; - - struct fastrpc_channel_ctx *cctx; - struct fastrpc_session_ctx *sctx; - struct fastrpc_buf *init_mem; - - int tgid; - int pd; - bool is_secure_dev; - /* Lock for lists */ - spinlock_t lock; - /* lock for allocations */ - struct mutex mutex; -}; - -static void fastrpc_free_map(struct kref *ref) -{ - struct fastrpc_map *map; - - map = container_of(ref, struct fastrpc_map, refcount); - - if (map->table) { - if (map->attr & FASTRPC_ATTR_SECUREMAP) { - struct qcom_scm_vmperm perm; - int err = 0; - - perm.vmid = QCOM_SCM_VMID_HLOS; - perm.perm = QCOM_SCM_PERM_RWX; - err = qcom_scm_assign_mem(map->phys, map->size, - &(map->fl->cctx->vmperms[0].vmid), &perm, 1); - if (err) { - dev_err(map->fl->sctx->dev, "Failed to assign memory phys 0x%llx size 0x%llx err %d", - map->phys, map->size, err); - return; - } - } - dma_buf_unmap_attachment(map->attach, map->table, - DMA_BIDIRECTIONAL); - dma_buf_detach(map->buf, map->attach); - dma_buf_put(map->buf); - } - - kfree(map); -} - -static void fastrpc_map_put(struct fastrpc_map *map) -{ - if (map) - kref_put(&map->refcount, fastrpc_free_map); -} - -static void fastrpc_map_get(struct fastrpc_map *map) -{ - if (map) - kref_get(&map->refcount); -} - - -static int fastrpc_map_lookup(struct fastrpc_user *fl, int fd, - struct fastrpc_map **ppmap) -{ - struct fastrpc_map *map = NULL; - - mutex_lock(&fl->mutex); - list_for_each_entry(map, &fl->maps, node) { - if (map->fd == fd) { - *ppmap = map; - mutex_unlock(&fl->mutex); - return 0; - } - } - mutex_unlock(&fl->mutex); - - return -ENOENT; -} - -static int fastrpc_map_find(struct fastrpc_user *fl, int fd, - struct fastrpc_map **ppmap) -{ - int ret = fastrpc_map_lookup(fl, fd, ppmap); - - if (!ret) - fastrpc_map_get(*ppmap); - - return ret; -} - -static void fastrpc_buf_free(struct fastrpc_buf *buf) -{ - dma_free_coherent(buf->dev, buf->size, buf->virt, - FASTRPC_PHYS(buf->phys)); - kfree(buf); -} - -static int fastrpc_buf_alloc(struct fastrpc_user *fl, struct device *dev, - u64 size, struct fastrpc_buf **obuf) -{ - struct fastrpc_buf *buf; - - buf = kzalloc(sizeof(*buf), GFP_KERNEL); - if (!buf) - return -ENOMEM; - - INIT_LIST_HEAD(&buf->attachments); - INIT_LIST_HEAD(&buf->node); - mutex_init(&buf->lock); - - buf->fl = fl; - buf->virt = NULL; - buf->phys = 0; - buf->size = size; - buf->dev = dev; - buf->raddr = 0; - - buf->virt = dma_alloc_coherent(dev, buf->size, (dma_addr_t *)&buf->phys, - GFP_KERNEL); - if (!buf->virt) { - mutex_destroy(&buf->lock); - kfree(buf); - return -ENOMEM; - } - - if (fl->sctx && fl->sctx->sid) - buf->phys += ((u64)fl->sctx->sid << 32); - - *obuf = buf; - - return 0; -} - -static void fastrpc_channel_ctx_free(struct kref *ref) -{ - struct fastrpc_channel_ctx *cctx; - - cctx = container_of(ref, struct fastrpc_channel_ctx, refcount); - - kfree(cctx); -} - -static void fastrpc_channel_ctx_get(struct fastrpc_channel_ctx *cctx) -{ - kref_get(&cctx->refcount); -} - -static void fastrpc_channel_ctx_put(struct fastrpc_channel_ctx *cctx) -{ - kref_put(&cctx->refcount, fastrpc_channel_ctx_free); -} - -static void fastrpc_context_free(struct kref *ref) -{ - struct fastrpc_invoke_ctx *ctx; - struct fastrpc_channel_ctx *cctx; - unsigned long flags; - int i; - - ctx = container_of(ref, struct fastrpc_invoke_ctx, refcount); - cctx = ctx->cctx; - - for (i = 0; i < ctx->nbufs; i++) - fastrpc_map_put(ctx->maps[i]); - - if (ctx->buf) - fastrpc_buf_free(ctx->buf); - - spin_lock_irqsave(&cctx->lock, flags); - idr_remove(&cctx->ctx_idr, ctx->ctxid >> 4); - spin_unlock_irqrestore(&cctx->lock, flags); - - kfree(ctx->maps); - kfree(ctx->olaps); - kfree(ctx); - - fastrpc_channel_ctx_put(cctx); -} - -static void fastrpc_context_get(struct fastrpc_invoke_ctx *ctx) -{ - kref_get(&ctx->refcount); -} - -static void fastrpc_context_put(struct fastrpc_invoke_ctx *ctx) -{ - kref_put(&ctx->refcount, fastrpc_context_free); -} - -static void fastrpc_context_put_wq(struct work_struct *work) -{ - struct fastrpc_invoke_ctx *ctx = - container_of(work, struct fastrpc_invoke_ctx, put_work); - - fastrpc_context_put(ctx); -} - -#define CMP(aa, bb) ((aa) == (bb) ? 0 : (aa) < (bb) ? -1 : 1) -static int olaps_cmp(const void *a, const void *b) -{ - struct fastrpc_buf_overlap *pa = (struct fastrpc_buf_overlap *)a; - struct fastrpc_buf_overlap *pb = (struct fastrpc_buf_overlap *)b; - /* sort with lowest starting buffer first */ - int st = CMP(pa->start, pb->start); - /* sort with highest ending buffer first */ - int ed = CMP(pb->end, pa->end); - - return st == 0 ? ed : st; -} - -static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) -{ - u64 max_end = 0; - int i; - - for (i = 0; i < ctx->nbufs; ++i) { - ctx->olaps[i].start = ctx->args[i].ptr; - ctx->olaps[i].end = ctx->olaps[i].start + ctx->args[i].length; - ctx->olaps[i].raix = i; - } - - sort(ctx->olaps, ctx->nbufs, sizeof(*ctx->olaps), olaps_cmp, NULL); - - for (i = 0; i < ctx->nbufs; ++i) { - /* Falling inside previous range */ - if (ctx->olaps[i].start < max_end) { - ctx->olaps[i].mstart = max_end; - ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].offset = max_end - ctx->olaps[i].start; - - if (ctx->olaps[i].end > max_end) { - max_end = ctx->olaps[i].end; - } else { - ctx->olaps[i].mend = 0; - ctx->olaps[i].mstart = 0; - } - - } else { - ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].mstart = ctx->olaps[i].start; - ctx->olaps[i].offset = 0; - max_end = ctx->olaps[i].end; - } - } -} - -static struct fastrpc_invoke_ctx *fastrpc_context_alloc( - struct fastrpc_user *user, u32 kernel, u32 sc, - struct fastrpc_invoke_args *args) -{ - struct fastrpc_channel_ctx *cctx = user->cctx; - struct fastrpc_invoke_ctx *ctx = NULL; - unsigned long flags; - int ret; - - ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return ERR_PTR(-ENOMEM); - - INIT_LIST_HEAD(&ctx->node); - ctx->fl = user; - ctx->nscalars = REMOTE_SCALARS_LENGTH(sc); - ctx->nbufs = REMOTE_SCALARS_INBUFS(sc) + - REMOTE_SCALARS_OUTBUFS(sc); - - if (ctx->nscalars) { - ctx->maps = kcalloc(ctx->nscalars, - sizeof(*ctx->maps), GFP_KERNEL); - if (!ctx->maps) { - kfree(ctx); - return ERR_PTR(-ENOMEM); - } - ctx->olaps = kcalloc(ctx->nscalars, - sizeof(*ctx->olaps), GFP_KERNEL); - if (!ctx->olaps) { - kfree(ctx->maps); - kfree(ctx); - return ERR_PTR(-ENOMEM); - } - ctx->args = args; - fastrpc_get_buff_overlaps(ctx); - } - - /* Released in fastrpc_context_put() */ - fastrpc_channel_ctx_get(cctx); - - ctx->sc = sc; - ctx->retval = -1; - ctx->pid = current->pid; - ctx->tgid = user->tgid; - ctx->cctx = cctx; - init_completion(&ctx->work); - INIT_WORK(&ctx->put_work, fastrpc_context_put_wq); - - spin_lock(&user->lock); - list_add_tail(&ctx->node, &user->pending); - spin_unlock(&user->lock); - - spin_lock_irqsave(&cctx->lock, flags); - ret = idr_alloc_cyclic(&cctx->ctx_idr, ctx, 1, - FASTRPC_CTX_MAX, GFP_ATOMIC); - if (ret < 0) { - spin_unlock_irqrestore(&cctx->lock, flags); - goto err_idr; - } - ctx->ctxid = ret << 4; - spin_unlock_irqrestore(&cctx->lock, flags); - - kref_init(&ctx->refcount); - - return ctx; -err_idr: - spin_lock(&user->lock); - list_del(&ctx->node); - spin_unlock(&user->lock); - fastrpc_channel_ctx_put(cctx); - kfree(ctx->maps); - kfree(ctx->olaps); - kfree(ctx); - - return ERR_PTR(ret); -} - -static struct sg_table * -fastrpc_map_dma_buf(struct dma_buf_attachment *attachment, - enum dma_data_direction dir) -{ - struct fastrpc_dma_buf_attachment *a = attachment->priv; - struct sg_table *table; - int ret; - - table = &a->sgt; - - ret = dma_map_sgtable(attachment->dev, table, dir, 0); - if (ret) - table = ERR_PTR(ret); - return table; -} - -static void fastrpc_unmap_dma_buf(struct dma_buf_attachment *attach, - struct sg_table *table, - enum dma_data_direction dir) -{ - dma_unmap_sgtable(attach->dev, table, dir, 0); -} - -static void fastrpc_release(struct dma_buf *dmabuf) -{ - struct fastrpc_buf *buffer = dmabuf->priv; - - fastrpc_buf_free(buffer); -} - -static int fastrpc_dma_buf_attach(struct dma_buf *dmabuf, - struct dma_buf_attachment *attachment) -{ - struct fastrpc_dma_buf_attachment *a; - struct fastrpc_buf *buffer = dmabuf->priv; - int ret; - - a = kzalloc(sizeof(*a), GFP_KERNEL); - if (!a) - return -ENOMEM; - - ret = dma_get_sgtable(buffer->dev, &a->sgt, buffer->virt, - FASTRPC_PHYS(buffer->phys), buffer->size); - if (ret < 0) { - dev_err(buffer->dev, "failed to get scatterlist from DMA API\n"); - kfree(a); - return -EINVAL; - } - - a->dev = attachment->dev; - INIT_LIST_HEAD(&a->node); - attachment->priv = a; - - mutex_lock(&buffer->lock); - list_add(&a->node, &buffer->attachments); - mutex_unlock(&buffer->lock); - - return 0; -} - -static void fastrpc_dma_buf_detatch(struct dma_buf *dmabuf, - struct dma_buf_attachment *attachment) -{ - struct fastrpc_dma_buf_attachment *a = attachment->priv; - struct fastrpc_buf *buffer = dmabuf->priv; - - mutex_lock(&buffer->lock); - list_del(&a->node); - mutex_unlock(&buffer->lock); - sg_free_table(&a->sgt); - kfree(a); -} - -static int fastrpc_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) -{ - struct fastrpc_buf *buf = dmabuf->priv; - - dma_buf_map_set_vaddr(map, buf->virt); - - return 0; -} - -static int fastrpc_mmap(struct dma_buf *dmabuf, - struct vm_area_struct *vma) -{ - struct fastrpc_buf *buf = dmabuf->priv; - size_t size = vma->vm_end - vma->vm_start; - - return dma_mmap_coherent(buf->dev, vma, buf->virt, - FASTRPC_PHYS(buf->phys), size); -} - -static const struct dma_buf_ops fastrpc_dma_buf_ops = { - .attach = fastrpc_dma_buf_attach, - .detach = fastrpc_dma_buf_detatch, - .map_dma_buf = fastrpc_map_dma_buf, - .unmap_dma_buf = fastrpc_unmap_dma_buf, - .mmap = fastrpc_mmap, - .vmap = fastrpc_vmap, - .release = fastrpc_release, -}; - -static int fastrpc_map_create(struct fastrpc_user *fl, int fd, - u64 len, u32 attr, struct fastrpc_map **ppmap) -{ - struct fastrpc_session_ctx *sess = fl->sctx; - struct fastrpc_map *map = NULL; - int err = 0; - - if (!fastrpc_map_find(fl, fd, ppmap)) - return 0; - - map = kzalloc(sizeof(*map), GFP_KERNEL); - if (!map) - return -ENOMEM; - - INIT_LIST_HEAD(&map->node); - map->fl = fl; - map->fd = fd; - map->buf = dma_buf_get(fd); - if (IS_ERR(map->buf)) { - err = PTR_ERR(map->buf); - goto get_err; - } - - map->attach = dma_buf_attach(map->buf, sess->dev); - if (IS_ERR(map->attach)) { - dev_err(sess->dev, "Failed to attach dmabuf\n"); - err = PTR_ERR(map->attach); - goto attach_err; - } - - map->table = dma_buf_map_attachment(map->attach, DMA_BIDIRECTIONAL); - if (IS_ERR(map->table)) { - err = PTR_ERR(map->table); - goto map_err; - } - - map->phys = sg_dma_address(map->table->sgl); - map->phys += ((u64)fl->sctx->sid << 32); - map->size = len; - map->va = sg_virt(map->table->sgl); - map->len = len; - kref_init(&map->refcount); - - if (attr & FASTRPC_ATTR_SECUREMAP) { - /* - * If subsystem VMIDs are defined in DTSI, then do - * hyp_assign from HLOS to those VM(s) - */ - unsigned int perms = BIT(QCOM_SCM_VMID_HLOS); - - map->attr = attr; - err = qcom_scm_assign_mem(map->phys, (u64)map->size, &perms, - fl->cctx->vmperms, fl->cctx->vmcount); - if (err) { - dev_err(sess->dev, "Failed to assign memory with phys 0x%llx size 0x%llx err %d", - map->phys, map->size, err); - goto map_err; - } - } - spin_lock(&fl->lock); - list_add_tail(&map->node, &fl->maps); - spin_unlock(&fl->lock); - *ppmap = map; - - return 0; - -map_err: - dma_buf_detach(map->buf, map->attach); -attach_err: - dma_buf_put(map->buf); -get_err: - kfree(map); - - return err; -} - -/* - * Fastrpc payload buffer with metadata looks like: - * - * >>>>>> START of METADATA <<<<<<<<< - * +---------------------------------+ - * | Arguments | - * | type:(union fastrpc_remote_arg)| - * | (0 - N) | - * +---------------------------------+ - * | Invoke Buffer list | - * | type:(struct fastrpc_invoke_buf)| - * | (0 - N) | - * +---------------------------------+ - * | Page info list | - * | type:(struct fastrpc_phy_page) | - * | (0 - N) | - * +---------------------------------+ - * | Optional info | - * |(can be specific to SoC/Firmware)| - * +---------------------------------+ - * >>>>>>>> END of METADATA <<<<<<<<< - * +---------------------------------+ - * | Inline ARGS | - * | (0-N) | - * +---------------------------------+ - */ - -static int fastrpc_get_meta_size(struct fastrpc_invoke_ctx *ctx) -{ - int size = 0; - - size = (sizeof(struct fastrpc_remote_buf) + - sizeof(struct fastrpc_invoke_buf) + - sizeof(struct fastrpc_phy_page)) * ctx->nscalars + - sizeof(u64) * FASTRPC_MAX_FDLIST + - sizeof(u32) * FASTRPC_MAX_CRCLIST; - - return size; -} - -static u64 fastrpc_get_payload_size(struct fastrpc_invoke_ctx *ctx, int metalen) -{ - u64 size = 0; - int oix; - - size = ALIGN(metalen, FASTRPC_ALIGN); - for (oix = 0; oix < ctx->nbufs; oix++) { - int i = ctx->olaps[oix].raix; - - if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1) { - - if (ctx->olaps[oix].offset == 0) - size = ALIGN(size, FASTRPC_ALIGN); - - size += (ctx->olaps[oix].mend - ctx->olaps[oix].mstart); - } - } - - return size; -} - -static int fastrpc_create_maps(struct fastrpc_invoke_ctx *ctx) -{ - struct device *dev = ctx->fl->sctx->dev; - int i, err; - - for (i = 0; i < ctx->nscalars; ++i) { - - if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1 || - ctx->args[i].length == 0) - continue; - - err = fastrpc_map_create(ctx->fl, ctx->args[i].fd, - ctx->args[i].length, ctx->args[i].attr, &ctx->maps[i]); - if (err) { - dev_err(dev, "Error Creating map %d\n", err); - return -EINVAL; - } - - } - return 0; -} - -static struct fastrpc_invoke_buf *fastrpc_invoke_buf_start(union fastrpc_remote_arg *pra, int len) -{ - return (struct fastrpc_invoke_buf *)(&pra[len]); -} - -static struct fastrpc_phy_page *fastrpc_phy_page_start(struct fastrpc_invoke_buf *buf, int len) -{ - return (struct fastrpc_phy_page *)(&buf[len]); -} - -static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) -{ - struct device *dev = ctx->fl->sctx->dev; - union fastrpc_remote_arg *rpra; - struct fastrpc_invoke_buf *list; - struct fastrpc_phy_page *pages; - int inbufs, i, oix, err = 0; - u64 len, rlen, pkt_size; - u64 pg_start, pg_end; - uintptr_t args; - int metalen; - - inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); - metalen = fastrpc_get_meta_size(ctx); - pkt_size = fastrpc_get_payload_size(ctx, metalen); - - err = fastrpc_create_maps(ctx); - if (err) - return err; - - ctx->msg_sz = pkt_size; - - err = fastrpc_buf_alloc(ctx->fl, dev, pkt_size, &ctx->buf); - if (err) - return err; - - rpra = ctx->buf->virt; - list = fastrpc_invoke_buf_start(rpra, ctx->nscalars); - pages = fastrpc_phy_page_start(list, ctx->nscalars); - args = (uintptr_t)ctx->buf->virt + metalen; - rlen = pkt_size - metalen; - ctx->rpra = rpra; - - for (oix = 0; oix < ctx->nbufs; ++oix) { - int mlen; - - i = ctx->olaps[oix].raix; - len = ctx->args[i].length; - - rpra[i].buf.pv = 0; - rpra[i].buf.len = len; - list[i].num = len ? 1 : 0; - list[i].pgidx = i; - - if (!len) - continue; - - if (ctx->maps[i]) { - struct vm_area_struct *vma = NULL; - - rpra[i].buf.pv = (u64) ctx->args[i].ptr; - pages[i].addr = ctx->maps[i]->phys; - - mmap_read_lock(current->mm); - vma = find_vma(current->mm, ctx->args[i].ptr); - if (vma) - pages[i].addr += ctx->args[i].ptr - - vma->vm_start; - mmap_read_unlock(current->mm); - - pg_start = (ctx->args[i].ptr & PAGE_MASK) >> PAGE_SHIFT; - pg_end = ((ctx->args[i].ptr + len - 1) & PAGE_MASK) >> - PAGE_SHIFT; - pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - - } else { - - if (ctx->olaps[oix].offset == 0) { - rlen -= ALIGN(args, FASTRPC_ALIGN) - args; - args = ALIGN(args, FASTRPC_ALIGN); - } - - mlen = ctx->olaps[oix].mend - ctx->olaps[oix].mstart; - - if (rlen < mlen) - goto bail; - - rpra[i].buf.pv = args - ctx->olaps[oix].offset; - pages[i].addr = ctx->buf->phys - - ctx->olaps[oix].offset + - (pkt_size - rlen); - pages[i].addr = pages[i].addr & PAGE_MASK; - - pg_start = (args & PAGE_MASK) >> PAGE_SHIFT; - pg_end = ((args + len - 1) & PAGE_MASK) >> PAGE_SHIFT; - pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - args = args + mlen; - rlen -= mlen; - } - - if (i < inbufs && !ctx->maps[i]) { - void *dst = (void *)(uintptr_t)rpra[i].buf.pv; - void *src = (void *)(uintptr_t)ctx->args[i].ptr; - - if (!kernel) { - if (copy_from_user(dst, (void __user *)src, - len)) { - err = -EFAULT; - goto bail; - } - } else { - memcpy(dst, src, len); - } - } - } - - for (i = ctx->nbufs; i < ctx->nscalars; ++i) { - list[i].num = ctx->args[i].length ? 1 : 0; - list[i].pgidx = i; - if (ctx->maps[i]) { - pages[i].addr = ctx->maps[i]->phys; - pages[i].size = ctx->maps[i]->size; - } - rpra[i].dma.fd = ctx->args[i].fd; - rpra[i].dma.len = ctx->args[i].length; - rpra[i].dma.offset = (u64) ctx->args[i].ptr; - } - -bail: - if (err) - dev_err(dev, "Error: get invoke args failed:%d\n", err); - - return err; -} - -static int fastrpc_put_args(struct fastrpc_invoke_ctx *ctx, - u32 kernel) -{ - union fastrpc_remote_arg *rpra = ctx->rpra; - struct fastrpc_user *fl = ctx->fl; - struct fastrpc_map *mmap = NULL; - struct fastrpc_invoke_buf *list; - struct fastrpc_phy_page *pages; - u64 *fdlist; - int i, inbufs, outbufs, handles; - - inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); - outbufs = REMOTE_SCALARS_OUTBUFS(ctx->sc); - handles = REMOTE_SCALARS_INHANDLES(ctx->sc) + REMOTE_SCALARS_OUTHANDLES(ctx->sc); - list = fastrpc_invoke_buf_start(rpra, ctx->nscalars); - pages = fastrpc_phy_page_start(list, ctx->nscalars); - fdlist = (uint64_t *)(pages + inbufs + outbufs + handles); - - for (i = inbufs; i < ctx->nbufs; ++i) { -<<<<<<< - if (!ctx->maps[i]) { - void *src = (void *)(uintptr_t)rpra[i].buf.pv; - void *dst = (void *)(uintptr_t)ctx->args[i].ptr; - u64 len = rpra[i].buf.len; -======= - void *src = (void *)(uintptr_t)rpra[i].pv; - void *dst = (void *)(uintptr_t)ctx->args[i].ptr; - u64 len = rpra[i].len; ->>>>>>> - - if (!kernel) { - if (copy_to_user((void __user *)dst, src, len)) - return -EFAULT; - } else { - memcpy(dst, src, len); - } - } - - for (i = 0; i < FASTRPC_MAX_FDLIST; i++) { - if (!fdlist[i]) - break; - if (!fastrpc_map_lookup(fl, (int)fdlist[i], &mmap)) - fastrpc_map_put(mmap); - } - - return 0; -} - -static int fastrpc_invoke_send(struct fastrpc_session_ctx *sctx, - struct fastrpc_invoke_ctx *ctx, - u32 kernel, uint32_t handle) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_user *fl = ctx->fl; - struct fastrpc_msg *msg = &ctx->msg; - int ret; - - cctx = fl->cctx; - msg->pid = fl->tgid; - msg->tid = current->pid; - - if (kernel) - msg->pid = 0; - - msg->ctx = ctx->ctxid | fl->pd; - msg->handle = handle; - msg->sc = ctx->sc; - msg->addr = ctx->buf ? ctx->buf->phys : 0; - msg->size = roundup(ctx->msg_sz, PAGE_SIZE); - fastrpc_context_get(ctx); - - ret = rpmsg_send(cctx->rpdev->ept, (void *)msg, sizeof(*msg)); - - if (ret) - fastrpc_context_put(ctx); - - return ret; - -} - -static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel, - u32 handle, u32 sc, - struct fastrpc_invoke_args *args) -{ - struct fastrpc_invoke_ctx *ctx = NULL; - int err = 0; - - if (!fl->sctx) - return -EINVAL; - - if (!fl->cctx->rpdev) - return -EPIPE; - - if (handle == FASTRPC_INIT_HANDLE && !kernel) { - dev_warn_ratelimited(fl->sctx->dev, "user app trying to send a kernel RPC message (%d)\n", handle); - return -EPERM; - } - - ctx = fastrpc_context_alloc(fl, kernel, sc, args); - if (IS_ERR(ctx)) - return PTR_ERR(ctx); - - if (ctx->nscalars) { - err = fastrpc_get_args(kernel, ctx); - if (err) - goto bail; - } - - /* make sure that all CPU memory writes are seen by DSP */ - dma_wmb(); - /* Send invoke buffer to remote dsp */ - err = fastrpc_invoke_send(fl->sctx, ctx, kernel, handle); - if (err) - goto bail; - - if (kernel) { - if (!wait_for_completion_timeout(&ctx->work, 10 * HZ)) - err = -ETIMEDOUT; - } else { - err = wait_for_completion_interruptible(&ctx->work); - } - - if (err) - goto bail; - - /* Check the response from remote dsp */ - err = ctx->retval; - if (err) - goto bail; - - if (ctx->nscalars) { - /* make sure that all memory writes by DSP are seen by CPU */ - dma_rmb(); - /* populate all the output buffers with results */ - err = fastrpc_put_args(ctx, kernel); - if (err) - goto bail; - } - -bail: - if (err != -ERESTARTSYS && err != -ETIMEDOUT) { - /* We are done with this compute context */ - spin_lock(&fl->lock); - list_del(&ctx->node); - spin_unlock(&fl->lock); - fastrpc_context_put(ctx); - } - if (err) - dev_dbg(fl->sctx->dev, "Error: Invoke Failed %d\n", err); - - return err; -} - -static bool is_session_rejected(struct fastrpc_user *fl, bool unsigned_pd_request) -{ - /* Check if the device node is non-secure and channel is secure*/ - if (!fl->is_secure_dev && fl->cctx->secure) { - /* - * Allow untrusted applications to offload only to Unsigned PD when - * channel is configured as secure and block untrusted apps on channel - * that does not support unsigned PD offload - */ - if (!fl->cctx->unsigned_support || !unsigned_pd_request) { - dev_err(&fl->cctx->rpdev->dev, "Error: Untrusted application trying to offload to signed PD"); - return true; - } - } - - return false; -} - -static int fastrpc_init_create_process(struct fastrpc_user *fl, - char __user *argp) -{ - struct fastrpc_init_create init; - struct fastrpc_invoke_args *args; - struct fastrpc_phy_page pages[1]; - struct fastrpc_map *map = NULL; - struct fastrpc_buf *imem = NULL; - int memlen; - int err; - struct { - int pgid; - u32 namelen; - u32 filelen; - u32 pageslen; - u32 attrs; - u32 siglen; - } inbuf; - u32 sc; - bool unsigned_module = false; - - args = kcalloc(FASTRPC_CREATE_PROCESS_NARGS, sizeof(*args), GFP_KERNEL); - if (!args) - return -ENOMEM; - - if (copy_from_user(&init, argp, sizeof(init))) { - err = -EFAULT; - goto err; - } - - if (init.attrs & FASTRPC_MODE_UNSIGNED_MODULE) - unsigned_module = true; - - if (is_session_rejected(fl, unsigned_module)) { - err = -ECONNREFUSED; - goto err; - } - - if (init.filelen > INIT_FILELEN_MAX) { - err = -EINVAL; - goto err; - } - - inbuf.pgid = fl->tgid; - inbuf.namelen = strlen(current->comm) + 1; - inbuf.filelen = init.filelen; - inbuf.pageslen = 1; - inbuf.attrs = init.attrs; - inbuf.siglen = init.siglen; - fl->pd = USER_PD; - - if (init.filelen && init.filefd) { - err = fastrpc_map_create(fl, init.filefd, init.filelen, 0, &map); - if (err) - goto err; - } - - memlen = ALIGN(max(INIT_FILELEN_MAX, (int)init.filelen * 4), - 1024 * 1024); - err = fastrpc_buf_alloc(fl, fl->sctx->dev, memlen, - &imem); - if (err) - goto err_alloc; - - fl->init_mem = imem; - args[0].ptr = (u64)(uintptr_t)&inbuf; - args[0].length = sizeof(inbuf); - args[0].fd = -1; - - args[1].ptr = (u64)(uintptr_t)current->comm; - args[1].length = inbuf.namelen; - args[1].fd = -1; - - args[2].ptr = (u64) init.file; - args[2].length = inbuf.filelen; - args[2].fd = init.filefd; - - pages[0].addr = imem->phys; - pages[0].size = imem->size; - - args[3].ptr = (u64)(uintptr_t) pages; - args[3].length = 1 * sizeof(*pages); - args[3].fd = -1; - - args[4].ptr = (u64)(uintptr_t)&inbuf.attrs; - args[4].length = sizeof(inbuf.attrs); - args[4].fd = -1; - - args[5].ptr = (u64)(uintptr_t) &inbuf.siglen; - args[5].length = sizeof(inbuf.siglen); - args[5].fd = -1; - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE, 4, 0); - if (init.attrs) - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE_ATTR, 6, 0); - - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, args); - if (err) - goto err_invoke; - - kfree(args); - - return 0; - -err_invoke: - fl->init_mem = NULL; - fastrpc_buf_free(imem); -err_alloc: - if (map) { - spin_lock(&fl->lock); - list_del(&map->node); - spin_unlock(&fl->lock); - fastrpc_map_put(map); - } -err: - kfree(args); - - return err; -} - -static struct fastrpc_session_ctx *fastrpc_session_alloc( - struct fastrpc_channel_ctx *cctx) -{ - struct fastrpc_session_ctx *session = NULL; - unsigned long flags; - int i; - - spin_lock_irqsave(&cctx->lock, flags); - for (i = 0; i < cctx->sesscount; i++) { - if (!cctx->session[i].used && cctx->session[i].valid) { - cctx->session[i].used = true; - session = &cctx->session[i]; - break; - } - } - spin_unlock_irqrestore(&cctx->lock, flags); - - return session; -} - -static void fastrpc_session_free(struct fastrpc_channel_ctx *cctx, - struct fastrpc_session_ctx *session) -{ - unsigned long flags; - - spin_lock_irqsave(&cctx->lock, flags); - session->used = false; - spin_unlock_irqrestore(&cctx->lock, flags); -} - -static int fastrpc_release_current_dsp_process(struct fastrpc_user *fl) -{ - struct fastrpc_invoke_args args[1]; - int tgid = 0; - u32 sc; - - tgid = fl->tgid; - args[0].ptr = (u64)(uintptr_t) &tgid; - args[0].length = sizeof(tgid); - args[0].fd = -1; - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_RELEASE, 1, 0); - - return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, &args[0]); -} - -static int fastrpc_device_release(struct inode *inode, struct file *file) -{ - struct fastrpc_user *fl = (struct fastrpc_user *)file->private_data; - struct fastrpc_channel_ctx *cctx = fl->cctx; - struct fastrpc_invoke_ctx *ctx, *n; - struct fastrpc_map *map, *m; - struct fastrpc_buf *buf, *b; - unsigned long flags; - - fastrpc_release_current_dsp_process(fl); - - spin_lock_irqsave(&cctx->lock, flags); - list_del(&fl->user); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (fl->init_mem) - fastrpc_buf_free(fl->init_mem); - - list_for_each_entry_safe(ctx, n, &fl->pending, node) { - list_del(&ctx->node); - fastrpc_context_put(ctx); - } - - list_for_each_entry_safe(map, m, &fl->maps, node) { - list_del(&map->node); - fastrpc_map_put(map); - } - - list_for_each_entry_safe(buf, b, &fl->mmaps, node) { - list_del(&buf->node); - fastrpc_buf_free(buf); - } - - fastrpc_session_free(cctx, fl->sctx); - fastrpc_channel_ctx_put(cctx); - - mutex_destroy(&fl->mutex); - kfree(fl); - file->private_data = NULL; - - return 0; -} - -static int fastrpc_device_open(struct inode *inode, struct file *filp) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_device *fdevice; - struct fastrpc_user *fl = NULL; - unsigned long flags; - - fdevice = miscdev_to_fdevice(filp->private_data); - cctx = fdevice->cctx; - - fl = kzalloc(sizeof(*fl), GFP_KERNEL); - if (!fl) - return -ENOMEM; - - /* Released in fastrpc_device_release() */ - fastrpc_channel_ctx_get(cctx); - - filp->private_data = fl; - spin_lock_init(&fl->lock); - mutex_init(&fl->mutex); - INIT_LIST_HEAD(&fl->pending); - INIT_LIST_HEAD(&fl->maps); - INIT_LIST_HEAD(&fl->mmaps); - INIT_LIST_HEAD(&fl->user); - fl->tgid = current->tgid; - fl->cctx = cctx; - fl->is_secure_dev = fdevice->secure; - - fl->sctx = fastrpc_session_alloc(cctx); - if (!fl->sctx) { - dev_err(&cctx->rpdev->dev, "No session available\n"); - mutex_destroy(&fl->mutex); - kfree(fl); - - return -EBUSY; - } - - spin_lock_irqsave(&cctx->lock, flags); - list_add_tail(&fl->user, &cctx->users); - spin_unlock_irqrestore(&cctx->lock, flags); - - return 0; -} - -static int fastrpc_dmabuf_alloc(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_alloc_dma_buf bp; - DEFINE_DMA_BUF_EXPORT_INFO(exp_info); - struct fastrpc_buf *buf = NULL; - int err; - - if (copy_from_user(&bp, argp, sizeof(bp))) - return -EFAULT; - - err = fastrpc_buf_alloc(fl, fl->sctx->dev, bp.size, &buf); - if (err) - return err; - exp_info.ops = &fastrpc_dma_buf_ops; - exp_info.size = bp.size; - exp_info.flags = O_RDWR; - exp_info.priv = buf; - buf->dmabuf = dma_buf_export(&exp_info); - if (IS_ERR(buf->dmabuf)) { - err = PTR_ERR(buf->dmabuf); - fastrpc_buf_free(buf); - return err; - } - - bp.fd = dma_buf_fd(buf->dmabuf, O_ACCMODE); - if (bp.fd < 0) { - dma_buf_put(buf->dmabuf); - return -EINVAL; - } - - if (copy_to_user(argp, &bp, sizeof(bp))) { - /* - * The usercopy failed, but we can't do much about it, as - * dma_buf_fd() already called fd_install() and made the - * file descriptor accessible for the current process. It - * might already be closed and dmabuf no longer valid when - * we reach this point. Therefore "leak" the fd and rely on - * the process exit path to do any required cleanup. - */ - return -EFAULT; - } - - return 0; -} - -static int fastrpc_init_attach(struct fastrpc_user *fl, int pd) -{ - struct fastrpc_invoke_args args[1]; - int tgid = fl->tgid; - u32 sc; - - args[0].ptr = (u64)(uintptr_t) &tgid; - args[0].length = sizeof(tgid); - args[0].fd = -1; - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_ATTACH, 1, 0); - fl->pd = pd; - - return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, &args[0]); -} - -static int fastrpc_invoke(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args *args = NULL; - struct fastrpc_invoke inv; - u32 nscalars; - int err; - - if (copy_from_user(&inv, argp, sizeof(inv))) - return -EFAULT; - - /* nscalars is truncated here to max supported value */ - nscalars = REMOTE_SCALARS_LENGTH(inv.sc); - if (nscalars) { - args = kcalloc(nscalars, sizeof(*args), GFP_KERNEL); - if (!args) - return -ENOMEM; - - if (copy_from_user(args, (void __user *)(uintptr_t)inv.args, - nscalars * sizeof(*args))) { - kfree(args); - return -EFAULT; - } - } - - err = fastrpc_internal_invoke(fl, false, inv.handle, inv.sc, args); - kfree(args); - - return err; -} - -static int fastrpc_get_info_from_dsp(struct fastrpc_user *fl, uint32_t *dsp_attr_buf, - uint32_t dsp_attr_buf_len) -{ - struct fastrpc_invoke_args args[2] = { 0 }; - - /* Capability filled in userspace */ - dsp_attr_buf[0] = 0; - - args[0].ptr = (u64)(uintptr_t)&dsp_attr_buf_len; - args[0].length = sizeof(dsp_attr_buf_len); - args[0].fd = -1; - args[1].ptr = (u64)(uintptr_t)&dsp_attr_buf[1]; - args[1].length = dsp_attr_buf_len; - args[1].fd = -1; - fl->pd = 1; - - return fastrpc_internal_invoke(fl, true, FASTRPC_DSP_UTILITIES_HANDLE, - FASTRPC_SCALARS(0, 1, 1), args); -} - -static int fastrpc_get_info_from_kernel(struct fastrpc_ioctl_capability *cap, - struct fastrpc_user *fl) -{ - struct fastrpc_channel_ctx *cctx = fl->cctx; - uint32_t attribute_id = cap->attribute_id; - uint32_t *dsp_attributes; - unsigned long flags; - uint32_t domain = cap->domain; - int err; - - spin_lock_irqsave(&cctx->lock, flags); - /* check if we already have queried dsp for attributes */ - if (cctx->valid_attributes) { - spin_unlock_irqrestore(&cctx->lock, flags); - goto done; - } - spin_unlock_irqrestore(&cctx->lock, flags); - - dsp_attributes = kzalloc(FASTRPC_MAX_DSP_ATTRIBUTES_LEN, GFP_KERNEL); - if (!dsp_attributes) - return -ENOMEM; - - err = fastrpc_get_info_from_dsp(fl, dsp_attributes, FASTRPC_MAX_DSP_ATTRIBUTES_LEN); - if (err == DSP_UNSUPPORTED_API) { - dev_info(&cctx->rpdev->dev, - "Warning: DSP capabilities not supported on domain: %d\n", domain); - kfree(dsp_attributes); - return -EOPNOTSUPP; - } else if (err) { - dev_err(&cctx->rpdev->dev, "Error: dsp information is incorrect err: %d\n", err); - kfree(dsp_attributes); - return err; - } - - spin_lock_irqsave(&cctx->lock, flags); - memcpy(cctx->dsp_attributes, dsp_attributes, FASTRPC_MAX_DSP_ATTRIBUTES_LEN); - cctx->valid_attributes = true; - spin_unlock_irqrestore(&cctx->lock, flags); - kfree(dsp_attributes); -done: - cap->capability = cctx->dsp_attributes[attribute_id]; - return 0; -} - -static int fastrpc_get_dsp_info(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_ioctl_capability cap = {0}; - int err = 0; - - if (copy_from_user(&cap, argp, sizeof(cap))) - return -EFAULT; - - cap.capability = 0; - if (cap.domain >= FASTRPC_DEV_MAX) { - dev_err(&fl->cctx->rpdev->dev, "Error: Invalid domain id:%d, err:%d\n", - cap.domain, err); - return -ECHRNG; - } - - /* Fastrpc Capablities does not support modem domain */ - if (cap.domain == MDSP_DOMAIN_ID) { - dev_err(&fl->cctx->rpdev->dev, "Error: modem not supported %d\n", err); - return -ECHRNG; - } - - if (cap.attribute_id >= FASTRPC_MAX_DSP_ATTRIBUTES) { - dev_err(&fl->cctx->rpdev->dev, "Error: invalid attribute: %d, err: %d\n", - cap.attribute_id, err); - return -EOVERFLOW; - } - - err = fastrpc_get_info_from_kernel(&cap, fl); - if (err) - return err; - - if (copy_to_user(argp, &cap.capability, sizeof(cap.capability))) - return -EFAULT; - - return 0; -} - -static int fastrpc_req_munmap_impl(struct fastrpc_user *fl, - struct fastrpc_req_munmap *req) -{ - struct fastrpc_invoke_args args[1] = { [0] = { 0 } }; - struct fastrpc_buf *buf, *b; - struct fastrpc_munmap_req_msg req_msg; - struct device *dev = fl->sctx->dev; - int err; - u32 sc; - - spin_lock(&fl->lock); - list_for_each_entry_safe(buf, b, &fl->mmaps, node) { - if ((buf->raddr == req->vaddrout) && (buf->size == req->size)) - break; - buf = NULL; - } - spin_unlock(&fl->lock); - - if (!buf) { - dev_err(dev, "mmap not in list\n"); - return -EINVAL; - } - - req_msg.pgid = fl->tgid; - req_msg.size = buf->size; - req_msg.vaddr = buf->raddr; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MUNMAP, 1, 0); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - if (!err) { - dev_dbg(dev, "unmmap\tpt 0x%09lx OK\n", buf->raddr); - spin_lock(&fl->lock); - list_del(&buf->node); - spin_unlock(&fl->lock); - fastrpc_buf_free(buf); - } else { - dev_err(dev, "unmmap\tpt 0x%09lx ERROR\n", buf->raddr); - } - - return err; -} - -static int fastrpc_req_munmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_req_munmap req; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - return fastrpc_req_munmap_impl(fl, &req); -} - -static int fastrpc_req_mmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args args[3] = { [0 ... 2] = { 0 } }; - struct fastrpc_buf *buf = NULL; - struct fastrpc_mmap_req_msg req_msg; - struct fastrpc_mmap_rsp_msg rsp_msg; - struct fastrpc_req_munmap req_unmap; - struct fastrpc_phy_page pages; - struct fastrpc_req_mmap req; - struct device *dev = fl->sctx->dev; - int err; - u32 sc; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - if (req.flags != ADSP_MMAP_ADD_PAGES) { - dev_err(dev, "flag not supported 0x%x\n", req.flags); - return -EINVAL; - } - - if (req.vaddrin) { - dev_err(dev, "adding user allocated pages is not supported\n"); - return -EINVAL; - } - - err = fastrpc_buf_alloc(fl, fl->sctx->dev, req.size, &buf); - if (err) { - dev_err(dev, "failed to allocate buffer\n"); - return err; - } - - req_msg.pgid = fl->tgid; - req_msg.flags = req.flags; - req_msg.vaddr = req.vaddrin; - req_msg.num = sizeof(pages); - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - pages.addr = buf->phys; - pages.size = buf->size; - - args[1].ptr = (u64) (uintptr_t) &pages; - args[1].length = sizeof(pages); - - args[2].ptr = (u64) (uintptr_t) &rsp_msg; - args[2].length = sizeof(rsp_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MMAP, 2, 1); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - if (err) { - dev_err(dev, "mmap error (len 0x%08llx)\n", buf->size); - goto err_invoke; - } - - /* update the buffer to be able to deallocate the memory on the DSP */ - buf->raddr = (uintptr_t) rsp_msg.vaddr; - - /* let the client know the address to use */ - req.vaddrout = rsp_msg.vaddr; - - spin_lock(&fl->lock); - list_add_tail(&buf->node, &fl->mmaps); - spin_unlock(&fl->lock); - - if (copy_to_user((void __user *)argp, &req, sizeof(req))) { - /* unmap the memory and release the buffer */ - req_unmap.vaddrout = buf->raddr; - req_unmap.size = buf->size; - fastrpc_req_munmap_impl(fl, &req_unmap); - return -EFAULT; - } - - dev_dbg(dev, "mmap\t\tpt 0x%09lx OK [len 0x%08llx]\n", - buf->raddr, buf->size); - - return 0; - -err_invoke: - fastrpc_buf_free(buf); - - return err; -} - -static int fastrpc_req_mem_unmap_impl(struct fastrpc_user *fl, struct fastrpc_mem_unmap *req) -{ - struct fastrpc_invoke_args args[1] = { [0] = { 0 } }; - struct fastrpc_map *map = NULL, *m; - struct fastrpc_mem_unmap_req_msg req_msg = { 0 }; - int err = 0; - u32 sc; - struct device *dev = fl->sctx->dev; - - spin_lock(&fl->lock); - list_for_each_entry_safe(map, m, &fl->maps, node) { - if ((req->fd < 0 || map->fd == req->fd) && (map->raddr == req->vaddr)) - break; - map = NULL; - } - - spin_unlock(&fl->lock); - - if (!map) { - dev_err(dev, "map not in list\n"); - return -EINVAL; - } - - req_msg.pgid = fl->tgid; - req_msg.len = map->len; - req_msg.vaddrin = map->raddr; - req_msg.fd = map->fd; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_UNMAP, 1, 0); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - fastrpc_map_put(map); - if (err) - dev_err(dev, "unmmap\tpt fd = %d, 0x%09llx error\n", map->fd, map->raddr); - - return err; -} - -static int fastrpc_req_mem_unmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_mem_unmap req; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - return fastrpc_req_mem_unmap_impl(fl, &req); -} - -static int fastrpc_req_mem_map(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args args[4] = { [0 ... 3] = { 0 } }; - struct fastrpc_mem_map_req_msg req_msg = { 0 }; - struct fastrpc_mmap_rsp_msg rsp_msg = { 0 }; - struct fastrpc_mem_unmap req_unmap = { 0 }; - struct fastrpc_phy_page pages = { 0 }; - struct fastrpc_mem_map req; - struct device *dev = fl->sctx->dev; - struct fastrpc_map *map = NULL; - int err; - u32 sc; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - /* create SMMU mapping */ - err = fastrpc_map_create(fl, req.fd, req.length, 0, &map); - if (err) { - dev_err(dev, "failed to map buffer, fd = %d\n", req.fd); - return err; - } - - req_msg.pgid = fl->tgid; - req_msg.fd = req.fd; - req_msg.offset = req.offset; - req_msg.vaddrin = req.vaddrin; - map->va = (void *) (uintptr_t) req.vaddrin; - req_msg.flags = req.flags; - req_msg.num = sizeof(pages); - req_msg.data_len = 0; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - pages.addr = map->phys; - pages.size = map->size; - - args[1].ptr = (u64) (uintptr_t) &pages; - args[1].length = sizeof(pages); - - args[2].ptr = (u64) (uintptr_t) &pages; - args[2].length = 0; - - args[3].ptr = (u64) (uintptr_t) &rsp_msg; - args[3].length = sizeof(rsp_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_MAP, 3, 1); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, &args[0]); - if (err) { - dev_err(dev, "mem mmap error, fd %d, vaddr %llx, size %lld\n", - req.fd, req.vaddrin, map->size); - goto err_invoke; - } - - /* update the buffer to be able to deallocate the memory on the DSP */ - map->raddr = rsp_msg.vaddr; - - /* let the client know the address to use */ - req.vaddrout = rsp_msg.vaddr; - - if (copy_to_user((void __user *)argp, &req, sizeof(req))) { - /* unmap the memory and release the buffer */ - req_unmap.vaddr = (uintptr_t) rsp_msg.vaddr; - req_unmap.length = map->size; - fastrpc_req_mem_unmap_impl(fl, &req_unmap); - return -EFAULT; - } - - return 0; - -err_invoke: - fastrpc_map_put(map); - - return err; -} - -static long fastrpc_device_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - struct fastrpc_user *fl = (struct fastrpc_user *)file->private_data; - char __user *argp = (char __user *)arg; - int err; - - switch (cmd) { - case FASTRPC_IOCTL_INVOKE: - err = fastrpc_invoke(fl, argp); - break; - case FASTRPC_IOCTL_INIT_ATTACH: - err = fastrpc_init_attach(fl, AUDIO_PD); - break; - case FASTRPC_IOCTL_INIT_ATTACH_SNS: - err = fastrpc_init_attach(fl, SENSORS_PD); - break; - case FASTRPC_IOCTL_INIT_CREATE: - err = fastrpc_init_create_process(fl, argp); - break; - case FASTRPC_IOCTL_ALLOC_DMA_BUFF: - err = fastrpc_dmabuf_alloc(fl, argp); - break; - case FASTRPC_IOCTL_MMAP: - err = fastrpc_req_mmap(fl, argp); - break; - case FASTRPC_IOCTL_MUNMAP: - err = fastrpc_req_munmap(fl, argp); - break; - case FASTRPC_IOCTL_MEM_MAP: - err = fastrpc_req_mem_map(fl, argp); - break; - case FASTRPC_IOCTL_MEM_UNMAP: - err = fastrpc_req_mem_unmap(fl, argp); - break; - case FASTRPC_IOCTL_GET_DSP_INFO: - err = fastrpc_get_dsp_info(fl, argp); - break; - default: - err = -ENOTTY; - break; - } - - return err; -} - -static const struct file_operations fastrpc_fops = { - .open = fastrpc_device_open, - .release = fastrpc_device_release, - .unlocked_ioctl = fastrpc_device_ioctl, - .compat_ioctl = fastrpc_device_ioctl, -}; - -static int fastrpc_cb_probe(struct platform_device *pdev) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_session_ctx *sess; - struct device *dev = &pdev->dev; - int i, sessions = 0; - unsigned long flags; - int rc; - - cctx = dev_get_drvdata(dev->parent); - if (!cctx) - return -EINVAL; - - of_property_read_u32(dev->of_node, "qcom,nsessions", &sessions); - - spin_lock_irqsave(&cctx->lock, flags); - sess = &cctx->session[cctx->sesscount]; - sess->used = false; - sess->valid = true; - sess->dev = dev; - dev_set_drvdata(dev, sess); - - if (of_property_read_u32(dev->of_node, "reg", &sess->sid)) - dev_info(dev, "FastRPC Session ID not specified in DT\n"); - - if (sessions > 0) { - struct fastrpc_session_ctx *dup_sess; - - for (i = 1; i < sessions; i++) { - if (cctx->sesscount++ >= FASTRPC_MAX_SESSIONS) - break; - dup_sess = &cctx->session[cctx->sesscount]; - memcpy(dup_sess, sess, sizeof(*dup_sess)); - } - } - cctx->sesscount++; - spin_unlock_irqrestore(&cctx->lock, flags); - rc = dma_set_mask(dev, DMA_BIT_MASK(32)); - if (rc) { - dev_err(dev, "32-bit DMA enable failed\n"); - return rc; - } - - return 0; -} - -static int fastrpc_cb_remove(struct platform_device *pdev) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(pdev->dev.parent); - struct fastrpc_session_ctx *sess = dev_get_drvdata(&pdev->dev); - unsigned long flags; - int i; - - spin_lock_irqsave(&cctx->lock, flags); - for (i = 1; i < FASTRPC_MAX_SESSIONS; i++) { - if (cctx->session[i].sid == sess->sid) { - cctx->session[i].valid = false; - cctx->sesscount--; - } - } - spin_unlock_irqrestore(&cctx->lock, flags); - - return 0; -} - -static const struct of_device_id fastrpc_match_table[] = { - { .compatible = "qcom,fastrpc-compute-cb", }, - {} -}; - -static struct platform_driver fastrpc_cb_driver = { - .probe = fastrpc_cb_probe, - .remove = fastrpc_cb_remove, - .driver = { - .name = "qcom,fastrpc-cb", - .of_match_table = fastrpc_match_table, - .suppress_bind_attrs = true, - }, -}; - -static int fastrpc_device_register(struct device *dev, struct fastrpc_channel_ctx *cctx, - bool is_secured, const char *domain) -{ - struct fastrpc_device *fdev; - int err; - - fdev = devm_kzalloc(dev, sizeof(*fdev), GFP_KERNEL); - if (!fdev) - return -ENOMEM; - - fdev->secure = is_secured; - fdev->cctx = cctx; - fdev->miscdev.minor = MISC_DYNAMIC_MINOR; - fdev->miscdev.fops = &fastrpc_fops; - fdev->miscdev.name = devm_kasprintf(dev, GFP_KERNEL, "fastrpc-%s%s", - domain, is_secured ? "-secure" : ""); - err = misc_register(&fdev->miscdev); - if (!err) { - if (is_secured) - cctx->secure_fdevice = fdev; - else - cctx->fdevice = fdev; - } - - return err; -} - -static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) -{ - struct device *rdev = &rpdev->dev; - struct fastrpc_channel_ctx *data; - int i, err, domain_id = -1, vmcount; - const char *domain; - bool secure_dsp; - unsigned int vmids[FASTRPC_MAX_VMIDS]; - - err = of_property_read_string(rdev->of_node, "label", &domain); - if (err) { - dev_info(rdev, "FastRPC Domain not specified in DT\n"); - return err; - } - - for (i = 0; i <= CDSP_DOMAIN_ID; i++) { - if (!strcmp(domains[i], domain)) { - domain_id = i; - break; - } - } - - if (domain_id < 0) { - dev_info(rdev, "FastRPC Invalid Domain ID %d\n", domain_id); - return -EINVAL; - } - - vmcount = of_property_read_variable_u32_array(rdev->of_node, - "qcom,vmids", &vmids[0], 0, FASTRPC_MAX_VMIDS); - if (vmcount < 0) - vmcount = 0; - else if (!qcom_scm_is_available()) - return -EPROBE_DEFER; - - data = kzalloc(sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - if (vmcount) { - data->vmcount = vmcount; - data->perms = BIT(QCOM_SCM_VMID_HLOS); - for (i = 0; i < data->vmcount; i++) { - data->vmperms[i].vmid = vmids[i]; - data->vmperms[i].perm = QCOM_SCM_PERM_RWX; - } - } - - secure_dsp = !(of_property_read_bool(rdev->of_node, "qcom,non-secure-domain")); - data->secure = secure_dsp; - - switch (domain_id) { - case ADSP_DOMAIN_ID: - case MDSP_DOMAIN_ID: - case SDSP_DOMAIN_ID: - /* Unsigned PD offloading is only supported on CDSP*/ - data->unsigned_support = false; - err = fastrpc_device_register(rdev, data, secure_dsp, domains[domain_id]); - if (err) - goto fdev_error; - break; - case CDSP_DOMAIN_ID: - data->unsigned_support = true; - /* Create both device nodes so that we can allow both Signed and Unsigned PD */ - err = fastrpc_device_register(rdev, data, true, domains[domain_id]); - if (err) - goto fdev_error; - - err = fastrpc_device_register(rdev, data, false, domains[domain_id]); - if (err) - goto fdev_error; - break; - default: - err = -EINVAL; - goto fdev_error; - } - - kref_init(&data->refcount); - - dev_set_drvdata(&rpdev->dev, data); - dma_set_mask_and_coherent(rdev, DMA_BIT_MASK(32)); - INIT_LIST_HEAD(&data->users); - spin_lock_init(&data->lock); - idr_init(&data->ctx_idr); - data->domain_id = domain_id; - data->rpdev = rpdev; - - return of_platform_populate(rdev->of_node, NULL, NULL, rdev); -fdev_error: - kfree(data); - return err; -} - -static void fastrpc_notify_users(struct fastrpc_user *user) -{ - struct fastrpc_invoke_ctx *ctx; - - spin_lock(&user->lock); - list_for_each_entry(ctx, &user->pending, node) - complete(&ctx->work); - spin_unlock(&user->lock); -} - -static void fastrpc_rpmsg_remove(struct rpmsg_device *rpdev) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(&rpdev->dev); - struct fastrpc_user *user; - unsigned long flags; - - spin_lock_irqsave(&cctx->lock, flags); - list_for_each_entry(user, &cctx->users, user) - fastrpc_notify_users(user); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (cctx->fdevice) - misc_deregister(&cctx->fdevice->miscdev); - - if (cctx->secure_fdevice) - misc_deregister(&cctx->secure_fdevice->miscdev); - - of_platform_depopulate(&rpdev->dev); - - cctx->rpdev = NULL; - fastrpc_channel_ctx_put(cctx); -} - -static int fastrpc_rpmsg_callback(struct rpmsg_device *rpdev, void *data, - int len, void *priv, u32 addr) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(&rpdev->dev); - struct fastrpc_invoke_rsp *rsp = data; - struct fastrpc_invoke_ctx *ctx; - unsigned long flags; - unsigned long ctxid; - - if (len < sizeof(*rsp)) - return -EINVAL; - - ctxid = ((rsp->ctx & FASTRPC_CTXID_MASK) >> 4); - - spin_lock_irqsave(&cctx->lock, flags); - ctx = idr_find(&cctx->ctx_idr, ctxid); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (!ctx) { - dev_err(&rpdev->dev, "No context ID matches response\n"); - return -ENOENT; - } - - ctx->retval = rsp->retval; - complete(&ctx->work); - - /* - * The DMA buffer associated with the context cannot be freed in - * interrupt context so schedule it through a worker thread to - * avoid a kernel BUG. - */ - schedule_work(&ctx->put_work); - - return 0; -} - -static const struct of_device_id fastrpc_rpmsg_of_match[] = { - { .compatible = "qcom,fastrpc" }, - { }, -}; -MODULE_DEVICE_TABLE(of, fastrpc_rpmsg_of_match); - -static struct rpmsg_driver fastrpc_driver = { - .probe = fastrpc_rpmsg_probe, - .remove = fastrpc_rpmsg_remove, - .callback = fastrpc_rpmsg_callback, - .drv = { - .name = "qcom,fastrpc", - .of_match_table = fastrpc_rpmsg_of_match, - }, -}; - -static int fastrpc_init(void) -{ - int ret; - - ret = platform_driver_register(&fastrpc_cb_driver); - if (ret < 0) { - pr_err("fastrpc: failed to register cb driver\n"); - return ret; - } - - ret = register_rpmsg_driver(&fastrpc_driver); - if (ret < 0) { - pr_err("fastrpc: failed to register rpmsg driver\n"); - platform_driver_unregister(&fastrpc_cb_driver); - return ret; - } - - return 0; -} -module_init(fastrpc_init); - -static void fastrpc_exit(void) -{ - platform_driver_unregister(&fastrpc_cb_driver); - unregister_rpmsg_driver(&fastrpc_driver); -} -module_exit(fastrpc_exit); - -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/b42f7c232a68fe3a2a83a0d9b5bf92a639ec1865/preimage.2 b/rr-cache/b42f7c232a68fe3a2a83a0d9b5bf92a639ec1865/preimage.2 deleted file mode 100644 index e0641cd..0000000 --- a/rr-cache/b42f7c232a68fe3a2a83a0d9b5bf92a639ec1865/preimage.2 +++ /dev/null @@ -1,2245 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2011-2018, The Linux Foundation. All rights reserved. -// Copyright (c) 2018, Linaro Limited - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define ADSP_DOMAIN_ID (0) -#define MDSP_DOMAIN_ID (1) -#define SDSP_DOMAIN_ID (2) -#define CDSP_DOMAIN_ID (3) -#define FASTRPC_DEV_MAX 4 /* adsp, mdsp, slpi, cdsp*/ -#define FASTRPC_MAX_SESSIONS 13 /*12 compute, 1 cpz*/ -#define FASTRPC_MAX_VMIDS 16 -#define FASTRPC_ALIGN 128 -#define FASTRPC_MAX_FDLIST 16 -#define FASTRPC_MAX_CRCLIST 64 -#define FASTRPC_PHYS(p) ((p) & 0xffffffff) -#define FASTRPC_CTX_MAX (256) -#define FASTRPC_INIT_HANDLE 1 -#define FASTRPC_DSP_UTILITIES_HANDLE 2 -#define FASTRPC_CTXID_MASK (0xFF0) -#define INIT_FILELEN_MAX (2 * 1024 * 1024) -#define FASTRPC_DEVICE_NAME "fastrpc" -#define ADSP_MMAP_ADD_PAGES 0x1000 -#define DSP_UNSUPPORTED_API (0x80000414) -/* MAX NUMBER of DSP ATTRIBUTES SUPPORTED */ -#define FASTRPC_MAX_DSP_ATTRIBUTES (256) -#define FASTRPC_MAX_DSP_ATTRIBUTES_LEN (sizeof(u32) * FASTRPC_MAX_DSP_ATTRIBUTES) - -/* Retrives number of input buffers from the scalars parameter */ -#define REMOTE_SCALARS_INBUFS(sc) (((sc) >> 16) & 0x0ff) - -/* Retrives number of output buffers from the scalars parameter */ -#define REMOTE_SCALARS_OUTBUFS(sc) (((sc) >> 8) & 0x0ff) - -/* Retrives number of input handles from the scalars parameter */ -#define REMOTE_SCALARS_INHANDLES(sc) (((sc) >> 4) & 0x0f) - -/* Retrives number of output handles from the scalars parameter */ -#define REMOTE_SCALARS_OUTHANDLES(sc) ((sc) & 0x0f) - -#define REMOTE_SCALARS_LENGTH(sc) (REMOTE_SCALARS_INBUFS(sc) + \ - REMOTE_SCALARS_OUTBUFS(sc) + \ - REMOTE_SCALARS_INHANDLES(sc)+ \ - REMOTE_SCALARS_OUTHANDLES(sc)) -#define FASTRPC_BUILD_SCALARS(attr, method, in, out, oin, oout) \ - (((attr & 0x07) << 29) | \ - ((method & 0x1f) << 24) | \ - ((in & 0xff) << 16) | \ - ((out & 0xff) << 8) | \ - ((oin & 0x0f) << 4) | \ - (oout & 0x0f)) - -#define FASTRPC_SCALARS(method, in, out) \ - FASTRPC_BUILD_SCALARS(0, method, in, out, 0, 0) - -#define FASTRPC_CREATE_PROCESS_NARGS 6 -/* Remote Method id table */ -#define FASTRPC_RMID_INIT_ATTACH 0 -#define FASTRPC_RMID_INIT_RELEASE 1 -#define FASTRPC_RMID_INIT_MMAP 4 -#define FASTRPC_RMID_INIT_MUNMAP 5 -#define FASTRPC_RMID_INIT_CREATE 6 -#define FASTRPC_RMID_INIT_CREATE_ATTR 7 -#define FASTRPC_RMID_INIT_CREATE_STATIC 8 -#define FASTRPC_RMID_INIT_MEM_MAP 10 -#define FASTRPC_RMID_INIT_MEM_UNMAP 11 - -/* Protection Domain(PD) ids */ -#define AUDIO_PD (0) /* also GUEST_OS PD? */ -#define USER_PD (1) -#define SENSORS_PD (2) - -#define miscdev_to_fdevice(d) container_of(d, struct fastrpc_device, miscdev) - -static const char *domains[FASTRPC_DEV_MAX] = { "adsp", "mdsp", - "sdsp", "cdsp"}; -struct fastrpc_phy_page { - u64 addr; /* physical address */ - u64 size; /* size of contiguous region */ -}; - -struct fastrpc_invoke_buf { - u32 num; /* number of contiguous regions */ - u32 pgidx; /* index to start of contiguous region */ -}; - -struct fastrpc_remote_dmahandle { - s32 fd; /* dma handle fd */ - u32 offset; /* dma handle offset */ - u32 len; /* dma handle length */ -}; - -struct fastrpc_remote_buf { - u64 pv; /* buffer pointer */ - u64 len; /* length of buffer */ -}; - -union fastrpc_remote_arg { - struct fastrpc_remote_buf buf; - struct fastrpc_remote_dmahandle dma; -}; - -struct fastrpc_mmap_rsp_msg { - u64 vaddr; -}; - -struct fastrpc_mmap_req_msg { - s32 pgid; - u32 flags; - u64 vaddr; - s32 num; -}; - -struct fastrpc_mem_map_req_msg { - s32 pgid; - s32 fd; - s32 offset; - u32 flags; - u64 vaddrin; - s32 num; - s32 data_len; -}; - -struct fastrpc_munmap_req_msg { - s32 pgid; - u64 vaddr; - u64 size; -}; - -struct fastrpc_mem_unmap_req_msg { - s32 pgid; - s32 fd; - u64 vaddrin; - u64 len; -}; - -struct fastrpc_msg { - int pid; /* process group id */ - int tid; /* thread id */ - u64 ctx; /* invoke caller context */ - u32 handle; /* handle to invoke */ - u32 sc; /* scalars structure describing the data */ - u64 addr; /* physical address */ - u64 size; /* size of contiguous region */ -}; - -struct fastrpc_invoke_rsp { - u64 ctx; /* invoke caller context */ - int retval; /* invoke return value */ -}; - -struct fastrpc_buf_overlap { - u64 start; - u64 end; - int raix; - u64 mstart; - u64 mend; - u64 offset; -}; - -struct fastrpc_buf { - struct fastrpc_user *fl; - struct dma_buf *dmabuf; - struct device *dev; - void *virt; - u64 phys; - u64 size; - /* Lock for dma buf attachments */ - struct mutex lock; - struct list_head attachments; - /* mmap support */ - struct list_head node; /* list of user requested mmaps */ - uintptr_t raddr; -}; - -struct fastrpc_dma_buf_attachment { - struct device *dev; - struct sg_table sgt; - struct list_head node; -}; - -struct fastrpc_map { - struct list_head node; - struct fastrpc_user *fl; - int fd; - struct dma_buf *buf; - struct sg_table *table; - struct dma_buf_attachment *attach; - u64 phys; - u64 size; - void *va; - u64 len; - u64 raddr; - u32 attr; - struct kref refcount; -}; - -struct fastrpc_invoke_ctx { - int nscalars; - int nbufs; - int retval; - int pid; - int tgid; - u32 sc; - u32 *crc; - u64 ctxid; - u64 msg_sz; - struct kref refcount; - struct list_head node; /* list of ctxs */ - struct completion work; - struct work_struct put_work; - struct fastrpc_msg msg; - struct fastrpc_user *fl; - union fastrpc_remote_arg *rpra; - struct fastrpc_map **maps; - struct fastrpc_buf *buf; - struct fastrpc_invoke_args *args; - struct fastrpc_buf_overlap *olaps; - struct fastrpc_channel_ctx *cctx; -}; - -struct fastrpc_session_ctx { - struct device *dev; - int sid; - bool used; - bool valid; -}; - -struct fastrpc_channel_ctx { - int domain_id; - int sesscount; - int vmcount; - u32 perms; - struct qcom_scm_vmperm vmperms[FASTRPC_MAX_VMIDS]; - struct rpmsg_device *rpdev; - struct fastrpc_session_ctx session[FASTRPC_MAX_SESSIONS]; - spinlock_t lock; - struct idr ctx_idr; - struct list_head users; - struct kref refcount; - /* Flag if dsp attributes are cached */ - bool valid_attributes; - u32 dsp_attributes[FASTRPC_MAX_DSP_ATTRIBUTES]; - struct fastrpc_device *secure_fdevice; - struct fastrpc_device *fdevice; - bool secure; - bool unsigned_support; -}; - -struct fastrpc_device { - struct fastrpc_channel_ctx *cctx; - struct miscdevice miscdev; - bool secure; -}; - -struct fastrpc_user { - struct list_head user; - struct list_head maps; - struct list_head pending; - struct list_head mmaps; - - struct fastrpc_channel_ctx *cctx; - struct fastrpc_session_ctx *sctx; - struct fastrpc_buf *init_mem; - - int tgid; - int pd; - bool is_secure_dev; - /* Lock for lists */ - spinlock_t lock; - /* lock for allocations */ - struct mutex mutex; -}; - -static void fastrpc_free_map(struct kref *ref) -{ - struct fastrpc_map *map; - - map = container_of(ref, struct fastrpc_map, refcount); - - if (map->table) { - if (map->attr & FASTRPC_ATTR_SECUREMAP) { - struct qcom_scm_vmperm perm; - int err = 0; - - perm.vmid = QCOM_SCM_VMID_HLOS; - perm.perm = QCOM_SCM_PERM_RWX; - err = qcom_scm_assign_mem(map->phys, map->size, - &(map->fl->cctx->vmperms[0].vmid), &perm, 1); - if (err) { - dev_err(map->fl->sctx->dev, "Failed to assign memory phys 0x%llx size 0x%llx err %d", - map->phys, map->size, err); - return; - } - } - dma_buf_unmap_attachment(map->attach, map->table, - DMA_BIDIRECTIONAL); - dma_buf_detach(map->buf, map->attach); - dma_buf_put(map->buf); - } - - kfree(map); -} - -static void fastrpc_map_put(struct fastrpc_map *map) -{ - if (map) - kref_put(&map->refcount, fastrpc_free_map); -} - -static void fastrpc_map_get(struct fastrpc_map *map) -{ - if (map) - kref_get(&map->refcount); -} - - -static int fastrpc_map_lookup(struct fastrpc_user *fl, int fd, - struct fastrpc_map **ppmap) -{ - struct fastrpc_map *map = NULL; - - mutex_lock(&fl->mutex); - list_for_each_entry(map, &fl->maps, node) { - if (map->fd == fd) { - *ppmap = map; - mutex_unlock(&fl->mutex); - return 0; - } - } - mutex_unlock(&fl->mutex); - - return -ENOENT; -} - -static int fastrpc_map_find(struct fastrpc_user *fl, int fd, - struct fastrpc_map **ppmap) -{ - int ret = fastrpc_map_lookup(fl, fd, ppmap); - - if (!ret) - fastrpc_map_get(*ppmap); - - return ret; -} - -static void fastrpc_buf_free(struct fastrpc_buf *buf) -{ - dma_free_coherent(buf->dev, buf->size, buf->virt, - FASTRPC_PHYS(buf->phys)); - kfree(buf); -} - -static int fastrpc_buf_alloc(struct fastrpc_user *fl, struct device *dev, - u64 size, struct fastrpc_buf **obuf) -{ - struct fastrpc_buf *buf; - - buf = kzalloc(sizeof(*buf), GFP_KERNEL); - if (!buf) - return -ENOMEM; - - INIT_LIST_HEAD(&buf->attachments); - INIT_LIST_HEAD(&buf->node); - mutex_init(&buf->lock); - - buf->fl = fl; - buf->virt = NULL; - buf->phys = 0; - buf->size = size; - buf->dev = dev; - buf->raddr = 0; - - buf->virt = dma_alloc_coherent(dev, buf->size, (dma_addr_t *)&buf->phys, - GFP_KERNEL); - if (!buf->virt) { - mutex_destroy(&buf->lock); - kfree(buf); - return -ENOMEM; - } - - if (fl->sctx && fl->sctx->sid) - buf->phys += ((u64)fl->sctx->sid << 32); - - *obuf = buf; - - return 0; -} - -static void fastrpc_channel_ctx_free(struct kref *ref) -{ - struct fastrpc_channel_ctx *cctx; - - cctx = container_of(ref, struct fastrpc_channel_ctx, refcount); - - kfree(cctx); -} - -static void fastrpc_channel_ctx_get(struct fastrpc_channel_ctx *cctx) -{ - kref_get(&cctx->refcount); -} - -static void fastrpc_channel_ctx_put(struct fastrpc_channel_ctx *cctx) -{ - kref_put(&cctx->refcount, fastrpc_channel_ctx_free); -} - -static void fastrpc_context_free(struct kref *ref) -{ - struct fastrpc_invoke_ctx *ctx; - struct fastrpc_channel_ctx *cctx; - unsigned long flags; - int i; - - ctx = container_of(ref, struct fastrpc_invoke_ctx, refcount); - cctx = ctx->cctx; - - for (i = 0; i < ctx->nbufs; i++) - fastrpc_map_put(ctx->maps[i]); - - if (ctx->buf) - fastrpc_buf_free(ctx->buf); - - spin_lock_irqsave(&cctx->lock, flags); - idr_remove(&cctx->ctx_idr, ctx->ctxid >> 4); - spin_unlock_irqrestore(&cctx->lock, flags); - - kfree(ctx->maps); - kfree(ctx->olaps); - kfree(ctx); - - fastrpc_channel_ctx_put(cctx); -} - -static void fastrpc_context_get(struct fastrpc_invoke_ctx *ctx) -{ - kref_get(&ctx->refcount); -} - -static void fastrpc_context_put(struct fastrpc_invoke_ctx *ctx) -{ - kref_put(&ctx->refcount, fastrpc_context_free); -} - -static void fastrpc_context_put_wq(struct work_struct *work) -{ - struct fastrpc_invoke_ctx *ctx = - container_of(work, struct fastrpc_invoke_ctx, put_work); - - fastrpc_context_put(ctx); -} - -#define CMP(aa, bb) ((aa) == (bb) ? 0 : (aa) < (bb) ? -1 : 1) -static int olaps_cmp(const void *a, const void *b) -{ - struct fastrpc_buf_overlap *pa = (struct fastrpc_buf_overlap *)a; - struct fastrpc_buf_overlap *pb = (struct fastrpc_buf_overlap *)b; - /* sort with lowest starting buffer first */ - int st = CMP(pa->start, pb->start); - /* sort with highest ending buffer first */ - int ed = CMP(pb->end, pa->end); - - return st == 0 ? ed : st; -} - -static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) -{ - u64 max_end = 0; - int i; - - for (i = 0; i < ctx->nbufs; ++i) { - ctx->olaps[i].start = ctx->args[i].ptr; - ctx->olaps[i].end = ctx->olaps[i].start + ctx->args[i].length; - ctx->olaps[i].raix = i; - } - - sort(ctx->olaps, ctx->nbufs, sizeof(*ctx->olaps), olaps_cmp, NULL); - - for (i = 0; i < ctx->nbufs; ++i) { - /* Falling inside previous range */ - if (ctx->olaps[i].start < max_end) { - ctx->olaps[i].mstart = max_end; - ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].offset = max_end - ctx->olaps[i].start; - - if (ctx->olaps[i].end > max_end) { - max_end = ctx->olaps[i].end; - } else { - ctx->olaps[i].mend = 0; - ctx->olaps[i].mstart = 0; - } - - } else { - ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].mstart = ctx->olaps[i].start; - ctx->olaps[i].offset = 0; - max_end = ctx->olaps[i].end; - } - } -} - -static struct fastrpc_invoke_ctx *fastrpc_context_alloc( - struct fastrpc_user *user, u32 kernel, u32 sc, - struct fastrpc_invoke_args *args) -{ - struct fastrpc_channel_ctx *cctx = user->cctx; - struct fastrpc_invoke_ctx *ctx = NULL; - unsigned long flags; - int ret; - - ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return ERR_PTR(-ENOMEM); - - INIT_LIST_HEAD(&ctx->node); - ctx->fl = user; - ctx->nscalars = REMOTE_SCALARS_LENGTH(sc); - ctx->nbufs = REMOTE_SCALARS_INBUFS(sc) + - REMOTE_SCALARS_OUTBUFS(sc); - - if (ctx->nscalars) { - ctx->maps = kcalloc(ctx->nscalars, - sizeof(*ctx->maps), GFP_KERNEL); - if (!ctx->maps) { - kfree(ctx); - return ERR_PTR(-ENOMEM); - } - ctx->olaps = kcalloc(ctx->nscalars, - sizeof(*ctx->olaps), GFP_KERNEL); - if (!ctx->olaps) { - kfree(ctx->maps); - kfree(ctx); - return ERR_PTR(-ENOMEM); - } - ctx->args = args; - fastrpc_get_buff_overlaps(ctx); - } - - /* Released in fastrpc_context_put() */ - fastrpc_channel_ctx_get(cctx); - - ctx->sc = sc; - ctx->retval = -1; - ctx->pid = current->pid; - ctx->tgid = user->tgid; - ctx->cctx = cctx; - init_completion(&ctx->work); - INIT_WORK(&ctx->put_work, fastrpc_context_put_wq); - - spin_lock(&user->lock); - list_add_tail(&ctx->node, &user->pending); - spin_unlock(&user->lock); - - spin_lock_irqsave(&cctx->lock, flags); - ret = idr_alloc_cyclic(&cctx->ctx_idr, ctx, 1, - FASTRPC_CTX_MAX, GFP_ATOMIC); - if (ret < 0) { - spin_unlock_irqrestore(&cctx->lock, flags); - goto err_idr; - } - ctx->ctxid = ret << 4; - spin_unlock_irqrestore(&cctx->lock, flags); - - kref_init(&ctx->refcount); - - return ctx; -err_idr: - spin_lock(&user->lock); - list_del(&ctx->node); - spin_unlock(&user->lock); - fastrpc_channel_ctx_put(cctx); - kfree(ctx->maps); - kfree(ctx->olaps); - kfree(ctx); - - return ERR_PTR(ret); -} - -static struct sg_table * -fastrpc_map_dma_buf(struct dma_buf_attachment *attachment, - enum dma_data_direction dir) -{ - struct fastrpc_dma_buf_attachment *a = attachment->priv; - struct sg_table *table; - int ret; - - table = &a->sgt; - - ret = dma_map_sgtable(attachment->dev, table, dir, 0); - if (ret) - table = ERR_PTR(ret); - return table; -} - -static void fastrpc_unmap_dma_buf(struct dma_buf_attachment *attach, - struct sg_table *table, - enum dma_data_direction dir) -{ - dma_unmap_sgtable(attach->dev, table, dir, 0); -} - -static void fastrpc_release(struct dma_buf *dmabuf) -{ - struct fastrpc_buf *buffer = dmabuf->priv; - - fastrpc_buf_free(buffer); -} - -static int fastrpc_dma_buf_attach(struct dma_buf *dmabuf, - struct dma_buf_attachment *attachment) -{ - struct fastrpc_dma_buf_attachment *a; - struct fastrpc_buf *buffer = dmabuf->priv; - int ret; - - a = kzalloc(sizeof(*a), GFP_KERNEL); - if (!a) - return -ENOMEM; - - ret = dma_get_sgtable(buffer->dev, &a->sgt, buffer->virt, - FASTRPC_PHYS(buffer->phys), buffer->size); - if (ret < 0) { - dev_err(buffer->dev, "failed to get scatterlist from DMA API\n"); - kfree(a); - return -EINVAL; - } - - a->dev = attachment->dev; - INIT_LIST_HEAD(&a->node); - attachment->priv = a; - - mutex_lock(&buffer->lock); - list_add(&a->node, &buffer->attachments); - mutex_unlock(&buffer->lock); - - return 0; -} - -static void fastrpc_dma_buf_detatch(struct dma_buf *dmabuf, - struct dma_buf_attachment *attachment) -{ - struct fastrpc_dma_buf_attachment *a = attachment->priv; - struct fastrpc_buf *buffer = dmabuf->priv; - - mutex_lock(&buffer->lock); - list_del(&a->node); - mutex_unlock(&buffer->lock); - sg_free_table(&a->sgt); - kfree(a); -} - -static int fastrpc_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) -{ - struct fastrpc_buf *buf = dmabuf->priv; - - dma_buf_map_set_vaddr(map, buf->virt); - - return 0; -} - -static int fastrpc_mmap(struct dma_buf *dmabuf, - struct vm_area_struct *vma) -{ - struct fastrpc_buf *buf = dmabuf->priv; - size_t size = vma->vm_end - vma->vm_start; - - return dma_mmap_coherent(buf->dev, vma, buf->virt, - FASTRPC_PHYS(buf->phys), size); -} - -static const struct dma_buf_ops fastrpc_dma_buf_ops = { - .attach = fastrpc_dma_buf_attach, - .detach = fastrpc_dma_buf_detatch, - .map_dma_buf = fastrpc_map_dma_buf, - .unmap_dma_buf = fastrpc_unmap_dma_buf, - .mmap = fastrpc_mmap, - .vmap = fastrpc_vmap, - .release = fastrpc_release, -}; - -static int fastrpc_map_create(struct fastrpc_user *fl, int fd, - u64 len, u32 attr, struct fastrpc_map **ppmap) -{ - struct fastrpc_session_ctx *sess = fl->sctx; - struct fastrpc_map *map = NULL; - int err = 0; - - if (!fastrpc_map_find(fl, fd, ppmap)) - return 0; - - map = kzalloc(sizeof(*map), GFP_KERNEL); - if (!map) - return -ENOMEM; - - INIT_LIST_HEAD(&map->node); - map->fl = fl; - map->fd = fd; - map->buf = dma_buf_get(fd); - if (IS_ERR(map->buf)) { - err = PTR_ERR(map->buf); - goto get_err; - } - - map->attach = dma_buf_attach(map->buf, sess->dev); - if (IS_ERR(map->attach)) { - dev_err(sess->dev, "Failed to attach dmabuf\n"); - err = PTR_ERR(map->attach); - goto attach_err; - } - - map->table = dma_buf_map_attachment(map->attach, DMA_BIDIRECTIONAL); - if (IS_ERR(map->table)) { - err = PTR_ERR(map->table); - goto map_err; - } - - map->phys = sg_dma_address(map->table->sgl); - map->phys += ((u64)fl->sctx->sid << 32); - map->size = len; - map->va = sg_virt(map->table->sgl); - map->len = len; - kref_init(&map->refcount); - - if (attr & FASTRPC_ATTR_SECUREMAP) { - /* - * If subsystem VMIDs are defined in DTSI, then do - * hyp_assign from HLOS to those VM(s) - */ - unsigned int perms = BIT(QCOM_SCM_VMID_HLOS); - - map->attr = attr; - err = qcom_scm_assign_mem(map->phys, (u64)map->size, &perms, - fl->cctx->vmperms, fl->cctx->vmcount); - if (err) { - dev_err(sess->dev, "Failed to assign memory with phys 0x%llx size 0x%llx err %d", - map->phys, map->size, err); - goto map_err; - } - } - spin_lock(&fl->lock); - list_add_tail(&map->node, &fl->maps); - spin_unlock(&fl->lock); - *ppmap = map; - - return 0; - -map_err: - dma_buf_detach(map->buf, map->attach); -attach_err: - dma_buf_put(map->buf); -get_err: - kfree(map); - - return err; -} - -/* - * Fastrpc payload buffer with metadata looks like: - * - * >>>>>> START of METADATA <<<<<<<<< - * +---------------------------------+ - * | Arguments | - * | type:(union fastrpc_remote_arg)| - * | (0 - N) | - * +---------------------------------+ - * | Invoke Buffer list | - * | type:(struct fastrpc_invoke_buf)| - * | (0 - N) | - * +---------------------------------+ - * | Page info list | - * | type:(struct fastrpc_phy_page) | - * | (0 - N) | - * +---------------------------------+ - * | Optional info | - * |(can be specific to SoC/Firmware)| - * +---------------------------------+ - * >>>>>>>> END of METADATA <<<<<<<<< - * +---------------------------------+ - * | Inline ARGS | - * | (0-N) | - * +---------------------------------+ - */ - -static int fastrpc_get_meta_size(struct fastrpc_invoke_ctx *ctx) -{ - int size = 0; - - size = (sizeof(struct fastrpc_remote_buf) + - sizeof(struct fastrpc_invoke_buf) + - sizeof(struct fastrpc_phy_page)) * ctx->nscalars + - sizeof(u64) * FASTRPC_MAX_FDLIST + - sizeof(u32) * FASTRPC_MAX_CRCLIST; - - return size; -} - -static u64 fastrpc_get_payload_size(struct fastrpc_invoke_ctx *ctx, int metalen) -{ - u64 size = 0; - int oix; - - size = ALIGN(metalen, FASTRPC_ALIGN); - for (oix = 0; oix < ctx->nbufs; oix++) { - int i = ctx->olaps[oix].raix; - - if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1) { - - if (ctx->olaps[oix].offset == 0) - size = ALIGN(size, FASTRPC_ALIGN); - - size += (ctx->olaps[oix].mend - ctx->olaps[oix].mstart); - } - } - - return size; -} - -static int fastrpc_create_maps(struct fastrpc_invoke_ctx *ctx) -{ - struct device *dev = ctx->fl->sctx->dev; - int i, err; - - for (i = 0; i < ctx->nscalars; ++i) { - - if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1 || - ctx->args[i].length == 0) - continue; - - err = fastrpc_map_create(ctx->fl, ctx->args[i].fd, - ctx->args[i].length, ctx->args[i].attr, &ctx->maps[i]); - if (err) { - dev_err(dev, "Error Creating map %d\n", err); - return -EINVAL; - } - - } - return 0; -} - -static struct fastrpc_invoke_buf *fastrpc_invoke_buf_start(union fastrpc_remote_arg *pra, int len) -{ - return (struct fastrpc_invoke_buf *)(&pra[len]); -} - -static struct fastrpc_phy_page *fastrpc_phy_page_start(struct fastrpc_invoke_buf *buf, int len) -{ - return (struct fastrpc_phy_page *)(&buf[len]); -} - -static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) -{ - struct device *dev = ctx->fl->sctx->dev; - union fastrpc_remote_arg *rpra; - struct fastrpc_invoke_buf *list; - struct fastrpc_phy_page *pages; - int inbufs, i, oix, err = 0; - u64 len, rlen, pkt_size; - u64 pg_start, pg_end; - uintptr_t args; - int metalen; - - inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); - metalen = fastrpc_get_meta_size(ctx); - pkt_size = fastrpc_get_payload_size(ctx, metalen); - - err = fastrpc_create_maps(ctx); - if (err) - return err; - - ctx->msg_sz = pkt_size; - - err = fastrpc_buf_alloc(ctx->fl, dev, pkt_size, &ctx->buf); - if (err) - return err; - - rpra = ctx->buf->virt; - list = fastrpc_invoke_buf_start(rpra, ctx->nscalars); - pages = fastrpc_phy_page_start(list, ctx->nscalars); - args = (uintptr_t)ctx->buf->virt + metalen; - rlen = pkt_size - metalen; - ctx->rpra = rpra; - - for (oix = 0; oix < ctx->nbufs; ++oix) { - int mlen; - - i = ctx->olaps[oix].raix; - len = ctx->args[i].length; - - rpra[i].buf.pv = 0; - rpra[i].buf.len = len; - list[i].num = len ? 1 : 0; - list[i].pgidx = i; - - if (!len) - continue; - - if (ctx->maps[i]) { - struct vm_area_struct *vma = NULL; - - rpra[i].buf.pv = (u64) ctx->args[i].ptr; - pages[i].addr = ctx->maps[i]->phys; - - mmap_read_lock(current->mm); - vma = find_vma(current->mm, ctx->args[i].ptr); - if (vma) - pages[i].addr += ctx->args[i].ptr - - vma->vm_start; - mmap_read_unlock(current->mm); - - pg_start = (ctx->args[i].ptr & PAGE_MASK) >> PAGE_SHIFT; - pg_end = ((ctx->args[i].ptr + len - 1) & PAGE_MASK) >> - PAGE_SHIFT; - pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - - } else { - - if (ctx->olaps[oix].offset == 0) { - rlen -= ALIGN(args, FASTRPC_ALIGN) - args; - args = ALIGN(args, FASTRPC_ALIGN); - } - - mlen = ctx->olaps[oix].mend - ctx->olaps[oix].mstart; - - if (rlen < mlen) - goto bail; - - rpra[i].buf.pv = args - ctx->olaps[oix].offset; - pages[i].addr = ctx->buf->phys - - ctx->olaps[oix].offset + - (pkt_size - rlen); - pages[i].addr = pages[i].addr & PAGE_MASK; - - pg_start = (args & PAGE_MASK) >> PAGE_SHIFT; - pg_end = ((args + len - 1) & PAGE_MASK) >> PAGE_SHIFT; - pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - args = args + mlen; - rlen -= mlen; - } - - if (i < inbufs && !ctx->maps[i]) { - void *dst = (void *)(uintptr_t)rpra[i].buf.pv; - void *src = (void *)(uintptr_t)ctx->args[i].ptr; - - if (!kernel) { - if (copy_from_user(dst, (void __user *)src, - len)) { - err = -EFAULT; - goto bail; - } - } else { - memcpy(dst, src, len); - } - } - } - - for (i = ctx->nbufs; i < ctx->nscalars; ++i) { - list[i].num = ctx->args[i].length ? 1 : 0; - list[i].pgidx = i; - if (ctx->maps[i]) { - pages[i].addr = ctx->maps[i]->phys; - pages[i].size = ctx->maps[i]->size; - } - rpra[i].dma.fd = ctx->args[i].fd; - rpra[i].dma.len = ctx->args[i].length; - rpra[i].dma.offset = (u64) ctx->args[i].ptr; - } - -bail: - if (err) - dev_err(dev, "Error: get invoke args failed:%d\n", err); - - return err; -} - -static int fastrpc_put_args(struct fastrpc_invoke_ctx *ctx, - u32 kernel) -{ - union fastrpc_remote_arg *rpra = ctx->rpra; - struct fastrpc_user *fl = ctx->fl; - struct fastrpc_map *mmap = NULL; - struct fastrpc_invoke_buf *list; - struct fastrpc_phy_page *pages; - u64 *fdlist; - int i, inbufs, outbufs, handles; - - inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); - outbufs = REMOTE_SCALARS_OUTBUFS(ctx->sc); - handles = REMOTE_SCALARS_INHANDLES(ctx->sc) + REMOTE_SCALARS_OUTHANDLES(ctx->sc); - list = fastrpc_invoke_buf_start(rpra, ctx->nscalars); - pages = fastrpc_phy_page_start(list, ctx->nscalars); - fdlist = (uint64_t *)(pages + inbufs + outbufs + handles); - - for (i = inbufs; i < ctx->nbufs; ++i) { -<<<<<<< - if (!ctx->maps[i]) { - void *src = (void *)(uintptr_t)rpra[i].buf.pv; - void *dst = (void *)(uintptr_t)ctx->args[i].ptr; - u64 len = rpra[i].buf.len; -======= - void *src = (void *)(uintptr_t)rpra[i].pv; - void *dst = (void *)(uintptr_t)ctx->args[i].ptr; - u64 len = rpra[i].len; ->>>>>>> - - if (!kernel) { - if (copy_to_user((void __user *)dst, src, len)) - return -EFAULT; - } else { - memcpy(dst, src, len); - } - } - - for (i = 0; i < FASTRPC_MAX_FDLIST; i++) { - if (!fdlist[i]) - break; - if (!fastrpc_map_lookup(fl, (int)fdlist[i], &mmap)) - fastrpc_map_put(mmap); - } - - return 0; -} - -static int fastrpc_invoke_send(struct fastrpc_session_ctx *sctx, - struct fastrpc_invoke_ctx *ctx, - u32 kernel, uint32_t handle) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_user *fl = ctx->fl; - struct fastrpc_msg *msg = &ctx->msg; - int ret; - - cctx = fl->cctx; - msg->pid = fl->tgid; - msg->tid = current->pid; - - if (kernel) - msg->pid = 0; - - msg->ctx = ctx->ctxid | fl->pd; - msg->handle = handle; - msg->sc = ctx->sc; - msg->addr = ctx->buf ? ctx->buf->phys : 0; - msg->size = roundup(ctx->msg_sz, PAGE_SIZE); - fastrpc_context_get(ctx); - - ret = rpmsg_send(cctx->rpdev->ept, (void *)msg, sizeof(*msg)); - - if (ret) - fastrpc_context_put(ctx); - - return ret; - -} - -static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel, - u32 handle, u32 sc, - struct fastrpc_invoke_args *args) -{ - struct fastrpc_invoke_ctx *ctx = NULL; - int err = 0; - - if (!fl->sctx) - return -EINVAL; - - if (!fl->cctx->rpdev) - return -EPIPE; - - if (handle == FASTRPC_INIT_HANDLE && !kernel) { - dev_warn_ratelimited(fl->sctx->dev, "user app trying to send a kernel RPC message (%d)\n", handle); - return -EPERM; - } - - ctx = fastrpc_context_alloc(fl, kernel, sc, args); - if (IS_ERR(ctx)) - return PTR_ERR(ctx); - - if (ctx->nscalars) { - err = fastrpc_get_args(kernel, ctx); - if (err) - goto bail; - } - - /* make sure that all CPU memory writes are seen by DSP */ - dma_wmb(); - /* Send invoke buffer to remote dsp */ - err = fastrpc_invoke_send(fl->sctx, ctx, kernel, handle); - if (err) - goto bail; - - if (kernel) { - if (!wait_for_completion_timeout(&ctx->work, 10 * HZ)) - err = -ETIMEDOUT; - } else { - err = wait_for_completion_interruptible(&ctx->work); - } - - if (err) - goto bail; - - /* Check the response from remote dsp */ - err = ctx->retval; - if (err) - goto bail; - - if (ctx->nscalars) { - /* make sure that all memory writes by DSP are seen by CPU */ - dma_rmb(); - /* populate all the output buffers with results */ - err = fastrpc_put_args(ctx, kernel); - if (err) - goto bail; - } - -bail: - if (err != -ERESTARTSYS && err != -ETIMEDOUT) { - /* We are done with this compute context */ - spin_lock(&fl->lock); - list_del(&ctx->node); - spin_unlock(&fl->lock); - fastrpc_context_put(ctx); - } - if (err) - dev_dbg(fl->sctx->dev, "Error: Invoke Failed %d\n", err); - - return err; -} - -static bool is_session_rejected(struct fastrpc_user *fl, bool unsigned_pd_request) -{ - /* Check if the device node is non-secure and channel is secure*/ - if (!fl->is_secure_dev && fl->cctx->secure) { - /* - * Allow untrusted applications to offload only to Unsigned PD when - * channel is configured as secure and block untrusted apps on channel - * that does not support unsigned PD offload - */ - if (!fl->cctx->unsigned_support || !unsigned_pd_request) { - dev_err(&fl->cctx->rpdev->dev, "Error: Untrusted application trying to offload to signed PD"); - return true; - } - } - - return false; -} - -static int fastrpc_init_create_process(struct fastrpc_user *fl, - char __user *argp) -{ - struct fastrpc_init_create init; - struct fastrpc_invoke_args *args; - struct fastrpc_phy_page pages[1]; - struct fastrpc_map *map = NULL; - struct fastrpc_buf *imem = NULL; - int memlen; - int err; - struct { - int pgid; - u32 namelen; - u32 filelen; - u32 pageslen; - u32 attrs; - u32 siglen; - } inbuf; - u32 sc; - bool unsigned_module = false; - - args = kcalloc(FASTRPC_CREATE_PROCESS_NARGS, sizeof(*args), GFP_KERNEL); - if (!args) - return -ENOMEM; - - if (copy_from_user(&init, argp, sizeof(init))) { - err = -EFAULT; - goto err; - } - - if (init.attrs & FASTRPC_MODE_UNSIGNED_MODULE) - unsigned_module = true; - - if (is_session_rejected(fl, unsigned_module)) { - err = -ECONNREFUSED; - goto err; - } - - if (init.filelen > INIT_FILELEN_MAX) { - err = -EINVAL; - goto err; - } - - inbuf.pgid = fl->tgid; - inbuf.namelen = strlen(current->comm) + 1; - inbuf.filelen = init.filelen; - inbuf.pageslen = 1; - inbuf.attrs = init.attrs; - inbuf.siglen = init.siglen; - fl->pd = USER_PD; - - if (init.filelen && init.filefd) { - err = fastrpc_map_create(fl, init.filefd, init.filelen, 0, &map); - if (err) - goto err; - } - - memlen = ALIGN(max(INIT_FILELEN_MAX, (int)init.filelen * 4), - 1024 * 1024); - err = fastrpc_buf_alloc(fl, fl->sctx->dev, memlen, - &imem); - if (err) - goto err_alloc; - - fl->init_mem = imem; - args[0].ptr = (u64)(uintptr_t)&inbuf; - args[0].length = sizeof(inbuf); - args[0].fd = -1; - - args[1].ptr = (u64)(uintptr_t)current->comm; - args[1].length = inbuf.namelen; - args[1].fd = -1; - - args[2].ptr = (u64) init.file; - args[2].length = inbuf.filelen; - args[2].fd = init.filefd; - - pages[0].addr = imem->phys; - pages[0].size = imem->size; - - args[3].ptr = (u64)(uintptr_t) pages; - args[3].length = 1 * sizeof(*pages); - args[3].fd = -1; - - args[4].ptr = (u64)(uintptr_t)&inbuf.attrs; - args[4].length = sizeof(inbuf.attrs); - args[4].fd = -1; - - args[5].ptr = (u64)(uintptr_t) &inbuf.siglen; - args[5].length = sizeof(inbuf.siglen); - args[5].fd = -1; - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE, 4, 0); - if (init.attrs) - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE_ATTR, 6, 0); - - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, args); - if (err) - goto err_invoke; - - kfree(args); - - return 0; - -err_invoke: - fl->init_mem = NULL; - fastrpc_buf_free(imem); -err_alloc: - if (map) { - spin_lock(&fl->lock); - list_del(&map->node); - spin_unlock(&fl->lock); - fastrpc_map_put(map); - } -err: - kfree(args); - - return err; -} - -static struct fastrpc_session_ctx *fastrpc_session_alloc( - struct fastrpc_channel_ctx *cctx) -{ - struct fastrpc_session_ctx *session = NULL; - unsigned long flags; - int i; - - spin_lock_irqsave(&cctx->lock, flags); - for (i = 0; i < cctx->sesscount; i++) { - if (!cctx->session[i].used && cctx->session[i].valid) { - cctx->session[i].used = true; - session = &cctx->session[i]; - break; - } - } - spin_unlock_irqrestore(&cctx->lock, flags); - - return session; -} - -static void fastrpc_session_free(struct fastrpc_channel_ctx *cctx, - struct fastrpc_session_ctx *session) -{ - unsigned long flags; - - spin_lock_irqsave(&cctx->lock, flags); - session->used = false; - spin_unlock_irqrestore(&cctx->lock, flags); -} - -static int fastrpc_release_current_dsp_process(struct fastrpc_user *fl) -{ - struct fastrpc_invoke_args args[1]; - int tgid = 0; - u32 sc; - - tgid = fl->tgid; - args[0].ptr = (u64)(uintptr_t) &tgid; - args[0].length = sizeof(tgid); - args[0].fd = -1; - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_RELEASE, 1, 0); - - return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, &args[0]); -} - -static int fastrpc_device_release(struct inode *inode, struct file *file) -{ - struct fastrpc_user *fl = (struct fastrpc_user *)file->private_data; - struct fastrpc_channel_ctx *cctx = fl->cctx; - struct fastrpc_invoke_ctx *ctx, *n; - struct fastrpc_map *map, *m; - struct fastrpc_buf *buf, *b; - unsigned long flags; - - fastrpc_release_current_dsp_process(fl); - - spin_lock_irqsave(&cctx->lock, flags); - list_del(&fl->user); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (fl->init_mem) - fastrpc_buf_free(fl->init_mem); - - list_for_each_entry_safe(ctx, n, &fl->pending, node) { - list_del(&ctx->node); - fastrpc_context_put(ctx); - } - - list_for_each_entry_safe(map, m, &fl->maps, node) { - list_del(&map->node); - fastrpc_map_put(map); - } - - list_for_each_entry_safe(buf, b, &fl->mmaps, node) { - list_del(&buf->node); - fastrpc_buf_free(buf); - } - - fastrpc_session_free(cctx, fl->sctx); - fastrpc_channel_ctx_put(cctx); - - mutex_destroy(&fl->mutex); - kfree(fl); - file->private_data = NULL; - - return 0; -} - -static int fastrpc_device_open(struct inode *inode, struct file *filp) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_device *fdevice; - struct fastrpc_user *fl = NULL; - unsigned long flags; - - fdevice = miscdev_to_fdevice(filp->private_data); - cctx = fdevice->cctx; - - fl = kzalloc(sizeof(*fl), GFP_KERNEL); - if (!fl) - return -ENOMEM; - - /* Released in fastrpc_device_release() */ - fastrpc_channel_ctx_get(cctx); - - filp->private_data = fl; - spin_lock_init(&fl->lock); - mutex_init(&fl->mutex); - INIT_LIST_HEAD(&fl->pending); - INIT_LIST_HEAD(&fl->maps); - INIT_LIST_HEAD(&fl->mmaps); - INIT_LIST_HEAD(&fl->user); - fl->tgid = current->tgid; - fl->cctx = cctx; - fl->is_secure_dev = fdevice->secure; - - fl->sctx = fastrpc_session_alloc(cctx); - if (!fl->sctx) { - dev_err(&cctx->rpdev->dev, "No session available\n"); - mutex_destroy(&fl->mutex); - kfree(fl); - - return -EBUSY; - } - - spin_lock_irqsave(&cctx->lock, flags); - list_add_tail(&fl->user, &cctx->users); - spin_unlock_irqrestore(&cctx->lock, flags); - - return 0; -} - -static int fastrpc_dmabuf_alloc(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_alloc_dma_buf bp; - DEFINE_DMA_BUF_EXPORT_INFO(exp_info); - struct fastrpc_buf *buf = NULL; - int err; - - if (copy_from_user(&bp, argp, sizeof(bp))) - return -EFAULT; - - err = fastrpc_buf_alloc(fl, fl->sctx->dev, bp.size, &buf); - if (err) - return err; - exp_info.ops = &fastrpc_dma_buf_ops; - exp_info.size = bp.size; - exp_info.flags = O_RDWR; - exp_info.priv = buf; - buf->dmabuf = dma_buf_export(&exp_info); - if (IS_ERR(buf->dmabuf)) { - err = PTR_ERR(buf->dmabuf); - fastrpc_buf_free(buf); - return err; - } - - bp.fd = dma_buf_fd(buf->dmabuf, O_ACCMODE); - if (bp.fd < 0) { - dma_buf_put(buf->dmabuf); - return -EINVAL; - } - - if (copy_to_user(argp, &bp, sizeof(bp))) { - /* - * The usercopy failed, but we can't do much about it, as - * dma_buf_fd() already called fd_install() and made the - * file descriptor accessible for the current process. It - * might already be closed and dmabuf no longer valid when - * we reach this point. Therefore "leak" the fd and rely on - * the process exit path to do any required cleanup. - */ - return -EFAULT; - } - - return 0; -} - -static int fastrpc_init_attach(struct fastrpc_user *fl, int pd) -{ - struct fastrpc_invoke_args args[1]; - int tgid = fl->tgid; - u32 sc; - - args[0].ptr = (u64)(uintptr_t) &tgid; - args[0].length = sizeof(tgid); - args[0].fd = -1; - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_ATTACH, 1, 0); - fl->pd = pd; - - return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, &args[0]); -} - -static int fastrpc_invoke(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args *args = NULL; - struct fastrpc_invoke inv; - u32 nscalars; - int err; - - if (copy_from_user(&inv, argp, sizeof(inv))) - return -EFAULT; - - /* nscalars is truncated here to max supported value */ - nscalars = REMOTE_SCALARS_LENGTH(inv.sc); - if (nscalars) { - args = kcalloc(nscalars, sizeof(*args), GFP_KERNEL); - if (!args) - return -ENOMEM; - - if (copy_from_user(args, (void __user *)(uintptr_t)inv.args, - nscalars * sizeof(*args))) { - kfree(args); - return -EFAULT; - } - } - - err = fastrpc_internal_invoke(fl, false, inv.handle, inv.sc, args); - kfree(args); - - return err; -} - -static int fastrpc_get_info_from_dsp(struct fastrpc_user *fl, uint32_t *dsp_attr_buf, - uint32_t dsp_attr_buf_len) -{ - struct fastrpc_invoke_args args[2] = { 0 }; - - /* Capability filled in userspace */ - dsp_attr_buf[0] = 0; - - args[0].ptr = (u64)(uintptr_t)&dsp_attr_buf_len; - args[0].length = sizeof(dsp_attr_buf_len); - args[0].fd = -1; - args[1].ptr = (u64)(uintptr_t)&dsp_attr_buf[1]; - args[1].length = dsp_attr_buf_len; - args[1].fd = -1; - fl->pd = 1; - - return fastrpc_internal_invoke(fl, true, FASTRPC_DSP_UTILITIES_HANDLE, - FASTRPC_SCALARS(0, 1, 1), args); -} - -static int fastrpc_get_info_from_kernel(struct fastrpc_ioctl_capability *cap, - struct fastrpc_user *fl) -{ - struct fastrpc_channel_ctx *cctx = fl->cctx; - uint32_t attribute_id = cap->attribute_id; - uint32_t *dsp_attributes; - unsigned long flags; - uint32_t domain = cap->domain; - int err; - - spin_lock_irqsave(&cctx->lock, flags); - /* check if we already have queried dsp for attributes */ - if (cctx->valid_attributes) { - spin_unlock_irqrestore(&cctx->lock, flags); - goto done; - } - spin_unlock_irqrestore(&cctx->lock, flags); - - dsp_attributes = kzalloc(FASTRPC_MAX_DSP_ATTRIBUTES_LEN, GFP_KERNEL); - if (!dsp_attributes) - return -ENOMEM; - - err = fastrpc_get_info_from_dsp(fl, dsp_attributes, FASTRPC_MAX_DSP_ATTRIBUTES_LEN); - if (err == DSP_UNSUPPORTED_API) { - dev_info(&cctx->rpdev->dev, - "Warning: DSP capabilities not supported on domain: %d\n", domain); - kfree(dsp_attributes); - return -EOPNOTSUPP; - } else if (err) { - dev_err(&cctx->rpdev->dev, "Error: dsp information is incorrect err: %d\n", err); - kfree(dsp_attributes); - return err; - } - - spin_lock_irqsave(&cctx->lock, flags); - memcpy(cctx->dsp_attributes, dsp_attributes, FASTRPC_MAX_DSP_ATTRIBUTES_LEN); - cctx->valid_attributes = true; - spin_unlock_irqrestore(&cctx->lock, flags); - kfree(dsp_attributes); -done: - cap->capability = cctx->dsp_attributes[attribute_id]; - return 0; -} - -static int fastrpc_get_dsp_info(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_ioctl_capability cap = {0}; - int err = 0; - - if (copy_from_user(&cap, argp, sizeof(cap))) - return -EFAULT; - - cap.capability = 0; - if (cap.domain >= FASTRPC_DEV_MAX) { - dev_err(&fl->cctx->rpdev->dev, "Error: Invalid domain id:%d, err:%d\n", - cap.domain, err); - return -ECHRNG; - } - - /* Fastrpc Capablities does not support modem domain */ - if (cap.domain == MDSP_DOMAIN_ID) { - dev_err(&fl->cctx->rpdev->dev, "Error: modem not supported %d\n", err); - return -ECHRNG; - } - - if (cap.attribute_id >= FASTRPC_MAX_DSP_ATTRIBUTES) { - dev_err(&fl->cctx->rpdev->dev, "Error: invalid attribute: %d, err: %d\n", - cap.attribute_id, err); - return -EOVERFLOW; - } - - err = fastrpc_get_info_from_kernel(&cap, fl); - if (err) - return err; - - if (copy_to_user(argp, &cap.capability, sizeof(cap.capability))) - return -EFAULT; - - return 0; -} - -static int fastrpc_req_munmap_impl(struct fastrpc_user *fl, - struct fastrpc_req_munmap *req) -{ - struct fastrpc_invoke_args args[1] = { [0] = { 0 } }; - struct fastrpc_buf *buf, *b; - struct fastrpc_munmap_req_msg req_msg; - struct device *dev = fl->sctx->dev; - int err; - u32 sc; - - spin_lock(&fl->lock); - list_for_each_entry_safe(buf, b, &fl->mmaps, node) { - if ((buf->raddr == req->vaddrout) && (buf->size == req->size)) - break; - buf = NULL; - } - spin_unlock(&fl->lock); - - if (!buf) { - dev_err(dev, "mmap not in list\n"); - return -EINVAL; - } - - req_msg.pgid = fl->tgid; - req_msg.size = buf->size; - req_msg.vaddr = buf->raddr; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MUNMAP, 1, 0); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - if (!err) { - dev_dbg(dev, "unmmap\tpt 0x%09lx OK\n", buf->raddr); - spin_lock(&fl->lock); - list_del(&buf->node); - spin_unlock(&fl->lock); - fastrpc_buf_free(buf); - } else { - dev_err(dev, "unmmap\tpt 0x%09lx ERROR\n", buf->raddr); - } - - return err; -} - -static int fastrpc_req_munmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_req_munmap req; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - return fastrpc_req_munmap_impl(fl, &req); -} - -static int fastrpc_req_mmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args args[3] = { [0 ... 2] = { 0 } }; - struct fastrpc_buf *buf = NULL; - struct fastrpc_mmap_req_msg req_msg; - struct fastrpc_mmap_rsp_msg rsp_msg; - struct fastrpc_req_munmap req_unmap; - struct fastrpc_phy_page pages; - struct fastrpc_req_mmap req; - struct device *dev = fl->sctx->dev; - int err; - u32 sc; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - if (req.flags != ADSP_MMAP_ADD_PAGES) { - dev_err(dev, "flag not supported 0x%x\n", req.flags); - return -EINVAL; - } - - if (req.vaddrin) { - dev_err(dev, "adding user allocated pages is not supported\n"); - return -EINVAL; - } - - err = fastrpc_buf_alloc(fl, fl->sctx->dev, req.size, &buf); - if (err) { - dev_err(dev, "failed to allocate buffer\n"); - return err; - } - - req_msg.pgid = fl->tgid; - req_msg.flags = req.flags; - req_msg.vaddr = req.vaddrin; - req_msg.num = sizeof(pages); - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - pages.addr = buf->phys; - pages.size = buf->size; - - args[1].ptr = (u64) (uintptr_t) &pages; - args[1].length = sizeof(pages); - - args[2].ptr = (u64) (uintptr_t) &rsp_msg; - args[2].length = sizeof(rsp_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MMAP, 2, 1); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - if (err) { - dev_err(dev, "mmap error (len 0x%08llx)\n", buf->size); - goto err_invoke; - } - - /* update the buffer to be able to deallocate the memory on the DSP */ - buf->raddr = (uintptr_t) rsp_msg.vaddr; - - /* let the client know the address to use */ - req.vaddrout = rsp_msg.vaddr; - - spin_lock(&fl->lock); - list_add_tail(&buf->node, &fl->mmaps); - spin_unlock(&fl->lock); - - if (copy_to_user((void __user *)argp, &req, sizeof(req))) { - /* unmap the memory and release the buffer */ - req_unmap.vaddrout = buf->raddr; - req_unmap.size = buf->size; - fastrpc_req_munmap_impl(fl, &req_unmap); - return -EFAULT; - } - - dev_dbg(dev, "mmap\t\tpt 0x%09lx OK [len 0x%08llx]\n", - buf->raddr, buf->size); - - return 0; - -err_invoke: - fastrpc_buf_free(buf); - - return err; -} - -static int fastrpc_req_mem_unmap_impl(struct fastrpc_user *fl, struct fastrpc_mem_unmap *req) -{ - struct fastrpc_invoke_args args[1] = { [0] = { 0 } }; - struct fastrpc_map *map = NULL, *m; - struct fastrpc_mem_unmap_req_msg req_msg = { 0 }; - int err = 0; - u32 sc; - struct device *dev = fl->sctx->dev; - - spin_lock(&fl->lock); - list_for_each_entry_safe(map, m, &fl->maps, node) { - if ((req->fd < 0 || map->fd == req->fd) && (map->raddr == req->vaddr)) - break; - map = NULL; - } - - spin_unlock(&fl->lock); - - if (!map) { - dev_err(dev, "map not in list\n"); - return -EINVAL; - } - - req_msg.pgid = fl->tgid; - req_msg.len = map->len; - req_msg.vaddrin = map->raddr; - req_msg.fd = map->fd; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_UNMAP, 1, 0); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - fastrpc_map_put(map); - if (err) - dev_err(dev, "unmmap\tpt fd = %d, 0x%09llx error\n", map->fd, map->raddr); - - return err; -} - -static int fastrpc_req_mem_unmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_mem_unmap req; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - return fastrpc_req_mem_unmap_impl(fl, &req); -} - -static int fastrpc_req_mem_map(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args args[4] = { [0 ... 3] = { 0 } }; - struct fastrpc_mem_map_req_msg req_msg = { 0 }; - struct fastrpc_mmap_rsp_msg rsp_msg = { 0 }; - struct fastrpc_mem_unmap req_unmap = { 0 }; - struct fastrpc_phy_page pages = { 0 }; - struct fastrpc_mem_map req; - struct device *dev = fl->sctx->dev; - struct fastrpc_map *map = NULL; - int err; - u32 sc; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - /* create SMMU mapping */ - err = fastrpc_map_create(fl, req.fd, req.length, 0, &map); - if (err) { - dev_err(dev, "failed to map buffer, fd = %d\n", req.fd); - return err; - } - - req_msg.pgid = fl->tgid; - req_msg.fd = req.fd; - req_msg.offset = req.offset; - req_msg.vaddrin = req.vaddrin; - map->va = (void *) (uintptr_t) req.vaddrin; - req_msg.flags = req.flags; - req_msg.num = sizeof(pages); - req_msg.data_len = 0; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - pages.addr = map->phys; - pages.size = map->size; - - args[1].ptr = (u64) (uintptr_t) &pages; - args[1].length = sizeof(pages); - - args[2].ptr = (u64) (uintptr_t) &pages; - args[2].length = 0; - - args[3].ptr = (u64) (uintptr_t) &rsp_msg; - args[3].length = sizeof(rsp_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_MAP, 3, 1); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, &args[0]); - if (err) { - dev_err(dev, "mem mmap error, fd %d, vaddr %llx, size %lld\n", - req.fd, req.vaddrin, map->size); - goto err_invoke; - } - - /* update the buffer to be able to deallocate the memory on the DSP */ - map->raddr = rsp_msg.vaddr; - - /* let the client know the address to use */ - req.vaddrout = rsp_msg.vaddr; - - if (copy_to_user((void __user *)argp, &req, sizeof(req))) { - /* unmap the memory and release the buffer */ - req_unmap.vaddr = (uintptr_t) rsp_msg.vaddr; - req_unmap.length = map->size; - fastrpc_req_mem_unmap_impl(fl, &req_unmap); - return -EFAULT; - } - - return 0; - -err_invoke: - fastrpc_map_put(map); - - return err; -} - -static long fastrpc_device_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - struct fastrpc_user *fl = (struct fastrpc_user *)file->private_data; - char __user *argp = (char __user *)arg; - int err; - - switch (cmd) { - case FASTRPC_IOCTL_INVOKE: - err = fastrpc_invoke(fl, argp); - break; - case FASTRPC_IOCTL_INIT_ATTACH: - err = fastrpc_init_attach(fl, AUDIO_PD); - break; - case FASTRPC_IOCTL_INIT_ATTACH_SNS: - err = fastrpc_init_attach(fl, SENSORS_PD); - break; - case FASTRPC_IOCTL_INIT_CREATE: - err = fastrpc_init_create_process(fl, argp); - break; - case FASTRPC_IOCTL_ALLOC_DMA_BUFF: - err = fastrpc_dmabuf_alloc(fl, argp); - break; - case FASTRPC_IOCTL_MMAP: - err = fastrpc_req_mmap(fl, argp); - break; - case FASTRPC_IOCTL_MUNMAP: - err = fastrpc_req_munmap(fl, argp); - break; - case FASTRPC_IOCTL_MEM_MAP: - err = fastrpc_req_mem_map(fl, argp); - break; - case FASTRPC_IOCTL_MEM_UNMAP: - err = fastrpc_req_mem_unmap(fl, argp); - break; - case FASTRPC_IOCTL_GET_DSP_INFO: - err = fastrpc_get_dsp_info(fl, argp); - break; - default: - err = -ENOTTY; - break; - } - - return err; -} - -static const struct file_operations fastrpc_fops = { - .open = fastrpc_device_open, - .release = fastrpc_device_release, - .unlocked_ioctl = fastrpc_device_ioctl, - .compat_ioctl = fastrpc_device_ioctl, -}; - -static int fastrpc_cb_probe(struct platform_device *pdev) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_session_ctx *sess; - struct device *dev = &pdev->dev; - int i, sessions = 0; - unsigned long flags; - int rc; - - cctx = dev_get_drvdata(dev->parent); - if (!cctx) - return -EINVAL; - - of_property_read_u32(dev->of_node, "qcom,nsessions", &sessions); - - spin_lock_irqsave(&cctx->lock, flags); - sess = &cctx->session[cctx->sesscount]; - sess->used = false; - sess->valid = true; - sess->dev = dev; - dev_set_drvdata(dev, sess); - - if (of_property_read_u32(dev->of_node, "reg", &sess->sid)) - dev_info(dev, "FastRPC Session ID not specified in DT\n"); - - if (sessions > 0) { - struct fastrpc_session_ctx *dup_sess; - - for (i = 1; i < sessions; i++) { - if (cctx->sesscount++ >= FASTRPC_MAX_SESSIONS) - break; - dup_sess = &cctx->session[cctx->sesscount]; - memcpy(dup_sess, sess, sizeof(*dup_sess)); - } - } - cctx->sesscount++; - spin_unlock_irqrestore(&cctx->lock, flags); - rc = dma_set_mask(dev, DMA_BIT_MASK(32)); - if (rc) { - dev_err(dev, "32-bit DMA enable failed\n"); - return rc; - } - - return 0; -} - -static int fastrpc_cb_remove(struct platform_device *pdev) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(pdev->dev.parent); - struct fastrpc_session_ctx *sess = dev_get_drvdata(&pdev->dev); - unsigned long flags; - int i; - - spin_lock_irqsave(&cctx->lock, flags); - for (i = 1; i < FASTRPC_MAX_SESSIONS; i++) { - if (cctx->session[i].sid == sess->sid) { - cctx->session[i].valid = false; - cctx->sesscount--; - } - } - spin_unlock_irqrestore(&cctx->lock, flags); - - return 0; -} - -static const struct of_device_id fastrpc_match_table[] = { - { .compatible = "qcom,fastrpc-compute-cb", }, - {} -}; - -static struct platform_driver fastrpc_cb_driver = { - .probe = fastrpc_cb_probe, - .remove = fastrpc_cb_remove, - .driver = { - .name = "qcom,fastrpc-cb", - .of_match_table = fastrpc_match_table, - .suppress_bind_attrs = true, - }, -}; - -static int fastrpc_device_register(struct device *dev, struct fastrpc_channel_ctx *cctx, - bool is_secured, const char *domain) -{ - struct fastrpc_device *fdev; - int err; - - fdev = devm_kzalloc(dev, sizeof(*fdev), GFP_KERNEL); - if (!fdev) - return -ENOMEM; - - fdev->secure = is_secured; - fdev->cctx = cctx; - fdev->miscdev.minor = MISC_DYNAMIC_MINOR; - fdev->miscdev.fops = &fastrpc_fops; - fdev->miscdev.name = devm_kasprintf(dev, GFP_KERNEL, "fastrpc-%s%s", - domain, is_secured ? "-secure" : ""); - err = misc_register(&fdev->miscdev); - if (!err) { - if (is_secured) - cctx->secure_fdevice = fdev; - else - cctx->fdevice = fdev; - } - - return err; -} - -static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) -{ - struct device *rdev = &rpdev->dev; - struct fastrpc_channel_ctx *data; - int i, err, domain_id = -1, vmcount; - const char *domain; - bool secure_dsp; - unsigned int vmids[FASTRPC_MAX_VMIDS]; - - err = of_property_read_string(rdev->of_node, "label", &domain); - if (err) { - dev_info(rdev, "FastRPC Domain not specified in DT\n"); - return err; - } - - for (i = 0; i <= CDSP_DOMAIN_ID; i++) { - if (!strcmp(domains[i], domain)) { - domain_id = i; - break; - } - } - - if (domain_id < 0) { - dev_info(rdev, "FastRPC Invalid Domain ID %d\n", domain_id); - return -EINVAL; - } - - vmcount = of_property_read_variable_u32_array(rdev->of_node, - "qcom,vmids", &vmids[0], 0, FASTRPC_MAX_VMIDS); - if (vmcount < 0) - vmcount = 0; - else if (!qcom_scm_is_available()) - return -EPROBE_DEFER; - - data = kzalloc(sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - if (vmcount) { - data->vmcount = vmcount; - data->perms = BIT(QCOM_SCM_VMID_HLOS); - for (i = 0; i < data->vmcount; i++) { - data->vmperms[i].vmid = vmids[i]; - data->vmperms[i].perm = QCOM_SCM_PERM_RWX; - } - } - - secure_dsp = !(of_property_read_bool(rdev->of_node, "qcom,non-secure-domain")); - data->secure = secure_dsp; - - switch (domain_id) { - case ADSP_DOMAIN_ID: - case MDSP_DOMAIN_ID: - case SDSP_DOMAIN_ID: - /* Unsigned PD offloading is only supported on CDSP*/ - data->unsigned_support = false; - err = fastrpc_device_register(rdev, data, secure_dsp, domains[domain_id]); - if (err) - goto fdev_error; - break; - case CDSP_DOMAIN_ID: - data->unsigned_support = true; - /* Create both device nodes so that we can allow both Signed and Unsigned PD */ - err = fastrpc_device_register(rdev, data, true, domains[domain_id]); - if (err) - goto fdev_error; - - err = fastrpc_device_register(rdev, data, false, domains[domain_id]); - if (err) - goto fdev_error; - break; - default: - err = -EINVAL; - goto fdev_error; - } - - kref_init(&data->refcount); - - dev_set_drvdata(&rpdev->dev, data); - dma_set_mask_and_coherent(rdev, DMA_BIT_MASK(32)); - INIT_LIST_HEAD(&data->users); - spin_lock_init(&data->lock); - idr_init(&data->ctx_idr); - data->domain_id = domain_id; - data->rpdev = rpdev; - - return of_platform_populate(rdev->of_node, NULL, NULL, rdev); -fdev_error: - kfree(data); - return err; -} - -static void fastrpc_notify_users(struct fastrpc_user *user) -{ - struct fastrpc_invoke_ctx *ctx; - - spin_lock(&user->lock); - list_for_each_entry(ctx, &user->pending, node) - complete(&ctx->work); - spin_unlock(&user->lock); -} - -static void fastrpc_rpmsg_remove(struct rpmsg_device *rpdev) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(&rpdev->dev); - struct fastrpc_user *user; - unsigned long flags; - - spin_lock_irqsave(&cctx->lock, flags); - list_for_each_entry(user, &cctx->users, user) - fastrpc_notify_users(user); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (cctx->fdevice) - misc_deregister(&cctx->fdevice->miscdev); - - if (cctx->secure_fdevice) - misc_deregister(&cctx->secure_fdevice->miscdev); - - of_platform_depopulate(&rpdev->dev); - - cctx->rpdev = NULL; - fastrpc_channel_ctx_put(cctx); -} - -static int fastrpc_rpmsg_callback(struct rpmsg_device *rpdev, void *data, - int len, void *priv, u32 addr) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(&rpdev->dev); - struct fastrpc_invoke_rsp *rsp = data; - struct fastrpc_invoke_ctx *ctx; - unsigned long flags; - unsigned long ctxid; - - if (len < sizeof(*rsp)) - return -EINVAL; - - ctxid = ((rsp->ctx & FASTRPC_CTXID_MASK) >> 4); - - spin_lock_irqsave(&cctx->lock, flags); - ctx = idr_find(&cctx->ctx_idr, ctxid); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (!ctx) { - dev_err(&rpdev->dev, "No context ID matches response\n"); - return -ENOENT; - } - - ctx->retval = rsp->retval; - complete(&ctx->work); - - /* - * The DMA buffer associated with the context cannot be freed in - * interrupt context so schedule it through a worker thread to - * avoid a kernel BUG. - */ - schedule_work(&ctx->put_work); - - return 0; -} - -static const struct of_device_id fastrpc_rpmsg_of_match[] = { - { .compatible = "qcom,fastrpc" }, - { }, -}; -MODULE_DEVICE_TABLE(of, fastrpc_rpmsg_of_match); - -static struct rpmsg_driver fastrpc_driver = { - .probe = fastrpc_rpmsg_probe, - .remove = fastrpc_rpmsg_remove, - .callback = fastrpc_rpmsg_callback, - .drv = { - .name = "qcom,fastrpc", - .of_match_table = fastrpc_rpmsg_of_match, - }, -}; - -static int fastrpc_init(void) -{ - int ret; - - ret = platform_driver_register(&fastrpc_cb_driver); - if (ret < 0) { - pr_err("fastrpc: failed to register cb driver\n"); - return ret; - } - - ret = register_rpmsg_driver(&fastrpc_driver); - if (ret < 0) { - pr_err("fastrpc: failed to register rpmsg driver\n"); - platform_driver_unregister(&fastrpc_cb_driver); - return ret; - } - - return 0; -} -module_init(fastrpc_init); - -static void fastrpc_exit(void) -{ - platform_driver_unregister(&fastrpc_cb_driver); - unregister_rpmsg_driver(&fastrpc_driver); -} -module_exit(fastrpc_exit); - -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/bc7d9698dba1c29a1e7f828eeb3346db01a8d266/preimage b/rr-cache/bc7d9698dba1c29a1e7f828eeb3346db01a8d266/preimage deleted file mode 100644 index 9837851..0000000 --- a/rr-cache/bc7d9698dba1c29a1e7f828eeb3346db01a8d266/preimage +++ /dev/null @@ -1,1333 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_NUMA_BALANCING=y -CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_HUGETLB=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_USER_NS=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_ARCH_ACTIONS=y -CONFIG_ARCH_SUNXI=y -CONFIG_ARCH_ALPINE=y -CONFIG_ARCH_APPLE=y -CONFIG_ARCH_BCM2835=y -CONFIG_ARCH_BCM4908=y -CONFIG_ARCH_BCM_IPROC=y -CONFIG_ARCH_BERLIN=y -CONFIG_ARCH_BRCMSTB=y -CONFIG_ARCH_EXYNOS=y -CONFIG_ARCH_K3=y -CONFIG_ARCH_LAYERSCAPE=y -CONFIG_ARCH_LG1K=y -CONFIG_ARCH_HISI=y -CONFIG_ARCH_KEEMBAY=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MESON=y -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_MXC=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_RENESAS=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_S32=y -CONFIG_ARCH_SEATTLE=y -CONFIG_ARCH_INTEL_SOCFPGA=y -CONFIG_ARCH_SYNQUACER=y -CONFIG_ARCH_TEGRA=y -CONFIG_ARCH_SPRD=y -CONFIG_ARCH_THUNDER=y -CONFIG_ARCH_THUNDER2=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_ARCH_VEXPRESS=y -CONFIG_ARCH_VISCONTI=y -CONFIG_ARCH_XGENE=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_ARM64_VA_BITS_48=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_SMT=y -CONFIG_NUMA=y -CONFIG_SECCOMP=y -CONFIG_KEXEC=y -CONFIG_KEXEC_FILE=y -CONFIG_CRASH_DUMP=y -CONFIG_XEN=y -CONFIG_COMPAT=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_HIBERNATION=y -CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -CONFIG_ENERGY_MODEL=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPUFREQ_DT=y -CONFIG_ACPI_CPPC_CPUFREQ=m -CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m -CONFIG_ARM_ARMADA_37XX_CPUFREQ=y -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_IMX_CPUFREQ_DT=m -CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y -CONFIG_ARM_QCOM_CPUFREQ_HW=y -CONFIG_ARM_RASPBERRYPI_CPUFREQ=m -CONFIG_ARM_SCMI_CPUFREQ=y -CONFIG_ARM_TEGRA186_CPUFREQ=y -CONFIG_QORIQ_CPUFREQ=y -CONFIG_ARM_SCMI_PROTOCOL=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_RASPBERRYPI_FIRMWARE=y -CONFIG_INTEL_STRATIX10_SERVICE=y -CONFIG_INTEL_STRATIX10_RSU=m -CONFIG_QCOM_SCM=y -CONFIG_EFI_CAPSULE_LOADER=y -CONFIG_IMX_SCU=y -CONFIG_IMX_SCU_PD=y -CONFIG_ACPI=y -CONFIG_ACPI_APEI=y -CONFIG_ACPI_APEI_GHES=y -CONFIG_ACPI_APEI_PCIEAER=y -CONFIG_ACPI_APEI_MEMORY_FAILURE=y -CONFIG_ACPI_APEI_EINJ=y -CONFIG_VIRTUALIZATION=y -CONFIG_KVM=y -CONFIG_ARM64_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64_CE=m -CONFIG_CRYPTO_SHA3_ARM64=m -CONFIG_CRYPTO_SM3_ARM64_CE=m -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_AES_ARM64_BS=m -CONFIG_JUMP_LABEL=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_BLK_INLINE_ENCRYPTION=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_KSM=y -CONFIG_MEMORY_FAILURE=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=m -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_NET_DSA=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBS=m -CONFIG_NET_SCH_ETF=m -CONFIG_NET_SCH_TAPRIO=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_GACT=m -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_GATE=m -CONFIG_QRTR=m -CONFIG_QRTR_SMD=m -CONFIG_QRTR_TUN=m -CONFIG_BPF_JIT=y -CONFIG_CAN=m -CONFIG_CAN_RCAR=m -CONFIG_CAN_RCAR_CANFD=m -CONFIG_CAN_FLEXCAN=m -CONFIG_CAN_MCP251XFD=m -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -# CONFIG_BT_HS is not set -# CONFIG_BT_LE is not set -CONFIG_BT_LEDS=y -# CONFIG_BT_DEBUGFS is not set -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIUART_3WIRE=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HCIUART_QCA=y -CONFIG_BT_QCOMSMD=m -CONFIG_CFG80211=m -CONFIG_CFG80211_WEXT=y -CONFIG_MAC80211=m -CONFIG_MAC80211_LEDS=y -CONFIG_RFKILL=y -<<<<<<< -======= -CONFIG_WCN36XX=m ->>>>>>> -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y -CONFIG_NFC=m -CONFIG_NFC_NCI=m -CONFIG_NFC_S3FWRN5_I2C=m -CONFIG_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCI_IOV=y -CONFIG_PCI_PASID=y -CONFIG_HOTPLUG_PCI=y -CONFIG_HOTPLUG_PCI_ACPI=y -CONFIG_PCI_AARDVARK=y -CONFIG_PCI_TEGRA=y -CONFIG_PCIE_RCAR_HOST=y -CONFIG_PCIE_RCAR_EP=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCI_XGENE=y -CONFIG_PCIE_ALTERA=y -CONFIG_PCIE_ALTERA_MSI=y -CONFIG_PCI_HOST_THUNDER_PEM=y -CONFIG_PCI_HOST_THUNDER_ECAM=y -CONFIG_PCIE_ROCKCHIP_HOST=m -CONFIG_PCIE_BRCMSTB=m -CONFIG_PCI_IMX6=y -CONFIG_PCI_LAYERSCAPE=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y -CONFIG_PCI_HISI=y -CONFIG_PCIE_QCOM=y -CONFIG_PCIE_ARMADA_8K=y -CONFIG_PCIE_KIRIN=y -CONFIG_PCIE_HISI_STB=y -CONFIG_PCIE_TEGRA194_HOST=m -CONFIG_PCIE_VISCONTI_HOST=y -CONFIG_PCI_ENDPOINT=y -CONFIG_PCI_ENDPOINT_CONFIGFS=y -CONFIG_PCI_EPF_TEST=m -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_HISILICON_LPC=y -CONFIG_FSL_MC_BUS=y -CONFIG_TEGRA_ACONNECT=m -CONFIG_GNSS=m -CONFIG_GNSS_MTK_SERIAL=m -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_SST25L=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_DENALI_DT=y -CONFIG_MTD_NAND_MARVELL=y -CONFIG_MTD_NAND_FSL_IFC=y -CONFIG_MTD_NAND_QCOM=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTK_DEVAPC=m -CONFIG_SPI_CADENCE_QUADSPI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=m -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_NVME=m -CONFIG_QCOM_COINCELL=m -CONFIG_QCOM_FASTRPC=m -CONFIG_SRAM=y -CONFIG_PCI_ENDPOINT_TEST=m -CONFIG_EEPROM_AT24=m -CONFIG_EEPROM_AT25=m -CONFIG_UACCE=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_SAS_ATA=y -CONFIG_SCSI_HISI_SAS=y -CONFIG_SCSI_HISI_SAS_PCI=y -CONFIG_MEGARAID_SAS=y -CONFIG_SCSI_MPT3SAS=m -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=y -CONFIG_SCSI_UFS_HISI=y -CONFIG_SCSI_UFS_EXYNOS=y -CONFIG_SCSI_UFS_CRYPTO=y -CONFIG_ATA=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_AHCI_CEVA=y -CONFIG_AHCI_MVEBU=y -CONFIG_AHCI_XGENE=y -CONFIG_AHCI_QORIQ=y -CONFIG_SATA_SIL24=y -CONFIG_SATA_RCAR=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_OF_PLATFORM=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_NETDEVICES=y -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_TUN=y -CONFIG_VETH=m -CONFIG_VIRTIO_NET=y -CONFIG_NET_DSA_MSCC_FELIX=m -CONFIG_AMD_XGBE=y -CONFIG_NET_XGENE=y -CONFIG_ATL1C=m -CONFIG_BCMGENET=m -CONFIG_BNX2X=m -CONFIG_MACB=y -CONFIG_THUNDER_NIC_PF=y -CONFIG_FEC=y -CONFIG_FSL_FMAN=y -CONFIG_FSL_DPAA_ETH=y -CONFIG_FSL_DPAA2_ETH=y -CONFIG_FSL_ENETC=y -CONFIG_FSL_ENETC_VF=y -CONFIG_FSL_ENETC_QOS=y -CONFIG_HIX5HD2_GMAC=y -CONFIG_HNS_DSAF=y -CONFIG_HNS_ENET=y -CONFIG_HNS3=y -CONFIG_HNS3_HCLGE=y -CONFIG_HNS3_ENET=y -CONFIG_E1000=y -CONFIG_E1000E=y -CONFIG_IGB=y -CONFIG_IGBVF=y -CONFIG_MVNETA=y -CONFIG_MVPP2=y -CONFIG_SKY2=y -CONFIG_MLX4_EN=m -CONFIG_MLX5_CORE=m -CONFIG_MLX5_CORE_EN=y -CONFIG_QCOM_EMAC=m -CONFIG_RMNET=m -CONFIG_SH_ETH=y -CONFIG_RAVB=y -CONFIG_SMC91X=y -CONFIG_SMSC911X=y -CONFIG_SNI_AVE=y -CONFIG_SNI_NETSEC=y -CONFIG_STMMAC_ETH=m -CONFIG_TI_K3_AM65_CPSW_NUSS=y -CONFIG_QCOM_IPA=m -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -CONFIG_AQUANTIA_PHY=y -CONFIG_BCM54140_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_MARVELL_10G_PHY=m -CONFIG_MESON_GXL_PHY=m -CONFIG_MICREL_PHY=y -CONFIG_MICROSEMI_PHY=y -CONFIG_AT803X_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_ROCKCHIP_PHY=y -CONFIG_DP83867_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9800=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_ATH10K_SNOC=m -CONFIG_WCN36XX=m -CONFIG_ATH11K=m -CONFIG_ATH11K_AHB=m -CONFIG_ATH11K_PCI=m -CONFIG_BRCMFMAC=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_PCIE=m -CONFIG_WL18XX=m -CONFIG_WLCORE_SDIO=m -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_ADC=m -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_SNVS_PWRKEY=m -CONFIG_KEYBOARD_IMX_SC_KEY=m -CONFIG_KEYBOARD_CROS_EC=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=m -CONFIG_TOUCHSCREEN_GOODIX=m -CONFIG_TOUCHSCREEN_EDT_FT5X06=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_PM8941_PWRKEY=y -CONFIG_INPUT_PM8XXX_VIBRATOR=m -CONFIG_INPUT_PWM_BEEPER=m -CONFIG_INPUT_PWM_VIBRA=m -CONFIG_INPUT_HISI_POWERKEY=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIO_AMBAKMI=y -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_BCM2835AUX=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_OMAP=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_UNIPHIER=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_MESON=y -CONFIG_SERIAL_MESON_CONSOLE=y -CONFIG_SERIAL_SAMSUNG=y -CONFIG_SERIAL_SAMSUNG_CONSOLE=y -CONFIG_SERIAL_TEGRA=y -CONFIG_SERIAL_TEGRA_TCU=y -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SERIAL_QCOM_GENI=y -CONFIG_SERIAL_QCOM_GENI_CONSOLE=y -CONFIG_SERIAL_XILINX_PS_UART=y -CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -CONFIG_SERIAL_FSL_LPUART=y -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -CONFIG_SERIAL_FSL_LINFLEXUART=y -CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -CONFIG_SERIAL_MVEBU_UART=y -CONFIG_SERIAL_OWL=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_IPMI_HANDLER=m -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SI=m -CONFIG_TCG_TPM=y -CONFIG_TCG_TIS_I2C_INFINEON=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_I2C_BCM2835=m -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_I2C_GPIO=m -CONFIG_I2C_IMX=y -CONFIG_I2C_IMX_LPI2C=y -CONFIG_I2C_MESON=y -CONFIG_I2C_MT65XX=y -CONFIG_I2C_MV64XXX=y -CONFIG_I2C_OMAP=y -CONFIG_I2C_OWL=y -CONFIG_I2C_PXA=y -CONFIG_I2C_QCOM_CCI=m -CONFIG_I2C_QCOM_GENI=m -CONFIG_I2C_QUP=y -CONFIG_I2C_RIIC=y -CONFIG_I2C_RK3X=y -CONFIG_I2C_S3C2410=y -CONFIG_I2C_SH_MOBILE=y -CONFIG_I2C_TEGRA=y -CONFIG_I2C_UNIPHIER_F=y -CONFIG_I2C_RCAR=y -CONFIG_I2C_CROS_EC_TUNNEL=y -CONFIG_SPI=y -CONFIG_SPI_ARMADA_3700=y -CONFIG_SPI_BCM2835=m -CONFIG_SPI_BCM2835AUX=m -CONFIG_SPI_DESIGNWARE=m -CONFIG_SPI_DW_DMA=y -CONFIG_SPI_DW_MMIO=m -CONFIG_SPI_FSL_LPSPI=y -CONFIG_SPI_FSL_QUADSPI=y -CONFIG_SPI_NXP_FLEXSPI=y -CONFIG_SPI_IMX=m -CONFIG_SPI_FSL_DSPI=y -CONFIG_SPI_MESON_SPICC=m -CONFIG_SPI_MESON_SPIFC=m -CONFIG_SPI_ORION=y -CONFIG_SPI_PL022=y -CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_RPCIF=m -CONFIG_SPI_QCOM_QSPI=m -CONFIG_SPI_QUP=y -CONFIG_SPI_QCOM_GENI=m -CONFIG_SPI_S3C64XX=y -CONFIG_SPI_SH_MSIOF=m -CONFIG_SPI_SUN6I=y -CONFIG_SPI_SPIDEV=m -CONFIG_SPMI=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_PINCTRL_MAX77620=y -CONFIG_PINCTRL_OWL=y -CONFIG_PINCTRL_S700=y -CONFIG_PINCTRL_S900=y -CONFIG_PINCTRL_IMX8MM=y -CONFIG_PINCTRL_IMX8MN=y -CONFIG_PINCTRL_IMX8MP=y -CONFIG_PINCTRL_IMX8MQ=y -CONFIG_PINCTRL_IMX8QM=y -CONFIG_PINCTRL_IMX8QXP=y -CONFIG_PINCTRL_IMX8DXL=y -CONFIG_PINCTRL_IMX8ULP=y -CONFIG_PINCTRL_MSM=y -CONFIG_PINCTRL_IPQ8074=y -CONFIG_PINCTRL_IPQ6018=y -CONFIG_PINCTRL_MSM8916=y -CONFIG_PINCTRL_MSM8994=y -CONFIG_PINCTRL_MSM8996=y -CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_QCS404=y -CONFIG_PINCTRL_QDF2XXX=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -CONFIG_PINCTRL_SC7180=y -CONFIG_PINCTRL_SC7280=y -CONFIG_PINCTRL_SDM845=y -CONFIG_PINCTRL_SM8150=y -CONFIG_PINCTRL_SM8250=y -CONFIG_PINCTRL_SM8350=y -<<<<<<< -CONFIG_PINCTRL_LPASS_LPI=y -======= -CONFIG_PINCTRL_SM8450=y -CONFIG_PINCTRL_LPASS_LPI=m ->>>>>>> -CONFIG_GPIO_ALTERA=m -CONFIG_GPIO_DAVINCI=y -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_MB86S7X=y -CONFIG_GPIO_MPC8XXX=y -CONFIG_GPIO_MXC=y -CONFIG_GPIO_PL061=y -CONFIG_GPIO_RCAR=y -CONFIG_GPIO_UNIPHIER=y -CONFIG_GPIO_VISCONTI=y -CONFIG_GPIO_WCD934X=m -CONFIG_GPIO_XGENE=y -CONFIG_GPIO_XGENE_SB=y -CONFIG_GPIO_MAX732X=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_BD9571MWV=m -CONFIG_GPIO_MAX77620=y -CONFIG_GPIO_SL28CPLD=m -CONFIG_POWER_AVS=y -CONFIG_QCOM_CPR=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_RESET_QCOM_PON=m -CONFIG_POWER_RESET_XGENE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_SYSCON_REBOOT_MODE=y -CONFIG_BATTERY_SBS=m -CONFIG_BATTERY_BQ27XXX=y -CONFIG_SENSORS_ARM_SCMI=y -CONFIG_BATTERY_MAX17042=m -CONFIG_CHARGER_BQ25890=m -CONFIG_CHARGER_BQ25980=m -CONFIG_SENSORS_ARM_SCPI=y -CONFIG_SENSORS_JC42=m -CONFIG_SENSORS_LM90=m -CONFIG_SENSORS_PWM_FAN=m -CONFIG_SENSORS_RASPBERRYPI_HWMON=m -CONFIG_SENSORS_SL28CPLD=m -CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_INA3221=m -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_CPU_THERMAL=y -CONFIG_THERMAL_EMULATION=y -CONFIG_QORIQ_THERMAL=m -CONFIG_SUN8I_THERMAL=y -CONFIG_IMX_SC_THERMAL=m -CONFIG_IMX8MM_THERMAL=m -CONFIG_ROCKCHIP_THERMAL=m -CONFIG_RCAR_THERMAL=y -CONFIG_RCAR_GEN3_THERMAL=y -CONFIG_ARMADA_THERMAL=y -CONFIG_BCM2711_THERMAL=m -CONFIG_BCM2835_THERMAL=m -CONFIG_BRCMSTB_THERMAL=m -CONFIG_EXYNOS_THERMAL=y -CONFIG_TEGRA_BPMP_THERMAL=m -CONFIG_TEGRA_SOCTHERM=m -CONFIG_QCOM_TSENS=y -CONFIG_QCOM_SPMI_TEMP_ALARM=m -CONFIG_QCOM_LMH=m -CONFIG_QCOM_SPMI_ADC_TM5=m -CONFIG_UNIPHIER_THERMAL=y -CONFIG_WATCHDOG=y -CONFIG_SL28CPLD_WATCHDOG=m -CONFIG_PM8916_WATCHDOG=y -CONFIG_ARM_SP805_WATCHDOG=y -CONFIG_ARM_SBSA_WATCHDOG=y -CONFIG_ARM_SMC_WATCHDOG=y -CONFIG_S3C2410_WATCHDOG=y -CONFIG_DW_WATCHDOG=y -CONFIG_SUNXI_WATCHDOG=m -CONFIG_IMX2_WDT=y -CONFIG_IMX_SC_WDT=m -CONFIG_QCOM_WDT=m -CONFIG_MESON_GXBB_WATCHDOG=m -CONFIG_MESON_WATCHDOG=m -CONFIG_RENESAS_WDT=y -CONFIG_UNIPHIER_WATCHDOG=y -CONFIG_BCM2835_WDT=y -CONFIG_MFD_ALTERA_SYSMGR=y -CONFIG_MFD_BD9571MWV=y -CONFIG_MFD_AXP20X_I2C=y -CONFIG_MFD_AXP20X_RSB=y -CONFIG_MFD_EXYNOS_LPASS=m -CONFIG_MFD_HI6421_PMIC=y -CONFIG_MFD_HI655X_PMIC=y -CONFIG_MFD_MAX77620=y -CONFIG_MFD_MT6397=y -CONFIG_MFD_QCOM_QCA639X=y -CONFIG_MFD_QCOM_RPM=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_MFD_RK808=y -CONFIG_MFD_SEC_CORE=y -CONFIG_MFD_SL28CPLD=y -CONFIG_MFD_ROHM_BD718XX=y -CONFIG_MFD_WCD934X=m -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_AXP20X=y -CONFIG_REGULATOR_BD718XX=y -CONFIG_REGULATOR_BD9571MWV=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_HI6421V530=y -CONFIG_REGULATOR_HI655X=y -CONFIG_REGULATOR_MAX77620=y -CONFIG_REGULATOR_MAX8973=y -CONFIG_REGULATOR_MP8859=y -CONFIG_REGULATOR_MT6358=y -CONFIG_REGULATOR_MT6397=y -CONFIG_REGULATOR_PCA9450=y -CONFIG_REGULATOR_PF8X00=y -CONFIG_REGULATOR_PFUZE100=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_QCOM_RPMH=y -CONFIG_REGULATOR_QCOM_SMD_RPM=y -CONFIG_REGULATOR_QCOM_SPMI=y -CONFIG_REGULATOR_QCOM_USB_VBUS=m -CONFIG_REGULATOR_RK808=y -CONFIG_REGULATOR_S2MPS11=y -CONFIG_REGULATOR_TPS65132=m -CONFIG_REGULATOR_VCTRL=m -CONFIG_RC_CORE=m -CONFIG_RC_DECODERS=y -CONFIG_RC_DEVICES=y -CONFIG_IR_MESON=m -CONFIG_IR_SUNXI=m -CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y -# CONFIG_DVB_NET is not set -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VIDEO_RCAR_CSI2=m -CONFIG_VIDEO_RCAR_VIN=m -CONFIG_VIDEO_SUN6I_CSI=m -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m -CONFIG_VIDEO_SAMSUNG_S5P_MFC=m -CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m -CONFIG_VIDEO_RENESAS_FDP1=m -CONFIG_VIDEO_RENESAS_FCP=m -CONFIG_VIDEO_RENESAS_VSP1=m -CONFIG_VIDEO_QCOM_VENUS=m -CONFIG_SDR_PLATFORM_DRIVERS=y -CONFIG_VIDEO_RCAR_DRIF=m -CONFIG_VIDEO_IMX219=m -CONFIG_VIDEO_OV5640=m -CONFIG_VIDEO_OV5645=m -CONFIG_VIDEO_QCOM_CAMSS=m -CONFIG_VIDEO_QCOM_VENUS=m -CONFIG_DRM=m -CONFIG_DRM_I2C_NXP_TDA998X=m -CONFIG_DRM_MALI_DISPLAY=m -CONFIG_DRM_NOUVEAU=m -CONFIG_DRM_EXYNOS=m -CONFIG_DRM_EXYNOS5433_DECON=y -CONFIG_DRM_EXYNOS7_DECON=y -CONFIG_DRM_EXYNOS_DSI=y -# CONFIG_DRM_EXYNOS_DP is not set -CONFIG_DRM_EXYNOS_HDMI=y -CONFIG_DRM_EXYNOS_MIC=y -CONFIG_DRM_ROCKCHIP=m -CONFIG_ROCKCHIP_ANALOGIX_DP=y -CONFIG_ROCKCHIP_CDN_DP=y -CONFIG_ROCKCHIP_DW_HDMI=y -CONFIG_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_ROCKCHIP_INNO_HDMI=y -CONFIG_ROCKCHIP_LVDS=y -CONFIG_DRM_RCAR_DU=m -CONFIG_DRM_RCAR_DW_HDMI=m -CONFIG_DRM_SUN4I=m -CONFIG_DRM_SUN6I_DSI=m -CONFIG_DRM_SUN8I_DW_HDMI=m -CONFIG_DRM_SUN8I_MIXER=m -CONFIG_DRM_MSM=m -CONFIG_DRM_TEGRA=m -CONFIG_DRM_PANEL_LVDS=m -CONFIG_DRM_PANEL_SIMPLE=m -CONFIG_DRM_PANEL_EDP=m -CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m -CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m -CONFIG_DRM_PANEL_RAYDIUM_RM67191=m -CONFIG_DRM_PANEL_SITRONIX_ST7703=m -CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m -CONFIG_DRM_DISPLAY_CONNECTOR=m -CONFIG_DRM_LONTIUM_LT8912B=m -CONFIG_DRM_NWL_MIPI_DSI=m -CONFIG_DRM_LONTIUM_LT9611=m -CONFIG_DRM_PARADE_PS8640=m -CONFIG_DRM_SII902X=m -CONFIG_DRM_SIMPLE_BRIDGE=m -CONFIG_DRM_THINE_THC63LVD1024=m -CONFIG_DRM_TI_SN65DSI86=m -CONFIG_DRM_LONTIUM_LT9611UXC=m -CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m -CONFIG_DRM_LONTIUM_LT9611=m -CONFIG_DRM_LONTIUM_LT9611UXC=m -CONFIG_DRM_I2C_ADV7511=m -CONFIG_DRM_I2C_ADV7511_AUDIO=y -CONFIG_DRM_DW_HDMI_AHB_AUDIO=m -CONFIG_DRM_DW_HDMI_CEC=m -CONFIG_DRM_IMX_DCSS=m -CONFIG_DRM_VC4=m -CONFIG_DRM_ETNAVIV=m -CONFIG_DRM_HISI_HIBMC=m -CONFIG_DRM_HISI_KIRIN=m -CONFIG_DRM_MEDIATEK=m -CONFIG_DRM_MEDIATEK_HDMI=m -CONFIG_DRM_MXSFB=m -CONFIG_DRM_MESON=m -CONFIG_DRM_PL111=m -CONFIG_DRM_LIMA=m -CONFIG_DRM_PANFROST=m -CONFIG_FB=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_EFI=y -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_LP855X=m -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_HDA_TEGRA=m -CONFIG_SND_HDA_CODEC_HDMI=m -CONFIG_SND_SOC=y -CONFIG_SND_BCM2835_SOC_I2S=m -CONFIG_SND_SOC_FSL_SAI=m -CONFIG_SND_SOC_FSL_ASRC=m -CONFIG_SND_SOC_FSL_MICFIL=m -CONFIG_SND_SOC_FSL_EASRC=m -CONFIG_SND_IMX_SOC=m -CONFIG_SND_SOC_IMX_SGTL5000=m -CONFIG_SND_SOC_IMX_SPDIF=m -CONFIG_SND_SOC_IMX_AUDMIX=m -CONFIG_SND_SOC_FSL_ASOC_CARD=m -CONFIG_SND_MESON_AXG_SOUND_CARD=m -CONFIG_SND_MESON_GX_SOUND_CARD=m -CONFIG_SND_SOC_QCOM=m -CONFIG_SND_SOC_APQ8016_SBC=m -CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m -CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -CONFIG_SND_SOC_MSM8996=m -CONFIG_SND_SOC_QDSP6=m -CONFIG_SND_SOC_SDM845=m -CONFIG_SND_SOC_SM8250=m -CONFIG_SND_SOC_ROCKCHIP=m -CONFIG_SND_SOC_ROCKCHIP_SPDIF=m -CONFIG_SND_SOC_ROCKCHIP_RT5645=m -CONFIG_SND_SOC_RK3399_GRU_SOUND=m -CONFIG_SND_SOC_SAMSUNG=y -CONFIG_SND_SOC_RCAR=m -CONFIG_SND_SOC_RZ=m -CONFIG_SND_SUN4I_I2S=m -CONFIG_SND_SUN4I_SPDIF=m -CONFIG_SND_SOC_TEGRA=m -CONFIG_SND_SOC_TEGRA210_AHUB=m -CONFIG_SND_SOC_TEGRA210_DMIC=m -CONFIG_SND_SOC_TEGRA210_I2S=m -CONFIG_SND_SOC_TEGRA186_DSPK=m -CONFIG_SND_SOC_TEGRA210_ADMAIF=m -CONFIG_SND_SOC_TEGRA210_MVC=m -CONFIG_SND_SOC_TEGRA210_SFC=m -CONFIG_SND_SOC_TEGRA210_AMX=m -CONFIG_SND_SOC_TEGRA210_ADX=m -CONFIG_SND_SOC_TEGRA210_MIXER=m -CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m -CONFIG_SND_SOC_AK4613=m -CONFIG_SND_SOC_ES7134=m -CONFIG_SND_SOC_ES7241=m -CONFIG_SND_SOC_GTM601=m -CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m -CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -CONFIG_SND_SOC_PCM3168A_I2C=m -CONFIG_SND_SOC_RT5659=m -CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -CONFIG_SND_SOC_SIMPLE_MUX=m -CONFIG_SND_SOC_TAS571X=m -CONFIG_SND_SOC_TLV320AIC32X4_I2C=m -CONFIG_SND_SOC_WCD934X=m -CONFIG_SND_SOC_WM8904=m -CONFIG_SND_SOC_WM8960=m -CONFIG_SND_SOC_WM8962=m -CONFIG_SND_SOC_WM8978=m -CONFIG_SND_SOC_WSA881X=m -CONFIG_SND_SOC_LPASS_WSA_MACRO=m -CONFIG_SND_SOC_LPASS_VA_MACRO=m -CONFIG_SND_SIMPLE_CARD=m -CONFIG_SND_AUDIO_GRAPH_CARD=m -CONFIG_HID_MULTITOUCH=m -CONFIG_I2C_HID_ACPI=m -CONFIG_I2C_HID_OF=m -CONFIG_I2C_HID=m -<<<<<<< -======= -CONFIG_USB=y ->>>>>>> -CONFIG_USB_CONN_GPIO=m -CONFIG_USB=y -CONFIG_USB_OTG=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PCI=m -CONFIG_USB_XHCI_PCI_RENESAS=m -CONFIG_USB_XHCI_HCD=m -CONFIG_USB_XHCI_TEGRA=y -CONFIG_USB_XHCI_PCI=m -CONFIG_USB_XHCI_PCI_RENESAS=m -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_EXYNOS=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_EXYNOS=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_RENESAS_USBHS_HCD=m -CONFIG_USB_RENESAS_USBHS=m -CONFIG_USB_ACM=m -CONFIG_USB_STORAGE=y -CONFIG_USB_MTU3=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SUNXI=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_ULPI=y -CONFIG_USB_DWC2=y -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_ISP1760=y -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_HSIC_USB3503=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_GADGET=y -CONFIG_USB_RENESAS_USBHS_UDC=m -CONFIG_USB_RENESAS_USB3=m -CONFIG_USB_TEGRA_XUDC=m -CONFIG_USB_CONFIGFS=m -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_TYPEC=y -CONFIG_TYPEC_TCPM=m -CONFIG_TYPEC_TCPCI=m -CONFIG_TYPEC_FUSB302=m -CONFIG_TYPEC_HD3SS3220=m -CONFIG_TYPEC_TPS6598X=m -CONFIG_TYPEC_QCOM_PMIC=m -CONFIG_MMC=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ACPI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MMC_SDHCI_ESDHC_IMX=y -CONFIG_MMC_SDHCI_TEGRA=y -CONFIG_MMC_SDHCI_F_SDH30=y -CONFIG_MMC_MESON_GX=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_MMC_SPI=y -CONFIG_MMC_SDHI=y -CONFIG_MMC_UNIPHIER=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_EXYNOS=y -CONFIG_MMC_DW_HI3798CV200=y -CONFIG_MMC_DW_K3=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SUNXI=y -CONFIG_MMC_BCM2835=y -CONFIG_MMC_MTK=y -CONFIG_MMC_SDHCI_XENON=y -CONFIG_MMC_SDHCI_AM654=y -CONFIG_MMC_OWL=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_LM3692X=m -CONFIG_LEDS_PCA9532=m -CONFIG_LEDS_CLASS_MULTICOLOR=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_QCOM_LPG=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_EDAC=y -CONFIG_EDAC_GHES=y -CONFIG_EDAC_LAYERSCAPE=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=m -CONFIG_RTC_DRV_HYM8563=m -CONFIG_RTC_DRV_MAX77686=y -CONFIG_RTC_DRV_RK808=m -CONFIG_RTC_DRV_PCF85063=m -CONFIG_RTC_DRV_PCF85363=m -CONFIG_RTC_DRV_M41T80=m -CONFIG_RTC_DRV_RX8581=m -CONFIG_RTC_DRV_RV3028=m -CONFIG_RTC_DRV_RV8803=m -CONFIG_RTC_DRV_S5M=y -CONFIG_RTC_DRV_DS3232=y -CONFIG_RTC_DRV_PCF2127=m -CONFIG_RTC_DRV_EFI=y -CONFIG_RTC_DRV_CROS_EC=y -CONFIG_RTC_DRV_FSL_FTM_ALARM=m -CONFIG_RTC_DRV_S3C=y -CONFIG_RTC_DRV_PL031=y -CONFIG_RTC_DRV_SUN6I=y -CONFIG_RTC_DRV_ARMADA38X=y -CONFIG_RTC_DRV_PM8XXX=m -CONFIG_RTC_DRV_TEGRA=y -CONFIG_RTC_DRV_SNVS=m -CONFIG_RTC_DRV_IMX_SC=m -CONFIG_RTC_DRV_XGENE=y -CONFIG_DMADEVICES=y -CONFIG_DMA_BCM2835=y -CONFIG_DMA_SUN6I=m -CONFIG_FSL_EDMA=y -CONFIG_IMX_SDMA=y -CONFIG_K3_DMA=y -CONFIG_MV_XOR=y -CONFIG_MV_XOR_V2=y -CONFIG_OWL_DMA=y -CONFIG_PL330_DMA=y -CONFIG_TEGRA20_APB_DMA=y -CONFIG_TEGRA210_ADMA=m -CONFIG_QCOM_BAM_DMA=y -CONFIG_QCOM_HIDMA_MGMT=y -CONFIG_QCOM_HIDMA=y -CONFIG_RCAR_DMAC=y -CONFIG_RENESAS_USB_DMAC=m -CONFIG_RZ_DMAC=y -CONFIG_TI_K3_UDMA=y -CONFIG_TI_K3_UDMA_GLUE_LAYER=y -CONFIG_VFIO=y -CONFIG_VFIO_PCI=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_MMIO=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -CONFIG_MFD_CROS_EC_DEV=y -CONFIG_STAGING=y -CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_HANTRO=m -CONFIG_VIDEO_IMX_MEDIA=m -CONFIG_CHROME_PLATFORMS=y -CONFIG_CROS_EC=y -CONFIG_CROS_EC_I2C=y -CONFIG_CROS_EC_SPI=y -CONFIG_CROS_EC_CHARDEV=m -CONFIG_COMMON_CLK_SCMI=y -CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMMON_CLK_CS2000_CP=y -CONFIG_COMMON_CLK_FSL_SAI=y -CONFIG_COMMON_CLK_S2MPS11=y -CONFIG_COMMON_CLK_PWM=y -CONFIG_COMMON_CLK_VC5=y -CONFIG_COMMON_CLK_ZYNQMP=y -CONFIG_COMMON_CLK_BD718XX=m -CONFIG_CLK_RASPBERRYPI=m -CONFIG_CLK_IMX8MM=y -CONFIG_CLK_IMX8MN=y -CONFIG_CLK_IMX8MP=y -CONFIG_CLK_IMX8MQ=y -CONFIG_CLK_IMX8QXP=y -CONFIG_CLK_IMX8ULP=y -CONFIG_TI_SCI_CLK=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_QCOM_A53PLL=y -CONFIG_QCOM_CLK_APCS_MSM8916=y -CONFIG_QCOM_CLK_APCC_MSM8996=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_QCOM_CLK_RPMH=y -CONFIG_IPQ_GCC_8074=y -CONFIG_IPQ_GCC_6018=y -CONFIG_MSM_GCC_8916=y -CONFIG_MSM_GCC_8994=y -CONFIG_MSM_MMCC_8996=y -CONFIG_MSM_GCC_8998=y -CONFIG_QCS_GCC_404=y -CONFIG_SC_GCC_7180=y -CONFIG_SC_GCC_7280=y -CONFIG_SDM_CAMCC_845=m -CONFIG_SDM_GCC_845=y -CONFIG_SDM_GPUCC_845=y -CONFIG_SDM_VIDEOCC_845=y -CONFIG_SDM_DISPCC_845=y -CONFIG_SM_GCC_8150=y -CONFIG_SM_GCC_8250=y -CONFIG_SM_GCC_8350=y -CONFIG_SM_GCC_8450=y -CONFIG_SM_GPUCC_8150=y -CONFIG_SM_GPUCC_8250=y -CONFIG_SM_DISPCC_8250=y -CONFIG_SM_VIDEOCC_8250=y -CONFIG_QCOM_HFPLL=y -CONFIG_CLK_GFM_LPASS_SM8250=m -CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y -CONFIG_CLK_GFM_LPASS_SM8250=y -CONFIG_HWSPINLOCK=y -CONFIG_SDM_GPUCC_845=y -CONFIG_SDM_DISPCC_845=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_ARM_MHU=y -CONFIG_IMX_MBOX=y -CONFIG_PLATFORM_MHU=y -CONFIG_BCM2835_MBOX=y -CONFIG_QCOM_APCS_IPC=y -CONFIG_QCOM_IPCC=y -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_TEGRA_IOMMU_SMMU=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_V3=y -CONFIG_MTK_IOMMU=y -CONFIG_QCOM_IOMMU=y -CONFIG_REMOTEPROC=y -CONFIG_QCOM_Q6V5_MSS=m -CONFIG_QCOM_Q6V5_PAS=m -CONFIG_QCOM_SYSMON=m -CONFIG_QCOM_WCNSS_PIL=m -CONFIG_RPMSG_CHAR=m -CONFIG_RPMSG_QCOM_GLINK_RPM=y -CONFIG_RPMSG_QCOM_GLINK_SMEM=m -CONFIG_RPMSG_QCOM_SMD=y -CONFIG_SOUNDWIRE=m -CONFIG_SOUNDWIRE_QCOM=m -CONFIG_OWL_PM_DOMAINS=y -CONFIG_RASPBERRYPI_POWER=y -CONFIG_FSL_DPAA=y -CONFIG_FSL_MC_DPIO=y -CONFIG_FSL_RCPM=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MAILBOX=y -<<<<<<< -======= -CONFIG_QCOM_COMMAND_DB=y ->>>>>>> -CONFIG_QCOM_AOSS_QMP=y -CONFIG_QCOM_COMMAND_DB=y -CONFIG_QCOM_GENI_SE=y -CONFIG_QCOM_RMTFS_MEM=m -CONFIG_QCOM_RPMH=y -CONFIG_QCOM_RPMHPD=y -CONFIG_QCOM_RPMPD=y -CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_QCOM_SMP2P=y -CONFIG_QCOM_SMSM=y -CONFIG_QCOM_SOCINFO=m -CONFIG_QCOM_WCNSS_CTRL=m -CONFIG_QCOM_STATS=m -CONFIG_QCOM_APR=m -CONFIG_ARCH_R8A774A1=y -CONFIG_ARCH_R8A774B1=y -CONFIG_ARCH_R8A774C0=y -CONFIG_ARCH_R8A774E1=y -CONFIG_ARCH_R8A77950=y -CONFIG_ARCH_R8A77951=y -CONFIG_ARCH_R8A77960=y -CONFIG_ARCH_R8A77961=y -CONFIG_ARCH_R8A77965=y -CONFIG_ARCH_R8A77970=y -CONFIG_ARCH_R8A77980=y -CONFIG_ARCH_R8A77990=y -CONFIG_ARCH_R8A77995=y -CONFIG_ARCH_R8A779A0=y -CONFIG_ARCH_R8A779F0=y -CONFIG_ARCH_R9A07G044=y -CONFIG_ROCKCHIP_PM_DOMAINS=y -CONFIG_ARCH_TEGRA_132_SOC=y -CONFIG_ARCH_TEGRA_210_SOC=y -CONFIG_ARCH_TEGRA_186_SOC=y -CONFIG_ARCH_TEGRA_194_SOC=y -CONFIG_ARCH_TEGRA_234_SOC=y -CONFIG_TI_SCI_PM_DOMAINS=y -CONFIG_ARM_IMX_BUS_DEVFREQ=m -CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m -CONFIG_EXTCON_PTN5150=m -CONFIG_EXTCON_USB_GPIO=y -CONFIG_EXTCON_USBC_CROS_EC=y -CONFIG_RENESAS_RPCIF=m -CONFIG_IIO=y -CONFIG_EXYNOS_ADC=y -CONFIG_MAX9611=m -CONFIG_QCOM_SPMI_VADC=m -CONFIG_QCOM_SPMI_ADC5=m -CONFIG_ROCKCHIP_SARADC=m -CONFIG_RZG2L_ADC=m -CONFIG_IIO_CROS_EC_SENSORS_CORE=m -CONFIG_IIO_CROS_EC_SENSORS=m -CONFIG_IIO_ST_LSM6DSX=m -CONFIG_IIO_CROS_EC_LIGHT_PROX=m -CONFIG_SENSORS_ISL29018=m -CONFIG_VCNL4000=m -CONFIG_IIO_ST_MAGN_3AXIS=m -CONFIG_IIO_CROS_EC_BARO=m -CONFIG_MPL3115=m -CONFIG_PWM=y -CONFIG_PWM_BCM2835=m -CONFIG_PWM_CROS_EC=m -CONFIG_PWM_IMX27=m -CONFIG_PWM_MESON=m -CONFIG_PWM_MTK_DISP=m -CONFIG_PWM_MEDIATEK=m -CONFIG_PWM_RCAR=m -CONFIG_PWM_RENESAS_TPU=m -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_SAMSUNG=y -CONFIG_PWM_SL28CPLD=m -CONFIG_PWM_SUN4I=m -CONFIG_PWM_TEGRA=m -CONFIG_PWM_VISCONTI=m -CONFIG_SL28CPLD_INTC=y -CONFIG_QCOM_PDC=y -CONFIG_RESET_IMX7=y -CONFIG_RESET_QCOM_AOSS=y -CONFIG_RESET_QCOM_PDC=m -CONFIG_RESET_RZG2L_USBPHY_CTRL=y -CONFIG_RESET_TI_SCI=y -CONFIG_PHY_XGENE=y -CONFIG_PHY_SUN4I_USB=y -CONFIG_PHY_MIXEL_MIPI_DPHY=m -CONFIG_PHY_HI6220_USB=y -CONFIG_PHY_HISTB_COMBPHY=y -CONFIG_PHY_HISI_INNO_USB2=y -CONFIG_PHY_MVEBU_CP110_COMPHY=y -CONFIG_PHY_MTK_TPHY=y -CONFIG_PHY_QCOM_QMP=y -CONFIG_PHY_QCOM_QMP_TYPEC=y -CONFIG_PHY_QCOM_QUSB2=m -CONFIG_PHY_QCOM_UFS=y -CONFIG_PHY_QCOM_USB_HS=y -CONFIG_PHY_QCOM_USB_HS_SNPS_28NM=y -CONFIG_PHY_QCOM_USB_SS=y -CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y -CONFIG_PHY_RCAR_GEN3_PCIE=y -CONFIG_PHY_RCAR_GEN3_USB2=y -CONFIG_PHY_RCAR_GEN3_USB3=m -CONFIG_PHY_ROCKCHIP_EMMC=y -CONFIG_PHY_ROCKCHIP_INNO_HDMI=m -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m -CONFIG_PHY_ROCKCHIP_PCIE=m -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_SAMSUNG_UFS=y -CONFIG_PHY_UNIPHIER_USB2=y -CONFIG_PHY_UNIPHIER_USB3=y -CONFIG_PHY_TEGRA_XUSB=y -CONFIG_ARM_SMMU_V3_PMU=m -CONFIG_FSL_IMX8_DDR_PMU=m -CONFIG_HISI_PMU=y -CONFIG_QCOM_L2_PMU=y -CONFIG_QCOM_L3_PMU=y -CONFIG_NVMEM_IMX_OCOTP=y -CONFIG_NVMEM_IMX_OCOTP_SCU=y -CONFIG_QCOM_QFPROM=y -CONFIG_MTK_EFUSE=y -CONFIG_ROCKCHIP_EFUSE=y -CONFIG_NVMEM_SUNXI_SID=y -CONFIG_UNIPHIER_EFUSE=y -CONFIG_MESON_EFUSE=m -CONFIG_NVMEM_RMEM=m -CONFIG_FPGA=y -CONFIG_FPGA_MGR_STRATIX10_SOC=m -CONFIG_FPGA_BRIDGE=m -CONFIG_ALTERA_FREEZE_BRIDGE=m -CONFIG_FPGA_REGION=m -CONFIG_OF_FPGA_REGION=m -CONFIG_TEE=y -CONFIG_OPTEE=y -CONFIG_SLIMBUS=m -CONFIG_SLIM_QCOM_CTRL=m -CONFIG_SLIM_QCOM_NGD_CTRL=m -CONFIG_MUX_MMIO=y -CONFIG_INTERCONNECT=y -CONFIG_INTERCONNECT_IMX=m -CONFIG_INTERCONNECT_IMX8MM=m -CONFIG_INTERCONNECT_IMX8MN=m -CONFIG_INTERCONNECT_IMX8MQ=m -CONFIG_INTERCONNECT_QCOM=y -CONFIG_INTERCONNECT_QCOM_MSM8916=m -CONFIG_INTERCONNECT_QCOM_MSM8974=m -<<<<<<< -======= -CONFIG_INTERCONNECT_QCOM_MSM8996=m ->>>>>>> -CONFIG_INTERCONNECT_QCOM_OSM_L3=m -CONFIG_INTERCONNECT_QCOM_QCS404=m -CONFIG_INTERCONNECT_QCOM_SC7180=m -CONFIG_INTERCONNECT_QCOM_SC7280=y -CONFIG_INTERCONNECT_QCOM_SDM845=y -CONFIG_INTERCONNECT_QCOM_QCS404=m -CONFIG_INTERCONNECT_QCOM_SC7180=m -CONFIG_INTERCONNECT_QCOM_SDM845=m -CONFIG_INTERCONNECT_QCOM_SM8150=m -CONFIG_INTERCONNECT_QCOM_SM8250=m -CONFIG_INTERCONNECT_QCOM_SM8350=m -CONFIG_INTERCONNECT_QCOM_SM8450=m -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_BTRFS_FS=m -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_FS_ENCRYPTION=y -CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y -CONFIG_FANOTIFY=y -CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_QUOTA=y -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=m -CONFIG_CUSE=m -CONFIG_OVERLAY_FS=m -CONFIG_VFAT_FS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_HUGETLBFS=y -CONFIG_CONFIGFS_FS=y -CONFIG_EFIVAR_FS=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_ROOT_NFS=y -CONFIG_9P_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_USER_API_HASH=y -CONFIG_CRYPTO_USER_API_SKCIPHER=y -CONFIG_CRYPTO_USER_API_RNG=m -CONFIG_CRYPTO_USER_API_AEAD=y -CONFIG_CRYPTO_DEV_SUN8I_CE=m -CONFIG_CRYPTO_DEV_FSL_CAAM=m -CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m -CONFIG_CRYPTO_DEV_QCE=y -CONFIG_CRYPTO_DEV_QCOM_RNG=m -CONFIG_CRYPTO_DEV_CCREE=m -CONFIG_CRYPTO_DEV_HISI_SEC2=m -CONFIG_CRYPTO_DEV_HISI_ZIP=m -CONFIG_CRYPTO_DEV_HISI_HPRE=m -CONFIG_CRYPTO_DEV_HISI_TRNG=m -CONFIG_DMA_CMA=y -CONFIG_CMA_SIZE_MBYTES=32 -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_INFO_REDUCED=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_FTRACE is not set -CONFIG_MEMTEST=y diff --git a/rr-cache/c59c8fc36c46da74994abae491591396cddb6dd0/preimage b/rr-cache/c59c8fc36c46da74994abae491591396cddb6dd0/preimage deleted file mode 100644 index a71335e..0000000 --- a/rr-cache/c59c8fc36c46da74994abae491591396cddb6dd0/preimage +++ /dev/null @@ -1,7562 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/******************************************************************************* - This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. - ST Ethernet IPs are built around a Synopsys IP Core. - - Copyright(C) 2007-2011 STMicroelectronics Ltd - - - Author: Giuseppe Cavallaro - - Documentation available at: - http://www.stlinux.com - Support available at: - https://bugzilla.stlinux.com/ -*******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_DEBUG_FS -#include -#include -#endif /* CONFIG_DEBUG_FS */ -#include -#include -#include -#include -#include -#include -#include "stmmac_ptp.h" -#include "stmmac.h" -#include "stmmac_xdp.h" -#include -#include -#include "dwmac1000.h" -#include "dwxgmac2.h" -#include "hwif.h" - -/* As long as the interface is active, we keep the timestamping counter enabled - * with fine resolution and binary rollover. This avoid non-monotonic behavior - * (clock jumps) when changing timestamping settings at runtime. - */ -#define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ - PTP_TCR_TSCTRLSSR) - -#define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) -#define TSO_MAX_BUFF_SIZE (SZ_16K - 1) - -/* Module parameters */ -#define TX_TIMEO 5000 -static int watchdog = TX_TIMEO; -module_param(watchdog, int, 0644); -MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); - -static int debug = -1; -module_param(debug, int, 0644); -MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); - -static int phyaddr = -1; -module_param(phyaddr, int, 0444); -MODULE_PARM_DESC(phyaddr, "Physical device address"); - -#define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4) -#define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4) - -<<<<<<< -#define STMMAC_XDP_PASS 0 -#define STMMAC_XDP_CONSUMED BIT(0) -======= -/* Limit to make sure XDP TX and slow path can coexist */ -#define STMMAC_XSK_TX_BUDGET_MAX 256 -#define STMMAC_TX_XSK_AVAIL 16 -#define STMMAC_RX_FILL_BATCH 16 - -#define STMMAC_XDP_PASS 0 -#define STMMAC_XDP_CONSUMED BIT(0) -#define STMMAC_XDP_TX BIT(1) -#define STMMAC_XDP_REDIRECT BIT(2) ->>>>>>> - -static int flow_ctrl = FLOW_AUTO; -module_param(flow_ctrl, int, 0644); -MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); - -static int pause = PAUSE_TIME; -module_param(pause, int, 0644); -MODULE_PARM_DESC(pause, "Flow Control Pause Time"); - -#define TC_DEFAULT 64 -static int tc = TC_DEFAULT; -module_param(tc, int, 0644); -MODULE_PARM_DESC(tc, "DMA threshold control value"); - -#define DEFAULT_BUFSIZE 1536 -static int buf_sz = DEFAULT_BUFSIZE; -module_param(buf_sz, int, 0644); -MODULE_PARM_DESC(buf_sz, "DMA buffer size"); - -#define STMMAC_RX_COPYBREAK 256 - -static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | - NETIF_MSG_LINK | NETIF_MSG_IFUP | - NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); - -#define STMMAC_DEFAULT_LPI_TIMER 1000 -static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; -module_param(eee_timer, int, 0644); -MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); -#define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) - -/* By default the driver will use the ring mode to manage tx and rx descriptors, - * but allow user to force to use the chain instead of the ring - */ -static unsigned int chain_mode; -module_param(chain_mode, int, 0444); -MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); - -static irqreturn_t stmmac_interrupt(int irq, void *dev_id); -/* For MSI interrupts handling */ -static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); -static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); -static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); -static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); -static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); -static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); - -#ifdef CONFIG_DEBUG_FS -static const struct net_device_ops stmmac_netdev_ops; -static void stmmac_init_fs(struct net_device *dev); -static void stmmac_exit_fs(struct net_device *dev); -#endif - -#define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) - -int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) -{ - int ret = 0; - - if (enabled) { - ret = clk_prepare_enable(priv->plat->stmmac_clk); - if (ret) - return ret; - ret = clk_prepare_enable(priv->plat->pclk); - if (ret) { - clk_disable_unprepare(priv->plat->stmmac_clk); - return ret; - } - if (priv->plat->clks_config) { - ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); - if (ret) { - clk_disable_unprepare(priv->plat->stmmac_clk); - clk_disable_unprepare(priv->plat->pclk); - return ret; - } - } - } else { - clk_disable_unprepare(priv->plat->stmmac_clk); - clk_disable_unprepare(priv->plat->pclk); - if (priv->plat->clks_config) - priv->plat->clks_config(priv->plat->bsp_priv, enabled); - } - - return ret; -} -EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); - -/** - * stmmac_verify_args - verify the driver parameters. - * Description: it checks the driver parameters and set a default in case of - * errors. - */ -static void stmmac_verify_args(void) -{ - if (unlikely(watchdog < 0)) - watchdog = TX_TIMEO; - if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) - buf_sz = DEFAULT_BUFSIZE; - if (unlikely(flow_ctrl > 1)) - flow_ctrl = FLOW_AUTO; - else if (likely(flow_ctrl < 0)) - flow_ctrl = FLOW_OFF; - if (unlikely((pause < 0) || (pause > 0xffff))) - pause = PAUSE_TIME; - if (eee_timer < 0) - eee_timer = STMMAC_DEFAULT_LPI_TIMER; -} - -static void __stmmac_disable_all_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_cnt = priv->plat->rx_queues_to_use; - u32 tx_queues_cnt = priv->plat->tx_queues_to_use; - u32 maxq = max(rx_queues_cnt, tx_queues_cnt); - u32 queue; - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - if (stmmac_xdp_is_enabled(priv) && - test_bit(queue, priv->af_xdp_zc_qps)) { - napi_disable(&ch->rxtx_napi); - continue; - } - - if (queue < rx_queues_cnt) - napi_disable(&ch->rx_napi); - if (queue < tx_queues_cnt) - napi_disable(&ch->tx_napi); - } -} - -/** - * stmmac_disable_all_queues - Disable all queues - * @priv: driver private structure - */ -static void stmmac_disable_all_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_cnt = priv->plat->rx_queues_to_use; - struct stmmac_rx_queue *rx_q; - u32 queue; - - /* synchronize_rcu() needed for pending XDP buffers to drain */ - for (queue = 0; queue < rx_queues_cnt; queue++) { - rx_q = &priv->rx_queue[queue]; - if (rx_q->xsk_pool) { - synchronize_rcu(); - break; - } - } - - __stmmac_disable_all_queues(priv); -} - -/** - * stmmac_enable_all_queues - Enable all queues - * @priv: driver private structure - */ -static void stmmac_enable_all_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_cnt = priv->plat->rx_queues_to_use; - u32 tx_queues_cnt = priv->plat->tx_queues_to_use; - u32 maxq = max(rx_queues_cnt, tx_queues_cnt); - u32 queue; - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - if (stmmac_xdp_is_enabled(priv) && - test_bit(queue, priv->af_xdp_zc_qps)) { - napi_enable(&ch->rxtx_napi); - continue; - } - - if (queue < rx_queues_cnt) - napi_enable(&ch->rx_napi); - if (queue < tx_queues_cnt) - napi_enable(&ch->tx_napi); - } -} - -static void stmmac_service_event_schedule(struct stmmac_priv *priv) -{ - if (!test_bit(STMMAC_DOWN, &priv->state) && - !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) - queue_work(priv->wq, &priv->service_task); -} - -static void stmmac_global_err(struct stmmac_priv *priv) -{ - netif_carrier_off(priv->dev); - set_bit(STMMAC_RESET_REQUESTED, &priv->state); - stmmac_service_event_schedule(priv); -} - -/** - * stmmac_clk_csr_set - dynamically set the MDC clock - * @priv: driver private structure - * Description: this is to dynamically set the MDC clock according to the csr - * clock input. - * Note: - * If a specific clk_csr value is passed from the platform - * this means that the CSR Clock Range selection cannot be - * changed at run-time and it is fixed (as reported in the driver - * documentation). Viceversa the driver will try to set the MDC - * clock dynamically according to the actual clock input. - */ -static void stmmac_clk_csr_set(struct stmmac_priv *priv) -{ - u32 clk_rate; - - clk_rate = clk_get_rate(priv->plat->stmmac_clk); - - /* Platform provided default clk_csr would be assumed valid - * for all other cases except for the below mentioned ones. - * For values higher than the IEEE 802.3 specified frequency - * we can not estimate the proper divider as it is not known - * the frequency of clk_csr_i. So we do not change the default - * divider. - */ - if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { - if (clk_rate < CSR_F_35M) - priv->clk_csr = STMMAC_CSR_20_35M; - else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) - priv->clk_csr = STMMAC_CSR_35_60M; - else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) - priv->clk_csr = STMMAC_CSR_60_100M; - else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) - priv->clk_csr = STMMAC_CSR_100_150M; - else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) - priv->clk_csr = STMMAC_CSR_150_250M; - else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) - priv->clk_csr = STMMAC_CSR_250_300M; - } - - if (priv->plat->has_sun8i) { - if (clk_rate > 160000000) - priv->clk_csr = 0x03; - else if (clk_rate > 80000000) - priv->clk_csr = 0x02; - else if (clk_rate > 40000000) - priv->clk_csr = 0x01; - else - priv->clk_csr = 0; - } - - if (priv->plat->has_xgmac) { - if (clk_rate > 400000000) - priv->clk_csr = 0x5; - else if (clk_rate > 350000000) - priv->clk_csr = 0x4; - else if (clk_rate > 300000000) - priv->clk_csr = 0x3; - else if (clk_rate > 250000000) - priv->clk_csr = 0x2; - else if (clk_rate > 150000000) - priv->clk_csr = 0x1; - else - priv->clk_csr = 0x0; - } -} - -static void print_pkt(unsigned char *buf, int len) -{ - pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); - print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); -} - -static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - u32 avail; - - if (tx_q->dirty_tx > tx_q->cur_tx) - avail = tx_q->dirty_tx - tx_q->cur_tx - 1; - else - avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; - - return avail; -} - -/** - * stmmac_rx_dirty - Get RX queue dirty - * @priv: driver private structure - * @queue: RX queue index - */ -static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - u32 dirty; - - if (rx_q->dirty_rx <= rx_q->cur_rx) - dirty = rx_q->cur_rx - rx_q->dirty_rx; - else - dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; - - return dirty; -} - -static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) -{ - int tx_lpi_timer; - - /* Clear/set the SW EEE timer flag based on LPI ET enablement */ - priv->eee_sw_timer_en = en ? 0 : 1; - tx_lpi_timer = en ? priv->tx_lpi_timer : 0; - stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); -} - -/** - * stmmac_enable_eee_mode - check and enter in LPI mode - * @priv: driver private structure - * Description: this function is to verify and enter in LPI mode in case of - * EEE. - */ -static void stmmac_enable_eee_mode(struct stmmac_priv *priv) -{ - u32 tx_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - /* check if all TX queues have the work finished */ - for (queue = 0; queue < tx_cnt; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - if (tx_q->dirty_tx != tx_q->cur_tx) - return; /* still unfinished work */ - } - - /* Check and enter in LPI mode */ - if (!priv->tx_path_in_lpi_mode) - stmmac_set_eee_mode(priv, priv->hw, - priv->plat->en_tx_lpi_clockgating); -} - -/** - * stmmac_disable_eee_mode - disable and exit from LPI mode - * @priv: driver private structure - * Description: this function is to exit and disable EEE in case of - * LPI state is true. This is called by the xmit. - */ -void stmmac_disable_eee_mode(struct stmmac_priv *priv) -{ - if (!priv->eee_sw_timer_en) { - stmmac_lpi_entry_timer_config(priv, 0); - return; - } - - stmmac_reset_eee_mode(priv, priv->hw); - del_timer_sync(&priv->eee_ctrl_timer); - priv->tx_path_in_lpi_mode = false; -} - -/** - * stmmac_eee_ctrl_timer - EEE TX SW timer. - * @t: timer_list struct containing private info - * Description: - * if there is no data transfer and if we are not in LPI state, - * then MAC Transmitter can be moved to LPI state. - */ -static void stmmac_eee_ctrl_timer(struct timer_list *t) -{ - struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); - - stmmac_enable_eee_mode(priv); - mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); -} - -/** - * stmmac_eee_init - init EEE - * @priv: driver private structure - * Description: - * if the GMAC supports the EEE (from the HW cap reg) and the phy device - * can also manage EEE, this function enable the LPI state and start related - * timer. - */ -bool stmmac_eee_init(struct stmmac_priv *priv) -{ - int eee_tw_timer = priv->eee_tw_timer; - - /* Using PCS we cannot dial with the phy registers at this stage - * so we do not support extra feature like EEE. - */ - if (priv->hw->pcs == STMMAC_PCS_TBI || - priv->hw->pcs == STMMAC_PCS_RTBI) - return false; - - /* Check if MAC core supports the EEE feature. */ - if (!priv->dma_cap.eee) - return false; - - mutex_lock(&priv->lock); - - /* Check if it needs to be deactivated */ - if (!priv->eee_active) { - if (priv->eee_enabled) { - netdev_dbg(priv->dev, "disable EEE\n"); - stmmac_lpi_entry_timer_config(priv, 0); - del_timer_sync(&priv->eee_ctrl_timer); - stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); - if (priv->hw->xpcs) - xpcs_config_eee(priv->hw->xpcs, - priv->plat->mult_fact_100ns, - false); - } - mutex_unlock(&priv->lock); - return false; - } - - if (priv->eee_active && !priv->eee_enabled) { - timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); - stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, - eee_tw_timer); - if (priv->hw->xpcs) - xpcs_config_eee(priv->hw->xpcs, - priv->plat->mult_fact_100ns, - true); - } - - if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { - del_timer_sync(&priv->eee_ctrl_timer); - priv->tx_path_in_lpi_mode = false; - stmmac_lpi_entry_timer_config(priv, 1); - } else { - stmmac_lpi_entry_timer_config(priv, 0); - mod_timer(&priv->eee_ctrl_timer, - STMMAC_LPI_T(priv->tx_lpi_timer)); - } - - mutex_unlock(&priv->lock); - netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); - return true; -} - -static inline u32 stmmac_cdc_adjust(struct stmmac_priv *priv) -{ - /* Correct the clk domain crossing(CDC) error */ - if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) - return (2 * NSEC_PER_SEC) / priv->plat->clk_ptp_rate; - return 0; -} - -/* stmmac_get_tx_hwtstamp - get HW TX timestamps - * @priv: driver private structure - * @p : descriptor pointer - * @skb : the socket buffer - * Description : - * This function will read timestamp from the descriptor & pass it to stack. - * and also perform some sanity checks. - */ -static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, - struct dma_desc *p, struct sk_buff *skb) -{ - struct skb_shared_hwtstamps shhwtstamp; - bool found = false; - u64 ns = 0; - - if (!priv->hwts_tx_en) - return; - - /* exit if skb doesn't support hw tstamp */ - if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) - return; - - /* check tx tstamp status */ - if (stmmac_get_tx_timestamp_status(priv, p)) { - stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); - found = true; - } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { - found = true; - } - - if (found) { - ns -= stmmac_cdc_adjust(priv); - - memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); - shhwtstamp.hwtstamp = ns_to_ktime(ns); - - netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); - /* pass tstamp to stack */ - skb_tstamp_tx(skb, &shhwtstamp); - } -} - -/* stmmac_get_rx_hwtstamp - get HW RX timestamps - * @priv: driver private structure - * @p : descriptor pointer - * @np : next descriptor pointer - * @skb : the socket buffer - * Description : - * This function will read received packet's timestamp from the descriptor - * and pass it to stack. It also perform some sanity checks. - */ -static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, - struct dma_desc *np, struct sk_buff *skb) -{ - struct skb_shared_hwtstamps *shhwtstamp = NULL; - struct dma_desc *desc = p; - u64 ns = 0; - - if (!priv->hwts_rx_en) - return; - /* For GMAC4, the valid timestamp is from CTX next desc. */ - if (priv->plat->has_gmac4 || priv->plat->has_xgmac) - desc = np; - - /* Check if timestamp is available */ - if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { - stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); - - ns -= stmmac_cdc_adjust(priv); - - netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); - shhwtstamp = skb_hwtstamps(skb); - memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); - shhwtstamp->hwtstamp = ns_to_ktime(ns); - } else { - netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); - } -} - -/** - * stmmac_hwtstamp_set - control hardware timestamping. - * @dev: device pointer. - * @ifr: An IOCTL specific structure, that can contain a pointer to - * a proprietary structure used to pass information to the driver. - * Description: - * This function configures the MAC to enable/disable both outgoing(TX) - * and incoming(RX) packets time stamping based on user input. - * Return Value: - * 0 on success and an appropriate -ve integer on failure. - */ -static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct hwtstamp_config config; - u32 ptp_v2 = 0; - u32 tstamp_all = 0; - u32 ptp_over_ipv4_udp = 0; - u32 ptp_over_ipv6_udp = 0; - u32 ptp_over_ethernet = 0; - u32 snap_type_sel = 0; - u32 ts_master_en = 0; - u32 ts_event_en = 0; - - if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { - netdev_alert(priv->dev, "No support for HW time stamping\n"); - priv->hwts_tx_en = 0; - priv->hwts_rx_en = 0; - - return -EOPNOTSUPP; - } - - if (copy_from_user(&config, ifr->ifr_data, - sizeof(config))) - return -EFAULT; - - netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", - __func__, config.flags, config.tx_type, config.rx_filter); - - /* reserved for future extensions */ - if (config.flags) - return -EINVAL; - - if (config.tx_type != HWTSTAMP_TX_OFF && - config.tx_type != HWTSTAMP_TX_ON) - return -ERANGE; - - if (priv->adv_ts) { - switch (config.rx_filter) { - case HWTSTAMP_FILTER_NONE: - /* time stamp no incoming packet at all */ - config.rx_filter = HWTSTAMP_FILTER_NONE; - break; - - case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: - /* PTP v1, UDP, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; - /* 'xmac' hardware can support Sync, Pdelay_Req and - * Pdelay_resp by setting bit14 and bits17/16 to 01 - * This leaves Delay_Req timestamps out. - * Enable all events *and* general purpose message - * timestamping - */ - snap_type_sel = PTP_TCR_SNAPTYPSEL_1; - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: - /* PTP v1, UDP, Sync packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; - /* take time stamp for SYNC messages only */ - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: - /* PTP v1, UDP, Delay_req packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; - /* take time stamp for Delay_Req messages only */ - ts_master_en = PTP_TCR_TSMSTRENA; - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: - /* PTP v2, UDP, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for all event messages */ - snap_type_sel = PTP_TCR_SNAPTYPSEL_1; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: - /* PTP v2, UDP, Sync packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for SYNC messages only */ - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: - /* PTP v2, UDP, Delay_req packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for Delay_Req messages only */ - ts_master_en = PTP_TCR_TSMSTRENA; - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_EVENT: - /* PTP v2/802.AS1 any layer, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; - ptp_v2 = PTP_TCR_TSVER2ENA; - snap_type_sel = PTP_TCR_SNAPTYPSEL_1; - if (priv->synopsys_id < DWMAC_CORE_4_10) - ts_event_en = PTP_TCR_TSEVNTENA; - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - ptp_over_ethernet = PTP_TCR_TSIPENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_SYNC: - /* PTP v2/802.AS1, any layer, Sync packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for SYNC messages only */ - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - ptp_over_ethernet = PTP_TCR_TSIPENA; - break; - - case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: - /* PTP v2/802.AS1, any layer, Delay_req packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; - ptp_v2 = PTP_TCR_TSVER2ENA; - /* take time stamp for Delay_Req messages only */ - ts_master_en = PTP_TCR_TSMSTRENA; - ts_event_en = PTP_TCR_TSEVNTENA; - - ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; - ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; - ptp_over_ethernet = PTP_TCR_TSIPENA; - break; - - case HWTSTAMP_FILTER_NTP_ALL: - case HWTSTAMP_FILTER_ALL: - /* time stamp any incoming packet */ - config.rx_filter = HWTSTAMP_FILTER_ALL; - tstamp_all = PTP_TCR_TSENALL; - break; - - default: - return -ERANGE; - } - } else { - switch (config.rx_filter) { - case HWTSTAMP_FILTER_NONE: - config.rx_filter = HWTSTAMP_FILTER_NONE; - break; - default: - /* PTP v1, UDP, any kind of event packet */ - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; - break; - } - } - priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); - priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; - - priv->systime_flags = STMMAC_HWTS_ACTIVE; - - if (priv->hwts_tx_en || priv->hwts_rx_en) { - priv->systime_flags |= tstamp_all | ptp_v2 | - ptp_over_ethernet | ptp_over_ipv6_udp | - ptp_over_ipv4_udp | ts_event_en | - ts_master_en | snap_type_sel; - } - - stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); - - memcpy(&priv->tstamp_config, &config, sizeof(config)); - - return copy_to_user(ifr->ifr_data, &config, - sizeof(config)) ? -EFAULT : 0; -} - -/** - * stmmac_hwtstamp_get - read hardware timestamping. - * @dev: device pointer. - * @ifr: An IOCTL specific structure, that can contain a pointer to - * a proprietary structure used to pass information to the driver. - * Description: - * This function obtain the current hardware timestamping settings - * as requested. - */ -static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct hwtstamp_config *config = &priv->tstamp_config; - - if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) - return -EOPNOTSUPP; - - return copy_to_user(ifr->ifr_data, config, - sizeof(*config)) ? -EFAULT : 0; -} - -/** - * stmmac_init_tstamp_counter - init hardware timestamping counter - * @priv: driver private structure - * @systime_flags: timestamping flags - * Description: - * Initialize hardware counter for packet timestamping. - * This is valid as long as the interface is open and not suspended. - * Will be rerun after resuming from suspend, case in which the timestamping - * flags updated by stmmac_hwtstamp_set() also need to be restored. - */ -int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) -{ - bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; - struct timespec64 now; - u32 sec_inc = 0; - u64 temp = 0; - int ret; - - if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) - return -EOPNOTSUPP; - - ret = clk_prepare_enable(priv->plat->clk_ptp_ref); - if (ret < 0) { - netdev_warn(priv->dev, - "failed to enable PTP reference clock: %pe\n", - ERR_PTR(ret)); - return ret; - } - - stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); - priv->systime_flags = systime_flags; - - /* program Sub Second Increment reg */ - stmmac_config_sub_second_increment(priv, priv->ptpaddr, - priv->plat->clk_ptp_rate, - xmac, &sec_inc); - temp = div_u64(1000000000ULL, sec_inc); - - /* Store sub second increment for later use */ - priv->sub_second_inc = sec_inc; - - /* calculate default added value: - * formula is : - * addend = (2^32)/freq_div_ratio; - * where, freq_div_ratio = 1e9ns/sec_inc - */ - temp = (u64)(temp << 32); - priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); - stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); - - /* initialize system time */ - ktime_get_real_ts64(&now); - - /* lower 32 bits of tv_sec are safe until y2106 */ - stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); - - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); - -/** - * stmmac_init_ptp - init PTP - * @priv: driver private structure - * Description: this is to verify if the HW supports the PTPv1 or PTPv2. - * This is done by looking at the HW cap. register. - * This function also registers the ptp driver. - */ -static int stmmac_init_ptp(struct stmmac_priv *priv) -{ - bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; - int ret; - - ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); - if (ret) - return ret; - - priv->adv_ts = 0; - /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ - if (xmac && priv->dma_cap.atime_stamp) - priv->adv_ts = 1; - /* Dwmac 3.x core with extend_desc can support adv_ts */ - else if (priv->extend_desc && priv->dma_cap.atime_stamp) - priv->adv_ts = 1; - - if (priv->dma_cap.time_stamp) - netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); - - if (priv->adv_ts) - netdev_info(priv->dev, - "IEEE 1588-2008 Advanced Timestamp supported\n"); - - priv->hwts_tx_en = 0; - priv->hwts_rx_en = 0; - - stmmac_ptp_register(priv); - - return 0; -} - -static void stmmac_release_ptp(struct stmmac_priv *priv) -{ - clk_disable_unprepare(priv->plat->clk_ptp_ref); - stmmac_ptp_unregister(priv); -} - -/** - * stmmac_mac_flow_ctrl - Configure flow control in all queues - * @priv: driver private structure - * @duplex: duplex passed to the next function - * Description: It is used for configuring the flow control in all queues - */ -static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) -{ - u32 tx_cnt = priv->plat->tx_queues_to_use; - - stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, - priv->pause, tx_cnt); -} - -static void stmmac_validate(struct phylink_config *config, - unsigned long *supported, - struct phylink_link_state *state) -{ - struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); - __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - int tx_cnt = priv->plat->tx_queues_to_use; - int max_speed = priv->plat->max_speed; - - phylink_set(mac_supported, 10baseT_Half); - phylink_set(mac_supported, 10baseT_Full); - phylink_set(mac_supported, 100baseT_Half); - phylink_set(mac_supported, 100baseT_Full); - phylink_set(mac_supported, 1000baseT_Half); - phylink_set(mac_supported, 1000baseT_Full); - phylink_set(mac_supported, 1000baseKX_Full); - - phylink_set(mac_supported, Autoneg); - phylink_set(mac_supported, Pause); - phylink_set(mac_supported, Asym_Pause); - phylink_set_port_modes(mac_supported); - - /* Cut down 1G if asked to */ - if ((max_speed > 0) && (max_speed < 1000)) { - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseX_Full); - } else if (priv->plat->has_gmac4) { - if (!max_speed || max_speed >= 2500) { - phylink_set(mac_supported, 2500baseT_Full); - phylink_set(mac_supported, 2500baseX_Full); - } - } else if (priv->plat->has_xgmac) { - if (!max_speed || (max_speed >= 2500)) { - phylink_set(mac_supported, 2500baseT_Full); - phylink_set(mac_supported, 2500baseX_Full); - } - if (!max_speed || (max_speed >= 5000)) { - phylink_set(mac_supported, 5000baseT_Full); - } - if (!max_speed || (max_speed >= 10000)) { - phylink_set(mac_supported, 10000baseSR_Full); - phylink_set(mac_supported, 10000baseLR_Full); - phylink_set(mac_supported, 10000baseER_Full); - phylink_set(mac_supported, 10000baseLRM_Full); - phylink_set(mac_supported, 10000baseT_Full); - phylink_set(mac_supported, 10000baseKX4_Full); - phylink_set(mac_supported, 10000baseKR_Full); - } - if (!max_speed || (max_speed >= 25000)) { - phylink_set(mac_supported, 25000baseCR_Full); - phylink_set(mac_supported, 25000baseKR_Full); - phylink_set(mac_supported, 25000baseSR_Full); - } - if (!max_speed || (max_speed >= 40000)) { - phylink_set(mac_supported, 40000baseKR4_Full); - phylink_set(mac_supported, 40000baseCR4_Full); - phylink_set(mac_supported, 40000baseSR4_Full); - phylink_set(mac_supported, 40000baseLR4_Full); - } - if (!max_speed || (max_speed >= 50000)) { - phylink_set(mac_supported, 50000baseCR2_Full); - phylink_set(mac_supported, 50000baseKR2_Full); - phylink_set(mac_supported, 50000baseSR2_Full); - phylink_set(mac_supported, 50000baseKR_Full); - phylink_set(mac_supported, 50000baseSR_Full); - phylink_set(mac_supported, 50000baseCR_Full); - phylink_set(mac_supported, 50000baseLR_ER_FR_Full); - phylink_set(mac_supported, 50000baseDR_Full); - } - if (!max_speed || (max_speed >= 100000)) { - phylink_set(mac_supported, 100000baseKR4_Full); - phylink_set(mac_supported, 100000baseSR4_Full); - phylink_set(mac_supported, 100000baseCR4_Full); - phylink_set(mac_supported, 100000baseLR4_ER4_Full); - phylink_set(mac_supported, 100000baseKR2_Full); - phylink_set(mac_supported, 100000baseSR2_Full); - phylink_set(mac_supported, 100000baseCR2_Full); - phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); - phylink_set(mac_supported, 100000baseDR2_Full); - } - } - - /* Half-Duplex can only work with single queue */ - if (tx_cnt > 1) { - phylink_set(mask, 10baseT_Half); - phylink_set(mask, 100baseT_Half); - phylink_set(mask, 1000baseT_Half); - } - - linkmode_and(supported, supported, mac_supported); - linkmode_andnot(supported, supported, mask); - - linkmode_and(state->advertising, state->advertising, mac_supported); - linkmode_andnot(state->advertising, state->advertising, mask); - - /* If PCS is supported, check which modes it supports. */ - if (priv->hw->xpcs) - xpcs_validate(priv->hw->xpcs, supported, state); -} - -static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, - const struct phylink_link_state *state) -{ - /* Nothing to do, xpcs_config() handles everything */ -} - -static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) -{ - struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; - enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; - enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; - bool *hs_enable = &fpe_cfg->hs_enable; - - if (is_up && *hs_enable) { - stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); - } else { - *lo_state = FPE_STATE_OFF; - *lp_state = FPE_STATE_OFF; - } -} - -static void stmmac_mac_link_down(struct phylink_config *config, - unsigned int mode, phy_interface_t interface) -{ - struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); - - stmmac_mac_set(priv, priv->ioaddr, false); - priv->eee_active = false; - priv->tx_lpi_enabled = false; - priv->eee_enabled = stmmac_eee_init(priv); - stmmac_set_eee_pls(priv, priv->hw, false); - - if (priv->dma_cap.fpesel) - stmmac_fpe_link_state_handle(priv, false); -} - -static void stmmac_mac_link_up(struct phylink_config *config, - struct phy_device *phy, - unsigned int mode, phy_interface_t interface, - int speed, int duplex, - bool tx_pause, bool rx_pause) -{ - struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); - u32 ctrl; - - ctrl = readl(priv->ioaddr + MAC_CTRL_REG); - ctrl &= ~priv->hw->link.speed_mask; - - if (interface == PHY_INTERFACE_MODE_USXGMII) { - switch (speed) { - case SPEED_10000: - ctrl |= priv->hw->link.xgmii.speed10000; - break; - case SPEED_5000: - ctrl |= priv->hw->link.xgmii.speed5000; - break; - case SPEED_2500: - ctrl |= priv->hw->link.xgmii.speed2500; - break; - default: - return; - } - } else if (interface == PHY_INTERFACE_MODE_XLGMII) { - switch (speed) { - case SPEED_100000: - ctrl |= priv->hw->link.xlgmii.speed100000; - break; - case SPEED_50000: - ctrl |= priv->hw->link.xlgmii.speed50000; - break; - case SPEED_40000: - ctrl |= priv->hw->link.xlgmii.speed40000; - break; - case SPEED_25000: - ctrl |= priv->hw->link.xlgmii.speed25000; - break; - case SPEED_10000: - ctrl |= priv->hw->link.xgmii.speed10000; - break; - case SPEED_2500: - ctrl |= priv->hw->link.speed2500; - break; - case SPEED_1000: - ctrl |= priv->hw->link.speed1000; - break; - default: - return; - } - } else { - switch (speed) { - case SPEED_2500: - ctrl |= priv->hw->link.speed2500; - break; - case SPEED_1000: - ctrl |= priv->hw->link.speed1000; - break; - case SPEED_100: - ctrl |= priv->hw->link.speed100; - break; - case SPEED_10: - ctrl |= priv->hw->link.speed10; - break; - default: - return; - } - } - - priv->speed = speed; - - if (priv->plat->fix_mac_speed) - priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); - - if (!duplex) - ctrl &= ~priv->hw->link.duplex; - else - ctrl |= priv->hw->link.duplex; - - /* Flow Control operation */ - if (tx_pause && rx_pause) - stmmac_mac_flow_ctrl(priv, duplex); - - writel(ctrl, priv->ioaddr + MAC_CTRL_REG); - - stmmac_mac_set(priv, priv->ioaddr, true); - if (phy && priv->dma_cap.eee) { - priv->eee_active = phy_init_eee(phy, 1) >= 0; - priv->eee_enabled = stmmac_eee_init(priv); - priv->tx_lpi_enabled = priv->eee_enabled; - stmmac_set_eee_pls(priv, priv->hw, true); - } - - if (priv->dma_cap.fpesel) - stmmac_fpe_link_state_handle(priv, true); -} - -static const struct phylink_mac_ops stmmac_phylink_mac_ops = { - .validate = stmmac_validate, - .mac_config = stmmac_mac_config, - .mac_link_down = stmmac_mac_link_down, - .mac_link_up = stmmac_mac_link_up, -}; - -/** - * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported - * @priv: driver private structure - * Description: this is to verify if the HW supports the PCS. - * Physical Coding Sublayer (PCS) interface that can be used when the MAC is - * configured for the TBI, RTBI, or SGMII PHY interface. - */ -static void stmmac_check_pcs_mode(struct stmmac_priv *priv) -{ - int interface = priv->plat->interface; - - if (priv->dma_cap.pcs) { - if ((interface == PHY_INTERFACE_MODE_RGMII) || - (interface == PHY_INTERFACE_MODE_RGMII_ID) || - (interface == PHY_INTERFACE_MODE_RGMII_RXID) || - (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { - netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); - priv->hw->pcs = STMMAC_PCS_RGMII; - } else if (interface == PHY_INTERFACE_MODE_SGMII) { - netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); - priv->hw->pcs = STMMAC_PCS_SGMII; - } - } -} - -/** - * stmmac_init_phy - PHY initialization - * @dev: net device structure - * Description: it initializes the driver's PHY state, and attaches the PHY - * to the mac driver. - * Return value: - * 0 on success - */ -static int stmmac_init_phy(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct device_node *node; - int ret; - - node = priv->plat->phylink_node; - - if (node) - ret = phylink_of_phy_connect(priv->phylink, node, 0); - - /* Some DT bindings do not set-up the PHY handle. Let's try to - * manually parse it - */ - if (!node || ret) { - int addr = priv->plat->phy_addr; - struct phy_device *phydev; - - phydev = mdiobus_get_phy(priv->mii, addr); - if (!phydev) { - netdev_err(priv->dev, "no phy at addr %d\n", addr); - return -ENODEV; - } - - ret = phylink_connect_phy(priv->phylink, phydev); - } - - if (!priv->plat->pmt) { - struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; - - phylink_ethtool_get_wol(priv->phylink, &wol); - device_set_wakeup_capable(priv->device, !!wol.supported); - } - - return ret; -} - -static int stmmac_phy_setup(struct stmmac_priv *priv) -{ - struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; - struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); - int mode = priv->plat->phy_interface; - struct phylink *phylink; - - priv->phylink_config.dev = &priv->dev->dev; - priv->phylink_config.type = PHYLINK_NETDEV; - priv->phylink_config.pcs_poll = true; - if (priv->plat->mdio_bus_data) - priv->phylink_config.ovr_an_inband = - mdio_bus_data->xpcs_an_inband; - - if (!fwnode) - fwnode = dev_fwnode(priv->device); - - phylink = phylink_create(&priv->phylink_config, fwnode, - mode, &stmmac_phylink_mac_ops); - if (IS_ERR(phylink)) - return PTR_ERR(phylink); - - if (priv->hw->xpcs) - phylink_set_pcs(phylink, &priv->hw->xpcs->pcs); - - priv->phylink = phylink; - return 0; -} - -static void stmmac_display_rx_rings(struct stmmac_priv *priv) -{ - u32 rx_cnt = priv->plat->rx_queues_to_use; - unsigned int desc_size; - void *head_rx; - u32 queue; - - /* Display RX rings */ - for (queue = 0; queue < rx_cnt; queue++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - pr_info("\tRX Queue %u rings\n", queue); - - if (priv->extend_desc) { - head_rx = (void *)rx_q->dma_erx; - desc_size = sizeof(struct dma_extended_desc); - } else { - head_rx = (void *)rx_q->dma_rx; - desc_size = sizeof(struct dma_desc); - } - - /* Display RX ring */ - stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true, - rx_q->dma_rx_phy, desc_size); - } -} - -static void stmmac_display_tx_rings(struct stmmac_priv *priv) -{ - u32 tx_cnt = priv->plat->tx_queues_to_use; - unsigned int desc_size; - void *head_tx; - u32 queue; - - /* Display TX rings */ - for (queue = 0; queue < tx_cnt; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - pr_info("\tTX Queue %d rings\n", queue); - - if (priv->extend_desc) { - head_tx = (void *)tx_q->dma_etx; - desc_size = sizeof(struct dma_extended_desc); - } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { - head_tx = (void *)tx_q->dma_entx; - desc_size = sizeof(struct dma_edesc); - } else { - head_tx = (void *)tx_q->dma_tx; - desc_size = sizeof(struct dma_desc); - } - - stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false, - tx_q->dma_tx_phy, desc_size); - } -} - -static void stmmac_display_rings(struct stmmac_priv *priv) -{ - /* Display RX ring */ - stmmac_display_rx_rings(priv); - - /* Display TX ring */ - stmmac_display_tx_rings(priv); -} - -static int stmmac_set_bfsize(int mtu, int bufsize) -{ - int ret = bufsize; - - if (mtu >= BUF_SIZE_8KiB) - ret = BUF_SIZE_16KiB; - else if (mtu >= BUF_SIZE_4KiB) - ret = BUF_SIZE_8KiB; - else if (mtu >= BUF_SIZE_2KiB) - ret = BUF_SIZE_4KiB; - else if (mtu > DEFAULT_BUFSIZE) - ret = BUF_SIZE_2KiB; - else - ret = DEFAULT_BUFSIZE; - - return ret; -} - -/** - * stmmac_clear_rx_descriptors - clear RX descriptors - * @priv: driver private structure - * @queue: RX queue index - * Description: this function is called to clear the RX descriptors - * in case of both basic and extended descriptors are used. - */ -static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - /* Clear the RX descriptors */ - for (i = 0; i < priv->dma_rx_size; i++) - if (priv->extend_desc) - stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, - priv->use_riwt, priv->mode, - (i == priv->dma_rx_size - 1), - priv->dma_buf_sz); - else - stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], - priv->use_riwt, priv->mode, - (i == priv->dma_rx_size - 1), - priv->dma_buf_sz); -} - -/** - * stmmac_clear_tx_descriptors - clear tx descriptors - * @priv: driver private structure - * @queue: TX queue index. - * Description: this function is called to clear the TX descriptors - * in case of both basic and extended descriptors are used. - */ -static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int i; - - /* Clear the TX descriptors */ - for (i = 0; i < priv->dma_tx_size; i++) { - int last = (i == (priv->dma_tx_size - 1)); - struct dma_desc *p; - - if (priv->extend_desc) - p = &tx_q->dma_etx[i].basic; - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &tx_q->dma_entx[i].basic; - else - p = &tx_q->dma_tx[i]; - - stmmac_init_tx_desc(priv, p, priv->mode, last); - } -} - -/** - * stmmac_clear_descriptors - clear descriptors - * @priv: driver private structure - * Description: this function is called to clear the TX and RX descriptors - * in case of both basic and extended descriptors are used. - */ -static void stmmac_clear_descriptors(struct stmmac_priv *priv) -{ - u32 rx_queue_cnt = priv->plat->rx_queues_to_use; - u32 tx_queue_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - /* Clear the RX descriptors */ - for (queue = 0; queue < rx_queue_cnt; queue++) - stmmac_clear_rx_descriptors(priv, queue); - - /* Clear the TX descriptors */ - for (queue = 0; queue < tx_queue_cnt; queue++) - stmmac_clear_tx_descriptors(priv, queue); -} - -/** - * stmmac_init_rx_buffers - init the RX descriptor buffer. - * @priv: driver private structure - * @p: descriptor pointer - * @i: descriptor index - * @flags: gfp flag - * @queue: RX queue index - * Description: this function is called to allocate a receive buffer, perform - * the DMA mapping and init the descriptor. - */ -static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, - int i, gfp_t flags, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; - -<<<<<<< - buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); - if (!buf->page) - return -ENOMEM; - buf->page_offset = stmmac_rx_offset(priv); -======= - if (!buf->page) { - buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); - if (!buf->page) - return -ENOMEM; - buf->page_offset = stmmac_rx_offset(priv); - } ->>>>>>> - - if (priv->sph && !buf->sec_page) { - buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); - if (!buf->sec_page) - return -ENOMEM; - - buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); - } else { - buf->sec_page = NULL; - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); - } - - buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; - - stmmac_set_desc_addr(priv, p, buf->addr); - if (priv->dma_buf_sz == BUF_SIZE_16KiB) - stmmac_init_desc3(priv, p); - - return 0; -} - -/** - * stmmac_free_rx_buffer - free RX dma buffers - * @priv: private structure - * @queue: RX queue index - * @i: buffer index. - */ -static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; - - if (buf->page) - page_pool_put_full_page(rx_q->page_pool, buf->page, false); - buf->page = NULL; - - if (buf->sec_page) - page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); - buf->sec_page = NULL; -} - -/** - * stmmac_free_tx_buffer - free RX dma buffers - * @priv: private structure - * @queue: RX queue index - * @i: buffer index. - */ -static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - if (tx_q->tx_skbuff_dma[i].buf && - tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { - if (tx_q->tx_skbuff_dma[i].map_as_page) - dma_unmap_page(priv->device, - tx_q->tx_skbuff_dma[i].buf, - tx_q->tx_skbuff_dma[i].len, - DMA_TO_DEVICE); - else - dma_unmap_single(priv->device, - tx_q->tx_skbuff_dma[i].buf, - tx_q->tx_skbuff_dma[i].len, - DMA_TO_DEVICE); - } - - if (tx_q->xdpf[i] && - (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || - tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { - xdp_return_frame(tx_q->xdpf[i]); - tx_q->xdpf[i] = NULL; - } - - if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) - tx_q->xsk_frames_done++; - - if (tx_q->tx_skbuff[i] && - tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { - dev_kfree_skb_any(tx_q->tx_skbuff[i]); - tx_q->tx_skbuff[i] = NULL; - } - - tx_q->tx_skbuff_dma[i].buf = 0; - tx_q->tx_skbuff_dma[i].map_as_page = false; -} - -/** - * dma_free_rx_skbufs - free RX dma buffers - * @priv: private structure - * @queue: RX queue index - */ -static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) -{ - int i; - - for (i = 0; i < priv->dma_rx_size; i++) - stmmac_free_rx_buffer(priv, queue, i); -} - -static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue, - gfp_t flags) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - for (i = 0; i < priv->dma_rx_size; i++) { - struct dma_desc *p; - int ret; - - if (priv->extend_desc) - p = &((rx_q->dma_erx + i)->basic); - else - p = rx_q->dma_rx + i; - - ret = stmmac_init_rx_buffers(priv, p, i, flags, - queue); - if (ret) - return ret; - - rx_q->buf_alloc_num++; - } - -<<<<<<< - for (queue = 0; queue < rx_count; queue++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - for (i = 0; i < priv->dma_rx_size; i++) { - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; - struct dma_desc *p; - - if (priv->extend_desc) - p = &((rx_q->dma_erx + i)->basic); - else - p = rx_q->dma_rx + i; - - if (!buf->page) { - buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); - if (!buf->page) - goto err_reinit_rx_buffers; - - buf->addr = page_pool_get_dma_addr(buf->page) + - buf->page_offset; - } - - if (priv->sph && !buf->sec_page) { - buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); - if (!buf->sec_page) - goto err_reinit_rx_buffers; - - buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); - } - - stmmac_set_desc_addr(priv, p, buf->addr); - if (priv->sph) - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); - else - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); - if (priv->dma_buf_sz == BUF_SIZE_16KiB) - stmmac_init_desc3(priv, p); - } - } - - return; - -err_reinit_rx_buffers: - do { - while (--i >= 0) - stmmac_free_rx_buffer(priv, queue, i); - - if (queue == 0) - break; - - i = priv->dma_rx_size; - } while (queue-- > 0); -======= - return 0; ->>>>>>> -} - -/** - * dma_free_rx_xskbufs - free RX dma buffers from XSK pool - * @priv: private structure - * @queue: RX queue index - */ -static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - for (i = 0; i < priv->dma_rx_size; i++) { - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; - - if (!buf->xdp) - continue; - - xsk_buff_free(buf->xdp); - buf->xdp = NULL; - } -} - -static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int i; - - for (i = 0; i < priv->dma_rx_size; i++) { - struct stmmac_rx_buffer *buf; - dma_addr_t dma_addr; - struct dma_desc *p; - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + i); - else - p = rx_q->dma_rx + i; - - buf = &rx_q->buf_pool[i]; - - buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); - if (!buf->xdp) - return -ENOMEM; - - dma_addr = xsk_buff_xdp_get_dma(buf->xdp); - stmmac_set_desc_addr(priv, p, dma_addr); - rx_q->buf_alloc_num++; - } - - return 0; -} - -static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) -{ - if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) - return NULL; - - return xsk_get_pool_from_qid(priv->dev, queue); -} - -/** - * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) - * @priv: driver private structure - * @queue: RX queue index - * @flags: gfp flag. - * Description: this function initializes the DMA RX descriptors - * and allocates the socket buffers. It supports the chained and ring - * modes. - */ -static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int ret; - - netif_dbg(priv, probe, priv->dev, - "(%s) dma_rx_phy=0x%08x\n", __func__, - (u32)rx_q->dma_rx_phy); - - stmmac_clear_rx_descriptors(priv, queue); - - xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); - - rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); - - if (rx_q->xsk_pool) { - WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, - MEM_TYPE_XSK_BUFF_POOL, - NULL)); - netdev_info(priv->dev, - "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", - rx_q->queue_index); - xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); - } else { - WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, - MEM_TYPE_PAGE_POOL, - rx_q->page_pool)); - netdev_info(priv->dev, - "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", - rx_q->queue_index); - } - - if (rx_q->xsk_pool) { - /* RX XDP ZC buffer pool may not be populated, e.g. - * xdpsock TX-only. - */ - stmmac_alloc_rx_buffers_zc(priv, queue); - } else { - ret = stmmac_alloc_rx_buffers(priv, queue, flags); - if (ret < 0) - return -ENOMEM; - } - - rx_q->cur_rx = 0; - rx_q->dirty_rx = 0; - - /* Setup the chained descriptor addresses */ - if (priv->mode == STMMAC_CHAIN_MODE) { - if (priv->extend_desc) - stmmac_mode_init(priv, rx_q->dma_erx, - rx_q->dma_rx_phy, - priv->dma_rx_size, 1); - else - stmmac_mode_init(priv, rx_q->dma_rx, - rx_q->dma_rx_phy, - priv->dma_rx_size, 0); - } - - return 0; -} - -static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 rx_count = priv->plat->rx_queues_to_use; - u32 queue; - int ret; - - /* RX INITIALIZATION */ - netif_dbg(priv, probe, priv->dev, - "SKB addresses:\nskb\t\tskb data\tdma data\n"); - - for (queue = 0; queue < rx_count; queue++) { - ret = __init_dma_rx_desc_rings(priv, queue, flags); - if (ret) - goto err_init_rx_buffers; - } - - return 0; - -err_init_rx_buffers: - while (queue >= 0) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - if (rx_q->xsk_pool) - dma_free_rx_xskbufs(priv, queue); - else - dma_free_rx_skbufs(priv, queue); - - rx_q->buf_alloc_num = 0; - rx_q->xsk_pool = NULL; - - if (queue == 0) - break; - - queue--; - } - - return ret; -} - -/** - * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) - * @priv: driver private structure - * @queue : TX queue index - * Description: this function initializes the DMA TX descriptors - * and allocates the socket buffers. It supports the chained and ring - * modes. - */ -static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int i; - - netif_dbg(priv, probe, priv->dev, - "(%s) dma_tx_phy=0x%08x\n", __func__, - (u32)tx_q->dma_tx_phy); - - /* Setup the chained descriptor addresses */ - if (priv->mode == STMMAC_CHAIN_MODE) { - if (priv->extend_desc) - stmmac_mode_init(priv, tx_q->dma_etx, - tx_q->dma_tx_phy, - priv->dma_tx_size, 1); - else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) - stmmac_mode_init(priv, tx_q->dma_tx, - tx_q->dma_tx_phy, - priv->dma_tx_size, 0); - } - - tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); - - for (i = 0; i < priv->dma_tx_size; i++) { - struct dma_desc *p; - - if (priv->extend_desc) - p = &((tx_q->dma_etx + i)->basic); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &((tx_q->dma_entx + i)->basic); - else - p = tx_q->dma_tx + i; - - stmmac_clear_desc(priv, p); - - tx_q->tx_skbuff_dma[i].buf = 0; - tx_q->tx_skbuff_dma[i].map_as_page = false; - tx_q->tx_skbuff_dma[i].len = 0; - tx_q->tx_skbuff_dma[i].last_segment = false; - tx_q->tx_skbuff[i] = NULL; - } - - tx_q->dirty_tx = 0; - tx_q->cur_tx = 0; - tx_q->mss = 0; - - netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); - - return 0; -} - -static int init_dma_tx_desc_rings(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 tx_queue_cnt; - u32 queue; - - tx_queue_cnt = priv->plat->tx_queues_to_use; - - for (queue = 0; queue < tx_queue_cnt; queue++) - __init_dma_tx_desc_rings(priv, queue); - - return 0; -} - -/** - * init_dma_desc_rings - init the RX/TX descriptor rings - * @dev: net device structure - * @flags: gfp flag. - * Description: this function initializes the DMA RX/TX descriptors - * and allocates the socket buffers. It supports the chained and ring - * modes. - */ -static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret; - - ret = init_dma_rx_desc_rings(dev, flags); - if (ret) - return ret; - - ret = init_dma_tx_desc_rings(dev); - - stmmac_clear_descriptors(priv); - - if (netif_msg_hw(priv)) - stmmac_display_rings(priv); - - return ret; -} - -/** - * dma_free_tx_skbufs - free TX dma buffers - * @priv: private structure - * @queue: TX queue index - */ -static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int i; - - tx_q->xsk_frames_done = 0; - - for (i = 0; i < priv->dma_tx_size; i++) - stmmac_free_tx_buffer(priv, queue, i); - - if (tx_q->xsk_pool && tx_q->xsk_frames_done) { - xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); - tx_q->xsk_frames_done = 0; - tx_q->xsk_pool = NULL; - } -} - -/** - * stmmac_free_tx_skbufs - free TX skb buffers - * @priv: private structure - */ -static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) -{ - u32 tx_queue_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - for (queue = 0; queue < tx_queue_cnt; queue++) - dma_free_tx_skbufs(priv, queue); -} - -/** - * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) - * @priv: private structure - * @queue: RX queue index - */ -static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - /* Release the DMA RX socket buffers */ - if (rx_q->xsk_pool) - dma_free_rx_xskbufs(priv, queue); - else - dma_free_rx_skbufs(priv, queue); - - rx_q->buf_alloc_num = 0; - rx_q->xsk_pool = NULL; - - /* Free DMA regions of consistent memory previously allocated */ - if (!priv->extend_desc) - dma_free_coherent(priv->device, priv->dma_rx_size * - sizeof(struct dma_desc), - rx_q->dma_rx, rx_q->dma_rx_phy); - else - dma_free_coherent(priv->device, priv->dma_rx_size * - sizeof(struct dma_extended_desc), - rx_q->dma_erx, rx_q->dma_rx_phy); - - if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) - xdp_rxq_info_unreg(&rx_q->xdp_rxq); - - kfree(rx_q->buf_pool); - if (rx_q->page_pool) - page_pool_destroy(rx_q->page_pool); -} - -static void free_dma_rx_desc_resources(struct stmmac_priv *priv) -{ - u32 rx_count = priv->plat->rx_queues_to_use; - u32 queue; - - /* Free RX queue resources */ - for (queue = 0; queue < rx_count; queue++) - __free_dma_rx_desc_resources(priv, queue); -} - -/** - * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) - * @priv: private structure - * @queue: TX queue index - */ -static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - size_t size; - void *addr; - - /* Release the DMA TX socket buffers */ - dma_free_tx_skbufs(priv, queue); - - if (priv->extend_desc) { - size = sizeof(struct dma_extended_desc); - addr = tx_q->dma_etx; - } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { - size = sizeof(struct dma_edesc); - addr = tx_q->dma_entx; - } else { - size = sizeof(struct dma_desc); - addr = tx_q->dma_tx; - } - - size *= priv->dma_tx_size; - - dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); - - kfree(tx_q->tx_skbuff_dma); - kfree(tx_q->tx_skbuff); -} - -static void free_dma_tx_desc_resources(struct stmmac_priv *priv) -{ - u32 tx_count = priv->plat->tx_queues_to_use; - u32 queue; - - /* Free TX queue resources */ - for (queue = 0; queue < tx_count; queue++) - __free_dma_tx_desc_resources(priv, queue); -} - -/** - * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). - * @priv: private structure - * @queue: RX queue index - * Description: according to which descriptor can be used (extend or basic) - * this function allocates the resources for TX and RX paths. In case of - * reception, for example, it pre-allocated the RX socket buffer in order to - * allow zero-copy mechanism. - */ -static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - bool xdp_prog = stmmac_xdp_is_enabled(priv); - struct page_pool_params pp_params = { 0 }; - unsigned int num_pages; - unsigned int napi_id; - int ret; - - rx_q->queue_index = queue; - rx_q->priv_data = priv; - - pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; - pp_params.pool_size = priv->dma_rx_size; - num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); - pp_params.order = ilog2(num_pages); - pp_params.nid = dev_to_node(priv->device); - pp_params.dev = priv->device; - pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; - pp_params.offset = stmmac_rx_offset(priv); - pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); - - rx_q->page_pool = page_pool_create(&pp_params); - if (IS_ERR(rx_q->page_pool)) { - ret = PTR_ERR(rx_q->page_pool); - rx_q->page_pool = NULL; - return ret; - } - - rx_q->buf_pool = kcalloc(priv->dma_rx_size, - sizeof(*rx_q->buf_pool), - GFP_KERNEL); - if (!rx_q->buf_pool) - return -ENOMEM; - - if (priv->extend_desc) { - rx_q->dma_erx = dma_alloc_coherent(priv->device, - priv->dma_rx_size * - sizeof(struct dma_extended_desc), - &rx_q->dma_rx_phy, - GFP_KERNEL); - if (!rx_q->dma_erx) - return -ENOMEM; - - } else { - rx_q->dma_rx = dma_alloc_coherent(priv->device, - priv->dma_rx_size * - sizeof(struct dma_desc), - &rx_q->dma_rx_phy, - GFP_KERNEL); - if (!rx_q->dma_rx) - return -ENOMEM; - } - - if (stmmac_xdp_is_enabled(priv) && - test_bit(queue, priv->af_xdp_zc_qps)) - napi_id = ch->rxtx_napi.napi_id; - else - napi_id = ch->rx_napi.napi_id; - - ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, - rx_q->queue_index, - napi_id); - if (ret) { - netdev_err(priv->dev, "Failed to register xdp rxq info\n"); - return -EINVAL; - } - - return 0; -} - -static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) -{ - bool xdp_prog = stmmac_xdp_is_enabled(priv); - u32 rx_count = priv->plat->rx_queues_to_use; - u32 queue; - int ret; - - /* RX queues buffers and DMA */ - for (queue = 0; queue < rx_count; queue++) { -<<<<<<< - ret = __alloc_dma_rx_desc_resources(priv, queue); - if (ret) -======= - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct page_pool_params pp_params = { 0 }; - unsigned int num_pages; - - rx_q->queue_index = queue; - rx_q->priv_data = priv; - - pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; - pp_params.pool_size = priv->dma_rx_size; - num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); - pp_params.order = ilog2(num_pages); - pp_params.nid = dev_to_node(priv->device); - pp_params.dev = priv->device; - pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; - pp_params.offset = stmmac_rx_offset(priv); - pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); - - rx_q->page_pool = page_pool_create(&pp_params); - if (IS_ERR(rx_q->page_pool)) { - ret = PTR_ERR(rx_q->page_pool); - rx_q->page_pool = NULL; ->>>>>>> - goto err_dma; - } - - return 0; - -err_dma: - free_dma_rx_desc_resources(priv); - - return ret; -} - -/** - * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). - * @priv: private structure - * @queue: TX queue index - * Description: according to which descriptor can be used (extend or basic) - * this function allocates the resources for TX and RX paths. In case of - * reception, for example, it pre-allocated the RX socket buffer in order to - * allow zero-copy mechanism. - */ -static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - size_t size; - void *addr; - - tx_q->queue_index = queue; - tx_q->priv_data = priv; - - tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size, - sizeof(*tx_q->tx_skbuff_dma), - GFP_KERNEL); - if (!tx_q->tx_skbuff_dma) - return -ENOMEM; - - tx_q->tx_skbuff = kcalloc(priv->dma_tx_size, - sizeof(struct sk_buff *), - GFP_KERNEL); - if (!tx_q->tx_skbuff) - return -ENOMEM; - - if (priv->extend_desc) - size = sizeof(struct dma_extended_desc); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - size = sizeof(struct dma_edesc); - else - size = sizeof(struct dma_desc); - - size *= priv->dma_tx_size; - - addr = dma_alloc_coherent(priv->device, size, - &tx_q->dma_tx_phy, GFP_KERNEL); - if (!addr) - return -ENOMEM; - - if (priv->extend_desc) - tx_q->dma_etx = addr; - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - tx_q->dma_entx = addr; - else - tx_q->dma_tx = addr; - - return 0; -} - -static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) -{ - u32 tx_count = priv->plat->tx_queues_to_use; - u32 queue; - int ret; - - /* TX queues buffers and DMA */ - for (queue = 0; queue < tx_count; queue++) { - ret = __alloc_dma_tx_desc_resources(priv, queue); - if (ret) - goto err_dma; - } - - return 0; - -err_dma: - free_dma_tx_desc_resources(priv); - return ret; -} - -/** - * alloc_dma_desc_resources - alloc TX/RX resources. - * @priv: private structure - * Description: according to which descriptor can be used (extend or basic) - * this function allocates the resources for TX and RX paths. In case of - * reception, for example, it pre-allocated the RX socket buffer in order to - * allow zero-copy mechanism. - */ -static int alloc_dma_desc_resources(struct stmmac_priv *priv) -{ - /* RX Allocation */ - int ret = alloc_dma_rx_desc_resources(priv); - - if (ret) - return ret; - - ret = alloc_dma_tx_desc_resources(priv); - - return ret; -} - -/** - * free_dma_desc_resources - free dma desc resources - * @priv: private structure - */ -static void free_dma_desc_resources(struct stmmac_priv *priv) -{ - /* Release the DMA TX socket buffers */ - free_dma_tx_desc_resources(priv); - - /* Release the DMA RX socket buffers later - * to ensure all pending XDP_TX buffers are returned. - */ - free_dma_rx_desc_resources(priv); -} - -/** - * stmmac_mac_enable_rx_queues - Enable MAC rx queues - * @priv: driver private structure - * Description: It is used for enabling the rx queues in the MAC - */ -static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - int queue; - u8 mode; - - for (queue = 0; queue < rx_queues_count; queue++) { - mode = priv->plat->rx_queues_cfg[queue].mode_to_use; - stmmac_rx_queue_enable(priv, priv->hw, mode, queue); - } -} - -/** - * stmmac_start_rx_dma - start RX DMA channel - * @priv: driver private structure - * @chan: RX channel index - * Description: - * This starts a RX DMA channel - */ -static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); - stmmac_start_rx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_start_tx_dma - start TX DMA channel - * @priv: driver private structure - * @chan: TX channel index - * Description: - * This starts a TX DMA channel - */ -static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); - stmmac_start_tx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_stop_rx_dma - stop RX DMA channel - * @priv: driver private structure - * @chan: RX channel index - * Description: - * This stops a RX DMA channel - */ -static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); - stmmac_stop_rx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_stop_tx_dma - stop TX DMA channel - * @priv: driver private structure - * @chan: TX channel index - * Description: - * This stops a TX DMA channel - */ -static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) -{ - netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); - stmmac_stop_tx(priv, priv->ioaddr, chan); -} - -/** - * stmmac_start_all_dma - start all RX and TX DMA channels - * @priv: driver private structure - * Description: - * This starts all the RX and TX DMA channels - */ -static void stmmac_start_all_dma(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 chan = 0; - - for (chan = 0; chan < rx_channels_count; chan++) - stmmac_start_rx_dma(priv, chan); - - for (chan = 0; chan < tx_channels_count; chan++) - stmmac_start_tx_dma(priv, chan); -} - -/** - * stmmac_stop_all_dma - stop all RX and TX DMA channels - * @priv: driver private structure - * Description: - * This stops the RX and TX DMA channels - */ -static void stmmac_stop_all_dma(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 chan = 0; - - for (chan = 0; chan < rx_channels_count; chan++) - stmmac_stop_rx_dma(priv, chan); - - for (chan = 0; chan < tx_channels_count; chan++) - stmmac_stop_tx_dma(priv, chan); -} - -/** - * stmmac_dma_operation_mode - HW DMA operation mode - * @priv: driver private structure - * Description: it is used for configuring the DMA operation mode register in - * order to program the tx/rx DMA thresholds or Store-And-Forward mode. - */ -static void stmmac_dma_operation_mode(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - int rxfifosz = priv->plat->rx_fifo_size; - int txfifosz = priv->plat->tx_fifo_size; - u32 txmode = 0; - u32 rxmode = 0; - u32 chan = 0; - u8 qmode = 0; - - if (rxfifosz == 0) - rxfifosz = priv->dma_cap.rx_fifo_size; - if (txfifosz == 0) - txfifosz = priv->dma_cap.tx_fifo_size; - - /* Adjust for real per queue fifo size */ - rxfifosz /= rx_channels_count; - txfifosz /= tx_channels_count; - - if (priv->plat->force_thresh_dma_mode) { - txmode = tc; - rxmode = tc; - } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { - /* - * In case of GMAC, SF mode can be enabled - * to perform the TX COE in HW. This depends on: - * 1) TX COE if actually supported - * 2) There is no bugged Jumbo frame support - * that needs to not insert csum in the TDES. - */ - txmode = SF_DMA_MODE; - rxmode = SF_DMA_MODE; - priv->xstats.threshold = SF_DMA_MODE; - } else { - txmode = tc; - rxmode = SF_DMA_MODE; - } - - /* configure all channels */ - for (chan = 0; chan < rx_channels_count; chan++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; - u32 buf_size; - - qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; - - stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, - rxfifosz, qmode); - - if (rx_q->xsk_pool) { - buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); - stmmac_set_dma_bfsize(priv, priv->ioaddr, - buf_size, - chan); - } else { - stmmac_set_dma_bfsize(priv, priv->ioaddr, - priv->dma_buf_sz, - chan); - } - } - - for (chan = 0; chan < tx_channels_count; chan++) { - qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; - - stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, - txfifosz, qmode); - } -} - -static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) -{ - struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - struct xsk_buff_pool *pool = tx_q->xsk_pool; - unsigned int entry = tx_q->cur_tx; - struct dma_desc *tx_desc = NULL; - struct xdp_desc xdp_desc; - bool work_done = true; - - /* Avoids TX time-out as we are sharing with slow path */ - nq->trans_start = jiffies; - - budget = min(budget, stmmac_tx_avail(priv, queue)); - - while (budget-- > 0) { - dma_addr_t dma_addr; - bool set_ic; - - /* We are sharing with slow path and stop XSK TX desc submission when - * available TX ring is less than threshold. - */ - if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || - !netif_carrier_ok(priv->dev)) { - work_done = false; - break; - } - - if (!xsk_tx_peek_desc(pool, &xdp_desc)) - break; - - if (likely(priv->extend_desc)) - tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - tx_desc = &tx_q->dma_entx[entry].basic; - else - tx_desc = tx_q->dma_tx + entry; - - dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); - xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); - - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; - - /* To return XDP buffer to XSK pool, we simple call - * xsk_tx_completed(), so we don't need to fill up - * 'buf' and 'xdpf'. - */ - tx_q->tx_skbuff_dma[entry].buf = 0; - tx_q->xdpf[entry] = NULL; - - tx_q->tx_skbuff_dma[entry].map_as_page = false; - tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; - tx_q->tx_skbuff_dma[entry].last_segment = true; - tx_q->tx_skbuff_dma[entry].is_jumbo = false; - - stmmac_set_desc_addr(priv, tx_desc, dma_addr); - - tx_q->tx_count_frames++; - - if (!priv->tx_coal_frames[queue]) - set_ic = false; - else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, tx_desc); - priv->xstats.tx_set_ic_bit++; - } - - stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, - true, priv->mode, true, true, - xdp_desc.len); - - stmmac_enable_dma_transmission(priv, priv->ioaddr); - - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); - entry = tx_q->cur_tx; - } - - if (tx_desc) { - stmmac_flush_tx_descriptors(priv, queue); - xsk_tx_release(pool); - } - - /* Return true if all of the 3 conditions are met - * a) TX Budget is still available - * b) work_done = true when XSK TX desc peek is empty (no more - * pending XSK TX for transmission) - */ - return !!budget && work_done; -} - -/** - * stmmac_tx_clean - to manage the transmission completion - * @priv: driver private structure - * @budget: napi budget limiting this functions packet handling - * @queue: TX queue index - * Description: it reclaims the transmit resources after transmission completes. - */ -static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - unsigned int bytes_compl = 0, pkts_compl = 0; - unsigned int entry, xmits = 0, count = 0; - - __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); - - priv->xstats.tx_clean++; - - tx_q->xsk_frames_done = 0; - - entry = tx_q->dirty_tx; - - /* Try to clean all TX complete frame in 1 shot */ - while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) { - struct xdp_frame *xdpf; - struct sk_buff *skb; - struct dma_desc *p; - int status; - - if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || - tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { - xdpf = tx_q->xdpf[entry]; - skb = NULL; - } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { - xdpf = NULL; - skb = tx_q->tx_skbuff[entry]; - } else { - xdpf = NULL; - skb = NULL; - } - - if (priv->extend_desc) - p = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &tx_q->dma_entx[entry].basic; - else - p = tx_q->dma_tx + entry; - - status = stmmac_tx_status(priv, &priv->dev->stats, - &priv->xstats, p, priv->ioaddr); - /* Check if the descriptor is owned by the DMA */ - if (unlikely(status & tx_dma_own)) - break; - - count++; - - /* Make sure descriptor fields are read after reading - * the own bit. - */ - dma_rmb(); - - /* Just consider the last segment and ...*/ - if (likely(!(status & tx_not_ls))) { - /* ... verify the status error condition */ - if (unlikely(status & tx_err)) { - priv->dev->stats.tx_errors++; - } else { - priv->dev->stats.tx_packets++; - priv->xstats.tx_pkt_n++; - priv->xstats.txq_stats[queue].tx_pkt_n++; - } - if (skb) - stmmac_get_tx_hwtstamp(priv, p, skb); - } - - if (likely(tx_q->tx_skbuff_dma[entry].buf && - tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { - if (tx_q->tx_skbuff_dma[entry].map_as_page) - dma_unmap_page(priv->device, - tx_q->tx_skbuff_dma[entry].buf, - tx_q->tx_skbuff_dma[entry].len, - DMA_TO_DEVICE); - else - dma_unmap_single(priv->device, - tx_q->tx_skbuff_dma[entry].buf, - tx_q->tx_skbuff_dma[entry].len, - DMA_TO_DEVICE); - tx_q->tx_skbuff_dma[entry].buf = 0; - tx_q->tx_skbuff_dma[entry].len = 0; - tx_q->tx_skbuff_dma[entry].map_as_page = false; - } - - stmmac_clean_desc3(priv, tx_q, p); - - tx_q->tx_skbuff_dma[entry].last_segment = false; - tx_q->tx_skbuff_dma[entry].is_jumbo = false; - - if (xdpf && - tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { - xdp_return_frame_rx_napi(xdpf); - tx_q->xdpf[entry] = NULL; - } - - if (xdpf && - tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { - xdp_return_frame(xdpf); - tx_q->xdpf[entry] = NULL; - } - - if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) - tx_q->xsk_frames_done++; - - if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { - if (likely(skb)) { - pkts_compl++; - bytes_compl += skb->len; - dev_consume_skb_any(skb); - tx_q->tx_skbuff[entry] = NULL; - } - } - - stmmac_release_tx_desc(priv, p, priv->mode); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - } - tx_q->dirty_tx = entry; - - netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), - pkts_compl, bytes_compl); - - if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, - queue))) && - stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { - - netif_dbg(priv, tx_done, priv->dev, - "%s: restart transmit\n", __func__); - netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); - } - - if (tx_q->xsk_pool) { - bool work_done; - - if (tx_q->xsk_frames_done) - xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); - - if (xsk_uses_need_wakeup(tx_q->xsk_pool)) - xsk_set_tx_need_wakeup(tx_q->xsk_pool); - - /* For XSK TX, we try to send as many as possible. - * If XSK work done (XSK TX desc empty and budget still - * available), return "budget - 1" to reenable TX IRQ. - * Else, return "budget" to make NAPI continue polling. - */ - work_done = stmmac_xdp_xmit_zc(priv, queue, - STMMAC_XSK_TX_BUDGET_MAX); - if (work_done) - xmits = budget - 1; - else - xmits = budget; - } - - if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && - priv->eee_sw_timer_en) { - stmmac_enable_eee_mode(priv); - mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); - } - - /* We still have pending packets, let's call for a new scheduling */ - if (tx_q->dirty_tx != tx_q->cur_tx) - hrtimer_start(&tx_q->txtimer, - STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), - HRTIMER_MODE_REL); - - __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); - - /* Combine decisions from TX clean and XSK TX */ - return max(count, xmits); -} - -/** - * stmmac_tx_err - to manage the tx error - * @priv: driver private structure - * @chan: channel index - * Description: it cleans the descriptors and restarts the transmission - * in case of transmission errors. - */ -static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); - - stmmac_stop_tx_dma(priv, chan); - dma_free_tx_skbufs(priv, chan); - stmmac_clear_tx_descriptors(priv, chan); - tx_q->dirty_tx = 0; - tx_q->cur_tx = 0; - tx_q->mss = 0; - netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); - stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - tx_q->dma_tx_phy, chan); - stmmac_start_tx_dma(priv, chan); - - priv->dev->stats.tx_errors++; - netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); -} - -/** - * stmmac_set_dma_operation_mode - Set DMA operation mode by channel - * @priv: driver private structure - * @txmode: TX operating mode - * @rxmode: RX operating mode - * @chan: channel index - * Description: it is used for configuring of the DMA operation mode in - * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward - * mode. - */ -static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, - u32 rxmode, u32 chan) -{ - u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; - u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - int rxfifosz = priv->plat->rx_fifo_size; - int txfifosz = priv->plat->tx_fifo_size; - - if (rxfifosz == 0) - rxfifosz = priv->dma_cap.rx_fifo_size; - if (txfifosz == 0) - txfifosz = priv->dma_cap.tx_fifo_size; - - /* Adjust for real per queue fifo size */ - rxfifosz /= rx_channels_count; - txfifosz /= tx_channels_count; - - stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); - stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); -} - -static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) -{ - int ret; - - ret = stmmac_safety_feat_irq_status(priv, priv->dev, - priv->ioaddr, priv->dma_cap.asp, &priv->sstats); - if (ret && (ret != -EINVAL)) { - stmmac_global_err(priv); - return true; - } - - return false; -} - -static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) -{ - int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, - &priv->xstats, chan, dir); - struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - struct stmmac_channel *ch = &priv->channel[chan]; - struct napi_struct *rx_napi; - struct napi_struct *tx_napi; - unsigned long flags; - - rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; - tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; - - if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { - if (napi_schedule_prep(rx_napi)) { - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); - __napi_schedule(rx_napi); - } - } - - if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { - if (napi_schedule_prep(tx_napi)) { - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - __napi_schedule(tx_napi); - } - } - - return status; -} - -/** - * stmmac_dma_interrupt - DMA ISR - * @priv: driver private structure - * Description: this is the DMA ISR. It is called by the main ISR. - * It calls the dwmac dma routine and schedule poll method in case of some - * work can be done. - */ -static void stmmac_dma_interrupt(struct stmmac_priv *priv) -{ - u32 tx_channel_count = priv->plat->tx_queues_to_use; - u32 rx_channel_count = priv->plat->rx_queues_to_use; - u32 channels_to_check = tx_channel_count > rx_channel_count ? - tx_channel_count : rx_channel_count; - u32 chan; - int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; - - /* Make sure we never check beyond our status buffer. */ - if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) - channels_to_check = ARRAY_SIZE(status); - - for (chan = 0; chan < channels_to_check; chan++) - status[chan] = stmmac_napi_check(priv, chan, - DMA_DIR_RXTX); - - for (chan = 0; chan < tx_channel_count; chan++) { - if (unlikely(status[chan] & tx_hard_error_bump_tc)) { - /* Try to bump up the dma threshold on this failure */ - if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && - (tc <= 256)) { - tc += 64; - if (priv->plat->force_thresh_dma_mode) - stmmac_set_dma_operation_mode(priv, - tc, - tc, - chan); - else - stmmac_set_dma_operation_mode(priv, - tc, - SF_DMA_MODE, - chan); - priv->xstats.threshold = tc; - } - } else if (unlikely(status[chan] == tx_hard_error)) { - stmmac_tx_err(priv, chan); - } - } -} - -/** - * stmmac_mmc_setup: setup the Mac Management Counters (MMC) - * @priv: driver private structure - * Description: this masks the MMC irq, in fact, the counters are managed in SW. - */ -static void stmmac_mmc_setup(struct stmmac_priv *priv) -{ - unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | - MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; - - stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); - - if (priv->dma_cap.rmon) { - stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); - memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); - } else - netdev_info(priv->dev, "No MAC Management Counters available\n"); -} - -/** - * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. - * @priv: driver private structure - * Description: - * new GMAC chip generations have a new register to indicate the - * presence of the optional feature/functions. - * This can be also used to override the value passed through the - * platform and necessary for old MAC10/100 and GMAC chips. - */ -static int stmmac_get_hw_features(struct stmmac_priv *priv) -{ - return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; -} - -/** - * stmmac_check_ether_addr - check if the MAC addr is valid - * @priv: driver private structure - * Description: - * it is to verify if the MAC address is valid, in case of failures it - * generates a random MAC address - */ -static void stmmac_check_ether_addr(struct stmmac_priv *priv) -{ - u8 addr[ETH_ALEN]; - - if (!is_valid_ether_addr(priv->dev->dev_addr)) { - stmmac_get_umac_addr(priv, priv->hw, addr, 0); - if (is_valid_ether_addr(addr)) - eth_hw_addr_set(priv->dev, addr); - else - eth_hw_addr_random(priv->dev); - dev_info(priv->device, "device MAC address %pM\n", - priv->dev->dev_addr); - } -} - -/** - * stmmac_init_dma_engine - DMA init. - * @priv: driver private structure - * Description: - * It inits the DMA invoking the specific MAC/GMAC callback. - * Some DMA parameters can be passed from the platform; - * in case of these are not passed a default is kept for the MAC or GMAC. - */ -static int stmmac_init_dma_engine(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); - struct stmmac_rx_queue *rx_q; - struct stmmac_tx_queue *tx_q; - u32 chan = 0; - int atds = 0; - int ret = 0; - - if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { - dev_err(priv->device, "Invalid DMA configuration\n"); - return -EINVAL; - } - - if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) - atds = 1; - - ret = stmmac_reset(priv, priv->ioaddr); - if (ret) { - dev_err(priv->device, "Failed to reset the dma\n"); - return ret; - } - - /* DMA Configuration */ - stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); - - if (priv->plat->axi) - stmmac_axi(priv, priv->ioaddr, priv->plat->axi); - - /* DMA CSR Channel configuration */ - for (chan = 0; chan < dma_csr_ch; chan++) - stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); - - /* DMA RX Channel Configuration */ - for (chan = 0; chan < rx_channels_count; chan++) { - rx_q = &priv->rx_queue[chan]; - - stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - rx_q->dma_rx_phy, chan); - - rx_q->rx_tail_addr = rx_q->dma_rx_phy + - (rx_q->buf_alloc_num * - sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, - rx_q->rx_tail_addr, chan); - } - - /* DMA TX Channel Configuration */ - for (chan = 0; chan < tx_channels_count; chan++) { - tx_q = &priv->tx_queue[chan]; - - stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - tx_q->dma_tx_phy, chan); - - tx_q->tx_tail_addr = tx_q->dma_tx_phy; - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, - tx_q->tx_tail_addr, chan); - } - - return ret; -} - -static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - hrtimer_start(&tx_q->txtimer, - STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), - HRTIMER_MODE_REL); -} - -/** - * stmmac_tx_timer - mitigation sw timer for tx. - * @t: data pointer - * Description: - * This is the timer handler to directly invoke the stmmac_tx_clean. - */ -static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) -{ - struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); - struct stmmac_priv *priv = tx_q->priv_data; - struct stmmac_channel *ch; - struct napi_struct *napi; - - ch = &priv->channel[tx_q->queue_index]; - napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; - - if (likely(napi_schedule_prep(napi))) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - __napi_schedule(napi); - } - - return HRTIMER_NORESTART; -} - -/** - * stmmac_init_coalesce - init mitigation options. - * @priv: driver private structure - * Description: - * This inits the coalesce parameters: i.e. timer rate, - * timer handler and default threshold used for enabling the - * interrupt on completion bit. - */ -static void stmmac_init_coalesce(struct stmmac_priv *priv) -{ - u32 tx_channel_count = priv->plat->tx_queues_to_use; - u32 rx_channel_count = priv->plat->rx_queues_to_use; - u32 chan; - - for (chan = 0; chan < tx_channel_count; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - - priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; - priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; - - hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - tx_q->txtimer.function = stmmac_tx_timer; - } - - for (chan = 0; chan < rx_channel_count; chan++) - priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; -} - -static void stmmac_set_rings_length(struct stmmac_priv *priv) -{ - u32 rx_channels_count = priv->plat->rx_queues_to_use; - u32 tx_channels_count = priv->plat->tx_queues_to_use; - u32 chan; - - /* set TX ring length */ - for (chan = 0; chan < tx_channels_count; chan++) - stmmac_set_tx_ring_len(priv, priv->ioaddr, - (priv->dma_tx_size - 1), chan); - - /* set RX ring length */ - for (chan = 0; chan < rx_channels_count; chan++) - stmmac_set_rx_ring_len(priv, priv->ioaddr, - (priv->dma_rx_size - 1), chan); -} - -/** - * stmmac_set_tx_queue_weight - Set TX queue weight - * @priv: driver private structure - * Description: It is used for setting TX queues weight - */ -static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) -{ - u32 tx_queues_count = priv->plat->tx_queues_to_use; - u32 weight; - u32 queue; - - for (queue = 0; queue < tx_queues_count; queue++) { - weight = priv->plat->tx_queues_cfg[queue].weight; - stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); - } -} - -/** - * stmmac_configure_cbs - Configure CBS in TX queue - * @priv: driver private structure - * Description: It is used for configuring CBS in AVB TX queues - */ -static void stmmac_configure_cbs(struct stmmac_priv *priv) -{ - u32 tx_queues_count = priv->plat->tx_queues_to_use; - u32 mode_to_use; - u32 queue; - - /* queue 0 is reserved for legacy traffic */ - for (queue = 1; queue < tx_queues_count; queue++) { - mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; - if (mode_to_use == MTL_QUEUE_DCB) - continue; - - stmmac_config_cbs(priv, priv->hw, - priv->plat->tx_queues_cfg[queue].send_slope, - priv->plat->tx_queues_cfg[queue].idle_slope, - priv->plat->tx_queues_cfg[queue].high_credit, - priv->plat->tx_queues_cfg[queue].low_credit, - queue); - } -} - -/** - * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel - * @priv: driver private structure - * Description: It is used for mapping RX queues to RX dma channels - */ -static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 queue; - u32 chan; - - for (queue = 0; queue < rx_queues_count; queue++) { - chan = priv->plat->rx_queues_cfg[queue].chan; - stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); - } -} - -/** - * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority - * @priv: driver private structure - * Description: It is used for configuring the RX Queue Priority - */ -static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 queue; - u32 prio; - - for (queue = 0; queue < rx_queues_count; queue++) { - if (!priv->plat->rx_queues_cfg[queue].use_prio) - continue; - - prio = priv->plat->rx_queues_cfg[queue].prio; - stmmac_rx_queue_prio(priv, priv->hw, prio, queue); - } -} - -/** - * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority - * @priv: driver private structure - * Description: It is used for configuring the TX Queue Priority - */ -static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) -{ - u32 tx_queues_count = priv->plat->tx_queues_to_use; - u32 queue; - u32 prio; - - for (queue = 0; queue < tx_queues_count; queue++) { - if (!priv->plat->tx_queues_cfg[queue].use_prio) - continue; - - prio = priv->plat->tx_queues_cfg[queue].prio; - stmmac_tx_queue_prio(priv, priv->hw, prio, queue); - } -} - -/** - * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing - * @priv: driver private structure - * Description: It is used for configuring the RX queue routing - */ -static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 queue; - u8 packet; - - for (queue = 0; queue < rx_queues_count; queue++) { - /* no specific packet type routing specified for the queue */ - if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) - continue; - - packet = priv->plat->rx_queues_cfg[queue].pkt_route; - stmmac_rx_queue_routing(priv, priv->hw, packet, queue); - } -} - -static void stmmac_mac_config_rss(struct stmmac_priv *priv) -{ - if (!priv->dma_cap.rssen || !priv->plat->rss_en) { - priv->rss.enable = false; - return; - } - - if (priv->dev->features & NETIF_F_RXHASH) - priv->rss.enable = true; - else - priv->rss.enable = false; - - stmmac_rss_configure(priv, priv->hw, &priv->rss, - priv->plat->rx_queues_to_use); -} - -/** - * stmmac_mtl_configuration - Configure MTL - * @priv: driver private structure - * Description: It is used for configurring MTL - */ -static void stmmac_mtl_configuration(struct stmmac_priv *priv) -{ - u32 rx_queues_count = priv->plat->rx_queues_to_use; - u32 tx_queues_count = priv->plat->tx_queues_to_use; - - if (tx_queues_count > 1) - stmmac_set_tx_queue_weight(priv); - - /* Configure MTL RX algorithms */ - if (rx_queues_count > 1) - stmmac_prog_mtl_rx_algorithms(priv, priv->hw, - priv->plat->rx_sched_algorithm); - - /* Configure MTL TX algorithms */ - if (tx_queues_count > 1) - stmmac_prog_mtl_tx_algorithms(priv, priv->hw, - priv->plat->tx_sched_algorithm); - - /* Configure CBS in AVB TX queues */ - if (tx_queues_count > 1) - stmmac_configure_cbs(priv); - - /* Map RX MTL to DMA channels */ - stmmac_rx_queue_dma_chan_map(priv); - - /* Enable MAC RX Queues */ - stmmac_mac_enable_rx_queues(priv); - - /* Set RX priorities */ - if (rx_queues_count > 1) - stmmac_mac_config_rx_queues_prio(priv); - - /* Set TX priorities */ - if (tx_queues_count > 1) - stmmac_mac_config_tx_queues_prio(priv); - - /* Set RX routing */ - if (rx_queues_count > 1) - stmmac_mac_config_rx_queues_routing(priv); - - /* Receive Side Scaling */ - if (rx_queues_count > 1) - stmmac_mac_config_rss(priv); -} - -static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) -{ - if (priv->dma_cap.asp) { - netdev_info(priv->dev, "Enabling Safety Features\n"); - stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, - priv->plat->safety_feat_cfg); - } else { - netdev_info(priv->dev, "No Safety Features support found\n"); - } -} - -static int stmmac_fpe_start_wq(struct stmmac_priv *priv) -{ - char *name; - - clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); - clear_bit(__FPE_REMOVING, &priv->fpe_task_state); - - name = priv->wq_name; - sprintf(name, "%s-fpe", priv->dev->name); - - priv->fpe_wq = create_singlethread_workqueue(name); - if (!priv->fpe_wq) { - netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); - - return -ENOMEM; - } - netdev_info(priv->dev, "FPE workqueue start"); - - return 0; -} - -/** - * stmmac_hw_setup - setup mac in a usable state. - * @dev : pointer to the device structure. - * @init_ptp: initialize PTP if set - * Description: - * this is the main function to setup the HW in a usable state because the - * dma engine is reset, the core registers are configured (e.g. AXI, - * Checksum features, timers). The DMA is ready to start receiving and - * transmitting. - * Return value: - * 0 on success and an appropriate (-)ve integer as defined in errno.h - * file on failure. - */ -static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 rx_cnt = priv->plat->rx_queues_to_use; - u32 tx_cnt = priv->plat->tx_queues_to_use; - bool sph_en; - u32 chan; - int ret; - - /* DMA initialization and SW reset */ - ret = stmmac_init_dma_engine(priv); - if (ret < 0) { - netdev_err(priv->dev, "%s: DMA engine initialization failed\n", - __func__); - return ret; - } - - /* Copy the MAC addr into the HW */ - stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); - - /* PS and related bits will be programmed according to the speed */ - if (priv->hw->pcs) { - int speed = priv->plat->mac_port_sel_speed; - - if ((speed == SPEED_10) || (speed == SPEED_100) || - (speed == SPEED_1000)) { - priv->hw->ps = speed; - } else { - dev_warn(priv->device, "invalid port speed\n"); - priv->hw->ps = 0; - } - } - - /* Initialize the MAC Core */ - stmmac_core_init(priv, priv->hw, dev); - - /* Initialize MTL*/ - stmmac_mtl_configuration(priv); - - /* Initialize Safety Features */ - stmmac_safety_feat_configuration(priv); - - ret = stmmac_rx_ipc(priv, priv->hw); - if (!ret) { - netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); - priv->plat->rx_coe = STMMAC_RX_COE_NONE; - priv->hw->rx_csum = 0; - } - - /* Enable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, true); - - /* Set the HW DMA mode and the COE */ - stmmac_dma_operation_mode(priv); - - stmmac_mmc_setup(priv); - - if (init_ptp) { - ret = stmmac_init_ptp(priv); - if (ret == -EOPNOTSUPP) - netdev_warn(priv->dev, "PTP not supported by HW\n"); - else if (ret) - netdev_warn(priv->dev, "PTP init failed\n"); - } - - priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; - - /* Convert the timer from msec to usec */ - if (!priv->tx_lpi_timer) - priv->tx_lpi_timer = eee_timer * 1000; - - if (priv->use_riwt) { - u32 queue; - - for (queue = 0; queue < rx_cnt; queue++) { - if (!priv->rx_riwt[queue]) - priv->rx_riwt[queue] = DEF_DMA_RIWT; - - stmmac_rx_watchdog(priv, priv->ioaddr, - priv->rx_riwt[queue], queue); - } - } - - if (priv->hw->pcs) - stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); - - /* set TX and RX rings length */ - stmmac_set_rings_length(priv); - - /* Enable TSO */ - if (priv->tso) { - for (chan = 0; chan < tx_cnt; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - - /* TSO and TBS cannot co-exist */ - if (tx_q->tbs & STMMAC_TBS_AVAIL) - continue; - - stmmac_enable_tso(priv, priv->ioaddr, 1, chan); - } - } - - /* Enable Split Header */ - sph_en = (priv->hw->rx_csum > 0) && priv->sph; - for (chan = 0; chan < rx_cnt; chan++) - stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); - - - /* VLAN Tag Insertion */ - if (priv->dma_cap.vlins) - stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); - - /* TBS */ - for (chan = 0; chan < tx_cnt; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - int enable = tx_q->tbs & STMMAC_TBS_AVAIL; - - stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); - } - - /* Configure real RX and TX queues */ - netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); - netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); - - /* Start the ball rolling... */ - stmmac_start_all_dma(priv); - - if (priv->dma_cap.fpesel) { - stmmac_fpe_start_wq(priv); - - if (priv->plat->fpe_cfg->enable) - stmmac_fpe_handshake(priv, true); - } - - return 0; -} - -static void stmmac_hw_teardown(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - clk_disable_unprepare(priv->plat->clk_ptp_ref); -} - -static void stmmac_free_irq(struct net_device *dev, - enum request_irq_err irq_err, int irq_idx) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int j; - - switch (irq_err) { - case REQ_IRQ_ERR_ALL: - irq_idx = priv->plat->tx_queues_to_use; - fallthrough; - case REQ_IRQ_ERR_TX: - for (j = irq_idx - 1; j >= 0; j--) { - if (priv->tx_irq[j] > 0) { - irq_set_affinity_hint(priv->tx_irq[j], NULL); - free_irq(priv->tx_irq[j], &priv->tx_queue[j]); - } - } - irq_idx = priv->plat->rx_queues_to_use; - fallthrough; - case REQ_IRQ_ERR_RX: - for (j = irq_idx - 1; j >= 0; j--) { - if (priv->rx_irq[j] > 0) { - irq_set_affinity_hint(priv->rx_irq[j], NULL); - free_irq(priv->rx_irq[j], &priv->rx_queue[j]); - } - } - - if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) - free_irq(priv->sfty_ue_irq, dev); - fallthrough; - case REQ_IRQ_ERR_SFTY_UE: - if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) - free_irq(priv->sfty_ce_irq, dev); - fallthrough; - case REQ_IRQ_ERR_SFTY_CE: - if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) - free_irq(priv->lpi_irq, dev); - fallthrough; - case REQ_IRQ_ERR_LPI: - if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) - free_irq(priv->wol_irq, dev); - fallthrough; - case REQ_IRQ_ERR_WOL: - free_irq(dev->irq, dev); - fallthrough; - case REQ_IRQ_ERR_MAC: - case REQ_IRQ_ERR_NO: - /* If MAC IRQ request error, no more IRQ to free */ - break; - } -} - -static int stmmac_request_irq_multi_msi(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - enum request_irq_err irq_err; - cpumask_t cpu_mask; - int irq_idx = 0; - char *int_name; - int ret; - int i; - - /* For common interrupt */ - int_name = priv->int_name_mac; - sprintf(int_name, "%s:%s", dev->name, "mac"); - ret = request_irq(dev->irq, stmmac_mac_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc mac MSI %d (error: %d)\n", - __func__, dev->irq, ret); - irq_err = REQ_IRQ_ERR_MAC; - goto irq_error; - } - - /* Request the Wake IRQ in case of another line - * is used for WoL - */ - if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { - int_name = priv->int_name_wol; - sprintf(int_name, "%s:%s", dev->name, "wol"); - ret = request_irq(priv->wol_irq, - stmmac_mac_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc wol MSI %d (error: %d)\n", - __func__, priv->wol_irq, ret); - irq_err = REQ_IRQ_ERR_WOL; - goto irq_error; - } - } - - /* Request the LPI IRQ in case of another line - * is used for LPI - */ - if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { - int_name = priv->int_name_lpi; - sprintf(int_name, "%s:%s", dev->name, "lpi"); - ret = request_irq(priv->lpi_irq, - stmmac_mac_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc lpi MSI %d (error: %d)\n", - __func__, priv->lpi_irq, ret); - irq_err = REQ_IRQ_ERR_LPI; - goto irq_error; - } - } - - /* Request the Safety Feature Correctible Error line in - * case of another line is used - */ - if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { - int_name = priv->int_name_sfty_ce; - sprintf(int_name, "%s:%s", dev->name, "safety-ce"); - ret = request_irq(priv->sfty_ce_irq, - stmmac_safety_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc sfty ce MSI %d (error: %d)\n", - __func__, priv->sfty_ce_irq, ret); - irq_err = REQ_IRQ_ERR_SFTY_CE; - goto irq_error; - } - } - - /* Request the Safety Feature Uncorrectible Error line in - * case of another line is used - */ - if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { - int_name = priv->int_name_sfty_ue; - sprintf(int_name, "%s:%s", dev->name, "safety-ue"); - ret = request_irq(priv->sfty_ue_irq, - stmmac_safety_interrupt, - 0, int_name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc sfty ue MSI %d (error: %d)\n", - __func__, priv->sfty_ue_irq, ret); - irq_err = REQ_IRQ_ERR_SFTY_UE; - goto irq_error; - } - } - - /* Request Rx MSI irq */ - for (i = 0; i < priv->plat->rx_queues_to_use; i++) { - if (i >= MTL_MAX_RX_QUEUES) - break; - if (priv->rx_irq[i] == 0) - continue; - - int_name = priv->int_name_rx_irq[i]; - sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); - ret = request_irq(priv->rx_irq[i], - stmmac_msi_intr_rx, - 0, int_name, &priv->rx_queue[i]); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc rx-%d MSI %d (error: %d)\n", - __func__, i, priv->rx_irq[i], ret); - irq_err = REQ_IRQ_ERR_RX; - irq_idx = i; - goto irq_error; - } - cpumask_clear(&cpu_mask); - cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); - irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); - } - - /* Request Tx MSI irq */ - for (i = 0; i < priv->plat->tx_queues_to_use; i++) { - if (i >= MTL_MAX_TX_QUEUES) - break; - if (priv->tx_irq[i] == 0) - continue; - - int_name = priv->int_name_tx_irq[i]; - sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); - ret = request_irq(priv->tx_irq[i], - stmmac_msi_intr_tx, - 0, int_name, &priv->tx_queue[i]); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: alloc tx-%d MSI %d (error: %d)\n", - __func__, i, priv->tx_irq[i], ret); - irq_err = REQ_IRQ_ERR_TX; - irq_idx = i; - goto irq_error; - } - cpumask_clear(&cpu_mask); - cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); - irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); - } - - return 0; - -irq_error: - stmmac_free_irq(dev, irq_err, irq_idx); - return ret; -} - -static int stmmac_request_irq_single(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - enum request_irq_err irq_err; - int ret; - - ret = request_irq(dev->irq, stmmac_interrupt, - IRQF_SHARED, dev->name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: ERROR: allocating the IRQ %d (error: %d)\n", - __func__, dev->irq, ret); - irq_err = REQ_IRQ_ERR_MAC; - goto irq_error; - } - - /* Request the Wake IRQ in case of another line - * is used for WoL - */ - if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { - ret = request_irq(priv->wol_irq, stmmac_interrupt, - IRQF_SHARED, dev->name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: ERROR: allocating the WoL IRQ %d (%d)\n", - __func__, priv->wol_irq, ret); - irq_err = REQ_IRQ_ERR_WOL; - goto irq_error; - } - } - - /* Request the IRQ lines */ - if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { - ret = request_irq(priv->lpi_irq, stmmac_interrupt, - IRQF_SHARED, dev->name, dev); - if (unlikely(ret < 0)) { - netdev_err(priv->dev, - "%s: ERROR: allocating the LPI IRQ %d (%d)\n", - __func__, priv->lpi_irq, ret); - irq_err = REQ_IRQ_ERR_LPI; - goto irq_error; - } - } - - return 0; - -irq_error: - stmmac_free_irq(dev, irq_err, 0); - return ret; -} - -static int stmmac_request_irq(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret; - - /* Request the IRQ lines */ - if (priv->plat->multi_msi_en) - ret = stmmac_request_irq_multi_msi(dev); - else - ret = stmmac_request_irq_single(dev); - - return ret; -} - -/** - * stmmac_open - open entry point of the driver - * @dev : pointer to the device structure. - * Description: - * This function is the open entry point of the driver. - * Return value: - * 0 on success and an appropriate (-)ve integer as defined in errno.h - * file on failure. - */ -int stmmac_open(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int mode = priv->plat->phy_interface; - int bfsize = 0; - u32 chan; - int ret; - - ret = pm_runtime_get_sync(priv->device); - if (ret < 0) { - pm_runtime_put_noidle(priv->device); - return ret; - } - - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI && - (!priv->hw->xpcs || - xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { - ret = stmmac_init_phy(dev); - if (ret) { - netdev_err(priv->dev, - "%s: Cannot attach to PHY (error: %d)\n", - __func__, ret); - goto init_phy_error; - } - } - - /* Extra statistics */ - memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); - priv->xstats.threshold = tc; - - bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); - if (bfsize < 0) - bfsize = 0; - - if (bfsize < BUF_SIZE_16KiB) - bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); - - priv->dma_buf_sz = bfsize; - buf_sz = bfsize; - - priv->rx_copybreak = STMMAC_RX_COPYBREAK; - - if (!priv->dma_tx_size) - priv->dma_tx_size = DMA_DEFAULT_TX_SIZE; - if (!priv->dma_rx_size) - priv->dma_rx_size = DMA_DEFAULT_RX_SIZE; - - /* Earlier check for TBS */ - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; - int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; - - /* Setup per-TXQ tbs flag before TX descriptor alloc */ - tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; - } - - ret = alloc_dma_desc_resources(priv); - if (ret < 0) { - netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", - __func__); - goto dma_desc_error; - } - - ret = init_dma_desc_rings(dev, GFP_KERNEL); - if (ret < 0) { - netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", - __func__); - goto init_error; - } - - ret = stmmac_hw_setup(dev, true); - if (ret < 0) { - netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); - goto init_error; - } - - stmmac_init_coalesce(priv); - - phylink_start(priv->phylink); - /* We may have called phylink_speed_down before */ - phylink_speed_up(priv->phylink); - - ret = stmmac_request_irq(dev); - if (ret) - goto irq_error; - - stmmac_enable_all_queues(priv); - netif_tx_start_all_queues(priv->dev); - - return 0; - -irq_error: - phylink_stop(priv->phylink); - - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - stmmac_hw_teardown(dev); -init_error: - free_dma_desc_resources(priv); -dma_desc_error: - phylink_disconnect_phy(priv->phylink); -init_phy_error: - pm_runtime_put(priv->device); - return ret; -} - -static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) -{ - set_bit(__FPE_REMOVING, &priv->fpe_task_state); - - if (priv->fpe_wq) - destroy_workqueue(priv->fpe_wq); - - netdev_info(priv->dev, "FPE workqueue stop"); -} - -/** - * stmmac_release - close entry point of the driver - * @dev : device pointer. - * Description: - * This is the stop entry point of the driver. - */ -int stmmac_release(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 chan; - - netif_tx_disable(dev); - - if (device_may_wakeup(priv->device)) - phylink_speed_down(priv->phylink, false); - /* Stop and disconnect the PHY */ - phylink_stop(priv->phylink); - phylink_disconnect_phy(priv->phylink); - - stmmac_disable_all_queues(priv); - - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - /* Free the IRQ lines */ - stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); - - if (priv->eee_enabled) { - priv->tx_path_in_lpi_mode = false; - del_timer_sync(&priv->eee_ctrl_timer); - } - - /* Stop TX/RX DMA and clear the descriptors */ - stmmac_stop_all_dma(priv); - - /* Release and free the Rx/Tx resources */ - free_dma_desc_resources(priv); - - /* Disable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, false); - - netif_carrier_off(dev); - - stmmac_release_ptp(priv); - - pm_runtime_put(priv->device); - - if (priv->dma_cap.fpesel) - stmmac_fpe_stop_wq(priv); - - return 0; -} - -static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, - struct stmmac_tx_queue *tx_q) -{ - u16 tag = 0x0, inner_tag = 0x0; - u32 inner_type = 0x0; - struct dma_desc *p; - - if (!priv->dma_cap.vlins) - return false; - if (!skb_vlan_tag_present(skb)) - return false; - if (skb->vlan_proto == htons(ETH_P_8021AD)) { - inner_tag = skb_vlan_tag_get(skb); - inner_type = STMMAC_VLAN_INSERT; - } - - tag = skb_vlan_tag_get(skb); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - p = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - p = &tx_q->dma_tx[tx_q->cur_tx]; - - if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) - return false; - - stmmac_set_tx_owner(priv, p); - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); - return true; -} - -/** - * stmmac_tso_allocator - close entry point of the driver - * @priv: driver private structure - * @des: buffer start address - * @total_len: total length to fill in descriptors - * @last_segment: condition for the last descriptor - * @queue: TX queue index - * Description: - * This function fills descriptor and request new descriptors according to - * buffer length to fill - */ -static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, - int total_len, bool last_segment, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - struct dma_desc *desc; - u32 buff_size; - int tmp_len; - - tmp_len = total_len; - - while (tmp_len > 0) { - dma_addr_t curr_addr; - - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, - priv->dma_tx_size); - WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - desc = &tx_q->dma_tx[tx_q->cur_tx]; - - curr_addr = des + (total_len - tmp_len); - if (priv->dma_cap.addr64 <= 32) - desc->des0 = cpu_to_le32(curr_addr); - else - stmmac_set_desc_addr(priv, desc, curr_addr); - - buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? - TSO_MAX_BUFF_SIZE : tmp_len; - - stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, - 0, 1, - (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), - 0, 0); - - tmp_len -= TSO_MAX_BUFF_SIZE; - } -} - -static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - int desc_size; - - if (likely(priv->extend_desc)) - desc_size = sizeof(struct dma_extended_desc); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc_size = sizeof(struct dma_edesc); - else - desc_size = sizeof(struct dma_desc); - - /* The own bit must be the latest setting done when prepare the - * descriptor and then barrier is needed to make sure that - * all is coherent before granting the DMA engine. - */ - wmb(); - - tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); -} - -/** - * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) - * @skb : the socket buffer - * @dev : device pointer - * Description: this is the transmit function that is called on TSO frames - * (support available on GMAC4 and newer chips). - * Diagram below show the ring programming in case of TSO frames: - * - * First Descriptor - * -------- - * | DES0 |---> buffer1 = L2/L3/L4 header - * | DES1 |---> TCP Payload (can continue on next descr...) - * | DES2 |---> buffer 1 and 2 len - * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] - * -------- - * | - * ... - * | - * -------- - * | DES0 | --| Split TCP Payload on Buffers 1 and 2 - * | DES1 | --| - * | DES2 | --> buffer 1 and 2 len - * | DES3 | - * -------- - * - * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. - */ -static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct dma_desc *desc, *first, *mss_desc = NULL; - struct stmmac_priv *priv = netdev_priv(dev); - int nfrags = skb_shinfo(skb)->nr_frags; - u32 queue = skb_get_queue_mapping(skb); - unsigned int first_entry, tx_packets; - int tmp_pay_len = 0, first_tx; - struct stmmac_tx_queue *tx_q; - bool has_vlan, set_ic; - u8 proto_hdr_len, hdr; - u32 pay_len, mss; - dma_addr_t des; - int i; - - tx_q = &priv->tx_queue[queue]; - first_tx = tx_q->cur_tx; - - /* Compute header lengths */ - if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { - proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); - hdr = sizeof(struct udphdr); - } else { - proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); - hdr = tcp_hdrlen(skb); - } - - /* Desc availability based on threshold should be enough safe */ - if (unlikely(stmmac_tx_avail(priv, queue) < - (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { - if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, - queue)); - /* This is a hard error, log it. */ - netdev_err(priv->dev, - "%s: Tx Ring full when queue awake\n", - __func__); - } - return NETDEV_TX_BUSY; - } - - pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ - - mss = skb_shinfo(skb)->gso_size; - - /* set new MSS value if needed */ - if (mss != tx_q->mss) { - if (tx_q->tbs & STMMAC_TBS_AVAIL) - mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; - - stmmac_set_mss(priv, mss_desc, mss); - tx_q->mss = mss; - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, - priv->dma_tx_size); - WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); - } - - if (netif_msg_tx_queued(priv)) { - pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", - __func__, hdr, proto_hdr_len, pay_len, mss); - pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, - skb->data_len); - } - - /* Check if VLAN can be inserted by HW */ - has_vlan = stmmac_vlan_insert(priv, skb, tx_q); - - first_entry = tx_q->cur_tx; - WARN_ON(tx_q->tx_skbuff[first_entry]); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[first_entry].basic; - else - desc = &tx_q->dma_tx[first_entry]; - first = desc; - - if (has_vlan) - stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); - - /* first descriptor: fill Headers on Buf1 */ - des = dma_map_single(priv->device, skb->data, skb_headlen(skb), - DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; - - tx_q->tx_skbuff_dma[first_entry].buf = des; - tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); - tx_q->tx_skbuff_dma[first_entry].map_as_page = false; - tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; - - if (priv->dma_cap.addr64 <= 32) { - first->des0 = cpu_to_le32(des); - - /* Fill start of payload in buff2 of first descriptor */ - if (pay_len) - first->des1 = cpu_to_le32(des + proto_hdr_len); - - /* If needed take extra descriptors to fill the remaining payload */ - tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; - } else { - stmmac_set_desc_addr(priv, first, des); - tmp_pay_len = pay_len; - des += proto_hdr_len; - pay_len = 0; - } - - stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); - - /* Prepare fragments */ - for (i = 0; i < nfrags; i++) { - const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; - - des = skb_frag_dma_map(priv->device, frag, 0, - skb_frag_size(frag), - DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; - - stmmac_tso_allocator(priv, des, skb_frag_size(frag), - (i == nfrags - 1), queue); - - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; - tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); - tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; - } - - tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; - - /* Only the last descriptor gets to point to the skb. */ - tx_q->tx_skbuff[tx_q->cur_tx] = skb; - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; - - /* Manage tx mitigation */ - tx_packets = (tx_q->cur_tx + 1) - first_tx; - tx_q->tx_count_frames += tx_packets; - - if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) - set_ic = true; - else if (!priv->tx_coal_frames[queue]) - set_ic = false; - else if (tx_packets > priv->tx_coal_frames[queue]) - set_ic = true; - else if ((tx_q->tx_count_frames % - priv->tx_coal_frames[queue]) < tx_packets) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[tx_q->cur_tx].basic; - else - desc = &tx_q->dma_tx[tx_q->cur_tx]; - - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, desc); - priv->xstats.tx_set_ic_bit++; - } - - /* We've used all descriptors we need for this skb, however, - * advance cur_tx so that it references a fresh descriptor. - * ndo_start_xmit will fill this descriptor the next time it's - * called and stmmac_tx_clean may clean up to this descriptor. - */ - tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); - - if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { - netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", - __func__); - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); - } - - dev->stats.tx_bytes += skb->len; - priv->xstats.tx_tso_frames++; - priv->xstats.tx_tso_nfrags += nfrags; - - if (priv->sarc_type) - stmmac_set_desc_sarc(priv, first, priv->sarc_type); - - skb_tx_timestamp(skb); - - if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && - priv->hwts_tx_en)) { - /* declare that device is doing timestamping */ - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - stmmac_enable_tx_timestamp(priv, first); - } - - /* Complete the first descriptor before granting the DMA */ - stmmac_prepare_tso_tx_desc(priv, first, 1, - proto_hdr_len, - pay_len, - 1, tx_q->tx_skbuff_dma[first_entry].last_segment, - hdr / 4, (skb->len - proto_hdr_len)); - - /* If context desc is used to change MSS */ - if (mss_desc) { - /* Make sure that first descriptor has been completely - * written, including its own bit. This is because MSS is - * actually before first descriptor, so we need to make - * sure that MSS's own bit is the last thing written. - */ - dma_wmb(); - stmmac_set_tx_owner(priv, mss_desc); - } - - if (netif_msg_pktdata(priv)) { - pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", - __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, - tx_q->cur_tx, first, nfrags); - pr_info(">>> frame to be transmitted: "); - print_pkt(skb->data, skb_headlen(skb)); - } - - netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); - - stmmac_flush_tx_descriptors(priv, queue); - stmmac_tx_timer_arm(priv, queue); - - return NETDEV_TX_OK; - -dma_map_err: - dev_err(priv->device, "Tx dma map failed\n"); - dev_kfree_skb(skb); - priv->dev->stats.tx_dropped++; - return NETDEV_TX_OK; -} - -/** - * stmmac_xmit - Tx entry point of the driver - * @skb : the socket buffer - * @dev : device pointer - * Description : this is the tx entry point of the driver. - * It programs the chain or the ring and supports oversized frames - * and SG feature. - */ -static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) -{ - unsigned int first_entry, tx_packets, enh_desc; - struct stmmac_priv *priv = netdev_priv(dev); - unsigned int nopaged_len = skb_headlen(skb); - int i, csum_insertion = 0, is_jumbo = 0; - u32 queue = skb_get_queue_mapping(skb); - int nfrags = skb_shinfo(skb)->nr_frags; - int gso = skb_shinfo(skb)->gso_type; - struct dma_edesc *tbs_desc = NULL; - struct dma_desc *desc, *first; - struct stmmac_tx_queue *tx_q; - bool has_vlan, set_ic; - int entry, first_tx; - dma_addr_t des; - - tx_q = &priv->tx_queue[queue]; - first_tx = tx_q->cur_tx; - - if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) - stmmac_disable_eee_mode(priv); - - /* Manage oversized TCP frames for GMAC4 device */ - if (skb_is_gso(skb) && priv->tso) { - if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) - return stmmac_tso_xmit(skb, dev); - if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) - return stmmac_tso_xmit(skb, dev); - } - - if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { - if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, - queue)); - /* This is a hard error, log it. */ - netdev_err(priv->dev, - "%s: Tx Ring full when queue awake\n", - __func__); - } - return NETDEV_TX_BUSY; - } - - /* Check if VLAN can be inserted by HW */ - has_vlan = stmmac_vlan_insert(priv, skb, tx_q); - - entry = tx_q->cur_tx; - first_entry = entry; - WARN_ON(tx_q->tx_skbuff[first_entry]); - - csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); - - if (likely(priv->extend_desc)) - desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[entry].basic; - else - desc = tx_q->dma_tx + entry; - - first = desc; - - if (has_vlan) - stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); - - enh_desc = priv->plat->enh_desc; - /* To program the descriptors according to the size of the frame */ - if (enh_desc) - is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); - - if (unlikely(is_jumbo)) { - entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); - if (unlikely(entry < 0) && (entry != -EINVAL)) - goto dma_map_err; - } - - for (i = 0; i < nfrags; i++) { - const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; - int len = skb_frag_size(frag); - bool last_segment = (i == (nfrags - 1)); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - WARN_ON(tx_q->tx_skbuff[entry]); - - if (likely(priv->extend_desc)) - desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[entry].basic; - else - desc = tx_q->dma_tx + entry; - - des = skb_frag_dma_map(priv->device, frag, 0, len, - DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; /* should reuse desc w/o issues */ - - tx_q->tx_skbuff_dma[entry].buf = des; - - stmmac_set_desc_addr(priv, desc, des); - - tx_q->tx_skbuff_dma[entry].map_as_page = true; - tx_q->tx_skbuff_dma[entry].len = len; - tx_q->tx_skbuff_dma[entry].last_segment = last_segment; - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; - - /* Prepare the descriptor and set the own bit too */ - stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, - priv->mode, 1, last_segment, skb->len); - } - - /* Only the last descriptor gets to point to the skb. */ - tx_q->tx_skbuff[entry] = skb; - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; - - /* According to the coalesce parameter the IC bit for the latest - * segment is reset and the timer re-started to clean the tx status. - * This approach takes care about the fragments: desc is the first - * element in case of no SG. - */ - tx_packets = (entry + 1) - first_tx; - tx_q->tx_count_frames += tx_packets; - - if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) - set_ic = true; - else if (!priv->tx_coal_frames[queue]) - set_ic = false; - else if (tx_packets > priv->tx_coal_frames[queue]) - set_ic = true; - else if ((tx_q->tx_count_frames % - priv->tx_coal_frames[queue]) < tx_packets) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - if (likely(priv->extend_desc)) - desc = &tx_q->dma_etx[entry].basic; - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - desc = &tx_q->dma_entx[entry].basic; - else - desc = &tx_q->dma_tx[entry]; - - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, desc); - priv->xstats.tx_set_ic_bit++; - } - - /* We've used all descriptors we need for this skb, however, - * advance cur_tx so that it references a fresh descriptor. - * ndo_start_xmit will fill this descriptor the next time it's - * called and stmmac_tx_clean may clean up to this descriptor. - */ - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - tx_q->cur_tx = entry; - - if (netif_msg_pktdata(priv)) { - netdev_dbg(priv->dev, - "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", - __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, - entry, first, nfrags); - - netdev_dbg(priv->dev, ">>> frame to be transmitted: "); - print_pkt(skb->data, skb->len); - } - - if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { - netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", - __func__); - netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); - } - - dev->stats.tx_bytes += skb->len; - - if (priv->sarc_type) - stmmac_set_desc_sarc(priv, first, priv->sarc_type); - - skb_tx_timestamp(skb); - - /* Ready to fill the first descriptor and set the OWN bit w/o any - * problems because all the descriptors are actually ready to be - * passed to the DMA engine. - */ - if (likely(!is_jumbo)) { - bool last_segment = (nfrags == 0); - - des = dma_map_single(priv->device, skb->data, - nopaged_len, DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, des)) - goto dma_map_err; - - tx_q->tx_skbuff_dma[first_entry].buf = des; - tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; - tx_q->tx_skbuff_dma[first_entry].map_as_page = false; - - stmmac_set_desc_addr(priv, first, des); - - tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; - tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; - - if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && - priv->hwts_tx_en)) { - /* declare that device is doing timestamping */ - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - stmmac_enable_tx_timestamp(priv, first); - } - - /* Prepare the first descriptor setting the OWN bit too */ - stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, - csum_insertion, priv->mode, 0, last_segment, - skb->len); - } - - if (tx_q->tbs & STMMAC_TBS_EN) { - struct timespec64 ts = ns_to_timespec64(skb->tstamp); - - tbs_desc = &tx_q->dma_entx[first_entry]; - stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); - } - - stmmac_set_tx_owner(priv, first); - - netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); - - stmmac_enable_dma_transmission(priv, priv->ioaddr); - - stmmac_flush_tx_descriptors(priv, queue); - stmmac_tx_timer_arm(priv, queue); - - return NETDEV_TX_OK; - -dma_map_err: - netdev_err(priv->dev, "Tx DMA map failed\n"); - dev_kfree_skb(skb); - priv->dev->stats.tx_dropped++; - return NETDEV_TX_OK; -} - -static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) -{ - struct vlan_ethhdr *veth; - __be16 vlan_proto; - u16 vlanid; - - veth = (struct vlan_ethhdr *)skb->data; - vlan_proto = veth->h_vlan_proto; - - if ((vlan_proto == htons(ETH_P_8021Q) && - dev->features & NETIF_F_HW_VLAN_CTAG_RX) || - (vlan_proto == htons(ETH_P_8021AD) && - dev->features & NETIF_F_HW_VLAN_STAG_RX)) { - /* pop the vlan tag */ - vlanid = ntohs(veth->h_vlan_TCI); - memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); - skb_pull(skb, VLAN_HLEN); - __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); - } -} - -/** - * stmmac_rx_refill - refill used skb preallocated buffers - * @priv: driver private structure - * @queue: RX queue index - * Description : this is to reallocate the skb for the reception process - * that is based on zero-copy. - */ -static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - int dirty = stmmac_rx_dirty(priv, queue); - unsigned int entry = rx_q->dirty_rx; - - while (dirty-- > 0) { - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; - struct dma_desc *p; - bool use_rx_wd; - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + entry); - else - p = rx_q->dma_rx + entry; - - if (!buf->page) { - buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); - if (!buf->page) - break; - } - - if (priv->sph && !buf->sec_page) { - buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); - if (!buf->sec_page) - break; - - buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); - } - - buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; - - stmmac_set_desc_addr(priv, p, buf->addr); - if (priv->sph) - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); - else - stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); - stmmac_refill_desc3(priv, rx_q, p); - - rx_q->rx_count_frames++; - rx_q->rx_count_frames += priv->rx_coal_frames[queue]; - if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) - rx_q->rx_count_frames = 0; - - use_rx_wd = !priv->rx_coal_frames[queue]; - use_rx_wd |= rx_q->rx_count_frames > 0; - if (!priv->use_riwt) - use_rx_wd = false; - - dma_wmb(); - stmmac_set_rx_owner(priv, p, use_rx_wd); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); - } - rx_q->dirty_rx = entry; - rx_q->rx_tail_addr = rx_q->dma_rx_phy + - (rx_q->dirty_rx * sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); -} - -static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, - struct dma_desc *p, - int status, unsigned int len) -{ - unsigned int plen = 0, hlen = 0; - int coe = priv->hw->rx_csum; - - /* Not first descriptor, buffer is always zero */ - if (priv->sph && len) - return 0; - - /* First descriptor, get split header length */ - stmmac_get_rx_header_len(priv, p, &hlen); - if (priv->sph && hlen) { - priv->xstats.rx_split_hdr_pkt_n++; - return hlen; - } - - /* First descriptor, not last descriptor and not split header */ - if (status & rx_not_ls) - return priv->dma_buf_sz; - - plen = stmmac_get_rx_frame_len(priv, p, coe); - - /* First descriptor and last descriptor and not split header */ - return min_t(unsigned int, priv->dma_buf_sz, plen); -} - -static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, - struct dma_desc *p, - int status, unsigned int len) -{ - int coe = priv->hw->rx_csum; - unsigned int plen = 0; - - /* Not split header, buffer is not available */ - if (!priv->sph) - return 0; - - /* Not last descriptor */ - if (status & rx_not_ls) - return priv->dma_buf_sz; - - plen = stmmac_get_rx_frame_len(priv, p, coe); - - /* Last descriptor */ - return plen - len; -} - -<<<<<<< -static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, - struct xdp_frame *xdpf, bool dma_map) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - unsigned int entry = tx_q->cur_tx; - struct dma_desc *tx_desc; - dma_addr_t dma_addr; - bool set_ic; - - if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) - return STMMAC_XDP_CONSUMED; - - if (likely(priv->extend_desc)) - tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); - else if (tx_q->tbs & STMMAC_TBS_AVAIL) - tx_desc = &tx_q->dma_entx[entry].basic; - else - tx_desc = tx_q->dma_tx + entry; - - if (dma_map) { - dma_addr = dma_map_single(priv->device, xdpf->data, - xdpf->len, DMA_TO_DEVICE); - if (dma_mapping_error(priv->device, dma_addr)) - return STMMAC_XDP_CONSUMED; - - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; - } else { - struct page *page = virt_to_page(xdpf->data); - - dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + - xdpf->headroom; - dma_sync_single_for_device(priv->device, dma_addr, - xdpf->len, DMA_BIDIRECTIONAL); - - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; - } - - tx_q->tx_skbuff_dma[entry].buf = dma_addr; - tx_q->tx_skbuff_dma[entry].map_as_page = false; - tx_q->tx_skbuff_dma[entry].len = xdpf->len; - tx_q->tx_skbuff_dma[entry].last_segment = true; - tx_q->tx_skbuff_dma[entry].is_jumbo = false; - - tx_q->xdpf[entry] = xdpf; - - stmmac_set_desc_addr(priv, tx_desc, dma_addr); - - stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, - true, priv->mode, true, true, - xdpf->len); - - tx_q->tx_count_frames++; - - if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) - set_ic = true; - else - set_ic = false; - - if (set_ic) { - tx_q->tx_count_frames = 0; - stmmac_set_tx_ic(priv, tx_desc); - priv->xstats.tx_set_ic_bit++; - } - - stmmac_enable_dma_transmission(priv, priv->ioaddr); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); - tx_q->cur_tx = entry; - - return STMMAC_XDP_TX; -} - -static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, - int cpu) -{ - int index = cpu; - - if (unlikely(index < 0)) - index = 0; - - while (index >= priv->plat->tx_queues_to_use) - index -= priv->plat->tx_queues_to_use; - - return index; -} - -static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, - struct xdp_buff *xdp) -{ - struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); - int cpu = smp_processor_id(); - struct netdev_queue *nq; - int queue; - int res; - - if (unlikely(!xdpf)) - return STMMAC_XDP_CONSUMED; - - queue = stmmac_xdp_get_tx_queue(priv, cpu); - nq = netdev_get_tx_queue(priv->dev, queue); - - __netif_tx_lock(nq, cpu); - /* Avoids TX time-out as we are sharing with slow path */ - nq->trans_start = jiffies; - - res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); - if (res == STMMAC_XDP_TX) - stmmac_flush_tx_descriptors(priv, queue); - - __netif_tx_unlock(nq); - - return res; -} - -static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, - struct bpf_prog *prog, - struct xdp_buff *xdp) -{ - u32 act; - int res; -======= -static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, - struct xdp_buff *xdp) -{ - struct bpf_prog *prog; - int res; - u32 act; - - rcu_read_lock(); - - prog = READ_ONCE(priv->xdp_prog); - if (!prog) { - res = STMMAC_XDP_PASS; - goto unlock; - } ->>>>>>> - - act = bpf_prog_run_xdp(prog, xdp); - switch (act) { - case XDP_PASS: - res = STMMAC_XDP_PASS; - break; -<<<<<<< -======= - case XDP_TX: - res = stmmac_xdp_xmit_back(priv, xdp); - break; - case XDP_REDIRECT: - if (xdp_do_redirect(priv->dev, xdp, prog) < 0) - res = STMMAC_XDP_CONSUMED; - else - res = STMMAC_XDP_REDIRECT; - break; ->>>>>>> - default: - bpf_warn_invalid_xdp_action(act); - fallthrough; - case XDP_ABORTED: - trace_xdp_exception(priv->dev, prog, act); - fallthrough; - case XDP_DROP: - res = STMMAC_XDP_CONSUMED; - break; - } - -<<<<<<< - return res; -} - -static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, - struct xdp_buff *xdp) -{ - struct bpf_prog *prog; - int res; - - prog = READ_ONCE(priv->xdp_prog); - if (!prog) { - res = STMMAC_XDP_PASS; - goto out; - } - - res = __stmmac_xdp_run_prog(priv, prog, xdp); -out: - return ERR_PTR(-res); -} - -static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, - int xdp_status) -{ - int cpu = smp_processor_id(); - int queue; - - queue = stmmac_xdp_get_tx_queue(priv, cpu); - - if (xdp_status & STMMAC_XDP_TX) - stmmac_tx_timer_arm(priv, queue); - - if (xdp_status & STMMAC_XDP_REDIRECT) - xdp_do_flush(); -} - -static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, - struct xdp_buff *xdp) -{ - unsigned int metasize = xdp->data - xdp->data_meta; - unsigned int datasize = xdp->data_end - xdp->data; - struct sk_buff *skb; - - skb = __napi_alloc_skb(&ch->rxtx_napi, - xdp->data_end - xdp->data_hard_start, - GFP_ATOMIC | __GFP_NOWARN); - if (unlikely(!skb)) - return NULL; - - skb_reserve(skb, xdp->data - xdp->data_hard_start); - memcpy(__skb_put(skb, datasize), xdp->data, datasize); - if (metasize) - skb_metadata_set(skb, metasize); - - return skb; -} - -static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, - struct dma_desc *p, struct dma_desc *np, - struct xdp_buff *xdp) -{ - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned int len = xdp->data_end - xdp->data; - enum pkt_hash_types hash_type; - int coe = priv->hw->rx_csum; - struct sk_buff *skb; - u32 hash; - - skb = stmmac_construct_skb_zc(ch, xdp); - if (!skb) { - priv->dev->stats.rx_dropped++; - return; - } - - stmmac_get_rx_hwtstamp(priv, p, np, skb); - stmmac_rx_vlan(priv->dev, skb); - skb->protocol = eth_type_trans(skb, priv->dev); - - if (unlikely(!coe)) - skb_checksum_none_assert(skb); - else - skb->ip_summed = CHECKSUM_UNNECESSARY; - - if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) - skb_set_hash(skb, hash, hash_type); - - skb_record_rx_queue(skb, queue); - napi_gro_receive(&ch->rxtx_napi, skb); - - priv->dev->stats.rx_packets++; - priv->dev->stats.rx_bytes += len; -} - -static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - unsigned int entry = rx_q->dirty_rx; - struct dma_desc *rx_desc = NULL; - bool ret = true; - - budget = min(budget, stmmac_rx_dirty(priv, queue)); - - while (budget-- > 0 && entry != rx_q->cur_rx) { - struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; - dma_addr_t dma_addr; - bool use_rx_wd; - - if (!buf->xdp) { - buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); - if (!buf->xdp) { - ret = false; - break; - } - } - - if (priv->extend_desc) - rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); - else - rx_desc = rx_q->dma_rx + entry; - - dma_addr = xsk_buff_xdp_get_dma(buf->xdp); - stmmac_set_desc_addr(priv, rx_desc, dma_addr); - stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); - stmmac_refill_desc3(priv, rx_q, rx_desc); - - rx_q->rx_count_frames++; - rx_q->rx_count_frames += priv->rx_coal_frames[queue]; - if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) - rx_q->rx_count_frames = 0; - - use_rx_wd = !priv->rx_coal_frames[queue]; - use_rx_wd |= rx_q->rx_count_frames > 0; - if (!priv->use_riwt) - use_rx_wd = false; - - dma_wmb(); - stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); - - entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); - } - - if (rx_desc) { - rx_q->dirty_rx = entry; - rx_q->rx_tail_addr = rx_q->dma_rx_phy + - (rx_q->dirty_rx * sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); - } - - return ret; -} - -static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - unsigned int count = 0, error = 0, len = 0; - int dirty = stmmac_rx_dirty(priv, queue); - unsigned int next_entry = rx_q->cur_rx; - unsigned int desc_size; - struct bpf_prog *prog; - bool failure = false; - int xdp_status = 0; - int status = 0; - - if (netif_msg_rx_status(priv)) { - void *rx_head; - - netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); - if (priv->extend_desc) { - rx_head = (void *)rx_q->dma_erx; - desc_size = sizeof(struct dma_extended_desc); - } else { - rx_head = (void *)rx_q->dma_rx; - desc_size = sizeof(struct dma_desc); - } - - stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, - rx_q->dma_rx_phy, desc_size); - } - while (count < limit) { - struct stmmac_rx_buffer *buf; - unsigned int buf1_len = 0; - struct dma_desc *np, *p; - int entry; - int res; - - if (!count && rx_q->state_saved) { - error = rx_q->state.error; - len = rx_q->state.len; - } else { - rx_q->state_saved = false; - error = 0; - len = 0; - } - - if (count >= limit) - break; - -read_again: - buf1_len = 0; - entry = next_entry; - buf = &rx_q->buf_pool[entry]; - - if (dirty >= STMMAC_RX_FILL_BATCH) { - failure = failure || - !stmmac_rx_refill_zc(priv, queue, dirty); - dirty = 0; - } - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + entry); - else - p = rx_q->dma_rx + entry; - - /* read the status of the incoming frame */ - status = stmmac_rx_status(priv, &priv->dev->stats, - &priv->xstats, p); - /* check if managed by the DMA otherwise go ahead */ - if (unlikely(status & dma_own)) - break; - - /* Prefetch the next RX descriptor */ - rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, - priv->dma_rx_size); - next_entry = rx_q->cur_rx; - - if (priv->extend_desc) - np = (struct dma_desc *)(rx_q->dma_erx + next_entry); - else - np = rx_q->dma_rx + next_entry; - - prefetch(np); - - /* Ensure a valid XSK buffer before proceed */ - if (!buf->xdp) - break; - - if (priv->extend_desc) - stmmac_rx_extended_status(priv, &priv->dev->stats, - &priv->xstats, - rx_q->dma_erx + entry); - if (unlikely(status == discard_frame)) { - xsk_buff_free(buf->xdp); - buf->xdp = NULL; - dirty++; - error = 1; - if (!priv->hwts_rx_en) - priv->dev->stats.rx_errors++; - } - - if (unlikely(error && (status & rx_not_ls))) - goto read_again; - if (unlikely(error)) { - count++; - continue; - } - - /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ - if (likely(status & rx_not_ls)) { - xsk_buff_free(buf->xdp); - buf->xdp = NULL; - dirty++; - count++; - goto read_again; - } - - /* XDP ZC Frame only support primary buffers for now */ - buf1_len = stmmac_rx_buf1_len(priv, p, status, len); - len += buf1_len; - - /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 - * Type frames (LLC/LLC-SNAP) - * - * llc_snap is never checked in GMAC >= 4, so this ACS - * feature is always disabled and packets need to be - * stripped manually. - */ - if (likely(!(status & rx_not_ls)) && - (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || - unlikely(status != llc_snap))) { - buf1_len -= ETH_FCS_LEN; - len -= ETH_FCS_LEN; - } - - /* RX buffer is good and fit into a XSK pool buffer */ - buf->xdp->data_end = buf->xdp->data + buf1_len; - xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); - - prog = READ_ONCE(priv->xdp_prog); - res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); - - switch (res) { - case STMMAC_XDP_PASS: - stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); - xsk_buff_free(buf->xdp); - break; - case STMMAC_XDP_CONSUMED: - xsk_buff_free(buf->xdp); - priv->dev->stats.rx_dropped++; - break; - case STMMAC_XDP_TX: - case STMMAC_XDP_REDIRECT: - xdp_status |= res; - break; - } - - buf->xdp = NULL; - dirty++; - count++; - } - - if (status & rx_not_ls) { - rx_q->state_saved = true; - rx_q->state.error = error; - rx_q->state.len = len; - } - - stmmac_finalize_xdp_rx(priv, xdp_status); - - priv->xstats.rx_pkt_n += count; - priv->xstats.rxq_stats[queue].rx_pkt_n += count; - - if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { - if (failure || stmmac_rx_dirty(priv, queue) > 0) - xsk_set_rx_need_wakeup(rx_q->xsk_pool); - else - xsk_clear_rx_need_wakeup(rx_q->xsk_pool); - - return (int)count; - } - - return failure ? limit : (int)count; -} - -======= -unlock: - rcu_read_unlock(); - return ERR_PTR(-res); -} - ->>>>>>> -/** - * stmmac_rx - manage the receive process - * @priv: driver private structure - * @limit: napi bugget - * @queue: RX queue index. - * Description : this the function called by the napi poll method. - * It gets all the frames inside the ring. - */ -static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned int count = 0, error = 0, len = 0; - int status = 0, coe = priv->hw->rx_csum; - unsigned int next_entry = rx_q->cur_rx; - enum dma_data_direction dma_dir; - unsigned int desc_size; - struct sk_buff *skb = NULL; - struct xdp_buff xdp; -<<<<<<< -======= - int xdp_status = 0; ->>>>>>> - int buf_sz; - - dma_dir = page_pool_get_dma_dir(rx_q->page_pool); - buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; - - if (netif_msg_rx_status(priv)) { - void *rx_head; - - netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); - if (priv->extend_desc) { - rx_head = (void *)rx_q->dma_erx; - desc_size = sizeof(struct dma_extended_desc); - } else { - rx_head = (void *)rx_q->dma_rx; - desc_size = sizeof(struct dma_desc); - } - - stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, - rx_q->dma_rx_phy, desc_size); - } - while (count < limit) { - unsigned int buf1_len = 0, buf2_len = 0; - enum pkt_hash_types hash_type; - struct stmmac_rx_buffer *buf; - struct dma_desc *np, *p; - int entry; - u32 hash; - - if (!count && rx_q->state_saved) { - skb = rx_q->state.skb; - error = rx_q->state.error; - len = rx_q->state.len; - } else { - rx_q->state_saved = false; - skb = NULL; - error = 0; - len = 0; - } - - if (count >= limit) - break; - -read_again: - buf1_len = 0; - buf2_len = 0; - entry = next_entry; - buf = &rx_q->buf_pool[entry]; - - if (priv->extend_desc) - p = (struct dma_desc *)(rx_q->dma_erx + entry); - else - p = rx_q->dma_rx + entry; - - /* read the status of the incoming frame */ - status = stmmac_rx_status(priv, &priv->dev->stats, - &priv->xstats, p); - /* check if managed by the DMA otherwise go ahead */ - if (unlikely(status & dma_own)) - break; - - rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, - priv->dma_rx_size); - next_entry = rx_q->cur_rx; - - if (priv->extend_desc) - np = (struct dma_desc *)(rx_q->dma_erx + next_entry); - else - np = rx_q->dma_rx + next_entry; - - prefetch(np); - - if (priv->extend_desc) - stmmac_rx_extended_status(priv, &priv->dev->stats, - &priv->xstats, rx_q->dma_erx + entry); - if (unlikely(status == discard_frame)) { - page_pool_recycle_direct(rx_q->page_pool, buf->page); - buf->page = NULL; - error = 1; - if (!priv->hwts_rx_en) - priv->dev->stats.rx_errors++; - } - - if (unlikely(error && (status & rx_not_ls))) - goto read_again; - if (unlikely(error)) { - dev_kfree_skb(skb); - skb = NULL; - count++; - continue; - } - - /* Buffer is good. Go on. */ - - prefetch(page_address(buf->page) + buf->page_offset); - if (buf->sec_page) - prefetch(page_address(buf->sec_page)); - - buf1_len = stmmac_rx_buf1_len(priv, p, status, len); - len += buf1_len; - buf2_len = stmmac_rx_buf2_len(priv, p, status, len); - len += buf2_len; - - /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 - * Type frames (LLC/LLC-SNAP) - * - * llc_snap is never checked in GMAC >= 4, so this ACS - * feature is always disabled and packets need to be - * stripped manually. - */ - if (likely(!(status & rx_not_ls)) && - (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || - unlikely(status != llc_snap))) { - if (buf2_len) { - buf2_len -= ETH_FCS_LEN; - len -= ETH_FCS_LEN; - } else if (buf1_len) { - buf1_len -= ETH_FCS_LEN; - len -= ETH_FCS_LEN; - } - } - - if (!skb) { -<<<<<<< - dma_sync_single_for_cpu(priv->device, buf->addr, - buf1_len, dma_dir); - - xdp.data = page_address(buf->page) + buf->page_offset; - xdp.data_end = xdp.data + buf1_len; - xdp.data_hard_start = page_address(buf->page); - xdp_set_data_meta_invalid(&xdp); - xdp.frame_sz = buf_sz; - - skb = stmmac_xdp_run_prog(priv, &xdp); -======= - unsigned int pre_len, sync_len; - - dma_sync_single_for_cpu(priv->device, buf->addr, - buf1_len, dma_dir); - - xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); - xdp_prepare_buff(&xdp, page_address(buf->page), - buf->page_offset, buf1_len, false); - - pre_len = xdp.data_end - xdp.data_hard_start - - buf->page_offset; - skb = stmmac_xdp_run_prog(priv, &xdp); - /* Due xdp_adjust_tail: DMA sync for_device - * cover max len CPU touch - */ - sync_len = xdp.data_end - xdp.data_hard_start - - buf->page_offset; - sync_len = max(sync_len, pre_len); ->>>>>>> - - /* For Not XDP_PASS verdict */ - if (IS_ERR(skb)) { - unsigned int xdp_res = -PTR_ERR(skb); - - if (xdp_res & STMMAC_XDP_CONSUMED) { -<<<<<<< - page_pool_put_page(rx_q->page_pool, - virt_to_head_page(xdp.data), - sync_len, true); -======= - page_pool_recycle_direct(rx_q->page_pool, - buf->page); ->>>>>>> - buf->page = NULL; - priv->dev->stats.rx_dropped++; - - /* Clear skb as it was set as - * status by XDP program. - */ - skb = NULL; - - if (unlikely((status & rx_not_ls))) - goto read_again; - - count++; - continue; -<<<<<<< -======= - } else if (xdp_res & (STMMAC_XDP_TX | - STMMAC_XDP_REDIRECT)) { - xdp_status |= xdp_res; - buf->page = NULL; - skb = NULL; - count++; - continue; ->>>>>>> - } - } - } - - if (!skb) { - /* XDP program may expand or reduce tail */ - buf1_len = xdp.data_end - xdp.data; - - skb = napi_alloc_skb(&ch->rx_napi, buf1_len); - if (!skb) { - priv->dev->stats.rx_dropped++; - count++; - goto drain_data; - } - - /* XDP program may adjust header */ - skb_copy_to_linear_data(skb, xdp.data, buf1_len); - skb_put(skb, buf1_len); - - /* Data payload copied into SKB, page ready for recycle */ - page_pool_recycle_direct(rx_q->page_pool, buf->page); - buf->page = NULL; - } else if (buf1_len) { - dma_sync_single_for_cpu(priv->device, buf->addr, - buf1_len, dma_dir); - skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, - buf->page, buf->page_offset, buf1_len, - priv->dma_buf_sz); - - /* Data payload appended into SKB */ - page_pool_release_page(rx_q->page_pool, buf->page); - buf->page = NULL; - } - - if (buf2_len) { - dma_sync_single_for_cpu(priv->device, buf->sec_addr, - buf2_len, dma_dir); - skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, - buf->sec_page, 0, buf2_len, - priv->dma_buf_sz); - - /* Data payload appended into SKB */ - page_pool_release_page(rx_q->page_pool, buf->sec_page); - buf->sec_page = NULL; - } - -drain_data: - if (likely(status & rx_not_ls)) - goto read_again; - if (!skb) - continue; - - /* Got entire packet into SKB. Finish it. */ - - stmmac_get_rx_hwtstamp(priv, p, np, skb); - stmmac_rx_vlan(priv->dev, skb); - skb->protocol = eth_type_trans(skb, priv->dev); - - if (unlikely(!coe)) - skb_checksum_none_assert(skb); - else - skb->ip_summed = CHECKSUM_UNNECESSARY; - - if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) - skb_set_hash(skb, hash, hash_type); - - skb_record_rx_queue(skb, queue); - napi_gro_receive(&ch->rx_napi, skb); - skb = NULL; - - priv->dev->stats.rx_packets++; - priv->dev->stats.rx_bytes += len; - count++; - } - - if (status & rx_not_ls || skb) { - rx_q->state_saved = true; - rx_q->state.skb = skb; - rx_q->state.error = error; - rx_q->state.len = len; - } - - stmmac_finalize_xdp_rx(priv, xdp_status); - - stmmac_rx_refill(priv, queue); - - priv->xstats.rx_pkt_n += count; - priv->xstats.rxq_stats[queue].rx_pkt_n += count; - - return count; -} - -static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) -{ - struct stmmac_channel *ch = - container_of(napi, struct stmmac_channel, rx_napi); - struct stmmac_priv *priv = ch->priv_data; - u32 chan = ch->index; - int work_done; - - priv->xstats.napi_poll++; - - work_done = stmmac_rx(priv, budget, chan); - if (work_done < budget && napi_complete_done(napi, work_done)) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); - } - - return work_done; -} - -static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) -{ - struct stmmac_channel *ch = - container_of(napi, struct stmmac_channel, tx_napi); - struct stmmac_priv *priv = ch->priv_data; - u32 chan = ch->index; - int work_done; - - priv->xstats.napi_poll++; - - work_done = stmmac_tx_clean(priv, budget, chan); - work_done = min(work_done, budget); - - if (work_done < budget && napi_complete_done(napi, work_done)) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - } - - return work_done; -} - -static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) -{ - struct stmmac_channel *ch = - container_of(napi, struct stmmac_channel, rxtx_napi); - struct stmmac_priv *priv = ch->priv_data; - int rx_done, tx_done, rxtx_done; - u32 chan = ch->index; - - priv->xstats.napi_poll++; - - tx_done = stmmac_tx_clean(priv, budget, chan); - tx_done = min(tx_done, budget); - - rx_done = stmmac_rx_zc(priv, budget, chan); - - rxtx_done = max(tx_done, rx_done); - - /* If either TX or RX work is not complete, return budget - * and keep pooling - */ - if (rxtx_done >= budget) - return budget; - - /* all work done, exit the polling mode */ - if (napi_complete_done(napi, rxtx_done)) { - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - /* Both RX and TX work done are compelte, - * so enable both RX & TX IRQs. - */ - stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); - spin_unlock_irqrestore(&ch->lock, flags); - } - - return min(rxtx_done, budget - 1); -} - -/** - * stmmac_tx_timeout - * @dev : Pointer to net device structure - * @txqueue: the index of the hanging transmit queue - * Description: this function is called when a packet transmission fails to - * complete within a reasonable time. The driver will mark the error in the - * netdev structure and arrange for the device to be reset to a sane state - * in order to transmit a new packet. - */ -static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - stmmac_global_err(priv); -} - -/** - * stmmac_set_rx_mode - entry point for multicast addressing - * @dev : pointer to the device structure - * Description: - * This function is a driver entry point which gets called by the kernel - * whenever multicast addresses must be enabled/disabled. - * Return value: - * void. - */ -static void stmmac_set_rx_mode(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - stmmac_set_filter(priv, priv->hw, dev); -} - -/** - * stmmac_change_mtu - entry point to change MTU size for the device. - * @dev : device pointer. - * @new_mtu : the new MTU size for the device. - * Description: the Maximum Transfer Unit (MTU) is used by the network layer - * to drive packet transmission. Ethernet has an MTU of 1500 octets - * (ETH_DATA_LEN). This value can be changed with ifconfig. - * Return value: - * 0 on success and an appropriate (-)ve integer as defined in errno.h - * file on failure. - */ -static int stmmac_change_mtu(struct net_device *dev, int new_mtu) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int txfifosz = priv->plat->tx_fifo_size; - const int mtu = new_mtu; - - if (txfifosz == 0) - txfifosz = priv->dma_cap.tx_fifo_size; - - txfifosz /= priv->plat->tx_queues_to_use; - - if (netif_running(dev)) { - netdev_err(priv->dev, "must be stopped to change its MTU\n"); - return -EBUSY; - } - - if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { - netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); - return -EINVAL; - } - - new_mtu = STMMAC_ALIGN(new_mtu); - - /* If condition true, FIFO is too small or MTU too large */ - if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) - return -EINVAL; - - dev->mtu = mtu; - - netdev_update_features(dev); - - return 0; -} - -static netdev_features_t stmmac_fix_features(struct net_device *dev, - netdev_features_t features) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) - features &= ~NETIF_F_RXCSUM; - - if (!priv->plat->tx_coe) - features &= ~NETIF_F_CSUM_MASK; - - /* Some GMAC devices have a bugged Jumbo frame support that - * needs to have the Tx COE disabled for oversized frames - * (due to limited buffer sizes). In this case we disable - * the TX csum insertion in the TDES and not use SF. - */ - if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) - features &= ~NETIF_F_CSUM_MASK; - - /* Disable tso if asked by ethtool */ - if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { - if (features & NETIF_F_TSO) - priv->tso = true; - else - priv->tso = false; - } - - return features; -} - -static int stmmac_set_features(struct net_device *netdev, - netdev_features_t features) -{ - struct stmmac_priv *priv = netdev_priv(netdev); - bool sph_en; - u32 chan; - - /* Keep the COE Type in case of csum is supporting */ - if (features & NETIF_F_RXCSUM) - priv->hw->rx_csum = priv->plat->rx_coe; - else - priv->hw->rx_csum = 0; - /* No check needed because rx_coe has been set before and it will be - * fixed in case of issue. - */ - stmmac_rx_ipc(priv, priv->hw); - - sph_en = (priv->hw->rx_csum > 0) && priv->sph; - - for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) - stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); - - return 0; -} - -static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) -{ - struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; - enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; - enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; - bool *hs_enable = &fpe_cfg->hs_enable; - - if (status == FPE_EVENT_UNKNOWN || !*hs_enable) - return; - - /* If LP has sent verify mPacket, LP is FPE capable */ - if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { - if (*lp_state < FPE_STATE_CAPABLE) - *lp_state = FPE_STATE_CAPABLE; - - /* If user has requested FPE enable, quickly response */ - if (*hs_enable) - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - MPACKET_RESPONSE); - } - - /* If Local has sent verify mPacket, Local is FPE capable */ - if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { - if (*lo_state < FPE_STATE_CAPABLE) - *lo_state = FPE_STATE_CAPABLE; - } - - /* If LP has sent response mPacket, LP is entering FPE ON */ - if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) - *lp_state = FPE_STATE_ENTERING_ON; - - /* If Local has sent response mPacket, Local is entering FPE ON */ - if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) - *lo_state = FPE_STATE_ENTERING_ON; - - if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && - !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && - priv->fpe_wq) { - queue_work(priv->fpe_wq, &priv->fpe_task); - } -} - -static void stmmac_common_interrupt(struct stmmac_priv *priv) -{ - u32 rx_cnt = priv->plat->rx_queues_to_use; - u32 tx_cnt = priv->plat->tx_queues_to_use; - u32 queues_count; - u32 queue; - bool xmac; - - xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; - queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; - - if (priv->irq_wake) - pm_wakeup_event(priv->device, 0); - - if (priv->dma_cap.estsel) - stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, - &priv->xstats, tx_cnt); - - if (priv->dma_cap.fpesel) { - int status = stmmac_fpe_irq_status(priv, priv->ioaddr, - priv->dev); - - stmmac_fpe_event_status(priv, status); - } - - /* To handle GMAC own interrupts */ - if ((priv->plat->has_gmac) || xmac) { - int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); - - if (unlikely(status)) { - /* For LPI we need to save the tx status */ - if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) - priv->tx_path_in_lpi_mode = true; - if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) - priv->tx_path_in_lpi_mode = false; - } - - for (queue = 0; queue < queues_count; queue++) { - status = stmmac_host_mtl_irq_status(priv, priv->hw, - queue); - } - - /* PCS link status */ - if (priv->hw->pcs) { - if (priv->xstats.pcs_link) - netif_carrier_on(priv->dev); - else - netif_carrier_off(priv->dev); - } - - stmmac_timestamp_interrupt(priv, priv); - } -} - -/** - * stmmac_interrupt - main ISR - * @irq: interrupt number. - * @dev_id: to pass the net device pointer. - * Description: this is the main driver interrupt service routine. - * It can call: - * o DMA service routine (to manage incoming frame reception and transmission - * status) - * o Core interrupts to manage: remote wake-up, management counter, LPI - * interrupts. - */ -static irqreturn_t stmmac_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *)dev_id; - struct stmmac_priv *priv = netdev_priv(dev); - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - /* Check if a fatal error happened */ - if (stmmac_safety_feat_interrupt(priv)) - return IRQ_HANDLED; - - /* To handle Common interrupts */ - stmmac_common_interrupt(priv); - - /* To handle DMA interrupts */ - stmmac_dma_interrupt(priv); - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *)dev_id; - struct stmmac_priv *priv = netdev_priv(dev); - - if (unlikely(!dev)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - /* To handle Common interrupts */ - stmmac_common_interrupt(priv); - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *)dev_id; - struct stmmac_priv *priv = netdev_priv(dev); - - if (unlikely(!dev)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - /* Check if a fatal error happened */ - stmmac_safety_feat_interrupt(priv); - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) -{ - struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; - int chan = tx_q->queue_index; - struct stmmac_priv *priv; - int status; - - priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]); - - if (unlikely(!data)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - status = stmmac_napi_check(priv, chan, DMA_DIR_TX); - - if (unlikely(status & tx_hard_error_bump_tc)) { - /* Try to bump up the dma threshold on this failure */ - if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && - tc <= 256) { - tc += 64; - if (priv->plat->force_thresh_dma_mode) - stmmac_set_dma_operation_mode(priv, - tc, - tc, - chan); - else - stmmac_set_dma_operation_mode(priv, - tc, - SF_DMA_MODE, - chan); - priv->xstats.threshold = tc; - } - } else if (unlikely(status == tx_hard_error)) { - stmmac_tx_err(priv, chan); - } - - return IRQ_HANDLED; -} - -static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) -{ - struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; - int chan = rx_q->queue_index; - struct stmmac_priv *priv; - - priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]); - - if (unlikely(!data)) { - netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); - return IRQ_NONE; - } - - /* Check if adapter is up */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return IRQ_HANDLED; - - stmmac_napi_check(priv, chan, DMA_DIR_RX); - - return IRQ_HANDLED; -} - -#ifdef CONFIG_NET_POLL_CONTROLLER -/* Polling receive - used by NETCONSOLE and other diagnostic tools - * to allow network I/O with interrupts disabled. - */ -static void stmmac_poll_controller(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int i; - - /* If adapter is down, do nothing */ - if (test_bit(STMMAC_DOWN, &priv->state)) - return; - - if (priv->plat->multi_msi_en) { - for (i = 0; i < priv->plat->rx_queues_to_use; i++) - stmmac_msi_intr_rx(0, &priv->rx_queue[i]); - - for (i = 0; i < priv->plat->tx_queues_to_use; i++) - stmmac_msi_intr_tx(0, &priv->tx_queue[i]); - } else { - disable_irq(dev->irq); - stmmac_interrupt(dev->irq, dev); - enable_irq(dev->irq); - } -} -#endif - -/** - * stmmac_ioctl - Entry point for the Ioctl - * @dev: Device pointer. - * @rq: An IOCTL specefic structure, that can contain a pointer to - * a proprietary structure used to pass information to the driver. - * @cmd: IOCTL command - * Description: - * Currently it supports the phy_mii_ioctl(...) and HW time stamping. - */ -static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -{ - struct stmmac_priv *priv = netdev_priv (dev); - int ret = -EOPNOTSUPP; - - if (!netif_running(dev)) - return -EINVAL; - - switch (cmd) { - case SIOCGMIIPHY: - case SIOCGMIIREG: - case SIOCSMIIREG: - ret = phylink_mii_ioctl(priv->phylink, rq, cmd); - break; - case SIOCSHWTSTAMP: - ret = stmmac_hwtstamp_set(dev, rq); - break; - case SIOCGHWTSTAMP: - ret = stmmac_hwtstamp_get(dev, rq); - break; - default: - break; - } - - return ret; -} - -static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, - void *cb_priv) -{ - struct stmmac_priv *priv = cb_priv; - int ret = -EOPNOTSUPP; - - if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) - return ret; - - __stmmac_disable_all_queues(priv); - - switch (type) { - case TC_SETUP_CLSU32: - ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); - break; - case TC_SETUP_CLSFLOWER: - ret = stmmac_tc_setup_cls(priv, priv, type_data); - break; - default: - break; - } - - stmmac_enable_all_queues(priv); - return ret; -} - -static LIST_HEAD(stmmac_block_cb_list); - -static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, - void *type_data) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - - switch (type) { - case TC_SETUP_BLOCK: - return flow_block_cb_setup_simple(type_data, - &stmmac_block_cb_list, - stmmac_setup_tc_block_cb, - priv, priv, true); - case TC_SETUP_QDISC_CBS: - return stmmac_tc_setup_cbs(priv, priv, type_data); - case TC_SETUP_QDISC_TAPRIO: - return stmmac_tc_setup_taprio(priv, priv, type_data); - case TC_SETUP_QDISC_ETF: - return stmmac_tc_setup_etf(priv, priv, type_data); - default: - return -EOPNOTSUPP; - } -} - -static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, - struct net_device *sb_dev) -{ - int gso = skb_shinfo(skb)->gso_type; - - if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { - /* - * There is no way to determine the number of TSO/USO - * capable Queues. Let's use always the Queue 0 - * because if TSO/USO is supported then at least this - * one will be capable. - */ - return 0; - } - - return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; -} - -static int stmmac_set_mac_address(struct net_device *ndev, void *addr) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - int ret = 0; - - ret = pm_runtime_get_sync(priv->device); - if (ret < 0) { - pm_runtime_put_noidle(priv->device); - return ret; - } - - ret = eth_mac_addr(ndev, addr); - if (ret) - goto set_mac_error; - - stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); - -set_mac_error: - pm_runtime_put(priv->device); - - return ret; -} - -#ifdef CONFIG_DEBUG_FS -static struct dentry *stmmac_fs_dir; - -static void sysfs_display_ring(void *head, int size, int extend_desc, - struct seq_file *seq, dma_addr_t dma_phy_addr) -{ - int i; - struct dma_extended_desc *ep = (struct dma_extended_desc *)head; - struct dma_desc *p = (struct dma_desc *)head; - dma_addr_t dma_addr; - - for (i = 0; i < size; i++) { - if (extend_desc) { - dma_addr = dma_phy_addr + i * sizeof(*ep); - seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", - i, &dma_addr, - le32_to_cpu(ep->basic.des0), - le32_to_cpu(ep->basic.des1), - le32_to_cpu(ep->basic.des2), - le32_to_cpu(ep->basic.des3)); - ep++; - } else { - dma_addr = dma_phy_addr + i * sizeof(*p); - seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", - i, &dma_addr, - le32_to_cpu(p->des0), le32_to_cpu(p->des1), - le32_to_cpu(p->des2), le32_to_cpu(p->des3)); - p++; - } - seq_printf(seq, "\n"); - } -} - -static int stmmac_rings_status_show(struct seq_file *seq, void *v) -{ - struct net_device *dev = seq->private; - struct stmmac_priv *priv = netdev_priv(dev); - u32 rx_count = priv->plat->rx_queues_to_use; - u32 tx_count = priv->plat->tx_queues_to_use; - u32 queue; - - if ((dev->flags & IFF_UP) == 0) - return 0; - - for (queue = 0; queue < rx_count; queue++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - seq_printf(seq, "RX Queue %d:\n", queue); - - if (priv->extend_desc) { - seq_printf(seq, "Extended descriptor ring:\n"); - sysfs_display_ring((void *)rx_q->dma_erx, - priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy); - } else { - seq_printf(seq, "Descriptor ring:\n"); - sysfs_display_ring((void *)rx_q->dma_rx, - priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy); - } - } - - for (queue = 0; queue < tx_count; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - seq_printf(seq, "TX Queue %d:\n", queue); - - if (priv->extend_desc) { - seq_printf(seq, "Extended descriptor ring:\n"); - sysfs_display_ring((void *)tx_q->dma_etx, - priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy); - } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { - seq_printf(seq, "Descriptor ring:\n"); - sysfs_display_ring((void *)tx_q->dma_tx, - priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy); - } - } - - return 0; -} -DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); - -static int stmmac_dma_cap_show(struct seq_file *seq, void *v) -{ - struct net_device *dev = seq->private; - struct stmmac_priv *priv = netdev_priv(dev); - - if (!priv->hw_cap_support) { - seq_printf(seq, "DMA HW features not supported\n"); - return 0; - } - - seq_printf(seq, "==============================\n"); - seq_printf(seq, "\tDMA HW features\n"); - seq_printf(seq, "==============================\n"); - - seq_printf(seq, "\t10/100 Mbps: %s\n", - (priv->dma_cap.mbps_10_100) ? "Y" : "N"); - seq_printf(seq, "\t1000 Mbps: %s\n", - (priv->dma_cap.mbps_1000) ? "Y" : "N"); - seq_printf(seq, "\tHalf duplex: %s\n", - (priv->dma_cap.half_duplex) ? "Y" : "N"); - seq_printf(seq, "\tHash Filter: %s\n", - (priv->dma_cap.hash_filter) ? "Y" : "N"); - seq_printf(seq, "\tMultiple MAC address registers: %s\n", - (priv->dma_cap.multi_addr) ? "Y" : "N"); - seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", - (priv->dma_cap.pcs) ? "Y" : "N"); - seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", - (priv->dma_cap.sma_mdio) ? "Y" : "N"); - seq_printf(seq, "\tPMT Remote wake up: %s\n", - (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); - seq_printf(seq, "\tPMT Magic Frame: %s\n", - (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); - seq_printf(seq, "\tRMON module: %s\n", - (priv->dma_cap.rmon) ? "Y" : "N"); - seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", - (priv->dma_cap.time_stamp) ? "Y" : "N"); - seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", - (priv->dma_cap.atime_stamp) ? "Y" : "N"); - seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", - (priv->dma_cap.eee) ? "Y" : "N"); - seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); - seq_printf(seq, "\tChecksum Offload in TX: %s\n", - (priv->dma_cap.tx_coe) ? "Y" : "N"); - if (priv->synopsys_id >= DWMAC_CORE_4_00) { - seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", - (priv->dma_cap.rx_coe) ? "Y" : "N"); - } else { - seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", - (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); - seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", - (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); - } - seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", - (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); - seq_printf(seq, "\tNumber of Additional RX channel: %d\n", - priv->dma_cap.number_rx_channel); - seq_printf(seq, "\tNumber of Additional TX channel: %d\n", - priv->dma_cap.number_tx_channel); - seq_printf(seq, "\tNumber of Additional RX queues: %d\n", - priv->dma_cap.number_rx_queues); - seq_printf(seq, "\tNumber of Additional TX queues: %d\n", - priv->dma_cap.number_tx_queues); - seq_printf(seq, "\tEnhanced descriptors: %s\n", - (priv->dma_cap.enh_desc) ? "Y" : "N"); - seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); - seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); - seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); - seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); - seq_printf(seq, "\tNumber of PPS Outputs: %d\n", - priv->dma_cap.pps_out_num); - seq_printf(seq, "\tSafety Features: %s\n", - priv->dma_cap.asp ? "Y" : "N"); - seq_printf(seq, "\tFlexible RX Parser: %s\n", - priv->dma_cap.frpsel ? "Y" : "N"); - seq_printf(seq, "\tEnhanced Addressing: %d\n", - priv->dma_cap.addr64); - seq_printf(seq, "\tReceive Side Scaling: %s\n", - priv->dma_cap.rssen ? "Y" : "N"); - seq_printf(seq, "\tVLAN Hash Filtering: %s\n", - priv->dma_cap.vlhash ? "Y" : "N"); - seq_printf(seq, "\tSplit Header: %s\n", - priv->dma_cap.sphen ? "Y" : "N"); - seq_printf(seq, "\tVLAN TX Insertion: %s\n", - priv->dma_cap.vlins ? "Y" : "N"); - seq_printf(seq, "\tDouble VLAN: %s\n", - priv->dma_cap.dvlan ? "Y" : "N"); - seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", - priv->dma_cap.l3l4fnum); - seq_printf(seq, "\tARP Offloading: %s\n", - priv->dma_cap.arpoffsel ? "Y" : "N"); - seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", - priv->dma_cap.estsel ? "Y" : "N"); - seq_printf(seq, "\tFrame Preemption (FPE): %s\n", - priv->dma_cap.fpesel ? "Y" : "N"); - seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", - priv->dma_cap.tbssel ? "Y" : "N"); - return 0; -} -DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); - -/* Use network device events to rename debugfs file entries. - */ -static int stmmac_device_event(struct notifier_block *unused, - unsigned long event, void *ptr) -{ - struct net_device *dev = netdev_notifier_info_to_dev(ptr); - struct stmmac_priv *priv = netdev_priv(dev); - - if (dev->netdev_ops != &stmmac_netdev_ops) - goto done; - - switch (event) { - case NETDEV_CHANGENAME: - if (priv->dbgfs_dir) - priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, - priv->dbgfs_dir, - stmmac_fs_dir, - dev->name); - break; - } -done: - return NOTIFY_DONE; -} - -static struct notifier_block stmmac_notifier = { - .notifier_call = stmmac_device_event, -}; - -static void stmmac_init_fs(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - rtnl_lock(); - - /* Create per netdev entries */ - priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); - - /* Entry to report DMA RX/TX rings */ - debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, - &stmmac_rings_status_fops); - - /* Entry to report the DMA HW features */ - debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, - &stmmac_dma_cap_fops); - - rtnl_unlock(); -} - -static void stmmac_exit_fs(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - debugfs_remove_recursive(priv->dbgfs_dir); -} -#endif /* CONFIG_DEBUG_FS */ - -static u32 stmmac_vid_crc32_le(__le16 vid_le) -{ - unsigned char *data = (unsigned char *)&vid_le; - unsigned char data_byte = 0; - u32 crc = ~0x0; - u32 temp = 0; - int i, bits; - - bits = get_bitmask_order(VLAN_VID_MASK); - for (i = 0; i < bits; i++) { - if ((i % 8) == 0) - data_byte = data[i / 8]; - - temp = ((crc & 1) ^ data_byte) & 1; - crc >>= 1; - data_byte >>= 1; - - if (temp) - crc ^= 0xedb88320; - } - - return crc; -} - -static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) -{ - u32 crc, hash = 0; - __le16 pmatch = 0; - int count = 0; - u16 vid = 0; - - for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { - __le16 vid_le = cpu_to_le16(vid); - crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; - hash |= (1 << crc); - count++; - } - - if (!priv->dma_cap.vlhash) { - if (count > 2) /* VID = 0 always passes filter */ - return -EOPNOTSUPP; - - pmatch = cpu_to_le16(vid); - hash = 0; - } - - return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); -} - -static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - bool is_double = false; - int ret; - - if (be16_to_cpu(proto) == ETH_P_8021AD) - is_double = true; - - set_bit(vid, priv->active_vlans); - ret = stmmac_vlan_update(priv, is_double); - if (ret) { - clear_bit(vid, priv->active_vlans); - return ret; - } - - if (priv->hw->num_vlan) { - ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); - if (ret) - return ret; - } - - return 0; -} - -static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) -{ - struct stmmac_priv *priv = netdev_priv(ndev); - bool is_double = false; - int ret; - - ret = pm_runtime_get_sync(priv->device); - if (ret < 0) { - pm_runtime_put_noidle(priv->device); - return ret; - } - - if (be16_to_cpu(proto) == ETH_P_8021AD) - is_double = true; - - clear_bit(vid, priv->active_vlans); - - if (priv->hw->num_vlan) { - ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); - if (ret) - goto del_vlan_error; - } - - ret = stmmac_vlan_update(priv, is_double); - -del_vlan_error: - pm_runtime_put(priv->device); - - return ret; -} - -static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) -{ - struct stmmac_priv *priv = netdev_priv(dev); - - switch (bpf->command) { - case XDP_SETUP_PROG: - return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); -<<<<<<< -======= - case XDP_SETUP_XSK_POOL: - return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, - bpf->xsk.queue_id); ->>>>>>> - default: - return -EOPNOTSUPP; - } -} - -<<<<<<< -======= -static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, - struct xdp_frame **frames, u32 flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int cpu = smp_processor_id(); - struct netdev_queue *nq; - int i, nxmit = 0; - int queue; - - if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) - return -ENETDOWN; - - if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) - return -EINVAL; - - queue = stmmac_xdp_get_tx_queue(priv, cpu); - nq = netdev_get_tx_queue(priv->dev, queue); - - __netif_tx_lock(nq, cpu); - /* Avoids TX time-out as we are sharing with slow path */ - nq->trans_start = jiffies; - - for (i = 0; i < num_frames; i++) { - int res; - - res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); - if (res == STMMAC_XDP_CONSUMED) - break; - - nxmit++; - } - - if (flags & XDP_XMIT_FLUSH) { - stmmac_flush_tx_descriptors(priv, queue); - stmmac_tx_timer_arm(priv, queue); - } - - __netif_tx_unlock(nq); - - return nxmit; -} - -void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); - - stmmac_stop_rx_dma(priv, queue); - __free_dma_rx_desc_resources(priv, queue); -} - -void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - u32 buf_size; - int ret; - - ret = __alloc_dma_rx_desc_resources(priv, queue); - if (ret) { - netdev_err(priv->dev, "Failed to alloc RX desc.\n"); - return; - } - - ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL); - if (ret) { - __free_dma_rx_desc_resources(priv, queue); - netdev_err(priv->dev, "Failed to init RX desc.\n"); - return; - } - - stmmac_clear_rx_descriptors(priv, queue); - - stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - rx_q->dma_rx_phy, rx_q->queue_index); - - rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * - sizeof(struct dma_desc)); - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, - rx_q->rx_tail_addr, rx_q->queue_index); - - if (rx_q->xsk_pool && rx_q->buf_alloc_num) { - buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); - stmmac_set_dma_bfsize(priv, priv->ioaddr, - buf_size, - rx_q->queue_index); - } else { - stmmac_set_dma_bfsize(priv, priv->ioaddr, - priv->dma_buf_sz, - rx_q->queue_index); - } - - stmmac_start_rx_dma(priv, queue); - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); - spin_unlock_irqrestore(&ch->lock, flags); -} - -void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - - spin_lock_irqsave(&ch->lock, flags); - stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); - - stmmac_stop_tx_dma(priv, queue); - __free_dma_tx_desc_resources(priv, queue); -} - -void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) -{ - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - struct stmmac_channel *ch = &priv->channel[queue]; - unsigned long flags; - int ret; - - ret = __alloc_dma_tx_desc_resources(priv, queue); - if (ret) { - netdev_err(priv->dev, "Failed to alloc TX desc.\n"); - return; - } - - ret = __init_dma_tx_desc_rings(priv, queue); - if (ret) { - __free_dma_tx_desc_resources(priv, queue); - netdev_err(priv->dev, "Failed to init TX desc.\n"); - return; - } - - stmmac_clear_tx_descriptors(priv, queue); - - stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, - tx_q->dma_tx_phy, tx_q->queue_index); - - if (tx_q->tbs & STMMAC_TBS_AVAIL) - stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); - - tx_q->tx_tail_addr = tx_q->dma_tx_phy; - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, - tx_q->tx_tail_addr, tx_q->queue_index); - - stmmac_start_tx_dma(priv, queue); - - spin_lock_irqsave(&ch->lock, flags); - stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); - spin_unlock_irqrestore(&ch->lock, flags); -} - -int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) -{ - struct stmmac_priv *priv = netdev_priv(dev); - struct stmmac_rx_queue *rx_q; - struct stmmac_tx_queue *tx_q; - struct stmmac_channel *ch; - - if (test_bit(STMMAC_DOWN, &priv->state) || - !netif_carrier_ok(priv->dev)) - return -ENETDOWN; - - if (!stmmac_xdp_is_enabled(priv)) - return -ENXIO; - - if (queue >= priv->plat->rx_queues_to_use || - queue >= priv->plat->tx_queues_to_use) - return -EINVAL; - - rx_q = &priv->rx_queue[queue]; - tx_q = &priv->tx_queue[queue]; - ch = &priv->channel[queue]; - - if (!rx_q->xsk_pool && !tx_q->xsk_pool) - return -ENXIO; - - if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { - /* EQoS does not have per-DMA channel SW interrupt, - * so we schedule RX Napi straight-away. - */ - if (likely(napi_schedule_prep(&ch->rxtx_napi))) - __napi_schedule(&ch->rxtx_napi); - } - - return 0; -} - ->>>>>>> -static const struct net_device_ops stmmac_netdev_ops = { - .ndo_open = stmmac_open, - .ndo_start_xmit = stmmac_xmit, - .ndo_stop = stmmac_release, - .ndo_change_mtu = stmmac_change_mtu, - .ndo_fix_features = stmmac_fix_features, - .ndo_set_features = stmmac_set_features, - .ndo_set_rx_mode = stmmac_set_rx_mode, - .ndo_tx_timeout = stmmac_tx_timeout, - .ndo_eth_ioctl = stmmac_ioctl, - .ndo_setup_tc = stmmac_setup_tc, - .ndo_select_queue = stmmac_select_queue, -#ifdef CONFIG_NET_POLL_CONTROLLER - .ndo_poll_controller = stmmac_poll_controller, -#endif - .ndo_set_mac_address = stmmac_set_mac_address, - .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, - .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, - .ndo_bpf = stmmac_bpf, -<<<<<<< -======= - .ndo_xdp_xmit = stmmac_xdp_xmit, - .ndo_xsk_wakeup = stmmac_xsk_wakeup, ->>>>>>> -}; - -static void stmmac_reset_subtask(struct stmmac_priv *priv) -{ - if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) - return; - if (test_bit(STMMAC_DOWN, &priv->state)) - return; - - netdev_err(priv->dev, "Reset adapter.\n"); - - rtnl_lock(); - netif_trans_update(priv->dev); - while (test_and_set_bit(STMMAC_RESETING, &priv->state)) - usleep_range(1000, 2000); - - set_bit(STMMAC_DOWN, &priv->state); - dev_close(priv->dev); - dev_open(priv->dev, NULL); - clear_bit(STMMAC_DOWN, &priv->state); - clear_bit(STMMAC_RESETING, &priv->state); - rtnl_unlock(); -} - -static void stmmac_service_task(struct work_struct *work) -{ - struct stmmac_priv *priv = container_of(work, struct stmmac_priv, - service_task); - - stmmac_reset_subtask(priv); - clear_bit(STMMAC_SERVICE_SCHED, &priv->state); -} - -/** - * stmmac_hw_init - Init the MAC device - * @priv: driver private structure - * Description: this function is to configure the MAC device according to - * some platform parameters or the HW capability register. It prepares the - * driver to use either ring or chain modes and to setup either enhanced or - * normal descriptors. - */ -static int stmmac_hw_init(struct stmmac_priv *priv) -{ - int ret; - - /* dwmac-sun8i only work in chain mode */ - if (priv->plat->has_sun8i) - chain_mode = 1; - priv->chain_mode = chain_mode; - - /* Initialize HW Interface */ - ret = stmmac_hwif_init(priv); - if (ret) - return ret; - - /* Get the HW capability (new GMAC newer than 3.50a) */ - priv->hw_cap_support = stmmac_get_hw_features(priv); - if (priv->hw_cap_support) { - dev_info(priv->device, "DMA HW capability register supported\n"); - - /* We can override some gmac/dma configuration fields: e.g. - * enh_desc, tx_coe (e.g. that are passed through the - * platform) with the values from the HW capability - * register (if supported). - */ - priv->plat->enh_desc = priv->dma_cap.enh_desc; - priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && - !priv->plat->use_phy_wol; - priv->hw->pmt = priv->plat->pmt; - if (priv->dma_cap.hash_tb_sz) { - priv->hw->multicast_filter_bins = - (BIT(priv->dma_cap.hash_tb_sz) << 5); - priv->hw->mcast_bits_log2 = - ilog2(priv->hw->multicast_filter_bins); - } - - /* TXCOE doesn't work in thresh DMA mode */ - if (priv->plat->force_thresh_dma_mode) - priv->plat->tx_coe = 0; - else - priv->plat->tx_coe = priv->dma_cap.tx_coe; - - /* In case of GMAC4 rx_coe is from HW cap register. */ - priv->plat->rx_coe = priv->dma_cap.rx_coe; - - if (priv->dma_cap.rx_coe_type2) - priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; - else if (priv->dma_cap.rx_coe_type1) - priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; - - } else { - dev_info(priv->device, "No HW DMA feature register supported\n"); - } - - if (priv->plat->rx_coe) { - priv->hw->rx_csum = priv->plat->rx_coe; - dev_info(priv->device, "RX Checksum Offload Engine supported\n"); - if (priv->synopsys_id < DWMAC_CORE_4_00) - dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); - } - if (priv->plat->tx_coe) - dev_info(priv->device, "TX Checksum insertion supported\n"); - - if (priv->plat->pmt) { - dev_info(priv->device, "Wake-Up On Lan supported\n"); - device_set_wakeup_capable(priv->device, 1); - } - - if (priv->dma_cap.tsoen) - dev_info(priv->device, "TSO supported\n"); - - priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; - priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; - - /* Run HW quirks, if any */ - if (priv->hwif_quirks) { - ret = priv->hwif_quirks(priv); - if (ret) - return ret; - } - - /* Rx Watchdog is available in the COREs newer than the 3.40. - * In some case, for example on bugged HW this feature - * has to be disable and this can be done by passing the - * riwt_off field from the platform. - */ - if (((priv->synopsys_id >= DWMAC_CORE_3_50) || - (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { - priv->use_riwt = 1; - dev_info(priv->device, - "Enable RX Mitigation via HW Watchdog Timer\n"); - } - - return 0; -} - -static void stmmac_napi_add(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 queue, maxq; - - maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - ch->priv_data = priv; - ch->index = queue; - spin_lock_init(&ch->lock); - - if (queue < priv->plat->rx_queues_to_use) { - netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, - NAPI_POLL_WEIGHT); - } - if (queue < priv->plat->tx_queues_to_use) { - netif_tx_napi_add(dev, &ch->tx_napi, - stmmac_napi_poll_tx, - NAPI_POLL_WEIGHT); - } - if (queue < priv->plat->rx_queues_to_use && - queue < priv->plat->tx_queues_to_use) { - netif_napi_add(dev, &ch->rxtx_napi, - stmmac_napi_poll_rxtx, - NAPI_POLL_WEIGHT); - } - } -} - -static void stmmac_napi_del(struct net_device *dev) -{ - struct stmmac_priv *priv = netdev_priv(dev); - u32 queue, maxq; - - maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); - - for (queue = 0; queue < maxq; queue++) { - struct stmmac_channel *ch = &priv->channel[queue]; - - if (queue < priv->plat->rx_queues_to_use) - netif_napi_del(&ch->rx_napi); - if (queue < priv->plat->tx_queues_to_use) - netif_napi_del(&ch->tx_napi); - if (queue < priv->plat->rx_queues_to_use && - queue < priv->plat->tx_queues_to_use) { - netif_napi_del(&ch->rxtx_napi); - } - } -} - -int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret = 0; - - if (netif_running(dev)) - stmmac_release(dev); - - stmmac_napi_del(dev); - - priv->plat->rx_queues_to_use = rx_cnt; - priv->plat->tx_queues_to_use = tx_cnt; - - stmmac_napi_add(dev); - - if (netif_running(dev)) - ret = stmmac_open(dev); - - return ret; -} - -int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) -{ - struct stmmac_priv *priv = netdev_priv(dev); - int ret = 0; - - if (netif_running(dev)) - stmmac_release(dev); - - priv->dma_rx_size = rx_size; - priv->dma_tx_size = tx_size; - - if (netif_running(dev)) - ret = stmmac_open(dev); - - return ret; -} - -#define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" -static void stmmac_fpe_lp_task(struct work_struct *work) -{ - struct stmmac_priv *priv = container_of(work, struct stmmac_priv, - fpe_task); - struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; - enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; - enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; - bool *hs_enable = &fpe_cfg->hs_enable; - bool *enable = &fpe_cfg->enable; - int retries = 20; - - while (retries-- > 0) { - /* Bail out immediately if FPE handshake is OFF */ - if (*lo_state == FPE_STATE_OFF || !*hs_enable) - break; - - if (*lo_state == FPE_STATE_ENTERING_ON && - *lp_state == FPE_STATE_ENTERING_ON) { - stmmac_fpe_configure(priv, priv->ioaddr, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, - *enable); - - netdev_info(priv->dev, "configured FPE\n"); - - *lo_state = FPE_STATE_ON; - *lp_state = FPE_STATE_ON; - netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); - break; - } - - if ((*lo_state == FPE_STATE_CAPABLE || - *lo_state == FPE_STATE_ENTERING_ON) && - *lp_state != FPE_STATE_ON) { - netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, - *lo_state, *lp_state); - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - MPACKET_VERIFY); - } - /* Sleep then retry */ - msleep(500); - } - - clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); -} - -void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) -{ - if (priv->plat->fpe_cfg->hs_enable != enable) { - if (enable) { - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - MPACKET_VERIFY); - } else { - priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; - priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; - } - - priv->plat->fpe_cfg->hs_enable = enable; - } -} - -/** - * stmmac_dvr_probe - * @device: device pointer - * @plat_dat: platform data pointer - * @res: stmmac resource pointer - * Description: this is the main probe function used to - * call the alloc_etherdev, allocate the priv structure. - * Return: - * returns 0 on success, otherwise errno. - */ -int stmmac_dvr_probe(struct device *device, - struct plat_stmmacenet_data *plat_dat, - struct stmmac_resources *res) -{ - struct net_device *ndev = NULL; - struct stmmac_priv *priv; - u32 rxq; - int i, ret = 0; - - ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), - MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); - if (!ndev) - return -ENOMEM; - - SET_NETDEV_DEV(ndev, device); - - priv = netdev_priv(ndev); - priv->device = device; - priv->dev = ndev; - - stmmac_set_ethtool_ops(ndev); - priv->pause = pause; - priv->plat = plat_dat; - priv->ioaddr = res->addr; - priv->dev->base_addr = (unsigned long)res->addr; - priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; - - priv->dev->irq = res->irq; - priv->wol_irq = res->wol_irq; - priv->lpi_irq = res->lpi_irq; - priv->sfty_ce_irq = res->sfty_ce_irq; - priv->sfty_ue_irq = res->sfty_ue_irq; - for (i = 0; i < MTL_MAX_RX_QUEUES; i++) - priv->rx_irq[i] = res->rx_irq[i]; - for (i = 0; i < MTL_MAX_TX_QUEUES; i++) - priv->tx_irq[i] = res->tx_irq[i]; - - if (!is_zero_ether_addr(res->mac)) - eth_hw_addr_set(priv->dev, res->mac); - - dev_set_drvdata(device, priv->dev); - - /* Verify driver arguments */ - stmmac_verify_args(); - - priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); - if (!priv->af_xdp_zc_qps) - return -ENOMEM; - - /* Allocate workqueue */ - priv->wq = create_singlethread_workqueue("stmmac_wq"); - if (!priv->wq) { - dev_err(priv->device, "failed to create workqueue\n"); - return -ENOMEM; - } - - INIT_WORK(&priv->service_task, stmmac_service_task); - - /* Initialize Link Partner FPE workqueue */ - INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); - - /* Override with kernel parameters if supplied XXX CRS XXX - * this needs to have multiple instances - */ - if ((phyaddr >= 0) && (phyaddr <= 31)) - priv->plat->phy_addr = phyaddr; - - if (priv->plat->stmmac_rst) { - ret = reset_control_assert(priv->plat->stmmac_rst); - reset_control_deassert(priv->plat->stmmac_rst); - /* Some reset controllers have only reset callback instead of - * assert + deassert callbacks pair. - */ - if (ret == -ENOTSUPP) - reset_control_reset(priv->plat->stmmac_rst); - } - - ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); - if (ret == -ENOTSUPP) - dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", - ERR_PTR(ret)); - - /* Init MAC and get the capabilities */ - ret = stmmac_hw_init(priv); - if (ret) - goto error_hw_init; - - /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. - */ - if (priv->synopsys_id < DWMAC_CORE_5_20) - priv->plat->dma_cfg->dche = false; - - stmmac_check_ether_addr(priv); - - ndev->netdev_ops = &stmmac_netdev_ops; - - ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | - NETIF_F_RXCSUM; - - ret = stmmac_tc_init(priv, priv); - if (!ret) { - ndev->hw_features |= NETIF_F_HW_TC; - } - - if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { - ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; - if (priv->plat->has_gmac4) - ndev->hw_features |= NETIF_F_GSO_UDP_L4; - priv->tso = true; - dev_info(priv->device, "TSO feature enabled\n"); - } - - if (priv->dma_cap.sphen) { - ndev->hw_features |= NETIF_F_GRO; - priv->sph_cap = true; - priv->sph = priv->sph_cap; - dev_info(priv->device, "SPH feature enabled\n"); - } - - /* The current IP register MAC_HW_Feature1[ADDR64] only define - * 32/40/64 bit width, but some SOC support others like i.MX8MP - * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. - * So overwrite dma_cap.addr64 according to HW real design. - */ - if (priv->plat->addr64) - priv->dma_cap.addr64 = priv->plat->addr64; - - if (priv->dma_cap.addr64) { - ret = dma_set_mask_and_coherent(device, - DMA_BIT_MASK(priv->dma_cap.addr64)); - if (!ret) { - dev_info(priv->device, "Using %d bits DMA width\n", - priv->dma_cap.addr64); - - /* - * If more than 32 bits can be addressed, make sure to - * enable enhanced addressing mode. - */ - if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) - priv->plat->dma_cfg->eame = true; - } else { - ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); - if (ret) { - dev_err(priv->device, "Failed to set DMA Mask\n"); - goto error_hw_init; - } - - priv->dma_cap.addr64 = 32; - } - } - - ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; - ndev->watchdog_timeo = msecs_to_jiffies(watchdog); -#ifdef STMMAC_VLAN_TAG_USED - /* Both mac100 and gmac support receive VLAN tag detection */ - ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; - if (priv->dma_cap.vlhash) { - ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; - ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; - } - if (priv->dma_cap.vlins) { - ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; - if (priv->dma_cap.dvlan) - ndev->features |= NETIF_F_HW_VLAN_STAG_TX; - } -#endif - priv->msg_enable = netif_msg_init(debug, default_msg_level); - - /* Initialize RSS */ - rxq = priv->plat->rx_queues_to_use; - netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); - for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) - priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); - - if (priv->dma_cap.rssen && priv->plat->rss_en) - ndev->features |= NETIF_F_RXHASH; - - /* MTU range: 46 - hw-specific max */ - ndev->min_mtu = ETH_ZLEN - ETH_HLEN; - if (priv->plat->has_xgmac) - ndev->max_mtu = XGMAC_JUMBO_LEN; - else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) - ndev->max_mtu = JUMBO_LEN; - else - ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); - /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu - * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. - */ - if ((priv->plat->maxmtu < ndev->max_mtu) && - (priv->plat->maxmtu >= ndev->min_mtu)) - ndev->max_mtu = priv->plat->maxmtu; - else if (priv->plat->maxmtu < ndev->min_mtu) - dev_warn(priv->device, - "%s: warning: maxmtu having invalid value (%d)\n", - __func__, priv->plat->maxmtu); - - if (flow_ctrl) - priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ - - /* Setup channels NAPI */ - stmmac_napi_add(ndev); - - mutex_init(&priv->lock); - - /* If a specific clk_csr value is passed from the platform - * this means that the CSR Clock Range selection cannot be - * changed at run-time and it is fixed. Viceversa the driver'll try to - * set the MDC clock dynamically according to the csr actual - * clock input. - */ - if (priv->plat->clk_csr >= 0) - priv->clk_csr = priv->plat->clk_csr; - else - stmmac_clk_csr_set(priv); - - stmmac_check_pcs_mode(priv); - - pm_runtime_get_noresume(device); - pm_runtime_set_active(device); - if (!pm_runtime_enabled(device)) - pm_runtime_enable(device); - - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI) { - /* MDIO bus Registration */ - ret = stmmac_mdio_register(ndev); - if (ret < 0) { - dev_err(priv->device, - "%s: MDIO bus (id: %d) registration failed", - __func__, priv->plat->bus_id); - goto error_mdio_register; - } - } - - if (priv->plat->speed_mode_2500) - priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); - - if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { - ret = stmmac_xpcs_setup(priv->mii); - if (ret) - goto error_xpcs_setup; - } - - ret = stmmac_phy_setup(priv); - if (ret) { - netdev_err(ndev, "failed to setup phy (%d)\n", ret); - goto error_phy_setup; - } - - ret = register_netdev(ndev); - if (ret) { - dev_err(priv->device, "%s: ERROR %i registering the device\n", - __func__, ret); - goto error_netdev_register; - } - - if (priv->plat->serdes_powerup) { - ret = priv->plat->serdes_powerup(ndev, - priv->plat->bsp_priv); - - if (ret < 0) - goto error_serdes_powerup; - } - -#ifdef CONFIG_DEBUG_FS - stmmac_init_fs(ndev); -#endif - - if (priv->plat->dump_debug_regs) - priv->plat->dump_debug_regs(priv->plat->bsp_priv); - - /* Let pm_runtime_put() disable the clocks. - * If CONFIG_PM is not enabled, the clocks will stay powered. - */ - pm_runtime_put(device); - - return ret; - -error_serdes_powerup: - unregister_netdev(ndev); -error_netdev_register: - phylink_destroy(priv->phylink); -error_xpcs_setup: -error_phy_setup: - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI) - stmmac_mdio_unregister(ndev); -error_mdio_register: - stmmac_napi_del(ndev); -error_hw_init: - destroy_workqueue(priv->wq); - bitmap_free(priv->af_xdp_zc_qps); - - return ret; -} -EXPORT_SYMBOL_GPL(stmmac_dvr_probe); - -/** - * stmmac_dvr_remove - * @dev: device pointer - * Description: this function resets the TX/RX processes, disables the MAC RX/TX - * changes the link status, releases the DMA descriptor rings. - */ -int stmmac_dvr_remove(struct device *dev) -{ - struct net_device *ndev = dev_get_drvdata(dev); - struct stmmac_priv *priv = netdev_priv(ndev); - - netdev_info(priv->dev, "%s: removing driver", __func__); - - stmmac_stop_all_dma(priv); - stmmac_mac_set(priv, priv->ioaddr, false); - netif_carrier_off(ndev); - unregister_netdev(ndev); - - /* Serdes power down needs to happen after VLAN filter - * is deleted that is triggered by unregister_netdev(). - */ - if (priv->plat->serdes_powerdown) - priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); - -#ifdef CONFIG_DEBUG_FS - stmmac_exit_fs(ndev); -#endif - phylink_destroy(priv->phylink); - if (priv->plat->stmmac_rst) - reset_control_assert(priv->plat->stmmac_rst); - reset_control_assert(priv->plat->stmmac_ahb_rst); - pm_runtime_put(dev); - pm_runtime_disable(dev); - if (priv->hw->pcs != STMMAC_PCS_TBI && - priv->hw->pcs != STMMAC_PCS_RTBI) - stmmac_mdio_unregister(ndev); - destroy_workqueue(priv->wq); - mutex_destroy(&priv->lock); - bitmap_free(priv->af_xdp_zc_qps); - - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_dvr_remove); - -/** - * stmmac_suspend - suspend callback - * @dev: device pointer - * Description: this is the function to suspend the device and it is called - * by the platform driver to stop the network queue, release the resources, - * program the PMT register (for WoL), clean and release driver resources. - */ -int stmmac_suspend(struct device *dev) -{ - struct net_device *ndev = dev_get_drvdata(dev); - struct stmmac_priv *priv = netdev_priv(ndev); - u32 chan; - - if (!ndev || !netif_running(ndev)) - return 0; - - mutex_lock(&priv->lock); - - netif_device_detach(ndev); - - stmmac_disable_all_queues(priv); - - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) - hrtimer_cancel(&priv->tx_queue[chan].txtimer); - - if (priv->eee_enabled) { - priv->tx_path_in_lpi_mode = false; - del_timer_sync(&priv->eee_ctrl_timer); - } - - /* Stop TX/RX DMA */ - stmmac_stop_all_dma(priv); - - if (priv->plat->serdes_powerdown) - priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); - - /* Enable Power down mode by programming the PMT regs */ - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - stmmac_pmt(priv, priv->hw, priv->wolopts); - priv->irq_wake = 1; - } else { - stmmac_mac_set(priv, priv->ioaddr, false); - pinctrl_pm_select_sleep_state(priv->device); - } - - mutex_unlock(&priv->lock); - - rtnl_lock(); - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - phylink_suspend(priv->phylink, true); - } else { - if (device_may_wakeup(priv->device)) - phylink_speed_down(priv->phylink, false); - phylink_suspend(priv->phylink, false); - } - rtnl_unlock(); - - if (priv->dma_cap.fpesel) { - /* Disable FPE */ - stmmac_fpe_configure(priv, priv->ioaddr, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, false); - - stmmac_fpe_handshake(priv, false); - stmmac_fpe_stop_wq(priv); - } - - priv->speed = SPEED_UNKNOWN; - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_suspend); - -/** - * stmmac_reset_queues_param - reset queue parameters - * @priv: device pointer - */ -static void stmmac_reset_queues_param(struct stmmac_priv *priv) -{ - u32 rx_cnt = priv->plat->rx_queues_to_use; - u32 tx_cnt = priv->plat->tx_queues_to_use; - u32 queue; - - for (queue = 0; queue < rx_cnt; queue++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - rx_q->cur_rx = 0; - rx_q->dirty_rx = 0; - } - - for (queue = 0; queue < tx_cnt; queue++) { - struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; - - tx_q->cur_tx = 0; - tx_q->dirty_tx = 0; - tx_q->mss = 0; - - netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); - } -} - -/** - * stmmac_resume - resume callback - * @dev: device pointer - * Description: when resume this function is invoked to setup the DMA and CORE - * in a usable state. - */ -int stmmac_resume(struct device *dev) -{ - struct net_device *ndev = dev_get_drvdata(dev); - struct stmmac_priv *priv = netdev_priv(ndev); - int ret; - - if (!netif_running(ndev)) - return 0; - - /* Power Down bit, into the PM register, is cleared - * automatically as soon as a magic packet or a Wake-up frame - * is received. Anyway, it's better to manually clear - * this bit because it can generate problems while resuming - * from another devices (e.g. serial console). - */ - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - mutex_lock(&priv->lock); - stmmac_pmt(priv, priv->hw, 0); - mutex_unlock(&priv->lock); - priv->irq_wake = 0; - } else { - pinctrl_pm_select_default_state(priv->device); - /* reset the phy so that it's ready */ - if (priv->mii) - stmmac_mdio_reset(priv->mii); - } - - if (priv->plat->serdes_powerup) { - ret = priv->plat->serdes_powerup(ndev, - priv->plat->bsp_priv); - - if (ret < 0) - return ret; - } - - rtnl_lock(); - if (device_may_wakeup(priv->device) && priv->plat->pmt) { - phylink_resume(priv->phylink); - } else { - phylink_resume(priv->phylink); - if (device_may_wakeup(priv->device)) - phylink_speed_up(priv->phylink); - } - rtnl_unlock(); - - rtnl_lock(); - mutex_lock(&priv->lock); - - stmmac_reset_queues_param(priv); - - stmmac_free_tx_skbufs(priv); - stmmac_clear_descriptors(priv); - - stmmac_hw_setup(ndev, false); - stmmac_init_coalesce(priv); - stmmac_set_rx_mode(ndev); - - stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); - - stmmac_enable_all_queues(priv); - - mutex_unlock(&priv->lock); - rtnl_unlock(); - - netif_device_attach(ndev); - - return 0; -} -EXPORT_SYMBOL_GPL(stmmac_resume); - -#ifndef MODULE -static int __init stmmac_cmdline_opt(char *str) -{ - char *opt; - - if (!str || !*str) - return -EINVAL; - while ((opt = strsep(&str, ",")) != NULL) { - if (!strncmp(opt, "debug:", 6)) { - if (kstrtoint(opt + 6, 0, &debug)) - goto err; - } else if (!strncmp(opt, "phyaddr:", 8)) { - if (kstrtoint(opt + 8, 0, &phyaddr)) - goto err; - } else if (!strncmp(opt, "buf_sz:", 7)) { - if (kstrtoint(opt + 7, 0, &buf_sz)) - goto err; - } else if (!strncmp(opt, "tc:", 3)) { - if (kstrtoint(opt + 3, 0, &tc)) - goto err; - } else if (!strncmp(opt, "watchdog:", 9)) { - if (kstrtoint(opt + 9, 0, &watchdog)) - goto err; - } else if (!strncmp(opt, "flow_ctrl:", 10)) { - if (kstrtoint(opt + 10, 0, &flow_ctrl)) - goto err; - } else if (!strncmp(opt, "pause:", 6)) { - if (kstrtoint(opt + 6, 0, &pause)) - goto err; - } else if (!strncmp(opt, "eee_timer:", 10)) { - if (kstrtoint(opt + 10, 0, &eee_timer)) - goto err; - } else if (!strncmp(opt, "chain_mode:", 11)) { - if (kstrtoint(opt + 11, 0, &chain_mode)) - goto err; - } - } - return 0; - -err: - pr_err("%s: ERROR broken module parameter conversion", __func__); - return -EINVAL; -} - -__setup("stmmaceth=", stmmac_cmdline_opt); -#endif /* MODULE */ - -static int __init stmmac_init(void) -{ -#ifdef CONFIG_DEBUG_FS - /* Create debugfs main directory if it doesn't exist yet */ - if (!stmmac_fs_dir) - stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); - register_netdevice_notifier(&stmmac_notifier); -#endif - - return 0; -} - -static void __exit stmmac_exit(void) -{ -#ifdef CONFIG_DEBUG_FS - unregister_netdevice_notifier(&stmmac_notifier); - debugfs_remove_recursive(stmmac_fs_dir); -#endif -} - -module_init(stmmac_init) -module_exit(stmmac_exit) - -MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); -MODULE_AUTHOR("Giuseppe Cavallaro "); -MODULE_LICENSE("GPL"); diff --git a/rr-cache/c93aa1d88b83814abde67e32f1f814fc35cb0efd/preimage b/rr-cache/c93aa1d88b83814abde67e32f1f814fc35cb0efd/preimage deleted file mode 100644 index 1f5de87..0000000 --- a/rr-cache/c93aa1d88b83814abde67e32f1f814fc35cb0efd/preimage +++ /dev/null @@ -1,534 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2021, Linaro Ltd. - * - */ - -#ifndef _MHI_COMMON_H -#define _MHI_COMMON_H - -#include - -<<<<<<< -/* MHI register bits */ -#define MHIREGLEN_MHIREGLEN_MASK GENMASK(31, 0) -#define MHIREGLEN_MHIREGLEN_SHIFT 0 - -#define MHIVER_MHIVER_MASK GENMASK(31, 0) -#define MHIVER_MHIVER_SHIFT 0 - -#define MHICFG_NHWER_MASK GENMASK(31, 24) -#define MHICFG_NHWER_SHIFT 24 -#define MHICFG_NER_MASK GENMASK(23, 16) -#define MHICFG_NER_SHIFT 16 -#define MHICFG_NHWCH_MASK GENMASK(15, 8) -#define MHICFG_NHWCH_SHIFT 8 -#define MHICFG_NCH_MASK GENMASK(7, 0) -#define MHICFG_NCH_SHIFT 0 - -#define CHDBOFF_CHDBOFF_MASK GENMASK(31, 0) -#define CHDBOFF_CHDBOFF_SHIFT 0 - -#define ERDBOFF_ERDBOFF_MASK GENMASK(31, 0) -#define ERDBOFF_ERDBOFF_SHIFT 0 - -#define BHIOFF_BHIOFF_MASK GENMASK(31, 0) -#define BHIOFF_BHIOFF_SHIFT 0 - -#define BHIEOFF_BHIEOFF_MASK GENMASK(31, 0) -#define BHIEOFF_BHIEOFF_SHIFT 0 - -#define DEBUGOFF_DEBUGOFF_MASK GENMASK(31, 0) -#define DEBUGOFF_DEBUGOFF_SHIFT 0 - -#define MHICTRL_MHISTATE_MASK GENMASK(15, 8) -#define MHICTRL_MHISTATE_SHIFT 8 -#define MHICTRL_RESET_MASK 2 -#define MHICTRL_RESET_SHIFT 1 - -#define MHISTATUS_MHISTATE_MASK GENMASK(15, 8) -#define MHISTATUS_MHISTATE_SHIFT 8 -#define MHISTATUS_SYSERR_MASK 4 -#define MHISTATUS_SYSERR_SHIFT 2 -#define MHISTATUS_READY_MASK 1 -#define MHISTATUS_READY_SHIFT 0 - -#define CCABAP_LOWER_CCABAP_LOWER_MASK GENMASK(31, 0) -#define CCABAP_LOWER_CCABAP_LOWER_SHIFT 0 - -#define CCABAP_HIGHER_CCABAP_HIGHER_MASK GENMASK(31, 0) -#define CCABAP_HIGHER_CCABAP_HIGHER_SHIFT 0 - -#define ECABAP_LOWER_ECABAP_LOWER_MASK GENMASK(31, 0) -#define ECABAP_LOWER_ECABAP_LOWER_SHIFT 0 - -#define ECABAP_HIGHER_ECABAP_HIGHER_MASK GENMASK(31, 0) -#define ECABAP_HIGHER_ECABAP_HIGHER_SHIFT 0 - -#define CRCBAP_LOWER_CRCBAP_LOWER_MASK GENMASK(31, 0) -#define CRCBAP_LOWER_CRCBAP_LOWER_SHIFT 0 - -#define CRCBAP_HIGHER_CRCBAP_HIGHER_MASK GENMASK(31, 0) -#define CRCBAP_HIGHER_CRCBAP_HIGHER_SHIFT 0 - -#define CRDB_LOWER_CRDB_LOWER_MASK GENMASK(31, 0) -#define CRDB_LOWER_CRDB_LOWER_SHIFT 0 - -#define CRDB_HIGHER_CRDB_HIGHER_MASK GENMASK(31, 0) -#define CRDB_HIGHER_CRDB_HIGHER_SHIFT 0 - -#define MHICTRLBASE_LOWER_MHICTRLBASE_LOWER_MASK GENMASK(31, 0) -#define MHICTRLBASE_LOWER_MHICTRLBASE_LOWER_SHIFT 0 - -#define MHICTRLBASE_HIGHER_MHICTRLBASE_HIGHER_MASK GENMASK(31, 0) -#define MHICTRLBASE_HIGHER_MHICTRLBASE_HIGHER_SHIFT 0 - -#define MHICTRLLIMIT_LOWER_MHICTRLLIMIT_LOWER_MASK GENMASK(31, 0) -#define MHICTRLLIMIT_LOWER_MHICTRLLIMIT_LOWER_SHIFT 0 - -#define MHICTRLLIMIT_HIGHER_MHICTRLLIMIT_HIGHER_MASK GENMASK(31, 0) -#define MHICTRLLIMIT_HIGHER_MHICTRLLIMIT_HIGHER_SHIFT 0 - -#define MHIDATABASE_LOWER_MHIDATABASE_LOWER_MASK GENMASK(31, 0) -#define MHIDATABASE_LOWER_MHIDATABASE_LOWER_SHIFT 0 - -#define MHIDATABASE_HIGHER_MHIDATABASE_HIGHER_MASK GENMASK(31, 0) -#define MHIDATABASE_HIGHER_MHIDATABASE_HIGHER_SHIFT 0 - -#define MHIDATALIMIT_LOWER_MHIDATALIMIT_LOWER_MASK GENMASK(31, 0) -#define MHIDATALIMIT_LOWER_MHIDATALIMIT_LOWER_SHIFT 0 - -#define MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_MASK GENMASK(31, 0) -#define MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_SHIFT 0 - -/* Command Ring Element macros */ -/* No operation command */ -#define MHI_TRE_CMD_NOOP_PTR 0 -#define MHI_TRE_CMD_NOOP_DWORD0 0 -#define MHI_TRE_CMD_NOOP_DWORD1 (MHI_CMD_NOP << 16) - -/* Channel reset command */ -#define MHI_TRE_CMD_RESET_PTR 0 -#define MHI_TRE_CMD_RESET_DWORD0 0 -#define MHI_TRE_CMD_RESET_DWORD1(chid) ((chid << 24) | \ - (MHI_CMD_RESET_CHAN << 16)) - -/* Channel stop command */ -#define MHI_TRE_CMD_STOP_PTR 0 -#define MHI_TRE_CMD_STOP_DWORD0 0 -#define MHI_TRE_CMD_STOP_DWORD1(chid) ((chid << 24) | \ - (MHI_CMD_STOP_CHAN << 16)) - -/* Channel start command */ -#define MHI_TRE_CMD_START_PTR 0 -#define MHI_TRE_CMD_START_DWORD0 0 -#define MHI_TRE_CMD_START_DWORD1(chid) ((chid << 24) | \ - (MHI_CMD_START_CHAN << 16)) - -#define MHI_TRE_GET_CMD_CHID(tre) (((tre)->dword[1] >> 24) & 0xff) -#define MHI_TRE_GET_CMD_TYPE(tre) (((tre)->dword[1] >> 16) & 0xff) - -/* Event descriptor macros */ -/* Transfer completion event */ -#define MHI_TRE_EV_PTR(ptr) (ptr) -#define MHI_TRE_EV_DWORD0(code, len) ((code << 24) | len) -#define MHI_TRE_EV_DWORD1(chid, type) ((chid << 24) | (type << 16)) -#define MHI_TRE_GET_EV_PTR(tre) ((tre)->ptr) -#define MHI_TRE_GET_EV_CODE(tre) (((tre)->dword[0] >> 24) & 0xff) -#define MHI_TRE_GET_EV_LEN(tre) ((tre)->dword[0] & 0xffff) -#define MHI_TRE_GET_EV_CHID(tre) (((tre)->dword[1] >> 24) & 0xff) -#define MHI_TRE_GET_EV_TYPE(tre) (((tre)->dword[1] >> 16) & 0xff) -#define MHI_TRE_GET_EV_STATE(tre) (((tre)->dword[0] >> 24) & 0xff) -#define MHI_TRE_GET_EV_EXECENV(tre) (((tre)->dword[0] >> 24) & 0xff) -#define MHI_TRE_GET_EV_SEQ(tre) ((tre)->dword[0]) -#define MHI_TRE_GET_EV_TIME(tre) ((tre)->ptr) -#define MHI_TRE_GET_EV_COOKIE(tre) lower_32_bits((tre)->ptr) -#define MHI_TRE_GET_EV_VEID(tre) (((tre)->dword[0] >> 16) & 0xff) -#define MHI_TRE_GET_EV_LINKSPEED(tre) (((tre)->dword[1] >> 24) & 0xff) -#define MHI_TRE_GET_EV_LINKWIDTH(tre) ((tre)->dword[0] & 0xff) - -/* State change event */ -#define MHI_SC_EV_PTR 0 -#define MHI_SC_EV_DWORD0(state) (state << 24) -#define MHI_SC_EV_DWORD1(type) (type << 16) - -/* EE event */ -#define MHI_EE_EV_PTR 0 -#define MHI_EE_EV_DWORD0(ee) (ee << 24) -#define MHI_EE_EV_DWORD1(type) (type << 16) - -/* Command Completion event */ -#define MHI_CC_EV_PTR(ptr) (ptr) -#define MHI_CC_EV_DWORD0(code) (code << 24) -#define MHI_CC_EV_DWORD1(type) (type << 16) - -/* Transfer descriptor macros */ -#define MHI_TRE_DATA_PTR(ptr) (ptr) -#define MHI_TRE_DATA_DWORD0(len) (len & MHI_MAX_MTU) -#define MHI_TRE_DATA_DWORD1(bei, ieot, ieob, chain) ((2 << 16) | (bei << 10) \ - | (ieot << 9) | (ieob << 8) | chain) - -/* RSC transfer descriptor macros */ -#define MHI_RSCTRE_DATA_PTR(ptr, len) (((u64)len << 48) | ptr) -#define MHI_RSCTRE_DATA_DWORD0(cookie) (cookie) -#define MHI_RSCTRE_DATA_DWORD1 (MHI_PKT_TYPE_COALESCING << 16) -======= -/* MHI registers */ -#define REG_MHIREGLEN 0x00 -#define REG_MHIVER 0x08 -#define REG_MHICFG 0x10 -#define REG_CHDBOFF 0x18 -#define REG_ERDBOFF 0x20 -#define REG_BHIOFF 0x28 -#define REG_BHIEOFF 0x2c -#define REG_DEBUGOFF 0x30 -#define REG_MHICTRL 0x38 -#define REG_MHISTATUS 0x48 -#define REG_CCABAP_LOWER 0x58 -#define REG_CCABAP_HIGHER 0x5c -#define REG_ECABAP_LOWER 0x60 -#define REG_ECABAP_HIGHER 0x64 -#define REG_CRCBAP_LOWER 0x68 -#define REG_CRCBAP_HIGHER 0x6c -#define REG_CRDB_LOWER 0x70 -#define REG_CRDB_HIGHER 0x74 -#define REG_MHICTRLBASE_LOWER 0x80 -#define REG_MHICTRLBASE_HIGHER 0x84 -#define REG_MHICTRLLIMIT_LOWER 0x88 -#define REG_MHICTRLLIMIT_HIGHER 0x8c -#define REG_MHIDATABASE_LOWER 0x98 -#define REG_MHIDATABASE_HIGHER 0x9c -#define REG_MHIDATALIMIT_LOWER 0xa0 -#define REG_MHIDATALIMIT_HIGHER 0xa4 - -/* MHI BHI registers */ -#define REG_BHI_BHIVERSION_MINOR 0x00 -#define REG_BHI_BHIVERSION_MAJOR 0x04 -#define REG_BHI_IMGADDR_LOW 0x08 -#define REG_BHI_IMGADDR_HIGH 0x0c -#define REG_BHI_IMGSIZE 0x10 -#define REG_BHI_RSVD1 0x14 -#define REG_BHI_IMGTXDB 0x18 -#define REG_BHI_RSVD2 0x1c -#define REG_BHI_INTVEC 0x20 -#define REG_BHI_RSVD3 0x24 -#define REG_BHI_EXECENV 0x28 -#define REG_BHI_STATUS 0x2c -#define REG_BHI_ERRCODE 0x30 -#define REG_BHI_ERRDBG1 0x34 -#define REG_BHI_ERRDBG2 0x38 -#define REG_BHI_ERRDBG3 0x3c -#define REG_BHI_SERIALNU 0x40 -#define REG_BHI_SBLANTIROLLVER 0x44 -#define REG_BHI_NUMSEG 0x48 -#define REG_BHI_MSMHWID(n) (0x4c + (0x4 * (n))) -#define REG_BHI_OEMPKHASH(n) (0x64 + (0x4 * (n))) -#define REG_BHI_RSVD5 0xc4 - -/* BHI register bits */ -#define BHI_TXDB_SEQNUM_BMSK GENMASK(29, 0) -#define BHI_STATUS_MASK GENMASK(31, 30) -#define BHI_STATUS_ERROR 0x03 -#define BHI_STATUS_SUCCESS 0x02 -#define BHI_STATUS_RESET 0x00 - -/* MHI BHIE registers */ -#define REG_BHIE_MSMSOCID_OFFS 0x00 -#define REG_BHIE_TXVECADDR_LOW_OFFS 0x2c -#define REG_BHIE_TXVECADDR_HIGH_OFFS 0x30 -#define REG_BHIE_TXVECSIZE_OFFS 0x34 -#define REG_BHIE_TXVECDB_OFFS 0x3c -#define REG_BHIE_TXVECSTATUS_OFFS 0x44 -#define REG_BHIE_RXVECADDR_LOW_OFFS 0x60 -#define REG_BHIE_RXVECADDR_HIGH_OFFS 0x64 -#define REG_BHIE_RXVECSIZE_OFFS 0x68 -#define REG_BHIE_RXVECDB_OFFS 0x70 -#define REG_BHIE_RXVECSTATUS_OFFS 0x78 - -/* BHIE register bits */ -#define BHIE_TXVECDB_SEQNUM_BMSK GENMASK(29, 0) -#define BHIE_TXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0) -#define BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30) -#define BHIE_TXVECSTATUS_STATUS_RESET 0x00 -#define BHIE_TXVECSTATUS_STATUS_XFER_COMPL 0x02 -#define BHIE_TXVECSTATUS_STATUS_ERROR 0x03 -#define BHIE_RXVECDB_SEQNUM_BMSK GENMASK(29, 0) -#define BHIE_RXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0) -#define BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30) -#define BHIE_RXVECSTATUS_STATUS_RESET 0x00 -#define BHIE_RXVECSTATUS_STATUS_XFER_COMPL 0x02 -#define BHIE_RXVECSTATUS_STATUS_ERROR 0x03 - -/* MHI register bits */ -#define MHIREGLEN_MHIREGLEN_MASK GENMASK(31, 0) -#define MHIVER_MHIVER_MASK GENMASK(31, 0) -#define MHICFG_NHWER_MASK GENMASK(31, 24) -#define MHICFG_NER_MASK GENMASK(23, 16) -#define MHICFG_NHWCH_MASK GENMASK(15, 8) -#define MHICFG_NCH_MASK GENMASK(7, 0) -#define CHDBOFF_CHDBOFF_MASK GENMASK(31, 0) -#define ERDBOFF_ERDBOFF_MASK GENMASK(31, 0) -#define BHIOFF_BHIOFF_MASK GENMASK(31, 0) -#define BHIEOFF_BHIEOFF_MASK GENMASK(31, 0) -#define DEBUGOFF_DEBUGOFF_MASK GENMASK(31, 0) -#define MHICTRL_MHISTATE_MASK GENMASK(15, 8) -#define MHICTRL_RESET_MASK BIT(1) -#define MHISTATUS_MHISTATE_MASK GENMASK(15, 8) -#define MHISTATUS_SYSERR_MASK BIT(2) -#define MHISTATUS_READY_MASK BIT(0) -#define CCABAP_LOWER_CCABAP_LOWER_MASK GENMASK(31, 0) -#define CCABAP_HIGHER_CCABAP_HIGHER_MASK GENMASK(31, 0) -#define ECABAP_LOWER_ECABAP_LOWER_MASK GENMASK(31, 0) -#define ECABAP_HIGHER_ECABAP_HIGHER_MASK GENMASK(31, 0) -#define CRCBAP_LOWER_CRCBAP_LOWER_MASK GENMASK(31, 0) -#define CRCBAP_HIGHER_CRCBAP_HIGHER_MASK GENMASK(31, 0) -#define CRDB_LOWER_CRDB_LOWER_MASK GENMASK(31, 0) -#define CRDB_HIGHER_CRDB_HIGHER_MASK GENMASK(31, 0) -#define MHICTRLBASE_LOWER_MHICTRLBASE_LOWER_MASK GENMASK(31, 0) -#define MHICTRLBASE_HIGHER_MHICTRLBASE_HIGHER_MASK GENMASK(31, 0) -#define MHICTRLLIMIT_LOWER_MHICTRLLIMIT_LOWER_MASK GENMASK(31, 0) -#define MHICTRLLIMIT_HIGHER_MHICTRLLIMIT_HIGHER_MASK GENMASK(31, 0) -#define MHIDATABASE_LOWER_MHIDATABASE_LOWER_MASK GENMASK(31, 0) -#define MHIDATABASE_HIGHER_MHIDATABASE_HIGHER_MASK GENMASK(31, 0) -#define MHIDATALIMIT_LOWER_MHIDATALIMIT_LOWER_MASK GENMASK(31, 0) -#define MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_MASK GENMASK(31, 0) - -/* Command Ring Element macros */ -/* No operation command */ -#define MHI_TRE_CMD_NOOP_PTR 0 -#define MHI_TRE_CMD_NOOP_DWORD0 0 -#define MHI_TRE_CMD_NOOP_DWORD1 cpu_to_le32(MHI_CMD_NOP << 16) - -/* Channel reset command */ -#define MHI_TRE_CMD_RESET_PTR 0 -#define MHI_TRE_CMD_RESET_DWORD0 0 -#define MHI_TRE_CMD_RESET_DWORD1(chid) (cpu_to_le32((chid << 24) | \ - (MHI_CMD_RESET_CHAN << 16))) - -/* Channel stop command */ -#define MHI_TRE_CMD_STOP_PTR 0 -#define MHI_TRE_CMD_STOP_DWORD0 0 -#define MHI_TRE_CMD_STOP_DWORD1(chid) (cpu_to_le32((chid << 24) | \ - (MHI_CMD_STOP_CHAN << 16))) - -/* Channel start command */ -#define MHI_TRE_CMD_START_PTR 0 -#define MHI_TRE_CMD_START_DWORD0 0 -#define MHI_TRE_CMD_START_DWORD1(chid) (cpu_to_le32((chid << 24) | \ - (MHI_CMD_START_CHAN << 16))) - -#define MHI_TRE_GET_DWORD(tre, word) le32_to_cpu((tre)->dword[(word)]) -#define MHI_TRE_GET_CMD_CHID(tre) ((MHI_TRE_GET_DWORD(tre, 1) >> 24) & 0xFF) -#define MHI_TRE_GET_CMD_TYPE(tre) ((MHI_TRE_GET_DWORD(tre, 1) >> 16) & 0xFF) - -/* Event descriptor macros */ -/* Transfer completion event */ -#define MHI_TRE_EV_PTR(ptr) cpu_to_le64(ptr) -#define MHI_TRE_EV_DWORD0(code, len) cpu_to_le32((code << 24) | len) -#define MHI_TRE_EV_DWORD1(chid, type) cpu_to_le32((chid << 24) | (type << 16)) -#define MHI_TRE_GET_EV_PTR(tre) le64_to_cpu((tre)->ptr) -#define MHI_TRE_GET_EV_CODE(tre) ((MHI_TRE_GET_DWORD(tre, 0) >> 24) & 0xFF) -#define MHI_TRE_GET_EV_LEN(tre) (MHI_TRE_GET_DWORD(tre, 0) & 0xFFFF) -#define MHI_TRE_GET_EV_CHID(tre) ((MHI_TRE_GET_DWORD(tre, 1) >> 24) & 0xFF) -#define MHI_TRE_GET_EV_TYPE(tre) ((MHI_TRE_GET_DWORD(tre, 1) >> 16) & 0xFF) -#define MHI_TRE_GET_EV_STATE(tre) ((MHI_TRE_GET_DWORD(tre, 0) >> 24) & 0xFF) -#define MHI_TRE_GET_EV_EXECENV(tre) ((MHI_TRE_GET_DWORD(tre, 0) >> 24) & 0xFF) -#define MHI_TRE_GET_EV_SEQ(tre) MHI_TRE_GET_DWORD(tre, 0) -#define MHI_TRE_GET_EV_TIME(tre) MHI_TRE_GET_EV_PTR(tre) -#define MHI_TRE_GET_EV_COOKIE(tre) lower_32_bits(MHI_TRE_GET_EV_PTR(tre)) -#define MHI_TRE_GET_EV_VEID(tre) ((MHI_TRE_GET_DWORD(tre, 0) >> 16) & 0xFF) -#define MHI_TRE_GET_EV_LINKSPEED(tre) ((MHI_TRE_GET_DWORD(tre, 1) >> 24) & 0xFF) -#define MHI_TRE_GET_EV_LINKWIDTH(tre) (MHI_TRE_GET_DWORD(tre, 0) & 0xFF) - -/* State change event */ -#define MHI_SC_EV_PTR 0 -#define MHI_SC_EV_DWORD0(state) cpu_to_le32(state << 24) -#define MHI_SC_EV_DWORD1(type) cpu_to_le32(type << 16) - -/* EE event */ -#define MHI_EE_EV_PTR 0 -#define MHI_EE_EV_DWORD0(ee) cpu_to_le32(ee << 24) -#define MHI_EE_EV_DWORD1(type) cpu_to_le32(type << 16) - -/* Command Completion event */ -#define MHI_CC_EV_PTR(ptr) cpu_to_le64(ptr) -#define MHI_CC_EV_DWORD0(code) cpu_to_le32(code << 24) -#define MHI_CC_EV_DWORD1(type) cpu_to_le32(type << 16) - -/* Transfer descriptor macros */ -#define MHI_TRE_DATA_PTR(ptr) cpu_to_le64(ptr) -#define MHI_TRE_DATA_DWORD0(len) cpu_to_le32(len & MHI_MAX_MTU) -#define MHI_TRE_DATA_DWORD1(bei, ieot, ieob, chain) (cpu_to_le32((2 << 16) | (bei << 10) \ - | (ieot << 9) | (ieob << 8) | chain)) - -/* RSC transfer descriptor macros */ -#define MHI_RSCTRE_DATA_PTR(ptr, len) cpu_to_le64(((u64)len << 48) | ptr) -#define MHI_RSCTRE_DATA_DWORD0(cookie) cpu_to_le32(cookie) -#define MHI_RSCTRE_DATA_DWORD1 cpu_to_le32(MHI_PKT_TYPE_COALESCING << 16) ->>>>>>> - -enum mhi_pkt_type { - MHI_PKT_TYPE_INVALID = 0x0, - MHI_PKT_TYPE_NOOP_CMD = 0x1, - MHI_PKT_TYPE_TRANSFER = 0x2, - MHI_PKT_TYPE_COALESCING = 0x8, - MHI_PKT_TYPE_RESET_CHAN_CMD = 0x10, - MHI_PKT_TYPE_STOP_CHAN_CMD = 0x11, - MHI_PKT_TYPE_START_CHAN_CMD = 0x12, - MHI_PKT_TYPE_STATE_CHANGE_EVENT = 0x20, - MHI_PKT_TYPE_CMD_COMPLETION_EVENT = 0x21, - MHI_PKT_TYPE_TX_EVENT = 0x22, - MHI_PKT_TYPE_RSC_TX_EVENT = 0x28, - MHI_PKT_TYPE_EE_EVENT = 0x40, - MHI_PKT_TYPE_TSYNC_EVENT = 0x48, - MHI_PKT_TYPE_BW_REQ_EVENT = 0x50, - MHI_PKT_TYPE_STALE_EVENT, /* internal event */ -}; - -/* MHI transfer completion events */ -enum mhi_ev_ccs { - MHI_EV_CC_INVALID = 0x0, - MHI_EV_CC_SUCCESS = 0x1, - MHI_EV_CC_EOT = 0x2, /* End of transfer event */ - MHI_EV_CC_OVERFLOW = 0x3, - MHI_EV_CC_EOB = 0x4, /* End of block event */ - MHI_EV_CC_OOB = 0x5, /* Out of block event */ - MHI_EV_CC_DB_MODE = 0x6, - MHI_EV_CC_UNDEFINED_ERR = 0x10, - MHI_EV_CC_BAD_TRE = 0x11, -}; - -/* Channel state */ -enum mhi_ch_state { - MHI_CH_STATE_DISABLED, - MHI_CH_STATE_ENABLED, - MHI_CH_STATE_RUNNING, - MHI_CH_STATE_SUSPENDED, - MHI_CH_STATE_STOP, - MHI_CH_STATE_ERROR, -}; - -enum mhi_cmd_type { - MHI_CMD_NOP = 1, - MHI_CMD_RESET_CHAN = 16, - MHI_CMD_STOP_CHAN = 17, - MHI_CMD_START_CHAN = 18, -}; - -#define EV_CTX_RESERVED_MASK GENMASK(7, 0) -#define EV_CTX_INTMODC_MASK GENMASK(15, 8) -<<<<<<< -#define EV_CTX_INTMODC_SHIFT 8 -#define EV_CTX_INTMODT_MASK GENMASK(31, 16) -#define EV_CTX_INTMODT_SHIFT 16 -struct mhi_event_ctxt { - __u32 intmod; - __u32 ertype; - __u32 msivec; - - __u64 rbase __packed __aligned(4); - __u64 rlen __packed __aligned(4); - __u64 rp __packed __aligned(4); - __u64 wp __packed __aligned(4); -}; - -#define CHAN_CTX_CHSTATE_MASK GENMASK(7, 0) -#define CHAN_CTX_CHSTATE_SHIFT 0 -#define CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8) -#define CHAN_CTX_BRSTMODE_SHIFT 8 -#define CHAN_CTX_POLLCFG_MASK GENMASK(15, 10) -#define CHAN_CTX_POLLCFG_SHIFT 10 -#define CHAN_CTX_RESERVED_MASK GENMASK(31, 16) -struct mhi_chan_ctxt { - __u32 chcfg; - __u32 chtype; - __u32 erindex; - - __u64 rbase __packed __aligned(4); - __u64 rlen __packed __aligned(4); - __u64 rp __packed __aligned(4); - __u64 wp __packed __aligned(4); -}; - -struct mhi_cmd_ctxt { - __u32 reserved0; - __u32 reserved1; - __u32 reserved2; - - __u64 rbase __packed __aligned(4); - __u64 rlen __packed __aligned(4); - __u64 rp __packed __aligned(4); - __u64 wp __packed __aligned(4); -}; - -extern const char * const mhi_state_str[MHI_STATE_MAX]; -#define TO_MHI_STATE_STR(state) ((state >= MHI_STATE_MAX || \ - !mhi_state_str[state]) ? \ - "INVALID_STATE" : mhi_state_str[state]) -======= -#define EV_CTX_INTMODT_MASK GENMASK(31, 16) -struct mhi_event_ctxt { - __le32 intmod; - __le32 ertype; - __le32 msivec; - - __le64 rbase __packed __aligned(4); - __le64 rlen __packed __aligned(4); - __le64 rp __packed __aligned(4); - __le64 wp __packed __aligned(4); -}; - -#define CHAN_CTX_CHSTATE_MASK GENMASK(7, 0) -#define CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8) -#define CHAN_CTX_POLLCFG_MASK GENMASK(15, 10) -#define CHAN_CTX_RESERVED_MASK GENMASK(31, 16) -struct mhi_chan_ctxt { - __le32 chcfg; - __le32 chtype; - __le32 erindex; - - __le64 rbase __packed __aligned(4); - __le64 rlen __packed __aligned(4); - __le64 rp __packed __aligned(4); - __le64 wp __packed __aligned(4); -}; - -struct mhi_cmd_ctxt { - __le32 reserved0; - __le32 reserved1; - __le32 reserved2; - - __le64 rbase __packed __aligned(4); - __le64 rlen __packed __aligned(4); - __le64 rp __packed __aligned(4); - __le64 wp __packed __aligned(4); -}; - -static inline const char * const mhi_state_str(enum mhi_state state) -{ - switch (state) { - case MHI_STATE_RESET: - return "RESET"; - case MHI_STATE_READY: - return "READY"; - case MHI_STATE_M0: - return "M0"; - case MHI_STATE_M1: - return "M1"; - case MHI_STATE_M2: - return"M2"; - case MHI_STATE_M3: - return"M3"; - case MHI_STATE_M3_FAST: - return"M3 FAST"; - case MHI_STATE_BHI: - return"BHI"; - case MHI_STATE_SYS_ERR: - return "SYS ERROR"; - default: - return "Unknown state"; - } -}; ->>>>>>> - -#endif /* _MHI_COMMON_H */ diff --git a/rr-cache/cbc6317c2516a04a1c7d43e4be17b722fbac324e/preimage b/rr-cache/cbc6317c2516a04a1c7d43e4be17b722fbac324e/preimage deleted file mode 100644 index 33e31bc..0000000 --- a/rr-cache/cbc6317c2516a04a1c7d43e4be17b722fbac324e/preimage +++ /dev/null @@ -1,131 +0,0 @@ -<<<<<<< -# The config is based on running daily CI for enterprise Linux distros to -# seek regressions on linux-next builds on different bare-metal and virtual -# platforms. It can be used for example, -# -# $ make ARCH=arm64 defconfig debug.config -# -# Keep alphabetically sorted inside each section. -# -# printk and dmesg options -# -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_PRINTK_CALLER=y -CONFIG_PRINTK_TIME=y -CONFIG_SYMBOLIC_ERRNAME=y -# -# Compile-time checks and compiler options -# -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_FRAME_WARN=2048 -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# -# Generic Kernel Debugging Instruments -# -# CONFIG_UBSAN_ALIGNMENT is not set -# CONFIG_UBSAN_DIV_ZERO is not set -# CONFIG_UBSAN_TRAP is not set -# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_FS_ALLOW_ALL=y -CONFIG_DEBUG_IRQFLAGS=y -CONFIG_UBSAN=y -CONFIG_UBSAN_BOOL=y -CONFIG_UBSAN_BOUNDS=y -CONFIG_UBSAN_ENUM=y -CONFIG_UBSAN_SHIFT=y -CONFIG_UBSAN_UNREACHABLE=y -# -# Memory Debugging -# -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF is not set -# CONFIG_DEBUG_RODATA_TEST is not set -# CONFIG_DEBUG_WX is not set -# CONFIG_KFENCE is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_SLUB_STATS is not set -CONFIG_PAGE_EXTENSION=y -CONFIG_PAGE_OWNER=y -CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y -CONFIG_DEBUG_OBJECTS=y -CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 -CONFIG_DEBUG_OBJECTS_FREE=y -CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y -CONFIG_DEBUG_OBJECTS_RCU_HEAD=y -CONFIG_DEBUG_OBJECTS_TIMERS=y -CONFIG_DEBUG_OBJECTS_WORK=y -CONFIG_DEBUG_PER_CPU_MAPS=y -CONFIG_DEBUG_STACK_USAGE=y -CONFIG_DEBUG_VIRTUAL=y -CONFIG_DEBUG_VM=y -CONFIG_DEBUG_VM_PGFLAGS=y -CONFIG_DEBUG_VM_RB=y -CONFIG_DEBUG_VM_VMACACHE=y -CONFIG_GENERIC_PTDUMP=y -CONFIG_KASAN=y -CONFIG_KASAN_GENERIC=y -CONFIG_KASAN_INLINE=y -CONFIG_KASAN_VMALLOC=y -CONFIG_PTDUMP_DEBUGFS=y -CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_SLUB_DEBUG_ON=y -# -# Debug Oops, Lockups and Hangs -# -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_PANIC_ON_OOPS=y -CONFIG_PANIC_TIMEOUT=0 -CONFIG_SOFTLOCKUP_DETECTOR=y -# -# Lock Debugging (spinlocks, mutexes, etc...) -# -# CONFIG_PROVE_RAW_LOCK_NESTING is not set -CONFIG_PROVE_LOCKING=y -# -# Debug kernel data structures -# -CONFIG_BUG_ON_DATA_CORRUPTION=y -# -# RCU Debugging -# -CONFIG_PROVE_RCU=y -CONFIG_PROVE_RCU_LIST=y -# -# Tracers -# -CONFIG_BRANCH_PROFILE_NONE=y -CONFIG_DYNAMIC_FTRACE=y -CONFIG_FTRACE=y -CONFIG_FUNCTION_TRACER=y -# -# Landing team defines -# -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_PAGEALLOC=y -CONFIG_DEBUG_LOCK_ALLOC=y -CONFIG_SLUB_DEBUG=y -CONFIG_SLUB_DEBUG_ON=y -CONFIG_KASAN=y -======= -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_DEBUG_PAGEALLOC=y -CONFIG_DEBUG_LOCK_ALLOC=y -CONFIG_PROVE_LOCKING=y -CONFIG_PROVE_RCU=y -CONFIG_SLUB_DEBUG=y -CONFIG_SLUB_DEBUG_ON=y -CONFIG_KASAN=y -CONFIG_DEBUG_SPINLOCK=y ->>>>>>> -CONFIG_USB_GADGET_DEBUG=y -CONFIG_USB_GADGET_DEBUG_FILES=y diff --git a/rr-cache/e06e625c04171a8bcdefbfac612f7f543bb531f3/preimage b/rr-cache/e06e625c04171a8bcdefbfac612f7f543bb531f3/preimage deleted file mode 100644 index 7e7ee90..0000000 --- a/rr-cache/e06e625c04171a8bcdefbfac612f7f543bb531f3/preimage +++ /dev/null @@ -1,2494 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2011-2018, The Linux Foundation. All rights reserved. -// Copyright (c) 2018, Linaro Limited - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -<<<<<<< -======= -#include ->>>>>>> -#include - -#define ADSP_DOMAIN_ID (0) -#define MDSP_DOMAIN_ID (1) -#define SDSP_DOMAIN_ID (2) -#define CDSP_DOMAIN_ID (3) -#define FASTRPC_DEV_MAX 4 /* adsp, mdsp, slpi, cdsp*/ -<<<<<<< -#define FASTRPC_MAX_SESSIONS 13 /*12 compute, 1 cpz*/ -#define FASTRPC_MAX_VMIDS 16 -======= -#define FASTRPC_MAX_SESSIONS 9 /*8 compute, 1 cpz*/ ->>>>>>> -#define FASTRPC_ALIGN 128 -#define FASTRPC_MAX_FDLIST 16 -#define FASTRPC_MAX_CRCLIST 64 -#define FASTRPC_PHYS(p) ((p) & 0xffffffff) -#define FASTRPC_CTX_MAX (256) -#define FASTRPC_INIT_HANDLE 1 -#define FASTRPC_DSP_UTILITIES_HANDLE 2 -#define FASTRPC_CTXID_MASK (0xFF0) -#define INIT_FILELEN_MAX (2 * 1024 * 1024) -#define FASTRPC_DEVICE_NAME "fastrpc" -#define ADSP_MMAP_ADD_PAGES 0x1000 -#define DSP_UNSUPPORTED_API (0x80000414) -/* MAX NUMBER of DSP ATTRIBUTES SUPPORTED */ -#define FASTRPC_MAX_DSP_ATTRIBUTES (256) -#define FASTRPC_MAX_DSP_ATTRIBUTES_LEN (sizeof(u32) * FASTRPC_MAX_DSP_ATTRIBUTES) - -/* Retrives number of input buffers from the scalars parameter */ -#define REMOTE_SCALARS_INBUFS(sc) (((sc) >> 16) & 0x0ff) - -/* Retrives number of output buffers from the scalars parameter */ -#define REMOTE_SCALARS_OUTBUFS(sc) (((sc) >> 8) & 0x0ff) - -/* Retrives number of input handles from the scalars parameter */ -#define REMOTE_SCALARS_INHANDLES(sc) (((sc) >> 4) & 0x0f) - -/* Retrives number of output handles from the scalars parameter */ -#define REMOTE_SCALARS_OUTHANDLES(sc) ((sc) & 0x0f) - -#define REMOTE_SCALARS_LENGTH(sc) (REMOTE_SCALARS_INBUFS(sc) + \ - REMOTE_SCALARS_OUTBUFS(sc) + \ - REMOTE_SCALARS_INHANDLES(sc)+ \ - REMOTE_SCALARS_OUTHANDLES(sc)) -#define FASTRPC_BUILD_SCALARS(attr, method, in, out, oin, oout) \ - (((attr & 0x07) << 29) | \ - ((method & 0x1f) << 24) | \ - ((in & 0xff) << 16) | \ - ((out & 0xff) << 8) | \ - ((oin & 0x0f) << 4) | \ - (oout & 0x0f)) - -#define FASTRPC_SCALARS(method, in, out) \ - FASTRPC_BUILD_SCALARS(0, method, in, out, 0, 0) - -<<<<<<< -#define FASTRPC_CREATE_PROCESS_NARGS 6 -/* Remote Method id table */ -#define FASTRPC_RMID_INIT_ATTACH 0 -#define FASTRPC_RMID_INIT_RELEASE 1 -#define FASTRPC_RMID_INIT_MMAP 4 -#define FASTRPC_RMID_INIT_MUNMAP 5 -#define FASTRPC_RMID_INIT_CREATE 6 -#define FASTRPC_RMID_INIT_CREATE_ATTR 7 -#define FASTRPC_RMID_INIT_CREATE_STATIC 8 -#define FASTRPC_RMID_INIT_MEM_MAP 10 -#define FASTRPC_RMID_INIT_MEM_UNMAP 11 - -/* Protection Domain(PD) ids */ -#define AUDIO_PD (0) /* also GUEST_OS PD? */ -#define USER_PD (1) -#define SENSORS_PD (2) - -#define miscdev_to_fdevice(d) container_of(d, struct fastrpc_device, miscdev) -======= -#define miscdev_to_cctx(d) container_of(d, struct fastrpc_channel_ctx, miscdev) ->>>>>>> - -static const char *domains[FASTRPC_DEV_MAX] = { "adsp", "mdsp", - "sdsp", "cdsp"}; -struct fastrpc_phy_page { - u64 addr; /* physical address */ - u64 size; /* size of contiguous region */ -}; - -struct fastrpc_invoke_buf { - u32 num; /* number of contiguous regions */ - u32 pgidx; /* index to start of contiguous region */ -}; - -struct fastrpc_remote_arg { - u64 pv; - u64 len; -}; - -<<<<<<< -======= -struct fastrpc_mmap_rsp_msg { - u64 vaddr; -}; - -struct fastrpc_mmap_req_msg { - s32 pgid; - u32 flags; - u64 vaddr; - s32 num; -}; - -struct fastrpc_mem_map_req_msg { - s32 pgid; - s32 fd; - s32 offset; - u32 flags; - u64 vaddrin; - s32 num; - s32 data_len; -}; - -struct fastrpc_munmap_req_msg { - s32 pgid; - u64 vaddr; - u64 size; -}; - -struct fastrpc_mem_unmap_req_msg { - s32 pgid; - s32 fd; - u64 vaddrin; - u64 len; -}; - ->>>>>>> -struct fastrpc_msg { - int pid; /* process group id */ - int tid; /* thread id */ - u64 ctx; /* invoke caller context */ - u32 handle; /* handle to invoke */ - u32 sc; /* scalars structure describing the data */ - u64 addr; /* physical address */ - u64 size; /* size of contiguous region */ -}; - -struct fastrpc_invoke_rsp { - u64 ctx; /* invoke caller context */ - int retval; /* invoke return value */ -}; - -<<<<<<< -struct fastrpc_buf { - struct fastrpc_user *fl; -======= -struct fastrpc_buf_overlap { - u64 start; - u64 end; - int raix; - u64 mstart; - u64 mend; - u64 offset; -}; - -struct fastrpc_buf { - struct fastrpc_user *fl; - struct dma_buf *dmabuf; ->>>>>>> - struct device *dev; - void *virt; - u64 phys; - u64 size; -<<<<<<< -======= - /* Lock for dma buf attachments */ - struct mutex lock; - struct list_head attachments; - /* mmap support */ - struct list_head node; /* list of user requested mmaps */ - uintptr_t raddr; -}; - -struct fastrpc_dma_buf_attachment { - struct device *dev; - struct sg_table sgt; - struct list_head node; ->>>>>>> -}; - -struct fastrpc_map { - struct list_head node; - struct fastrpc_user *fl; - int fd; - struct dma_buf *buf; - struct sg_table *table; - struct dma_buf_attachment *attach; - u64 phys; - u64 size; - void *va; - u64 len; -<<<<<<< -======= - u64 raddr; - u32 attr; ->>>>>>> - struct kref refcount; -}; - -struct fastrpc_invoke_ctx { - int nscalars; - int nbufs; - int retval; - int pid; - int tgid; - u32 sc; - u32 *crc; - u64 ctxid; - u64 msg_sz; - struct kref refcount; - struct list_head node; /* list of ctxs */ - struct completion work; -<<<<<<< -======= - struct work_struct put_work; ->>>>>>> - struct fastrpc_msg msg; - struct fastrpc_user *fl; - struct fastrpc_remote_arg *rpra; - struct fastrpc_map **maps; - struct fastrpc_buf *buf; - struct fastrpc_invoke_args *args; -<<<<<<< -======= - struct fastrpc_buf_overlap *olaps; ->>>>>>> - struct fastrpc_channel_ctx *cctx; -}; - -struct fastrpc_session_ctx { - struct device *dev; - int sid; - bool used; - bool valid; -}; - -struct fastrpc_channel_ctx { - int domain_id; - int sesscount; - int vmcount; - u32 perms; - struct qcom_scm_vmperm vmperms[FASTRPC_MAX_VMIDS]; - struct rpmsg_device *rpdev; - struct fastrpc_session_ctx session[FASTRPC_MAX_SESSIONS]; - spinlock_t lock; - struct idr ctx_idr; - struct list_head users; - struct kref refcount; - /* Flag if dsp attributes are cached */ - bool valid_attributes; - u32 dsp_attributes[FASTRPC_MAX_DSP_ATTRIBUTES]; - struct fastrpc_device *secure_fdevice; - struct fastrpc_device *fdevice; - bool secure; - bool unsigned_support; -}; - -struct fastrpc_device { - struct fastrpc_channel_ctx *cctx; - struct miscdevice miscdev; - bool secure; -}; - -struct fastrpc_user { - struct list_head user; - struct list_head maps; - struct list_head pending; - struct list_head mmaps; - - struct fastrpc_channel_ctx *cctx; - struct fastrpc_session_ctx *sctx; - struct fastrpc_buf *init_mem; - - int tgid; - int pd; - bool is_secure_dev; - /* Lock for lists */ - spinlock_t lock; - /* lock for allocations */ - struct mutex mutex; -}; - -static void fastrpc_free_map(struct kref *ref) -{ - struct fastrpc_map *map; - - map = container_of(ref, struct fastrpc_map, refcount); - - if (map->table) { -<<<<<<< -======= - if (map->attr & FASTRPC_ATTR_SECUREMAP) { - struct qcom_scm_vmperm perm; - int err = 0; - - perm.vmid = QCOM_SCM_VMID_HLOS; - perm.perm = QCOM_SCM_PERM_RWX; - err = qcom_scm_assign_mem(map->phys, map->size, - &(map->fl->cctx->vmperms[0].vmid), &perm, 1); - if (err) { - dev_err(map->fl->sctx->dev, "Failed to assign memory phys 0x%llx size 0x%llx err %d", - map->phys, map->size, err); - return; - } - } ->>>>>>> - dma_buf_unmap_attachment(map->attach, map->table, - DMA_BIDIRECTIONAL); - dma_buf_detach(map->buf, map->attach); - dma_buf_put(map->buf); - } - - kfree(map); -} - -static void fastrpc_map_put(struct fastrpc_map *map) -{ - if (map) - kref_put(&map->refcount, fastrpc_free_map); -} - -static void fastrpc_map_get(struct fastrpc_map *map) -{ - if (map) - kref_get(&map->refcount); -} - -<<<<<<< - -static int fastrpc_map_lookup(struct fastrpc_user *fl, int fd, -======= -static int fastrpc_map_find(struct fastrpc_user *fl, int fd, ->>>>>>> - struct fastrpc_map **ppmap) -{ - struct fastrpc_map *map = NULL; - - mutex_lock(&fl->mutex); - list_for_each_entry(map, &fl->maps, node) { - if (map->fd == fd) { -<<<<<<< -======= - fastrpc_map_get(map); ->>>>>>> - *ppmap = map; - mutex_unlock(&fl->mutex); - return 0; - } - } - mutex_unlock(&fl->mutex); - - return -ENOENT; -} - -<<<<<<< -======= -static int fastrpc_map_find(struct fastrpc_user *fl, int fd, - struct fastrpc_map **ppmap) -{ - int ret = fastrpc_map_lookup(fl, fd, ppmap); - - if (!ret) - fastrpc_map_get(*ppmap); - - return ret; -} - ->>>>>>> -static void fastrpc_buf_free(struct fastrpc_buf *buf) -{ - dma_free_coherent(buf->dev, buf->size, buf->virt, - FASTRPC_PHYS(buf->phys)); - kfree(buf); -} - -static int fastrpc_buf_alloc(struct fastrpc_user *fl, struct device *dev, - u64 size, struct fastrpc_buf **obuf) -{ - struct fastrpc_buf *buf; - - buf = kzalloc(sizeof(*buf), GFP_KERNEL); - if (!buf) - return -ENOMEM; - -<<<<<<< -======= - INIT_LIST_HEAD(&buf->attachments); - INIT_LIST_HEAD(&buf->node); - mutex_init(&buf->lock); - ->>>>>>> - buf->fl = fl; - buf->virt = NULL; - buf->phys = 0; - buf->size = size; - buf->dev = dev; -<<<<<<< - buf->raddr = 0; - - buf->virt = dma_alloc_coherent(dev, buf->size, (dma_addr_t *)&buf->phys, - GFP_KERNEL); - if (!buf->virt) { - mutex_destroy(&buf->lock); - kfree(buf); - return -ENOMEM; - } -======= - - buf->virt = dma_alloc_coherent(dev, buf->size, (dma_addr_t *)&buf->phys, - GFP_KERNEL); - if (!buf->virt) - return -ENOMEM; ->>>>>>> - - if (fl->sctx && fl->sctx->sid) - buf->phys += ((u64)fl->sctx->sid << 32); - - *obuf = buf; - - return 0; -} - -<<<<<<< -======= -static void fastrpc_channel_ctx_free(struct kref *ref) -{ - struct fastrpc_channel_ctx *cctx; - - cctx = container_of(ref, struct fastrpc_channel_ctx, refcount); - - kfree(cctx); -} - -static void fastrpc_channel_ctx_get(struct fastrpc_channel_ctx *cctx) -{ - kref_get(&cctx->refcount); -} - -static void fastrpc_channel_ctx_put(struct fastrpc_channel_ctx *cctx) -{ - kref_put(&cctx->refcount, fastrpc_channel_ctx_free); -} - ->>>>>>> -static void fastrpc_context_free(struct kref *ref) -{ - struct fastrpc_invoke_ctx *ctx; - struct fastrpc_channel_ctx *cctx; -<<<<<<< -======= - unsigned long flags; ->>>>>>> - int i; - - ctx = container_of(ref, struct fastrpc_invoke_ctx, refcount); - cctx = ctx->cctx; - -<<<<<<< - for (i = 0; i < ctx->nbufs; i++) -======= - for (i = 0; i < ctx->nscalars; i++) ->>>>>>> - fastrpc_map_put(ctx->maps[i]); - - if (ctx->buf) - fastrpc_buf_free(ctx->buf); - -<<<<<<< - spin_lock(&cctx->lock); - idr_remove(&cctx->ctx_idr, ctx->ctxid >> 4); - spin_unlock(&cctx->lock); - - kfree(ctx->maps); - kfree(ctx); -======= - spin_lock_irqsave(&cctx->lock, flags); - idr_remove(&cctx->ctx_idr, ctx->ctxid >> 4); - spin_unlock_irqrestore(&cctx->lock, flags); - - kfree(ctx->maps); - kfree(ctx->olaps); - kfree(ctx); - - fastrpc_channel_ctx_put(cctx); ->>>>>>> -} - -static void fastrpc_context_get(struct fastrpc_invoke_ctx *ctx) -{ - kref_get(&ctx->refcount); -} - -static void fastrpc_context_put(struct fastrpc_invoke_ctx *ctx) -{ - kref_put(&ctx->refcount, fastrpc_context_free); -} - -<<<<<<< -======= -static void fastrpc_context_put_wq(struct work_struct *work) -{ - struct fastrpc_invoke_ctx *ctx = - container_of(work, struct fastrpc_invoke_ctx, put_work); - - fastrpc_context_put(ctx); -} - -#define CMP(aa, bb) ((aa) == (bb) ? 0 : (aa) < (bb) ? -1 : 1) -static int olaps_cmp(const void *a, const void *b) -{ - struct fastrpc_buf_overlap *pa = (struct fastrpc_buf_overlap *)a; - struct fastrpc_buf_overlap *pb = (struct fastrpc_buf_overlap *)b; - /* sort with lowest starting buffer first */ - int st = CMP(pa->start, pb->start); - /* sort with highest ending buffer first */ - int ed = CMP(pb->end, pa->end); - - return st == 0 ? ed : st; -} - -static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) -{ - u64 max_end = 0; - int i; - - for (i = 0; i < ctx->nbufs; ++i) { - ctx->olaps[i].start = ctx->args[i].ptr; - ctx->olaps[i].end = ctx->olaps[i].start + ctx->args[i].length; - ctx->olaps[i].raix = i; - } - - sort(ctx->olaps, ctx->nbufs, sizeof(*ctx->olaps), olaps_cmp, NULL); - - for (i = 0; i < ctx->nbufs; ++i) { - /* Falling inside previous range */ - if (ctx->olaps[i].start < max_end) { - ctx->olaps[i].mstart = max_end; - ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].offset = max_end - ctx->olaps[i].start; - - if (ctx->olaps[i].end > max_end) { - max_end = ctx->olaps[i].end; - } else { - ctx->olaps[i].mend = 0; - ctx->olaps[i].mstart = 0; - } - - } else { - ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].mstart = ctx->olaps[i].start; - ctx->olaps[i].offset = 0; - max_end = ctx->olaps[i].end; - } - } -} - ->>>>>>> -static struct fastrpc_invoke_ctx *fastrpc_context_alloc( - struct fastrpc_user *user, u32 kernel, u32 sc, - struct fastrpc_invoke_args *args) -{ - struct fastrpc_channel_ctx *cctx = user->cctx; - struct fastrpc_invoke_ctx *ctx = NULL; -<<<<<<< -======= - unsigned long flags; ->>>>>>> - int ret; - - ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return ERR_PTR(-ENOMEM); - - INIT_LIST_HEAD(&ctx->node); - ctx->fl = user; - ctx->nscalars = REMOTE_SCALARS_LENGTH(sc); - ctx->nbufs = REMOTE_SCALARS_INBUFS(sc) + - REMOTE_SCALARS_OUTBUFS(sc); - - if (ctx->nscalars) { - ctx->maps = kcalloc(ctx->nscalars, - sizeof(*ctx->maps), GFP_KERNEL); - if (!ctx->maps) { - kfree(ctx); - return ERR_PTR(-ENOMEM); - } -<<<<<<< - ctx->args = args; - } - -======= - ctx->olaps = kcalloc(ctx->nscalars, - sizeof(*ctx->olaps), GFP_KERNEL); - if (!ctx->olaps) { - kfree(ctx->maps); - kfree(ctx); - return ERR_PTR(-ENOMEM); - } - ctx->args = args; - fastrpc_get_buff_overlaps(ctx); - } - - /* Released in fastrpc_context_put() */ - fastrpc_channel_ctx_get(cctx); - ->>>>>>> - ctx->sc = sc; - ctx->retval = -1; - ctx->pid = current->pid; - ctx->tgid = user->tgid; - ctx->cctx = cctx; - init_completion(&ctx->work); -<<<<<<< -======= - INIT_WORK(&ctx->put_work, fastrpc_context_put_wq); ->>>>>>> - - spin_lock(&user->lock); - list_add_tail(&ctx->node, &user->pending); - spin_unlock(&user->lock); - -<<<<<<< - spin_lock(&cctx->lock); - ret = idr_alloc_cyclic(&cctx->ctx_idr, ctx, 1, - FASTRPC_CTX_MAX, GFP_ATOMIC); - if (ret < 0) { - spin_unlock(&cctx->lock); - goto err_idr; - } - ctx->ctxid = ret << 4; - spin_unlock(&cctx->lock); -======= - spin_lock_irqsave(&cctx->lock, flags); - ret = idr_alloc_cyclic(&cctx->ctx_idr, ctx, 1, - FASTRPC_CTX_MAX, GFP_ATOMIC); - if (ret < 0) { - spin_unlock_irqrestore(&cctx->lock, flags); - goto err_idr; - } - ctx->ctxid = ret << 4; - spin_unlock_irqrestore(&cctx->lock, flags); ->>>>>>> - - kref_init(&ctx->refcount); - - return ctx; -err_idr: - spin_lock(&user->lock); - list_del(&ctx->node); - spin_unlock(&user->lock); -<<<<<<< - fastrpc_channel_ctx_put(cctx); - kfree(ctx->maps); - kfree(ctx->olaps); -======= - kfree(ctx->maps); ->>>>>>> - kfree(ctx); - - return ERR_PTR(ret); -} - -<<<<<<< -static int fastrpc_map_create(struct fastrpc_user *fl, int fd, - u64 len, struct fastrpc_map **ppmap) -======= -static struct sg_table * -fastrpc_map_dma_buf(struct dma_buf_attachment *attachment, - enum dma_data_direction dir) -{ - struct fastrpc_dma_buf_attachment *a = attachment->priv; - struct sg_table *table; - int ret; - - table = &a->sgt; - - ret = dma_map_sgtable(attachment->dev, table, dir, 0); - if (ret) - table = ERR_PTR(ret); - return table; -} - -static void fastrpc_unmap_dma_buf(struct dma_buf_attachment *attach, - struct sg_table *table, - enum dma_data_direction dir) -{ - dma_unmap_sgtable(attach->dev, table, dir, 0); -} - -static void fastrpc_release(struct dma_buf *dmabuf) -{ - struct fastrpc_buf *buffer = dmabuf->priv; - - fastrpc_buf_free(buffer); -} - -static int fastrpc_dma_buf_attach(struct dma_buf *dmabuf, - struct dma_buf_attachment *attachment) -{ - struct fastrpc_dma_buf_attachment *a; - struct fastrpc_buf *buffer = dmabuf->priv; - int ret; - - a = kzalloc(sizeof(*a), GFP_KERNEL); - if (!a) - return -ENOMEM; - - ret = dma_get_sgtable(buffer->dev, &a->sgt, buffer->virt, - FASTRPC_PHYS(buffer->phys), buffer->size); - if (ret < 0) { - dev_err(buffer->dev, "failed to get scatterlist from DMA API\n"); - kfree(a); - return -EINVAL; - } - - a->dev = attachment->dev; - INIT_LIST_HEAD(&a->node); - attachment->priv = a; - - mutex_lock(&buffer->lock); - list_add(&a->node, &buffer->attachments); - mutex_unlock(&buffer->lock); - - return 0; -} - -static void fastrpc_dma_buf_detatch(struct dma_buf *dmabuf, - struct dma_buf_attachment *attachment) -{ - struct fastrpc_dma_buf_attachment *a = attachment->priv; - struct fastrpc_buf *buffer = dmabuf->priv; - - mutex_lock(&buffer->lock); - list_del(&a->node); - mutex_unlock(&buffer->lock); - sg_free_table(&a->sgt); - kfree(a); -} - -static int fastrpc_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) -{ - struct fastrpc_buf *buf = dmabuf->priv; - - dma_buf_map_set_vaddr(map, buf->virt); - - return 0; -} - -static int fastrpc_mmap(struct dma_buf *dmabuf, - struct vm_area_struct *vma) -{ - struct fastrpc_buf *buf = dmabuf->priv; - size_t size = vma->vm_end - vma->vm_start; - - return dma_mmap_coherent(buf->dev, vma, buf->virt, - FASTRPC_PHYS(buf->phys), size); -} - -static const struct dma_buf_ops fastrpc_dma_buf_ops = { - .attach = fastrpc_dma_buf_attach, - .detach = fastrpc_dma_buf_detatch, - .map_dma_buf = fastrpc_map_dma_buf, - .unmap_dma_buf = fastrpc_unmap_dma_buf, - .mmap = fastrpc_mmap, - .vmap = fastrpc_vmap, - .release = fastrpc_release, -}; - -static int fastrpc_map_create(struct fastrpc_user *fl, int fd, - u64 len, u32 attr, struct fastrpc_map **ppmap) ->>>>>>> -{ - struct fastrpc_session_ctx *sess = fl->sctx; - struct fastrpc_map *map = NULL; - int err = 0; - - if (!fastrpc_map_find(fl, fd, ppmap)) - return 0; - - map = kzalloc(sizeof(*map), GFP_KERNEL); - if (!map) - return -ENOMEM; - - INIT_LIST_HEAD(&map->node); - map->fl = fl; - map->fd = fd; - map->buf = dma_buf_get(fd); -<<<<<<< - if (!map->buf) { - err = -EINVAL; -======= - if (IS_ERR(map->buf)) { - err = PTR_ERR(map->buf); ->>>>>>> - goto get_err; - } - - map->attach = dma_buf_attach(map->buf, sess->dev); - if (IS_ERR(map->attach)) { - dev_err(sess->dev, "Failed to attach dmabuf\n"); - err = PTR_ERR(map->attach); - goto attach_err; - } - - map->table = dma_buf_map_attachment(map->attach, DMA_BIDIRECTIONAL); - if (IS_ERR(map->table)) { - err = PTR_ERR(map->table); - goto map_err; - } - - map->phys = sg_dma_address(map->table->sgl); - map->phys += ((u64)fl->sctx->sid << 32); - map->size = len; - map->va = sg_virt(map->table->sgl); - map->len = len; - kref_init(&map->refcount); - -<<<<<<< -======= - if (attr & FASTRPC_ATTR_SECUREMAP) { - /* - * If subsystem VMIDs are defined in DTSI, then do - * hyp_assign from HLOS to those VM(s) - */ - unsigned int perms = BIT(QCOM_SCM_VMID_HLOS); - - map->attr = attr; - err = qcom_scm_assign_mem(map->phys, (u64)map->size, &perms, - fl->cctx->vmperms, fl->cctx->vmcount); - if (err) { - dev_err(sess->dev, "Failed to assign memory with phys 0x%llx size 0x%llx err %d", - map->phys, map->size, err); - goto map_err; - } - } ->>>>>>> - spin_lock(&fl->lock); - list_add_tail(&map->node, &fl->maps); - spin_unlock(&fl->lock); - *ppmap = map; - - return 0; - -map_err: - dma_buf_detach(map->buf, map->attach); -attach_err: - dma_buf_put(map->buf); -get_err: - kfree(map); - - return err; -} - -/* - * Fastrpc payload buffer with metadata looks like: - * - * >>>>>> START of METADATA <<<<<<<<< - * +---------------------------------+ - * | Arguments | - * | type:(struct fastrpc_remote_arg)| - * | (0 - N) | - * +---------------------------------+ - * | Invoke Buffer list | - * | type:(struct fastrpc_invoke_buf)| - * | (0 - N) | - * +---------------------------------+ - * | Page info list | - * | type:(struct fastrpc_phy_page) | - * | (0 - N) | - * +---------------------------------+ - * | Optional info | - * |(can be specific to SoC/Firmware)| - * +---------------------------------+ - * >>>>>>>> END of METADATA <<<<<<<<< - * +---------------------------------+ - * | Inline ARGS | - * | (0-N) | - * +---------------------------------+ - */ - -static int fastrpc_get_meta_size(struct fastrpc_invoke_ctx *ctx) -{ - int size = 0; - - size = (sizeof(struct fastrpc_remote_arg) + - sizeof(struct fastrpc_invoke_buf) + - sizeof(struct fastrpc_phy_page)) * ctx->nscalars + - sizeof(u64) * FASTRPC_MAX_FDLIST + - sizeof(u32) * FASTRPC_MAX_CRCLIST; - - return size; -} - -static u64 fastrpc_get_payload_size(struct fastrpc_invoke_ctx *ctx, int metalen) -{ - u64 size = 0; -<<<<<<< - int i; - - size = ALIGN(metalen, FASTRPC_ALIGN); - for (i = 0; i < ctx->nscalars; i++) { - if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1) { - size = ALIGN(size, FASTRPC_ALIGN); - size += ctx->args[i].length; -======= - int oix; - - size = ALIGN(metalen, FASTRPC_ALIGN); - for (oix = 0; oix < ctx->nbufs; oix++) { - int i = ctx->olaps[oix].raix; - - if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1) { - - if (ctx->olaps[oix].offset == 0) - size = ALIGN(size, FASTRPC_ALIGN); - - size += (ctx->olaps[oix].mend - ctx->olaps[oix].mstart); ->>>>>>> - } - } - - return size; -} - -static int fastrpc_create_maps(struct fastrpc_invoke_ctx *ctx) -{ - struct device *dev = ctx->fl->sctx->dev; - int i, err; - - for (i = 0; i < ctx->nscalars; ++i) { -<<<<<<< -======= - /* Make sure reserved field is set to 0 */ - if (ctx->args[i].reserved) - return -EINVAL; ->>>>>>> - - if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1 || - ctx->args[i].length == 0) - continue; - - err = fastrpc_map_create(ctx->fl, ctx->args[i].fd, -<<<<<<< - ctx->args[i].length, &ctx->maps[i]); -======= - ctx->args[i].length, ctx->args[i].attr, &ctx->maps[i]); ->>>>>>> - if (err) { - dev_err(dev, "Error Creating map %d\n", err); - return -EINVAL; - } - - } - return 0; -} - -<<<<<<< -======= -static struct fastrpc_invoke_buf *fastrpc_invoke_buf_start(union fastrpc_remote_arg *pra, int len) -{ - return (struct fastrpc_invoke_buf *)(&pra[len]); -} - -static struct fastrpc_phy_page *fastrpc_phy_page_start(struct fastrpc_invoke_buf *buf, int len) -{ - return (struct fastrpc_phy_page *)(&buf[len]); -} - ->>>>>>> -static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) -{ - struct device *dev = ctx->fl->sctx->dev; - struct fastrpc_remote_arg *rpra; - struct fastrpc_invoke_buf *list; - struct fastrpc_phy_page *pages; -<<<<<<< - int inbufs, i, err = 0; - u64 rlen, pkt_size; - uintptr_t args; - int metalen; - - -======= - int inbufs, i, oix, err = 0; - u64 len, rlen, pkt_size; - u64 pg_start, pg_end; - uintptr_t args; - int metalen; - ->>>>>>> - inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); - metalen = fastrpc_get_meta_size(ctx); - pkt_size = fastrpc_get_payload_size(ctx, metalen); - - err = fastrpc_create_maps(ctx); - if (err) - return err; - - ctx->msg_sz = pkt_size; - - err = fastrpc_buf_alloc(ctx->fl, dev, pkt_size, &ctx->buf); - if (err) - return err; - - rpra = ctx->buf->virt; -<<<<<<< - list = ctx->buf->virt + ctx->nscalars * sizeof(*rpra); - pages = ctx->buf->virt + ctx->nscalars * (sizeof(*list) + - sizeof(*rpra)); -======= - list = fastrpc_invoke_buf_start(rpra, ctx->nscalars); - pages = fastrpc_phy_page_start(list, ctx->nscalars); ->>>>>>> - args = (uintptr_t)ctx->buf->virt + metalen; - rlen = pkt_size - metalen; - ctx->rpra = rpra; - -<<<<<<< - for (i = 0; i < ctx->nbufs; ++i) { - u64 len = ctx->args[i].length; -======= - for (oix = 0; oix < ctx->nbufs; ++oix) { - int mlen; - - i = ctx->olaps[oix].raix; - len = ctx->args[i].length; ->>>>>>> - - rpra[i].pv = 0; - rpra[i].len = len; - list[i].num = len ? 1 : 0; - list[i].pgidx = i; - - if (!len) - continue; - -<<<<<<< - if (ctx->maps[i]) { - struct vm_area_struct *vma = NULL; - - rpra[i].pv = (u64) ctx->args[i].ptr; - pages[i].addr = ctx->maps[i]->phys; - - mmap_read_lock(current->mm); - vma = find_vma(current->mm, ctx->args[i].ptr); - if (vma) - pages[i].addr += ctx->args[i].ptr - - vma->vm_start; - mmap_read_unlock(current->mm); - - pg_start = (ctx->args[i].ptr & PAGE_MASK) >> PAGE_SHIFT; - pg_end = ((ctx->args[i].ptr + len - 1) & PAGE_MASK) >> - PAGE_SHIFT; - pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - - } else { - - if (ctx->olaps[oix].offset == 0) { - rlen -= ALIGN(args, FASTRPC_ALIGN) - args; - args = ALIGN(args, FASTRPC_ALIGN); - } - - mlen = ctx->olaps[oix].mend - ctx->olaps[oix].mstart; - - if (rlen < mlen) - goto bail; - - rpra[i].pv = args - ctx->olaps[oix].offset; - pages[i].addr = ctx->buf->phys - - ctx->olaps[oix].offset + - (pkt_size - rlen); - pages[i].addr = pages[i].addr & PAGE_MASK; - - pg_start = (args & PAGE_MASK) >> PAGE_SHIFT; - pg_end = ((args + len - 1) & PAGE_MASK) >> PAGE_SHIFT; - pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - args = args + mlen; - rlen -= mlen; -======= - pages[i].size = roundup(len, PAGE_SIZE); - - if (ctx->maps[i]) { - rpra[i].pv = (u64) ctx->args[i].ptr; - pages[i].addr = ctx->maps[i]->phys; - } else { - rlen -= ALIGN(args, FASTRPC_ALIGN) - args; - args = ALIGN(args, FASTRPC_ALIGN); - if (rlen < len) - goto bail; - - rpra[i].pv = args; - pages[i].addr = ctx->buf->phys + (pkt_size - rlen); - pages[i].addr = pages[i].addr & PAGE_MASK; - args = args + len; - rlen -= len; ->>>>>>> - } - - if (i < inbufs && !ctx->maps[i]) { - void *dst = (void *)(uintptr_t)rpra[i].pv; - void *src = (void *)(uintptr_t)ctx->args[i].ptr; - - if (!kernel) { - if (copy_from_user(dst, (void __user *)src, - len)) { - err = -EFAULT; - goto bail; - } - } else { - memcpy(dst, src, len); - } - } - } - - for (i = ctx->nbufs; i < ctx->nscalars; ++i) { - rpra[i].pv = (u64) ctx->args[i].ptr; - rpra[i].len = ctx->args[i].length; - list[i].num = ctx->args[i].length ? 1 : 0; - list[i].pgidx = i; - pages[i].addr = ctx->maps[i]->phys; - pages[i].size = ctx->maps[i]->size; - } - -bail: - if (err) - dev_err(dev, "Error: get invoke args failed:%d\n", err); - - return err; -} - -static int fastrpc_put_args(struct fastrpc_invoke_ctx *ctx, - u32 kernel) -{ - struct fastrpc_remote_arg *rpra = ctx->rpra; -<<<<<<< - int i, inbufs; - - inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); -======= - struct fastrpc_user *fl = ctx->fl; - struct fastrpc_map *mmap = NULL; - struct fastrpc_invoke_buf *list; - struct fastrpc_phy_page *pages; - u64 *fdlist; - int i, inbufs, outbufs, handles; - - inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); - outbufs = REMOTE_SCALARS_OUTBUFS(ctx->sc); - handles = REMOTE_SCALARS_INHANDLES(ctx->sc) + REMOTE_SCALARS_OUTHANDLES(ctx->sc); - list = fastrpc_invoke_buf_start(rpra, ctx->nscalars); - pages = fastrpc_phy_page_start(list, ctx->nscalars); - fdlist = (uint64_t *)(pages + inbufs + outbufs + handles); ->>>>>>> - - for (i = inbufs; i < ctx->nbufs; ++i) { - void *src = (void *)(uintptr_t)rpra[i].pv; - void *dst = (void *)(uintptr_t)ctx->args[i].ptr; - u64 len = rpra[i].len; - - if (!kernel) { - if (copy_to_user((void __user *)dst, src, len)) - return -EFAULT; - } else { - memcpy(dst, src, len); - } - } - -<<<<<<< -======= - for (i = 0; i < FASTRPC_MAX_FDLIST; i++) { - if (!fdlist[i]) - break; - if (!fastrpc_map_lookup(fl, (int)fdlist[i], &mmap)) - fastrpc_map_put(mmap); - } - ->>>>>>> - return 0; -} - -static int fastrpc_invoke_send(struct fastrpc_session_ctx *sctx, - struct fastrpc_invoke_ctx *ctx, - u32 kernel, uint32_t handle) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_user *fl = ctx->fl; - struct fastrpc_msg *msg = &ctx->msg; -<<<<<<< -======= - int ret; ->>>>>>> - - cctx = fl->cctx; - msg->pid = fl->tgid; - msg->tid = current->pid; - - if (kernel) - msg->pid = 0; - - msg->ctx = ctx->ctxid | fl->pd; - msg->handle = handle; - msg->sc = ctx->sc; - msg->addr = ctx->buf ? ctx->buf->phys : 0; - msg->size = roundup(ctx->msg_sz, PAGE_SIZE); - fastrpc_context_get(ctx); - -<<<<<<< - ret = rpmsg_send(cctx->rpdev->ept, (void *)msg, sizeof(*msg)); - - if (ret) - fastrpc_context_put(ctx); - - return ret; - -======= - return rpmsg_send(cctx->rpdev->ept, (void *)msg, sizeof(*msg)); ->>>>>>> -} - -static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel, - u32 handle, u32 sc, - struct fastrpc_invoke_args *args) -{ - struct fastrpc_invoke_ctx *ctx = NULL; - int err = 0; - - if (!fl->sctx) - return -EINVAL; - -<<<<<<< -======= - if (!fl->cctx->rpdev) - return -EPIPE; - - if (handle == FASTRPC_INIT_HANDLE && !kernel) { - dev_warn_ratelimited(fl->sctx->dev, "user app trying to send a kernel RPC message (%d)\n", handle); - return -EPERM; - } - ->>>>>>> - ctx = fastrpc_context_alloc(fl, kernel, sc, args); - if (IS_ERR(ctx)) - return PTR_ERR(ctx); - - if (ctx->nscalars) { - err = fastrpc_get_args(kernel, ctx); - if (err) - goto bail; - } -<<<<<<< -======= - - /* make sure that all CPU memory writes are seen by DSP */ - dma_wmb(); ->>>>>>> - /* Send invoke buffer to remote dsp */ - err = fastrpc_invoke_send(fl->sctx, ctx, kernel, handle); - if (err) - goto bail; - -<<<<<<< - /* Wait for remote dsp to respond or time out */ - err = wait_for_completion_interruptible(&ctx->work); -======= - if (kernel) { - if (!wait_for_completion_timeout(&ctx->work, 10 * HZ)) - err = -ETIMEDOUT; - } else { - err = wait_for_completion_interruptible(&ctx->work); - } - ->>>>>>> - if (err) - goto bail; - - /* Check the response from remote dsp */ - err = ctx->retval; - if (err) - goto bail; - - if (ctx->nscalars) { -<<<<<<< -======= - /* make sure that all memory writes by DSP are seen by CPU */ - dma_rmb(); ->>>>>>> - /* populate all the output buffers with results */ - err = fastrpc_put_args(ctx, kernel); - if (err) - goto bail; - } - -bail: -<<<<<<< - /* We are done with this compute context, remove it from pending list */ - spin_lock(&fl->lock); - list_del(&ctx->node); - spin_unlock(&fl->lock); - fastrpc_context_put(ctx); - -======= - if (err != -ERESTARTSYS && err != -ETIMEDOUT) { - /* We are done with this compute context */ - spin_lock(&fl->lock); - list_del(&ctx->node); - spin_unlock(&fl->lock); - fastrpc_context_put(ctx); - } ->>>>>>> - if (err) - dev_dbg(fl->sctx->dev, "Error: Invoke Failed %d\n", err); - - return err; -} - -<<<<<<< -======= -static bool is_session_rejected(struct fastrpc_user *fl, bool unsigned_pd_request) -{ - /* Check if the device node is non-secure and channel is secure*/ - if (!fl->is_secure_dev && fl->cctx->secure) { - /* - * Allow untrusted applications to offload only to Unsigned PD when - * channel is configured as secure and block untrusted apps on channel - * that does not support unsigned PD offload - */ - if (!fl->cctx->unsigned_support || !unsigned_pd_request) { - dev_err(&fl->cctx->rpdev->dev, "Error: Untrusted application trying to offload to signed PD"); - return true; - } - } - - return false; -} - -static int fastrpc_init_create_process(struct fastrpc_user *fl, - char __user *argp) -{ - struct fastrpc_init_create init; - struct fastrpc_invoke_args *args; - struct fastrpc_phy_page pages[1]; - struct fastrpc_map *map = NULL; - struct fastrpc_buf *imem = NULL; - int memlen; - int err; - struct { - int pgid; - u32 namelen; - u32 filelen; - u32 pageslen; - u32 attrs; - u32 siglen; - } inbuf; - u32 sc; - bool unsigned_module = false; - - args = kcalloc(FASTRPC_CREATE_PROCESS_NARGS, sizeof(*args), GFP_KERNEL); - if (!args) - return -ENOMEM; - - if (copy_from_user(&init, argp, sizeof(init))) { - err = -EFAULT; - goto err; - } - - if (init.attrs & FASTRPC_MODE_UNSIGNED_MODULE) - unsigned_module = true; - - if (is_session_rejected(fl, unsigned_module)) { - err = -ECONNREFUSED; - goto err; - } - - if (init.filelen > INIT_FILELEN_MAX) { - err = -EINVAL; - goto err; - } - - inbuf.pgid = fl->tgid; - inbuf.namelen = strlen(current->comm) + 1; - inbuf.filelen = init.filelen; - inbuf.pageslen = 1; - inbuf.attrs = init.attrs; - inbuf.siglen = init.siglen; - fl->pd = USER_PD; - - if (init.filelen && init.filefd) { - err = fastrpc_map_create(fl, init.filefd, init.filelen, 0, &map); - if (err) - goto err; - } - - memlen = ALIGN(max(INIT_FILELEN_MAX, (int)init.filelen * 4), - 1024 * 1024); - err = fastrpc_buf_alloc(fl, fl->sctx->dev, memlen, - &imem); - if (err) - goto err_alloc; - - fl->init_mem = imem; - args[0].ptr = (u64)(uintptr_t)&inbuf; - args[0].length = sizeof(inbuf); - args[0].fd = -1; - - args[1].ptr = (u64)(uintptr_t)current->comm; - args[1].length = inbuf.namelen; - args[1].fd = -1; - - args[2].ptr = (u64) init.file; - args[2].length = inbuf.filelen; - args[2].fd = init.filefd; - - pages[0].addr = imem->phys; - pages[0].size = imem->size; - - args[3].ptr = (u64)(uintptr_t) pages; - args[3].length = 1 * sizeof(*pages); - args[3].fd = -1; - - args[4].ptr = (u64)(uintptr_t)&inbuf.attrs; - args[4].length = sizeof(inbuf.attrs); - args[4].fd = -1; - - args[5].ptr = (u64)(uintptr_t) &inbuf.siglen; - args[5].length = sizeof(inbuf.siglen); - args[5].fd = -1; - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE, 4, 0); - if (init.attrs) - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE_ATTR, 6, 0); - - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, args); - if (err) - goto err_invoke; - - kfree(args); - - return 0; - -err_invoke: - fl->init_mem = NULL; - fastrpc_buf_free(imem); -err_alloc: - if (map) { - spin_lock(&fl->lock); - list_del(&map->node); - spin_unlock(&fl->lock); - fastrpc_map_put(map); - } -err: - kfree(args); - - return err; -} - ->>>>>>> -static struct fastrpc_session_ctx *fastrpc_session_alloc( - struct fastrpc_channel_ctx *cctx) -{ - struct fastrpc_session_ctx *session = NULL; - unsigned long flags; - int i; - - spin_lock_irqsave(&cctx->lock, flags); - for (i = 0; i < cctx->sesscount; i++) { - if (!cctx->session[i].used && cctx->session[i].valid) { - cctx->session[i].used = true; - session = &cctx->session[i]; - break; - } - } - spin_unlock_irqrestore(&cctx->lock, flags); - - return session; -} - -static void fastrpc_session_free(struct fastrpc_channel_ctx *cctx, - struct fastrpc_session_ctx *session) -{ - unsigned long flags; - - spin_lock_irqsave(&cctx->lock, flags); - session->used = false; - spin_unlock_irqrestore(&cctx->lock, flags); -} - -static int fastrpc_release_current_dsp_process(struct fastrpc_user *fl) -{ - struct fastrpc_invoke_args args[1]; - int tgid = 0; - u32 sc; - - tgid = fl->tgid; - args[0].ptr = (u64)(uintptr_t) &tgid; - args[0].length = sizeof(tgid); - args[0].fd = -1; - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_RELEASE, 1, 0); - - return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, &args[0]); -} - -static int fastrpc_device_release(struct inode *inode, struct file *file) -{ - struct fastrpc_user *fl = (struct fastrpc_user *)file->private_data; - struct fastrpc_channel_ctx *cctx = fl->cctx; - struct fastrpc_invoke_ctx *ctx, *n; - struct fastrpc_map *map, *m; -<<<<<<< -======= - struct fastrpc_buf *buf, *b; - unsigned long flags; ->>>>>>> - - fastrpc_release_current_dsp_process(fl); - - spin_lock_irqsave(&cctx->lock, flags); - list_del(&fl->user); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (fl->init_mem) - fastrpc_buf_free(fl->init_mem); - - list_for_each_entry_safe(ctx, n, &fl->pending, node) { - list_del(&ctx->node); - fastrpc_context_put(ctx); - } - - list_for_each_entry_safe(map, m, &fl->maps, node) { - list_del(&map->node); - fastrpc_map_put(map); - } - - list_for_each_entry_safe(buf, b, &fl->mmaps, node) { - list_del(&buf->node); - fastrpc_buf_free(buf); - } - - if (fl->init_mem) - fastrpc_buf_free(fl->init_mem); - - list_for_each_entry_safe(ctx, n, &fl->pending, node) { - list_del(&ctx->node); - fastrpc_context_put(ctx); - } - - list_for_each_entry_safe(map, m, &fl->maps, node) { - list_del(&map->node); - fastrpc_map_put(map); - } - - fastrpc_session_free(cctx, fl->sctx); - fastrpc_channel_ctx_put(cctx); - - mutex_destroy(&fl->mutex); - kfree(fl); - file->private_data = NULL; - - return 0; -} - -static int fastrpc_device_open(struct inode *inode, struct file *filp) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_device *fdevice; - struct fastrpc_user *fl = NULL; - unsigned long flags; - - fdevice = miscdev_to_fdevice(filp->private_data); - cctx = fdevice->cctx; - - fl = kzalloc(sizeof(*fl), GFP_KERNEL); - if (!fl) - return -ENOMEM; - - /* Released in fastrpc_device_release() */ - fastrpc_channel_ctx_get(cctx); - - filp->private_data = fl; - spin_lock_init(&fl->lock); - mutex_init(&fl->mutex); - INIT_LIST_HEAD(&fl->pending); - INIT_LIST_HEAD(&fl->maps); - INIT_LIST_HEAD(&fl->mmaps); - INIT_LIST_HEAD(&fl->user); - fl->tgid = current->tgid; - fl->cctx = cctx; - fl->is_secure_dev = fdevice->secure; - - fl->sctx = fastrpc_session_alloc(cctx); - if (!fl->sctx) { - dev_err(&cctx->rpdev->dev, "No session available\n"); - mutex_destroy(&fl->mutex); - kfree(fl); - - return -EBUSY; - } - - spin_lock_irqsave(&cctx->lock, flags); - list_add_tail(&fl->user, &cctx->users); - spin_unlock_irqrestore(&cctx->lock, flags); - - return 0; -} - -<<<<<<< -======= -static int fastrpc_dmabuf_alloc(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_alloc_dma_buf bp; - DEFINE_DMA_BUF_EXPORT_INFO(exp_info); - struct fastrpc_buf *buf = NULL; - int err; - - if (copy_from_user(&bp, argp, sizeof(bp))) - return -EFAULT; - - err = fastrpc_buf_alloc(fl, fl->sctx->dev, bp.size, &buf); - if (err) - return err; - exp_info.ops = &fastrpc_dma_buf_ops; - exp_info.size = bp.size; - exp_info.flags = O_RDWR; - exp_info.priv = buf; - buf->dmabuf = dma_buf_export(&exp_info); - if (IS_ERR(buf->dmabuf)) { - err = PTR_ERR(buf->dmabuf); - fastrpc_buf_free(buf); - return err; - } - - bp.fd = dma_buf_fd(buf->dmabuf, O_ACCMODE); - if (bp.fd < 0) { - dma_buf_put(buf->dmabuf); - return -EINVAL; - } - - if (copy_to_user(argp, &bp, sizeof(bp))) { - /* - * The usercopy failed, but we can't do much about it, as - * dma_buf_fd() already called fd_install() and made the - * file descriptor accessible for the current process. It - * might already be closed and dmabuf no longer valid when - * we reach this point. Therefore "leak" the fd and rely on - * the process exit path to do any required cleanup. - */ - return -EFAULT; - } - - return 0; -} - -static int fastrpc_init_attach(struct fastrpc_user *fl, int pd) -{ - struct fastrpc_invoke_args args[1]; - int tgid = fl->tgid; - u32 sc; - - args[0].ptr = (u64)(uintptr_t) &tgid; - args[0].length = sizeof(tgid); - args[0].fd = -1; - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_ATTACH, 1, 0); - fl->pd = pd; - - return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, &args[0]); -} - ->>>>>>> -static int fastrpc_invoke(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args *args = NULL; - struct fastrpc_invoke inv; - u32 nscalars; - int err; - - if (copy_from_user(&inv, argp, sizeof(inv))) - return -EFAULT; - - /* nscalars is truncated here to max supported value */ - nscalars = REMOTE_SCALARS_LENGTH(inv.sc); - if (nscalars) { - args = kcalloc(nscalars, sizeof(*args), GFP_KERNEL); - if (!args) - return -ENOMEM; - - if (copy_from_user(args, (void __user *)(uintptr_t)inv.args, - nscalars * sizeof(*args))) { - kfree(args); - return -EFAULT; - } - } - - err = fastrpc_internal_invoke(fl, false, inv.handle, inv.sc, args); - kfree(args); - - return err; -} - -<<<<<<< -======= -static int fastrpc_get_info_from_dsp(struct fastrpc_user *fl, uint32_t *dsp_attr_buf, - uint32_t dsp_attr_buf_len) -{ - struct fastrpc_invoke_args args[2] = { 0 }; - - /* Capability filled in userspace */ - dsp_attr_buf[0] = 0; - - args[0].ptr = (u64)(uintptr_t)&dsp_attr_buf_len; - args[0].length = sizeof(dsp_attr_buf_len); - args[0].fd = -1; - args[1].ptr = (u64)(uintptr_t)&dsp_attr_buf[1]; - args[1].length = dsp_attr_buf_len; - args[1].fd = -1; - fl->pd = 1; - - return fastrpc_internal_invoke(fl, true, FASTRPC_DSP_UTILITIES_HANDLE, - FASTRPC_SCALARS(0, 1, 1), args); -} - -static int fastrpc_get_info_from_kernel(struct fastrpc_ioctl_capability *cap, - struct fastrpc_user *fl) -{ - struct fastrpc_channel_ctx *cctx = fl->cctx; - uint32_t attribute_id = cap->attribute_id; - uint32_t *dsp_attributes; - unsigned long flags; - uint32_t domain = cap->domain; - int err; - - spin_lock_irqsave(&cctx->lock, flags); - /* check if we already have queried dsp for attributes */ - if (cctx->valid_attributes) { - spin_unlock_irqrestore(&cctx->lock, flags); - goto done; - } - spin_unlock_irqrestore(&cctx->lock, flags); - - dsp_attributes = kzalloc(FASTRPC_MAX_DSP_ATTRIBUTES_LEN, GFP_KERNEL); - if (!dsp_attributes) - return -ENOMEM; - - err = fastrpc_get_info_from_dsp(fl, dsp_attributes, FASTRPC_MAX_DSP_ATTRIBUTES_LEN); - if (err == DSP_UNSUPPORTED_API) { - dev_info(&cctx->rpdev->dev, - "Warning: DSP capabilities not supported on domain: %d\n", domain); - kfree(dsp_attributes); - return -EOPNOTSUPP; - } else if (err) { - dev_err(&cctx->rpdev->dev, "Error: dsp information is incorrect err: %d\n", err); - kfree(dsp_attributes); - return err; - } - - spin_lock_irqsave(&cctx->lock, flags); - memcpy(cctx->dsp_attributes, dsp_attributes, FASTRPC_MAX_DSP_ATTRIBUTES_LEN); - cctx->valid_attributes = true; - spin_unlock_irqrestore(&cctx->lock, flags); - kfree(dsp_attributes); -done: - cap->capability = cctx->dsp_attributes[attribute_id]; - return 0; -} - -static int fastrpc_get_dsp_info(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_ioctl_capability cap = {0}; - int err = 0; - - if (copy_from_user(&cap, argp, sizeof(cap))) - return -EFAULT; - - cap.capability = 0; - if (cap.domain >= FASTRPC_DEV_MAX) { - dev_err(&fl->cctx->rpdev->dev, "Error: Invalid domain id:%d, err:%d\n", - cap.domain, err); - return -ECHRNG; - } - - /* Fastrpc Capablities does not support modem domain */ - if (cap.domain == MDSP_DOMAIN_ID) { - dev_err(&fl->cctx->rpdev->dev, "Error: modem not supported %d\n", err); - return -ECHRNG; - } - - if (cap.attribute_id >= FASTRPC_MAX_DSP_ATTRIBUTES) { - dev_err(&fl->cctx->rpdev->dev, "Error: invalid attribute: %d, err: %d\n", - cap.attribute_id, err); - return -EOVERFLOW; - } - - err = fastrpc_get_info_from_kernel(&cap, fl); - if (err) - return err; - - if (copy_to_user(argp, &cap.capability, sizeof(cap.capability))) - return -EFAULT; - - return 0; -} - -static int fastrpc_req_munmap_impl(struct fastrpc_user *fl, - struct fastrpc_req_munmap *req) -{ - struct fastrpc_invoke_args args[1] = { [0] = { 0 } }; - struct fastrpc_buf *buf, *b; - struct fastrpc_munmap_req_msg req_msg; - struct device *dev = fl->sctx->dev; - int err; - u32 sc; - - spin_lock(&fl->lock); - list_for_each_entry_safe(buf, b, &fl->mmaps, node) { - if ((buf->raddr == req->vaddrout) && (buf->size == req->size)) - break; - buf = NULL; - } - spin_unlock(&fl->lock); - - if (!buf) { - dev_err(dev, "mmap not in list\n"); - return -EINVAL; - } - - req_msg.pgid = fl->tgid; - req_msg.size = buf->size; - req_msg.vaddr = buf->raddr; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MUNMAP, 1, 0); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - if (!err) { - dev_dbg(dev, "unmmap\tpt 0x%09lx OK\n", buf->raddr); - spin_lock(&fl->lock); - list_del(&buf->node); - spin_unlock(&fl->lock); - fastrpc_buf_free(buf); - } else { - dev_err(dev, "unmmap\tpt 0x%09lx ERROR\n", buf->raddr); - } - - return err; -} - -static int fastrpc_req_munmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_req_munmap req; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - return fastrpc_req_munmap_impl(fl, &req); -} - -static int fastrpc_req_mmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args args[3] = { [0 ... 2] = { 0 } }; - struct fastrpc_buf *buf = NULL; - struct fastrpc_mmap_req_msg req_msg; - struct fastrpc_mmap_rsp_msg rsp_msg; - struct fastrpc_req_munmap req_unmap; - struct fastrpc_phy_page pages; - struct fastrpc_req_mmap req; - struct device *dev = fl->sctx->dev; - int err; - u32 sc; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - if (req.flags != ADSP_MMAP_ADD_PAGES) { - dev_err(dev, "flag not supported 0x%x\n", req.flags); - return -EINVAL; - } - - if (req.vaddrin) { - dev_err(dev, "adding user allocated pages is not supported\n"); - return -EINVAL; - } - - err = fastrpc_buf_alloc(fl, fl->sctx->dev, req.size, &buf); - if (err) { - dev_err(dev, "failed to allocate buffer\n"); - return err; - } - - req_msg.pgid = fl->tgid; - req_msg.flags = req.flags; - req_msg.vaddr = req.vaddrin; - req_msg.num = sizeof(pages); - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - pages.addr = buf->phys; - pages.size = buf->size; - - args[1].ptr = (u64) (uintptr_t) &pages; - args[1].length = sizeof(pages); - - args[2].ptr = (u64) (uintptr_t) &rsp_msg; - args[2].length = sizeof(rsp_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MMAP, 2, 1); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - if (err) { - dev_err(dev, "mmap error (len 0x%08llx)\n", buf->size); - goto err_invoke; - } - - /* update the buffer to be able to deallocate the memory on the DSP */ - buf->raddr = (uintptr_t) rsp_msg.vaddr; - - /* let the client know the address to use */ - req.vaddrout = rsp_msg.vaddr; - - spin_lock(&fl->lock); - list_add_tail(&buf->node, &fl->mmaps); - spin_unlock(&fl->lock); - - if (copy_to_user((void __user *)argp, &req, sizeof(req))) { - /* unmap the memory and release the buffer */ - req_unmap.vaddrout = buf->raddr; - req_unmap.size = buf->size; - fastrpc_req_munmap_impl(fl, &req_unmap); - return -EFAULT; - } - - dev_dbg(dev, "mmap\t\tpt 0x%09lx OK [len 0x%08llx]\n", - buf->raddr, buf->size); - - return 0; - -err_invoke: - fastrpc_buf_free(buf); - - return err; -} - -static int fastrpc_req_mem_unmap_impl(struct fastrpc_user *fl, struct fastrpc_mem_unmap *req) -{ - struct fastrpc_invoke_args args[1] = { [0] = { 0 } }; - struct fastrpc_map *map = NULL, *m; - struct fastrpc_mem_unmap_req_msg req_msg = { 0 }; - int err = 0; - u32 sc; - struct device *dev = fl->sctx->dev; - - spin_lock(&fl->lock); - list_for_each_entry_safe(map, m, &fl->maps, node) { - if ((req->fd < 0 || map->fd == req->fd) && (map->raddr == req->vaddr)) - break; - map = NULL; - } - - spin_unlock(&fl->lock); - - if (!map) { - dev_err(dev, "map not in list\n"); - return -EINVAL; - } - - req_msg.pgid = fl->tgid; - req_msg.len = map->len; - req_msg.vaddrin = map->raddr; - req_msg.fd = map->fd; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_UNMAP, 1, 0); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - fastrpc_map_put(map); - if (err) - dev_err(dev, "unmmap\tpt fd = %d, 0x%09llx error\n", map->fd, map->raddr); - - return err; -} - -static int fastrpc_req_mem_unmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_mem_unmap req; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - return fastrpc_req_mem_unmap_impl(fl, &req); -} - -static int fastrpc_req_mem_map(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args args[4] = { [0 ... 3] = { 0 } }; - struct fastrpc_mem_map_req_msg req_msg = { 0 }; - struct fastrpc_mmap_rsp_msg rsp_msg = { 0 }; - struct fastrpc_mem_unmap req_unmap = { 0 }; - struct fastrpc_phy_page pages = { 0 }; - struct fastrpc_mem_map req; - struct device *dev = fl->sctx->dev; - struct fastrpc_map *map = NULL; - int err; - u32 sc; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - /* create SMMU mapping */ - err = fastrpc_map_create(fl, req.fd, req.length, 0, &map); - if (err) { - dev_err(dev, "failed to map buffer, fd = %d\n", req.fd); - return err; - } - - req_msg.pgid = fl->tgid; - req_msg.fd = req.fd; - req_msg.offset = req.offset; - req_msg.vaddrin = req.vaddrin; - map->va = (void *) (uintptr_t) req.vaddrin; - req_msg.flags = req.flags; - req_msg.num = sizeof(pages); - req_msg.data_len = 0; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - pages.addr = map->phys; - pages.size = map->size; - - args[1].ptr = (u64) (uintptr_t) &pages; - args[1].length = sizeof(pages); - - args[2].ptr = (u64) (uintptr_t) &pages; - args[2].length = 0; - - args[3].ptr = (u64) (uintptr_t) &rsp_msg; - args[3].length = sizeof(rsp_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_MAP, 3, 1); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, &args[0]); - if (err) { - dev_err(dev, "mem mmap error, fd %d, vaddr %llx, size %lld\n", - req.fd, req.vaddrin, map->size); - goto err_invoke; - } - - /* update the buffer to be able to deallocate the memory on the DSP */ - map->raddr = rsp_msg.vaddr; - - /* let the client know the address to use */ - req.vaddrout = rsp_msg.vaddr; - - if (copy_to_user((void __user *)argp, &req, sizeof(req))) { - /* unmap the memory and release the buffer */ - req_unmap.vaddr = (uintptr_t) rsp_msg.vaddr; - req_unmap.length = map->size; - fastrpc_req_mem_unmap_impl(fl, &req_unmap); - return -EFAULT; - } - - return 0; - -err_invoke: - fastrpc_map_put(map); - - return err; -} - ->>>>>>> -static long fastrpc_device_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - struct fastrpc_user *fl = (struct fastrpc_user *)file->private_data; - char __user *argp = (char __user *)arg; - int err; - - switch (cmd) { - case FASTRPC_IOCTL_INVOKE: - err = fastrpc_invoke(fl, argp); - break; -<<<<<<< -======= - case FASTRPC_IOCTL_INIT_ATTACH: - err = fastrpc_init_attach(fl, AUDIO_PD); - break; - case FASTRPC_IOCTL_INIT_ATTACH_SNS: - err = fastrpc_init_attach(fl, SENSORS_PD); - break; - case FASTRPC_IOCTL_INIT_CREATE: - err = fastrpc_init_create_process(fl, argp); - break; - case FASTRPC_IOCTL_ALLOC_DMA_BUFF: - err = fastrpc_dmabuf_alloc(fl, argp); - break; - case FASTRPC_IOCTL_MMAP: - err = fastrpc_req_mmap(fl, argp); - break; - case FASTRPC_IOCTL_MUNMAP: - err = fastrpc_req_munmap(fl, argp); - break; - case FASTRPC_IOCTL_MEM_MAP: - err = fastrpc_req_mem_map(fl, argp); - break; - case FASTRPC_IOCTL_MEM_UNMAP: - err = fastrpc_req_mem_unmap(fl, argp); - break; - case FASTRPC_IOCTL_GET_DSP_INFO: - err = fastrpc_get_dsp_info(fl, argp); - break; ->>>>>>> - default: - err = -ENOTTY; - break; - } - - return err; -} - -static const struct file_operations fastrpc_fops = { - .open = fastrpc_device_open, - .release = fastrpc_device_release, - .unlocked_ioctl = fastrpc_device_ioctl, - .compat_ioctl = fastrpc_device_ioctl, -}; - -static int fastrpc_cb_probe(struct platform_device *pdev) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_session_ctx *sess; - struct device *dev = &pdev->dev; - int i, sessions = 0; - unsigned long flags; - int rc; - - cctx = dev_get_drvdata(dev->parent); - if (!cctx) - return -EINVAL; - - of_property_read_u32(dev->of_node, "qcom,nsessions", &sessions); - - spin_lock_irqsave(&cctx->lock, flags); - sess = &cctx->session[cctx->sesscount]; - sess->used = false; - sess->valid = true; - sess->dev = dev; - dev_set_drvdata(dev, sess); - - if (of_property_read_u32(dev->of_node, "reg", &sess->sid)) - dev_info(dev, "FastRPC Session ID not specified in DT\n"); - - if (sessions > 0) { - struct fastrpc_session_ctx *dup_sess; - - for (i = 1; i < sessions; i++) { - if (cctx->sesscount++ >= FASTRPC_MAX_SESSIONS) - break; - dup_sess = &cctx->session[cctx->sesscount]; - memcpy(dup_sess, sess, sizeof(*dup_sess)); - } - } - cctx->sesscount++; - spin_unlock_irqrestore(&cctx->lock, flags); - rc = dma_set_mask(dev, DMA_BIT_MASK(32)); - if (rc) { - dev_err(dev, "32-bit DMA enable failed\n"); - return rc; - } - - return 0; -} - -static int fastrpc_cb_remove(struct platform_device *pdev) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(pdev->dev.parent); - struct fastrpc_session_ctx *sess = dev_get_drvdata(&pdev->dev); - unsigned long flags; - int i; - - spin_lock_irqsave(&cctx->lock, flags); - for (i = 1; i < FASTRPC_MAX_SESSIONS; i++) { - if (cctx->session[i].sid == sess->sid) { - cctx->session[i].valid = false; - cctx->sesscount--; - } - } - spin_unlock_irqrestore(&cctx->lock, flags); - - return 0; -} - -static const struct of_device_id fastrpc_match_table[] = { - { .compatible = "qcom,fastrpc-compute-cb", }, - {} -}; - -static struct platform_driver fastrpc_cb_driver = { - .probe = fastrpc_cb_probe, - .remove = fastrpc_cb_remove, - .driver = { - .name = "qcom,fastrpc-cb", - .of_match_table = fastrpc_match_table, - .suppress_bind_attrs = true, - }, -}; - -static int fastrpc_device_register(struct device *dev, struct fastrpc_channel_ctx *cctx, - bool is_secured, const char *domain) -{ - struct fastrpc_device *fdev; - int err; - - fdev = devm_kzalloc(dev, sizeof(*fdev), GFP_KERNEL); - if (!fdev) - return -ENOMEM; - - fdev->secure = is_secured; - fdev->cctx = cctx; - fdev->miscdev.minor = MISC_DYNAMIC_MINOR; - fdev->miscdev.fops = &fastrpc_fops; - fdev->miscdev.name = devm_kasprintf(dev, GFP_KERNEL, "fastrpc-%s%s", - domain, is_secured ? "-secure" : ""); - err = misc_register(&fdev->miscdev); - if (!err) { - if (is_secured) - cctx->secure_fdevice = fdev; - else - cctx->fdevice = fdev; - } - - return err; -} - -static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) -{ - struct device *rdev = &rpdev->dev; - struct fastrpc_channel_ctx *data; - int i, err, domain_id = -1, vmcount; - const char *domain; - bool secure_dsp; - unsigned int vmids[FASTRPC_MAX_VMIDS]; - - err = of_property_read_string(rdev->of_node, "label", &domain); - if (err) { - dev_info(rdev, "FastRPC Domain not specified in DT\n"); - return err; - } - - for (i = 0; i <= CDSP_DOMAIN_ID; i++) { - if (!strcmp(domains[i], domain)) { - domain_id = i; - break; - } - } - - if (domain_id < 0) { - dev_info(rdev, "FastRPC Invalid Domain ID %d\n", domain_id); - return -EINVAL; - } - - vmcount = of_property_read_variable_u32_array(rdev->of_node, - "qcom,vmids", &vmids[0], 0, FASTRPC_MAX_VMIDS); - if (vmcount < 0) - vmcount = 0; - else if (!qcom_scm_is_available()) - return -EPROBE_DEFER; - - data = kzalloc(sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - if (vmcount) { - data->vmcount = vmcount; - data->perms = BIT(QCOM_SCM_VMID_HLOS); - for (i = 0; i < data->vmcount; i++) { - data->vmperms[i].vmid = vmids[i]; - data->vmperms[i].perm = QCOM_SCM_PERM_RWX; - } - } - - secure_dsp = !(of_property_read_bool(rdev->of_node, "qcom,non-secure-domain")); - data->secure = secure_dsp; - - switch (domain_id) { - case ADSP_DOMAIN_ID: - case MDSP_DOMAIN_ID: - case SDSP_DOMAIN_ID: - /* Unsigned PD offloading is only supported on CDSP*/ - data->unsigned_support = false; - err = fastrpc_device_register(rdev, data, secure_dsp, domains[domain_id]); - if (err) - goto fdev_error; - break; - case CDSP_DOMAIN_ID: - data->unsigned_support = true; - /* Create both device nodes so that we can allow both Signed and Unsigned PD */ - err = fastrpc_device_register(rdev, data, true, domains[domain_id]); - if (err) - goto fdev_error; - - err = fastrpc_device_register(rdev, data, false, domains[domain_id]); - if (err) - goto fdev_error; - break; - default: - err = -EINVAL; - goto fdev_error; - } - - kref_init(&data->refcount); - - dev_set_drvdata(&rpdev->dev, data); - dma_set_mask_and_coherent(rdev, DMA_BIT_MASK(32)); - INIT_LIST_HEAD(&data->users); - spin_lock_init(&data->lock); - idr_init(&data->ctx_idr); - data->domain_id = domain_id; - data->rpdev = rpdev; - - return of_platform_populate(rdev->of_node, NULL, NULL, rdev); -fdev_error: - kfree(data); - return err; -} - -static void fastrpc_notify_users(struct fastrpc_user *user) -{ - struct fastrpc_invoke_ctx *ctx; - - spin_lock(&user->lock); - list_for_each_entry(ctx, &user->pending, node) - complete(&ctx->work); - spin_unlock(&user->lock); -} - -static void fastrpc_notify_users(struct fastrpc_user *user) -{ - struct fastrpc_invoke_ctx *ctx; - - spin_lock(&user->lock); - list_for_each_entry(ctx, &user->pending, node) - complete(&ctx->work); - spin_unlock(&user->lock); -} - -static void fastrpc_rpmsg_remove(struct rpmsg_device *rpdev) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(&rpdev->dev); - struct fastrpc_user *user; -<<<<<<< - unsigned long flags; - - spin_lock_irqsave(&cctx->lock, flags); - list_for_each_entry(user, &cctx->users, user) - fastrpc_notify_users(user); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (cctx->fdevice) - misc_deregister(&cctx->fdevice->miscdev); - - if (cctx->secure_fdevice) - misc_deregister(&cctx->secure_fdevice->miscdev); -======= - - spin_lock(&cctx->lock); - list_for_each_entry(user, &cctx->users, user) - fastrpc_notify_users(user); - spin_unlock(&cctx->lock); ->>>>>>> - - of_platform_depopulate(&rpdev->dev); - - cctx->rpdev = NULL; - fastrpc_channel_ctx_put(cctx); -} - -static int fastrpc_rpmsg_callback(struct rpmsg_device *rpdev, void *data, - int len, void *priv, u32 addr) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(&rpdev->dev); - struct fastrpc_invoke_rsp *rsp = data; - struct fastrpc_invoke_ctx *ctx; - unsigned long flags; - unsigned long ctxid; - - if (len < sizeof(*rsp)) - return -EINVAL; - - ctxid = ((rsp->ctx & FASTRPC_CTXID_MASK) >> 4); - - spin_lock_irqsave(&cctx->lock, flags); - ctx = idr_find(&cctx->ctx_idr, ctxid); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (!ctx) { - dev_err(&rpdev->dev, "No context ID matches response\n"); - return -ENOENT; - } - - ctx->retval = rsp->retval; - complete(&ctx->work); -<<<<<<< - fastrpc_context_put(ctx); -======= - - /* - * The DMA buffer associated with the context cannot be freed in - * interrupt context so schedule it through a worker thread to - * avoid a kernel BUG. - */ - schedule_work(&ctx->put_work); ->>>>>>> - - return 0; -} - -static const struct of_device_id fastrpc_rpmsg_of_match[] = { - { .compatible = "qcom,fastrpc" }, - { }, -}; -MODULE_DEVICE_TABLE(of, fastrpc_rpmsg_of_match); - -static struct rpmsg_driver fastrpc_driver = { - .probe = fastrpc_rpmsg_probe, - .remove = fastrpc_rpmsg_remove, - .callback = fastrpc_rpmsg_callback, - .drv = { - .name = "qcom,fastrpc", - .of_match_table = fastrpc_rpmsg_of_match, - }, -}; - -static int fastrpc_init(void) -{ - int ret; - - ret = platform_driver_register(&fastrpc_cb_driver); - if (ret < 0) { - pr_err("fastrpc: failed to register cb driver\n"); - return ret; - } - - ret = register_rpmsg_driver(&fastrpc_driver); - if (ret < 0) { - pr_err("fastrpc: failed to register rpmsg driver\n"); - platform_driver_unregister(&fastrpc_cb_driver); - return ret; - } - - return 0; -} -module_init(fastrpc_init); - -static void fastrpc_exit(void) -{ - platform_driver_unregister(&fastrpc_cb_driver); - unregister_rpmsg_driver(&fastrpc_driver); -} -module_exit(fastrpc_exit); - -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/e43772d6874854fd8355afb9eb83ad8105068924/preimage b/rr-cache/e43772d6874854fd8355afb9eb83ad8105068924/preimage deleted file mode 100644 index af75bc4..0000000 --- a/rr-cache/e43772d6874854fd8355afb9eb83ad8105068924/preimage +++ /dev/null @@ -1,2191 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2011-2018, The Linux Foundation. All rights reserved. -// Copyright (c) 2018, Linaro Limited - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define ADSP_DOMAIN_ID (0) -#define MDSP_DOMAIN_ID (1) -#define SDSP_DOMAIN_ID (2) -#define CDSP_DOMAIN_ID (3) -#define FASTRPC_DEV_MAX 4 /* adsp, mdsp, slpi, cdsp*/ -<<<<<<< -#define FASTRPC_MAX_SESSIONS 13 /*12 compute, 1 cpz*/ -#define FASTRPC_MAX_VMIDS 16 -======= -#define FASTRPC_MAX_SESSIONS 9 /*8 compute, 1 cpz*/ ->>>>>>> -#define FASTRPC_ALIGN 128 -#define FASTRPC_MAX_FDLIST 16 -#define FASTRPC_MAX_CRCLIST 64 -#define FASTRPC_PHYS(p) ((p) & 0xffffffff) -#define FASTRPC_CTX_MAX (256) -#define FASTRPC_INIT_HANDLE 1 -#define FASTRPC_DSP_UTILITIES_HANDLE 2 -#define FASTRPC_CTXID_MASK (0xFF0) -#define INIT_FILELEN_MAX (2 * 1024 * 1024) -#define FASTRPC_DEVICE_NAME "fastrpc" -#define ADSP_MMAP_ADD_PAGES 0x1000 -#define DSP_UNSUPPORTED_API (0x80000414) -/* MAX NUMBER of DSP ATTRIBUTES SUPPORTED */ -#define FASTRPC_MAX_DSP_ATTRIBUTES (256) -#define FASTRPC_MAX_DSP_ATTRIBUTES_LEN (sizeof(u32) * FASTRPC_MAX_DSP_ATTRIBUTES) - -/* Retrives number of input buffers from the scalars parameter */ -#define REMOTE_SCALARS_INBUFS(sc) (((sc) >> 16) & 0x0ff) - -/* Retrives number of output buffers from the scalars parameter */ -#define REMOTE_SCALARS_OUTBUFS(sc) (((sc) >> 8) & 0x0ff) - -/* Retrives number of input handles from the scalars parameter */ -#define REMOTE_SCALARS_INHANDLES(sc) (((sc) >> 4) & 0x0f) - -/* Retrives number of output handles from the scalars parameter */ -#define REMOTE_SCALARS_OUTHANDLES(sc) ((sc) & 0x0f) - -#define REMOTE_SCALARS_LENGTH(sc) (REMOTE_SCALARS_INBUFS(sc) + \ - REMOTE_SCALARS_OUTBUFS(sc) + \ - REMOTE_SCALARS_INHANDLES(sc)+ \ - REMOTE_SCALARS_OUTHANDLES(sc)) -#define FASTRPC_BUILD_SCALARS(attr, method, in, out, oin, oout) \ - (((attr & 0x07) << 29) | \ - ((method & 0x1f) << 24) | \ - ((in & 0xff) << 16) | \ - ((out & 0xff) << 8) | \ - ((oin & 0x0f) << 4) | \ - (oout & 0x0f)) - -#define FASTRPC_SCALARS(method, in, out) \ - FASTRPC_BUILD_SCALARS(0, method, in, out, 0, 0) - -#define FASTRPC_CREATE_PROCESS_NARGS 6 -/* Remote Method id table */ -#define FASTRPC_RMID_INIT_ATTACH 0 -#define FASTRPC_RMID_INIT_RELEASE 1 -#define FASTRPC_RMID_INIT_MMAP 4 -#define FASTRPC_RMID_INIT_MUNMAP 5 -#define FASTRPC_RMID_INIT_CREATE 6 -#define FASTRPC_RMID_INIT_CREATE_ATTR 7 -#define FASTRPC_RMID_INIT_CREATE_STATIC 8 -#define FASTRPC_RMID_INIT_MEM_MAP 10 -#define FASTRPC_RMID_INIT_MEM_UNMAP 11 - -/* Protection Domain(PD) ids */ -#define AUDIO_PD (0) /* also GUEST_OS PD? */ -#define USER_PD (1) -#define SENSORS_PD (2) - -#define miscdev_to_fdevice(d) container_of(d, struct fastrpc_device, miscdev) - -static const char *domains[FASTRPC_DEV_MAX] = { "adsp", "mdsp", - "sdsp", "cdsp"}; -struct fastrpc_phy_page { - u64 addr; /* physical address */ - u64 size; /* size of contiguous region */ -}; - -struct fastrpc_invoke_buf { - u32 num; /* number of contiguous regions */ - u32 pgidx; /* index to start of contiguous region */ -}; - -struct fastrpc_remote_arg { - u64 pv; - u64 len; -}; - -struct fastrpc_mmap_rsp_msg { - u64 vaddr; -}; - -struct fastrpc_mmap_req_msg { - s32 pgid; - u32 flags; - u64 vaddr; - s32 num; -}; - -struct fastrpc_mem_map_req_msg { - s32 pgid; - s32 fd; - s32 offset; - u32 flags; - u64 vaddrin; - s32 num; - s32 data_len; -}; - -struct fastrpc_munmap_req_msg { - s32 pgid; - u64 vaddr; - u64 size; -}; - -struct fastrpc_mem_unmap_req_msg { - s32 pgid; - s32 fd; - u64 vaddrin; - u64 len; -}; - -struct fastrpc_msg { - int pid; /* process group id */ - int tid; /* thread id */ - u64 ctx; /* invoke caller context */ - u32 handle; /* handle to invoke */ - u32 sc; /* scalars structure describing the data */ - u64 addr; /* physical address */ - u64 size; /* size of contiguous region */ -}; - -struct fastrpc_invoke_rsp { - u64 ctx; /* invoke caller context */ - int retval; /* invoke return value */ -}; - -struct fastrpc_buf_overlap { - u64 start; - u64 end; - int raix; - u64 mstart; - u64 mend; - u64 offset; -}; - -struct fastrpc_buf { - struct fastrpc_user *fl; - struct dma_buf *dmabuf; - struct device *dev; - void *virt; - u64 phys; - u64 size; - /* Lock for dma buf attachments */ - struct mutex lock; - struct list_head attachments; - /* mmap support */ - struct list_head node; /* list of user requested mmaps */ - uintptr_t raddr; -}; - -struct fastrpc_dma_buf_attachment { - struct device *dev; - struct sg_table sgt; - struct list_head node; -}; - -struct fastrpc_map { - struct list_head node; - struct fastrpc_user *fl; - int fd; - struct dma_buf *buf; - struct sg_table *table; - struct dma_buf_attachment *attach; - u64 phys; - u64 size; - void *va; - u64 len; - u64 raddr; - u32 attr; - struct kref refcount; -}; - -struct fastrpc_invoke_ctx { - int nscalars; - int nbufs; - int retval; - int pid; - int tgid; - u32 sc; - u32 *crc; - u64 ctxid; - u64 msg_sz; - struct kref refcount; - struct list_head node; /* list of ctxs */ - struct completion work; - struct work_struct put_work; - struct fastrpc_msg msg; - struct fastrpc_user *fl; - struct fastrpc_remote_arg *rpra; - struct fastrpc_map **maps; - struct fastrpc_buf *buf; - struct fastrpc_invoke_args *args; - struct fastrpc_buf_overlap *olaps; - struct fastrpc_channel_ctx *cctx; -}; - -struct fastrpc_session_ctx { - struct device *dev; - int sid; - bool used; - bool valid; -}; - -struct fastrpc_channel_ctx { - int domain_id; - int sesscount; - int vmcount; - u32 perms; - struct qcom_scm_vmperm vmperms[FASTRPC_MAX_VMIDS]; - struct rpmsg_device *rpdev; - struct fastrpc_session_ctx session[FASTRPC_MAX_SESSIONS]; - spinlock_t lock; - struct idr ctx_idr; - struct list_head users; - struct kref refcount; - /* Flag if dsp attributes are cached */ - bool valid_attributes; - u32 dsp_attributes[FASTRPC_MAX_DSP_ATTRIBUTES]; - struct fastrpc_device *secure_fdevice; - struct fastrpc_device *fdevice; - bool secure; - bool unsigned_support; -}; - -struct fastrpc_device { - struct fastrpc_channel_ctx *cctx; - struct miscdevice miscdev; - bool secure; -}; - -struct fastrpc_user { - struct list_head user; - struct list_head maps; - struct list_head pending; - struct list_head mmaps; - - struct fastrpc_channel_ctx *cctx; - struct fastrpc_session_ctx *sctx; - struct fastrpc_buf *init_mem; - - int tgid; - int pd; - bool is_secure_dev; - /* Lock for lists */ - spinlock_t lock; - /* lock for allocations */ - struct mutex mutex; -}; - -static void fastrpc_free_map(struct kref *ref) -{ - struct fastrpc_map *map; - - map = container_of(ref, struct fastrpc_map, refcount); - - if (map->table) { - if (map->attr & FASTRPC_ATTR_SECUREMAP) { - struct qcom_scm_vmperm perm; - int err = 0; - - perm.vmid = QCOM_SCM_VMID_HLOS; - perm.perm = QCOM_SCM_PERM_RWX; - err = qcom_scm_assign_mem(map->phys, map->size, - &(map->fl->cctx->vmperms[0].vmid), &perm, 1); - if (err) { - dev_err(map->fl->sctx->dev, "Failed to assign memory phys 0x%llx size 0x%llx err %d", - map->phys, map->size, err); - return; - } - } - dma_buf_unmap_attachment(map->attach, map->table, - DMA_BIDIRECTIONAL); - dma_buf_detach(map->buf, map->attach); - dma_buf_put(map->buf); - } - - kfree(map); -} - -static void fastrpc_map_put(struct fastrpc_map *map) -{ - if (map) - kref_put(&map->refcount, fastrpc_free_map); -} - -static void fastrpc_map_get(struct fastrpc_map *map) -{ - if (map) - kref_get(&map->refcount); -} - -static int fastrpc_map_find(struct fastrpc_user *fl, int fd, - struct fastrpc_map **ppmap) -{ - struct fastrpc_map *map = NULL; - - mutex_lock(&fl->mutex); - list_for_each_entry(map, &fl->maps, node) { - if (map->fd == fd) { - fastrpc_map_get(map); - *ppmap = map; - mutex_unlock(&fl->mutex); - return 0; - } - } - mutex_unlock(&fl->mutex); - - return -ENOENT; -} - -static void fastrpc_buf_free(struct fastrpc_buf *buf) -{ - dma_free_coherent(buf->dev, buf->size, buf->virt, - FASTRPC_PHYS(buf->phys)); - kfree(buf); -} - -static int fastrpc_buf_alloc(struct fastrpc_user *fl, struct device *dev, - u64 size, struct fastrpc_buf **obuf) -{ - struct fastrpc_buf *buf; - - buf = kzalloc(sizeof(*buf), GFP_KERNEL); - if (!buf) - return -ENOMEM; - - INIT_LIST_HEAD(&buf->attachments); - INIT_LIST_HEAD(&buf->node); - mutex_init(&buf->lock); - - buf->fl = fl; - buf->virt = NULL; - buf->phys = 0; - buf->size = size; - buf->dev = dev; - buf->raddr = 0; - - buf->virt = dma_alloc_coherent(dev, buf->size, (dma_addr_t *)&buf->phys, - GFP_KERNEL); - if (!buf->virt) { - mutex_destroy(&buf->lock); - kfree(buf); - return -ENOMEM; - } - - if (fl->sctx && fl->sctx->sid) - buf->phys += ((u64)fl->sctx->sid << 32); - - *obuf = buf; - - return 0; -} - -static void fastrpc_channel_ctx_free(struct kref *ref) -{ - struct fastrpc_channel_ctx *cctx; - - cctx = container_of(ref, struct fastrpc_channel_ctx, refcount); - - kfree(cctx); -} - -static void fastrpc_channel_ctx_get(struct fastrpc_channel_ctx *cctx) -{ - kref_get(&cctx->refcount); -} - -static void fastrpc_channel_ctx_put(struct fastrpc_channel_ctx *cctx) -{ - kref_put(&cctx->refcount, fastrpc_channel_ctx_free); -} - -static void fastrpc_context_free(struct kref *ref) -{ - struct fastrpc_invoke_ctx *ctx; - struct fastrpc_channel_ctx *cctx; - unsigned long flags; - int i; - - ctx = container_of(ref, struct fastrpc_invoke_ctx, refcount); - cctx = ctx->cctx; - - for (i = 0; i < ctx->nscalars; i++) - fastrpc_map_put(ctx->maps[i]); - - if (ctx->buf) - fastrpc_buf_free(ctx->buf); - - spin_lock_irqsave(&cctx->lock, flags); - idr_remove(&cctx->ctx_idr, ctx->ctxid >> 4); - spin_unlock_irqrestore(&cctx->lock, flags); - - kfree(ctx->maps); - kfree(ctx->olaps); - kfree(ctx); - - fastrpc_channel_ctx_put(cctx); -} - -static void fastrpc_context_get(struct fastrpc_invoke_ctx *ctx) -{ - kref_get(&ctx->refcount); -} - -static void fastrpc_context_put(struct fastrpc_invoke_ctx *ctx) -{ - kref_put(&ctx->refcount, fastrpc_context_free); -} - -static void fastrpc_context_put_wq(struct work_struct *work) -{ - struct fastrpc_invoke_ctx *ctx = - container_of(work, struct fastrpc_invoke_ctx, put_work); - - fastrpc_context_put(ctx); -} - -#define CMP(aa, bb) ((aa) == (bb) ? 0 : (aa) < (bb) ? -1 : 1) -static int olaps_cmp(const void *a, const void *b) -{ - struct fastrpc_buf_overlap *pa = (struct fastrpc_buf_overlap *)a; - struct fastrpc_buf_overlap *pb = (struct fastrpc_buf_overlap *)b; - /* sort with lowest starting buffer first */ - int st = CMP(pa->start, pb->start); - /* sort with highest ending buffer first */ - int ed = CMP(pb->end, pa->end); - - return st == 0 ? ed : st; -} - -static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) -{ - u64 max_end = 0; - int i; - - for (i = 0; i < ctx->nbufs; ++i) { - ctx->olaps[i].start = ctx->args[i].ptr; - ctx->olaps[i].end = ctx->olaps[i].start + ctx->args[i].length; - ctx->olaps[i].raix = i; - } - - sort(ctx->olaps, ctx->nbufs, sizeof(*ctx->olaps), olaps_cmp, NULL); - - for (i = 0; i < ctx->nbufs; ++i) { - /* Falling inside previous range */ - if (ctx->olaps[i].start < max_end) { - ctx->olaps[i].mstart = max_end; - ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].offset = max_end - ctx->olaps[i].start; - - if (ctx->olaps[i].end > max_end) { - max_end = ctx->olaps[i].end; - } else { - ctx->olaps[i].mend = 0; - ctx->olaps[i].mstart = 0; - } - - } else { - ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].mstart = ctx->olaps[i].start; - ctx->olaps[i].offset = 0; - max_end = ctx->olaps[i].end; - } - } -} - -static struct fastrpc_invoke_ctx *fastrpc_context_alloc( - struct fastrpc_user *user, u32 kernel, u32 sc, - struct fastrpc_invoke_args *args) -{ - struct fastrpc_channel_ctx *cctx = user->cctx; - struct fastrpc_invoke_ctx *ctx = NULL; - unsigned long flags; - int ret; - - ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return ERR_PTR(-ENOMEM); - - INIT_LIST_HEAD(&ctx->node); - ctx->fl = user; - ctx->nscalars = REMOTE_SCALARS_LENGTH(sc); - ctx->nbufs = REMOTE_SCALARS_INBUFS(sc) + - REMOTE_SCALARS_OUTBUFS(sc); - - if (ctx->nscalars) { - ctx->maps = kcalloc(ctx->nscalars, - sizeof(*ctx->maps), GFP_KERNEL); - if (!ctx->maps) { - kfree(ctx); - return ERR_PTR(-ENOMEM); - } - ctx->olaps = kcalloc(ctx->nscalars, - sizeof(*ctx->olaps), GFP_KERNEL); - if (!ctx->olaps) { - kfree(ctx->maps); - kfree(ctx); - return ERR_PTR(-ENOMEM); - } - ctx->args = args; - fastrpc_get_buff_overlaps(ctx); - } - - /* Released in fastrpc_context_put() */ - fastrpc_channel_ctx_get(cctx); - - ctx->sc = sc; - ctx->retval = -1; - ctx->pid = current->pid; - ctx->tgid = user->tgid; - ctx->cctx = cctx; - init_completion(&ctx->work); - INIT_WORK(&ctx->put_work, fastrpc_context_put_wq); - - spin_lock(&user->lock); - list_add_tail(&ctx->node, &user->pending); - spin_unlock(&user->lock); - - spin_lock_irqsave(&cctx->lock, flags); - ret = idr_alloc_cyclic(&cctx->ctx_idr, ctx, 1, - FASTRPC_CTX_MAX, GFP_ATOMIC); - if (ret < 0) { - spin_unlock_irqrestore(&cctx->lock, flags); - goto err_idr; - } - ctx->ctxid = ret << 4; - spin_unlock_irqrestore(&cctx->lock, flags); - - kref_init(&ctx->refcount); - - return ctx; -err_idr: - spin_lock(&user->lock); - list_del(&ctx->node); - spin_unlock(&user->lock); - fastrpc_channel_ctx_put(cctx); - kfree(ctx->maps); - kfree(ctx->olaps); - kfree(ctx); - - return ERR_PTR(ret); -} - -static struct sg_table * -fastrpc_map_dma_buf(struct dma_buf_attachment *attachment, - enum dma_data_direction dir) -{ - struct fastrpc_dma_buf_attachment *a = attachment->priv; - struct sg_table *table; - int ret; - - table = &a->sgt; - - ret = dma_map_sgtable(attachment->dev, table, dir, 0); - if (ret) - table = ERR_PTR(ret); - return table; -} - -static void fastrpc_unmap_dma_buf(struct dma_buf_attachment *attach, - struct sg_table *table, - enum dma_data_direction dir) -{ - dma_unmap_sgtable(attach->dev, table, dir, 0); -} - -static void fastrpc_release(struct dma_buf *dmabuf) -{ - struct fastrpc_buf *buffer = dmabuf->priv; - - fastrpc_buf_free(buffer); -} - -static int fastrpc_dma_buf_attach(struct dma_buf *dmabuf, - struct dma_buf_attachment *attachment) -{ - struct fastrpc_dma_buf_attachment *a; - struct fastrpc_buf *buffer = dmabuf->priv; - int ret; - - a = kzalloc(sizeof(*a), GFP_KERNEL); - if (!a) - return -ENOMEM; - - ret = dma_get_sgtable(buffer->dev, &a->sgt, buffer->virt, - FASTRPC_PHYS(buffer->phys), buffer->size); - if (ret < 0) { - dev_err(buffer->dev, "failed to get scatterlist from DMA API\n"); - kfree(a); - return -EINVAL; - } - - a->dev = attachment->dev; - INIT_LIST_HEAD(&a->node); - attachment->priv = a; - - mutex_lock(&buffer->lock); - list_add(&a->node, &buffer->attachments); - mutex_unlock(&buffer->lock); - - return 0; -} - -static void fastrpc_dma_buf_detatch(struct dma_buf *dmabuf, - struct dma_buf_attachment *attachment) -{ - struct fastrpc_dma_buf_attachment *a = attachment->priv; - struct fastrpc_buf *buffer = dmabuf->priv; - - mutex_lock(&buffer->lock); - list_del(&a->node); - mutex_unlock(&buffer->lock); - sg_free_table(&a->sgt); - kfree(a); -} - -static int fastrpc_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) -{ - struct fastrpc_buf *buf = dmabuf->priv; - - dma_buf_map_set_vaddr(map, buf->virt); - - return 0; -} - -static int fastrpc_mmap(struct dma_buf *dmabuf, - struct vm_area_struct *vma) -{ - struct fastrpc_buf *buf = dmabuf->priv; - size_t size = vma->vm_end - vma->vm_start; - - return dma_mmap_coherent(buf->dev, vma, buf->virt, - FASTRPC_PHYS(buf->phys), size); -} - -static const struct dma_buf_ops fastrpc_dma_buf_ops = { - .attach = fastrpc_dma_buf_attach, - .detach = fastrpc_dma_buf_detatch, - .map_dma_buf = fastrpc_map_dma_buf, - .unmap_dma_buf = fastrpc_unmap_dma_buf, - .mmap = fastrpc_mmap, - .vmap = fastrpc_vmap, - .release = fastrpc_release, -}; - -static int fastrpc_map_create(struct fastrpc_user *fl, int fd, - u64 len, u32 attr, struct fastrpc_map **ppmap) -{ - struct fastrpc_session_ctx *sess = fl->sctx; - struct fastrpc_map *map = NULL; - int err = 0; - - if (!fastrpc_map_find(fl, fd, ppmap)) - return 0; - - map = kzalloc(sizeof(*map), GFP_KERNEL); - if (!map) - return -ENOMEM; - - INIT_LIST_HEAD(&map->node); - map->fl = fl; - map->fd = fd; - map->buf = dma_buf_get(fd); - if (IS_ERR(map->buf)) { - err = PTR_ERR(map->buf); - goto get_err; - } - - map->attach = dma_buf_attach(map->buf, sess->dev); - if (IS_ERR(map->attach)) { - dev_err(sess->dev, "Failed to attach dmabuf\n"); - err = PTR_ERR(map->attach); - goto attach_err; - } - - map->table = dma_buf_map_attachment(map->attach, DMA_BIDIRECTIONAL); - if (IS_ERR(map->table)) { - err = PTR_ERR(map->table); - goto map_err; - } - - map->phys = sg_dma_address(map->table->sgl); - map->phys += ((u64)fl->sctx->sid << 32); - map->size = len; - map->va = sg_virt(map->table->sgl); - map->len = len; - kref_init(&map->refcount); - - if (attr & FASTRPC_ATTR_SECUREMAP) { - /* - * If subsystem VMIDs are defined in DTSI, then do - * hyp_assign from HLOS to those VM(s) - */ - unsigned int perms = BIT(QCOM_SCM_VMID_HLOS); - - map->attr = attr; - err = qcom_scm_assign_mem(map->phys, (u64)map->size, &perms, - fl->cctx->vmperms, fl->cctx->vmcount); - if (err) { - dev_err(sess->dev, "Failed to assign memory with phys 0x%llx size 0x%llx err %d", - map->phys, map->size, err); - goto map_err; - } - } - spin_lock(&fl->lock); - list_add_tail(&map->node, &fl->maps); - spin_unlock(&fl->lock); - *ppmap = map; - - return 0; - -map_err: - dma_buf_detach(map->buf, map->attach); -attach_err: - dma_buf_put(map->buf); -get_err: - kfree(map); - - return err; -} - -/* - * Fastrpc payload buffer with metadata looks like: - * - * >>>>>> START of METADATA <<<<<<<<< - * +---------------------------------+ - * | Arguments | - * | type:(struct fastrpc_remote_arg)| - * | (0 - N) | - * +---------------------------------+ - * | Invoke Buffer list | - * | type:(struct fastrpc_invoke_buf)| - * | (0 - N) | - * +---------------------------------+ - * | Page info list | - * | type:(struct fastrpc_phy_page) | - * | (0 - N) | - * +---------------------------------+ - * | Optional info | - * |(can be specific to SoC/Firmware)| - * +---------------------------------+ - * >>>>>>>> END of METADATA <<<<<<<<< - * +---------------------------------+ - * | Inline ARGS | - * | (0-N) | - * +---------------------------------+ - */ - -static int fastrpc_get_meta_size(struct fastrpc_invoke_ctx *ctx) -{ - int size = 0; - - size = (sizeof(struct fastrpc_remote_arg) + - sizeof(struct fastrpc_invoke_buf) + - sizeof(struct fastrpc_phy_page)) * ctx->nscalars + - sizeof(u64) * FASTRPC_MAX_FDLIST + - sizeof(u32) * FASTRPC_MAX_CRCLIST; - - return size; -} - -static u64 fastrpc_get_payload_size(struct fastrpc_invoke_ctx *ctx, int metalen) -{ - u64 size = 0; - int oix; - - size = ALIGN(metalen, FASTRPC_ALIGN); - for (oix = 0; oix < ctx->nbufs; oix++) { - int i = ctx->olaps[oix].raix; - - if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1) { - - if (ctx->olaps[oix].offset == 0) - size = ALIGN(size, FASTRPC_ALIGN); - - size += (ctx->olaps[oix].mend - ctx->olaps[oix].mstart); - } - } - - return size; -} - -static int fastrpc_create_maps(struct fastrpc_invoke_ctx *ctx) -{ - struct device *dev = ctx->fl->sctx->dev; - int i, err; - - for (i = 0; i < ctx->nscalars; ++i) { - - if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1 || - ctx->args[i].length == 0) - continue; - - err = fastrpc_map_create(ctx->fl, ctx->args[i].fd, - ctx->args[i].length, ctx->args[i].attr, &ctx->maps[i]); - if (err) { - dev_err(dev, "Error Creating map %d\n", err); - return -EINVAL; - } - - } - return 0; -} - -static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) -{ - struct device *dev = ctx->fl->sctx->dev; - struct fastrpc_remote_arg *rpra; - struct fastrpc_invoke_buf *list; - struct fastrpc_phy_page *pages; - int inbufs, i, oix, err = 0; - u64 len, rlen, pkt_size; - u64 pg_start, pg_end; - uintptr_t args; - int metalen; - - inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); - metalen = fastrpc_get_meta_size(ctx); - pkt_size = fastrpc_get_payload_size(ctx, metalen); - - err = fastrpc_create_maps(ctx); - if (err) - return err; - - ctx->msg_sz = pkt_size; - - err = fastrpc_buf_alloc(ctx->fl, dev, pkt_size, &ctx->buf); - if (err) - return err; - - rpra = ctx->buf->virt; - list = ctx->buf->virt + ctx->nscalars * sizeof(*rpra); - pages = ctx->buf->virt + ctx->nscalars * (sizeof(*list) + - sizeof(*rpra)); - args = (uintptr_t)ctx->buf->virt + metalen; - rlen = pkt_size - metalen; - ctx->rpra = rpra; - - for (oix = 0; oix < ctx->nbufs; ++oix) { - int mlen; - - i = ctx->olaps[oix].raix; - len = ctx->args[i].length; - - rpra[i].pv = 0; - rpra[i].len = len; - list[i].num = len ? 1 : 0; - list[i].pgidx = i; - - if (!len) - continue; - - if (ctx->maps[i]) { - struct vm_area_struct *vma = NULL; - - rpra[i].pv = (u64) ctx->args[i].ptr; - pages[i].addr = ctx->maps[i]->phys; - - mmap_read_lock(current->mm); - vma = find_vma(current->mm, ctx->args[i].ptr); - if (vma) - pages[i].addr += ctx->args[i].ptr - - vma->vm_start; - mmap_read_unlock(current->mm); - - pg_start = (ctx->args[i].ptr & PAGE_MASK) >> PAGE_SHIFT; - pg_end = ((ctx->args[i].ptr + len - 1) & PAGE_MASK) >> - PAGE_SHIFT; - pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - - } else { - - if (ctx->olaps[oix].offset == 0) { - rlen -= ALIGN(args, FASTRPC_ALIGN) - args; - args = ALIGN(args, FASTRPC_ALIGN); - } - - mlen = ctx->olaps[oix].mend - ctx->olaps[oix].mstart; - - if (rlen < mlen) - goto bail; - - rpra[i].pv = args - ctx->olaps[oix].offset; - pages[i].addr = ctx->buf->phys - - ctx->olaps[oix].offset + - (pkt_size - rlen); - pages[i].addr = pages[i].addr & PAGE_MASK; - - pg_start = (args & PAGE_MASK) >> PAGE_SHIFT; - pg_end = ((args + len - 1) & PAGE_MASK) >> PAGE_SHIFT; - pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - args = args + mlen; - rlen -= mlen; - } - - if (i < inbufs && !ctx->maps[i]) { - void *dst = (void *)(uintptr_t)rpra[i].pv; - void *src = (void *)(uintptr_t)ctx->args[i].ptr; - - if (!kernel) { - if (copy_from_user(dst, (void __user *)src, - len)) { - err = -EFAULT; - goto bail; - } - } else { - memcpy(dst, src, len); - } - } - } - - for (i = ctx->nbufs; i < ctx->nscalars; ++i) { - rpra[i].pv = (u64) ctx->args[i].ptr; - rpra[i].len = ctx->args[i].length; - list[i].num = ctx->args[i].length ? 1 : 0; - list[i].pgidx = i; - pages[i].addr = ctx->maps[i]->phys; - pages[i].size = ctx->maps[i]->size; - } - -bail: - if (err) - dev_err(dev, "Error: get invoke args failed:%d\n", err); - - return err; -} - -static int fastrpc_put_args(struct fastrpc_invoke_ctx *ctx, - u32 kernel) -{ - struct fastrpc_remote_arg *rpra = ctx->rpra; - int i, inbufs; - - inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); - - for (i = inbufs; i < ctx->nbufs; ++i) { - void *src = (void *)(uintptr_t)rpra[i].pv; - void *dst = (void *)(uintptr_t)ctx->args[i].ptr; - u64 len = rpra[i].len; - - if (!kernel) { - if (copy_to_user((void __user *)dst, src, len)) - return -EFAULT; - } else { - memcpy(dst, src, len); - } - } - - return 0; -} - -static int fastrpc_invoke_send(struct fastrpc_session_ctx *sctx, - struct fastrpc_invoke_ctx *ctx, - u32 kernel, uint32_t handle) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_user *fl = ctx->fl; - struct fastrpc_msg *msg = &ctx->msg; - int ret; - - cctx = fl->cctx; - msg->pid = fl->tgid; - msg->tid = current->pid; - - if (kernel) - msg->pid = 0; - - msg->ctx = ctx->ctxid | fl->pd; - msg->handle = handle; - msg->sc = ctx->sc; - msg->addr = ctx->buf ? ctx->buf->phys : 0; - msg->size = roundup(ctx->msg_sz, PAGE_SIZE); - fastrpc_context_get(ctx); - - ret = rpmsg_send(cctx->rpdev->ept, (void *)msg, sizeof(*msg)); - - if (ret) - fastrpc_context_put(ctx); - - return ret; - -} - -static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel, - u32 handle, u32 sc, - struct fastrpc_invoke_args *args) -{ - struct fastrpc_invoke_ctx *ctx = NULL; - int err = 0; - - if (!fl->sctx) - return -EINVAL; - - if (!fl->cctx->rpdev) - return -EPIPE; - - if (handle == FASTRPC_INIT_HANDLE && !kernel) { - dev_warn_ratelimited(fl->sctx->dev, "user app trying to send a kernel RPC message (%d)\n", handle); - return -EPERM; - } - - ctx = fastrpc_context_alloc(fl, kernel, sc, args); - if (IS_ERR(ctx)) - return PTR_ERR(ctx); - - if (ctx->nscalars) { - err = fastrpc_get_args(kernel, ctx); - if (err) - goto bail; - } - - /* make sure that all CPU memory writes are seen by DSP */ - dma_wmb(); - /* Send invoke buffer to remote dsp */ - err = fastrpc_invoke_send(fl->sctx, ctx, kernel, handle); - if (err) - goto bail; - - if (kernel) { - if (!wait_for_completion_timeout(&ctx->work, 10 * HZ)) - err = -ETIMEDOUT; - } else { - err = wait_for_completion_interruptible(&ctx->work); - } - - if (err) - goto bail; - - /* Check the response from remote dsp */ - err = ctx->retval; - if (err) - goto bail; - - if (ctx->nscalars) { - /* make sure that all memory writes by DSP are seen by CPU */ - dma_rmb(); - /* populate all the output buffers with results */ - err = fastrpc_put_args(ctx, kernel); - if (err) - goto bail; - } - -bail: - if (err != -ERESTARTSYS && err != -ETIMEDOUT) { - /* We are done with this compute context */ - spin_lock(&fl->lock); - list_del(&ctx->node); - spin_unlock(&fl->lock); - fastrpc_context_put(ctx); - } - if (err) - dev_dbg(fl->sctx->dev, "Error: Invoke Failed %d\n", err); - - return err; -} - -static bool is_session_rejected(struct fastrpc_user *fl, bool unsigned_pd_request) -{ - /* Check if the device node is non-secure and channel is secure*/ - if (!fl->is_secure_dev && fl->cctx->secure) { - /* - * Allow untrusted applications to offload only to Unsigned PD when - * channel is configured as secure and block untrusted apps on channel - * that does not support unsigned PD offload - */ - if (!fl->cctx->unsigned_support || !unsigned_pd_request) { - dev_err(&fl->cctx->rpdev->dev, "Error: Untrusted application trying to offload to signed PD"); - return true; - } - } - - return false; -} - -static int fastrpc_init_create_process(struct fastrpc_user *fl, - char __user *argp) -{ - struct fastrpc_init_create init; - struct fastrpc_invoke_args *args; - struct fastrpc_phy_page pages[1]; - struct fastrpc_map *map = NULL; - struct fastrpc_buf *imem = NULL; - int memlen; - int err; - struct { - int pgid; - u32 namelen; - u32 filelen; - u32 pageslen; - u32 attrs; - u32 siglen; - } inbuf; - u32 sc; - bool unsigned_module = false; - - args = kcalloc(FASTRPC_CREATE_PROCESS_NARGS, sizeof(*args), GFP_KERNEL); - if (!args) - return -ENOMEM; - - if (copy_from_user(&init, argp, sizeof(init))) { - err = -EFAULT; - goto err; - } - - if (init.attrs & FASTRPC_MODE_UNSIGNED_MODULE) - unsigned_module = true; - - if (is_session_rejected(fl, unsigned_module)) { - err = -ECONNREFUSED; - goto err; - } - - if (init.filelen > INIT_FILELEN_MAX) { - err = -EINVAL; - goto err; - } - - inbuf.pgid = fl->tgid; - inbuf.namelen = strlen(current->comm) + 1; - inbuf.filelen = init.filelen; - inbuf.pageslen = 1; - inbuf.attrs = init.attrs; - inbuf.siglen = init.siglen; - fl->pd = USER_PD; - - if (init.filelen && init.filefd) { - err = fastrpc_map_create(fl, init.filefd, init.filelen, 0, &map); - if (err) - goto err; - } - - memlen = ALIGN(max(INIT_FILELEN_MAX, (int)init.filelen * 4), - 1024 * 1024); - err = fastrpc_buf_alloc(fl, fl->sctx->dev, memlen, - &imem); - if (err) - goto err_alloc; - - fl->init_mem = imem; - args[0].ptr = (u64)(uintptr_t)&inbuf; - args[0].length = sizeof(inbuf); - args[0].fd = -1; - - args[1].ptr = (u64)(uintptr_t)current->comm; - args[1].length = inbuf.namelen; - args[1].fd = -1; - - args[2].ptr = (u64) init.file; - args[2].length = inbuf.filelen; - args[2].fd = init.filefd; - - pages[0].addr = imem->phys; - pages[0].size = imem->size; - - args[3].ptr = (u64)(uintptr_t) pages; - args[3].length = 1 * sizeof(*pages); - args[3].fd = -1; - - args[4].ptr = (u64)(uintptr_t)&inbuf.attrs; - args[4].length = sizeof(inbuf.attrs); - args[4].fd = -1; - - args[5].ptr = (u64)(uintptr_t) &inbuf.siglen; - args[5].length = sizeof(inbuf.siglen); - args[5].fd = -1; - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE, 4, 0); - if (init.attrs) - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_CREATE_ATTR, 6, 0); - - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, args); - if (err) - goto err_invoke; - - kfree(args); - - return 0; - -err_invoke: - fl->init_mem = NULL; - fastrpc_buf_free(imem); -err_alloc: - if (map) { - spin_lock(&fl->lock); - list_del(&map->node); - spin_unlock(&fl->lock); - fastrpc_map_put(map); - } -err: - kfree(args); - - return err; -} - -static struct fastrpc_session_ctx *fastrpc_session_alloc( - struct fastrpc_channel_ctx *cctx) -{ - struct fastrpc_session_ctx *session = NULL; - unsigned long flags; - int i; - - spin_lock_irqsave(&cctx->lock, flags); - for (i = 0; i < cctx->sesscount; i++) { - if (!cctx->session[i].used && cctx->session[i].valid) { - cctx->session[i].used = true; - session = &cctx->session[i]; - break; - } - } - spin_unlock_irqrestore(&cctx->lock, flags); - - return session; -} - -static void fastrpc_session_free(struct fastrpc_channel_ctx *cctx, - struct fastrpc_session_ctx *session) -{ - unsigned long flags; - - spin_lock_irqsave(&cctx->lock, flags); - session->used = false; - spin_unlock_irqrestore(&cctx->lock, flags); -} - -static int fastrpc_release_current_dsp_process(struct fastrpc_user *fl) -{ - struct fastrpc_invoke_args args[1]; - int tgid = 0; - u32 sc; - - tgid = fl->tgid; - args[0].ptr = (u64)(uintptr_t) &tgid; - args[0].length = sizeof(tgid); - args[0].fd = -1; - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_RELEASE, 1, 0); - - return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, &args[0]); -} - -static int fastrpc_device_release(struct inode *inode, struct file *file) -{ - struct fastrpc_user *fl = (struct fastrpc_user *)file->private_data; - struct fastrpc_channel_ctx *cctx = fl->cctx; - struct fastrpc_invoke_ctx *ctx, *n; - struct fastrpc_map *map, *m; - struct fastrpc_buf *buf, *b; - unsigned long flags; - - fastrpc_release_current_dsp_process(fl); - - spin_lock_irqsave(&cctx->lock, flags); - list_del(&fl->user); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (fl->init_mem) - fastrpc_buf_free(fl->init_mem); - - list_for_each_entry_safe(ctx, n, &fl->pending, node) { - list_del(&ctx->node); - fastrpc_context_put(ctx); - } - - list_for_each_entry_safe(map, m, &fl->maps, node) { - list_del(&map->node); - fastrpc_map_put(map); - } - - list_for_each_entry_safe(buf, b, &fl->mmaps, node) { - list_del(&buf->node); - fastrpc_buf_free(buf); - } - - fastrpc_session_free(cctx, fl->sctx); - fastrpc_channel_ctx_put(cctx); - - mutex_destroy(&fl->mutex); - kfree(fl); - file->private_data = NULL; - - return 0; -} - -static int fastrpc_device_open(struct inode *inode, struct file *filp) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_device *fdevice; - struct fastrpc_user *fl = NULL; - unsigned long flags; - - fdevice = miscdev_to_fdevice(filp->private_data); - cctx = fdevice->cctx; - - fl = kzalloc(sizeof(*fl), GFP_KERNEL); - if (!fl) - return -ENOMEM; - - /* Released in fastrpc_device_release() */ - fastrpc_channel_ctx_get(cctx); - - filp->private_data = fl; - spin_lock_init(&fl->lock); - mutex_init(&fl->mutex); - INIT_LIST_HEAD(&fl->pending); - INIT_LIST_HEAD(&fl->maps); - INIT_LIST_HEAD(&fl->mmaps); - INIT_LIST_HEAD(&fl->user); - fl->tgid = current->tgid; - fl->cctx = cctx; - fl->is_secure_dev = fdevice->secure; - - fl->sctx = fastrpc_session_alloc(cctx); - if (!fl->sctx) { - dev_err(&cctx->rpdev->dev, "No session available\n"); - mutex_destroy(&fl->mutex); - kfree(fl); - - return -EBUSY; - } - - spin_lock_irqsave(&cctx->lock, flags); - list_add_tail(&fl->user, &cctx->users); - spin_unlock_irqrestore(&cctx->lock, flags); - - return 0; -} - -static int fastrpc_dmabuf_alloc(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_alloc_dma_buf bp; - DEFINE_DMA_BUF_EXPORT_INFO(exp_info); - struct fastrpc_buf *buf = NULL; - int err; - - if (copy_from_user(&bp, argp, sizeof(bp))) - return -EFAULT; - - err = fastrpc_buf_alloc(fl, fl->sctx->dev, bp.size, &buf); - if (err) - return err; - exp_info.ops = &fastrpc_dma_buf_ops; - exp_info.size = bp.size; - exp_info.flags = O_RDWR; - exp_info.priv = buf; - buf->dmabuf = dma_buf_export(&exp_info); - if (IS_ERR(buf->dmabuf)) { - err = PTR_ERR(buf->dmabuf); - fastrpc_buf_free(buf); - return err; - } - - bp.fd = dma_buf_fd(buf->dmabuf, O_ACCMODE); - if (bp.fd < 0) { - dma_buf_put(buf->dmabuf); - return -EINVAL; - } - - if (copy_to_user(argp, &bp, sizeof(bp))) { - /* - * The usercopy failed, but we can't do much about it, as - * dma_buf_fd() already called fd_install() and made the - * file descriptor accessible for the current process. It - * might already be closed and dmabuf no longer valid when - * we reach this point. Therefore "leak" the fd and rely on - * the process exit path to do any required cleanup. - */ - return -EFAULT; - } - - return 0; -} - -static int fastrpc_init_attach(struct fastrpc_user *fl, int pd) -{ - struct fastrpc_invoke_args args[1]; - int tgid = fl->tgid; - u32 sc; - - args[0].ptr = (u64)(uintptr_t) &tgid; - args[0].length = sizeof(tgid); - args[0].fd = -1; - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_ATTACH, 1, 0); - fl->pd = pd; - - return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, - sc, &args[0]); -} - -static int fastrpc_invoke(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args *args = NULL; - struct fastrpc_invoke inv; - u32 nscalars; - int err; - - if (copy_from_user(&inv, argp, sizeof(inv))) - return -EFAULT; - - /* nscalars is truncated here to max supported value */ - nscalars = REMOTE_SCALARS_LENGTH(inv.sc); - if (nscalars) { - args = kcalloc(nscalars, sizeof(*args), GFP_KERNEL); - if (!args) - return -ENOMEM; - - if (copy_from_user(args, (void __user *)(uintptr_t)inv.args, - nscalars * sizeof(*args))) { - kfree(args); - return -EFAULT; - } - } - - err = fastrpc_internal_invoke(fl, false, inv.handle, inv.sc, args); - kfree(args); - - return err; -} - -static int fastrpc_get_info_from_dsp(struct fastrpc_user *fl, uint32_t *dsp_attr_buf, - uint32_t dsp_attr_buf_len) -{ - struct fastrpc_invoke_args args[2] = { 0 }; - - /* Capability filled in userspace */ - dsp_attr_buf[0] = 0; - - args[0].ptr = (u64)(uintptr_t)&dsp_attr_buf_len; - args[0].length = sizeof(dsp_attr_buf_len); - args[0].fd = -1; - args[1].ptr = (u64)(uintptr_t)&dsp_attr_buf[1]; - args[1].length = dsp_attr_buf_len; - args[1].fd = -1; - fl->pd = 1; - - return fastrpc_internal_invoke(fl, true, FASTRPC_DSP_UTILITIES_HANDLE, - FASTRPC_SCALARS(0, 1, 1), args); -} - -static int fastrpc_get_info_from_kernel(struct fastrpc_ioctl_capability *cap, - struct fastrpc_user *fl) -{ - struct fastrpc_channel_ctx *cctx = fl->cctx; - uint32_t attribute_id = cap->attribute_id; - uint32_t *dsp_attributes; - unsigned long flags; - uint32_t domain = cap->domain; - int err; - - spin_lock_irqsave(&cctx->lock, flags); - /* check if we already have queried dsp for attributes */ - if (cctx->valid_attributes) { - spin_unlock_irqrestore(&cctx->lock, flags); - goto done; - } - spin_unlock_irqrestore(&cctx->lock, flags); - - dsp_attributes = kzalloc(FASTRPC_MAX_DSP_ATTRIBUTES_LEN, GFP_KERNEL); - if (!dsp_attributes) - return -ENOMEM; - - err = fastrpc_get_info_from_dsp(fl, dsp_attributes, FASTRPC_MAX_DSP_ATTRIBUTES_LEN); - if (err == DSP_UNSUPPORTED_API) { - dev_info(&cctx->rpdev->dev, - "Warning: DSP capabilities not supported on domain: %d\n", domain); - kfree(dsp_attributes); - return -EOPNOTSUPP; - } else if (err) { - dev_err(&cctx->rpdev->dev, "Error: dsp information is incorrect err: %d\n", err); - kfree(dsp_attributes); - return err; - } - - spin_lock_irqsave(&cctx->lock, flags); - memcpy(cctx->dsp_attributes, dsp_attributes, FASTRPC_MAX_DSP_ATTRIBUTES_LEN); - cctx->valid_attributes = true; - spin_unlock_irqrestore(&cctx->lock, flags); - kfree(dsp_attributes); -done: - cap->capability = cctx->dsp_attributes[attribute_id]; - return 0; -} - -static int fastrpc_get_dsp_info(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_ioctl_capability cap = {0}; - int err = 0; - - if (copy_from_user(&cap, argp, sizeof(cap))) - return -EFAULT; - - cap.capability = 0; - if (cap.domain >= FASTRPC_DEV_MAX) { - dev_err(&fl->cctx->rpdev->dev, "Error: Invalid domain id:%d, err:%d\n", - cap.domain, err); - return -ECHRNG; - } - - /* Fastrpc Capablities does not support modem domain */ - if (cap.domain == MDSP_DOMAIN_ID) { - dev_err(&fl->cctx->rpdev->dev, "Error: modem not supported %d\n", err); - return -ECHRNG; - } - - if (cap.attribute_id >= FASTRPC_MAX_DSP_ATTRIBUTES) { - dev_err(&fl->cctx->rpdev->dev, "Error: invalid attribute: %d, err: %d\n", - cap.attribute_id, err); - return -EOVERFLOW; - } - - err = fastrpc_get_info_from_kernel(&cap, fl); - if (err) - return err; - - if (copy_to_user(argp, &cap.capability, sizeof(cap.capability))) - return -EFAULT; - - return 0; -} - -static int fastrpc_req_munmap_impl(struct fastrpc_user *fl, - struct fastrpc_req_munmap *req) -{ - struct fastrpc_invoke_args args[1] = { [0] = { 0 } }; - struct fastrpc_buf *buf, *b; - struct fastrpc_munmap_req_msg req_msg; - struct device *dev = fl->sctx->dev; - int err; - u32 sc; - - spin_lock(&fl->lock); - list_for_each_entry_safe(buf, b, &fl->mmaps, node) { - if ((buf->raddr == req->vaddrout) && (buf->size == req->size)) - break; - buf = NULL; - } - spin_unlock(&fl->lock); - - if (!buf) { - dev_err(dev, "mmap not in list\n"); - return -EINVAL; - } - - req_msg.pgid = fl->tgid; - req_msg.size = buf->size; - req_msg.vaddr = buf->raddr; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MUNMAP, 1, 0); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - if (!err) { - dev_dbg(dev, "unmmap\tpt 0x%09lx OK\n", buf->raddr); - spin_lock(&fl->lock); - list_del(&buf->node); - spin_unlock(&fl->lock); - fastrpc_buf_free(buf); - } else { - dev_err(dev, "unmmap\tpt 0x%09lx ERROR\n", buf->raddr); - } - - return err; -} - -static int fastrpc_req_munmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_req_munmap req; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - return fastrpc_req_munmap_impl(fl, &req); -} - -static int fastrpc_req_mmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args args[3] = { [0 ... 2] = { 0 } }; - struct fastrpc_buf *buf = NULL; - struct fastrpc_mmap_req_msg req_msg; - struct fastrpc_mmap_rsp_msg rsp_msg; - struct fastrpc_req_munmap req_unmap; - struct fastrpc_phy_page pages; - struct fastrpc_req_mmap req; - struct device *dev = fl->sctx->dev; - int err; - u32 sc; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - if (req.flags != ADSP_MMAP_ADD_PAGES) { - dev_err(dev, "flag not supported 0x%x\n", req.flags); - return -EINVAL; - } - - if (req.vaddrin) { - dev_err(dev, "adding user allocated pages is not supported\n"); - return -EINVAL; - } - - err = fastrpc_buf_alloc(fl, fl->sctx->dev, req.size, &buf); - if (err) { - dev_err(dev, "failed to allocate buffer\n"); - return err; - } - - req_msg.pgid = fl->tgid; - req_msg.flags = req.flags; - req_msg.vaddr = req.vaddrin; - req_msg.num = sizeof(pages); - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - pages.addr = buf->phys; - pages.size = buf->size; - - args[1].ptr = (u64) (uintptr_t) &pages; - args[1].length = sizeof(pages); - - args[2].ptr = (u64) (uintptr_t) &rsp_msg; - args[2].length = sizeof(rsp_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MMAP, 2, 1); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - if (err) { - dev_err(dev, "mmap error (len 0x%08llx)\n", buf->size); - goto err_invoke; - } - - /* update the buffer to be able to deallocate the memory on the DSP */ - buf->raddr = (uintptr_t) rsp_msg.vaddr; - - /* let the client know the address to use */ - req.vaddrout = rsp_msg.vaddr; - - spin_lock(&fl->lock); - list_add_tail(&buf->node, &fl->mmaps); - spin_unlock(&fl->lock); - - if (copy_to_user((void __user *)argp, &req, sizeof(req))) { - /* unmap the memory and release the buffer */ - req_unmap.vaddrout = buf->raddr; - req_unmap.size = buf->size; - fastrpc_req_munmap_impl(fl, &req_unmap); - return -EFAULT; - } - - dev_dbg(dev, "mmap\t\tpt 0x%09lx OK [len 0x%08llx]\n", - buf->raddr, buf->size); - - return 0; - -err_invoke: - fastrpc_buf_free(buf); - - return err; -} - -static int fastrpc_req_mem_unmap_impl(struct fastrpc_user *fl, struct fastrpc_mem_unmap *req) -{ - struct fastrpc_invoke_args args[1] = { [0] = { 0 } }; - struct fastrpc_map *map = NULL, *m; - struct fastrpc_mem_unmap_req_msg req_msg = { 0 }; - int err = 0; - u32 sc; - struct device *dev = fl->sctx->dev; - - spin_lock(&fl->lock); - list_for_each_entry_safe(map, m, &fl->maps, node) { - if ((req->fd < 0 || map->fd == req->fd) && (map->raddr == req->vaddr)) - break; - map = NULL; - } - - spin_unlock(&fl->lock); - - if (!map) { - dev_err(dev, "map not in list\n"); - return -EINVAL; - } - - req_msg.pgid = fl->tgid; - req_msg.len = map->len; - req_msg.vaddrin = map->raddr; - req_msg.fd = map->fd; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_UNMAP, 1, 0); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, - &args[0]); - fastrpc_map_put(map); - if (err) - dev_err(dev, "unmmap\tpt fd = %d, 0x%09llx error\n", map->fd, map->raddr); - - return err; -} - -static int fastrpc_req_mem_unmap(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_mem_unmap req; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - return fastrpc_req_mem_unmap_impl(fl, &req); -} - -static int fastrpc_req_mem_map(struct fastrpc_user *fl, char __user *argp) -{ - struct fastrpc_invoke_args args[4] = { [0 ... 3] = { 0 } }; - struct fastrpc_mem_map_req_msg req_msg = { 0 }; - struct fastrpc_mmap_rsp_msg rsp_msg = { 0 }; - struct fastrpc_mem_unmap req_unmap = { 0 }; - struct fastrpc_phy_page pages = { 0 }; - struct fastrpc_mem_map req; - struct device *dev = fl->sctx->dev; - struct fastrpc_map *map = NULL; - int err; - u32 sc; - - if (copy_from_user(&req, argp, sizeof(req))) - return -EFAULT; - - /* create SMMU mapping */ - err = fastrpc_map_create(fl, req.fd, req.length, 0, &map); - if (err) { - dev_err(dev, "failed to map buffer, fd = %d\n", req.fd); - return err; - } - - req_msg.pgid = fl->tgid; - req_msg.fd = req.fd; - req_msg.offset = req.offset; - req_msg.vaddrin = req.vaddrin; - map->va = (void *) (uintptr_t) req.vaddrin; - req_msg.flags = req.flags; - req_msg.num = sizeof(pages); - req_msg.data_len = 0; - - args[0].ptr = (u64) (uintptr_t) &req_msg; - args[0].length = sizeof(req_msg); - - pages.addr = map->phys; - pages.size = map->size; - - args[1].ptr = (u64) (uintptr_t) &pages; - args[1].length = sizeof(pages); - - args[2].ptr = (u64) (uintptr_t) &pages; - args[2].length = 0; - - args[3].ptr = (u64) (uintptr_t) &rsp_msg; - args[3].length = sizeof(rsp_msg); - - sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_MAP, 3, 1); - err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, &args[0]); - if (err) { - dev_err(dev, "mem mmap error, fd %d, vaddr %llx, size %lld\n", - req.fd, req.vaddrin, map->size); - goto err_invoke; - } - - /* update the buffer to be able to deallocate the memory on the DSP */ - map->raddr = rsp_msg.vaddr; - - /* let the client know the address to use */ - req.vaddrout = rsp_msg.vaddr; - - if (copy_to_user((void __user *)argp, &req, sizeof(req))) { - /* unmap the memory and release the buffer */ - req_unmap.vaddr = (uintptr_t) rsp_msg.vaddr; - req_unmap.length = map->size; - fastrpc_req_mem_unmap_impl(fl, &req_unmap); - return -EFAULT; - } - - return 0; - -err_invoke: - fastrpc_map_put(map); - - return err; -} - -static long fastrpc_device_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - struct fastrpc_user *fl = (struct fastrpc_user *)file->private_data; - char __user *argp = (char __user *)arg; - int err; - - switch (cmd) { - case FASTRPC_IOCTL_INVOKE: - err = fastrpc_invoke(fl, argp); - break; - case FASTRPC_IOCTL_INIT_ATTACH: - err = fastrpc_init_attach(fl, AUDIO_PD); - break; - case FASTRPC_IOCTL_INIT_ATTACH_SNS: - err = fastrpc_init_attach(fl, SENSORS_PD); - break; - case FASTRPC_IOCTL_INIT_CREATE: - err = fastrpc_init_create_process(fl, argp); - break; - case FASTRPC_IOCTL_ALLOC_DMA_BUFF: - err = fastrpc_dmabuf_alloc(fl, argp); - break; - case FASTRPC_IOCTL_MMAP: - err = fastrpc_req_mmap(fl, argp); - break; - case FASTRPC_IOCTL_MUNMAP: - err = fastrpc_req_munmap(fl, argp); - break; - case FASTRPC_IOCTL_MEM_MAP: - err = fastrpc_req_mem_map(fl, argp); - break; - case FASTRPC_IOCTL_MEM_UNMAP: - err = fastrpc_req_mem_unmap(fl, argp); - break; - case FASTRPC_IOCTL_GET_DSP_INFO: - err = fastrpc_get_dsp_info(fl, argp); - break; - default: - err = -ENOTTY; - break; - } - - return err; -} - -static const struct file_operations fastrpc_fops = { - .open = fastrpc_device_open, - .release = fastrpc_device_release, - .unlocked_ioctl = fastrpc_device_ioctl, - .compat_ioctl = fastrpc_device_ioctl, -}; - -static int fastrpc_cb_probe(struct platform_device *pdev) -{ - struct fastrpc_channel_ctx *cctx; - struct fastrpc_session_ctx *sess; - struct device *dev = &pdev->dev; - int i, sessions = 0; - unsigned long flags; - int rc; - - cctx = dev_get_drvdata(dev->parent); - if (!cctx) - return -EINVAL; - - of_property_read_u32(dev->of_node, "qcom,nsessions", &sessions); - - spin_lock_irqsave(&cctx->lock, flags); - sess = &cctx->session[cctx->sesscount]; - sess->used = false; - sess->valid = true; - sess->dev = dev; - dev_set_drvdata(dev, sess); - - if (of_property_read_u32(dev->of_node, "reg", &sess->sid)) - dev_info(dev, "FastRPC Session ID not specified in DT\n"); - - if (sessions > 0) { - struct fastrpc_session_ctx *dup_sess; - - for (i = 1; i < sessions; i++) { - if (cctx->sesscount++ >= FASTRPC_MAX_SESSIONS) - break; - dup_sess = &cctx->session[cctx->sesscount]; - memcpy(dup_sess, sess, sizeof(*dup_sess)); - } - } - cctx->sesscount++; - spin_unlock_irqrestore(&cctx->lock, flags); - rc = dma_set_mask(dev, DMA_BIT_MASK(32)); - if (rc) { - dev_err(dev, "32-bit DMA enable failed\n"); - return rc; - } - - return 0; -} - -static int fastrpc_cb_remove(struct platform_device *pdev) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(pdev->dev.parent); - struct fastrpc_session_ctx *sess = dev_get_drvdata(&pdev->dev); - unsigned long flags; - int i; - - spin_lock_irqsave(&cctx->lock, flags); - for (i = 1; i < FASTRPC_MAX_SESSIONS; i++) { - if (cctx->session[i].sid == sess->sid) { - cctx->session[i].valid = false; - cctx->sesscount--; - } - } - spin_unlock_irqrestore(&cctx->lock, flags); - - return 0; -} - -static const struct of_device_id fastrpc_match_table[] = { - { .compatible = "qcom,fastrpc-compute-cb", }, - {} -}; - -static struct platform_driver fastrpc_cb_driver = { - .probe = fastrpc_cb_probe, - .remove = fastrpc_cb_remove, - .driver = { - .name = "qcom,fastrpc-cb", - .of_match_table = fastrpc_match_table, - .suppress_bind_attrs = true, - }, -}; - -static int fastrpc_device_register(struct device *dev, struct fastrpc_channel_ctx *cctx, - bool is_secured, const char *domain) -{ - struct fastrpc_device *fdev; - int err; - - fdev = devm_kzalloc(dev, sizeof(*fdev), GFP_KERNEL); - if (!fdev) - return -ENOMEM; - - fdev->secure = is_secured; - fdev->cctx = cctx; - fdev->miscdev.minor = MISC_DYNAMIC_MINOR; - fdev->miscdev.fops = &fastrpc_fops; - fdev->miscdev.name = devm_kasprintf(dev, GFP_KERNEL, "fastrpc-%s%s", - domain, is_secured ? "-secure" : ""); - err = misc_register(&fdev->miscdev); - if (!err) { - if (is_secured) - cctx->secure_fdevice = fdev; - else - cctx->fdevice = fdev; - } - - return err; -} - -static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) -{ - struct device *rdev = &rpdev->dev; - struct fastrpc_channel_ctx *data; - int i, err, domain_id = -1, vmcount; - const char *domain; - bool secure_dsp; - unsigned int vmids[FASTRPC_MAX_VMIDS]; - - err = of_property_read_string(rdev->of_node, "label", &domain); - if (err) { - dev_info(rdev, "FastRPC Domain not specified in DT\n"); - return err; - } - - for (i = 0; i <= CDSP_DOMAIN_ID; i++) { - if (!strcmp(domains[i], domain)) { - domain_id = i; - break; - } - } - - if (domain_id < 0) { - dev_info(rdev, "FastRPC Invalid Domain ID %d\n", domain_id); - return -EINVAL; - } - - vmcount = of_property_read_variable_u32_array(rdev->of_node, - "qcom,vmids", &vmids[0], 0, FASTRPC_MAX_VMIDS); - if (vmcount < 0) - vmcount = 0; - else if (!qcom_scm_is_available()) - return -EPROBE_DEFER; - - data = kzalloc(sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - if (vmcount) { - data->vmcount = vmcount; - data->perms = BIT(QCOM_SCM_VMID_HLOS); - for (i = 0; i < data->vmcount; i++) { - data->vmperms[i].vmid = vmids[i]; - data->vmperms[i].perm = QCOM_SCM_PERM_RWX; - } - } - - secure_dsp = !(of_property_read_bool(rdev->of_node, "qcom,non-secure-domain")); - data->secure = secure_dsp; - - switch (domain_id) { - case ADSP_DOMAIN_ID: - case MDSP_DOMAIN_ID: - case SDSP_DOMAIN_ID: - /* Unsigned PD offloading is only supported on CDSP*/ - data->unsigned_support = false; - err = fastrpc_device_register(rdev, data, secure_dsp, domains[domain_id]); - if (err) - goto fdev_error; - break; - case CDSP_DOMAIN_ID: - data->unsigned_support = true; - /* Create both device nodes so that we can allow both Signed and Unsigned PD */ - err = fastrpc_device_register(rdev, data, true, domains[domain_id]); - if (err) - goto fdev_error; - - err = fastrpc_device_register(rdev, data, false, domains[domain_id]); - if (err) - goto fdev_error; - break; - default: - err = -EINVAL; - goto fdev_error; - } - - kref_init(&data->refcount); - - dev_set_drvdata(&rpdev->dev, data); - dma_set_mask_and_coherent(rdev, DMA_BIT_MASK(32)); - INIT_LIST_HEAD(&data->users); - spin_lock_init(&data->lock); - idr_init(&data->ctx_idr); - data->domain_id = domain_id; - data->rpdev = rpdev; - - return of_platform_populate(rdev->of_node, NULL, NULL, rdev); -fdev_error: - kfree(data); - return err; -} - -static void fastrpc_notify_users(struct fastrpc_user *user) -{ - struct fastrpc_invoke_ctx *ctx; - - spin_lock(&user->lock); - list_for_each_entry(ctx, &user->pending, node) - complete(&ctx->work); - spin_unlock(&user->lock); -} - -static void fastrpc_rpmsg_remove(struct rpmsg_device *rpdev) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(&rpdev->dev); - struct fastrpc_user *user; - unsigned long flags; - - spin_lock_irqsave(&cctx->lock, flags); - list_for_each_entry(user, &cctx->users, user) - fastrpc_notify_users(user); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (cctx->fdevice) - misc_deregister(&cctx->fdevice->miscdev); - - if (cctx->secure_fdevice) - misc_deregister(&cctx->secure_fdevice->miscdev); - - of_platform_depopulate(&rpdev->dev); - - cctx->rpdev = NULL; - fastrpc_channel_ctx_put(cctx); -} - -static int fastrpc_rpmsg_callback(struct rpmsg_device *rpdev, void *data, - int len, void *priv, u32 addr) -{ - struct fastrpc_channel_ctx *cctx = dev_get_drvdata(&rpdev->dev); - struct fastrpc_invoke_rsp *rsp = data; - struct fastrpc_invoke_ctx *ctx; - unsigned long flags; - unsigned long ctxid; - - if (len < sizeof(*rsp)) - return -EINVAL; - - ctxid = ((rsp->ctx & FASTRPC_CTXID_MASK) >> 4); - - spin_lock_irqsave(&cctx->lock, flags); - ctx = idr_find(&cctx->ctx_idr, ctxid); - spin_unlock_irqrestore(&cctx->lock, flags); - - if (!ctx) { - dev_err(&rpdev->dev, "No context ID matches response\n"); - return -ENOENT; - } - - ctx->retval = rsp->retval; - complete(&ctx->work); - - /* - * The DMA buffer associated with the context cannot be freed in - * interrupt context so schedule it through a worker thread to - * avoid a kernel BUG. - */ - schedule_work(&ctx->put_work); - - return 0; -} - -static const struct of_device_id fastrpc_rpmsg_of_match[] = { - { .compatible = "qcom,fastrpc" }, - { }, -}; -MODULE_DEVICE_TABLE(of, fastrpc_rpmsg_of_match); - -static struct rpmsg_driver fastrpc_driver = { - .probe = fastrpc_rpmsg_probe, - .remove = fastrpc_rpmsg_remove, - .callback = fastrpc_rpmsg_callback, - .drv = { - .name = "qcom,fastrpc", - .of_match_table = fastrpc_rpmsg_of_match, - }, -}; - -static int fastrpc_init(void) -{ - int ret; - - ret = platform_driver_register(&fastrpc_cb_driver); - if (ret < 0) { - pr_err("fastrpc: failed to register cb driver\n"); - return ret; - } - - ret = register_rpmsg_driver(&fastrpc_driver); - if (ret < 0) { - pr_err("fastrpc: failed to register rpmsg driver\n"); - platform_driver_unregister(&fastrpc_cb_driver); - return ret; - } - - return 0; -} -module_init(fastrpc_init); - -static void fastrpc_exit(void) -{ - platform_driver_unregister(&fastrpc_cb_driver); - unregister_rpmsg_driver(&fastrpc_driver); -} -module_exit(fastrpc_exit); - -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/e5b0cf21321cbcfd76b908f3e8ebc7b5e2150b4e/postimage b/rr-cache/e5b0cf21321cbcfd76b908f3e8ebc7b5e2150b4e/postimage deleted file mode 100644 index 66f3b5a..0000000 --- a/rr-cache/e5b0cf21321cbcfd76b908f3e8ebc7b5e2150b4e/postimage +++ /dev/null @@ -1,666 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -/dts-v1/; - -#include -#include -#include "sm8150.dtsi" -#include "pmm8155au_1.dtsi" -#include "pmm8155au_2.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SA8155P ADP"; - compatible = "qcom,sa8155p-adp", "qcom,sa8155p"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vreg_3p3: vreg_3p3_regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_3p3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* - * S4A is always on and not controllable through RPMh. - * So model it as a fixed regulator. - */ - vreg_s4a_1p8: smps4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - - vin-supply = <&vreg_3p3>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xC>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; - snps,tx-sched-wrr; - - queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; - }; - - queue1 { - snps,weight = <0x11>; - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue2 { - snps,weight = <0x12>; - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue3 { - snps,weight = <0x13>; - snps,dcb-algorithm; - snps,priority = <0x3>; - }; - }; -}; - -&apps_rsc { - pmm8155au-1-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>; - vdd-l6-l9-supply = <&vreg_s6a_0p92>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s5a_2p04: smps5 { - regulator-name = "vreg_s5a_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6a_0p92: smps6 { - regulator-name = "vreg_s6a_0p92"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1a_0p752: ldo1 { - regulator-name = "vreg_l1a_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_3p1: - vreg_l2a_3p072: ldo2 { - regulator-name = "vreg_l2a_3p072"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p8: ldo3 { - regulator-name = "vreg_l3a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdd_usb_hs_core: - vdda_usb_ss_dp_core_1: - vreg_l5a_0p88: ldo5 { - regulator-name = "vreg_l5a_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7a_1p8: ldo7 { - regulator-name = "vreg_l7a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l10a_2p96: ldo10 { - regulator-name = "vreg_l10a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l11a_0p8: ldo11 { - regulator-name = "vreg_l11a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_1p8: - vreg_l12a_1p8: ldo12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p7: ldo13 { - regulator-name = "vreg_l13a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p7: ldo15 { - regulator-name = "vreg_l15a_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1704000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_2p96: ldo17 { - regulator-name = "vreg_l17a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - }; - - pmm8155au-2-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>; - vdd-l6-l9-supply = <&vreg_s6c_1p128>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s4c_1p352: smps4 { - regulator-name = "vreg_s4c_1p352"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5c_2p04: smps5 { - regulator-name = "vreg_s5c_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6c_1p128: smps6 { - regulator-name = "vreg_s6c_1p128"; - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1c_1p304: ldo1 { - regulator-name = "vreg_l1c_1p304"; - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p808: ldo2 { - regulator-name = "vreg_l2c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p2: ldo5 { - regulator-name = "vreg_l5c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7c_1p8: ldo7 { - regulator-name = "vreg_l7c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p2: ldo8 { - regulator-name = "vreg_l8c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l10c_3p3: ldo10 { - regulator-name = "vreg_l10c_3p3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l11c_0p8: ldo11 { - regulator-name = "vreg_l11c_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l12c_1p808: ldo12 { - regulator-name = "vreg_l12c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l13c_2p96: ldo13 { - regulator-name = "vreg_l13c_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l15c_1p9: ldo15 { - regulator-name = "vreg_l15c_1p9"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l16c_3p008: ldo16 { - regulator-name = "vreg_l16c_3p008"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l18c_0p88: ldo18 { - regulator-name = "vreg_l18c_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - }; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -ðernet { - status = "okay"; - - snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 11000 70000>; - - snps,ptp-ref-clk-rate = <250000000>; - snps,ptp-req-clk-rate = <96000000>; - - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - - pinctrl-names = "default"; - pinctrl-0 = <ðernet_defaults>; - - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - - compatible = "snps,dwmac-mdio"; - - /* Micrel KSZ9031RNZ PHY */ - rgmii_phy: phy@7 { - reg = <0x7>; - - interrupt-parent = <&tlmm>; - interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ - device_type = "ethernet-phy"; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&remoteproc_adsp { - status = "okay"; - firmware-name = "qcom/sa8155p/adsp.mdt"; -}; - -&remoteproc_cdsp { - status = "okay"; - firmware-name = "qcom/sa8155p/cdsp.mdt"; -}; - -&sdhc_2 { - status = "okay"; - - cd-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; - vqmmc-supply = <&vreg_l13c_2p96>; /* IO line power */ - vmmc-supply = <&vreg_l17a_2p96>; /* Card power line */ - bus-width = <4>; - no-sdio; - no-emmc; -}; - -&uart2 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l10a_2p96>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l5c_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-max-microamp = <87100>; - vdda-pll-supply = <&vreg_l5a_0p88>; - vdda-pll-max-microamp = <18300>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en1_default>; -}; - -&usb_1_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_1_qmpphy { - status = "disabled"; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en2_default>; -}; - -&usb_2_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_2_qmpphy { - status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie0_phy { - status = "okay"; - vdda-phy-supply = <&vreg_l18c_0p88>; - vdda-pll-supply = <&vreg_l8c_1p2>; -}; - -&pcie1_phy { - vdda-phy-supply = <&vreg_l18c_0p88>; - vdda-pll-supply = <&vreg_l8c_1p2>; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>; - - bt_en_default: bt_en_default { - mux { - pins = "gpio172"; - function = "gpio"; - }; - - config { - pins = "gpio172"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - wlan_en_default: wlan_en_default { - mux { - pins = "gpio169"; - function = "gpio"; - }; - - config { - pins = "gpio169"; - drive-strength = <16>; - output-high; - bias-pull-up; - }; - }; - - sdc2_on: sdc2_on { - clk { - pins = "sdc2_clk"; - bias-disable; /* No pull */ - drive-strength = <16>; /* 16 MA */ - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - - data { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - - sd-cd { - pins = "gpio96"; - function = "gpio"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_off: sdc2_off { - clk { - pins = "sdc2_clk"; - bias-disable; /* No pull */ - drive-strength = <2>; /* 2 MA */ - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - - data { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - - sd-cd { - pins = "gpio96"; - function = "gpio"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - usb2phy_ac_en1_default: usb2phy_ac_en1_default { - mux { - pins = "gpio113"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - usb2phy_ac_en2_default: usb2phy_ac_en2_default { - mux { - pins = "gpio123"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - ethernet_defaults: ethernet-defaults { - mdc { - pins = "gpio7"; - function = "rgmii"; - bias-pull-up; - }; - - mdio { - pins = "gpio59"; - function = "rgmii"; - bias-pull-up; - }; - - rgmii-rx { - pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116"; - function = "rgmii"; - bias-disable; - drive-strength = <2>; - }; - - rgmii-tx { - pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121"; - function = "rgmii"; - bias-pull-up; - drive-strength = <16>; - }; - - phy-intr { - pins = "gpio124"; - function = "emac_phy"; - bias-disable; - drive-strength = <8>; - }; - - pps { - pins = "gpio81"; - function = "emac_pps"; - bias-disable; - drive-strength = <8>; - }; - - phy-reset { - pins = "gpio79"; - function = "gpio"; - bias-pull-up; - drive-strength = <16>; - }; - }; -}; diff --git a/rr-cache/e5b0cf21321cbcfd76b908f3e8ebc7b5e2150b4e/preimage b/rr-cache/e5b0cf21321cbcfd76b908f3e8ebc7b5e2150b4e/preimage deleted file mode 100644 index b7b79d6..0000000 --- a/rr-cache/e5b0cf21321cbcfd76b908f3e8ebc7b5e2150b4e/preimage +++ /dev/null @@ -1,666 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -/dts-v1/; - -#include -#include -#include "sm8150.dtsi" -#include "pmm8155au_1.dtsi" -#include "pmm8155au_2.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SA8155P ADP"; - compatible = "qcom,sa8155p-adp", "qcom,sa8155p"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vreg_3p3: vreg_3p3_regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_3p3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* - * S4A is always on and not controllable through RPMh. - * So model it as a fixed regulator. - */ - vreg_s4a_1p8: smps4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - - vin-supply = <&vreg_3p3>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xC>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; - snps,tx-sched-wrr; - - queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; - }; - - queue1 { - snps,weight = <0x11>; - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue2 { - snps,weight = <0x12>; - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue3 { - snps,weight = <0x13>; - snps,dcb-algorithm; - snps,priority = <0x3>; - }; - }; -}; - -&apps_rsc { - pmm8155au-1-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>; - vdd-l6-l9-supply = <&vreg_s6a_0p92>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s5a_2p04: smps5 { - regulator-name = "vreg_s5a_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6a_0p92: smps6 { - regulator-name = "vreg_s6a_0p92"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1a_0p752: ldo1 { - regulator-name = "vreg_l1a_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_3p1: - vreg_l2a_3p072: ldo2 { - regulator-name = "vreg_l2a_3p072"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p8: ldo3 { - regulator-name = "vreg_l3a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdd_usb_hs_core: - vdda_usb_ss_dp_core_1: - vreg_l5a_0p88: ldo5 { - regulator-name = "vreg_l5a_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7a_1p8: ldo7 { - regulator-name = "vreg_l7a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l10a_2p96: ldo10 { - regulator-name = "vreg_l10a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l11a_0p8: ldo11 { - regulator-name = "vreg_l11a_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs_1p8: - vreg_l12a_1p8: ldo12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p7: ldo13 { - regulator-name = "vreg_l13a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p7: ldo15 { - regulator-name = "vreg_l15a_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1704000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_2p96: ldo17 { - regulator-name = "vreg_l17a_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - }; - - pmm8155au-2-rpmh-regulators { - compatible = "qcom,pmm8155au-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vreg_3p3>; - vdd-s2-supply = <&vreg_3p3>; - vdd-s3-supply = <&vreg_3p3>; - vdd-s4-supply = <&vreg_3p3>; - vdd-s5-supply = <&vreg_3p3>; - vdd-s6-supply = <&vreg_3p3>; - vdd-s7-supply = <&vreg_3p3>; - vdd-s8-supply = <&vreg_3p3>; - vdd-s9-supply = <&vreg_3p3>; - vdd-s10-supply = <&vreg_3p3>; - - vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>; - vdd-l2-l10-supply = <&vreg_3p3>; - vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>; - vdd-l6-l9-supply = <&vreg_s6c_1p128>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>; - vdd-l13-l16-l17-supply = <&vreg_3p3>; - - vreg_s4c_1p352: smps4 { - regulator-name = "vreg_s4c_1p352"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5c_2p04: smps5 { - regulator-name = "vreg_s5c_2p04"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6c_1p128: smps6 { - regulator-name = "vreg_s6c_1p128"; - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_l1c_1p304: ldo1 { - regulator-name = "vreg_l1c_1p304"; - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p808: ldo2 { - regulator-name = "vreg_l2c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p2: ldo5 { - regulator-name = "vreg_l5c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l7c_1p8: ldo7 { - regulator-name = "vreg_l7c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p2: ldo8 { - regulator-name = "vreg_l8c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-allow-set-load; - }; - - vreg_l10c_3p3: ldo10 { - regulator-name = "vreg_l10c_3p3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l11c_0p8: ldo11 { - regulator-name = "vreg_l11c_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l12c_1p808: ldo12 { - regulator-name = "vreg_l12c_1p808"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l13c_2p96: ldo13 { - regulator-name = "vreg_l13c_2p96"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l15c_1p9: ldo15 { - regulator-name = "vreg_l15c_1p9"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l16c_3p008: ldo16 { - regulator-name = "vreg_l16c_3p008"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l18c_0p88: ldo18 { - regulator-name = "vreg_l18c_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - }; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -ðernet { - status = "okay"; - - snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 11000 70000>; - - snps,ptp-ref-clk-rate = <250000000>; - snps,ptp-req-clk-rate = <96000000>; - - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - - pinctrl-names = "default"; - pinctrl-0 = <ðernet_defaults>; - - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - - compatible = "snps,dwmac-mdio"; - - /* Micrel KSZ9031RNZ PHY */ - rgmii_phy: phy@7 { - reg = <0x7>; - - interrupt-parent = <&tlmm>; - interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ - device_type = "ethernet-phy"; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&remoteproc_adsp { - status = "okay"; - firmware-name = "qcom/sa8155p/adsp.mdt"; -}; - -&remoteproc_cdsp { - status = "okay"; - firmware-name = "qcom/sa8155p/cdsp.mdt"; -}; - -&sdhc_2 { - status = "okay"; - - cd-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; - vqmmc-supply = <&vreg_l13c_2p96>; /* IO line power */ - vmmc-supply = <&vreg_l17a_2p96>; /* Card power line */ - bus-width = <4>; - no-sdio; - no-emmc; -}; - -&uart2 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l10a_2p96>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l5c_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-max-microamp = <87100>; - vdda-pll-supply = <&vreg_l5a_0p88>; - vdda-pll-max-microamp = <18300>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en1_default>; -}; - -&usb_1_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_1_qmpphy { - status = "disabled"; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb2phy_ac_en2_default>; -}; - -&usb_2_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_2_qmpphy { - status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie0_phy { - status = "okay"; - vdda-phy-supply = <&vreg_l18c_0p88>; - vdda-pll-supply = <&vreg_l8c_1p2>; -}; - -&pcie1_phy { - vdda-phy-supply = <&vreg_l18c_0p88>; - vdda-pll-supply = <&vreg_l8c_1p2>; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>; - -<<<<<<< - bt_en_default: bt_en_default { - mux { - pins = "gpio172"; - function = "gpio"; - }; - - config { - pins = "gpio172"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - wlan_en_default: wlan_en_default { - mux { - pins = "gpio169"; - function = "gpio"; - }; - - config { - pins = "gpio169"; - drive-strength = <16>; - output-high; - bias-pull-up; -======= - sdc2_on: sdc2_on { - clk { - pins = "sdc2_clk"; - bias-disable; /* No pull */ - drive-strength = <16>; /* 16 MA */ - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - - data { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - - sd-cd { - pins = "gpio96"; - function = "gpio"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_off: sdc2_off { - clk { - pins = "sdc2_clk"; - bias-disable; /* No pull */ - drive-strength = <2>; /* 2 MA */ - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - - data { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - - sd-cd { - pins = "gpio96"; - function = "gpio"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ ->>>>>>> - }; - }; - - usb2phy_ac_en1_default: usb2phy_ac_en1_default { - mux { - pins = "gpio113"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - usb2phy_ac_en2_default: usb2phy_ac_en2_default { - mux { - pins = "gpio123"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; - }; - - ethernet_defaults: ethernet-defaults { - mdc { - pins = "gpio7"; - function = "rgmii"; - bias-pull-up; - }; - - mdio { - pins = "gpio59"; - function = "rgmii"; - bias-pull-up; - }; - - rgmii-rx { - pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116"; - function = "rgmii"; - bias-disable; - drive-strength = <2>; - }; - - rgmii-tx { - pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121"; - function = "rgmii"; - bias-pull-up; - drive-strength = <16>; - }; - - phy-intr { - pins = "gpio124"; - function = "emac_phy"; - bias-disable; - drive-strength = <8>; - }; - - pps { - pins = "gpio81"; - function = "emac_pps"; - bias-disable; - drive-strength = <8>; - }; - - phy-reset { - pins = "gpio79"; - function = "gpio"; - bias-pull-up; - drive-strength = <16>; - }; - }; -}; diff --git a/rr-cache/e9839dd048e638e26be255ff1aa2ad010ec54d45/preimage b/rr-cache/e9839dd048e638e26be255ff1aa2ad010ec54d45/preimage deleted file mode 100644 index 57c0234..0000000 --- a/rr-cache/e9839dd048e638e26be255ff1aa2ad010ec54d45/preimage +++ /dev/null @@ -1,646 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - */ - -#include -#include "dpu_hwio.h" -#include "dpu_hw_ctl.h" -#include "dpu_kms.h" -#include "dpu_trace.h" - -#define CTL_LAYER(lm) \ - (((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004)) -#define CTL_LAYER_EXT(lm) \ - (0x40 + (((lm) - LM_0) * 0x004)) -#define CTL_LAYER_EXT2(lm) \ - (0x70 + (((lm) - LM_0) * 0x004)) -#define CTL_LAYER_EXT3(lm) \ - (0xA0 + (((lm) - LM_0) * 0x004)) -#define CTL_TOP 0x014 -#define CTL_FLUSH 0x018 -#define CTL_START 0x01C -#define CTL_PREPARE 0x0d0 -#define CTL_SW_RESET 0x030 -#define CTL_LAYER_EXTN_OFFSET 0x40 -#define CTL_MERGE_3D_ACTIVE 0x0E4 -#define CTL_INTF_ACTIVE 0x0F4 -#define CTL_MERGE_3D_FLUSH 0x100 -#define CTL_INTF_FLUSH 0x110 -#define CTL_INTF_MASTER 0x134 -#define CTL_FETCH_PIPE_ACTIVE 0x0FC - -#define CTL_MIXER_BORDER_OUT BIT(24) -#define CTL_FLUSH_MASK_CTL BIT(17) - -#define DPU_REG_RESET_TIMEOUT_US 2000 -#define MERGE_3D_IDX 23 -#define INTF_IDX 31 -#define CTL_INVALID_BIT 0xffff -#define CTL_DEFAULT_GROUP_ID 0xf - -static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19, - CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0, - 1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT}; - -static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl, - const struct dpu_mdss_cfg *m, - void __iomem *addr, - struct dpu_hw_blk_reg_map *b) -{ - int i; - - for (i = 0; i < m->ctl_count; i++) { - if (ctl == m->ctl[i].id) { - b->base_off = addr; - b->blk_off = m->ctl[i].base; - b->length = m->ctl[i].len; - b->hwversion = m->hwversion; - b->log_mask = DPU_DBG_MASK_CTL; - return &m->ctl[i]; - } - } - return ERR_PTR(-ENOMEM); -} - -static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count, - enum dpu_lm lm) -{ - int i; - int stages = -EINVAL; - - for (i = 0; i < count; i++) { - if (lm == mixer[i].id) { - stages = mixer[i].sblk->maxblendstages; - break; - } - } - - return stages; -} - -static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - - return DPU_REG_READ(c, CTL_FLUSH); -} - -static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx) -{ - trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask, - dpu_hw_ctl_get_flush_register(ctx)); - DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1); -} - -static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx) -{ - trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask, - dpu_hw_ctl_get_flush_register(ctx)); - DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1); -} - -static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) -{ - trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask, - dpu_hw_ctl_get_flush_register(ctx)); - ctx->pending_flush_mask = 0x0; -} - -static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx, - u32 flushbits) -{ - trace_dpu_hw_ctl_update_pending_flush(flushbits, - ctx->pending_flush_mask); - ctx->pending_flush_mask |= flushbits; -} - -static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) -{ - return ctx->pending_flush_mask; -} - -static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) -{ - - if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) - DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, - ctx->pending_merge_3d_flush_mask); - if (ctx->pending_flush_mask & BIT(INTF_IDX)) - DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH, - ctx->pending_intf_flush_mask); - - DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); -} - -static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx) -{ - trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask, - dpu_hw_ctl_get_flush_register(ctx)); - DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); -} - -static uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx, - enum dpu_sspp sspp) -{ - uint32_t flushbits = 0; - - switch (sspp) { - case SSPP_VIG0: - flushbits = BIT(0); - break; - case SSPP_VIG1: - flushbits = BIT(1); - break; - case SSPP_VIG2: - flushbits = BIT(2); - break; - case SSPP_VIG3: - flushbits = BIT(18); - break; - case SSPP_RGB0: - flushbits = BIT(3); - break; - case SSPP_RGB1: - flushbits = BIT(4); - break; - case SSPP_RGB2: - flushbits = BIT(5); - break; - case SSPP_RGB3: - flushbits = BIT(19); - break; - case SSPP_DMA0: - flushbits = BIT(11); - break; - case SSPP_DMA1: - flushbits = BIT(12); - break; - case SSPP_DMA2: - flushbits = BIT(24); - break; - case SSPP_DMA3: - flushbits = BIT(25); - break; - case SSPP_CURSOR0: - flushbits = BIT(22); - break; - case SSPP_CURSOR1: - flushbits = BIT(23); - break; - default: - break; - } - - return flushbits; -} - -static uint32_t dpu_hw_ctl_get_bitmask_mixer(struct dpu_hw_ctl *ctx, - enum dpu_lm lm) -{ - uint32_t flushbits = 0; - - switch (lm) { - case LM_0: - flushbits = BIT(6); - break; - case LM_1: - flushbits = BIT(7); - break; - case LM_2: - flushbits = BIT(8); - break; - case LM_3: - flushbits = BIT(9); - break; - case LM_4: - flushbits = BIT(10); - break; - case LM_5: - flushbits = BIT(20); - break; - default: - return -EINVAL; - } - - flushbits |= CTL_FLUSH_MASK_CTL; - - return flushbits; -} - -static void dpu_hw_ctl_update_pending_flush_intf(struct dpu_hw_ctl *ctx, - enum dpu_intf intf) -{ - switch (intf) { - case INTF_0: - ctx->pending_flush_mask |= BIT(31); - break; - case INTF_1: - ctx->pending_flush_mask |= BIT(30); - break; - case INTF_2: - ctx->pending_flush_mask |= BIT(29); - break; - case INTF_3: - ctx->pending_flush_mask |= BIT(28); - break; - default: - break; - } -} - -static void dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx, - enum dpu_intf intf) -{ - ctx->pending_intf_flush_mask |= BIT(intf - INTF_0); - ctx->pending_flush_mask |= BIT(INTF_IDX); -} - -static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx, - enum dpu_merge_3d merge_3d) -{ - ctx->pending_merge_3d_flush_mask |= BIT(merge_3d - MERGE_3D_0); - ctx->pending_flush_mask |= BIT(MERGE_3D_IDX); -} - -static uint32_t dpu_hw_ctl_get_bitmask_dspp(struct dpu_hw_ctl *ctx, - enum dpu_dspp dspp) -{ - uint32_t flushbits = 0; - - switch (dspp) { - case DSPP_0: - flushbits = BIT(13); - break; - case DSPP_1: - flushbits = BIT(14); - break; - case DSPP_2: - flushbits = BIT(15); - break; - case DSPP_3: - flushbits = BIT(21); - break; - default: - return 0; - } - - return flushbits; -} - -static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - ktime_t timeout; - u32 status; - - timeout = ktime_add_us(ktime_get(), timeout_us); - - /* - * it takes around 30us to have mdp finish resetting its ctl path - * poll every 50us so that reset should be completed at 1st poll - */ - do { - status = DPU_REG_READ(c, CTL_SW_RESET); - status &= 0x1; - if (status) - usleep_range(20, 50); - } while (status && ktime_compare_safe(ktime_get(), timeout) < 0); - - return status; -} - -static int dpu_hw_ctl_reset_control(struct dpu_hw_ctl *ctx) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - - pr_debug("issuing hw ctl reset for ctl:%d\n", ctx->idx); - DPU_REG_WRITE(c, CTL_SW_RESET, 0x1); - if (dpu_hw_ctl_poll_reset_status(ctx, DPU_REG_RESET_TIMEOUT_US)) - return -EINVAL; - - return 0; -} - -static int dpu_hw_ctl_wait_reset_status(struct dpu_hw_ctl *ctx) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - u32 status; - - status = DPU_REG_READ(c, CTL_SW_RESET); - status &= 0x01; - if (!status) - return 0; - - pr_debug("hw ctl reset is set for ctl:%d\n", ctx->idx); - if (dpu_hw_ctl_poll_reset_status(ctx, DPU_REG_RESET_TIMEOUT_US)) { - pr_err("hw recovery is not complete for ctl:%d\n", ctx->idx); - return -EINVAL; - } - - return 0; -} - -static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - int i; - - for (i = 0; i < ctx->mixer_count; i++) { - enum dpu_lm mixer_id = ctx->mixer_hw_caps[i].id; - - DPU_REG_WRITE(c, CTL_LAYER(mixer_id), 0); - DPU_REG_WRITE(c, CTL_LAYER_EXT(mixer_id), 0); - DPU_REG_WRITE(c, CTL_LAYER_EXT2(mixer_id), 0); - DPU_REG_WRITE(c, CTL_LAYER_EXT3(mixer_id), 0); - } - - DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0); -} - -static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, - enum dpu_lm lm, struct dpu_hw_stage_cfg *stage_cfg) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - u32 mixercfg = 0, mixercfg_ext = 0, mix, ext; - u32 mixercfg_ext2 = 0, mixercfg_ext3 = 0; - int i, j; - int stages; - int pipes_per_stage; - - stages = _mixer_stages(ctx->mixer_hw_caps, ctx->mixer_count, lm); - if (stages < 0) - return; - - if (test_bit(DPU_MIXER_SOURCESPLIT, - &ctx->mixer_hw_caps->features)) - pipes_per_stage = PIPES_PER_STAGE; - else - pipes_per_stage = 1; - - mixercfg = CTL_MIXER_BORDER_OUT; /* always set BORDER_OUT */ - - if (!stage_cfg) - goto exit; - - for (i = 0; i <= stages; i++) { - /* overflow to ext register if 'i + 1 > 7' */ - mix = (i + 1) & 0x7; - ext = i >= 7; - - for (j = 0 ; j < pipes_per_stage; j++) { - enum dpu_sspp_multirect_index rect_index = - stage_cfg->multirect_index[i][j]; - - switch (stage_cfg->stage[i][j]) { - case SSPP_VIG0: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext3 |= ((i + 1) & 0xF) << 0; - } else { - mixercfg |= mix << 0; - mixercfg_ext |= ext << 0; - } - break; - case SSPP_VIG1: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext3 |= ((i + 1) & 0xF) << 4; - } else { - mixercfg |= mix << 3; - mixercfg_ext |= ext << 2; - } - break; - case SSPP_VIG2: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext3 |= ((i + 1) & 0xF) << 8; - } else { - mixercfg |= mix << 6; - mixercfg_ext |= ext << 4; - } - break; - case SSPP_VIG3: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext3 |= ((i + 1) & 0xF) << 12; - } else { - mixercfg |= mix << 26; - mixercfg_ext |= ext << 6; - } - break; - case SSPP_RGB0: - mixercfg |= mix << 9; - mixercfg_ext |= ext << 8; - break; - case SSPP_RGB1: - mixercfg |= mix << 12; - mixercfg_ext |= ext << 10; - break; - case SSPP_RGB2: - mixercfg |= mix << 15; - mixercfg_ext |= ext << 12; - break; - case SSPP_RGB3: - mixercfg |= mix << 29; - mixercfg_ext |= ext << 14; - break; - case SSPP_DMA0: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext2 |= ((i + 1) & 0xF) << 8; - } else { - mixercfg |= mix << 18; - mixercfg_ext |= ext << 16; - } - break; - case SSPP_DMA1: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext2 |= ((i + 1) & 0xF) << 12; - } else { - mixercfg |= mix << 21; - mixercfg_ext |= ext << 18; - } - break; - case SSPP_DMA2: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext2 |= ((i + 1) & 0xF) << 16; - } else { - mix |= (i + 1) & 0xF; - mixercfg_ext2 |= mix << 0; - } - break; - case SSPP_DMA3: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext2 |= ((i + 1) & 0xF) << 20; - } else { - mix |= (i + 1) & 0xF; - mixercfg_ext2 |= mix << 4; - } - break; - case SSPP_CURSOR0: - mixercfg_ext |= ((i + 1) & 0xF) << 20; - break; - case SSPP_CURSOR1: - mixercfg_ext |= ((i + 1) & 0xF) << 26; - break; - default: - break; - } - } - } - -exit: - DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg); - DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext); - DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2); - DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3); -} - - -static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, - struct dpu_hw_intf_cfg *cfg) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - u32 intf_active = 0; - u32 mode_sel = 0; - u32 merge_3d_active = 0; -<<<<<<< -======= - - /* CTL_TOP[31:28] carries group_id to collate CTL paths - * per VM. Explicitly disable it until VM support is - * added in SW. Power on reset value is not disable. - */ - if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features))) - mode_sel = CTL_DEFAULT_GROUP_ID << 28; ->>>>>>> - - if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD) - mode_sel |= BIT(17); - - intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); - intf_active |= BIT(cfg->intf - INTF_0); - - merge_3d_active = DPU_REG_READ(c, CTL_MERGE_3D_ACTIVE); - if (cfg->merge_3d) - merge_3d_active |= BIT(cfg->merge_3d - MERGE_3D_0); - - DPU_REG_WRITE(c, CTL_TOP, mode_sel); - DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); - if (cfg->intf_master) - DPU_REG_WRITE(c, CTL_INTF_MASTER, BIT(cfg->intf_master - INTF_0)); - if (cfg->merge_3d) - DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active); - - if (cfg->intf_master) - DPU_ERROR("ACTIVE: %x %x %lx\n", intf_active, merge_3d_active, BIT(cfg->intf_master - INTF_0)); - else - DPU_ERROR("ACTIVE: %x %x\n", intf_active, merge_3d_active); -} - -static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, - struct dpu_hw_intf_cfg *cfg) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - u32 intf_cfg = 0; - - intf_cfg |= (cfg->intf & 0xF) << 4; - - if (cfg->mode_3d) { - intf_cfg |= BIT(19); - intf_cfg |= (cfg->mode_3d - 0x1) << 20; - } - - switch (cfg->intf_mode_sel) { - case DPU_CTL_MODE_SEL_VID: - intf_cfg &= ~BIT(17); - intf_cfg &= ~(0x3 << 15); - break; - case DPU_CTL_MODE_SEL_CMD: - intf_cfg |= BIT(17); - intf_cfg |= ((cfg->stream_sel & 0x3) << 15); - break; - default: - pr_err("unknown interface type %d\n", cfg->intf_mode_sel); - return; - } - - DPU_REG_WRITE(c, CTL_TOP, intf_cfg); -} - -static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx, - unsigned long *fetch_active) -{ - int i; - u32 val = 0; - - if (fetch_active) { - for (i = 0; i < SSPP_MAX; i++) { - if (test_bit(i, fetch_active) && - fetch_tbl[i] != CTL_INVALID_BIT) - val |= BIT(fetch_tbl[i]); - } - } - - DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val); -} - -static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, - unsigned long cap) -{ - if (cap & BIT(DPU_CTL_ACTIVE_CFG)) { - ops->trigger_flush = dpu_hw_ctl_trigger_flush_v1; - ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1; - ops->update_pending_flush_intf = - dpu_hw_ctl_update_pending_flush_intf_v1; - ops->update_pending_flush_merge_3d = - dpu_hw_ctl_update_pending_flush_merge_3d_v1; - } else { - ops->trigger_flush = dpu_hw_ctl_trigger_flush; - ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg; - ops->update_pending_flush_intf = - dpu_hw_ctl_update_pending_flush_intf; - } - ops->clear_pending_flush = dpu_hw_ctl_clear_pending_flush; - ops->update_pending_flush = dpu_hw_ctl_update_pending_flush; - ops->get_pending_flush = dpu_hw_ctl_get_pending_flush; - ops->get_flush_register = dpu_hw_ctl_get_flush_register; - ops->trigger_start = dpu_hw_ctl_trigger_start; - ops->trigger_pending = dpu_hw_ctl_trigger_pending; - ops->reset = dpu_hw_ctl_reset_control; - ops->wait_reset_status = dpu_hw_ctl_wait_reset_status; - ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages; - ops->setup_blendstage = dpu_hw_ctl_setup_blendstage; - ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp; - ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer; - ops->get_bitmask_dspp = dpu_hw_ctl_get_bitmask_dspp; - if (cap & BIT(DPU_CTL_FETCH_ACTIVE)) - ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active; -}; - -struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, - void __iomem *addr, - const struct dpu_mdss_cfg *m) -{ - struct dpu_hw_ctl *c; - const struct dpu_ctl_cfg *cfg; - - c = kzalloc(sizeof(*c), GFP_KERNEL); - if (!c) - return ERR_PTR(-ENOMEM); - - cfg = _ctl_offset(idx, m, addr, &c->hw); - if (IS_ERR_OR_NULL(cfg)) { - kfree(c); - pr_err("failed to create dpu_hw_ctl %d\n", idx); - return ERR_PTR(-EINVAL); - } - - c->caps = cfg; - _setup_ctl_ops(&c->ops, c->caps->features); - c->idx = idx; - c->mixer_count = m->mixer_count; - c->mixer_hw_caps = m->mixer; - - return c; -} - -void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx) -{ - kfree(ctx); -} diff --git a/rr-cache/eb2a574f27709226377dc4000c4882d227af3594/preimage.1 b/rr-cache/eb2a574f27709226377dc4000c4882d227af3594/preimage.1 deleted file mode 100644 index 87a0d87..0000000 --- a/rr-cache/eb2a574f27709226377dc4000c4882d227af3594/preimage.1 +++ /dev/null @@ -1,1029 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include -#include -#include -#include -#include "sm8250.dtsi" -#include "pm8150.dtsi" -#include "pm8150b.dtsi" -#include "pm8150l.dtsi" -#include "pm8009.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SM8250 MTP"; - compatible = "qcom,sm8250-mtp", "qcom,sm8250"; - - aliases { - serial0 = &uart12; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - thermal-zones { - camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150l_adc_tm 0>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - conn-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150b_adc_tm 0>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - mmw-pa1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150_adc_tm 2>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - mmw-pa2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150l_adc_tm 2>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - skin-msm-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150l_adc_tm 1>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - skin-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150_adc_tm 1>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8150_adc_tm 0>; - - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - vreg_s4a_1p8: pm8150-s4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; - - vreg_s6c_0p88: smpc6-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_s6c_0p88"; - - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-always-on; - vin-supply = <&vph_pwr>; - }; - - display_panel_avdd: display_gpio_regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "display_panel_avdd"; - regulator-min-microvolt = <5500000>; - regulator-max-microvolt = <5500000>; - regulator-enable-ramp-delay = <233>; - gpio = <&tlmm 61 0>; - enable-active-high; - regulator-boot-on; - pinctrl-names = "default"; - pinctrl-0 = <&display_panel_avdd_default>; - }; - -}; - -&adsp { - status = "okay"; - firmware-name = "qcom/sm8250/adsp.mbn"; -}; - -&apps_rsc { - pm8150-rpmh-regulators { - compatible = "qcom,pm8150-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; - vdd-l2-l10-supply = <&vreg_bob>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; - vdd-l6-l9-supply = <&vreg_s8c_1p3>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; - vdd-l13-l16-l17-supply = <&vreg_bob>; - - vreg_s5a_1p9: smps5 { - regulator-name = "vreg_s5a_1p9"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - vreg_s6a_0p95: smps6 { - regulator-name = "vreg_s6a_0p95"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - regulator-initial-mode = ; - }; - - vreg_l2a_3p1: ldo2 { - regulator-name = "vreg_l2a_3p1"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p9: ldo3 { - regulator-name = "vreg_l3a_0p9"; - regulator-min-microvolt = <928000>; - regulator-max-microvolt = <932000>; - regulator-initial-mode = ; - }; - - vreg_l5a_0p875: ldo5 { - regulator-name = "vreg_l5a_0p875"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l6a_1p2: ldo6 { - regulator-name = "vreg_l6a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p7: ldo7 { - regulator-name = "vreg_l7a_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l9a_1p2: ldo9 { - regulator-name = "vreg_l9a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l10a_1p8: ldo10 { - regulator-name = "vreg_l10a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l12a_1p8: ldo12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_ts_3p0: ldo13 { - regulator-name = "vreg_l13a_ts_3p0"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l14a_1p8: ldo14 { - regulator-name = "vreg_l14a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1880000>; - regulator-initial-mode = ; - }; - - vreg_l15a_11ad_io_1p8: ldo15 { - regulator-name = "vreg_l15a_11ad_io_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_3p0: ldo17 { - regulator-name = "vreg_l17a_3p0"; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l18a_0p9: ldo18 { - regulator-name = "vreg_l18a_0p9"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - }; - }; - - pm8150l-rpmh-regulators { - compatible = "qcom,pm8150l-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-l1-l8-supply = <&vreg_s4a_1p8>; - vdd-l2-l3-supply = <&vreg_s8c_1p3>; - vdd-l4-l5-l6-supply = <&vreg_bob>; - vdd-l7-l11-supply = <&vreg_bob>; - vdd-l9-l10-supply = <&vreg_bob>; - vdd-bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-name = "vreg_bob"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <4000000>; - regulator-initial-mode = ; - }; - - vreg_s8c_1p3: smps8 { - regulator-name = "vreg_s8c_1p3"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - regulator-initial-mode = ; - }; - - vreg_l1c_1p8: ldo1 { - regulator-name = "vreg_l1c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p2: ldo2 { - regulator-name = "vreg_l2c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l3c_0p92: ldo3 { - regulator-name = "vreg_l3c_0p92"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l4c_1p7: ldo4 { - regulator-name = "vreg_l4c_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p8: ldo5 { - regulator-name = "vreg_l5c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l6c_2p9: ldo6 { - regulator-name = "vreg_l6c_2p9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l7c_cam_vcm0_2p85: ldo7 { - regulator-name = "vreg_l7c_cam_vcm0_2p85"; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3104000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p8: ldo8 { - regulator-name = "vreg_l8c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l9c_2p9: ldo9 { - regulator-name = "vreg_l9c_2p9"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l10c_3p0: ldo10 { - regulator-name = "vreg_l10c_3p0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = ; - }; - - vreg_l11c_3p3: ldo11 { - regulator-name = "vreg_l11c_3p3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - }; - - pm8009-rpmh-regulators { - compatible = "qcom,pm8009-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vreg_bob>; - vdd-l2-supply = <&vreg_s8c_1p3>; - vdd-l5-l6-supply = <&vreg_bob>; - vdd-l7-supply = <&vreg_s4a_1p8>; - - vreg_l1f_cam_dvdd1_1p1: ldo1 { - regulator-name = "vreg_l1f_cam_dvdd1_1p1"; - regulator-min-microvolt = <1104000>; - regulator-max-microvolt = <1104000>; - regulator-initial-mode = ; - }; - - vreg_l2f_cam_dvdd0_1p2: ldo2 { - regulator-name = "vreg_l2f_cam_dvdd0_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l3f_cam_dvdd2_1p05: ldo3 { - regulator-name = "vreg_l3f_cam_dvdd2_1p05"; - regulator-min-microvolt = <1056000>; - regulator-max-microvolt = <1056000>; - regulator-initial-mode = ; - }; - - vreg_l5f_cam_avdd0_2p85: ldo5 { - regulator-name = "vreg_l5f_cam_avdd0_2p85"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = ; - }; - - vreg_l6f_cam_avdd1_2p85: ldo6 { - regulator-name = "vreg_l6f_cam_avdd1_2p85"; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <2856000>; - regulator-initial-mode = ; - }; - - vreg_l7f_1p8: ldo7 { - regulator-name = "vreg_l7f_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; -}; - -&cdsp { - status = "okay"; - firmware-name = "qcom/sm8250/cdsp.mbn"; -}; - -&dsi0 { - status = "okay"; - vdda-supply = <&vreg_l9a_1p2>; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - port@1 { - endpoint { - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l5a_0p875>; -}; - -#if 0 -&dsi1 { - status = "okay"; - vdda-supply = <&vreg_l9a_1p2>; - - ports { - port@1 { - endpoint { - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi1_phy { - status = "okay"; - vdds-supply = <&vreg_l5a_0p875>; -}; -#endif - -&gmu { - status = "okay"; -}; - -&gpu { - status = "okay"; - - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sm8250/a650_zap.mbn"; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <1000000>; - - /* NQ NFC chip @28 */ -}; - -&i2c13 { - status = "okay"; - - /* st,stmfts @ 49 */ -}; - -&i2c15 { - status = "okay"; - - /* smb1390 @ 10 */ - /* rtc6226 @ 64 */ -}; - -&mdss { - status = "okay"; -}; - -&mdss_mdp { - status = "okay"; -}; - -&pm8150_adc { - xo-therm@4c { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; - - skin-therm@4d { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; - - pa-therm1@4e { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; -}; - -&pm8150_adc_tm { - status = "okay"; - - xo-therm@0 { - reg = <0>; - io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; - - skin-therm@1 { - reg = <1>; - io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; - - pa-therm1@2 { - reg = <2>; - io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; -}; - -&pm8150b_adc { - conn-therm@4f { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; -}; - -&pm8150b_adc_tm { - status = "okay"; - - conn-therm@0 { - reg = <0>; - io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; -}; - -&pm8150l_adc_tm { - status = "okay"; - - camera-flash-therm@0 { - reg = <0>; - io-channels = <&pm8150l_adc ADC5_AMUX_THM1_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; - - skin-msm-therm@1 { - reg = <1>; - io-channels = <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; - - pa-therm2@2 { - reg = <2>; - io-channels = <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>; - qcom,ratiometric; - qcom,hw-settle-time-us = <200>; - }; -}; - -&pm8150l_adc { - camera-flash-therm@4d { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; - - skin-msm-therm@4e { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; - - pa-therm2@4f { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&qupv3_id_2 { - status = "okay"; -}; - -&slpi { - status = "okay"; - firmware-name = "qcom/sm8250/slpi.mbn"; -}; - -&soc { - wcd938x: codec { - compatible = "qcom,wcd9380-codec"; - #sound-dai-cells = <1>; - reset-gpios = <&tlmm 32 0>; - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-rxtx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; - vdd-mic-bias-supply = <&vreg_bob>; - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; - qcom,mbhc-headset-vthreshold-microvolt = <1700000>; - qcom,mbhc-headphone-vthreshold-microvolt = <50000>; - qcom,rx-device = <&wcd_rx>; - qcom,tx-device = <&wcd_tx>; - }; -}; - -&sound { - compatible = "qcom,sm8250-sndcard"; - model = "SM8250-MTP-WCD9380-WSA8810-VA-DMIC"; - audio-routing = - "SpkrLeft IN", "WSA_SPK1 OUT", - "SpkrRight IN", "WSA_SPK2 OUT", - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "AMIC1", "MIC BIAS1", - "AMIC2", "MIC BIAS2", - "AMIC3", "MIC BIAS3", - "AMIC4", "MIC BIAS3", - "AMIC5", "MIC BIAS4", - "TX SWR_ADC0", "ADC1_OUTPUT", - "TX SWR_ADC1", "ADC2_OUTPUT", - "TX SWR_ADC2", "ADC3_OUTPUT", - "TX SWR_ADC3", "ADC4_OUTPUT", - "TX SWR_DMIC0", "DMIC1_OUTPUT", - "TX SWR_DMIC1", "DMIC2_OUTPUT", - "TX SWR_DMIC2", "DMIC3_OUTPUT", - "TX SWR_DMIC3", "DMIC4_OUTPUT", - "TX SWR_DMIC4", "DMIC5_OUTPUT", - "TX SWR_DMIC5", "DMIC6_OUTPUT", - "TX SWR_DMIC6", "DMIC7_OUTPUT", - "TX SWR_DMIC7", "DMIC8_OUTPUT"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - mm2-dai-link { - link-name = "MultiMedia2"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; - }; - }; - - mm3-dai-link { - link-name = "MultiMedia3"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; - }; - }; - - wcd-playback-dai-link { - link-name = "WCD Playback"; - cpu { - sound-dai = <&q6afedai RX_CODEC_DMA_RX_0>; - }; - codec { - sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; - }; - platform { - sound-dai = <&q6routing>; - }; - }; - - wcd-capture-dai-link { - link-name = "WCD Capture"; - cpu { - sound-dai = <&q6afedai TX_CODEC_DMA_TX_3>; - }; - - codec { - sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>; - }; - platform { - sound-dai = <&q6routing>; - }; - }; - - wsa-dai-link { - link-name = "WSA Playback"; - cpu { - sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>; - }; - - codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; - }; - platform { - sound-dai = <&q6routing>; - }; - }; - - va-dai-link { - link-name = "VA Capture"; - cpu { - sound-dai = <&q6afedai VA_CODEC_DMA_TX_0>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&vamacro 0>; - }; - }; -}; - -&swr0 { - left_spkr: wsa8810-right@0,3{ - compatible = "sdw10217211000"; - reg = <0 3>; - powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrLeft"; - #sound-dai-cells = <0>; - }; - - right_spkr: wsa8810-left@0,4{ - compatible = "sdw10217211000"; - reg = <0 4>; - powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrRight"; - #sound-dai-cells = <0>; - }; -}; - -&swr1 { - wcd_rx: wcd9380-rx@0,4 { - compatible = "sdw20217010d00"; - reg = <0 4>; - qcom,rx-port-mapping = <1 2 3 4 5>; - }; -}; - -&swr2 { - wcd_tx: wcd9380-tx@0,3 { - compatible = "sdw20217010d00"; - reg = <0 3>; - qcom,tx-port-mapping = <2 3 4 5>; - }; -}; - -&tlmm { - gpio-reserved-ranges = <28 4>, <40 4>; - -<<<<<<< - display_panel_avdd_default: display_panel_avdd_default { - mux { - pins = "gpio61"; - function = "gpio"; - }; - - config { - pins = "gpio61"; - drive-strength = <8>; - bias-disable = <0>; - output-high; - }; - }; - -======= - wcd938x_reset_default: wcd938x_reset_default { - mux { - pins = "gpio32"; - function = "gpio"; - }; - - config { - pins = "gpio32"; - drive-strength = <16>; - output-high; - }; - }; - - wcd938x_reset_sleep: wcd938x_reset_sleep { - mux { - pins = "gpio32"; - function = "gpio"; - }; - - config { - pins = "gpio32"; - drive-strength = <16>; - bias-disable; - output-low; - }; - }; ->>>>>>> -}; - -&uart12 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - vcc-supply = <&vreg_l17a_3p0>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l6a_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l5a_0p875>; - vdda-pll-supply = <&vreg_l9a_1p2>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdda-pll-supply = <&vreg_l5a_0p875>; - vdda18-supply = <&vreg_l12a_1p8>; - vdda33-supply = <&vreg_l2a_3p1>; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdda-pll-supply = <&vreg_l5a_0p875>; - vdda18-supply = <&vreg_l12a_1p8>; - vdda33-supply = <&vreg_l2a_3p1>; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; -}; - -&swr0 { - left_right: wsa8810-right{ - compatible = "sdw10217211000"; - reg = <0 2>; - powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrRight"; - #sound-dai-cells = <0>; - }; - - left_spkr: wsa8810-left{ - compatible = "sdw10217211000"; - reg = <0 1>; - powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrLeft"; - #sound-dai-cells = <0>; - }; -}; - -&q6asmdai { - dai@0 { - reg = <0>; - direction = <2>; - }; -}; - -&sound { - compatible = "qcom,sm8250-sndcard"; - model = "SM8250"; - audio-routing = - "SpkrLeft IN", "WSA_SPK1 OUT", - "MM_DL1", "MultiMedia1 Playback"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - dma-dai-link { - link-name = "WSA Playback"; - cpu { - sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&left_spkr>, <&swr0 0>, <&wsamacro 0>; - }; - }; -}; - -&venus { - status = "okay"; -}; diff --git a/rr-cache/ec20b6c125b93d3eb71618b531b7abe1063b5669/preimage b/rr-cache/ec20b6c125b93d3eb71618b531b7abe1063b5669/preimage deleted file mode 100644 index 42914c8..0000000 --- a/rr-cache/ec20b6c125b93d3eb71618b531b7abe1063b5669/preimage +++ /dev/null @@ -1,644 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Network device configuration -# - -menuconfig NETDEVICES - default y if UML - depends on NET - bool "Network device support" - help - You can say N here if you don't intend to connect your Linux box to - any other computer at all. - - You'll have to say Y if your computer contains a network card that - you want to use under Linux. If you are going to run SLIP or PPP over - telephone line or null modem cable you need say Y here. Connecting - two machines with parallel ports using PLIP needs this, as well as - AX.25/KISS for sending Internet traffic over amateur radio links. - - See also "The Linux Network Administrator's Guide" by Olaf Kirch and - Terry Dawson. Available at . - - If unsure, say Y. - -# All the following symbols are dependent on NETDEVICES - do not repeat -# that for each of the symbols. -if NETDEVICES - -config MII - tristate - -config NET_CORE - default y - bool "Network core driver support" - help - You can say N here if you do not intend to use any of the - networking core drivers (i.e. VLAN, bridging, bonding, etc.) - -if NET_CORE - -config BONDING - tristate "Bonding driver support" - depends on INET - depends on IPV6 || IPV6=n - depends on TLS || TLS_DEVICE=n - help - Say 'Y' or 'M' if you wish to be able to 'bond' multiple Ethernet - Channels together. This is called 'Etherchannel' by Cisco, - 'Trunking' by Sun, 802.3ad by the IEEE, and 'Bonding' in Linux. - - The driver supports multiple bonding modes to allow for both high - performance and high availability operation. - - Refer to for more - information. - - To compile this driver as a module, choose M here: the module - will be called bonding. - -config DUMMY - tristate "Dummy net driver support" - help - This is essentially a bit-bucket device (i.e. traffic you send to - this device is consigned into oblivion) with a configurable IP - address. It is most commonly used in order to make your currently - inactive SLIP address seem like a real address for local programs. - If you use SLIP or PPP, you might want to say Y here. It won't - enlarge your kernel. What a deal. Read about it in the Network - Administrator's Guide, available from - . - - To compile this driver as a module, choose M here: the module - will be called dummy. - -config WIREGUARD - tristate "WireGuard secure network tunnel" - depends on NET && INET - depends on IPV6 || !IPV6 - select NET_UDP_TUNNEL - select DST_CACHE - select CRYPTO - select CRYPTO_LIB_CURVE25519 - select CRYPTO_LIB_CHACHA20POLY1305 - select CRYPTO_CHACHA20_X86_64 if X86 && 64BIT - select CRYPTO_POLY1305_X86_64 if X86 && 64BIT - select CRYPTO_BLAKE2S_X86 if X86 && 64BIT - select CRYPTO_CURVE25519_X86 if X86 && 64BIT - select ARM_CRYPTO if ARM - select ARM64_CRYPTO if ARM64 - select CRYPTO_CHACHA20_NEON if ARM || (ARM64 && KERNEL_MODE_NEON) - select CRYPTO_POLY1305_NEON if ARM64 && KERNEL_MODE_NEON - select CRYPTO_POLY1305_ARM if ARM - select CRYPTO_BLAKE2S_ARM if ARM - select CRYPTO_CURVE25519_NEON if ARM && KERNEL_MODE_NEON - select CRYPTO_CHACHA_MIPS if CPU_MIPS32_R2 - select CRYPTO_POLY1305_MIPS if MIPS - help - WireGuard is a secure, fast, and easy to use replacement for IPSec - that uses modern cryptography and clever networking tricks. It's - designed to be fairly general purpose and abstract enough to fit most - use cases, while at the same time remaining extremely simple to - configure. See www.wireguard.com for more info. - - It's safe to say Y or M here, as the driver is very lightweight and - is only in use when an administrator chooses to add an interface. - -config WIREGUARD_DEBUG - bool "Debugging checks and verbose messages" - depends on WIREGUARD - help - This will write log messages for handshake and other events - that occur for a WireGuard interface. It will also perform some - extra validation checks and unit tests at various points. This is - only useful for debugging. - - Say N here unless you know what you're doing. - -config EQUALIZER - tristate "EQL (serial line load balancing) support" - help - If you have two serial connections to some other computer (this - usually requires two modems and two telephone lines) and you use - SLIP (the protocol for sending Internet traffic over telephone - lines) or PPP (a better SLIP) on them, you can make them behave like - one double speed connection using this driver. Naturally, this has - to be supported at the other end as well, either with a similar EQL - Linux driver or with a Livingston Portmaster 2e. - - Say Y if you want this and read - . You may also want to read - section 6.2 of the NET-3-HOWTO, available from - . - - To compile this driver as a module, choose M here: the module - will be called eql. If unsure, say N. - -config NET_FC - bool "Fibre Channel driver support" - depends on SCSI && PCI - help - Fibre Channel is a high speed serial protocol mainly used to connect - large storage devices to the computer; it is compatible with and - intended to replace SCSI. - - If you intend to use Fibre Channel, you need to have a Fibre channel - adaptor card in your computer; say Y here and to the driver for your - adaptor below. You also should have said Y to "SCSI support" and - "SCSI generic support". - -config IFB - tristate "Intermediate Functional Block support" - depends on NET_ACT_MIRRED || NFT_FWD_NETDEV - select NET_REDIRECT - help - This is an intermediate driver that allows sharing of - resources. - To compile this driver as a module, choose M here: the module - will be called ifb. If you want to use more than one ifb - device at a time, you need to compile this driver as a module. - Instead of 'ifb', the devices will then be called 'ifb0', - 'ifb1' etc. - Look at the iproute2 documentation directory for usage etc - -source "drivers/net/team/Kconfig" - -config MACVLAN - tristate "MAC-VLAN support" - help - This allows one to create virtual interfaces that map packets to - or from specific MAC addresses to a particular interface. - - Macvlan devices can be added using the "ip" command from the - iproute2 package starting with the iproute2-2.6.23 release: - - "ip link add link [ address MAC ] [ NAME ] type macvlan" - - To compile this driver as a module, choose M here: the module - will be called macvlan. - -config MACVTAP - tristate "MAC-VLAN based tap driver" - depends on MACVLAN - depends on INET - select TAP - help - This adds a specialized tap character device driver that is based - on the MAC-VLAN network interface, called macvtap. A macvtap device - can be added in the same way as a macvlan device, using 'type - macvtap', and then be accessed through the tap user space interface. - - To compile this driver as a module, choose M here: the module - will be called macvtap. - -config IPVLAN_L3S - depends on NETFILTER - depends on IPVLAN - def_bool y - select NET_L3_MASTER_DEV - -config IPVLAN - tristate "IP-VLAN support" - depends on INET - depends on IPV6 || !IPV6 - help - This allows one to create virtual devices off of a main interface - and packets will be delivered based on the dest L3 (IPv6/IPv4 addr) - on packets. All interfaces (including the main interface) share L2 - making it transparent to the connected L2 switch. - - Ipvlan devices can be added using the "ip" command from the - iproute2 package starting with the iproute2-3.19 release: - - "ip link add link [ NAME ] type ipvlan" - - To compile this driver as a module, choose M here: the module - will be called ipvlan. - -config IPVTAP - tristate "IP-VLAN based tap driver" - depends on IPVLAN - depends on INET - select TAP - help - This adds a specialized tap character device driver that is based - on the IP-VLAN network interface, called ipvtap. An ipvtap device - can be added in the same way as a ipvlan device, using 'type - ipvtap', and then be accessed through the tap user space interface. - - To compile this driver as a module, choose M here: the module - will be called ipvtap. - -config VXLAN - tristate "Virtual eXtensible Local Area Network (VXLAN)" - depends on INET - select NET_UDP_TUNNEL - select GRO_CELLS - help - This allows one to create vxlan virtual interfaces that provide - Layer 2 Networks over Layer 3 Networks. VXLAN is often used - to tunnel virtual network infrastructure in virtualized environments. - For more information see: - http://tools.ietf.org/html/draft-mahalingam-dutt-dcops-vxlan-02 - - To compile this driver as a module, choose M here: the module - will be called vxlan. - -config GENEVE - tristate "Generic Network Virtualization Encapsulation" - depends on INET - depends on IPV6 || !IPV6 - select NET_UDP_TUNNEL - select GRO_CELLS - help - This allows one to create geneve virtual interfaces that provide - Layer 2 Networks over Layer 3 Networks. GENEVE is often used - to tunnel virtual network infrastructure in virtualized environments. - For more information see: - http://tools.ietf.org/html/draft-gross-geneve-02 - - To compile this driver as a module, choose M here: the module - will be called geneve. - -config BAREUDP - tristate "Bare UDP Encapsulation" - depends on INET - depends on IPV6 || !IPV6 - select NET_UDP_TUNNEL - select GRO_CELLS - help - This adds a bare UDP tunnel module for tunnelling different - kinds of traffic like MPLS, IP, etc. inside a UDP tunnel. - - To compile this driver as a module, choose M here: the module - will be called bareudp. - -config GTP - tristate "GPRS Tunneling Protocol datapath (GTP-U)" - depends on INET - select NET_UDP_TUNNEL - help - This allows one to create gtp virtual interfaces that provide - the GPRS Tunneling Protocol datapath (GTP-U). This tunneling protocol - is used to prevent subscribers from accessing mobile carrier core - network infrastructure. This driver requires a userspace software that - implements the signaling protocol (GTP-C) to update its PDP context - base, such as OpenGGSN for details. - -config NETCONSOLE_DYNAMIC - bool "Dynamic reconfiguration of logging targets" - depends on NETCONSOLE && SYSFS && CONFIGFS_FS && \ - !(NETCONSOLE=y && CONFIGFS_FS=m) - help - This option enables the ability to dynamically reconfigure target - parameters (interface, IP addresses, port numbers, MAC addresses) - at runtime through a userspace interface exported using configfs. - See for details. - -config NETPOLL - def_bool NETCONSOLE - select SRCU - -config NET_POLL_CONTROLLER - def_bool NETPOLL - -config NTB_NETDEV - tristate "Virtual Ethernet over NTB Transport" - depends on NTB_TRANSPORT - -config RIONET - tristate "RapidIO Ethernet over messaging driver support" - depends on RAPIDIO - -config RIONET_TX_SIZE - int "Number of outbound queue entries" - depends on RIONET - default "128" - -config RIONET_RX_SIZE - int "Number of inbound queue entries" - depends on RIONET - default "128" - -config TUN - tristate "Universal TUN/TAP device driver support" - depends on INET - select CRC32 - help - TUN/TAP provides packet reception and transmission for user space - programs. It can be viewed as a simple Point-to-Point or Ethernet - device, which instead of receiving packets from a physical media, - receives them from user space program and instead of sending packets - via physical media writes them to the user space program. - - When a program opens /dev/net/tun, driver creates and registers - corresponding net device tunX or tapX. After a program closed above - devices, driver will automatically delete tunXX or tapXX device and - all routes corresponding to it. - - Please read for more - information. - - To compile this driver as a module, choose M here: the module - will be called tun. - - If you don't know what to use this for, you don't need it. - -config TAP - tristate - help - This option is selected by any driver implementing tap user space - interface for a virtual interface to re-use core tap functionality. - -config TUN_VNET_CROSS_LE - bool "Support for cross-endian vnet headers on little-endian kernels" - default n - help - This option allows TUN/TAP and MACVTAP device drivers in a - little-endian kernel to parse vnet headers that come from a - big-endian legacy virtio device. - - Userspace programs can control the feature using the TUNSETVNETBE - and TUNGETVNETBE ioctls. - - Unless you have a little-endian system hosting a big-endian virtual - machine with a legacy virtio NIC, you should say N. - -config VETH - tristate "Virtual ethernet pair device" - help - This device is a local ethernet tunnel. Devices are created in pairs. - When one end receives the packet it appears on its pair and vice - versa. - -config VIRTIO_NET - tristate "Virtio network driver" - depends on VIRTIO - select NET_FAILOVER - help - This is the virtual network driver for virtio. It can be used with - QEMU based VMMs (like KVM or Xen). Say Y or M. - -config NLMON - tristate "Virtual netlink monitoring device" - help - This option enables a monitoring net device for netlink skbs. The - purpose of this is to analyze netlink messages with packet sockets. - Thus applications like tcpdump will be able to see local netlink - messages if they tap into the netlink device, record pcaps for further - diagnostics, etc. This is mostly intended for developers or support - to debug netlink issues. If unsure, say N. - -config NET_VRF - tristate "Virtual Routing and Forwarding (Lite)" - depends on IP_MULTIPLE_TABLES - depends on NET_L3_MASTER_DEV - depends on IPV6 || IPV6=n - depends on IPV6_MULTIPLE_TABLES || IPV6=n - help - This option enables the support for mapping interfaces into VRF's. The - support enables VRF devices. - -config VSOCKMON - tristate "Virtual vsock monitoring device" - depends on VHOST_VSOCK - help - This option enables a monitoring net device for vsock sockets. It is - mostly intended for developers or support to debug vsock issues. If - unsure, say N. - -config MHI_NET - tristate "MHI network driver" - depends on MHI_BUS - help - This is the network driver for MHI bus. It can be used with - QCOM based WWAN modems for IP or QMAP/rmnet protocol (like SDX55). - Say Y or M. - -config MHI_EP_NET - tristate "MHI Endpoint network driver" - depends on MHI_BUS_EP - help -<<<<<<< - This is the network driver for MHI Endpoint bus providing network - interface to QCOM modems such as SDX55. -======= - This is the network driver for MHI bus implementation in endpoint - devices. It is used provide the network interface for QCOM modems - such as SDX55. ->>>>>>> - Say Y or M. - -endif # NET_CORE - -config SUNGEM_PHY - tristate - -source "drivers/net/arcnet/Kconfig" - -source "drivers/atm/Kconfig" - -source "drivers/net/caif/Kconfig" - -source "drivers/net/dsa/Kconfig" - -source "drivers/net/ethernet/Kconfig" - -source "drivers/net/fddi/Kconfig" - -source "drivers/net/hippi/Kconfig" - -source "drivers/net/ipa/Kconfig" - -config NET_SB1000 - tristate "General Instruments Surfboard 1000" - depends on PNP - help - This is a driver for the General Instrument (also known as - NextLevel) SURFboard 1000 internal - cable modem. This is an ISA card which is used by a number of cable - TV companies to provide cable modem access. It's a one-way - downstream-only cable modem, meaning that your upstream net link is - provided by your regular phone modem. - - At present this driver only compiles as a module, so say M here if - you have this card. The module will be called sb1000. Then read - for - information on how to use this module, as it needs special ppp - scripts for establishing a connection. Further documentation - and the necessary scripts can be found at: - - - - - - If you don't have this card, of course say N. - -source "drivers/net/phy/Kconfig" - -source "drivers/net/mctp/Kconfig" - -source "drivers/net/mdio/Kconfig" - -source "drivers/net/pcs/Kconfig" - -source "drivers/net/plip/Kconfig" - -source "drivers/net/ppp/Kconfig" - -source "drivers/net/slip/Kconfig" - -source "drivers/s390/net/Kconfig" - -source "drivers/net/usb/Kconfig" - -source "drivers/net/wireless/Kconfig" - -source "drivers/net/wan/Kconfig" - -source "drivers/net/ieee802154/Kconfig" - -source "drivers/net/wwan/Kconfig" - -config XEN_NETDEV_FRONTEND - tristate "Xen network device frontend driver" - depends on XEN - select XEN_XENBUS_FRONTEND - select PAGE_POOL - default y - help - This driver provides support for Xen paravirtual network - devices exported by a Xen network driver domain (often - domain 0). - - The corresponding Linux backend driver is enabled by the - CONFIG_XEN_NETDEV_BACKEND option. - - If you are compiling a kernel for use as Xen guest, you - should say Y here. To compile this driver as a module, chose - M here: the module will be called xen-netfront. - -config XEN_NETDEV_BACKEND - tristate "Xen backend network device" - depends on XEN_BACKEND - help - This driver allows the kernel to act as a Xen network driver - domain which exports paravirtual network devices to other - Xen domains. These devices can be accessed by any operating - system that implements a compatible front end. - - The corresponding Linux frontend driver is enabled by the - CONFIG_XEN_NETDEV_FRONTEND configuration option. - - The backend driver presents a standard network device - endpoint for each paravirtual network device to the driver - domain network stack. These can then be bridged or routed - etc in order to provide full network connectivity. - - If you are compiling a kernel to run in a Xen network driver - domain (often this is domain 0) you should say Y here. To - compile this driver as a module, chose M here: the module - will be called xen-netback. - -config VMXNET3 - tristate "VMware VMXNET3 ethernet driver" - depends on PCI && INET - depends on PAGE_SIZE_LESS_THAN_64KB - help - This driver supports VMware's vmxnet3 virtual ethernet NIC. - To compile this driver as a module, choose M here: the - module will be called vmxnet3. - -config FUJITSU_ES - tristate "FUJITSU Extended Socket Network Device driver" - depends on ACPI - help - This driver provides support for Extended Socket network device - on Extended Partitioning of FUJITSU PRIMEQUEST 2000 E2 series. - -config USB4_NET - tristate "Networking over USB4 and Thunderbolt cables" - depends on USB4 && INET - help - Select this if you want to create network between two computers - over a USB4 and Thunderbolt cables. The driver supports Apple - ThunderboltIP protocol and allows communication with any host - supporting the same protocol including Windows and macOS. - - To compile this driver a module, choose M here. The module will be - called thunderbolt-net. - -source "drivers/net/hyperv/Kconfig" - -config NETDEVSIM - tristate "Simulated networking device" - depends on DEBUG_FS - depends on INET - depends on IPV6 || IPV6=n - depends on PSAMPLE || PSAMPLE=n - select NET_DEVLINK - help - This driver is a developer testing tool and software model that can - be used to test various control path networking APIs, especially - HW-offload related. - - To compile this driver as a module, choose M here: the module - will be called netdevsim. - -config NET_FAILOVER - tristate "Failover driver" - select FAILOVER - help - This provides an automated failover mechanism via APIs to create - and destroy a failover master netdev and manages a primary and - standby slave netdevs that get registered via the generic failover - infrastructure. This can be used by paravirtual drivers to enable - an alternate low latency datapath. It also enables live migration of - a VM with direct attached VF by failing over to the paravirtual - datapath when the VF is unplugged. - -config NETDEV_LEGACY_INIT - bool - depends on ISA - help - Drivers that call netdev_boot_setup_check() should select this - symbol, everything else no longer needs it. - -endif # NETDEVICES diff --git a/rr-cache/f285fdfe5adcadf77d60a81471e87da51069de06/preimage.1 b/rr-cache/f285fdfe5adcadf77d60a81471e87da51069de06/preimage.1 deleted file mode 100644 index 14868da..0000000 --- a/rr-cache/f285fdfe5adcadf77d60a81471e87da51069de06/preimage.1 +++ /dev/null @@ -1,1074 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Copyright (c) 2019-2020. Linaro Limited. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -#define EDID_BLOCK_SIZE 128 -#define EDID_NUM_BLOCKS 2 - -struct lt9611uxc { - struct device *dev; - struct drm_bridge bridge; - struct drm_connector connector; - - struct regmap *regmap; - /* Protects all accesses to registers by stopping the on-chip MCU */ - struct mutex ocm_lock; - - struct wait_queue_head wq; - struct work_struct work; - - struct device_node *dsi0_node; - struct device_node *dsi1_node; - struct mipi_dsi_device *dsi0; - struct mipi_dsi_device *dsi1; - struct platform_device *audio_pdev; - - struct gpio_desc *reset_gpio; - struct gpio_desc *enable_gpio; - - struct regulator_bulk_data supplies[2]; - - struct i2c_client *client; - - bool hpd_supported; - bool edid_read; - /* can be accessed from different threads, so protect this with ocm_lock */ - bool hdmi_connected; - uint8_t fw_version; -}; - -#define LT9611_PAGE_CONTROL 0xff - -static const struct regmap_range_cfg lt9611uxc_ranges[] = { - { - .name = "register_range", - .range_min = 0, - .range_max = 0xd0ff, - .selector_reg = LT9611_PAGE_CONTROL, - .selector_mask = 0xff, - .selector_shift = 0, - .window_start = 0, - .window_len = 0x100, - }, -}; - -static const struct regmap_config lt9611uxc_regmap_config = { - .reg_bits = 8, - .val_bits = 8, - .max_register = 0xffff, - .ranges = lt9611uxc_ranges, - .num_ranges = ARRAY_SIZE(lt9611uxc_ranges), -}; - -struct lt9611uxc_mode { - u16 hdisplay; - u16 vdisplay; - u8 vrefresh; - bool dual_dsi; -}; - -/* - * This chip supports only a fixed set of modes. - * Enumerate them here to check whether the mode is supported. - */ -static struct lt9611uxc_mode lt9611uxc_modes[] = { - { 3840, 2160, 60, true }, - { 3840, 2160, 30, true }, - { 1920, 1080, 60, false }, - { 1920, 1080, 30, false }, - { 1920, 1080, 25, false }, - { 1366, 768, 60, false }, - { 1360, 768, 60, false }, - { 1280, 1024, 60, false }, - { 1280, 800, 60, false }, - { 1280, 720, 60, false }, - { 1280, 720, 50, false }, - { 1280, 720, 30, false }, - { 1152, 864, 60, false }, - { 1024, 768, 60, false }, - { 800, 600, 60, false }, - { 720, 576, 50, false }, - { 720, 480, 60, false }, - { 640, 480, 60, false }, -}; - -static struct lt9611uxc *bridge_to_lt9611uxc(struct drm_bridge *bridge) -{ - return container_of(bridge, struct lt9611uxc, bridge); -} - -static struct lt9611uxc *connector_to_lt9611uxc(struct drm_connector *connector) -{ - return container_of(connector, struct lt9611uxc, connector); -} - -static void lt9611uxc_lock(struct lt9611uxc *lt9611uxc) -{ - mutex_lock(<9611uxc->ocm_lock); - regmap_write(lt9611uxc->regmap, 0x80ee, 0x01); -} - -static void lt9611uxc_unlock(struct lt9611uxc *lt9611uxc) -{ - regmap_write(lt9611uxc->regmap, 0x80ee, 0x00); - msleep(50); - mutex_unlock(<9611uxc->ocm_lock); -} - -static irqreturn_t lt9611uxc_irq_thread_handler(int irq, void *dev_id) -{ - struct lt9611uxc *lt9611uxc = dev_id; - unsigned int irq_status = 0; - unsigned int hpd_status = 0; - - lt9611uxc_lock(lt9611uxc); - - regmap_read(lt9611uxc->regmap, 0xb022, &irq_status); - regmap_read(lt9611uxc->regmap, 0xb023, &hpd_status); - if (irq_status) - regmap_write(lt9611uxc->regmap, 0xb022, 0); - - if (irq_status & BIT(0)) { - lt9611uxc->edid_read = !!(hpd_status & BIT(0)); - wake_up_all(<9611uxc->wq); - } - - if (irq_status & BIT(1)) { - lt9611uxc->hdmi_connected = hpd_status & BIT(1); - schedule_work(<9611uxc->work); - } - - lt9611uxc_unlock(lt9611uxc); - - return IRQ_HANDLED; -} - -static void lt9611uxc_hpd_work(struct work_struct *work) -{ - struct lt9611uxc *lt9611uxc = container_of(work, struct lt9611uxc, work); - bool connected; - - if (lt9611uxc->connector.dev) { - if (lt9611uxc->connector.dev->mode_config.funcs) - drm_kms_helper_hotplug_event(lt9611uxc->connector.dev); - } else { - - mutex_lock(<9611uxc->ocm_lock); - connected = lt9611uxc->hdmi_connected; - mutex_unlock(<9611uxc->ocm_lock); - - drm_bridge_hpd_notify(<9611uxc->bridge, - connected ? - connector_status_connected : - connector_status_disconnected); - } -} - -static void lt9611uxc_reset(struct lt9611uxc *lt9611uxc) -{ - gpiod_set_value_cansleep(lt9611uxc->reset_gpio, 1); - msleep(20); - - gpiod_set_value_cansleep(lt9611uxc->reset_gpio, 0); - msleep(20); - - gpiod_set_value_cansleep(lt9611uxc->reset_gpio, 1); - msleep(300); -} - -static void lt9611uxc_assert_5v(struct lt9611uxc *lt9611uxc) -{ - if (!lt9611uxc->enable_gpio) - return; - - gpiod_set_value_cansleep(lt9611uxc->enable_gpio, 1); - msleep(20); -} - -static int lt9611uxc_regulator_init(struct lt9611uxc *lt9611uxc) -{ - int ret; - - lt9611uxc->supplies[0].supply = "vdd"; - lt9611uxc->supplies[1].supply = "vcc"; - - ret = devm_regulator_bulk_get(lt9611uxc->dev, 2, lt9611uxc->supplies); - if (ret < 0) - return ret; - - return regulator_set_load(lt9611uxc->supplies[0].consumer, 200000); -} - -static int lt9611uxc_regulator_enable(struct lt9611uxc *lt9611uxc) -{ - int ret; - - ret = regulator_enable(lt9611uxc->supplies[0].consumer); - if (ret < 0) - return ret; - - usleep_range(1000, 10000); /* 50000 according to dtsi */ - - ret = regulator_enable(lt9611uxc->supplies[1].consumer); - if (ret < 0) { - regulator_disable(lt9611uxc->supplies[0].consumer); - return ret; - } - - return 0; -} - -static struct lt9611uxc_mode *lt9611uxc_find_mode(const struct drm_display_mode *mode) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(lt9611uxc_modes); i++) { - if (lt9611uxc_modes[i].hdisplay == mode->hdisplay && - lt9611uxc_modes[i].vdisplay == mode->vdisplay && - lt9611uxc_modes[i].vrefresh == drm_mode_vrefresh(mode)) { - return <9611uxc_modes[i]; - } - } - - return NULL; -} - -static struct mipi_dsi_device *lt9611uxc_attach_dsi(struct lt9611uxc *lt9611uxc, - struct device_node *dsi_node) -{ - const struct mipi_dsi_device_info info = { "lt9611uxc", 0, NULL }; - struct mipi_dsi_device *dsi; - struct mipi_dsi_host *host; - struct device *dev = lt9611uxc->dev; - int ret; - - host = of_find_mipi_dsi_host_by_node(dsi_node); - if (!host) { - dev_err(dev, "failed to find dsi host\n"); - return ERR_PTR(-EPROBE_DEFER); - } - - dsi = devm_mipi_dsi_device_register_full(dev, host, &info); - if (IS_ERR(dsi)) { - dev_err(dev, "failed to create dsi device\n"); - return dsi; - } - - dsi->lanes = 4; - dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_VIDEO_HSE; - - ret = devm_mipi_dsi_attach(dev, dsi); - if (ret < 0) { - dev_err(dev, "failed to attach dsi to host\n"); - return ERR_PTR(ret); - } - - return dsi; -} - -static int lt9611uxc_connector_get_modes(struct drm_connector *connector) -{ - struct lt9611uxc *lt9611uxc = connector_to_lt9611uxc(connector); - unsigned int count; - struct edid *edid; - - edid = lt9611uxc->bridge.funcs->get_edid(<9611uxc->bridge, connector); - drm_connector_update_edid_property(connector, edid); - count = drm_add_edid_modes(connector, edid); - kfree(edid); - - return count; -} - -static enum drm_connector_status lt9611uxc_connector_detect(struct drm_connector *connector, - bool force) -{ - struct lt9611uxc *lt9611uxc = connector_to_lt9611uxc(connector); - - return lt9611uxc->bridge.funcs->detect(<9611uxc->bridge); -} - -static enum drm_mode_status lt9611uxc_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - struct lt9611uxc_mode *lt9611uxc_mode = lt9611uxc_find_mode(mode); - struct lt9611uxc *lt9611uxc = connector_to_lt9611uxc(connector); - - if (!lt9611uxc_mode) - return MODE_BAD; - - if (lt9611uxc_mode->dual_dsi && (!lt9611uxc->dsi0 || !lt9611uxc->dsi1)) - return MODE_BAD; - - return MODE_OK; -} - -static const struct drm_connector_helper_funcs lt9611uxc_bridge_connector_helper_funcs = { - .get_modes = lt9611uxc_connector_get_modes, - .mode_valid = lt9611uxc_connector_mode_valid, -}; - -static const struct drm_connector_funcs lt9611uxc_bridge_connector_funcs = { - .fill_modes = drm_helper_probe_single_connector_modes, - .detect = lt9611uxc_connector_detect, - .destroy = drm_connector_cleanup, - .reset = drm_atomic_helper_connector_reset, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - -static int lt9611uxc_connector_init(struct drm_bridge *bridge, struct lt9611uxc *lt9611uxc) -{ - int ret; - - if (!bridge->encoder) { - DRM_ERROR("Parent encoder object not found"); - return -ENODEV; - } - - lt9611uxc->connector.polled = DRM_CONNECTOR_POLL_HPD; - - drm_connector_helper_add(<9611uxc->connector, - <9611uxc_bridge_connector_helper_funcs); - ret = drm_connector_init(bridge->dev, <9611uxc->connector, - <9611uxc_bridge_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA); - if (ret) { - DRM_ERROR("Failed to initialize connector with drm\n"); - return ret; - } - - return drm_connector_attach_encoder(<9611uxc->connector, bridge->encoder); -} - -static int lt9611uxc_bridge_attach(struct drm_bridge *bridge, - enum drm_bridge_attach_flags flags) -{ - struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); - int ret; - - if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { - ret = lt9611uxc_connector_init(bridge, lt9611uxc); - if (ret < 0) - return ret; - } - -<<<<<<< - /* Attach primary DSI */ - if (lt9611uxc->dsi0_node) { - lt9611uxc->dsi0 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi0_node); - if (IS_ERR(lt9611uxc->dsi0)) - return PTR_ERR(lt9611uxc->dsi0); - } - - /* Attach secondary DSI, if specified */ - if (lt9611uxc->dsi1_node) { - lt9611uxc->dsi1 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi1_node); - if (IS_ERR(lt9611uxc->dsi1)) { - ret = PTR_ERR(lt9611uxc->dsi1); - goto err_unregister_dsi0; - } - } - - return 0; - -err_unregister_dsi0: - if (lt9611uxc->dsi0) { - mipi_dsi_detach(lt9611uxc->dsi0); - mipi_dsi_device_unregister(lt9611uxc->dsi0); - } - - return ret; -======= - return 0; ->>>>>>> -} - -static enum drm_mode_status -lt9611uxc_bridge_mode_valid(struct drm_bridge *bridge, - const struct drm_display_info *info, - const struct drm_display_mode *mode) -{ - struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); - struct lt9611uxc_mode *lt9611uxc_mode = lt9611uxc_find_mode(mode); - - if (!lt9611uxc_mode) - return MODE_BAD; - - if (lt9611uxc_mode->dual_dsi && (!lt9611uxc->dsi0 || !lt9611uxc->dsi1)) - return MODE_BAD; - - return MODE_OK; -} - -static void lt9611uxc_video_setup(struct lt9611uxc *lt9611uxc, - const struct drm_display_mode *mode) -{ - u32 h_total, hactive, hsync_len, hfront_porch; - u32 v_total, vactive, vsync_len, vfront_porch; - - h_total = mode->htotal; - v_total = mode->vtotal; - - hactive = mode->hdisplay; - hsync_len = mode->hsync_end - mode->hsync_start; - hfront_porch = mode->hsync_start - mode->hdisplay; - - vactive = mode->vdisplay; - vsync_len = mode->vsync_end - mode->vsync_start; - vfront_porch = mode->vsync_start - mode->vdisplay; - - if (lt9611uxc->dsi0 && lt9611uxc->dsi1) - regmap_write(lt9611uxc->regmap, 0xb025, 0x03); - else if (lt9611uxc->dsi0) - regmap_write(lt9611uxc->regmap, 0xb025, 0x01); - else - regmap_write(lt9611uxc->regmap, 0xb025, 0x02); - - regmap_write(lt9611uxc->regmap, 0xd00d, (u8)(v_total / 256)); - regmap_write(lt9611uxc->regmap, 0xd00e, (u8)(v_total % 256)); - - regmap_write(lt9611uxc->regmap, 0xd00f, (u8)(vactive / 256)); - regmap_write(lt9611uxc->regmap, 0xd010, (u8)(vactive % 256)); - - regmap_write(lt9611uxc->regmap, 0xd011, (u8)(h_total / 256)); - regmap_write(lt9611uxc->regmap, 0xd012, (u8)(h_total % 256)); - - regmap_write(lt9611uxc->regmap, 0xd013, (u8)(hactive / 256)); - regmap_write(lt9611uxc->regmap, 0xd014, (u8)(hactive % 256)); - - regmap_write(lt9611uxc->regmap, 0xd015, (u8)(vsync_len % 256)); - - regmap_update_bits(lt9611uxc->regmap, 0xd016, 0xf, (u8)(hsync_len / 256)); - regmap_write(lt9611uxc->regmap, 0xd017, (u8)(hsync_len % 256)); - - regmap_update_bits(lt9611uxc->regmap, 0xd018, 0xf, (u8)(vfront_porch / 256)); - regmap_write(lt9611uxc->regmap, 0xd019, (u8)(vfront_porch % 256)); - - regmap_update_bits(lt9611uxc->regmap, 0xd01a, 0xf, (u8)(hfront_porch / 256)); - regmap_write(lt9611uxc->regmap, 0xd01b, (u8)(hfront_porch % 256)); -} - -static void lt9611uxc_bridge_mode_set(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adj_mode) -{ - struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); - - lt9611uxc_lock(lt9611uxc); - lt9611uxc_video_setup(lt9611uxc, mode); - lt9611uxc_unlock(lt9611uxc); -} - -static enum drm_connector_status lt9611uxc_bridge_detect(struct drm_bridge *bridge) -{ - struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); - unsigned int reg_val = 0; - int ret; - bool connected = true; - - lt9611uxc_lock(lt9611uxc); - - if (lt9611uxc->hpd_supported) { - ret = regmap_read(lt9611uxc->regmap, 0xb023, ®_val); - - if (ret) - dev_err(lt9611uxc->dev, "failed to read hpd status: %d\n", ret); - else - connected = reg_val & BIT(1); - } - lt9611uxc->hdmi_connected = connected; - - lt9611uxc_unlock(lt9611uxc); - - return connected ? connector_status_connected : - connector_status_disconnected; -} - -static int lt9611uxc_wait_for_edid(struct lt9611uxc *lt9611uxc) -{ - return wait_event_interruptible_timeout(lt9611uxc->wq, lt9611uxc->edid_read, - msecs_to_jiffies(500)); -} - -static int lt9611uxc_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) -{ - struct lt9611uxc *lt9611uxc = data; - int ret; - - if (len > EDID_BLOCK_SIZE) - return -EINVAL; - - if (block >= EDID_NUM_BLOCKS) - return -EINVAL; - - lt9611uxc_lock(lt9611uxc); - - regmap_write(lt9611uxc->regmap, 0xb00b, 0x10); - - regmap_write(lt9611uxc->regmap, 0xb00a, block * EDID_BLOCK_SIZE); - - ret = regmap_noinc_read(lt9611uxc->regmap, 0xb0b0, buf, len); - if (ret) - dev_err(lt9611uxc->dev, "edid read failed: %d\n", ret); - - lt9611uxc_unlock(lt9611uxc); - - return 0; -}; - -static struct edid *lt9611uxc_bridge_get_edid(struct drm_bridge *bridge, - struct drm_connector *connector) -{ - struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); - int ret; - - ret = lt9611uxc_wait_for_edid(lt9611uxc); - if (ret < 0) { - dev_err(lt9611uxc->dev, "wait for EDID failed: %d\n", ret); - return NULL; - } else if (ret == 0) { - dev_err(lt9611uxc->dev, "wait for EDID timeout\n"); - return NULL; - } - - return drm_do_get_edid(connector, lt9611uxc_get_edid_block, lt9611uxc); -} - -static const struct drm_bridge_funcs lt9611uxc_bridge_funcs = { - .attach = lt9611uxc_bridge_attach, - .mode_valid = lt9611uxc_bridge_mode_valid, - .mode_set = lt9611uxc_bridge_mode_set, - .detect = lt9611uxc_bridge_detect, - .get_edid = lt9611uxc_bridge_get_edid, -}; - -static int lt9611uxc_parse_dt(struct device *dev, - struct lt9611uxc *lt9611uxc) -{ - lt9611uxc->dsi0_node = of_graph_get_remote_node(dev->of_node, 0, -1); - lt9611uxc->dsi1_node = of_graph_get_remote_node(dev->of_node, 1, -1); - - if (!lt9611uxc->dsi0_node && !lt9611uxc->dsi1_node) { - dev_err(lt9611uxc->dev, "failed to get remote node for primary dsi\n"); - return -ENODEV; - } - - - return 0; -} - -static int lt9611uxc_gpio_init(struct lt9611uxc *lt9611uxc) -{ - struct device *dev = lt9611uxc->dev; - - lt9611uxc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); - if (IS_ERR(lt9611uxc->reset_gpio)) { - dev_err(dev, "failed to acquire reset gpio\n"); - return PTR_ERR(lt9611uxc->reset_gpio); - } - - lt9611uxc->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); - if (IS_ERR(lt9611uxc->enable_gpio)) { - dev_err(dev, "failed to acquire enable gpio\n"); - return PTR_ERR(lt9611uxc->enable_gpio); - } - - return 0; -} - -static int lt9611uxc_read_device_rev(struct lt9611uxc *lt9611uxc) -{ - unsigned int rev0, rev1, rev2; - int ret; - - lt9611uxc_lock(lt9611uxc); - - ret = regmap_read(lt9611uxc->regmap, 0x8100, &rev0); - ret |= regmap_read(lt9611uxc->regmap, 0x8101, &rev1); - ret |= regmap_read(lt9611uxc->regmap, 0x8102, &rev2); - if (ret) - dev_err(lt9611uxc->dev, "failed to read revision: %d\n", ret); - else - dev_info(lt9611uxc->dev, "LT9611 revision: 0x%02x.%02x.%02x\n", rev0, rev1, rev2); - - lt9611uxc_unlock(lt9611uxc); - - return ret; -} - -static int lt9611uxc_read_version(struct lt9611uxc *lt9611uxc) -{ - unsigned int rev; - int ret; - - lt9611uxc_lock(lt9611uxc); - - ret = regmap_read(lt9611uxc->regmap, 0xb021, &rev); - if (ret) - dev_err(lt9611uxc->dev, "failed to read revision: %d\n", ret); - else - dev_info(lt9611uxc->dev, "LT9611 version: 0x%02x\n", rev); - - lt9611uxc_unlock(lt9611uxc); - - return ret < 0 ? ret : rev; -} - -static int lt9611uxc_hdmi_hw_params(struct device *dev, void *data, - struct hdmi_codec_daifmt *fmt, - struct hdmi_codec_params *hparms) -{ - /* - * LT9611UXC will automatically detect rate and sample size, so no need - * to setup anything here. - */ - return 0; -} - -static void lt9611uxc_audio_shutdown(struct device *dev, void *data) -{ -} - -static int lt9611uxc_hdmi_i2s_get_dai_id(struct snd_soc_component *component, - struct device_node *endpoint) -{ - struct of_endpoint of_ep; - int ret; - - ret = of_graph_parse_endpoint(endpoint, &of_ep); - if (ret < 0) - return ret; - - /* - * HDMI sound should be located as reg = <2> - * Then, it is sound port 0 - */ - if (of_ep.port == 2) - return 0; - - return -EINVAL; -} - -static const struct hdmi_codec_ops lt9611uxc_codec_ops = { - .hw_params = lt9611uxc_hdmi_hw_params, - .audio_shutdown = lt9611uxc_audio_shutdown, - .get_dai_id = lt9611uxc_hdmi_i2s_get_dai_id, -}; - -static int lt9611uxc_audio_init(struct device *dev, struct lt9611uxc *lt9611uxc) -{ - struct hdmi_codec_pdata codec_data = { - .ops = <9611uxc_codec_ops, - .max_i2s_channels = 2, - .i2s = 1, - .data = lt9611uxc, - }; - - lt9611uxc->audio_pdev = - platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, - PLATFORM_DEVID_AUTO, - &codec_data, sizeof(codec_data)); - - return PTR_ERR_OR_ZERO(lt9611uxc->audio_pdev); -} - -static void lt9611uxc_audio_exit(struct lt9611uxc *lt9611uxc) -{ - if (lt9611uxc->audio_pdev) { - platform_device_unregister(lt9611uxc->audio_pdev); - lt9611uxc->audio_pdev = NULL; - } -} - -#define LT9611UXC_FW_PAGE_SIZE 32 -static void lt9611uxc_firmware_write_page(struct lt9611uxc *lt9611uxc, u16 addr, const u8 *buf) -{ - struct reg_sequence seq_write_prepare[] = { - REG_SEQ0(0x805a, 0x04), - REG_SEQ0(0x805a, 0x00), - - REG_SEQ0(0x805e, 0xdf), - REG_SEQ0(0x805a, 0x20), - REG_SEQ0(0x805a, 0x00), - REG_SEQ0(0x8058, 0x21), - }; - - struct reg_sequence seq_write_addr[] = { - REG_SEQ0(0x805b, (addr >> 16) & 0xff), - REG_SEQ0(0x805c, (addr >> 8) & 0xff), - REG_SEQ0(0x805d, addr & 0xff), - REG_SEQ0(0x805a, 0x10), - REG_SEQ0(0x805a, 0x00), - }; - - regmap_write(lt9611uxc->regmap, 0x8108, 0xbf); - msleep(20); - regmap_write(lt9611uxc->regmap, 0x8108, 0xff); - msleep(20); - regmap_multi_reg_write(lt9611uxc->regmap, seq_write_prepare, ARRAY_SIZE(seq_write_prepare)); - regmap_noinc_write(lt9611uxc->regmap, 0x8059, buf, LT9611UXC_FW_PAGE_SIZE); - regmap_multi_reg_write(lt9611uxc->regmap, seq_write_addr, ARRAY_SIZE(seq_write_addr)); - msleep(20); -} - -static void lt9611uxc_firmware_read_page(struct lt9611uxc *lt9611uxc, u16 addr, char *buf) -{ - struct reg_sequence seq_read_page[] = { - REG_SEQ0(0x805a, 0xa0), - REG_SEQ0(0x805a, 0x80), - REG_SEQ0(0x805b, (addr >> 16) & 0xff), - REG_SEQ0(0x805c, (addr >> 8) & 0xff), - REG_SEQ0(0x805d, addr & 0xff), - REG_SEQ0(0x805a, 0x90), - REG_SEQ0(0x805a, 0x80), - REG_SEQ0(0x8058, 0x21), - }; - - regmap_multi_reg_write(lt9611uxc->regmap, seq_read_page, ARRAY_SIZE(seq_read_page)); - regmap_noinc_read(lt9611uxc->regmap, 0x805f, buf, LT9611UXC_FW_PAGE_SIZE); -} - -static char *lt9611uxc_firmware_read(struct lt9611uxc *lt9611uxc, size_t size) -{ - struct reg_sequence seq_read_setup[] = { - REG_SEQ0(0x805a, 0x84), - REG_SEQ0(0x805a, 0x80), - }; - - char *readbuf; - u16 offset; - - readbuf = kzalloc(ALIGN(size, 32), GFP_KERNEL); - if (!readbuf) - return NULL; - - regmap_multi_reg_write(lt9611uxc->regmap, seq_read_setup, ARRAY_SIZE(seq_read_setup)); - - for (offset = 0; - offset < size; - offset += LT9611UXC_FW_PAGE_SIZE) - lt9611uxc_firmware_read_page(lt9611uxc, offset, &readbuf[offset]); - - return readbuf; -} - -static int lt9611uxc_firmware_update(struct lt9611uxc *lt9611uxc) -{ - int ret; - u16 offset; - size_t remain; - char *readbuf; - const struct firmware *fw; - - struct reg_sequence seq_setup[] = { - REG_SEQ0(0x805e, 0xdf), - REG_SEQ0(0x8058, 0x00), - REG_SEQ0(0x8059, 0x50), - REG_SEQ0(0x805a, 0x10), - REG_SEQ0(0x805a, 0x00), - }; - - - struct reg_sequence seq_block_erase[] = { - REG_SEQ0(0x805a, 0x04), - REG_SEQ0(0x805a, 0x00), - REG_SEQ0(0x805b, 0x00), - REG_SEQ0(0x805c, 0x00), - REG_SEQ0(0x805d, 0x00), - REG_SEQ0(0x805a, 0x01), - REG_SEQ0(0x805a, 0x00), - }; - - ret = request_firmware(&fw, "lt9611uxc_fw.bin", lt9611uxc->dev); - if (ret < 0) - return ret; - - dev_info(lt9611uxc->dev, "Updating firmware\n"); - lt9611uxc_lock(lt9611uxc); - - regmap_multi_reg_write(lt9611uxc->regmap, seq_setup, ARRAY_SIZE(seq_setup)); - - /* - * Need erase block 2 timess here. Sometimes, block erase can fail. - * This is a workaroud. - */ - regmap_multi_reg_write(lt9611uxc->regmap, seq_block_erase, ARRAY_SIZE(seq_block_erase)); - msleep(3000); - regmap_multi_reg_write(lt9611uxc->regmap, seq_block_erase, ARRAY_SIZE(seq_block_erase)); - msleep(3000); - - for (offset = 0, remain = fw->size; - remain >= LT9611UXC_FW_PAGE_SIZE; - offset += LT9611UXC_FW_PAGE_SIZE, remain -= LT9611UXC_FW_PAGE_SIZE) - lt9611uxc_firmware_write_page(lt9611uxc, offset, fw->data + offset); - - if (remain > 0) { - char buf[LT9611UXC_FW_PAGE_SIZE]; - - memset(buf, 0xff, LT9611UXC_FW_PAGE_SIZE); - memcpy(buf, fw->data + offset, remain); - lt9611uxc_firmware_write_page(lt9611uxc, offset, buf); - } - msleep(20); - - readbuf = lt9611uxc_firmware_read(lt9611uxc, fw->size); - if (!readbuf) { - ret = -ENOMEM; - goto out; - } - - if (!memcmp(readbuf, fw->data, fw->size)) { - dev_err(lt9611uxc->dev, "Firmware update failed\n"); - print_hex_dump(KERN_ERR, "fw: ", DUMP_PREFIX_OFFSET, 16, 1, readbuf, fw->size, false); - ret = -EINVAL; - } else { - dev_info(lt9611uxc->dev, "Firmware updates successfully\n"); - ret = 0; - } - kfree(readbuf); - -out: - lt9611uxc_unlock(lt9611uxc); - lt9611uxc_reset(lt9611uxc); - release_firmware(fw); - - return ret; -} - -static ssize_t lt9611uxc_firmware_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) -{ - struct lt9611uxc *lt9611uxc = dev_get_drvdata(dev); - int ret; - - ret = lt9611uxc_firmware_update(lt9611uxc); - if (ret < 0) - return ret; - return len; -} - -static ssize_t lt9611uxc_firmware_show(struct device *dev, struct device_attribute *attr, char *buf) -{ - struct lt9611uxc *lt9611uxc = dev_get_drvdata(dev); - - return sysfs_emit(buf, "%02x\n", lt9611uxc->fw_version); -} - -static DEVICE_ATTR_RW(lt9611uxc_firmware); - -static struct attribute *lt9611uxc_attrs[] = { - &dev_attr_lt9611uxc_firmware.attr, - NULL, -}; - -static const struct attribute_group lt9611uxc_attr_group = { - .attrs = lt9611uxc_attrs, -}; - -static const struct attribute_group *lt9611uxc_attr_groups[] = { - <9611uxc_attr_group, - NULL, -}; - -static int lt9611uxc_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct lt9611uxc *lt9611uxc; - struct device *dev = &client->dev; - int ret; - bool fw_updated = false; - - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { - dev_err(dev, "device doesn't support I2C\n"); - return -ENODEV; - } - - lt9611uxc = devm_kzalloc(dev, sizeof(*lt9611uxc), GFP_KERNEL); - if (!lt9611uxc) - return -ENOMEM; - - lt9611uxc->dev = &client->dev; - lt9611uxc->client = client; - mutex_init(<9611uxc->ocm_lock); - - lt9611uxc->regmap = devm_regmap_init_i2c(client, <9611uxc_regmap_config); - if (IS_ERR(lt9611uxc->regmap)) { - dev_err(lt9611uxc->dev, "regmap i2c init failed\n"); - return PTR_ERR(lt9611uxc->regmap); - } - - ret = lt9611uxc_parse_dt(&client->dev, lt9611uxc); - if (ret) { - dev_err(dev, "failed to parse device tree\n"); - return ret; - } - - ret = lt9611uxc_gpio_init(lt9611uxc); - if (ret < 0) - goto err_of_put; - - ret = lt9611uxc_regulator_init(lt9611uxc); - if (ret < 0) - goto err_of_put; - - lt9611uxc_assert_5v(lt9611uxc); - - ret = lt9611uxc_regulator_enable(lt9611uxc); - if (ret) - goto err_of_put; - - lt9611uxc_reset(lt9611uxc); - - ret = lt9611uxc_read_device_rev(lt9611uxc); - if (ret) { - dev_err(dev, "failed to read chip rev\n"); - goto err_disable_regulators; - } - -retry: - ret = lt9611uxc_read_version(lt9611uxc); - if (ret < 0) { - dev_err(dev, "failed to read FW version\n"); - goto err_disable_regulators; - } else if (ret == 0) { - if (!fw_updated) { - fw_updated = true; - dev_err(dev, "FW version 0, enforcing firmware update\n"); - ret = lt9611uxc_firmware_update(lt9611uxc); - if (ret < 0) - goto err_disable_regulators; - else - goto retry; - } else { - dev_err(dev, "FW version 0, update failed\n"); - ret = -EOPNOTSUPP; - goto err_disable_regulators; - } - } else if (ret < 0x40) { - dev_info(dev, "FW version 0x%x, HPD not supported\n", ret); - } else { - lt9611uxc->hpd_supported = true; - } - lt9611uxc->fw_version = ret; - - init_waitqueue_head(<9611uxc->wq); - INIT_WORK(<9611uxc->work, lt9611uxc_hpd_work); - - ret = devm_request_threaded_irq(dev, client->irq, NULL, - lt9611uxc_irq_thread_handler, - IRQF_ONESHOT, "lt9611uxc", lt9611uxc); - if (ret) { - dev_err(dev, "failed to request irq\n"); - goto err_disable_regulators; - } - - i2c_set_clientdata(client, lt9611uxc); - - lt9611uxc->bridge.funcs = <9611uxc_bridge_funcs; - lt9611uxc->bridge.of_node = client->dev.of_node; - lt9611uxc->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID; - if (lt9611uxc->hpd_supported) - lt9611uxc->bridge.ops |= DRM_BRIDGE_OP_HPD; - lt9611uxc->bridge.type = DRM_MODE_CONNECTOR_HDMIA; - - drm_bridge_add(<9611uxc->bridge); - - /* Attach primary DSI */ - lt9611uxc->dsi0 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi0_node); - if (IS_ERR(lt9611uxc->dsi0)) { - ret = PTR_ERR(lt9611uxc->dsi0); - goto err_remove_bridge; - } - - /* Attach secondary DSI, if specified */ - if (lt9611uxc->dsi1_node) { - lt9611uxc->dsi1 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi1_node); - if (IS_ERR(lt9611uxc->dsi1)) { - ret = PTR_ERR(lt9611uxc->dsi1); - goto err_remove_bridge; - } - } - - return lt9611uxc_audio_init(dev, lt9611uxc); - -err_remove_bridge: - drm_bridge_remove(<9611uxc->bridge); - -err_disable_regulators: - regulator_bulk_disable(ARRAY_SIZE(lt9611uxc->supplies), lt9611uxc->supplies); - -err_of_put: - of_node_put(lt9611uxc->dsi1_node); - of_node_put(lt9611uxc->dsi0_node); - - return ret; -} - -static int lt9611uxc_remove(struct i2c_client *client) -{ - struct lt9611uxc *lt9611uxc = i2c_get_clientdata(client); - - disable_irq(client->irq); - flush_scheduled_work(); - lt9611uxc_audio_exit(lt9611uxc); - drm_bridge_remove(<9611uxc->bridge); - - mutex_destroy(<9611uxc->ocm_lock); - - regulator_bulk_disable(ARRAY_SIZE(lt9611uxc->supplies), lt9611uxc->supplies); - - of_node_put(lt9611uxc->dsi1_node); - of_node_put(lt9611uxc->dsi0_node); - - return 0; -} - -static struct i2c_device_id lt9611uxc_id[] = { - { "lontium,lt9611uxc", 0 }, - { /* sentinel */ } -}; - -static const struct of_device_id lt9611uxc_match_table[] = { - { .compatible = "lontium,lt9611uxc" }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, lt9611uxc_match_table); - -static struct i2c_driver lt9611uxc_driver = { - .driver = { - .name = "lt9611uxc", - .of_match_table = lt9611uxc_match_table, - .dev_groups = lt9611uxc_attr_groups, - }, - .probe = lt9611uxc_probe, - .remove = lt9611uxc_remove, - .id_table = lt9611uxc_id, -}; -module_i2c_driver(lt9611uxc_driver); - -MODULE_AUTHOR("Dmitry Baryshkov "); -MODULE_LICENSE("GPL v2"); diff --git a/rr-cache/f93bd68f8905ee72aa0a339525fd22c07d672dd9/postimage b/rr-cache/f93bd68f8905ee72aa0a339525fd22c07d672dd9/postimage deleted file mode 100644 index d3be46f..0000000 --- a/rr-cache/f93bd68f8905ee72aa0a339525fd22c07d672dd9/postimage +++ /dev/null @@ -1,1249 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_NUMA_BALANCING=y -CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_HUGETLB=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_USER_NS=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_ARCH_ACTIONS=y -CONFIG_ARCH_SUNXI=y -CONFIG_ARCH_ALPINE=y -CONFIG_ARCH_APPLE=y -CONFIG_ARCH_BCM2835=y -CONFIG_ARCH_BCM4908=y -CONFIG_ARCH_BCM_IPROC=y -CONFIG_ARCH_BERLIN=y -CONFIG_ARCH_BRCMSTB=y -CONFIG_ARCH_EXYNOS=y -CONFIG_ARCH_K3=y -CONFIG_ARCH_LAYERSCAPE=y -CONFIG_ARCH_LG1K=y -CONFIG_ARCH_HISI=y -CONFIG_ARCH_KEEMBAY=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MESON=y -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_MXC=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_RENESAS=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_S32=y -CONFIG_ARCH_SEATTLE=y -CONFIG_ARCH_INTEL_SOCFPGA=y -CONFIG_ARCH_SYNQUACER=y -CONFIG_ARCH_TEGRA=y -CONFIG_ARCH_SPRD=y -CONFIG_ARCH_THUNDER=y -CONFIG_ARCH_THUNDER2=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_ARCH_VEXPRESS=y -CONFIG_ARCH_VISCONTI=y -CONFIG_ARCH_XGENE=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_ARM64_VA_BITS_48=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_SMT=y -CONFIG_NUMA=y -CONFIG_SECCOMP=y -CONFIG_KEXEC=y -CONFIG_KEXEC_FILE=y -CONFIG_CRASH_DUMP=y -CONFIG_XEN=y -CONFIG_COMPAT=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_HIBERNATION=y -CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -CONFIG_ENERGY_MODEL=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPUFREQ_DT=y -CONFIG_ACPI_CPPC_CPUFREQ=m -CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m -CONFIG_ARM_ARMADA_37XX_CPUFREQ=y -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_IMX_CPUFREQ_DT=m -CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y -CONFIG_ARM_QCOM_CPUFREQ_HW=y -CONFIG_ARM_RASPBERRYPI_CPUFREQ=m -CONFIG_ARM_SCMI_CPUFREQ=y -CONFIG_ARM_TEGRA186_CPUFREQ=y -CONFIG_QORIQ_CPUFREQ=y -CONFIG_ARM_SCMI_PROTOCOL=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_RASPBERRYPI_FIRMWARE=y -CONFIG_INTEL_STRATIX10_SERVICE=y -CONFIG_INTEL_STRATIX10_RSU=m -CONFIG_QCOM_SCM=y -CONFIG_EFI_CAPSULE_LOADER=y -CONFIG_IMX_SCU=y -CONFIG_IMX_SCU_PD=y -CONFIG_ACPI=y -CONFIG_ACPI_APEI=y -CONFIG_ACPI_APEI_GHES=y -CONFIG_ACPI_APEI_PCIEAER=y -CONFIG_ACPI_APEI_MEMORY_FAILURE=y -CONFIG_ACPI_APEI_EINJ=y -CONFIG_VIRTUALIZATION=y -CONFIG_KVM=y -CONFIG_ARM64_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64_CE=m -CONFIG_CRYPTO_SHA3_ARM64=m -CONFIG_CRYPTO_SM3_ARM64_CE=m -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_AES_ARM64_BS=m -CONFIG_JUMP_LABEL=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_KSM=y -CONFIG_MEMORY_FAILURE=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=m -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_NET_DSA=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBS=m -CONFIG_NET_SCH_ETF=m -CONFIG_NET_SCH_TAPRIO=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_GACT=m -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_GATE=m -CONFIG_QRTR=m -CONFIG_QRTR_SMD=m -CONFIG_QRTR_TUN=m -CONFIG_BPF_JIT=y -CONFIG_CAN=m -CONFIG_CAN_RCAR=m -CONFIG_CAN_RCAR_CANFD=m -CONFIG_CAN_FLEXCAN=m -CONFIG_BT=m -CONFIG_BT_HIDP=m -# CONFIG_BT_HS is not set -# CONFIG_BT_LE is not set -CONFIG_BT_LEDS=y -# CONFIG_BT_DEBUGFS is not set -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HCIUART_QCA=y -CONFIG_BT_QCOMSMD=m -CONFIG_CFG80211=m -CONFIG_MAC80211=m -CONFIG_MAC80211_LEDS=y -CONFIG_RFKILL=m -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y -CONFIG_NFC=m -CONFIG_NFC_NCI=m -CONFIG_NFC_S3FWRN5_I2C=m -CONFIG_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCI_IOV=y -CONFIG_PCI_PASID=y -CONFIG_HOTPLUG_PCI=y -CONFIG_HOTPLUG_PCI_ACPI=y -CONFIG_PCI_AARDVARK=y -CONFIG_PCI_TEGRA=y -CONFIG_PCIE_RCAR_HOST=y -CONFIG_PCIE_RCAR_EP=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCI_XGENE=y -CONFIG_PCIE_ALTERA=y -CONFIG_PCIE_ALTERA_MSI=y -CONFIG_PCI_HOST_THUNDER_PEM=y -CONFIG_PCI_HOST_THUNDER_ECAM=y -CONFIG_PCIE_ROCKCHIP_HOST=m -CONFIG_PCIE_BRCMSTB=m -CONFIG_PCI_IMX6=y -CONFIG_PCI_LAYERSCAPE=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y -CONFIG_PCI_HISI=y -CONFIG_PCIE_QCOM=y -CONFIG_PCIE_ARMADA_8K=y -CONFIG_PCIE_KIRIN=y -CONFIG_PCIE_HISI_STB=y -CONFIG_PCIE_TEGRA194_HOST=m -CONFIG_PCIE_VISCONTI_HOST=y -CONFIG_PCI_ENDPOINT=y -CONFIG_PCI_ENDPOINT_CONFIGFS=y -CONFIG_PCI_EPF_TEST=m -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_HISILICON_LPC=y -CONFIG_FSL_MC_BUS=y -CONFIG_TEGRA_ACONNECT=m -CONFIG_GNSS=m -CONFIG_GNSS_MTK_SERIAL=m -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_SST25L=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_DENALI_DT=y -CONFIG_MTD_NAND_MARVELL=y -CONFIG_MTD_NAND_FSL_IFC=y -CONFIG_MTD_NAND_QCOM=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTK_DEVAPC=m -CONFIG_SPI_CADENCE_QUADSPI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=m -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_NVME=m -CONFIG_SRAM=y -CONFIG_PCI_ENDPOINT_TEST=m -CONFIG_EEPROM_AT24=m -CONFIG_EEPROM_AT25=m -CONFIG_UACCE=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_SAS_ATA=y -CONFIG_SCSI_HISI_SAS=y -CONFIG_SCSI_HISI_SAS_PCI=y -CONFIG_MEGARAID_SAS=y -CONFIG_SCSI_MPT3SAS=m -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=m -CONFIG_SCSI_UFS_HISI=y -CONFIG_SCSI_UFS_EXYNOS=y -CONFIG_ATA=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_AHCI_CEVA=y -CONFIG_AHCI_MVEBU=y -CONFIG_AHCI_XGENE=y -CONFIG_AHCI_QORIQ=y -CONFIG_SATA_SIL24=y -CONFIG_SATA_RCAR=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_OF_PLATFORM=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_NETDEVICES=y -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_TUN=y -CONFIG_VETH=m -CONFIG_VIRTIO_NET=y -CONFIG_NET_DSA_MSCC_FELIX=m -CONFIG_AMD_XGBE=y -CONFIG_NET_XGENE=y -CONFIG_ATL1C=m -CONFIG_BCMGENET=m -CONFIG_BNX2X=m -CONFIG_MACB=y -CONFIG_THUNDER_NIC_PF=y -CONFIG_FEC=y -CONFIG_FSL_FMAN=y -CONFIG_FSL_DPAA_ETH=y -CONFIG_FSL_DPAA2_ETH=y -CONFIG_FSL_ENETC=y -CONFIG_FSL_ENETC_VF=y -CONFIG_FSL_ENETC_QOS=y -CONFIG_HIX5HD2_GMAC=y -CONFIG_HNS_DSAF=y -CONFIG_HNS_ENET=y -CONFIG_HNS3=y -CONFIG_HNS3_HCLGE=y -CONFIG_HNS3_ENET=y -CONFIG_E1000=y -CONFIG_E1000E=y -CONFIG_IGB=y -CONFIG_IGBVF=y -CONFIG_MVNETA=y -CONFIG_MVPP2=y -CONFIG_SKY2=y -CONFIG_MLX4_EN=m -CONFIG_MLX5_CORE=m -CONFIG_MLX5_CORE_EN=y -CONFIG_QCOM_EMAC=m -CONFIG_RMNET=m -CONFIG_SH_ETH=y -CONFIG_RAVB=y -CONFIG_SMC91X=y -CONFIG_SMSC911X=y -CONFIG_SNI_AVE=y -CONFIG_SNI_NETSEC=y -CONFIG_STMMAC_ETH=m -CONFIG_TI_K3_AM65_CPSW_NUSS=y -CONFIG_QCOM_IPA=m -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -CONFIG_AQUANTIA_PHY=y -CONFIG_BCM54140_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_MARVELL_10G_PHY=m -CONFIG_MESON_GXL_PHY=m -CONFIG_MICREL_PHY=y -CONFIG_MICROSEMI_PHY=y -CONFIG_AT803X_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_ROCKCHIP_PHY=y -CONFIG_DP83867_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9800=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_ATH10K_SNOC=m -CONFIG_WCN36XX=m -CONFIG_BRCMFMAC=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_PCIE=m -CONFIG_WL18XX=m -CONFIG_WLCORE_SDIO=m -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_ADC=m -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_SNVS_PWRKEY=m -CONFIG_KEYBOARD_IMX_SC_KEY=m -CONFIG_KEYBOARD_CROS_EC=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=m -CONFIG_TOUCHSCREEN_GOODIX=m -CONFIG_TOUCHSCREEN_EDT_FT5X06=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_PM8941_PWRKEY=y -CONFIG_INPUT_PM8XXX_VIBRATOR=m -CONFIG_INPUT_PWM_BEEPER=m -CONFIG_INPUT_PWM_VIBRA=m -CONFIG_INPUT_HISI_POWERKEY=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIO_AMBAKMI=y -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_BCM2835AUX=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_OMAP=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_UNIPHIER=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_MESON=y -CONFIG_SERIAL_MESON_CONSOLE=y -CONFIG_SERIAL_SAMSUNG=y -CONFIG_SERIAL_SAMSUNG_CONSOLE=y -CONFIG_SERIAL_TEGRA=y -CONFIG_SERIAL_TEGRA_TCU=y -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SERIAL_QCOM_GENI=y -CONFIG_SERIAL_QCOM_GENI_CONSOLE=y -CONFIG_SERIAL_XILINX_PS_UART=y -CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -CONFIG_SERIAL_FSL_LPUART=y -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -CONFIG_SERIAL_FSL_LINFLEXUART=y -CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -CONFIG_SERIAL_MVEBU_UART=y -CONFIG_SERIAL_OWL=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_IPMI_HANDLER=m -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SI=m -CONFIG_TCG_TPM=y -CONFIG_TCG_TIS_I2C_INFINEON=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_I2C_BCM2835=m -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_I2C_GPIO=m -CONFIG_I2C_IMX=y -CONFIG_I2C_IMX_LPI2C=y -CONFIG_I2C_MESON=y -CONFIG_I2C_MT65XX=y -CONFIG_I2C_MV64XXX=y -CONFIG_I2C_OMAP=y -CONFIG_I2C_OWL=y -CONFIG_I2C_PXA=y -CONFIG_I2C_QCOM_CCI=m -CONFIG_I2C_QCOM_GENI=m -CONFIG_I2C_QUP=y -CONFIG_I2C_RIIC=y -CONFIG_I2C_RK3X=y -CONFIG_I2C_S3C2410=y -CONFIG_I2C_SH_MOBILE=y -CONFIG_I2C_TEGRA=y -CONFIG_I2C_UNIPHIER_F=y -CONFIG_I2C_RCAR=y -CONFIG_I2C_CROS_EC_TUNNEL=y -CONFIG_SPI=y -CONFIG_SPI_ARMADA_3700=y -CONFIG_SPI_BCM2835=m -CONFIG_SPI_BCM2835AUX=m -CONFIG_SPI_DESIGNWARE=m -CONFIG_SPI_DW_DMA=y -CONFIG_SPI_DW_MMIO=m -CONFIG_SPI_FSL_LPSPI=y -CONFIG_SPI_FSL_QUADSPI=y -CONFIG_SPI_NXP_FLEXSPI=y -CONFIG_SPI_IMX=m -CONFIG_SPI_FSL_DSPI=y -CONFIG_SPI_MESON_SPICC=m -CONFIG_SPI_MESON_SPIFC=m -CONFIG_SPI_ORION=y -CONFIG_SPI_PL022=y -CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_RPCIF=m -CONFIG_SPI_QCOM_QSPI=m -CONFIG_SPI_QUP=y -CONFIG_SPI_QCOM_GENI=m -CONFIG_SPI_S3C64XX=y -CONFIG_SPI_SH_MSIOF=m -CONFIG_SPI_SUN6I=y -CONFIG_SPI_SPIDEV=m -CONFIG_SPMI=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_PINCTRL_MAX77620=y -CONFIG_PINCTRL_OWL=y -CONFIG_PINCTRL_S700=y -CONFIG_PINCTRL_S900=y -CONFIG_PINCTRL_IMX8MM=y -CONFIG_PINCTRL_IMX8MN=y -CONFIG_PINCTRL_IMX8MP=y -CONFIG_PINCTRL_IMX8MQ=y -CONFIG_PINCTRL_IMX8QM=y -CONFIG_PINCTRL_IMX8QXP=y -CONFIG_PINCTRL_IMX8DXL=y -CONFIG_PINCTRL_IMX8ULP=y -CONFIG_PINCTRL_MSM=y -CONFIG_PINCTRL_IPQ8074=y -CONFIG_PINCTRL_IPQ6018=y -CONFIG_PINCTRL_MSM8916=y -CONFIG_PINCTRL_MSM8994=y -CONFIG_PINCTRL_MSM8996=y -CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_QCS404=y -CONFIG_PINCTRL_QDF2XXX=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -CONFIG_PINCTRL_SC7180=y -CONFIG_PINCTRL_SC7280=y -CONFIG_PINCTRL_SDM845=y -CONFIG_PINCTRL_SM8150=y -CONFIG_PINCTRL_SM8250=y -CONFIG_PINCTRL_SM8350=y -CONFIG_PINCTRL_LPASS_LPI=m -CONFIG_GPIO_ALTERA=m -CONFIG_GPIO_DAVINCI=y -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_MB86S7X=y -CONFIG_GPIO_MPC8XXX=y -CONFIG_GPIO_MXC=y -CONFIG_GPIO_PL061=y -CONFIG_GPIO_RCAR=y -CONFIG_GPIO_UNIPHIER=y -CONFIG_GPIO_VISCONTI=y -CONFIG_GPIO_WCD934X=m -CONFIG_GPIO_XGENE=y -CONFIG_GPIO_XGENE_SB=y -CONFIG_GPIO_MAX732X=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_BD9571MWV=m -CONFIG_GPIO_MAX77620=y -CONFIG_GPIO_SL28CPLD=m -CONFIG_POWER_AVS=y -CONFIG_QCOM_CPR=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_RESET_QCOM_PON=m -CONFIG_POWER_RESET_XGENE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_SYSCON_REBOOT_MODE=y -CONFIG_BATTERY_SBS=m -CONFIG_BATTERY_BQ27XXX=y -CONFIG_SENSORS_ARM_SCMI=y -CONFIG_BATTERY_MAX17042=m -CONFIG_CHARGER_BQ25890=m -CONFIG_CHARGER_BQ25980=m -CONFIG_SENSORS_ARM_SCPI=y -CONFIG_SENSORS_JC42=m -CONFIG_SENSORS_LM90=m -CONFIG_SENSORS_PWM_FAN=m -CONFIG_SENSORS_RASPBERRYPI_HWMON=m -CONFIG_SENSORS_SL28CPLD=m -CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_INA3221=m -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_CPU_THERMAL=y -CONFIG_THERMAL_EMULATION=y -CONFIG_QORIQ_THERMAL=m -CONFIG_SUN8I_THERMAL=y -CONFIG_IMX_SC_THERMAL=m -CONFIG_IMX8MM_THERMAL=m -CONFIG_ROCKCHIP_THERMAL=m -CONFIG_RCAR_THERMAL=y -CONFIG_RCAR_GEN3_THERMAL=y -CONFIG_ARMADA_THERMAL=y -CONFIG_BCM2711_THERMAL=m -CONFIG_BCM2835_THERMAL=m -CONFIG_BRCMSTB_THERMAL=m -CONFIG_EXYNOS_THERMAL=y -CONFIG_TEGRA_BPMP_THERMAL=m -CONFIG_TEGRA_SOCTHERM=m -CONFIG_QCOM_TSENS=y -CONFIG_QCOM_SPMI_TEMP_ALARM=m -CONFIG_QCOM_LMH=m -CONFIG_UNIPHIER_THERMAL=y -CONFIG_WATCHDOG=y -CONFIG_SL28CPLD_WATCHDOG=m -CONFIG_ARM_SP805_WATCHDOG=y -CONFIG_ARM_SBSA_WATCHDOG=y -CONFIG_ARM_SMC_WATCHDOG=y -CONFIG_S3C2410_WATCHDOG=y -CONFIG_DW_WATCHDOG=y -CONFIG_SUNXI_WATCHDOG=m -CONFIG_IMX2_WDT=y -CONFIG_IMX_SC_WDT=m -CONFIG_QCOM_WDT=m -CONFIG_MESON_GXBB_WATCHDOG=m -CONFIG_MESON_WATCHDOG=m -CONFIG_RENESAS_WDT=y -CONFIG_UNIPHIER_WATCHDOG=y -CONFIG_BCM2835_WDT=y -CONFIG_MFD_ALTERA_SYSMGR=y -CONFIG_MFD_BD9571MWV=y -CONFIG_MFD_AXP20X_I2C=y -CONFIG_MFD_AXP20X_RSB=y -CONFIG_MFD_EXYNOS_LPASS=m -CONFIG_MFD_HI6421_PMIC=y -CONFIG_MFD_HI655X_PMIC=y -CONFIG_MFD_MAX77620=y -CONFIG_MFD_MT6397=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_MFD_RK808=y -CONFIG_MFD_SEC_CORE=y -CONFIG_MFD_SL28CPLD=y -CONFIG_MFD_ROHM_BD718XX=y -CONFIG_MFD_WCD934X=m -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_AXP20X=y -CONFIG_REGULATOR_BD718XX=y -CONFIG_REGULATOR_BD9571MWV=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_HI6421V530=y -CONFIG_REGULATOR_HI655X=y -CONFIG_REGULATOR_MAX77620=y -CONFIG_REGULATOR_MAX8973=y -CONFIG_REGULATOR_MP8859=y -CONFIG_REGULATOR_MT6358=y -CONFIG_REGULATOR_MT6397=y -CONFIG_REGULATOR_PCA9450=y -CONFIG_REGULATOR_PF8X00=y -CONFIG_REGULATOR_PFUZE100=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_QCOM_RPMH=y -CONFIG_REGULATOR_QCOM_SMD_RPM=y -CONFIG_REGULATOR_QCOM_SPMI=y -CONFIG_REGULATOR_RK808=y -CONFIG_REGULATOR_S2MPS11=y -CONFIG_REGULATOR_TPS65132=m -CONFIG_REGULATOR_VCTRL=m -CONFIG_RC_CORE=m -CONFIG_RC_DECODERS=y -CONFIG_RC_DEVICES=y -CONFIG_IR_MESON=m -CONFIG_IR_SUNXI=m -CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y -# CONFIG_DVB_NET is not set -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VIDEO_RCAR_CSI2=m -CONFIG_VIDEO_RCAR_VIN=m -CONFIG_VIDEO_SUN6I_CSI=m -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m -CONFIG_VIDEO_SAMSUNG_S5P_MFC=m -CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m -CONFIG_VIDEO_RENESAS_FDP1=m -CONFIG_VIDEO_RENESAS_FCP=m -CONFIG_VIDEO_RENESAS_VSP1=m -CONFIG_VIDEO_QCOM_VENUS=m -CONFIG_SDR_PLATFORM_DRIVERS=y -CONFIG_VIDEO_RCAR_DRIF=m -CONFIG_VIDEO_IMX219=m -CONFIG_VIDEO_OV5640=m -CONFIG_VIDEO_OV5645=m -CONFIG_VIDEO_QCOM_CAMSS=m -CONFIG_DRM=m -CONFIG_DRM_I2C_NXP_TDA998X=m -CONFIG_DRM_MALI_DISPLAY=m -CONFIG_DRM_NOUVEAU=m -CONFIG_DRM_EXYNOS=m -CONFIG_DRM_EXYNOS5433_DECON=y -CONFIG_DRM_EXYNOS7_DECON=y -CONFIG_DRM_EXYNOS_DSI=y -# CONFIG_DRM_EXYNOS_DP is not set -CONFIG_DRM_EXYNOS_HDMI=y -CONFIG_DRM_EXYNOS_MIC=y -CONFIG_DRM_ROCKCHIP=m -CONFIG_ROCKCHIP_ANALOGIX_DP=y -CONFIG_ROCKCHIP_CDN_DP=y -CONFIG_ROCKCHIP_DW_HDMI=y -CONFIG_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_ROCKCHIP_INNO_HDMI=y -CONFIG_ROCKCHIP_LVDS=y -CONFIG_DRM_RCAR_DU=m -CONFIG_DRM_RCAR_DW_HDMI=m -CONFIG_DRM_SUN4I=m -CONFIG_DRM_SUN6I_DSI=m -CONFIG_DRM_SUN8I_DW_HDMI=m -CONFIG_DRM_SUN8I_MIXER=m -CONFIG_DRM_MSM=m -CONFIG_DRM_TEGRA=m -CONFIG_DRM_PANEL_LVDS=m -CONFIG_DRM_PANEL_SIMPLE=m -CONFIG_DRM_PANEL_EDP=m -CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m -CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m -CONFIG_DRM_PANEL_RAYDIUM_RM67191=m -CONFIG_DRM_PANEL_SITRONIX_ST7703=m -CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m -CONFIG_DRM_DISPLAY_CONNECTOR=m -CONFIG_DRM_LONTIUM_LT8912B=m -CONFIG_DRM_NWL_MIPI_DSI=m -CONFIG_DRM_LONTIUM_LT9611=m -CONFIG_DRM_PARADE_PS8640=m -CONFIG_DRM_SII902X=m -CONFIG_DRM_SIMPLE_BRIDGE=m -CONFIG_DRM_THINE_THC63LVD1024=m -CONFIG_DRM_TI_SN65DSI86=m -CONFIG_DRM_LONTIUM_LT9611UXC=m -CONFIG_DRM_I2C_ADV7511=m -CONFIG_DRM_I2C_ADV7511_AUDIO=y -CONFIG_DRM_DW_HDMI_AHB_AUDIO=m -CONFIG_DRM_DW_HDMI_CEC=m -CONFIG_DRM_IMX_DCSS=m -CONFIG_DRM_VC4=m -CONFIG_DRM_ETNAVIV=m -CONFIG_DRM_HISI_HIBMC=m -CONFIG_DRM_HISI_KIRIN=m -CONFIG_DRM_MEDIATEK=m -CONFIG_DRM_MEDIATEK_HDMI=m -CONFIG_DRM_MXSFB=m -CONFIG_DRM_MESON=m -CONFIG_DRM_PL111=m -CONFIG_DRM_LIMA=m -CONFIG_DRM_PANFROST=m -CONFIG_FB=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_EFI=y -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_LP855X=m -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_HDA_TEGRA=m -CONFIG_SND_HDA_CODEC_HDMI=m -CONFIG_SND_SOC=y -CONFIG_SND_BCM2835_SOC_I2S=m -CONFIG_SND_SOC_FSL_SAI=m -CONFIG_SND_SOC_FSL_ASRC=m -CONFIG_SND_SOC_FSL_MICFIL=m -CONFIG_SND_SOC_FSL_EASRC=m -CONFIG_SND_IMX_SOC=m -CONFIG_SND_SOC_IMX_SGTL5000=m -CONFIG_SND_SOC_IMX_SPDIF=m -CONFIG_SND_SOC_IMX_AUDMIX=m -CONFIG_SND_SOC_FSL_ASOC_CARD=m -CONFIG_SND_MESON_AXG_SOUND_CARD=m -CONFIG_SND_MESON_GX_SOUND_CARD=m -CONFIG_SND_SOC_QCOM=m -CONFIG_SND_SOC_APQ8016_SBC=m -CONFIG_SND_SOC_MSM8996=m -CONFIG_SND_SOC_SDM845=m -CONFIG_SND_SOC_SM8250=m -CONFIG_SND_SOC_ROCKCHIP=m -CONFIG_SND_SOC_ROCKCHIP_SPDIF=m -CONFIG_SND_SOC_ROCKCHIP_RT5645=m -CONFIG_SND_SOC_RK3399_GRU_SOUND=m -CONFIG_SND_SOC_SAMSUNG=y -CONFIG_SND_SOC_RCAR=m -CONFIG_SND_SOC_RZ=m -CONFIG_SND_SUN4I_I2S=m -CONFIG_SND_SUN4I_SPDIF=m -CONFIG_SND_SOC_TEGRA=m -CONFIG_SND_SOC_TEGRA210_AHUB=m -CONFIG_SND_SOC_TEGRA210_DMIC=m -CONFIG_SND_SOC_TEGRA210_I2S=m -CONFIG_SND_SOC_TEGRA186_DSPK=m -CONFIG_SND_SOC_TEGRA210_ADMAIF=m -CONFIG_SND_SOC_TEGRA210_MVC=m -CONFIG_SND_SOC_TEGRA210_SFC=m -CONFIG_SND_SOC_TEGRA210_AMX=m -CONFIG_SND_SOC_TEGRA210_ADX=m -CONFIG_SND_SOC_TEGRA210_MIXER=m -CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m -CONFIG_SND_SOC_AK4613=m -CONFIG_SND_SOC_ES7134=m -CONFIG_SND_SOC_ES7241=m -CONFIG_SND_SOC_GTM601=m -CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m -CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -CONFIG_SND_SOC_PCM3168A_I2C=m -CONFIG_SND_SOC_RT5659=m -CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -CONFIG_SND_SOC_SIMPLE_MUX=m -CONFIG_SND_SOC_TAS571X=m -CONFIG_SND_SOC_TLV320AIC32X4_I2C=m -CONFIG_SND_SOC_WCD934X=m -CONFIG_SND_SOC_WM8904=m -CONFIG_SND_SOC_WM8960=m -CONFIG_SND_SOC_WM8962=m -CONFIG_SND_SOC_WM8978=m -CONFIG_SND_SOC_WSA881X=m -CONFIG_SND_SOC_LPASS_WSA_MACRO=m -CONFIG_SND_SOC_LPASS_VA_MACRO=m -CONFIG_SND_SIMPLE_CARD=m -CONFIG_SND_AUDIO_GRAPH_CARD=m -CONFIG_HID_MULTITOUCH=m -CONFIG_I2C_HID_ACPI=m -CONFIG_I2C_HID_OF=m -CONFIG_USB_CONN_GPIO=m -CONFIG_USB=y -CONFIG_USB_OTG=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PCI=m -CONFIG_USB_XHCI_PCI_RENESAS=m -CONFIG_USB_XHCI_TEGRA=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_EXYNOS=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_EXYNOS=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_RENESAS_USBHS_HCD=m -CONFIG_USB_RENESAS_USBHS=m -CONFIG_USB_ACM=m -CONFIG_USB_STORAGE=y -CONFIG_USB_MTU3=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SUNXI=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC2=y -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_ISP1760=y -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_HSIC_USB3503=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_GADGET=y -CONFIG_USB_RENESAS_USBHS_UDC=m -CONFIG_USB_RENESAS_USB3=m -CONFIG_USB_TEGRA_XUDC=m -CONFIG_USB_CONFIGFS=m -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_TYPEC=m -CONFIG_TYPEC_TCPM=m -CONFIG_TYPEC_TCPCI=m -CONFIG_TYPEC_FUSB302=m -CONFIG_TYPEC_HD3SS3220=m -CONFIG_TYPEC_TPS6598X=m -CONFIG_MMC=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ACPI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MMC_SDHCI_ESDHC_IMX=y -CONFIG_MMC_SDHCI_TEGRA=y -CONFIG_MMC_SDHCI_F_SDH30=y -CONFIG_MMC_MESON_GX=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_MMC_SPI=y -CONFIG_MMC_SDHI=y -CONFIG_MMC_UNIPHIER=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_EXYNOS=y -CONFIG_MMC_DW_HI3798CV200=y -CONFIG_MMC_DW_K3=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SUNXI=y -CONFIG_MMC_BCM2835=y -CONFIG_MMC_MTK=y -CONFIG_MMC_SDHCI_XENON=y -CONFIG_MMC_SDHCI_AM654=y -CONFIG_MMC_OWL=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_LM3692X=m -CONFIG_LEDS_PCA9532=m -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_EDAC=y -CONFIG_EDAC_GHES=y -CONFIG_EDAC_LAYERSCAPE=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=m -CONFIG_RTC_DRV_HYM8563=m -CONFIG_RTC_DRV_MAX77686=y -CONFIG_RTC_DRV_RK808=m -CONFIG_RTC_DRV_PCF85063=m -CONFIG_RTC_DRV_PCF85363=m -CONFIG_RTC_DRV_M41T80=m -CONFIG_RTC_DRV_RX8581=m -CONFIG_RTC_DRV_RV3028=m -CONFIG_RTC_DRV_RV8803=m -CONFIG_RTC_DRV_S5M=y -CONFIG_RTC_DRV_DS3232=y -CONFIG_RTC_DRV_PCF2127=m -CONFIG_RTC_DRV_EFI=y -CONFIG_RTC_DRV_CROS_EC=y -CONFIG_RTC_DRV_FSL_FTM_ALARM=m -CONFIG_RTC_DRV_S3C=y -CONFIG_RTC_DRV_PL031=y -CONFIG_RTC_DRV_SUN6I=y -CONFIG_RTC_DRV_ARMADA38X=y -CONFIG_RTC_DRV_PM8XXX=m -CONFIG_RTC_DRV_TEGRA=y -CONFIG_RTC_DRV_SNVS=m -CONFIG_RTC_DRV_IMX_SC=m -CONFIG_RTC_DRV_XGENE=y -CONFIG_DMADEVICES=y -CONFIG_DMA_BCM2835=y -CONFIG_DMA_SUN6I=m -CONFIG_FSL_EDMA=y -CONFIG_IMX_SDMA=y -CONFIG_K3_DMA=y -CONFIG_MV_XOR=y -CONFIG_MV_XOR_V2=y -CONFIG_OWL_DMA=y -CONFIG_PL330_DMA=y -CONFIG_TEGRA20_APB_DMA=y -CONFIG_TEGRA210_ADMA=m -CONFIG_QCOM_BAM_DMA=y -CONFIG_QCOM_HIDMA_MGMT=y -CONFIG_QCOM_HIDMA=y -CONFIG_RCAR_DMAC=y -CONFIG_RENESAS_USB_DMAC=m -CONFIG_RZ_DMAC=y -CONFIG_TI_K3_UDMA=y -CONFIG_TI_K3_UDMA_GLUE_LAYER=y -CONFIG_VFIO=y -CONFIG_VFIO_PCI=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_MMIO=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -CONFIG_MFD_CROS_EC_DEV=y -CONFIG_STAGING=y -CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_HANTRO=m -CONFIG_VIDEO_IMX_MEDIA=m -CONFIG_CHROME_PLATFORMS=y -CONFIG_CROS_EC=y -CONFIG_CROS_EC_I2C=y -CONFIG_CROS_EC_SPI=y -CONFIG_CROS_EC_CHARDEV=m -CONFIG_COMMON_CLK_SCMI=y -CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMMON_CLK_CS2000_CP=y -CONFIG_COMMON_CLK_FSL_SAI=y -CONFIG_COMMON_CLK_S2MPS11=y -CONFIG_COMMON_CLK_PWM=y -CONFIG_COMMON_CLK_VC5=y -CONFIG_COMMON_CLK_ZYNQMP=y -CONFIG_COMMON_CLK_BD718XX=m -CONFIG_CLK_RASPBERRYPI=m -CONFIG_CLK_IMX8MM=y -CONFIG_CLK_IMX8MN=y -CONFIG_CLK_IMX8MP=y -CONFIG_CLK_IMX8MQ=y -CONFIG_CLK_IMX8QXP=y -CONFIG_CLK_IMX8ULP=y -CONFIG_TI_SCI_CLK=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_QCOM_A53PLL=y -CONFIG_QCOM_CLK_APCS_MSM8916=y -CONFIG_QCOM_CLK_APCC_MSM8996=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_QCOM_CLK_RPMH=y -CONFIG_IPQ_GCC_8074=y -CONFIG_IPQ_GCC_6018=y -CONFIG_MSM_GCC_8916=y -CONFIG_MSM_GCC_8994=y -CONFIG_MSM_MMCC_8996=y -CONFIG_MSM_GCC_8998=y -CONFIG_QCS_GCC_404=y -CONFIG_SC_GCC_7180=y -CONFIG_SC_GCC_7280=y -CONFIG_SDM_CAMCC_845=m -CONFIG_SDM_GCC_845=y -CONFIG_SDM_GPUCC_845=y -CONFIG_SDM_VIDEOCC_845=y -CONFIG_SDM_DISPCC_845=y -CONFIG_SM_GCC_8150=y -CONFIG_SM_GCC_8250=y -CONFIG_SM_GCC_8350=y -CONFIG_SM_GPUCC_8150=y -CONFIG_SM_GPUCC_8250=y -CONFIG_SM_DISPCC_8250=y -CONFIG_QCOM_HFPLL=y -CONFIG_CLK_GFM_LPASS_SM8250=m -CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_ARM_MHU=y -CONFIG_IMX_MBOX=y -CONFIG_PLATFORM_MHU=y -CONFIG_BCM2835_MBOX=y -CONFIG_QCOM_APCS_IPC=y -CONFIG_QCOM_IPCC=y -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_TEGRA_IOMMU_SMMU=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_V3=y -CONFIG_MTK_IOMMU=y -CONFIG_QCOM_IOMMU=y -CONFIG_REMOTEPROC=y -CONFIG_QCOM_Q6V5_MSS=m -CONFIG_QCOM_Q6V5_PAS=m -CONFIG_QCOM_SYSMON=m -CONFIG_QCOM_WCNSS_PIL=m -CONFIG_RPMSG_CHAR=m -CONFIG_RPMSG_QCOM_GLINK_RPM=y -CONFIG_RPMSG_QCOM_GLINK_SMEM=m -CONFIG_RPMSG_QCOM_SMD=y -CONFIG_SOUNDWIRE=m -CONFIG_SOUNDWIRE_QCOM=m -CONFIG_OWL_PM_DOMAINS=y -CONFIG_RASPBERRYPI_POWER=y -CONFIG_FSL_DPAA=y -CONFIG_FSL_MC_DPIO=y -CONFIG_FSL_RCPM=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_QCOM_AOSS_QMP=y -CONFIG_QCOM_COMMAND_DB=y -CONFIG_QCOM_GENI_SE=y -CONFIG_QCOM_RMTFS_MEM=m -CONFIG_QCOM_RPMH=y -CONFIG_QCOM_RPMHPD=y -CONFIG_QCOM_RPMPD=y -CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_QCOM_SMP2P=y -CONFIG_QCOM_SMSM=y -CONFIG_QCOM_SOCINFO=m -CONFIG_QCOM_WCNSS_CTRL=m -CONFIG_QCOM_STATS=m -CONFIG_QCOM_APR=m -CONFIG_ARCH_R8A774A1=y -CONFIG_ARCH_R8A774B1=y -CONFIG_ARCH_R8A774C0=y -CONFIG_ARCH_R8A774E1=y -CONFIG_ARCH_R8A77950=y -CONFIG_ARCH_R8A77951=y -CONFIG_ARCH_R8A77960=y -CONFIG_ARCH_R8A77961=y -CONFIG_ARCH_R8A77965=y -CONFIG_ARCH_R8A77970=y -CONFIG_ARCH_R8A77980=y -CONFIG_ARCH_R8A77990=y -CONFIG_ARCH_R8A77995=y -CONFIG_ARCH_R8A779A0=y -CONFIG_ARCH_R8A779F0=y -CONFIG_ARCH_R9A07G044=y -CONFIG_ROCKCHIP_PM_DOMAINS=y -CONFIG_ARCH_TEGRA_132_SOC=y -CONFIG_ARCH_TEGRA_210_SOC=y -CONFIG_ARCH_TEGRA_186_SOC=y -CONFIG_ARCH_TEGRA_194_SOC=y -CONFIG_ARCH_TEGRA_234_SOC=y -CONFIG_TI_SCI_PM_DOMAINS=y -CONFIG_ARM_IMX_BUS_DEVFREQ=m -CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m -CONFIG_EXTCON_PTN5150=m -CONFIG_EXTCON_USB_GPIO=y -CONFIG_EXTCON_USBC_CROS_EC=y -CONFIG_RENESAS_RPCIF=m -CONFIG_IIO=y -CONFIG_EXYNOS_ADC=y -CONFIG_MAX9611=m -CONFIG_QCOM_SPMI_VADC=m -CONFIG_QCOM_SPMI_ADC5=m -CONFIG_ROCKCHIP_SARADC=m -CONFIG_RZG2L_ADC=m -CONFIG_IIO_CROS_EC_SENSORS_CORE=m -CONFIG_IIO_CROS_EC_SENSORS=m -CONFIG_IIO_ST_LSM6DSX=m -CONFIG_IIO_CROS_EC_LIGHT_PROX=m -CONFIG_SENSORS_ISL29018=m -CONFIG_VCNL4000=m -CONFIG_IIO_ST_MAGN_3AXIS=m -CONFIG_IIO_CROS_EC_BARO=m -CONFIG_MPL3115=m -CONFIG_PWM=y -CONFIG_PWM_BCM2835=m -CONFIG_PWM_CROS_EC=m -CONFIG_PWM_IMX27=m -CONFIG_PWM_MESON=m -CONFIG_PWM_MTK_DISP=m -CONFIG_PWM_MEDIATEK=m -CONFIG_PWM_RCAR=m -CONFIG_PWM_RENESAS_TPU=m -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_SAMSUNG=y -CONFIG_PWM_SL28CPLD=m -CONFIG_PWM_SUN4I=m -CONFIG_PWM_TEGRA=m -CONFIG_PWM_VISCONTI=m -CONFIG_SL28CPLD_INTC=y -CONFIG_QCOM_PDC=y -CONFIG_RESET_IMX7=y -CONFIG_RESET_QCOM_AOSS=y -CONFIG_RESET_QCOM_PDC=m -CONFIG_RESET_RZG2L_USBPHY_CTRL=y -CONFIG_RESET_TI_SCI=y -CONFIG_PHY_XGENE=y -CONFIG_PHY_SUN4I_USB=y -CONFIG_PHY_MIXEL_MIPI_DPHY=m -CONFIG_PHY_HI6220_USB=y -CONFIG_PHY_HISTB_COMBPHY=y -CONFIG_PHY_HISI_INNO_USB2=y -CONFIG_PHY_MVEBU_CP110_COMPHY=y -CONFIG_PHY_MTK_TPHY=y -CONFIG_PHY_QCOM_QMP=m -CONFIG_PHY_QCOM_QUSB2=m -CONFIG_PHY_QCOM_USB_HS=y -CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y -CONFIG_PHY_RCAR_GEN3_PCIE=y -CONFIG_PHY_RCAR_GEN3_USB2=y -CONFIG_PHY_RCAR_GEN3_USB3=m -CONFIG_PHY_ROCKCHIP_EMMC=y -CONFIG_PHY_ROCKCHIP_INNO_HDMI=m -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m -CONFIG_PHY_ROCKCHIP_PCIE=m -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_SAMSUNG_UFS=y -CONFIG_PHY_UNIPHIER_USB2=y -CONFIG_PHY_UNIPHIER_USB3=y -CONFIG_PHY_TEGRA_XUSB=y -CONFIG_ARM_SMMU_V3_PMU=m -CONFIG_FSL_IMX8_DDR_PMU=m -CONFIG_HISI_PMU=y -CONFIG_QCOM_L2_PMU=y -CONFIG_QCOM_L3_PMU=y -CONFIG_NVMEM_IMX_OCOTP=y -CONFIG_NVMEM_IMX_OCOTP_SCU=y -CONFIG_QCOM_QFPROM=y -CONFIG_MTK_EFUSE=y -CONFIG_ROCKCHIP_EFUSE=y -CONFIG_NVMEM_SUNXI_SID=y -CONFIG_UNIPHIER_EFUSE=y -CONFIG_MESON_EFUSE=m -CONFIG_NVMEM_RMEM=m -CONFIG_FPGA=y -CONFIG_FPGA_MGR_STRATIX10_SOC=m -CONFIG_FPGA_BRIDGE=m -CONFIG_ALTERA_FREEZE_BRIDGE=m -CONFIG_FPGA_REGION=m -CONFIG_OF_FPGA_REGION=m -CONFIG_TEE=y -CONFIG_OPTEE=y -CONFIG_SLIMBUS=m -CONFIG_SLIM_QCOM_CTRL=m -CONFIG_SLIM_QCOM_NGD_CTRL=m -CONFIG_MUX_MMIO=y -CONFIG_INTERCONNECT=y -CONFIG_INTERCONNECT_IMX=m -CONFIG_INTERCONNECT_IMX8MM=m -CONFIG_INTERCONNECT_IMX8MN=m -CONFIG_INTERCONNECT_IMX8MQ=m -CONFIG_INTERCONNECT_QCOM=y -CONFIG_INTERCONNECT_QCOM_MSM8916=m -CONFIG_INTERCONNECT_QCOM_OSM_L3=m -CONFIG_INTERCONNECT_QCOM_SC7280=y -CONFIG_INTERCONNECT_QCOM_QCS404=m -CONFIG_INTERCONNECT_QCOM_SDM845=y -CONFIG_INTERCONNECT_QCOM_SM8150=m -CONFIG_INTERCONNECT_QCOM_SM8250=m -CONFIG_INTERCONNECT_QCOM_SM8350=m -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_BTRFS_FS=m -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_FANOTIFY=y -CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_QUOTA=y -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=m -CONFIG_CUSE=m -CONFIG_OVERLAY_FS=m -CONFIG_VFAT_FS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_HUGETLBFS=y -CONFIG_CONFIGFS_FS=y -CONFIG_EFIVAR_FS=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_ROOT_NFS=y -CONFIG_9P_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_USER_API_RNG=m -CONFIG_CRYPTO_DEV_SUN8I_CE=m -CONFIG_CRYPTO_DEV_FSL_CAAM=m -CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m -CONFIG_CRYPTO_DEV_QCOM_RNG=m -CONFIG_CRYPTO_DEV_CCREE=m -CONFIG_CRYPTO_DEV_HISI_SEC2=m -CONFIG_CRYPTO_DEV_HISI_ZIP=m -CONFIG_CRYPTO_DEV_HISI_HPRE=m -CONFIG_CRYPTO_DEV_HISI_TRNG=m -CONFIG_CMA_SIZE_MBYTES=32 -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_INFO_REDUCED=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_FTRACE is not set -CONFIG_MEMTEST=y diff --git a/rr-cache/f93bd68f8905ee72aa0a339525fd22c07d672dd9/preimage b/rr-cache/f93bd68f8905ee72aa0a339525fd22c07d672dd9/preimage deleted file mode 100644 index a04c6c4..0000000 --- a/rr-cache/f93bd68f8905ee72aa0a339525fd22c07d672dd9/preimage +++ /dev/null @@ -1,1253 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_NUMA_BALANCING=y -CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_HUGETLB=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_USER_NS=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_ARCH_ACTIONS=y -CONFIG_ARCH_SUNXI=y -CONFIG_ARCH_ALPINE=y -CONFIG_ARCH_APPLE=y -CONFIG_ARCH_BCM2835=y -CONFIG_ARCH_BCM4908=y -CONFIG_ARCH_BCM_IPROC=y -CONFIG_ARCH_BERLIN=y -CONFIG_ARCH_BRCMSTB=y -CONFIG_ARCH_EXYNOS=y -CONFIG_ARCH_K3=y -CONFIG_ARCH_LAYERSCAPE=y -CONFIG_ARCH_LG1K=y -CONFIG_ARCH_HISI=y -CONFIG_ARCH_KEEMBAY=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MESON=y -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_MXC=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_RENESAS=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_S32=y -CONFIG_ARCH_SEATTLE=y -CONFIG_ARCH_INTEL_SOCFPGA=y -CONFIG_ARCH_SYNQUACER=y -CONFIG_ARCH_TEGRA=y -CONFIG_ARCH_SPRD=y -CONFIG_ARCH_THUNDER=y -CONFIG_ARCH_THUNDER2=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_ARCH_VEXPRESS=y -CONFIG_ARCH_VISCONTI=y -CONFIG_ARCH_XGENE=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_ARM64_VA_BITS_48=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_SMT=y -CONFIG_NUMA=y -CONFIG_SECCOMP=y -CONFIG_KEXEC=y -CONFIG_KEXEC_FILE=y -CONFIG_CRASH_DUMP=y -CONFIG_XEN=y -CONFIG_COMPAT=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_HIBERNATION=y -CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -CONFIG_ENERGY_MODEL=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPUFREQ_DT=y -CONFIG_ACPI_CPPC_CPUFREQ=m -CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m -CONFIG_ARM_ARMADA_37XX_CPUFREQ=y -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_IMX_CPUFREQ_DT=m -CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y -CONFIG_ARM_QCOM_CPUFREQ_HW=y -CONFIG_ARM_RASPBERRYPI_CPUFREQ=m -CONFIG_ARM_SCMI_CPUFREQ=y -CONFIG_ARM_TEGRA186_CPUFREQ=y -CONFIG_QORIQ_CPUFREQ=y -CONFIG_ARM_SCMI_PROTOCOL=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_RASPBERRYPI_FIRMWARE=y -CONFIG_INTEL_STRATIX10_SERVICE=y -CONFIG_INTEL_STRATIX10_RSU=m -CONFIG_QCOM_SCM=y -CONFIG_EFI_CAPSULE_LOADER=y -CONFIG_IMX_SCU=y -CONFIG_IMX_SCU_PD=y -CONFIG_ACPI=y -CONFIG_ACPI_APEI=y -CONFIG_ACPI_APEI_GHES=y -CONFIG_ACPI_APEI_PCIEAER=y -CONFIG_ACPI_APEI_MEMORY_FAILURE=y -CONFIG_ACPI_APEI_EINJ=y -CONFIG_VIRTUALIZATION=y -CONFIG_KVM=y -CONFIG_ARM64_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64_CE=m -CONFIG_CRYPTO_SHA3_ARM64=m -CONFIG_CRYPTO_SM3_ARM64_CE=m -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_AES_ARM64_BS=m -CONFIG_JUMP_LABEL=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_KSM=y -CONFIG_MEMORY_FAILURE=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=m -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_NET_DSA=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBS=m -CONFIG_NET_SCH_ETF=m -CONFIG_NET_SCH_TAPRIO=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_GACT=m -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_GATE=m -CONFIG_QRTR=m -CONFIG_QRTR_SMD=m -CONFIG_QRTR_TUN=m -CONFIG_BPF_JIT=y -CONFIG_CAN=m -CONFIG_CAN_RCAR=m -CONFIG_CAN_RCAR_CANFD=m -CONFIG_CAN_FLEXCAN=m -CONFIG_BT=m -CONFIG_BT_HIDP=m -# CONFIG_BT_HS is not set -# CONFIG_BT_LE is not set -CONFIG_BT_LEDS=y -# CONFIG_BT_DEBUGFS is not set -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HCIUART_QCA=y -CONFIG_BT_QCOMSMD=m -CONFIG_CFG80211=m -CONFIG_MAC80211=m -CONFIG_MAC80211_LEDS=y -CONFIG_RFKILL=m -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y -CONFIG_NFC=m -CONFIG_NFC_NCI=m -CONFIG_NFC_S3FWRN5_I2C=m -CONFIG_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCI_IOV=y -CONFIG_PCI_PASID=y -CONFIG_HOTPLUG_PCI=y -CONFIG_HOTPLUG_PCI_ACPI=y -CONFIG_PCI_AARDVARK=y -CONFIG_PCI_TEGRA=y -CONFIG_PCIE_RCAR_HOST=y -CONFIG_PCIE_RCAR_EP=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCI_XGENE=y -CONFIG_PCIE_ALTERA=y -CONFIG_PCIE_ALTERA_MSI=y -CONFIG_PCI_HOST_THUNDER_PEM=y -CONFIG_PCI_HOST_THUNDER_ECAM=y -CONFIG_PCIE_ROCKCHIP_HOST=m -CONFIG_PCIE_BRCMSTB=m -CONFIG_PCI_IMX6=y -CONFIG_PCI_LAYERSCAPE=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y -CONFIG_PCI_HISI=y -CONFIG_PCIE_QCOM=y -CONFIG_PCIE_ARMADA_8K=y -CONFIG_PCIE_KIRIN=y -CONFIG_PCIE_HISI_STB=y -CONFIG_PCIE_TEGRA194_HOST=m -CONFIG_PCIE_VISCONTI_HOST=y -CONFIG_PCI_ENDPOINT=y -CONFIG_PCI_ENDPOINT_CONFIGFS=y -CONFIG_PCI_EPF_TEST=m -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_HISILICON_LPC=y -CONFIG_FSL_MC_BUS=y -CONFIG_TEGRA_ACONNECT=m -CONFIG_GNSS=m -CONFIG_GNSS_MTK_SERIAL=m -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_SST25L=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_DENALI_DT=y -CONFIG_MTD_NAND_MARVELL=y -CONFIG_MTD_NAND_FSL_IFC=y -CONFIG_MTD_NAND_QCOM=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTK_DEVAPC=m -CONFIG_SPI_CADENCE_QUADSPI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=m -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_NVME=m -CONFIG_SRAM=y -CONFIG_PCI_ENDPOINT_TEST=m -CONFIG_EEPROM_AT24=m -CONFIG_EEPROM_AT25=m -CONFIG_UACCE=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_SAS_ATA=y -CONFIG_SCSI_HISI_SAS=y -CONFIG_SCSI_HISI_SAS_PCI=y -CONFIG_MEGARAID_SAS=y -CONFIG_SCSI_MPT3SAS=m -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=m -CONFIG_SCSI_UFS_HISI=y -CONFIG_SCSI_UFS_EXYNOS=y -CONFIG_ATA=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_AHCI_CEVA=y -CONFIG_AHCI_MVEBU=y -CONFIG_AHCI_XGENE=y -CONFIG_AHCI_QORIQ=y -CONFIG_SATA_SIL24=y -CONFIG_SATA_RCAR=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_OF_PLATFORM=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_NETDEVICES=y -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_TUN=y -CONFIG_VETH=m -CONFIG_VIRTIO_NET=y -CONFIG_NET_DSA_MSCC_FELIX=m -CONFIG_AMD_XGBE=y -CONFIG_NET_XGENE=y -CONFIG_ATL1C=m -CONFIG_BCMGENET=m -CONFIG_BNX2X=m -CONFIG_MACB=y -CONFIG_THUNDER_NIC_PF=y -CONFIG_FEC=y -CONFIG_FSL_FMAN=y -CONFIG_FSL_DPAA_ETH=y -CONFIG_FSL_DPAA2_ETH=y -CONFIG_FSL_ENETC=y -CONFIG_FSL_ENETC_VF=y -CONFIG_FSL_ENETC_QOS=y -CONFIG_HIX5HD2_GMAC=y -CONFIG_HNS_DSAF=y -CONFIG_HNS_ENET=y -CONFIG_HNS3=y -CONFIG_HNS3_HCLGE=y -CONFIG_HNS3_ENET=y -CONFIG_E1000=y -CONFIG_E1000E=y -CONFIG_IGB=y -CONFIG_IGBVF=y -CONFIG_MVNETA=y -CONFIG_MVPP2=y -CONFIG_SKY2=y -CONFIG_MLX4_EN=m -CONFIG_MLX5_CORE=m -CONFIG_MLX5_CORE_EN=y -CONFIG_QCOM_EMAC=m -CONFIG_RMNET=m -CONFIG_SH_ETH=y -CONFIG_RAVB=y -CONFIG_SMC91X=y -CONFIG_SMSC911X=y -CONFIG_SNI_AVE=y -CONFIG_SNI_NETSEC=y -CONFIG_STMMAC_ETH=m -CONFIG_TI_K3_AM65_CPSW_NUSS=y -CONFIG_QCOM_IPA=m -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -CONFIG_AQUANTIA_PHY=y -CONFIG_BCM54140_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_MARVELL_10G_PHY=m -CONFIG_MESON_GXL_PHY=m -CONFIG_MICREL_PHY=y -CONFIG_MICROSEMI_PHY=y -CONFIG_AT803X_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_ROCKCHIP_PHY=y -CONFIG_DP83867_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9800=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_ATH10K_SNOC=m -CONFIG_WCN36XX=m -CONFIG_BRCMFMAC=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_PCIE=m -CONFIG_WL18XX=m -CONFIG_WLCORE_SDIO=m -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_ADC=m -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_SNVS_PWRKEY=m -CONFIG_KEYBOARD_IMX_SC_KEY=m -CONFIG_KEYBOARD_CROS_EC=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=m -CONFIG_TOUCHSCREEN_GOODIX=m -CONFIG_TOUCHSCREEN_EDT_FT5X06=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_PM8941_PWRKEY=y -CONFIG_INPUT_PM8XXX_VIBRATOR=m -CONFIG_INPUT_PWM_BEEPER=m -CONFIG_INPUT_PWM_VIBRA=m -CONFIG_INPUT_HISI_POWERKEY=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIO_AMBAKMI=y -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_BCM2835AUX=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_OMAP=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_UNIPHIER=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_MESON=y -CONFIG_SERIAL_MESON_CONSOLE=y -CONFIG_SERIAL_SAMSUNG=y -CONFIG_SERIAL_SAMSUNG_CONSOLE=y -CONFIG_SERIAL_TEGRA=y -CONFIG_SERIAL_TEGRA_TCU=y -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SERIAL_QCOM_GENI=y -CONFIG_SERIAL_QCOM_GENI_CONSOLE=y -CONFIG_SERIAL_XILINX_PS_UART=y -CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -CONFIG_SERIAL_FSL_LPUART=y -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -CONFIG_SERIAL_FSL_LINFLEXUART=y -CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -CONFIG_SERIAL_MVEBU_UART=y -CONFIG_SERIAL_OWL=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_IPMI_HANDLER=m -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SI=m -CONFIG_TCG_TPM=y -CONFIG_TCG_TIS_I2C_INFINEON=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_I2C_BCM2835=m -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_I2C_GPIO=m -CONFIG_I2C_IMX=y -CONFIG_I2C_IMX_LPI2C=y -CONFIG_I2C_MESON=y -CONFIG_I2C_MT65XX=y -CONFIG_I2C_MV64XXX=y -CONFIG_I2C_OMAP=y -CONFIG_I2C_OWL=y -CONFIG_I2C_PXA=y -CONFIG_I2C_QCOM_CCI=m -CONFIG_I2C_QCOM_GENI=m -CONFIG_I2C_QUP=y -CONFIG_I2C_RIIC=y -CONFIG_I2C_RK3X=y -CONFIG_I2C_S3C2410=y -CONFIG_I2C_SH_MOBILE=y -CONFIG_I2C_TEGRA=y -CONFIG_I2C_UNIPHIER_F=y -CONFIG_I2C_RCAR=y -CONFIG_I2C_CROS_EC_TUNNEL=y -CONFIG_SPI=y -CONFIG_SPI_ARMADA_3700=y -CONFIG_SPI_BCM2835=m -CONFIG_SPI_BCM2835AUX=m -CONFIG_SPI_DESIGNWARE=m -CONFIG_SPI_DW_DMA=y -CONFIG_SPI_DW_MMIO=m -CONFIG_SPI_FSL_LPSPI=y -CONFIG_SPI_FSL_QUADSPI=y -CONFIG_SPI_NXP_FLEXSPI=y -CONFIG_SPI_IMX=m -CONFIG_SPI_FSL_DSPI=y -CONFIG_SPI_MESON_SPICC=m -CONFIG_SPI_MESON_SPIFC=m -CONFIG_SPI_ORION=y -CONFIG_SPI_PL022=y -CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_RPCIF=m -CONFIG_SPI_QCOM_QSPI=m -CONFIG_SPI_QUP=y -CONFIG_SPI_QCOM_GENI=m -CONFIG_SPI_S3C64XX=y -CONFIG_SPI_SH_MSIOF=m -CONFIG_SPI_SUN6I=y -CONFIG_SPI_SPIDEV=m -CONFIG_SPMI=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_PINCTRL_MAX77620=y -CONFIG_PINCTRL_OWL=y -CONFIG_PINCTRL_S700=y -CONFIG_PINCTRL_S900=y -CONFIG_PINCTRL_IMX8MM=y -CONFIG_PINCTRL_IMX8MN=y -CONFIG_PINCTRL_IMX8MP=y -CONFIG_PINCTRL_IMX8MQ=y -CONFIG_PINCTRL_IMX8QM=y -CONFIG_PINCTRL_IMX8QXP=y -CONFIG_PINCTRL_IMX8DXL=y -CONFIG_PINCTRL_IMX8ULP=y -CONFIG_PINCTRL_MSM=y -CONFIG_PINCTRL_IPQ8074=y -CONFIG_PINCTRL_IPQ6018=y -CONFIG_PINCTRL_MSM8916=y -CONFIG_PINCTRL_MSM8994=y -CONFIG_PINCTRL_MSM8996=y -CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_QCS404=y -CONFIG_PINCTRL_QDF2XXX=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -CONFIG_PINCTRL_SC7180=y -CONFIG_PINCTRL_SC7280=y -CONFIG_PINCTRL_SDM845=y -CONFIG_PINCTRL_SM8150=y -CONFIG_PINCTRL_SM8250=y -CONFIG_PINCTRL_SM8350=y -CONFIG_PINCTRL_LPASS_LPI=m -CONFIG_GPIO_ALTERA=m -CONFIG_GPIO_DAVINCI=y -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_MB86S7X=y -CONFIG_GPIO_MPC8XXX=y -CONFIG_GPIO_MXC=y -CONFIG_GPIO_PL061=y -CONFIG_GPIO_RCAR=y -CONFIG_GPIO_UNIPHIER=y -CONFIG_GPIO_VISCONTI=y -CONFIG_GPIO_WCD934X=m -CONFIG_GPIO_XGENE=y -CONFIG_GPIO_XGENE_SB=y -CONFIG_GPIO_MAX732X=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_BD9571MWV=m -CONFIG_GPIO_MAX77620=y -CONFIG_GPIO_SL28CPLD=m -CONFIG_POWER_AVS=y -CONFIG_QCOM_CPR=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_RESET_QCOM_PON=m -CONFIG_POWER_RESET_XGENE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_SYSCON_REBOOT_MODE=y -CONFIG_BATTERY_SBS=m -CONFIG_BATTERY_BQ27XXX=y -CONFIG_SENSORS_ARM_SCMI=y -CONFIG_BATTERY_MAX17042=m -CONFIG_CHARGER_BQ25890=m -CONFIG_CHARGER_BQ25980=m -CONFIG_SENSORS_ARM_SCPI=y -CONFIG_SENSORS_JC42=m -CONFIG_SENSORS_LM90=m -CONFIG_SENSORS_PWM_FAN=m -CONFIG_SENSORS_RASPBERRYPI_HWMON=m -CONFIG_SENSORS_SL28CPLD=m -CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_INA3221=m -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_CPU_THERMAL=y -CONFIG_THERMAL_EMULATION=y -CONFIG_QORIQ_THERMAL=m -CONFIG_SUN8I_THERMAL=y -CONFIG_IMX_SC_THERMAL=m -CONFIG_IMX8MM_THERMAL=m -CONFIG_ROCKCHIP_THERMAL=m -CONFIG_RCAR_THERMAL=y -CONFIG_RCAR_GEN3_THERMAL=y -CONFIG_ARMADA_THERMAL=y -CONFIG_BCM2711_THERMAL=m -CONFIG_BCM2835_THERMAL=m -CONFIG_BRCMSTB_THERMAL=m -CONFIG_EXYNOS_THERMAL=y -CONFIG_TEGRA_BPMP_THERMAL=m -CONFIG_TEGRA_SOCTHERM=m -CONFIG_QCOM_TSENS=y -CONFIG_QCOM_SPMI_TEMP_ALARM=m -CONFIG_QCOM_LMH=m -CONFIG_UNIPHIER_THERMAL=y -CONFIG_WATCHDOG=y -CONFIG_SL28CPLD_WATCHDOG=m -CONFIG_ARM_SP805_WATCHDOG=y -CONFIG_ARM_SBSA_WATCHDOG=y -CONFIG_ARM_SMC_WATCHDOG=y -CONFIG_S3C2410_WATCHDOG=y -CONFIG_DW_WATCHDOG=y -CONFIG_SUNXI_WATCHDOG=m -CONFIG_IMX2_WDT=y -CONFIG_IMX_SC_WDT=m -CONFIG_QCOM_WDT=m -CONFIG_MESON_GXBB_WATCHDOG=m -CONFIG_MESON_WATCHDOG=m -CONFIG_RENESAS_WDT=y -CONFIG_UNIPHIER_WATCHDOG=y -CONFIG_BCM2835_WDT=y -CONFIG_MFD_ALTERA_SYSMGR=y -CONFIG_MFD_BD9571MWV=y -CONFIG_MFD_AXP20X_I2C=y -CONFIG_MFD_AXP20X_RSB=y -CONFIG_MFD_EXYNOS_LPASS=m -CONFIG_MFD_HI6421_PMIC=y -CONFIG_MFD_HI655X_PMIC=y -CONFIG_MFD_MAX77620=y -CONFIG_MFD_MT6397=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_MFD_RK808=y -CONFIG_MFD_SEC_CORE=y -CONFIG_MFD_SL28CPLD=y -CONFIG_MFD_ROHM_BD718XX=y -CONFIG_MFD_WCD934X=m -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_AXP20X=y -CONFIG_REGULATOR_BD718XX=y -CONFIG_REGULATOR_BD9571MWV=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_HI6421V530=y -CONFIG_REGULATOR_HI655X=y -CONFIG_REGULATOR_MAX77620=y -CONFIG_REGULATOR_MAX8973=y -CONFIG_REGULATOR_MP8859=y -CONFIG_REGULATOR_MT6358=y -CONFIG_REGULATOR_MT6397=y -CONFIG_REGULATOR_PCA9450=y -CONFIG_REGULATOR_PF8X00=y -CONFIG_REGULATOR_PFUZE100=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_QCOM_RPMH=y -CONFIG_REGULATOR_QCOM_SMD_RPM=y -CONFIG_REGULATOR_QCOM_SPMI=y -CONFIG_REGULATOR_RK808=y -CONFIG_REGULATOR_S2MPS11=y -CONFIG_REGULATOR_TPS65132=m -CONFIG_REGULATOR_VCTRL=m -CONFIG_RC_CORE=m -CONFIG_RC_DECODERS=y -CONFIG_RC_DEVICES=y -CONFIG_IR_MESON=m -CONFIG_IR_SUNXI=m -CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y -# CONFIG_DVB_NET is not set -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VIDEO_RCAR_CSI2=m -CONFIG_VIDEO_RCAR_VIN=m -CONFIG_VIDEO_SUN6I_CSI=m -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m -CONFIG_VIDEO_SAMSUNG_S5P_MFC=m -CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m -CONFIG_VIDEO_RENESAS_FDP1=m -CONFIG_VIDEO_RENESAS_FCP=m -CONFIG_VIDEO_RENESAS_VSP1=m -CONFIG_VIDEO_QCOM_VENUS=m -CONFIG_SDR_PLATFORM_DRIVERS=y -CONFIG_VIDEO_RCAR_DRIF=m -CONFIG_VIDEO_IMX219=m -CONFIG_VIDEO_OV5640=m -CONFIG_VIDEO_OV5645=m -CONFIG_VIDEO_QCOM_CAMSS=m -CONFIG_DRM=m -CONFIG_DRM_I2C_NXP_TDA998X=m -CONFIG_DRM_MALI_DISPLAY=m -CONFIG_DRM_NOUVEAU=m -CONFIG_DRM_EXYNOS=m -CONFIG_DRM_EXYNOS5433_DECON=y -CONFIG_DRM_EXYNOS7_DECON=y -CONFIG_DRM_EXYNOS_DSI=y -# CONFIG_DRM_EXYNOS_DP is not set -CONFIG_DRM_EXYNOS_HDMI=y -CONFIG_DRM_EXYNOS_MIC=y -CONFIG_DRM_ROCKCHIP=m -CONFIG_ROCKCHIP_ANALOGIX_DP=y -CONFIG_ROCKCHIP_CDN_DP=y -CONFIG_ROCKCHIP_DW_HDMI=y -CONFIG_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_ROCKCHIP_INNO_HDMI=y -CONFIG_ROCKCHIP_LVDS=y -CONFIG_DRM_RCAR_DU=m -CONFIG_DRM_RCAR_DW_HDMI=m -CONFIG_DRM_SUN4I=m -CONFIG_DRM_SUN6I_DSI=m -CONFIG_DRM_SUN8I_DW_HDMI=m -CONFIG_DRM_SUN8I_MIXER=m -CONFIG_DRM_MSM=m -CONFIG_DRM_TEGRA=m -CONFIG_DRM_PANEL_LVDS=m -CONFIG_DRM_PANEL_SIMPLE=m -CONFIG_DRM_PANEL_EDP=m -CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m -CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m -CONFIG_DRM_PANEL_RAYDIUM_RM67191=m -CONFIG_DRM_PANEL_SITRONIX_ST7703=m -CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m -CONFIG_DRM_DISPLAY_CONNECTOR=m -CONFIG_DRM_LONTIUM_LT8912B=m -CONFIG_DRM_NWL_MIPI_DSI=m -CONFIG_DRM_LONTIUM_LT9611=m -CONFIG_DRM_PARADE_PS8640=m -CONFIG_DRM_SII902X=m -CONFIG_DRM_SIMPLE_BRIDGE=m -CONFIG_DRM_THINE_THC63LVD1024=m -CONFIG_DRM_TI_SN65DSI86=m -CONFIG_DRM_LONTIUM_LT9611UXC=m -CONFIG_DRM_I2C_ADV7511=m -CONFIG_DRM_I2C_ADV7511_AUDIO=y -CONFIG_DRM_DW_HDMI_AHB_AUDIO=m -CONFIG_DRM_DW_HDMI_CEC=m -CONFIG_DRM_IMX_DCSS=m -CONFIG_DRM_VC4=m -CONFIG_DRM_ETNAVIV=m -CONFIG_DRM_HISI_HIBMC=m -CONFIG_DRM_HISI_KIRIN=m -CONFIG_DRM_MEDIATEK=m -CONFIG_DRM_MEDIATEK_HDMI=m -CONFIG_DRM_MXSFB=m -CONFIG_DRM_MESON=m -CONFIG_DRM_PL111=m -CONFIG_DRM_LIMA=m -CONFIG_DRM_PANFROST=m -CONFIG_FB=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_EFI=y -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_LP855X=m -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_HDA_TEGRA=m -CONFIG_SND_HDA_CODEC_HDMI=m -CONFIG_SND_SOC=y -CONFIG_SND_BCM2835_SOC_I2S=m -CONFIG_SND_SOC_FSL_SAI=m -CONFIG_SND_SOC_FSL_ASRC=m -CONFIG_SND_SOC_FSL_MICFIL=m -CONFIG_SND_SOC_FSL_EASRC=m -CONFIG_SND_IMX_SOC=m -CONFIG_SND_SOC_IMX_SGTL5000=m -CONFIG_SND_SOC_IMX_SPDIF=m -CONFIG_SND_SOC_IMX_AUDMIX=m -CONFIG_SND_SOC_FSL_ASOC_CARD=m -CONFIG_SND_MESON_AXG_SOUND_CARD=m -CONFIG_SND_MESON_GX_SOUND_CARD=m -CONFIG_SND_SOC_QCOM=m -CONFIG_SND_SOC_APQ8016_SBC=m -CONFIG_SND_SOC_MSM8996=m -CONFIG_SND_SOC_SDM845=m -CONFIG_SND_SOC_SM8250=m -CONFIG_SND_SOC_ROCKCHIP=m -CONFIG_SND_SOC_ROCKCHIP_SPDIF=m -CONFIG_SND_SOC_ROCKCHIP_RT5645=m -CONFIG_SND_SOC_RK3399_GRU_SOUND=m -CONFIG_SND_SOC_SAMSUNG=y -CONFIG_SND_SOC_RCAR=m -CONFIG_SND_SOC_RZ=m -CONFIG_SND_SUN4I_I2S=m -CONFIG_SND_SUN4I_SPDIF=m -CONFIG_SND_SOC_TEGRA=m -CONFIG_SND_SOC_TEGRA210_AHUB=m -CONFIG_SND_SOC_TEGRA210_DMIC=m -CONFIG_SND_SOC_TEGRA210_I2S=m -CONFIG_SND_SOC_TEGRA186_DSPK=m -CONFIG_SND_SOC_TEGRA210_ADMAIF=m -CONFIG_SND_SOC_TEGRA210_MVC=m -CONFIG_SND_SOC_TEGRA210_SFC=m -CONFIG_SND_SOC_TEGRA210_AMX=m -CONFIG_SND_SOC_TEGRA210_ADX=m -CONFIG_SND_SOC_TEGRA210_MIXER=m -CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m -CONFIG_SND_SOC_AK4613=m -CONFIG_SND_SOC_ES7134=m -CONFIG_SND_SOC_ES7241=m -CONFIG_SND_SOC_GTM601=m -CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m -CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -CONFIG_SND_SOC_PCM3168A_I2C=m -CONFIG_SND_SOC_RT5659=m -CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -CONFIG_SND_SOC_SIMPLE_MUX=m -CONFIG_SND_SOC_TAS571X=m -CONFIG_SND_SOC_TLV320AIC32X4_I2C=m -CONFIG_SND_SOC_WCD934X=m -CONFIG_SND_SOC_WM8904=m -CONFIG_SND_SOC_WM8960=m -CONFIG_SND_SOC_WM8962=m -CONFIG_SND_SOC_WM8978=m -CONFIG_SND_SOC_WSA881X=m -CONFIG_SND_SOC_LPASS_WSA_MACRO=m -CONFIG_SND_SOC_LPASS_VA_MACRO=m -CONFIG_SND_SIMPLE_CARD=m -CONFIG_SND_AUDIO_GRAPH_CARD=m -CONFIG_HID_MULTITOUCH=m -CONFIG_I2C_HID_ACPI=m -CONFIG_I2C_HID_OF=m -CONFIG_USB_CONN_GPIO=m -CONFIG_USB=y -CONFIG_USB_OTG=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PCI=m -CONFIG_USB_XHCI_PCI_RENESAS=m -CONFIG_USB_XHCI_TEGRA=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_EXYNOS=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_EXYNOS=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_RENESAS_USBHS_HCD=m -CONFIG_USB_RENESAS_USBHS=m -CONFIG_USB_ACM=m -CONFIG_USB_STORAGE=y -CONFIG_USB_MTU3=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SUNXI=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC2=y -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_ISP1760=y -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_HSIC_USB3503=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_GADGET=y -CONFIG_USB_RENESAS_USBHS_UDC=m -CONFIG_USB_RENESAS_USB3=m -CONFIG_USB_TEGRA_XUDC=m -CONFIG_USB_CONFIGFS=m -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_TYPEC=m -CONFIG_TYPEC_TCPM=m -CONFIG_TYPEC_TCPCI=m -CONFIG_TYPEC_FUSB302=m -CONFIG_TYPEC_HD3SS3220=m -CONFIG_TYPEC_TPS6598X=m -CONFIG_MMC=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ACPI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MMC_SDHCI_ESDHC_IMX=y -CONFIG_MMC_SDHCI_TEGRA=y -CONFIG_MMC_SDHCI_F_SDH30=y -CONFIG_MMC_MESON_GX=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_MMC_SPI=y -CONFIG_MMC_SDHI=y -CONFIG_MMC_UNIPHIER=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_EXYNOS=y -CONFIG_MMC_DW_HI3798CV200=y -CONFIG_MMC_DW_K3=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SUNXI=y -CONFIG_MMC_BCM2835=y -CONFIG_MMC_MTK=y -CONFIG_MMC_SDHCI_XENON=y -CONFIG_MMC_SDHCI_AM654=y -CONFIG_MMC_OWL=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_LM3692X=m -CONFIG_LEDS_PCA9532=m -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_EDAC=y -CONFIG_EDAC_GHES=y -CONFIG_EDAC_LAYERSCAPE=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=m -CONFIG_RTC_DRV_HYM8563=m -CONFIG_RTC_DRV_MAX77686=y -CONFIG_RTC_DRV_RK808=m -CONFIG_RTC_DRV_PCF85063=m -CONFIG_RTC_DRV_PCF85363=m -CONFIG_RTC_DRV_M41T80=m -CONFIG_RTC_DRV_RX8581=m -CONFIG_RTC_DRV_RV3028=m -CONFIG_RTC_DRV_RV8803=m -CONFIG_RTC_DRV_S5M=y -CONFIG_RTC_DRV_DS3232=y -CONFIG_RTC_DRV_PCF2127=m -CONFIG_RTC_DRV_EFI=y -CONFIG_RTC_DRV_CROS_EC=y -CONFIG_RTC_DRV_FSL_FTM_ALARM=m -CONFIG_RTC_DRV_S3C=y -CONFIG_RTC_DRV_PL031=y -CONFIG_RTC_DRV_SUN6I=y -CONFIG_RTC_DRV_ARMADA38X=y -CONFIG_RTC_DRV_PM8XXX=m -CONFIG_RTC_DRV_TEGRA=y -CONFIG_RTC_DRV_SNVS=m -CONFIG_RTC_DRV_IMX_SC=m -CONFIG_RTC_DRV_XGENE=y -CONFIG_DMADEVICES=y -CONFIG_DMA_BCM2835=y -CONFIG_DMA_SUN6I=m -CONFIG_FSL_EDMA=y -CONFIG_IMX_SDMA=y -CONFIG_K3_DMA=y -CONFIG_MV_XOR=y -CONFIG_MV_XOR_V2=y -CONFIG_OWL_DMA=y -CONFIG_PL330_DMA=y -CONFIG_TEGRA20_APB_DMA=y -CONFIG_TEGRA210_ADMA=m -CONFIG_QCOM_BAM_DMA=y -CONFIG_QCOM_HIDMA_MGMT=y -CONFIG_QCOM_HIDMA=y -CONFIG_RCAR_DMAC=y -CONFIG_RENESAS_USB_DMAC=m -CONFIG_RZ_DMAC=y -CONFIG_TI_K3_UDMA=y -CONFIG_TI_K3_UDMA_GLUE_LAYER=y -CONFIG_VFIO=y -CONFIG_VFIO_PCI=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_MMIO=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -CONFIG_MFD_CROS_EC_DEV=y -CONFIG_STAGING=y -CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_HANTRO=m -CONFIG_VIDEO_IMX_MEDIA=m -CONFIG_CHROME_PLATFORMS=y -CONFIG_CROS_EC=y -CONFIG_CROS_EC_I2C=y -CONFIG_CROS_EC_SPI=y -CONFIG_CROS_EC_CHARDEV=m -CONFIG_COMMON_CLK_SCMI=y -CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMMON_CLK_CS2000_CP=y -CONFIG_COMMON_CLK_FSL_SAI=y -CONFIG_COMMON_CLK_S2MPS11=y -CONFIG_COMMON_CLK_PWM=y -CONFIG_COMMON_CLK_VC5=y -CONFIG_COMMON_CLK_ZYNQMP=y -CONFIG_COMMON_CLK_BD718XX=m -CONFIG_CLK_RASPBERRYPI=m -CONFIG_CLK_IMX8MM=y -CONFIG_CLK_IMX8MN=y -CONFIG_CLK_IMX8MP=y -CONFIG_CLK_IMX8MQ=y -CONFIG_CLK_IMX8QXP=y -CONFIG_CLK_IMX8ULP=y -CONFIG_TI_SCI_CLK=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_QCOM_A53PLL=y -CONFIG_QCOM_CLK_APCS_MSM8916=y -CONFIG_QCOM_CLK_APCC_MSM8996=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_QCOM_CLK_RPMH=y -CONFIG_IPQ_GCC_8074=y -CONFIG_IPQ_GCC_6018=y -CONFIG_MSM_GCC_8916=y -CONFIG_MSM_GCC_8994=y -CONFIG_MSM_MMCC_8996=y -CONFIG_MSM_GCC_8998=y -CONFIG_QCS_GCC_404=y -CONFIG_SC_GCC_7180=y -CONFIG_SC_GCC_7280=y -CONFIG_SDM_CAMCC_845=m -CONFIG_SDM_GCC_845=y -CONFIG_SDM_GPUCC_845=y -CONFIG_SDM_VIDEOCC_845=y -CONFIG_SDM_DISPCC_845=y -CONFIG_SM_GCC_8150=y -CONFIG_SM_GCC_8250=y -CONFIG_SM_GCC_8350=y -CONFIG_SM_GPUCC_8150=y -CONFIG_SM_GPUCC_8250=y -CONFIG_SM_DISPCC_8250=y -CONFIG_QCOM_HFPLL=y -CONFIG_CLK_GFM_LPASS_SM8250=m -CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_ARM_MHU=y -CONFIG_IMX_MBOX=y -CONFIG_PLATFORM_MHU=y -CONFIG_BCM2835_MBOX=y -CONFIG_QCOM_APCS_IPC=y -CONFIG_QCOM_IPCC=y -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_TEGRA_IOMMU_SMMU=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_V3=y -CONFIG_MTK_IOMMU=y -CONFIG_QCOM_IOMMU=y -CONFIG_REMOTEPROC=y -CONFIG_QCOM_Q6V5_MSS=m -CONFIG_QCOM_Q6V5_PAS=m -CONFIG_QCOM_SYSMON=m -CONFIG_QCOM_WCNSS_PIL=m -CONFIG_RPMSG_CHAR=m -CONFIG_RPMSG_QCOM_GLINK_RPM=y -CONFIG_RPMSG_QCOM_GLINK_SMEM=m -CONFIG_RPMSG_QCOM_SMD=y -CONFIG_SOUNDWIRE=m -CONFIG_SOUNDWIRE_QCOM=m -CONFIG_OWL_PM_DOMAINS=y -CONFIG_RASPBERRYPI_POWER=y -CONFIG_FSL_DPAA=y -CONFIG_FSL_MC_DPIO=y -CONFIG_FSL_RCPM=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_QCOM_AOSS_QMP=y -CONFIG_QCOM_COMMAND_DB=y -CONFIG_QCOM_GENI_SE=y -CONFIG_QCOM_RMTFS_MEM=m -CONFIG_QCOM_RPMH=y -CONFIG_QCOM_RPMHPD=y -CONFIG_QCOM_RPMPD=y -CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_QCOM_SMP2P=y -CONFIG_QCOM_SMSM=y -CONFIG_QCOM_SOCINFO=m -CONFIG_QCOM_WCNSS_CTRL=m -CONFIG_QCOM_STATS=m -CONFIG_QCOM_APR=m -CONFIG_ARCH_R8A774A1=y -CONFIG_ARCH_R8A774B1=y -CONFIG_ARCH_R8A774C0=y -CONFIG_ARCH_R8A774E1=y -CONFIG_ARCH_R8A77950=y -CONFIG_ARCH_R8A77951=y -CONFIG_ARCH_R8A77960=y -CONFIG_ARCH_R8A77961=y -CONFIG_ARCH_R8A77965=y -CONFIG_ARCH_R8A77970=y -CONFIG_ARCH_R8A77980=y -CONFIG_ARCH_R8A77990=y -CONFIG_ARCH_R8A77995=y -CONFIG_ARCH_R8A779A0=y -CONFIG_ARCH_R8A779F0=y -CONFIG_ARCH_R9A07G044=y -CONFIG_ROCKCHIP_PM_DOMAINS=y -CONFIG_ARCH_TEGRA_132_SOC=y -CONFIG_ARCH_TEGRA_210_SOC=y -CONFIG_ARCH_TEGRA_186_SOC=y -CONFIG_ARCH_TEGRA_194_SOC=y -CONFIG_ARCH_TEGRA_234_SOC=y -CONFIG_TI_SCI_PM_DOMAINS=y -CONFIG_ARM_IMX_BUS_DEVFREQ=m -CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m -CONFIG_EXTCON_PTN5150=m -CONFIG_EXTCON_USB_GPIO=y -CONFIG_EXTCON_USBC_CROS_EC=y -CONFIG_RENESAS_RPCIF=m -CONFIG_IIO=y -CONFIG_EXYNOS_ADC=y -CONFIG_MAX9611=m -CONFIG_QCOM_SPMI_VADC=m -CONFIG_QCOM_SPMI_ADC5=m -CONFIG_ROCKCHIP_SARADC=m -CONFIG_RZG2L_ADC=m -CONFIG_IIO_CROS_EC_SENSORS_CORE=m -CONFIG_IIO_CROS_EC_SENSORS=m -CONFIG_IIO_ST_LSM6DSX=m -CONFIG_IIO_CROS_EC_LIGHT_PROX=m -CONFIG_SENSORS_ISL29018=m -CONFIG_VCNL4000=m -CONFIG_IIO_ST_MAGN_3AXIS=m -CONFIG_IIO_CROS_EC_BARO=m -CONFIG_MPL3115=m -CONFIG_PWM=y -CONFIG_PWM_BCM2835=m -CONFIG_PWM_CROS_EC=m -CONFIG_PWM_IMX27=m -CONFIG_PWM_MESON=m -CONFIG_PWM_MTK_DISP=m -CONFIG_PWM_MEDIATEK=m -CONFIG_PWM_RCAR=m -CONFIG_PWM_RENESAS_TPU=m -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_SAMSUNG=y -CONFIG_PWM_SL28CPLD=m -CONFIG_PWM_SUN4I=m -CONFIG_PWM_TEGRA=m -CONFIG_PWM_VISCONTI=m -CONFIG_SL28CPLD_INTC=y -CONFIG_QCOM_PDC=y -CONFIG_RESET_IMX7=y -CONFIG_RESET_QCOM_AOSS=y -CONFIG_RESET_QCOM_PDC=m -CONFIG_RESET_RZG2L_USBPHY_CTRL=y -CONFIG_RESET_TI_SCI=y -CONFIG_PHY_XGENE=y -CONFIG_PHY_SUN4I_USB=y -CONFIG_PHY_MIXEL_MIPI_DPHY=m -CONFIG_PHY_HI6220_USB=y -CONFIG_PHY_HISTB_COMBPHY=y -CONFIG_PHY_HISI_INNO_USB2=y -CONFIG_PHY_MVEBU_CP110_COMPHY=y -CONFIG_PHY_MTK_TPHY=y -CONFIG_PHY_QCOM_QMP=m -CONFIG_PHY_QCOM_QUSB2=m -CONFIG_PHY_QCOM_USB_HS=y -CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y -CONFIG_PHY_RCAR_GEN3_PCIE=y -CONFIG_PHY_RCAR_GEN3_USB2=y -CONFIG_PHY_RCAR_GEN3_USB3=m -CONFIG_PHY_ROCKCHIP_EMMC=y -CONFIG_PHY_ROCKCHIP_INNO_HDMI=m -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m -CONFIG_PHY_ROCKCHIP_PCIE=m -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_SAMSUNG_UFS=y -CONFIG_PHY_UNIPHIER_USB2=y -CONFIG_PHY_UNIPHIER_USB3=y -CONFIG_PHY_TEGRA_XUSB=y -CONFIG_ARM_SMMU_V3_PMU=m -CONFIG_FSL_IMX8_DDR_PMU=m -CONFIG_HISI_PMU=y -CONFIG_QCOM_L2_PMU=y -CONFIG_QCOM_L3_PMU=y -CONFIG_NVMEM_IMX_OCOTP=y -CONFIG_NVMEM_IMX_OCOTP_SCU=y -CONFIG_QCOM_QFPROM=y -CONFIG_MTK_EFUSE=y -CONFIG_ROCKCHIP_EFUSE=y -CONFIG_NVMEM_SUNXI_SID=y -CONFIG_UNIPHIER_EFUSE=y -CONFIG_MESON_EFUSE=m -CONFIG_NVMEM_RMEM=m -CONFIG_FPGA=y -CONFIG_FPGA_MGR_STRATIX10_SOC=m -CONFIG_FPGA_BRIDGE=m -CONFIG_ALTERA_FREEZE_BRIDGE=m -CONFIG_FPGA_REGION=m -CONFIG_OF_FPGA_REGION=m -CONFIG_TEE=y -CONFIG_OPTEE=y -CONFIG_SLIMBUS=m -CONFIG_SLIM_QCOM_CTRL=m -CONFIG_SLIM_QCOM_NGD_CTRL=m -CONFIG_MUX_MMIO=y -CONFIG_INTERCONNECT=y -CONFIG_INTERCONNECT_IMX=m -CONFIG_INTERCONNECT_IMX8MM=m -CONFIG_INTERCONNECT_IMX8MN=m -CONFIG_INTERCONNECT_IMX8MQ=m -CONFIG_INTERCONNECT_QCOM=y -CONFIG_INTERCONNECT_QCOM_MSM8916=m -<<<<<<< -CONFIG_INTERCONNECT_QCOM_OSM_L3=m -CONFIG_INTERCONNECT_QCOM_SC7280=y -CONFIG_INTERCONNECT_QCOM_SDM845=y -======= -CONFIG_INTERCONNECT_QCOM_QCS404=m -CONFIG_INTERCONNECT_QCOM_SDM845=m ->>>>>>> -CONFIG_INTERCONNECT_QCOM_SM8150=m -CONFIG_INTERCONNECT_QCOM_SM8250=m -CONFIG_INTERCONNECT_QCOM_SM8350=m -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_BTRFS_FS=m -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_FANOTIFY=y -CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_QUOTA=y -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=m -CONFIG_CUSE=m -CONFIG_OVERLAY_FS=m -CONFIG_VFAT_FS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_HUGETLBFS=y -CONFIG_CONFIGFS_FS=y -CONFIG_EFIVAR_FS=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_ROOT_NFS=y -CONFIG_9P_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_USER_API_RNG=m -CONFIG_CRYPTO_DEV_SUN8I_CE=m -CONFIG_CRYPTO_DEV_FSL_CAAM=m -CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m -CONFIG_CRYPTO_DEV_QCOM_RNG=m -CONFIG_CRYPTO_DEV_CCREE=m -CONFIG_CRYPTO_DEV_HISI_SEC2=m -CONFIG_CRYPTO_DEV_HISI_ZIP=m -CONFIG_CRYPTO_DEV_HISI_HPRE=m -CONFIG_CRYPTO_DEV_HISI_TRNG=m -CONFIG_CMA_SIZE_MBYTES=32 -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_INFO_REDUCED=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_FTRACE is not set -CONFIG_MEMTEST=y diff --git a/rr-cache/f93bd68f8905ee72aa0a339525fd22c07d672dd9/thisimage b/rr-cache/f93bd68f8905ee72aa0a339525fd22c07d672dd9/thisimage deleted file mode 100644 index b81740c..0000000 --- a/rr-cache/f93bd68f8905ee72aa0a339525fd22c07d672dd9/thisimage +++ /dev/null @@ -1,1279 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_BPF_SYSCALL=y -CONFIG_BPF_JIT=y -CONFIG_PREEMPT=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASKSTATS=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_NUMA_BALANCING=y -CONFIG_MEMCG=y -CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_HUGETLB=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_CGROUP_BPF=y -CONFIG_USER_NS=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_ARCH_ACTIONS=y -CONFIG_ARCH_SUNXI=y -CONFIG_ARCH_ALPINE=y -CONFIG_ARCH_APPLE=y -CONFIG_ARCH_BCM2835=y -CONFIG_ARCH_BCM4908=y -CONFIG_ARCH_BCM_IPROC=y -CONFIG_ARCH_BERLIN=y -CONFIG_ARCH_BRCMSTB=y -CONFIG_ARCH_EXYNOS=y -CONFIG_ARCH_K3=y -CONFIG_ARCH_LAYERSCAPE=y -CONFIG_ARCH_LG1K=y -CONFIG_ARCH_HISI=y -CONFIG_ARCH_KEEMBAY=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MESON=y -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_MXC=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_RENESAS=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_S32=y -CONFIG_ARCH_SEATTLE=y -CONFIG_ARCH_INTEL_SOCFPGA=y -CONFIG_ARCH_SYNQUACER=y -CONFIG_ARCH_TEGRA=y -CONFIG_ARCH_TESLA_FSD=y -CONFIG_ARCH_SPRD=y -CONFIG_ARCH_THUNDER=y -CONFIG_ARCH_THUNDER2=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_ARCH_VEXPRESS=y -CONFIG_ARCH_VISCONTI=y -CONFIG_ARCH_XGENE=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_ARM64_VA_BITS_48=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_SMT=y -CONFIG_NUMA=y -CONFIG_KEXEC=y -CONFIG_KEXEC_FILE=y -CONFIG_CRASH_DUMP=y -CONFIG_XEN=y -CONFIG_COMPAT=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_HIBERNATION=y -CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -CONFIG_ENERGY_MODEL=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -CONFIG_CPUFREQ_DT=y -CONFIG_ACPI_CPPC_CPUFREQ=m -CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m -CONFIG_ARM_ARMADA_37XX_CPUFREQ=y -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_IMX_CPUFREQ_DT=m -CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y -CONFIG_ARM_QCOM_CPUFREQ_HW=y -CONFIG_ARM_RASPBERRYPI_CPUFREQ=m -CONFIG_ARM_SCMI_CPUFREQ=y -CONFIG_ARM_TEGRA186_CPUFREQ=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_QORIQ_CPUFREQ=y -CONFIG_ACPI=y -CONFIG_ACPI_APEI=y -CONFIG_ACPI_APEI_GHES=y -CONFIG_ACPI_APEI_PCIEAER=y -CONFIG_ACPI_APEI_MEMORY_FAILURE=y -CONFIG_ACPI_APEI_EINJ=y -CONFIG_VIRTUALIZATION=y -CONFIG_KVM=y -CONFIG_ARM64_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64_CE=m -CONFIG_CRYPTO_SHA3_ARM64=m -CONFIG_CRYPTO_SM3_ARM64_CE=m -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_AES_ARM64_BS=m -CONFIG_JUMP_LABEL=y -CONFIG_SECCOMP=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_KSM=y -CONFIG_MEMORY_FAILURE=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=m -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_NET_DSA=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBS=m -CONFIG_NET_SCH_ETF=m -CONFIG_NET_SCH_TAPRIO=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_GACT=m -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_GATE=m -CONFIG_QRTR=m -CONFIG_QRTR_SMD=m -CONFIG_QRTR_TUN=m -CONFIG_CAN=m -CONFIG_CAN_FLEXCAN=m -CONFIG_CAN_RCAR=m -CONFIG_CAN_RCAR_CANFD=m -CONFIG_CAN_MCP251XFD=m -CONFIG_BT=m -CONFIG_BT_HIDP=m -# CONFIG_BT_LE is not set -CONFIG_BT_LEDS=y -# CONFIG_BT_DEBUGFS is not set -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HCIUART_QCA=y -CONFIG_BT_HCIUART_MRVL=y -CONFIG_BT_MRVL=m -CONFIG_BT_MRVL_SDIO=m -CONFIG_BT_QCOMSMD=m -CONFIG_CFG80211=m -CONFIG_MAC80211=m -CONFIG_MAC80211_LEDS=y -CONFIG_RFKILL=m -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y -CONFIG_NFC=m -CONFIG_NFC_NCI=m -CONFIG_NFC_S3FWRN5_I2C=m -CONFIG_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIEAER=y -CONFIG_PCI_IOV=y -CONFIG_PCI_PASID=y -CONFIG_HOTPLUG_PCI=y -CONFIG_HOTPLUG_PCI_ACPI=y -CONFIG_PCI_AARDVARK=y -CONFIG_PCI_TEGRA=y -CONFIG_PCIE_RCAR_HOST=y -CONFIG_PCIE_RCAR_EP=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCI_XGENE=y -CONFIG_PCIE_ALTERA=y -CONFIG_PCIE_ALTERA_MSI=y -CONFIG_PCI_HOST_THUNDER_PEM=y -CONFIG_PCI_HOST_THUNDER_ECAM=y -CONFIG_PCIE_ROCKCHIP_HOST=m -CONFIG_PCIE_BRCMSTB=m -CONFIG_PCI_IMX6=y -CONFIG_PCI_LAYERSCAPE=y -CONFIG_PCI_HISI=y -CONFIG_PCIE_QCOM=y -CONFIG_PCIE_ARMADA_8K=y -CONFIG_PCIE_KIRIN=y -CONFIG_PCIE_HISI_STB=y -CONFIG_PCIE_TEGRA194_HOST=m -CONFIG_PCIE_VISCONTI_HOST=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y -CONFIG_PCI_ENDPOINT=y -CONFIG_PCI_ENDPOINT_CONFIGFS=y -CONFIG_PCI_EPF_TEST=m -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_HISILICON_LPC=y -CONFIG_TEGRA_ACONNECT=m -CONFIG_ARM_SCMI_PROTOCOL=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_RASPBERRYPI_FIRMWARE=y -CONFIG_INTEL_STRATIX10_SERVICE=y -CONFIG_INTEL_STRATIX10_RSU=m -CONFIG_EFI_CAPSULE_LOADER=y -CONFIG_IMX_SCU=y -CONFIG_IMX_SCU_PD=y -CONFIG_GNSS=m -CONFIG_GNSS_MTK_SERIAL=m -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_SST25L=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_BRCMNAND=m -CONFIG_MTD_NAND_DENALI_DT=y -CONFIG_MTD_NAND_MARVELL=y -CONFIG_MTD_NAND_FSL_IFC=y -CONFIG_MTD_NAND_QCOM=y -CONFIG_MTD_SPI_NOR=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=m -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_NVME=m -CONFIG_SRAM=y -CONFIG_PCI_ENDPOINT_TEST=m -CONFIG_EEPROM_AT24=m -CONFIG_EEPROM_AT25=m -CONFIG_UACCE=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_SAS_ATA=y -CONFIG_SCSI_HISI_SAS=y -CONFIG_SCSI_HISI_SAS_PCI=y -CONFIG_MEGARAID_SAS=y -CONFIG_SCSI_MPT3SAS=m -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=m -CONFIG_SCSI_UFS_HISI=y -CONFIG_SCSI_UFS_EXYNOS=y -CONFIG_ATA=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_AHCI_BRCM=m -CONFIG_AHCI_CEVA=y -CONFIG_AHCI_MVEBU=y -CONFIG_AHCI_XGENE=y -CONFIG_AHCI_QORIQ=y -CONFIG_SATA_SIL24=y -CONFIG_SATA_RCAR=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_OF_PLATFORM=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_NETDEVICES=y -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_TUN=y -CONFIG_VETH=m -CONFIG_VIRTIO_NET=y -CONFIG_NET_DSA_BCM_SF2=m -CONFIG_NET_DSA_MSCC_FELIX=m -CONFIG_AMD_XGBE=y -CONFIG_NET_XGENE=y -CONFIG_ATL1C=m -CONFIG_BCMGENET=m -CONFIG_SYSTEMPORT=m -CONFIG_BNX2X=m -CONFIG_MACB=y -CONFIG_THUNDER_NIC_PF=y -CONFIG_FEC=y -CONFIG_FSL_FMAN=y -CONFIG_FSL_DPAA_ETH=y -CONFIG_FSL_DPAA2_ETH=y -CONFIG_FSL_ENETC=y -CONFIG_FSL_ENETC_VF=y -CONFIG_FSL_ENETC_QOS=y -CONFIG_HIX5HD2_GMAC=y -CONFIG_HNS_DSAF=y -CONFIG_HNS_ENET=y -CONFIG_HNS3=y -CONFIG_HNS3_HCLGE=y -CONFIG_HNS3_ENET=y -CONFIG_E1000=y -CONFIG_E1000E=y -CONFIG_IGB=y -CONFIG_IGBVF=y -CONFIG_MVNETA=y -CONFIG_MVPP2=y -CONFIG_SKY2=y -CONFIG_MLX4_EN=m -CONFIG_MLX5_CORE=m -CONFIG_MLX5_CORE_EN=y -CONFIG_QCOM_EMAC=m -CONFIG_RMNET=m -CONFIG_R8169=m -CONFIG_SH_ETH=y -CONFIG_RAVB=y -CONFIG_SMC91X=y -CONFIG_SMSC911X=y -CONFIG_SNI_AVE=y -CONFIG_SNI_NETSEC=y -CONFIG_STMMAC_ETH=m -CONFIG_TI_K3_AM65_CPSW_NUSS=y -CONFIG_QCOM_IPA=m -CONFIG_MESON_GXL_PHY=m -CONFIG_AQUANTIA_PHY=y -CONFIG_BCM54140_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_MARVELL_10G_PHY=m -CONFIG_MICREL_PHY=y -CONFIG_MICROSEMI_PHY=y -CONFIG_AT803X_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_ROCKCHIP_PHY=y -CONFIG_DP83867_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_USB_BRCMSTB=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9800=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_ATH10K_SNOC=m -CONFIG_WCN36XX=m -CONFIG_BRCMFMAC=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_SDIO=m -CONFIG_MWIFIEX_PCIE=m -CONFIG_WL18XX=m -CONFIG_WLCORE_SDIO=m -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_ADC=m -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_SNVS_PWRKEY=m -CONFIG_KEYBOARD_IMX_SC_KEY=m -CONFIG_KEYBOARD_CROS_EC=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=m -CONFIG_TOUCHSCREEN_GOODIX=m -CONFIG_TOUCHSCREEN_EDT_FT5X06=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_PM8941_PWRKEY=y -CONFIG_INPUT_PM8XXX_VIBRATOR=m -CONFIG_INPUT_PWM_BEEPER=m -CONFIG_INPUT_PWM_VIBRA=m -CONFIG_INPUT_HISI_POWERKEY=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIO_AMBAKMI=y -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_BCM2835AUX=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_OMAP=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_UNIPHIER=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_MESON=y -CONFIG_SERIAL_MESON_CONSOLE=y -CONFIG_SERIAL_SAMSUNG=y -CONFIG_SERIAL_SAMSUNG_CONSOLE=y -CONFIG_SERIAL_TEGRA=y -CONFIG_SERIAL_TEGRA_TCU=y -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SERIAL_QCOM_GENI=y -CONFIG_SERIAL_QCOM_GENI_CONSOLE=y -CONFIG_SERIAL_XILINX_PS_UART=y -CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -CONFIG_SERIAL_FSL_LPUART=y -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -CONFIG_SERIAL_FSL_LINFLEXUART=y -CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -CONFIG_SERIAL_MVEBU_UART=y -CONFIG_SERIAL_OWL=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_IPMI_HANDLER=m -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SI=m -CONFIG_TCG_TPM=y -CONFIG_TCG_TIS_I2C_INFINEON=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_I2C_BCM2835=m -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_I2C_GPIO=m -CONFIG_I2C_IMX=y -CONFIG_I2C_IMX_LPI2C=y -CONFIG_I2C_MESON=y -CONFIG_I2C_MT65XX=y -CONFIG_I2C_MV64XXX=y -CONFIG_I2C_OMAP=y -CONFIG_I2C_OWL=y -CONFIG_I2C_PXA=y -CONFIG_I2C_QCOM_CCI=m -CONFIG_I2C_QCOM_GENI=m -CONFIG_I2C_QUP=y -CONFIG_I2C_RIIC=y -CONFIG_I2C_RK3X=y -CONFIG_I2C_S3C2410=y -CONFIG_I2C_SH_MOBILE=y -CONFIG_I2C_TEGRA=y -CONFIG_I2C_UNIPHIER_F=y -CONFIG_I2C_RCAR=y -CONFIG_I2C_CROS_EC_TUNNEL=y -CONFIG_SPI=y -CONFIG_SPI_ARMADA_3700=y -CONFIG_SPI_BCM2835=m -CONFIG_SPI_BCM2835AUX=m -CONFIG_SPI_CADENCE_QUADSPI=y -CONFIG_SPI_DESIGNWARE=m -CONFIG_SPI_DW_DMA=y -CONFIG_SPI_DW_MMIO=m -CONFIG_SPI_FSL_LPSPI=y -CONFIG_SPI_FSL_QUADSPI=y -CONFIG_SPI_NXP_FLEXSPI=y -CONFIG_SPI_IMX=m -CONFIG_SPI_FSL_DSPI=y -CONFIG_SPI_MESON_SPICC=m -CONFIG_SPI_MESON_SPIFC=m -CONFIG_SPI_ORION=y -CONFIG_SPI_PL022=y -CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_RPCIF=m -CONFIG_SPI_RSPI=m -CONFIG_SPI_QCOM_QSPI=m -CONFIG_SPI_QUP=y -CONFIG_SPI_QCOM_GENI=m -CONFIG_SPI_S3C64XX=y -CONFIG_SPI_SH_MSIOF=m -CONFIG_SPI_SUN6I=y -CONFIG_SPI_SPIDEV=m -CONFIG_SPMI=y -CONFIG_PINCTRL_MAX77620=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_PINCTRL_OWL=y -CONFIG_PINCTRL_S700=y -CONFIG_PINCTRL_S900=y -CONFIG_PINCTRL_IMX8MM=y -CONFIG_PINCTRL_IMX8MN=y -CONFIG_PINCTRL_IMX8MP=y -CONFIG_PINCTRL_IMX8MQ=y -CONFIG_PINCTRL_IMX8QM=y -CONFIG_PINCTRL_IMX8QXP=y -CONFIG_PINCTRL_IMX8DXL=y -CONFIG_PINCTRL_IMX8ULP=y -CONFIG_PINCTRL_MSM=y -CONFIG_PINCTRL_IPQ8074=y -CONFIG_PINCTRL_IPQ6018=y -CONFIG_PINCTRL_MSM8916=y -CONFIG_PINCTRL_MSM8994=y -CONFIG_PINCTRL_MSM8996=y -CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_QCS404=y -CONFIG_PINCTRL_QDF2XXX=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -CONFIG_PINCTRL_SC7180=y -CONFIG_PINCTRL_SC7280=y -CONFIG_PINCTRL_SDM845=y -CONFIG_PINCTRL_SM8150=y -CONFIG_PINCTRL_SM8250=y -CONFIG_PINCTRL_SM8350=y -CONFIG_PINCTRL_SM8450=y -CONFIG_PINCTRL_LPASS_LPI=m -CONFIG_GPIO_ALTERA=m -CONFIG_GPIO_DAVINCI=y -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_MB86S7X=y -CONFIG_GPIO_MPC8XXX=y -CONFIG_GPIO_MXC=y -CONFIG_GPIO_PL061=y -CONFIG_GPIO_RCAR=y -CONFIG_GPIO_UNIPHIER=y -CONFIG_GPIO_VISCONTI=y -CONFIG_GPIO_WCD934X=m -CONFIG_GPIO_XGENE=y -CONFIG_GPIO_XGENE_SB=y -CONFIG_GPIO_MAX732X=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_BD9571MWV=m -CONFIG_GPIO_MAX77620=y -CONFIG_GPIO_SL28CPLD=m -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_RESET_QCOM_PON=m -CONFIG_POWER_RESET_XGENE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_SYSCON_REBOOT_MODE=y -CONFIG_BATTERY_SBS=m -CONFIG_BATTERY_BQ27XXX=y -CONFIG_BATTERY_MAX17042=m -CONFIG_CHARGER_BQ25890=m -CONFIG_CHARGER_BQ25980=m -CONFIG_SENSORS_ARM_SCMI=y -CONFIG_SENSORS_ARM_SCPI=y -CONFIG_SENSORS_JC42=m -CONFIG_SENSORS_LM75=m -CONFIG_SENSORS_LM90=m -CONFIG_SENSORS_PWM_FAN=m -CONFIG_SENSORS_RASPBERRYPI_HWMON=m -CONFIG_SENSORS_SL28CPLD=m -CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_INA3221=m -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_CPU_THERMAL=y -CONFIG_THERMAL_EMULATION=y -CONFIG_IMX_SC_THERMAL=m -CONFIG_IMX8MM_THERMAL=m -CONFIG_QORIQ_THERMAL=m -CONFIG_SUN8I_THERMAL=y -CONFIG_ROCKCHIP_THERMAL=m -CONFIG_RCAR_THERMAL=y -CONFIG_RCAR_GEN3_THERMAL=y -CONFIG_RZG2L_THERMAL=y -CONFIG_ARMADA_THERMAL=y -CONFIG_BCM2711_THERMAL=m -CONFIG_BCM2835_THERMAL=m -CONFIG_BRCMSTB_THERMAL=m -CONFIG_EXYNOS_THERMAL=y -CONFIG_TEGRA_SOCTHERM=m -CONFIG_TEGRA_BPMP_THERMAL=m -CONFIG_QCOM_TSENS=y -CONFIG_QCOM_SPMI_TEMP_ALARM=m -CONFIG_QCOM_LMH=m -CONFIG_UNIPHIER_THERMAL=y -CONFIG_WATCHDOG=y -CONFIG_SL28CPLD_WATCHDOG=m -CONFIG_ARM_SP805_WATCHDOG=y -CONFIG_ARM_SBSA_WATCHDOG=y -CONFIG_S3C2410_WATCHDOG=y -CONFIG_BCM7038_WDT=m -CONFIG_DW_WATCHDOG=y -CONFIG_SUNXI_WATCHDOG=m -CONFIG_IMX2_WDT=y -CONFIG_IMX_SC_WDT=m -CONFIG_QCOM_WDT=m -CONFIG_MESON_GXBB_WATCHDOG=m -CONFIG_MESON_WATCHDOG=m -CONFIG_ARM_SMC_WATCHDOG=y -CONFIG_RENESAS_WDT=y -CONFIG_RENESAS_RZG2LWDT=y -CONFIG_UNIPHIER_WATCHDOG=y -CONFIG_BCM2835_WDT=y -CONFIG_MFD_ALTERA_SYSMGR=y -CONFIG_MFD_BD9571MWV=y -CONFIG_MFD_AXP20X_I2C=y -CONFIG_MFD_AXP20X_RSB=y -CONFIG_MFD_EXYNOS_LPASS=m -CONFIG_MFD_HI6421_PMIC=y -CONFIG_MFD_HI655X_PMIC=y -CONFIG_MFD_MAX77620=y -CONFIG_MFD_MT6397=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_MFD_RK808=y -CONFIG_MFD_SEC_CORE=y -CONFIG_MFD_SL28CPLD=y -CONFIG_MFD_ROHM_BD718XX=y -CONFIG_MFD_WCD934X=m -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_AXP20X=y -CONFIG_REGULATOR_BD718XX=y -CONFIG_REGULATOR_BD9571MWV=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_HI6421V530=y -CONFIG_REGULATOR_HI655X=y -CONFIG_REGULATOR_MAX77620=y -CONFIG_REGULATOR_MAX8973=y -CONFIG_REGULATOR_MP8859=y -CONFIG_REGULATOR_MT6358=y -CONFIG_REGULATOR_MT6397=y -CONFIG_REGULATOR_PCA9450=y -CONFIG_REGULATOR_PF8X00=y -CONFIG_REGULATOR_PFUZE100=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_QCOM_RPMH=y -CONFIG_REGULATOR_QCOM_SMD_RPM=y -CONFIG_REGULATOR_QCOM_SPMI=y -CONFIG_REGULATOR_RK808=y -CONFIG_REGULATOR_S2MPS11=y -CONFIG_REGULATOR_TPS65132=m -CONFIG_REGULATOR_VCTRL=m -CONFIG_RC_CORE=m -CONFIG_RC_DECODERS=y -CONFIG_RC_DEVICES=y -CONFIG_IR_MESON=m -CONFIG_IR_SUNXI=m -CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y -# CONFIG_DVB_NET is not set -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VIDEO_QCOM_CAMSS=m -CONFIG_VIDEO_RCAR_CSI2=m -CONFIG_VIDEO_RCAR_VIN=m -CONFIG_VIDEO_SUN6I_CSI=m -CONFIG_VIDEO_RCAR_ISP=m -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m -CONFIG_VIDEO_SAMSUNG_S5P_MFC=m -CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m -CONFIG_VIDEO_RENESAS_FDP1=m -CONFIG_VIDEO_RENESAS_FCP=m -CONFIG_VIDEO_RENESAS_VSP1=m -CONFIG_VIDEO_QCOM_VENUS=m -CONFIG_SDR_PLATFORM_DRIVERS=y -CONFIG_VIDEO_RCAR_DRIF=m -CONFIG_VIDEO_IMX219=m -CONFIG_VIDEO_OV5640=m -CONFIG_VIDEO_OV5645=m -CONFIG_DRM=m -CONFIG_DRM_I2C_NXP_TDA998X=m -CONFIG_DRM_MALI_DISPLAY=m -CONFIG_DRM_NOUVEAU=m -CONFIG_DRM_EXYNOS=m -CONFIG_DRM_EXYNOS5433_DECON=y -CONFIG_DRM_EXYNOS7_DECON=y -CONFIG_DRM_EXYNOS_DSI=y -# CONFIG_DRM_EXYNOS_DP is not set -CONFIG_DRM_EXYNOS_HDMI=y -CONFIG_DRM_EXYNOS_MIC=y -CONFIG_DRM_ROCKCHIP=m -CONFIG_ROCKCHIP_ANALOGIX_DP=y -CONFIG_ROCKCHIP_CDN_DP=y -CONFIG_ROCKCHIP_DW_HDMI=y -CONFIG_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_ROCKCHIP_INNO_HDMI=y -CONFIG_ROCKCHIP_LVDS=y -CONFIG_DRM_RCAR_DU=m -CONFIG_DRM_RCAR_DW_HDMI=m -CONFIG_DRM_RCAR_MIPI_DSI=m -CONFIG_DRM_SUN4I=m -CONFIG_DRM_SUN6I_DSI=m -CONFIG_DRM_SUN8I_DW_HDMI=m -CONFIG_DRM_SUN8I_MIXER=m -CONFIG_DRM_MSM=m -CONFIG_DRM_TEGRA=m -CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m -CONFIG_DRM_PANEL_LVDS=m -CONFIG_DRM_PANEL_SIMPLE=m -CONFIG_DRM_PANEL_EDP=m -CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m -CONFIG_DRM_PANEL_RAYDIUM_RM67191=m -CONFIG_DRM_PANEL_SITRONIX_ST7703=m -CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m -CONFIG_DRM_LONTIUM_LT8912B=m -CONFIG_DRM_LONTIUM_LT9611=m -CONFIG_DRM_LONTIUM_LT9611UXC=m -CONFIG_DRM_NWL_MIPI_DSI=m -CONFIG_DRM_PARADE_PS8640=m -CONFIG_DRM_SII902X=m -CONFIG_DRM_SIMPLE_BRIDGE=m -CONFIG_DRM_THINE_THC63LVD1024=m -CONFIG_DRM_TI_SN65DSI86=m -CONFIG_DRM_I2C_ADV7511=m -CONFIG_DRM_I2C_ADV7511_AUDIO=y -CONFIG_DRM_DW_HDMI_AHB_AUDIO=m -CONFIG_DRM_DW_HDMI_CEC=m -CONFIG_DRM_IMX_DCSS=m -CONFIG_DRM_VC4=m -CONFIG_DRM_ETNAVIV=m -CONFIG_DRM_HISI_HIBMC=m -CONFIG_DRM_HISI_KIRIN=m -CONFIG_DRM_MEDIATEK=m -CONFIG_DRM_MEDIATEK_HDMI=m -CONFIG_DRM_MXSFB=m -CONFIG_DRM_MESON=m -CONFIG_DRM_PL111=m -CONFIG_DRM_LIMA=m -CONFIG_DRM_PANFROST=m -CONFIG_FB=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_EFI=y -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_LP855X=m -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_HDA_TEGRA=m -CONFIG_SND_HDA_CODEC_HDMI=m -CONFIG_SND_SOC=y -CONFIG_SND_BCM2835_SOC_I2S=m -CONFIG_SND_SOC_FSL_ASRC=m -CONFIG_SND_SOC_FSL_MICFIL=m -CONFIG_SND_SOC_FSL_EASRC=m -CONFIG_SND_IMX_SOC=m -CONFIG_SND_SOC_IMX_SGTL5000=m -CONFIG_SND_SOC_IMX_SPDIF=m -CONFIG_SND_SOC_FSL_ASOC_CARD=m -CONFIG_SND_SOC_IMX_AUDMIX=m -CONFIG_SND_MESON_AXG_SOUND_CARD=m -CONFIG_SND_MESON_GX_SOUND_CARD=m -CONFIG_SND_SOC_QCOM=m -CONFIG_SND_SOC_APQ8016_SBC=m -CONFIG_SND_SOC_MSM8996=m -CONFIG_SND_SOC_SDM845=m -CONFIG_SND_SOC_SM8250=m -CONFIG_SND_SOC_ROCKCHIP=m -CONFIG_SND_SOC_ROCKCHIP_SPDIF=m -CONFIG_SND_SOC_ROCKCHIP_RT5645=m -CONFIG_SND_SOC_RK3399_GRU_SOUND=m -CONFIG_SND_SOC_SAMSUNG=y -CONFIG_SND_SOC_RCAR=m -CONFIG_SND_SOC_RZ=m -CONFIG_SND_SUN4I_I2S=m -CONFIG_SND_SUN4I_SPDIF=m -CONFIG_SND_SOC_TEGRA=m -CONFIG_SND_SOC_TEGRA210_AHUB=m -CONFIG_SND_SOC_TEGRA210_DMIC=m -CONFIG_SND_SOC_TEGRA210_I2S=m -CONFIG_SND_SOC_TEGRA186_DSPK=m -CONFIG_SND_SOC_TEGRA210_ADMAIF=m -CONFIG_SND_SOC_TEGRA210_MVC=m -CONFIG_SND_SOC_TEGRA210_SFC=m -CONFIG_SND_SOC_TEGRA210_AMX=m -CONFIG_SND_SOC_TEGRA210_ADX=m -CONFIG_SND_SOC_TEGRA210_MIXER=m -CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m -CONFIG_SND_SOC_AK4613=m -CONFIG_SND_SOC_ES7134=m -CONFIG_SND_SOC_ES7241=m -CONFIG_SND_SOC_GTM601=m -CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m -CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -CONFIG_SND_SOC_PCM3168A_I2C=m -CONFIG_SND_SOC_RT5659=m -CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -CONFIG_SND_SOC_SIMPLE_MUX=m -CONFIG_SND_SOC_TAS571X=m -CONFIG_SND_SOC_TLV320AIC32X4_I2C=m -CONFIG_SND_SOC_WCD934X=m -CONFIG_SND_SOC_WM8904=m -CONFIG_SND_SOC_WM8960=m -CONFIG_SND_SOC_WM8962=m -CONFIG_SND_SOC_WM8978=m -CONFIG_SND_SOC_WSA881X=m -CONFIG_SND_SOC_NAU8822=m -CONFIG_SND_SOC_LPASS_WSA_MACRO=m -CONFIG_SND_SOC_LPASS_VA_MACRO=m -CONFIG_SND_SIMPLE_CARD=m -CONFIG_SND_AUDIO_GRAPH_CARD=m -CONFIG_SND_AUDIO_GRAPH_CARD2=m -CONFIG_HID_MULTITOUCH=m -CONFIG_I2C_HID_ACPI=m -CONFIG_I2C_HID_OF=m -CONFIG_USB=y -CONFIG_USB_OTG=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PCI_RENESAS=m -CONFIG_USB_XHCI_TEGRA=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_EXYNOS=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_EXYNOS=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_RENESAS_USBHS_HCD=m -CONFIG_USB_RENESAS_USBHS=m -CONFIG_USB_ACM=m -CONFIG_USB_STORAGE=y -CONFIG_USB_CDNS_SUPPORT=m -CONFIG_USB_CDNS3=m -CONFIG_USB_CDNS3_GADGET=y -CONFIG_USB_CDNS3_HOST=y -CONFIG_USB_MTU3=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SUNXI=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC2=y -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_ISP1760=y -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_HSIC_USB3503=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_GADGET=y -CONFIG_USB_RENESAS_USBHS_UDC=m -CONFIG_USB_RENESAS_USB3=m -CONFIG_USB_TEGRA_XUDC=m -CONFIG_USB_CONFIGFS=m -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_TYPEC=m -CONFIG_TYPEC_TCPM=m -CONFIG_TYPEC_TCPCI=m -CONFIG_TYPEC_FUSB302=m -CONFIG_TYPEC_TPS6598X=m -CONFIG_TYPEC_HD3SS3220=m -CONFIG_MMC=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ACPI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MMC_SDHCI_ESDHC_IMX=y -CONFIG_MMC_SDHCI_TEGRA=y -CONFIG_MMC_SDHCI_F_SDH30=y -CONFIG_MMC_MESON_GX=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_MMC_SPI=y -CONFIG_MMC_SDHI=y -CONFIG_MMC_UNIPHIER=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_EXYNOS=y -CONFIG_MMC_DW_HI3798CV200=y -CONFIG_MMC_DW_K3=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SUNXI=y -CONFIG_MMC_BCM2835=y -CONFIG_MMC_MTK=y -CONFIG_MMC_SDHCI_XENON=y -CONFIG_MMC_SDHCI_AM654=y -CONFIG_MMC_OWL=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_LM3692X=m -CONFIG_LEDS_PCA9532=m -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_EDAC=y -CONFIG_EDAC_GHES=y -CONFIG_EDAC_LAYERSCAPE=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=m -CONFIG_RTC_DRV_HYM8563=m -CONFIG_RTC_DRV_MAX77686=y -CONFIG_RTC_DRV_RK808=m -CONFIG_RTC_DRV_PCF85063=m -CONFIG_RTC_DRV_PCF85363=m -CONFIG_RTC_DRV_M41T80=m -CONFIG_RTC_DRV_RX8581=m -CONFIG_RTC_DRV_RV3028=m -CONFIG_RTC_DRV_RV8803=m -CONFIG_RTC_DRV_S5M=y -CONFIG_RTC_DRV_DS3232=y -CONFIG_RTC_DRV_PCF2127=m -CONFIG_RTC_DRV_EFI=y -CONFIG_RTC_DRV_CROS_EC=y -CONFIG_RTC_DRV_FSL_FTM_ALARM=m -CONFIG_RTC_DRV_S3C=y -CONFIG_RTC_DRV_PL031=y -CONFIG_RTC_DRV_SUN6I=y -CONFIG_RTC_DRV_ARMADA38X=y -CONFIG_RTC_DRV_PM8XXX=m -CONFIG_RTC_DRV_TEGRA=y -CONFIG_RTC_DRV_SNVS=m -CONFIG_RTC_DRV_IMX_SC=m -CONFIG_RTC_DRV_XGENE=y -CONFIG_RTC_DRV_MT6397=m -CONFIG_DMADEVICES=y -CONFIG_DMA_BCM2835=y -CONFIG_DMA_SUN6I=m -CONFIG_FSL_EDMA=y -CONFIG_IMX_SDMA=m -CONFIG_K3_DMA=y -CONFIG_MV_XOR=y -CONFIG_MV_XOR_V2=y -CONFIG_OWL_DMA=y -CONFIG_PL330_DMA=y -CONFIG_TEGRA186_GPC_DMA=m -CONFIG_TEGRA20_APB_DMA=y -CONFIG_TEGRA210_ADMA=m -CONFIG_QCOM_BAM_DMA=y -CONFIG_QCOM_HIDMA_MGMT=y -CONFIG_QCOM_HIDMA=y -CONFIG_RCAR_DMAC=y -CONFIG_RENESAS_USB_DMAC=m -CONFIG_RZ_DMAC=y -CONFIG_TI_K3_UDMA=y -CONFIG_TI_K3_UDMA_GLUE_LAYER=y -CONFIG_VFIO=y -CONFIG_VFIO_PCI=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_MMIO=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -CONFIG_STAGING=y -CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_HANTRO=m -CONFIG_VIDEO_IMX_MEDIA=m -CONFIG_CHROME_PLATFORMS=y -CONFIG_CROS_EC=y -CONFIG_CROS_EC_I2C=y -CONFIG_CROS_EC_SPI=y -CONFIG_CROS_EC_CHARDEV=m -CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_SCMI=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMMON_CLK_CS2000_CP=y -CONFIG_COMMON_CLK_FSL_SAI=y -CONFIG_COMMON_CLK_S2MPS11=y -CONFIG_COMMON_CLK_PWM=y -CONFIG_COMMON_CLK_VC5=y -CONFIG_COMMON_CLK_BD718XX=m -CONFIG_CLK_RASPBERRYPI=m -CONFIG_CLK_IMX8MM=y -CONFIG_CLK_IMX8MN=y -CONFIG_CLK_IMX8MP=y -CONFIG_CLK_IMX8MQ=y -CONFIG_CLK_IMX8QXP=y -CONFIG_CLK_IMX8ULP=y -CONFIG_TI_SCI_CLK=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_QCOM_A53PLL=y -CONFIG_QCOM_CLK_APCS_MSM8916=y -CONFIG_QCOM_CLK_APCC_MSM8996=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_QCOM_CLK_RPMH=y -CONFIG_IPQ_GCC_6018=y -CONFIG_IPQ_GCC_8074=y -CONFIG_MSM_GCC_8916=y -CONFIG_MSM_GCC_8994=y -CONFIG_MSM_MMCC_8996=y -CONFIG_MSM_GCC_8998=y -CONFIG_QCS_GCC_404=y -CONFIG_SC_GCC_7180=y -CONFIG_SC_GCC_7280=y -CONFIG_SDM_CAMCC_845=m -CONFIG_SDM_GPUCC_845=y -CONFIG_SDM_VIDEOCC_845=y -CONFIG_SDM_DISPCC_845=y -CONFIG_SM_GCC_8350=y -CONFIG_SM_GCC_8450=y -CONFIG_SM_GPUCC_8150=y -CONFIG_SM_GPUCC_8250=y -CONFIG_QCOM_HFPLL=y -CONFIG_CLK_GFM_LPASS_SM8250=m -CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_RENESAS_OSTM=y -CONFIG_ARM_MHU=y -CONFIG_IMX_MBOX=y -CONFIG_PLATFORM_MHU=y -CONFIG_BCM2835_MBOX=y -CONFIG_QCOM_APCS_IPC=y -CONFIG_QCOM_IPCC=y -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_TEGRA_IOMMU_SMMU=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_V3=y -CONFIG_MTK_IOMMU=y -CONFIG_QCOM_IOMMU=y -CONFIG_REMOTEPROC=y -CONFIG_QCOM_Q6V5_MSS=m -CONFIG_QCOM_Q6V5_PAS=m -CONFIG_QCOM_SYSMON=m -CONFIG_QCOM_WCNSS_PIL=m -CONFIG_RPMSG_CHAR=m -CONFIG_RPMSG_QCOM_GLINK_RPM=y -CONFIG_RPMSG_QCOM_GLINK_SMEM=m -CONFIG_RPMSG_QCOM_SMD=y -CONFIG_SOUNDWIRE=m -CONFIG_SOUNDWIRE_QCOM=m -CONFIG_OWL_PM_DOMAINS=y -CONFIG_RASPBERRYPI_POWER=y -CONFIG_FSL_DPAA=y -CONFIG_FSL_MC_DPIO=y -CONFIG_FSL_RCPM=y -CONFIG_MTK_DEVAPC=m -CONFIG_MTK_PMIC_WRAP=y -CONFIG_QCOM_AOSS_QMP=y -CONFIG_QCOM_COMMAND_DB=y -CONFIG_QCOM_CPR=y -CONFIG_QCOM_GENI_SE=y -CONFIG_QCOM_RMTFS_MEM=m -CONFIG_QCOM_RPMH=y -CONFIG_QCOM_RPMHPD=y -CONFIG_QCOM_RPMPD=y -CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_QCOM_SMP2P=y -CONFIG_QCOM_SMSM=y -CONFIG_QCOM_SOCINFO=m -CONFIG_QCOM_STATS=m -CONFIG_QCOM_WCNSS_CTRL=m -CONFIG_QCOM_APR=m -CONFIG_ARCH_R8A77995=y -CONFIG_ARCH_R8A77990=y -CONFIG_ARCH_R8A77950=y -CONFIG_ARCH_R8A77951=y -CONFIG_ARCH_R8A77965=y -CONFIG_ARCH_R8A77960=y -CONFIG_ARCH_R8A77961=y -CONFIG_ARCH_R8A779F0=y -CONFIG_ARCH_R8A77980=y -CONFIG_ARCH_R8A77970=y -CONFIG_ARCH_R8A779A0=y -CONFIG_ARCH_R8A774C0=y -CONFIG_ARCH_R8A774E1=y -CONFIG_ARCH_R8A774A1=y -CONFIG_ARCH_R8A774B1=y -CONFIG_ARCH_R9A07G044=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_ROCKCHIP_PM_DOMAINS=y -CONFIG_ARCH_TEGRA_132_SOC=y -CONFIG_ARCH_TEGRA_210_SOC=y -CONFIG_ARCH_TEGRA_186_SOC=y -CONFIG_ARCH_TEGRA_194_SOC=y -CONFIG_ARCH_TEGRA_234_SOC=y -CONFIG_TI_SCI_PM_DOMAINS=y -CONFIG_ARM_IMX_BUS_DEVFREQ=m -CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m -CONFIG_EXTCON_PTN5150=m -CONFIG_EXTCON_USB_GPIO=y -CONFIG_EXTCON_USBC_CROS_EC=y -CONFIG_RENESAS_RPCIF=m -CONFIG_IIO=y -CONFIG_EXYNOS_ADC=y -CONFIG_MAX9611=m -CONFIG_QCOM_SPMI_VADC=m -CONFIG_QCOM_SPMI_ADC5=m -CONFIG_ROCKCHIP_SARADC=m -CONFIG_RZG2L_ADC=m -CONFIG_TI_ADS1015=m -CONFIG_IIO_CROS_EC_SENSORS_CORE=m -CONFIG_IIO_CROS_EC_SENSORS=m -CONFIG_IIO_ST_LSM6DSX=m -CONFIG_IIO_CROS_EC_LIGHT_PROX=m -CONFIG_SENSORS_ISL29018=m -CONFIG_VCNL4000=m -CONFIG_IIO_ST_MAGN_3AXIS=m -CONFIG_IIO_CROS_EC_BARO=m -CONFIG_MPL3115=m -CONFIG_PWM=y -CONFIG_PWM_BCM2835=m -CONFIG_PWM_BRCMSTB=m -CONFIG_PWM_CROS_EC=m -CONFIG_PWM_IMX27=m -CONFIG_PWM_MESON=m -CONFIG_PWM_MTK_DISP=m -CONFIG_PWM_MEDIATEK=m -CONFIG_PWM_RCAR=m -CONFIG_PWM_RENESAS_TPU=m -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_SAMSUNG=y -CONFIG_PWM_SL28CPLD=m -CONFIG_PWM_SUN4I=m -CONFIG_PWM_TEGRA=m -CONFIG_PWM_VISCONTI=m -CONFIG_SL28CPLD_INTC=y -CONFIG_QCOM_PDC=y -CONFIG_RESET_IMX7=y -CONFIG_RESET_QCOM_AOSS=y -CONFIG_RESET_QCOM_PDC=m -CONFIG_RESET_RZG2L_USBPHY_CTRL=y -CONFIG_RESET_TI_SCI=y -CONFIG_PHY_XGENE=y -CONFIG_PHY_SUN4I_USB=y -CONFIG_PHY_CADENCE_SIERRA=m -CONFIG_PHY_MIXEL_MIPI_DPHY=m -CONFIG_PHY_FSL_IMX8M_PCIE=y -CONFIG_PHY_HI6220_USB=y -CONFIG_PHY_HISTB_COMBPHY=y -CONFIG_PHY_HISI_INNO_USB2=y -CONFIG_PHY_MVEBU_CP110_COMPHY=y -CONFIG_PHY_MTK_TPHY=y -CONFIG_PHY_QCOM_QMP=m -CONFIG_PHY_QCOM_QUSB2=m -CONFIG_PHY_QCOM_USB_HS=y -CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y -CONFIG_PHY_RCAR_GEN3_PCIE=y -CONFIG_PHY_RCAR_GEN3_USB2=y -CONFIG_PHY_RCAR_GEN3_USB3=m -CONFIG_PHY_ROCKCHIP_EMMC=y -CONFIG_PHY_ROCKCHIP_INNO_HDMI=m -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m -CONFIG_PHY_ROCKCHIP_PCIE=m -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_SAMSUNG_UFS=y -CONFIG_PHY_UNIPHIER_USB2=y -CONFIG_PHY_UNIPHIER_USB3=y -CONFIG_PHY_TEGRA_XUSB=y -CONFIG_PHY_AM654_SERDES=m -CONFIG_PHY_J721E_WIZ=m -CONFIG_ARM_SMMU_V3_PMU=m -CONFIG_FSL_IMX8_DDR_PMU=m -CONFIG_QCOM_L2_PMU=y -CONFIG_QCOM_L3_PMU=y -CONFIG_HISI_PMU=y -CONFIG_NVMEM_IMX_OCOTP=y -CONFIG_NVMEM_IMX_OCOTP_SCU=y -CONFIG_MTK_EFUSE=y -CONFIG_QCOM_QFPROM=y -CONFIG_ROCKCHIP_EFUSE=y -CONFIG_NVMEM_SUNXI_SID=y -CONFIG_UNIPHIER_EFUSE=y -CONFIG_MESON_EFUSE=m -CONFIG_NVMEM_RMEM=m -CONFIG_NVMEM_LAYERSCAPE_SFP=m -CONFIG_FPGA=y -CONFIG_FPGA_MGR_ALTERA_CVP=m -CONFIG_FPGA_MGR_STRATIX10_SOC=m -CONFIG_FPGA_BRIDGE=m -CONFIG_ALTERA_FREEZE_BRIDGE=m -CONFIG_FPGA_REGION=m -CONFIG_OF_FPGA_REGION=m -CONFIG_TEE=y -CONFIG_OPTEE=y -CONFIG_MUX_MMIO=y -CONFIG_SLIMBUS=m -CONFIG_SLIM_QCOM_CTRL=m -CONFIG_SLIM_QCOM_NGD_CTRL=m -CONFIG_INTERCONNECT=y -CONFIG_INTERCONNECT_IMX=m -CONFIG_INTERCONNECT_IMX8MM=m -CONFIG_INTERCONNECT_IMX8MN=m -CONFIG_INTERCONNECT_IMX8MQ=m -CONFIG_INTERCONNECT_QCOM=y -CONFIG_INTERCONNECT_QCOM_MSM8916=m -<<<<<<< -CONFIG_INTERCONNECT_QCOM_OSM_L3=m -CONFIG_INTERCONNECT_QCOM_SC7280=y -CONFIG_INTERCONNECT_QCOM_SDM845=y -======= -CONFIG_INTERCONNECT_QCOM_QCS404=m -CONFIG_INTERCONNECT_QCOM_SDM845=m ->>>>>>> -CONFIG_INTERCONNECT_QCOM_SM8150=m -CONFIG_INTERCONNECT_QCOM_SM8250=m -CONFIG_INTERCONNECT_QCOM_SM8350=m -CONFIG_INTERCONNECT_QCOM_SM8450=m -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_BTRFS_FS=m -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_FANOTIFY=y -CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_QUOTA=y -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=m -CONFIG_CUSE=m -CONFIG_OVERLAY_FS=m -CONFIG_VFAT_FS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_HUGETLBFS=y -CONFIG_CONFIGFS_FS=y -CONFIG_EFIVAR_FS=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_ROOT_NFS=y -CONFIG_9P_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_USER_API_RNG=m -CONFIG_CRYPTO_DEV_SUN8I_CE=m -CONFIG_CRYPTO_DEV_FSL_CAAM=m -CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m -CONFIG_CRYPTO_DEV_QCOM_RNG=m -CONFIG_CRYPTO_DEV_CCREE=m -CONFIG_CRYPTO_DEV_HISI_SEC2=m -CONFIG_CRYPTO_DEV_HISI_ZIP=m -CONFIG_CRYPTO_DEV_HISI_HPRE=m -CONFIG_CRYPTO_DEV_HISI_TRNG=m -CONFIG_CMA_SIZE_MBYTES=32 -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_INFO_REDUCED=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_FTRACE is not set -CONFIG_MEMTEST=y diff --git a/rr-cache/fc133b9e653e8e01d9db9d355605ddda8cf2b6a5/preimage b/rr-cache/fc133b9e653e8e01d9db9d355605ddda8cf2b6a5/preimage deleted file mode 100644 index 75dfd32..0000000 --- a/rr-cache/fc133b9e653e8e01d9db9d355605ddda8cf2b6a5/preimage +++ /dev/null @@ -1,5589 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - i2c14 = &i2c14; - i2c15 = &i2c15; - i2c16 = &i2c16; - i2c17 = &i2c17; - i2c18 = &i2c18; - i2c19 = &i2c19; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - spi5 = &spi5; - spi6 = &spi6; - spi7 = &spi7; - spi8 = &spi8; - spi9 = &spi9; - spi10 = &spi10; - spi11 = &spi11; - spi12 = &spi12; - spi13 = &spi13; - spi14 = &spi14; - spi15 = &spi15; - spi16 = &spi16; - spi17 = &spi17; - spi18 = &spi18; - spi19 = &spi19; - }; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x200>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x300>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x400>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <379>; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x500>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <379>; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x600>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <379>; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x700>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <444>; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 2>; - operating-points-v2 = <&cpu7_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <350>; - exit-latency-us = <461>; - min-residency-us = <1890>; - local-timer-stop; - }; - - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <360>; - exit-latency-us = <531>; - min-residency-us = <3934>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <264>; - exit-latency-us = <621>; - min-residency-us = <952>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <702>; - exit-latency-us = <1061>; - min-residency-us = <4488>; - local-timer-stop; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x400000F4>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9987>; - local-timer-stop; - }; - }; -<<<<<<< -======= - }; - - cpu0_opp_table: cpu0_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu0_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp2: opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <800000 9600000>; - }; - - cpu0_opp3: opp-518400000 { - opp-hz = /bits/ 64 <518400000>; - opp-peak-kBps = <800000 16588800>; - }; - - cpu0_opp4: opp-614400000 { - opp-hz = /bits/ 64 <614400000>; - opp-peak-kBps = <800000 16588800>; - }; - - cpu0_opp5: opp-691200000 { - opp-hz = /bits/ 64 <691200000>; - opp-peak-kBps = <800000 19660800>; - }; - - cpu0_opp6: opp-787200000 { - opp-hz = /bits/ 64 <787200000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu0_opp7: opp-883200000 { - opp-hz = /bits/ 64 <883200000>; - opp-peak-kBps = <1804000 23347200>; - }; - - cpu0_opp8: opp-979200000 { - opp-hz = /bits/ 64 <979200000>; - opp-peak-kBps = <1804000 26419200>; - }; - - cpu0_opp9: opp-1075200000 { - opp-hz = /bits/ 64 <1075200000>; - opp-peak-kBps = <1804000 29491200>; - }; - - cpu0_opp10: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <1804000 32563200>; - }; - - cpu0_opp11: opp-1248000000 { - opp-hz = /bits/ 64 <1248000000>; - opp-peak-kBps = <1804000 36249600>; - }; - - cpu0_opp12: opp-1344000000 { - opp-hz = /bits/ 64 <1344000000>; - opp-peak-kBps = <2188000 36249600>; - }; - - cpu0_opp13: opp-1420800000 { - opp-hz = /bits/ 64 <1420800000>; - opp-peak-kBps = <2188000 39321600>; - }; - - cpu0_opp14: opp-1516800000 { - opp-hz = /bits/ 64 <1516800000>; - opp-peak-kBps = <3072000 42393600>; - }; - - cpu0_opp15: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <3072000 42393600>; - }; - - cpu0_opp16: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <4068000 42393600>; - }; - - cpu0_opp17: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <4068000 42393600>; - }; - }; - - cpu4_opp_table: cpu4_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu4_opp1: opp-710400000 { - opp-hz = /bits/ 64 <710400000>; - opp-peak-kBps = <1804000 19660800>; - }; - - cpu4_opp2: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 23347200>; - }; - - cpu4_opp3: opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <2188000 26419200>; - }; - - cpu4_opp4: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 26419200>; - }; - - cpu4_opp5: opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <3072000 29491200>; - }; - - cpu4_opp6: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 29491200>; - }; - - cpu4_opp7: opp-1382400000 { - opp-hz = /bits/ 64 <1382400000>; - opp-peak-kBps = <4068000 32563200>; - }; - - cpu4_opp8: opp-1478400000 { - opp-hz = /bits/ 64 <1478400000>; - opp-peak-kBps = <4068000 32563200>; - }; - - cpu4_opp9: opp-1574400000 { - opp-hz = /bits/ 64 <1574400000>; - opp-peak-kBps = <5412000 39321600>; - }; - - cpu4_opp10: opp-1670400000 { - opp-hz = /bits/ 64 <1670400000>; - opp-peak-kBps = <5412000 42393600>; - }; - - cpu4_opp11: opp-1766400000 { - opp-hz = /bits/ 64 <1766400000>; - opp-peak-kBps = <5412000 45465600>; - }; - - cpu4_opp12: opp-1862400000 { - opp-hz = /bits/ 64 <1862400000>; - opp-peak-kBps = <6220000 45465600>; - }; - - cpu4_opp13: opp-1958400000 { - opp-hz = /bits/ 64 <1958400000>; - opp-peak-kBps = <6220000 48537600>; - }; - - cpu4_opp14: opp-2054400000 { - opp-hz = /bits/ 64 <2054400000>; - opp-peak-kBps = <7216000 48537600>; - }; - - cpu4_opp15: opp-2150400000 { - opp-hz = /bits/ 64 <2150400000>; - opp-peak-kBps = <7216000 51609600>; - }; - - cpu4_opp16: opp-2246400000 { - opp-hz = /bits/ 64 <2246400000>; - opp-peak-kBps = <7216000 51609600>; - }; - - cpu4_opp17: opp-2342400000 { - opp-hz = /bits/ 64 <2342400000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu4_opp18: opp-2419200000 { - opp-hz = /bits/ 64 <2419200000>; - opp-peak-kBps = <8368000 51609600>; - }; - }; - - cpu7_opp_table: cpu7_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu7_opp1: opp-844800000 { - opp-hz = /bits/ 64 <844800000>; - opp-peak-kBps = <2188000 19660800>; - }; - - cpu7_opp2: opp-960000000 { - opp-hz = /bits/ 64 <960000000>; - opp-peak-kBps = <2188000 26419200>; - }; - - cpu7_opp3: opp-1075200000 { - opp-hz = /bits/ 64 <1075200000>; - opp-peak-kBps = <3072000 26419200>; - }; - - cpu7_opp4: opp-1190400000 { - opp-hz = /bits/ 64 <1190400000>; - opp-peak-kBps = <3072000 29491200>; - }; - - cpu7_opp5: opp-1305600000 { - opp-hz = /bits/ 64 <1305600000>; - opp-peak-kBps = <4068000 32563200>; - }; - - cpu7_opp6: opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <4068000 32563200>; - }; - - cpu7_opp7: opp-1516800000 { - opp-hz = /bits/ 64 <1516800000>; - opp-peak-kBps = <4068000 36249600>; - }; - - cpu7_opp8: opp-1632000000 { - opp-hz = /bits/ 64 <1632000000>; - opp-peak-kBps = <5412000 39321600>; - }; - - cpu7_opp9: opp-1747200000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <5412000 42393600>; - }; - - cpu7_opp10: opp-1862400000 { - opp-hz = /bits/ 64 <1862400000>; - opp-peak-kBps = <6220000 45465600>; - }; - - cpu7_opp11: opp-1977600000 { - opp-hz = /bits/ 64 <1977600000>; - opp-peak-kBps = <6220000 48537600>; - }; - - cpu7_opp12: opp-2073600000 { - opp-hz = /bits/ 64 <2073600000>; - opp-peak-kBps = <7216000 48537600>; - }; - - cpu7_opp13: opp-2169600000 { - opp-hz = /bits/ 64 <2169600000>; - opp-peak-kBps = <7216000 51609600>; - }; - - cpu7_opp14: opp-2265600000 { - opp-hz = /bits/ 64 <2265600000>; - opp-peak-kBps = <7216000 51609600>; - }; - - cpu7_opp15: opp-2361600000 { - opp-hz = /bits/ 64 <2361600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp16: opp-2457600000 { - opp-hz = /bits/ 64 <2457600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp17: opp-2553600000 { - opp-hz = /bits/ 64 <2553600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp18: opp-2649600000 { - opp-hz = /bits/ 64 <2649600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp19: opp-2745600000 { - opp-hz = /bits/ 64 <2745600000>; - opp-peak-kBps = <8368000 51609600>; - }; - - cpu7_opp20: opp-2841600000 { - opp-hz = /bits/ 64 <2841600000>; - opp-peak-kBps = <8368000 51609600>; - }; ->>>>>>> - }; - - firmware { - scm: scm { - compatible = "qcom,scm"; - #reset-cells = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_aop_mem: memory@80700000 { - reg = <0x0 0x80700000 0x0 0x160000>; - no-map; - }; - - cmd_db: memory@80860000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x80860000 0x0 0x20000>; - no-map; - }; - - smem_mem: memory@80900000 { - reg = <0x0 0x80900000 0x0 0x200000>; - no-map; - }; - - removed_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x5300000>; - no-map; - }; - - camera_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x500000>; - no-map; - }; - - wlan_mem: memory@86700000 { - reg = <0x0 0x86700000 0x0 0x100000>; - no-map; - }; - - ipa_fw_mem: memory@86800000 { - reg = <0x0 0x86800000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@86810000 { - reg = <0x0 0x86810000 0x0 0xa000>; - no-map; - }; - - gpu_mem: memory@8681a000 { - reg = <0x0 0x8681a000 0x0 0x2000>; - no-map; - }; - - npu_mem: memory@86900000 { - reg = <0x0 0x86900000 0x0 0x500000>; - no-map; - }; - - video_mem: memory@86e00000 { - reg = <0x0 0x86e00000 0x0 0x500000>; - no-map; - }; - - cvp_mem: memory@87300000 { - reg = <0x0 0x87300000 0x0 0x500000>; - no-map; - }; - - cdsp_mem: memory@87800000 { - reg = <0x0 0x87800000 0x0 0x1400000>; - no-map; - }; - - slpi_mem: memory@88c00000 { - reg = <0x0 0x88c00000 0x0 0x1500000>; - no-map; - }; - - adsp_mem: memory@8a100000 { - reg = <0x0 0x8a100000 0x0 0x1d00000>; - no-map; - }; - - spss_mem: memory@8be00000 { - reg = <0x0 0x8be00000 0x0 0x100000>; - no-map; - }; - - cdsp_secure_heap: memory@8bf00000 { - reg = <0x0 0x8bf00000 0x0 0x4600000>; - no-map; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - smp2p_cdsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_cdsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8250"; - reg = <0x0 0x00100000 0x0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "bi_tcxo_ao", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - }; - - ipcc: mailbox@408000 { - compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; - reg = <0 0x00408000 0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - }; - - rng: rng@793000 { - compatible = "qcom,prng-ee"; - reg = <0 0x00793000 0 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - qup_opp_table: qup-opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - }; - - gpi_dma2: dma-controller@800000 { - compatible = "qcom,sm8250-gpi-dma"; - reg = <0 0x00800000 0 0x70000>; - interrupts = , - , - , - , - , - , - , - , - , - ; - dma-channels = <10>; - dma-channel-mask = <0x3f>; - iommus = <&apps_smmu 0x76 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_2: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - iommus = <&apps_smmu 0x63 0x0>; - ranges; - status = "disabled"; - - i2c14: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_default>; - interrupts = ; - dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, - <&gpi_dma2 1 0 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi14: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - interrupts = ; - dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, - <&gpi_dma2 1 0 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c15: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c15_default>; - interrupts = ; - dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, - <&gpi_dma2 1 1 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi15: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - interrupts = ; - dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, - <&gpi_dma2 1 1 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c16: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c16_default>; - interrupts = ; - dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, - <&gpi_dma2 1 2 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi16: spi@888000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - interrupts = ; - dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, - <&gpi_dma2 1 2 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c17: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c17_default>; - interrupts = ; - dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, - <&gpi_dma2 1 3 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi17: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - interrupts = ; - dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, - <&gpi_dma2 1 3 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart17: serial@88c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart17_default>; - interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c18: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c18_default>; - interrupts = ; - dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, - <&gpi_dma2 1 4 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi18: spi@890000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - interrupts = ; - dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, - <&gpi_dma2 1 4 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart18: serial@890000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart18_default>; - interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c19: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c19_default>; - interrupts = ; - dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, - <&gpi_dma2 1 5 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi19: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - interrupts = ; - dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, - <&gpi_dma2 1 5 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma0: dma-controller@900000 { - compatible = "qcom,sm8250-gpi-dma"; - reg = <0 0x00900000 0 0x70000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <15>; - dma-channel-mask = <0x7ff>; - iommus = <&apps_smmu 0x5b6 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_0: geniqup@9c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x009c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - iommus = <&apps_smmu 0x5a3 0x0>; - ranges; - status = "disabled"; - - i2c0: i2c@980000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00980000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = ; - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, - <&gpi_dma0 1 0 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@980000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00980000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - interrupts = ; - dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, - <&gpi_dma0 1 0 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@984000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00984000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = ; - dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, - <&gpi_dma0 1 1 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@984000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00984000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - interrupts = ; - dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, - <&gpi_dma0 1 1 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@988000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00988000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = ; - dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, - <&gpi_dma0 1 2 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@988000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00988000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - interrupts = ; - dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, - <&gpi_dma0 1 2 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart2: serial@988000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x00988000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart2_default>; - interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c3: i2c@98c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0098c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = ; - dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, - <&gpi_dma0 1 3 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@98c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0098c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - interrupts = ; - dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, - <&gpi_dma0 1 3 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@990000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00990000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = ; - dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, - <&gpi_dma0 1 4 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@990000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00990000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - interrupts = ; - dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, - <&gpi_dma0 1 4 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@994000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00994000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = ; - dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, - <&gpi_dma0 1 5 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@994000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00994000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - interrupts = ; - dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, - <&gpi_dma0 1 5 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@998000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00998000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = ; - dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, - <&gpi_dma0 1 6 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@998000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00998000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - interrupts = ; - dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, - <&gpi_dma0 1 6 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart6: serial@998000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00998000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart6_default>; - interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c7: i2c@99c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0099c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; - dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, - <&gpi_dma0 1 7 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi7: spi@99c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0099c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - interrupts = ; - dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, - <&gpi_dma0 1 7 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gpi_dma1: dma-controller@a00000 { - compatible = "qcom,sm8250-gpi-dma"; - reg = <0 0x00a00000 0 0x70000>; - interrupts = , - , - , - , - , - , - , - , - , - ; - dma-channels = <10>; - dma-channel-mask = <0x3f>; - iommus = <&apps_smmu 0x56 0x0>; - #dma-cells = <3>; - status = "disabled"; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - iommus = <&apps_smmu 0x43 0x0>; - ranges; - status = "disabled"; - - i2c8: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = ; - dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, - <&gpi_dma1 1 0 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi8: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - interrupts = ; - dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, - <&gpi_dma1 1 0 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c9: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = ; - dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, - <&gpi_dma1 1 1 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi9: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - interrupts = ; - dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, - <&gpi_dma1 1 1 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = ; - dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, - <&gpi_dma1 1 2 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi10: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - interrupts = ; - dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, - <&gpi_dma1 1 2 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c11: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = ; - dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, - <&gpi_dma1 1 3 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi11: spi@a8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - interrupts = ; - dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, - <&gpi_dma1 1 3 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c12: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c12_default>; - interrupts = ; - dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, - <&gpi_dma1 1 4 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi12: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = ; - dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, - <&gpi_dma1 1 4 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart12: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a90000 0x0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart12_default>; - interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default>; - interrupts = ; - dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, - <&gpi_dma1 1 5 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi13: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - interrupts = ; - dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, - <&gpi_dma1 1 5 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8250-config-noc"; - reg = <0 0x01500000 0 0xa580>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sm8250-system-noc"; - reg = <0 0x01620000 0 0x1c200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@163d000 { - compatible = "qcom,sm8250-mc-virt"; - reg = <0 0x0163d000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8250-aggre1-noc"; - reg = <0 0x016e0000 0 0x1f180>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8250-aggre2-noc"; - reg = <0 0x01700000 0 0x33000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - compute_noc: interconnect@1733000 { - compatible = "qcom,sm8250-compute-noc"; - reg = <0 0x01733000 0 0xa180>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8250-mmss-noc"; - reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - pcie0: pci@1c00000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; - reg = <0 0x01c00000 0 0x3000>, - <0 0x60000000 0 0xf1d>, - <0 0x60000f20 0 0xa8>, - <0 0x60001000 0 0x1000>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "tbu", - "ddrss_sf_tbu"; - - iommus = <&apps_smmu 0x1c00 0x7f>; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; - - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_0_GDSC>; - - phys = <&pcie0_lane>; - phy-names = "pciephy"; - - perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; - - status = "disabled"; - }; - - pcie0_phy: phy@1c06000 { - compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; - reg = <0 0x01c06000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_WIFI_CLKREF_EN>, - <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie0_lane: phy@1c06200 { - reg = <0 0x1c06200 0 0x170>, /* tx */ - <0 0x1c06400 0 0x200>, /* rx */ - <0 0x1c06800 0 0x1f0>, /* pcs */ - <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; - }; - - pcie1: pci@1c08000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; - reg = <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <2>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ref", - "tbu", - "ddrss_sf_tbu"; - - assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; - assigned-clock-rates = <19200000>; - - iommus = <&apps_smmu 0x1c80 0x7f>; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; - - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_1_GDSC>; - - phys = <&pcie1_lane>; - phy-names = "pciephy"; - - perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; - - status = "disabled"; - }; - - pcie1_phy: phy@1c0e000 { - compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; - reg = <0 0x01c0e000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, - <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie1_lane: phy@1c0e200 { - reg = <0 0x1c0e200 0 0x170>, /* tx0 */ - <0 0x1c0e400 0 0x200>, /* rx0 */ - <0 0x1c0ea00 0 0x1f0>, /* pcs */ - <0 0x1c0e600 0 0x170>, /* tx1 */ - <0 0x1c0e800 0 0x200>, /* rx1 */ - <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; - }; - - pcie2: pci@1c10000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; - reg = <0 0x01c10000 0 0x3000>, - <0 0x64000000 0 0xf1d>, - <0 0x64000f20 0 0xa8>, - <0 0x64001000 0 0x1000>, - <0 0x64100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; - device_type = "pci"; - linux,pci-domain = <2>; - bus-range = <0x00 0xff>; - num-lanes = <2>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, - <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, - <&gcc GCC_PCIE_2_AUX_CLK>, - <&gcc GCC_PCIE_2_CFG_AHB_CLK>, - <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_2_SLV_AXI_CLK>, - <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_MDM_CLKREF_EN>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ref", - "tbu", - "ddrss_sf_tbu"; - - assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; - assigned-clock-rates = <19200000>; - - iommus = <&apps_smmu 0x1d00 0x7f>; - iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, - <0x100 &apps_smmu 0x1d01 0x1>; - - resets = <&gcc GCC_PCIE_2_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_2_GDSC>; - - phys = <&pcie2_lane>; - phy-names = "pciephy"; - - perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_default_state>; - - status = "disabled"; - }; - - pcie2_phy: phy@1c16000 { - compatible = "qcom,sm8250-qmp-modem-pcie-phy"; - reg = <0 0x1c16000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_2_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MDM_CLKREF_EN>, - <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_2_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie2_lane: phy@1c16200 { - reg = <0 0x1c16200 0 0x170>, /* tx0 */ - <0 0x1c16400 0 0x200>, /* rx0 */ - <0 0x1c16a00 0 0x1f0>, /* pcs */ - <0 0x1c16600 0 0x170>, /* tx1 */ - <0 0x1c16800 0 0x200>, /* rx1 */ - <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ - clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_2_pipe_clk"; - }; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8250-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8250-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8250-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x01f40000 0x0 0x40000>; - #hwlock-cells = <1>; - }; - - wsamacro: codec@3240000 { - compatible = "qcom,sm8250-lpass-wsa-macro"; - reg = <0 0x03240000 0 0x1000>; - clocks = <&audiocc 1>, - <&audiocc 0>, - <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&aoncc 0>, - <&vamacro>; - - clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; - - #clock-cells = <0>; - clock-frequency = <9600000>; - clock-output-names = "mclk"; - #sound-dai-cells = <1>; - - pinctrl-names = "default"; - pinctrl-0 = <&wsa_swr_active>; - }; - - swr0: soundwire-controller@3250000 { - reg = <0 0x03250000 0 0x2000>; - compatible = "qcom,soundwire-v1.5.1"; - interrupts = ; - clocks = <&wsamacro>; - clock-names = "iface"; - - qcom,din-ports = <2>; - qcom,dout-ports = <6>; - - qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; - qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; - qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; - qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; - - #sound-dai-cells = <1>; - #address-cells = <2>; - #size-cells = <0>; - }; - - audiocc: clock-controller@3300000 { - compatible = "qcom,sm8250-lpass-audiocc"; - reg = <0 0x03300000 0 0x30000>; - #clock-cells = <1>; - clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; - clock-names = "core", "audio", "bus"; - }; - - vamacro: codec@3370000 { - compatible = "qcom,sm8250-lpass-va-macro"; - reg = <0 0x03370000 0 0x1000>; - clocks = <&aoncc 0>, - <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; - - clock-names = "mclk", "macro", "dcodec"; - - #clock-cells = <0>; - clock-frequency = <9600000>; - clock-output-names = "fsgen"; - #sound-dai-cells = <1>; - }; - - rxmacro: rxmacro@3200000 { - pinctrl-names = "default"; - pinctrl-0 = <&rx_swr_active>; - compatible = "qcom,sm8250-lpass-rx-macro"; - reg = <0 0x3200000 0 0x1000>; - - clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&vamacro>; - - clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; - - #clock-cells = <0>; - clock-frequency = <9600000>; - clock-output-names = "mclk"; - #sound-dai-cells = <1>; - }; - - swr1: soundwire-controller@3210000 { - reg = <0 0x3210000 0 0x2000>; - compatible = "qcom,soundwire-v1.5.1"; - interrupts = ; - clocks = <&rxmacro>; - clock-names = "iface"; - label = "RX"; - qcom,din-ports = <0>; - qcom,dout-ports = <5>; - - qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; - qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; - qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; - qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; - qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; - qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; - qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; - qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; - - #sound-dai-cells = <1>; - #address-cells = <2>; - #size-cells = <0>; - }; - - txmacro: txmacro@3220000 { - pinctrl-names = "default"; - pinctrl-0 = <&tx_swr_active>; - compatible = "qcom,sm8250-lpass-tx-macro"; - reg = <0 0x3220000 0 0x1000>; - - clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&vamacro>; - - clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; - - #clock-cells = <0>; - clock-frequency = <9600000>; - clock-output-names = "mclk"; - #address-cells = <2>; - #size-cells = <2>; - #sound-dai-cells = <1>; - }; - - /* tx macro */ - swr2: soundwire-controller@3230000 { - reg = <0 0x3230000 0 0x2000>; - compatible = "qcom,soundwire-v1.5.1"; - interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "core"; - - clocks = <&txmacro>; - clock-names = "iface"; - label = "TX"; - - qcom,din-ports = <5>; - qcom,dout-ports = <0>; - qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; - qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; - qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; - qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; - qcom,port-offset = <1>; - #sound-dai-cells = <1>; - #address-cells = <2>; - #size-cells = <0>; - }; - - aoncc: clock-controller@3380000 { - compatible = "qcom,sm8250-lpass-aoncc"; - reg = <0 0x03380000 0 0x40000>; - #clock-cells = <1>; - clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; - clock-names = "core", "audio", "bus"; - }; - - lpass_tlmm: pinctrl@33c0000{ - compatible = "qcom,sm8250-lpass-lpi-pinctrl"; - reg = <0 0x033c0000 0x0 0x20000>, - <0 0x03550000 0x0 0x10000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&lpass_tlmm 0 0 14>; - - clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; - clock-names = "core", "audio"; - - wsa_swr_active: wsa-swr-active-pins { - clk { - pins = "gpio10"; - function = "wsa_swr_clk"; - drive-strength = <2>; - slew-rate = <1>; - bias-disable; - }; - - data { - pins = "gpio11"; - function = "wsa_swr_data"; - drive-strength = <2>; - slew-rate = <1>; - bias-bus-hold; - - }; - }; - - wsa_swr_sleep: wsa-swr-sleep-pins { - clk { - pins = "gpio10"; - function = "wsa_swr_clk"; - drive-strength = <2>; - input-enable; - bias-pull-down; - }; - - data { - pins = "gpio11"; - function = "wsa_swr_data"; - drive-strength = <2>; - input-enable; - bias-pull-down; - - }; - }; - - dmic01_active: dmic01-active-pins { - clk { - pins = "gpio6"; - function = "dmic1_clk"; - drive-strength = <8>; - output-high; - }; - data { - pins = "gpio7"; - function = "dmic1_data"; - drive-strength = <8>; - input-enable; - }; - }; - - dmic01_sleep: dmic01-sleep-pins { - clk { - pins = "gpio6"; - function = "dmic1_clk"; - drive-strength = <2>; - bias-disable; - output-low; - }; - - data { - pins = "gpio7"; - function = "dmic1_data"; - drive-strength = <2>; - pull-down; - input-enable; - }; - }; - - rx_swr_active: rx_swr-active-pins { - clk { - pins = "gpio3"; - function = "swr_rx_clk"; - drive-strength = <2>; - slew-rate = <1>; - bias-disable; - }; - - data { - pins = "gpio4", "gpio5"; - function = "swr_rx_data"; - drive-strength = <2>; - slew-rate = <1>; - bias-bus-hold; - }; - }; - - tx_swr_active: tx_swr-active-pins { - clk { - pins = "gpio0"; - function = "swr_tx_clk"; - drive-strength = <2>; - slew-rate = <1>; - bias-disable; - }; - - data { - pins = "gpio1", "gpio2"; - function = "swr_tx_data"; - drive-strength = <2>; - slew-rate = <1>; - bias-bus-hold; - }; - }; - - tx_swr_sleep: tx_swr-sleep-pins { - clk { - pins = "gpio0"; - function = "swr_tx_clk"; - drive-strength = <2>; - input-enable; - bias-pull-down; - }; - - data1 { - pins = "gpio1"; - function = "swr_tx_data"; - drive-strength = <2>; - input-enable; - bias-bus-hold; - }; - - data2 { - pins = "gpio2"; - function = "swr_tx_data"; - drive-strength = <2>; - input-enable; - bias-pull-down; - }; - }; - }; - - slimbam: dma@3a84000 { - compatible = "qcom,bam-v1.7.0"; - qcom,controlled-remotely; - reg = <0 0x3a84000 0 0x2a000>; - num-channels = <31>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,num-ees = <2>; - iommus = <&apps_smmu 0x1826 0x0>; - }; - - slim: slim@3ac0000 { - compatible = "qcom,slim-ngd-v2.2.0"; - reg = <0 0x3ac0000 0 0x2c000>; - interrupts = ; - - qcom,apps-ch-pipes = <0x780000>; - qcom,ea-pc = <0x270>; - status = "okay"; - dmas = <&slimbam 3>, <&slimbam 4>, - <&slimbam 5>, <&slimbam 6>; - dma-names = "rx", "tx", "tx2", "rx2"; - - iommus = <&apps_smmu 0x1826 0x0>; - #address-cells = <1>; - #size-cells = <0>; - - ngd@1 { - reg = <1>; - #address-cells = <2>; - #size-cells = <0>; - }; - }; - - slimbam: dma@3a84000 { - compatible = "qcom,bam-v1.7.0"; - qcom,controlled-remotely; - reg = <0 0x3a84000 0 0x2a000>; - num-channels = <31>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,num-ees = <2>; - iommus = <&apps_smmu 0x1826 0x0>; - }; - - slim: slim@3ac0000 { - compatible = "qcom,slim-ngd-v2.2.0"; - reg = <0 0x3ac0000 0 0x2c000>; - interrupts = ; - - qcom,apps-ch-pipes = <0x780000>; - qcom,ea-pc = <0x270>; - status = "okay"; - dmas = <&slimbam 3>, <&slimbam 4>, - <&slimbam 5>, <&slimbam 6>; - dma-names = "rx", "tx", "tx2", "rx2"; - - iommus = <&apps_smmu 0x1826 0x0>; - #address-cells = <1>; - #size-cells = <0>; - - ngd@1 { - reg = <1>; - #address-cells = <2>; - #size-cells = <0>; - }; - }; - - gpu: gpu@3d00000 { - compatible = "qcom,adreno-650.2", - "qcom,adreno"; - - reg = <0 0x03d00000 0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = ; - - iommus = <&adreno_smmu 0 0x401>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - - status = "disabled"; - - zap-shader { - memory-region = <&gpu_mem>; - }; - - /* note: downstream checks gpu binning for 670 Mhz */ - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-670000000 { - opp-hz = /bits/ 64 <670000000>; - opp-level = ; - }; - - opp-587000000 { - opp-hz = /bits/ 64 <587000000>; - opp-level = ; - }; - - opp-525000000 { - opp-hz = /bits/ 64 <525000000>; - opp-level = ; - }; - - opp-490000000 { - opp-hz = /bits/ 64 <490000000>; - opp-level = ; - }; - - opp-441600000 { - opp-hz = /bits/ 64 <441600000>; - opp-level = ; - }; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-level = ; - }; - - opp-305000000 { - opp-hz = /bits/ 64 <305000000>; - opp-level = ; - }; - }; - }; - - gmu: gmu@3d6a000 { - compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; - - reg = <0 0x03d6a000 0 0x30000>, - <0 0x3de0000 0 0x10000>, - <0 0xb290000 0 0x10000>, - <0 0xb490000 0 0x10000>; - reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5 0x400>; - - operating-points-v2 = <&gmu_opp_table>; - - status = "disabled"; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = ; - }; - }; - }; - - gpucc: clock-controller@3d90000 { - compatible = "qcom,sm8250-gpucc"; - reg = <0 0x03d90000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - adreno_smmu: iommu@3da0000 { - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; - reg = <0 0x03da0000 0 0x10000>; - #iommu-cells = <2>; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; - clock-names = "ahb", "bus", "iface"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - slpi: remoteproc@5c00000 { - compatible = "qcom,sm8250-slpi-pas"; - reg = <0 0x05c00000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8250_LCX>, - <&rpmhpd SM8250_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "slpi"; - qcom,remote-pid = <3>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0541 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0542 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0543 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - - cdsp: remoteproc@8300000 { - compatible = "qcom,sm8250-cdsp-pas"; - reg = <0 0x08300000 0 0x10000>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8250_CX>; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_cdsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "cdsp"; - qcom,remote-pid = <5>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x1001 0x0460>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x1002 0x0460>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1003 0x0460>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1004 0x0460>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1005 0x0460>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x1006 0x0460>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x1007 0x0460>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x1008 0x0460>; - }; - - /* note: secure cb9 in downstream */ - }; - }; - }; - - sound: sound { - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8250-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_2_hsphy: phy@88e4000 { - compatible = "qcom,sm8250-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e4000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - }; - - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sm8250-qmp-usb3-dp-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x40>, - <0 0x088ea000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - orientation-switch; - - usb_1_ssphy: usb3-phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - - dp_phy: dp-phy@88ea200 { - reg = <0 0x088ea200 0 0x200>, - <0 0x088ea400 0 0x200>, - <0 0x088eac00 0 0x400>, - <0 0x088ea600 0 0x200>, - <0 0x088ea800 0 0x200>, - <0 0x088eaa00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - - port { - usb_1_qmp_switch: endpoint { - }; - }; - }; - - usb_2_qmpphy: phy@88eb000 { - compatible = "qcom,sm8250-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_EN>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: phy@88eb200 { - reg = <0 0x088eb200 0 0x200>, - <0 0x088eb400 0 0x200>, - <0 0x088eb800 0 0x800>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - sdhc_2: sdhci@8804000 { - compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x08804000 0 0x1000>; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "core", "xo"; - iommus = <&apps_smmu 0x4a0 0x0>; - qcom,dll-config = <0x0007642c>; - qcom,ddr-config = <0x80040868>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&sdhc2_opp_table>; - - status = "disabled"; - - sdhc2_opp_table: sdhc2-opp-table { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-202000000 { - opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - }; - }; - - dc_noc: interconnect@90c0000 { - compatible = "qcom,sm8250-dc-noc"; - reg = <0 0x090c0000 0 0x4200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9100000 { - compatible = "qcom,sm8250-gem-noc"; - reg = <0 0x09100000 0 0xb4000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - npu_noc: interconnect@9990000 { - compatible = "qcom,sm8250-npu-noc"; - reg = <0 0x09990000 0 0x1600>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_EN>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, - <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - system-cache-controller@9200000 { - compatible = "qcom,sm8250-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_EN>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>, - <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x20 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - venus: video-codec@aa00000 { - compatible = "qcom,sm8250-venus"; - reg = <0 0x0aa00000 0 0x100000>; - interrupts = ; - power-domains = <&videocc MVS0C_GDSC>, - <&videocc MVS0_GDSC>, - <&rpmhpd SM8250_MX>; - power-domain-names = "venus", "vcodec0", "mx"; - operating-points-v2 = <&venus_opp_table>; - - clocks = <&gcc GCC_VIDEO_AXI0_CLK>, - <&videocc VIDEO_CC_MVS0C_CLK>, - <&videocc VIDEO_CC_MVS0_CLK>; - clock-names = "iface", "core", "vcodec0_core"; - - interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, - <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "cpu-cfg", "video-mem"; - - iommus = <&apps_smmu 0x2100 0x0400>; - memory-region = <&video_mem>; - - resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, - <&videocc VIDEO_CC_MVS0C_CLK_ARES>; - reset-names = "bus", "core"; - - status = "disabled"; - - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; - - venus_opp_table: venus-opp-table { - compatible = "operating-points-v2"; - - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-1014000000 { - opp-hz = /bits/ 64 <1014000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-1098000000 { - opp-hz = /bits/ 64 <1098000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-1332000000 { - opp-hz = /bits/ 64 <1332000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; - - videocc: clock-controller@abf0000 { - compatible = "qcom,sm8250-videocc"; - reg = <0 0x0abf0000 0 0x10000>; - clocks = <&gcc GCC_VIDEO_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>; - power-domains = <&rpmhpd SM8250_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - mdss: mdss@ae00000 { - compatible = "qcom,sm8250-mdss"; - reg = <0 0x0ae00000 0 0x1000>; - reg-names = "mdss"; - - interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, - <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; - - power-domains = <&dispcc MDSS_GDSC>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "nrt_bus", "core"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <460000000>; - - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - iommus = <&apps_smmu 0x820 0x402>; - - status = "disabled"; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mdss_mdp: mdp@ae01000 { - compatible = "qcom,sm8250-dpu"; - reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <460000000>, - <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; - - interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - - port@2 { - reg = <2>; - dpu_intf0_out: endpoint { - remote-endpoint = <&dp_in>; - }; - }; - }; - - mdp_opp_table: mdp-opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-345000000 { - opp-hz = /bits/ 64 <345000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-460000000 { - opp-hz = /bits/ 64 <460000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; - - mdss_dp: displayport-controller@ae90000{ - cell-index = <0>; - compatible = "qcom,sc7180-dp"; - - reg = <0 0xae90000 0 0x1400>; - - interrupt-parent = <&mdss>; - interrupts = <12>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; - clock-names = "core_iface", "core_aux", - "ctrl_link", "ctrl_link_iface", "stream_pixel"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; - assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; - - phys = <&dp_phy>; - phy-names = "dp"; - - operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dp_in: endpoint { - remote-endpoint = - <&dpu_intf0_out>; - }; - }; - - port@1 { - reg = <1>; - dp_out: endpoint { }; - }; - }; - - dp_opp_table: dp-opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; - - dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae94000 0 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; - - operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; - - phys = <&dsi0_phy>; - phy-names = "dsi"; - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&dpu_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - }; - }; - }; - }; - - dsi0_phy: dsi-phy@ae94400 { - compatible = "qcom,dsi-phy-7nm"; - reg = <0 0x0ae94400 0 0x200>, - <0 0x0ae94600 0 0x280>, - <0 0x0ae94900 0 0x260>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; - - status = "disabled"; - }; - - dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae96000 0 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; - - operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; - - phys = <&dsi1_phy>; - phy-names = "dsi"; - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi1_in: endpoint { - remote-endpoint = <&dpu_intf2_out>; - }; - }; - - port@1 { - reg = <1>; - dsi1_out: endpoint { - }; - }; - }; - }; - - dsi1_phy: dsi-phy@ae96400 { - compatible = "qcom,dsi-phy-7nm"; - reg = <0 0x0ae96400 0 0x200>, - <0 0x0ae96600 0 0x280>, - <0 0x0ae96900 0 0x260>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; - - status = "disabled"; - - dsi_opp_table: dsi-opp-table { - compatible = "operating-points-v2"; - - opp-187500000 { - opp-hz = /bits/ 64 <187500000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-358000000 { - opp-hz = /bits/ 64 <358000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - }; - }; - }; - - dispcc: clock-controller@af00000 { - compatible = "qcom,sm8250-dispcc"; - reg = <0 0x0af00000 0 0x10000>; - power-domains = <&rpmhpd SM8250_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, - <&dsi1_phy 0>, - <&dsi1_phy 1>, - <&dp_phy 0>, - <&dp_phy 1>; - clock-names = "bi_tcxo", - "dsi0_phy_pll_out_byteclk", - "dsi0_phy_pll_out_dsiclk", - "dsi1_phy_pll_out_byteclk", - "dsi1_phy_pll_out_dsiclk", - "dp_phy_pll_link_clk", - "dp_phy_pll_vco_div_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8250-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; - qcom,pdc-ranges = <0 480 94>, <94 609 31>, - <125 63 1>, <126 716 12>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <9>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8250-aoss-qmp"; - reg = <0 0x0c300000 0 0x400>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_AOP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - }; - - sram@c3f0000 { - compatible = "qcom,rpmh-stats"; - reg = <0 0x0c3f0000 0 0x400>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c440000 0x0 0x0001100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x0100000>, - <0x0 0x0e700000 0x0 0x00a0000>, - <0x0 0x0c40a000 0x0 0x0026000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8250-pinctrl"; - reg = <0 0x0f100000 0 0x300000>, - <0 0x0f500000 0 0x300000>, - <0 0x0f900000 0 0x300000>; - reg-names = "west", "south", "north"; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 181>; - wakeup-parent = <&pdc>; - - pri_mi2s_active: pri-mi2s-active { - sclk { - pins = "gpio138"; - function = "mi2s0_sck"; - drive-strength = <8>; - bias-disable; - }; - - ws { - pins = "gpio141"; - function = "mi2s0_ws"; - drive-strength = <8>; - output-high; - }; - - data0 { - pins = "gpio139"; - function = "mi2s0_data0"; - drive-strength = <8>; - bias-disable; - output-high; - }; - - data1 { - pins = "gpio140"; - function = "mi2s0_data1"; - drive-strength = <8>; - output-high; - }; - }; - - qup_i2c0_default: qup-i2c0-default { - mux { - pins = "gpio28", "gpio29"; - function = "qup0"; - }; - - config { - pins = "gpio28", "gpio29"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins = "gpio4", "gpio5"; - function = "qup1"; - }; - - config { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c2_default: qup-i2c2-default { - mux { - pins = "gpio115", "gpio116"; - function = "qup2"; - }; - - config { - pins = "gpio115", "gpio116"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c3_default: qup-i2c3-default { - mux { - pins = "gpio119", "gpio120"; - function = "qup3"; - }; - - config { - pins = "gpio119", "gpio120"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c4_default: qup-i2c4-default { - mux { - pins = "gpio8", "gpio9"; - function = "qup4"; - }; - - config { - pins = "gpio8", "gpio9"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c5_default: qup-i2c5-default { - mux { - pins = "gpio12", "gpio13"; - function = "qup5"; - }; - - config { - pins = "gpio12", "gpio13"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c6_default: qup-i2c6-default { - mux { - pins = "gpio16", "gpio17"; - function = "qup6"; - }; - - config { - pins = "gpio16", "gpio17"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c7_default: qup-i2c7-default { - mux { - pins = "gpio20", "gpio21"; - function = "qup7"; - }; - - config { - pins = "gpio20", "gpio21"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c8_default: qup-i2c8-default { - mux { - pins = "gpio24", "gpio25"; - function = "qup8"; - }; - - config { - pins = "gpio24", "gpio25"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c9_default: qup-i2c9-default { - mux { - pins = "gpio125", "gpio126"; - function = "qup9"; - }; - - config { - pins = "gpio125", "gpio126"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c10_default: qup-i2c10-default { - mux { - pins = "gpio129", "gpio130"; - function = "qup10"; - }; - - config { - pins = "gpio129", "gpio130"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c11_default: qup-i2c11-default { - mux { - pins = "gpio60", "gpio61"; - function = "qup11"; - }; - - config { - pins = "gpio60", "gpio61"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c12_default: qup-i2c12-default { - mux { - pins = "gpio32", "gpio33"; - function = "qup12"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c13_default: qup-i2c13-default { - mux { - pins = "gpio36", "gpio37"; - function = "qup13"; - }; - - config { - pins = "gpio36", "gpio37"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c14_default: qup-i2c14-default { - mux { - pins = "gpio40", "gpio41"; - function = "qup14"; - }; - - config { - pins = "gpio40", "gpio41"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c15_default: qup-i2c15-default { - mux { - pins = "gpio44", "gpio45"; - function = "qup15"; - }; - - config { - pins = "gpio44", "gpio45"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c16_default: qup-i2c16-default { - mux { - pins = "gpio48", "gpio49"; - function = "qup16"; - }; - - config { - pins = "gpio48", "gpio49"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c17_default: qup-i2c17-default { - mux { - pins = "gpio52", "gpio53"; - function = "qup17"; - }; - - config { - pins = "gpio52", "gpio53"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c18_default: qup-i2c18-default { - mux { - pins = "gpio56", "gpio57"; - function = "qup18"; - }; - - config { - pins = "gpio56", "gpio57"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c19_default: qup-i2c19-default { - mux { - pins = "gpio0", "gpio1"; - function = "qup19"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_spi0_cs: qup-spi0-cs { - pins = "gpio31"; - function = "qup0"; - }; - - qup_spi0_cs_gpio: qup-spi0-cs-gpio { - pins = "gpio31"; - function = "gpio"; - }; - - qup_spi0_data_clk: qup-spi0-data-clk { - pins = "gpio28", "gpio29", - "gpio30"; - function = "qup0"; - }; - - qup_spi1_cs: qup-spi1-cs { - pins = "gpio7"; - function = "qup1"; - }; - - qup_spi1_cs_gpio: qup-spi1-cs-gpio { - pins = "gpio7"; - function = "gpio"; - }; - - qup_spi1_data_clk: qup-spi1-data-clk { - pins = "gpio4", "gpio5", - "gpio6"; - function = "qup1"; - }; - - qup_spi2_cs: qup-spi2-cs { - pins = "gpio118"; - function = "qup2"; - }; - - qup_spi2_cs_gpio: qup-spi2-cs-gpio { - pins = "gpio118"; - function = "gpio"; - }; - - qup_spi2_data_clk: qup-spi2-data-clk { - pins = "gpio115", "gpio116", - "gpio117"; - function = "qup2"; - }; - - qup_spi3_cs: qup-spi3-cs { - pins = "gpio122"; - function = "qup3"; - }; - - qup_spi3_cs_gpio: qup-spi3-cs-gpio { - pins = "gpio122"; - function = "gpio"; - }; - - qup_spi3_data_clk: qup-spi3-data-clk { - pins = "gpio119", "gpio120", - "gpio121"; - function = "qup3"; - }; - - qup_spi4_cs: qup-spi4-cs { - pins = "gpio11"; - function = "qup4"; - }; - - qup_spi4_cs_gpio: qup-spi4-cs-gpio { - pins = "gpio11"; - function = "gpio"; - }; - - qup_spi4_data_clk: qup-spi4-data-clk { - pins = "gpio8", "gpio9", - "gpio10"; - function = "qup4"; - }; - - qup_spi5_cs: qup-spi5-cs { - pins = "gpio15"; - function = "qup5"; - }; - - qup_spi5_cs_gpio: qup-spi5-cs-gpio { - pins = "gpio15"; - function = "gpio"; - }; - - qup_spi5_data_clk: qup-spi5-data-clk { - pins = "gpio12", "gpio13", - "gpio14"; - function = "qup5"; - }; - - qup_spi6_cs: qup-spi6-cs { - pins = "gpio19"; - function = "qup6"; - }; - - qup_spi6_cs_gpio: qup-spi6-cs-gpio { - pins = "gpio19"; - function = "gpio"; - }; - - qup_spi6_data_clk: qup-spi6-data-clk { - pins = "gpio16", "gpio17", - "gpio18"; - function = "qup6"; - }; - - qup_spi7_cs: qup-spi7-cs { - pins = "gpio23"; - function = "qup7"; - }; - - qup_spi7_cs_gpio: qup-spi7-cs-gpio { - pins = "gpio23"; - function = "gpio"; - }; - - qup_spi7_data_clk: qup-spi7-data-clk { - pins = "gpio20", "gpio21", - "gpio22"; - function = "qup7"; - }; - - qup_spi8_cs: qup-spi8-cs { - pins = "gpio27"; - function = "qup8"; - }; - - qup_spi8_cs_gpio: qup-spi8-cs-gpio { - pins = "gpio27"; - function = "gpio"; - }; - - qup_spi8_data_clk: qup-spi8-data-clk { - pins = "gpio24", "gpio25", - "gpio26"; - function = "qup8"; - }; - - qup_spi9_cs: qup-spi9-cs { - pins = "gpio128"; - function = "qup9"; - }; - - qup_spi9_cs_gpio: qup-spi9-cs-gpio { - pins = "gpio128"; - function = "gpio"; - }; - - qup_spi9_data_clk: qup-spi9-data-clk { - pins = "gpio125", "gpio126", - "gpio127"; - function = "qup9"; - }; - - qup_spi10_cs: qup-spi10-cs { - pins = "gpio132"; - function = "qup10"; - }; - - qup_spi10_cs_gpio: qup-spi10-cs-gpio { - pins = "gpio132"; - function = "gpio"; - }; - - qup_spi10_data_clk: qup-spi10-data-clk { - pins = "gpio129", "gpio130", - "gpio131"; - function = "qup10"; - }; - - qup_spi11_cs: qup-spi11-cs { - pins = "gpio63"; - function = "qup11"; - }; - - qup_spi11_cs_gpio: qup-spi11-cs-gpio { - pins = "gpio63"; - function = "gpio"; - }; - - qup_spi11_data_clk: qup-spi11-data-clk { - pins = "gpio60", "gpio61", - "gpio62"; - function = "qup11"; - }; - - qup_spi12_cs: qup-spi12-cs { - pins = "gpio35"; - function = "qup12"; - }; - - qup_spi12_cs_gpio: qup-spi12-cs-gpio { - pins = "gpio35"; - function = "gpio"; - }; - - qup_spi12_data_clk: qup-spi12-data-clk { - pins = "gpio32", "gpio33", - "gpio34"; - function = "qup12"; - }; - - qup_spi13_cs: qup-spi13-cs { - pins = "gpio39"; - function = "qup13"; - }; - - qup_spi13_cs_gpio: qup-spi13-cs-gpio { - pins = "gpio39"; - function = "gpio"; - }; - - qup_spi13_data_clk: qup-spi13-data-clk { - pins = "gpio36", "gpio37", - "gpio38"; - function = "qup13"; - }; - - qup_spi14_cs: qup-spi14-cs { - pins = "gpio43"; - function = "qup14"; - }; - - qup_spi14_cs_gpio: qup-spi14-cs-gpio { - pins = "gpio43"; - function = "gpio"; - }; - - qup_spi14_data_clk: qup-spi14-data-clk { - pins = "gpio40", "gpio41", - "gpio42"; - function = "qup14"; - }; - - qup_spi15_cs: qup-spi15-cs { - pins = "gpio47"; - function = "qup15"; - }; - - qup_spi15_cs_gpio: qup-spi15-cs-gpio { - pins = "gpio47"; - function = "gpio"; - }; - - qup_spi15_data_clk: qup-spi15-data-clk { - pins = "gpio44", "gpio45", - "gpio46"; - function = "qup15"; - }; - - qup_spi16_cs: qup-spi16-cs { - pins = "gpio51"; - function = "qup16"; - }; - - qup_spi16_cs_gpio: qup-spi16-cs-gpio { - pins = "gpio51"; - function = "gpio"; - }; - - qup_spi16_data_clk: qup-spi16-data-clk { - pins = "gpio48", "gpio49", - "gpio50"; - function = "qup16"; - }; - - qup_spi17_cs: qup-spi17-cs { - pins = "gpio55"; - function = "qup17"; - }; - - qup_spi17_cs_gpio: qup-spi17-cs-gpio { - pins = "gpio55"; - function = "gpio"; - }; - - qup_spi17_data_clk: qup-spi17-data-clk { - pins = "gpio52", "gpio53", - "gpio54"; - function = "qup17"; - }; - - qup_spi18_cs: qup-spi18-cs { - pins = "gpio59"; - function = "qup18"; - }; - - qup_spi18_cs_gpio: qup-spi18-cs-gpio { - pins = "gpio59"; - function = "gpio"; - }; - - qup_spi18_data_clk: qup-spi18-data-clk { - pins = "gpio56", "gpio57", - "gpio58"; - function = "qup18"; - }; - - qup_spi19_cs: qup-spi19-cs { - pins = "gpio3"; - function = "qup19"; - }; - - qup_spi19_cs_gpio: qup-spi19-cs-gpio { - pins = "gpio3"; - function = "gpio"; - }; - - qup_spi19_data_clk: qup-spi19-data-clk { - pins = "gpio0", "gpio1", - "gpio2"; - function = "qup19"; - }; - - qup_uart2_default: qup-uart2-default { - mux { - pins = "gpio117", "gpio118"; - function = "qup2"; - }; - }; - - qup_uart6_default: qup-uart6-default { - mux { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - function = "qup6"; - }; - }; - - qup_uart12_default: qup-uart12-default { - mux { - pins = "gpio34", "gpio35"; - function = "qup12"; - }; - }; - - qup_uart17_default: qup-uart17-default { - mux { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - function = "qup17"; - }; - }; - - qup_uart18_default: qup-uart18-default { - mux { - pins = "gpio58", "gpio59"; - function = "qup18"; - }; - }; - - tert_mi2s_active: tert-mi2s-active { - sck { - pins = "gpio133"; - function = "mi2s2_sck"; - drive-strength = <8>; - bias-disable; - }; - - data0 { - pins = "gpio134"; - function = "mi2s2_data0"; - drive-strength = <8>; - bias-disable; - output-high; - }; - - ws { - pins = "gpio135"; - function = "mi2s2_ws"; - drive-strength = <8>; - output-high; - }; - }; - - sdc2_sleep_state: sdc2-sleep { - clk { - pins = "sdc2_clk"; - drive-strength = <2>; - bias-disable; - }; - - cmd { - pins = "sdc2_cmd"; - drive-strength = <2>; - bias-pull-up; - }; - - data { - pins = "sdc2_data"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_default_state: pcie0-default { - perst { - pins = "gpio79"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq { - pins = "gpio80"; - function = "pci_e0"; - drive-strength = <2>; - bias-pull-up; - }; - - wake { - pins = "gpio81"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_default_state: pcie1-default { - perst { - pins = "gpio82"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq { - pins = "gpio83"; - function = "pci_e1"; - drive-strength = <2>; - bias-pull-up; - }; - - wake { - pins = "gpio84"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie2_default_state: pcie2-default { - perst { - pins = "gpio85"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq { - pins = "gpio86"; - function = "pci_e2"; - drive-strength = <2>; - bias-pull-up; - }; - - wake { - pins = "gpio87"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - adsp: remoteproc@17300000 { - compatible = "qcom,sm8250-adsp-pas"; - reg = <0 0x17300000 0 0x100>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8250_LCX>, - <&rpmhpd SM8250_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <2>; - - apr { - compatible = "qcom,apr-v2"; - qcom,glink-channels = "apr_audio_svc"; - qcom,apr-domain = ; - #address-cells = <1>; - #size-cells = <0>; - qcom,intents = <512 20>; - - apr-service@3 { - reg = ; - compatible = "qcom,q6core"; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - }; - - q6afe: apr-service@4 { - compatible = "qcom,q6afe"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - q6afedai: dais { - compatible = "qcom,q6afe-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - }; - - q6afecc: cc { - compatible = "qcom,q6afe-clocks"; - #clock-cells = <2>; - }; - }; - - q6asm: apr-service@7 { - compatible = "qcom,q6asm"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - q6asmdai: dais { - compatible = "qcom,q6asm-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - iommus = <&apps_smmu 0x1801 0x0>; - }; - }; - - q6adm: apr-service@8 { - compatible = "qcom,q6adm"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - q6routing: routing { - compatible = "qcom,q6adm-routing"; - #sound-dai-cells = <0>; - }; - }; - }; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1803 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1804 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1805 0x0>; - }; - }; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; - - watchdog@17c10000 { - compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; - clocks = <&sleep_clk>; - interrupts = ; - }; - - timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17c21000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17c23000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17c25000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17c27000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17c29000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x17c2b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x17c2d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , , - , ; - - rpmhcc: clock-controller { - compatible = "qcom,sm8250-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8250-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - - epss_l3: interconnect@18590000 { - compatible = "qcom,sm8250-epss-l3"; - reg = <0 0x18590000 0 0x1000>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@18591000 { - compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0 0x18591000 0 0x1000>, - <0 0x18592000 0 0x1000>, - <0 0x18593000 0 0x1000>; - reg-names = "freq-domain0", "freq-domain1", - "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0 0x01dc4000 0 0x24000>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - iommus = <&apps_smmu 0x584 0x0011>, - <&apps_smmu 0x586 0x0011>, - <&apps_smmu 0x594 0x0011>, - <&apps_smmu 0x596 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - - crypto: crypto@1dfa000 { - compatible = "qcom,sm8250-qce"; - reg = <0 0x01dfa000 0 0x6000>; - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x584 0x0011>, - <&apps_smmu 0x586 0x0011>, - <&apps_smmu 0x594 0x0011>, - <&apps_smmu 0x596 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "memory"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 14>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 15>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - compute-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - compute_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - npu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - npu_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 8>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; -- GitLab