diff --git a/runtime/interpreter/mterp/Makefile_mterp b/runtime/interpreter/mterp/Makefile_mterp
deleted file mode 100644
index ac8da69742d03b6f4ef59e4322d35d0d40b7e4c8..0000000000000000000000000000000000000000
--- a/runtime/interpreter/mterp/Makefile_mterp
+++ /dev/null
@@ -1,49 +0,0 @@
-# Copyright (C) 2016 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-#
-# Makefile for the Art fast interpreter.  This is not currently
-# integrated into the build system.
-#
-
-SHELL := /bin/sh
-
-# Build system has TARGET_ARCH=arm, but we can support the exact architecture
-# if it is worthwhile.
-#
-# To generate sources:
-# for arch in arm arm64 x86 x86_64 mips mips64
-# do
-#   TARGET_ARCH_EXT=$arch make -f Makefile_mterp
-# done
-#
-
-OUTPUT_DIR := out
-
-# Accumulate all possible dependencies for the generated files in a very
-# conservative fashion.  If it's not one of the generated files in "out",
-# assume it's a dependency.
-SOURCE_DEPS := \
-	$(shell find . -path ./$(OUTPUT_DIR) -prune -o -type f -print) \
-
-# Source files generated by the script.  There's always one C and one
-# assembly file, though in practice one or the other could be empty.
-GEN_SOURCES := \
-	$(OUTPUT_DIR)/interp_asm_$(TARGET_ARCH_EXT).S
-
-target: $(GEN_SOURCES)
-
-$(GEN_SOURCES): $(SOURCE_DEPS)
-	@mkdir -p out
-	./gen_mterp.py $(TARGET_ARCH_EXT) $(OUTPUT_DIR)
diff --git a/runtime/interpreter/mterp/README.txt b/runtime/interpreter/mterp/README.txt
index 19e02bec5010c1676d393520850b40c007cec9ad..54bb634cb59ebb2f373792103cd130c886b216e3 100644
--- a/runtime/interpreter/mterp/README.txt
+++ b/runtime/interpreter/mterp/README.txt
@@ -1,108 +1,29 @@
-rt "mterp" README
-
-NOTE: Find rebuilding instructions at the bottom of this file.
-
-
 ==== Overview ====
 
-Every configuration has a "config-*" file that controls how the sources
-are generated.  The sources are written into the "out" directory, where
+The assembly source code is produced from custom python-based templates.
+All the architecture-specific template files are concatenated to create
+one big python script. This generated python script is then executed to
+produced the final assembly file. The template syntax is:
+ * Lines starting with % are python code. They will be copied as-is to
+   the script (without the %) and thus executed during the generation.
+ * Other lines are text, and they are essentially syntax sugar for
+   out.write('''(line text)''') and thus they write the main output.
+ * Within a text line, $ can be used insert variables from code.
+
+The final assembly sources are written into the "out" directory, where
 they are picked up by the Android build system.
 
 The best way to become familiar with the interpreter is to look at the
 generated files in the "out" directory.
 
 
-==== Config file format ====
-
-The config files are parsed from top to bottom.  Each line in the file
-may be blank, hold a comment (line starts with '#'), or be a command.
-
-The commands are:
-
-  handler-style <computed-goto|jump-table>
-
-    Specify which style of interpreter to generate.  In computed-goto,
-    each handler is allocated a fixed region, allowing transitions to
-    be done via table-start-address + (opcode * handler-size). With
-    jump-table style, handlers may be of any length, and the generated
-    table is an array of pointers to the handlers.  This command is required,
-    and must be the first command in the config file.
-
-  handler-size <bytes>
-
-    Specify the size of the fixed region, in bytes.  On most platforms
-    this will need to be a power of 2.  For jump-table implementations,
-    this command is ignored.
-
-  import <filename>
-
-    The specified file is included immediately, in its entirety.  No
-    substitutions are performed.  ".cpp" and ".h" files are copied to the
-    C output, ".S" files are copied to the asm output.
-
-  asm-alt-stub <filename>
-
-    When present, this command will cause the generation of an alternate
-    set of entry points (for computed-goto interpreters) or an alternate
-    jump table (for jump-table interpreters).
-
-  fallback-stub <filename>
-
-    Specifies a file to be used for the special FALLBACK tag on the "op"
-    command below.  Intended to be used to transfer control to an alternate
-    interpreter to single-step a not-yet-implemented opcode.  Note: should
-    note be used on RETURN-class instructions.
-
-  op-start <directory>
-
-    Indicates the start of the opcode list.  Must precede any "op"
-    commands.  The specified directory is the default location to pull
-    instruction files from.
-
-  op <opcode> <directory>|FALLBACK
-
-    Can only appear after "op-start" and before "op-end".  Overrides the
-    default source file location of the specified opcode.  The opcode
-    definition will come from the specified file, e.g. "op OP_NOP arm"
-    will load from "arm/OP_NOP.S".  A substitution dictionary will be
-    applied (see below).  If the special "FALLBACK" token is used instead of
-    a directory name, the source file specified in fallback-stub will instead
-    be used for this opcode.
-
-  alt <opcode> <directory>
-
-    Can only appear after "op-start" and before "op-end".  Similar to the
-    "op" command above, but denotes a source file to override the entry
-    in the alternate handler table.  The opcode definition will come from
-    the specified file, e.g. "alt OP_NOP arm" will load from
-    "arm/ALT_OP_NOP.S".  A substitution dictionary will be applied
-    (see below).
-
-  op-end
-
-    Indicates the end of the opcode list.  All kNumPackedOpcodes
-    opcodes are emitted when this is seen, followed by any code that
-    didn't fit inside the fixed-size instruction handler space.
-
-The order of "op" and "alt" directives are not significant; the generation
-tool will extract ordering info from the VM sources.
-
-Typically the form in which most opcodes currently exist is used in
-the "op-start" directive.
-
 ==== Instruction file format ====
 
 The assembly instruction files are simply fragments of assembly sources.
 The starting label will be provided by the generation tool, as will
-declarations for the segment type and alignment.  The expected target
-assembler is GNU "as", but others will work (may require fiddling with
-some of the pseudo-ops emitted by the generation tool).
-
-A substitution dictionary is applied to all opcode fragments as they are
-appended to the output.  Substitutions can look like "$value" or "${value}".
+declarations for the segment type and alignment.
 
-The dictionary always includes:
+The following global variables are generally available:
 
   $opcode - opcode name, e.g. "OP_NOP"
   $opnum - opcode number, e.g. 0 for OP_NOP
@@ -113,29 +34,6 @@ Both C and assembly sources will be passed through the C pre-processor,
 so you can take advantage of C-style comments and preprocessor directives
 like "#define".
 
-Some generator operations are available.
-
-  %include "filename" [subst-dict]
-
-    Includes the file, which should look like "arm/OP_NOP.S".  You can
-    specify values for the substitution dictionary, using standard Python
-    syntax.  For example, this:
-      %include "arm/unop.S" {"result":"r1"}
-    would insert "arm/unop.S" at the current file position, replacing
-    occurrences of "$result" with "r1".
-
-  %default <subst-dict>
-
-    Specify default substitution dictionary values, using standard Python
-    syntax.  Useful if you want to have a "base" version and variants.
-
-  %break
-
-    Identifies the split between the main portion of the instruction
-    handler (which must fit in "handler-size" bytes) and the "sister"
-    code, which is appended to the end of the instruction handler block.
-    In jump table implementations, %break is ignored.
-
 The generation tool does *not* print a warning if your instructions
 exceed "handler-size", but the VM will abort on startup if it detects an
 oversized handler.  On architectures with fixed-width instructions this
@@ -153,20 +51,6 @@ If a constant in the file becomes out of sync, the VM will log an error
 message and abort during startup.
 
 
-==== Development tips ====
-
-If you need to debug the initial piece of an opcode handler, and your
-debug code expands it beyond the handler size limit, you can insert a
-generic header at the top:
-
-    b       ${opcode}_start
-%break
-${opcode}_start:
-
-If you already have a %break, it's okay to leave it in place -- the second
-%break is ignored.
-
-
 ==== Rebuilding ====
 
 If you change any of the source file fragments, you need to rebuild the
@@ -174,7 +58,7 @@ combined source files in the "out" directory.  Make sure the files in
 "out" are editable, then:
 
     $ cd mterp
-    $ ./rebuild.sh
+    $ ./gen_mterp.py
 
 The ultimate goal is to have the build system generate the necessary
 output files without requiring this separate step, but we're not yet
diff --git a/runtime/interpreter/mterp/arm/alt_stub.S b/runtime/interpreter/mterp/arm/alt_stub.S
index 8799d9520c60c1c51c22b3f3db39acee190061f0..9e6f91ecf78b2b1d8f90d22aa77dabbcb83bde06 100644
--- a/runtime/interpreter/mterp/arm/alt_stub.S
+++ b/runtime/interpreter/mterp/arm/alt_stub.S
@@ -1,3 +1,4 @@
+%def alt_stub():
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
diff --git a/runtime/interpreter/mterp/arm/bincmp.S b/runtime/interpreter/mterp/arm/bincmp.S
index 8fad42f0d239f3df111c820d33616d8c7a987f75..368c2d697147a9731df85b1e40f6946ccc25c293 100644
--- a/runtime/interpreter/mterp/arm/bincmp.S
+++ b/runtime/interpreter/mterp/arm/bincmp.S
@@ -1,3 +1,4 @@
+%def bincmp(condition=""):
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
diff --git a/runtime/interpreter/mterp/arm/binop.S b/runtime/interpreter/mterp/arm/binop.S
index eeb72ef65b44caa6cd39f3a524a1e54f6988c0fc..72ae9f4b3823f1bc897b6a6558a430ba6718c4a7 100644
--- a/runtime/interpreter/mterp/arm/binop.S
+++ b/runtime/interpreter/mterp/arm/binop.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"r0", "chkzero":"0"}
+%def binop(preinstr="", result="r0", chkzero="0", instr=""):
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0 op r1".
diff --git a/runtime/interpreter/mterp/arm/binop2addr.S b/runtime/interpreter/mterp/arm/binop2addr.S
index d09a43ae48ee6c9edaee16c2fcc8c76c740f79a1..6f7f23c2aaedaa5a4c63bff43e5c2fa91e18cff8 100644
--- a/runtime/interpreter/mterp/arm/binop2addr.S
+++ b/runtime/interpreter/mterp/arm/binop2addr.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"r0", "chkzero":"0"}
+%def binop2addr(preinstr="", result="r0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
diff --git a/runtime/interpreter/mterp/arm/binopLit16.S b/runtime/interpreter/mterp/arm/binopLit16.S
index 065394e4ef2738d86028db15fefb7afa635c3049..86291b565567866089a063dd9f7c1a4f54664ee5 100644
--- a/runtime/interpreter/mterp/arm/binopLit16.S
+++ b/runtime/interpreter/mterp/arm/binopLit16.S
@@ -1,4 +1,4 @@
-%default {"result":"r0", "chkzero":"0"}
+%def binopLit16(result="r0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
diff --git a/runtime/interpreter/mterp/arm/binopLit8.S b/runtime/interpreter/mterp/arm/binopLit8.S
index 7c9c6312cded9e89ca1a2f59f9d73f6306be60e7..b850e496e7957b8b5dba4647702c94321e6f2c6f 100644
--- a/runtime/interpreter/mterp/arm/binopLit8.S
+++ b/runtime/interpreter/mterp/arm/binopLit8.S
@@ -1,4 +1,4 @@
-%default {"extract":"asr     r1, r3, #8", "result":"r0", "chkzero":"0"}
+%def binopLit8(extract="asr     r1, r3, #8", result="r0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
diff --git a/runtime/interpreter/mterp/arm/binopWide.S b/runtime/interpreter/mterp/arm/binopWide.S
index 4d880015c87127ff23b45d469c654250cab4cb03..b708627f971fb673e6144ee05d77706ed592cd98 100644
--- a/runtime/interpreter/mterp/arm/binopWide.S
+++ b/runtime/interpreter/mterp/arm/binopWide.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result0":"r0", "result1":"r1", "chkzero":"0"}
+%def binopWide(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""):
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0-r1 op r2-r3".
diff --git a/runtime/interpreter/mterp/arm/binopWide2addr.S b/runtime/interpreter/mterp/arm/binopWide2addr.S
index bb16335c343ff9fcb3dab99f53ea3794b1a7cec4..2ce513088ba3a60898a49a966879deadda93a2be 100644
--- a/runtime/interpreter/mterp/arm/binopWide2addr.S
+++ b/runtime/interpreter/mterp/arm/binopWide2addr.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result0":"r0", "result1":"r1", "chkzero":"0"}
+%def binopWide2addr(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""):
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0-r1 op r2-r3".
diff --git a/runtime/interpreter/mterp/arm/const.S b/runtime/interpreter/mterp/arm/const.S
index f6f8157a0b31b0078bdc1dd3f84802b65399c75c..a22f366c975e5e94a339b5939c0dbfe01f7eb71f 100644
--- a/runtime/interpreter/mterp/arm/const.S
+++ b/runtime/interpreter/mterp/arm/const.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedConstHandler" }
+%def const(helper="UndefinedConstHandler"):
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
diff --git a/runtime/interpreter/mterp/arm/entry.S b/runtime/interpreter/mterp/arm/entry.S
index 7c7c527ef44c97b6122343b1cc50f0726635477f..d17802b705f5baea99abf9a590f622da44aacb94 100644
--- a/runtime/interpreter/mterp/arm/entry.S
+++ b/runtime/interpreter/mterp/arm/entry.S
@@ -1,3 +1,4 @@
+%def entry():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
diff --git a/runtime/interpreter/mterp/arm/fallback.S b/runtime/interpreter/mterp/arm/fallback.S
index 44e7e1220d841247a99eb6ff9ae11f11f0a1ea8e..3685700dec0c663d42de39d9698f2f39a64da74a 100644
--- a/runtime/interpreter/mterp/arm/fallback.S
+++ b/runtime/interpreter/mterp/arm/fallback.S
@@ -1,3 +1,4 @@
+%def fallback():
 /* Transfer stub to alternate interpreter */
     b    MterpFallback
 
diff --git a/runtime/interpreter/mterp/arm/fbinop.S b/runtime/interpreter/mterp/arm/fbinop.S
index 594ee032d18e5d165e9c2f5c10494599e9d6b428..0f75f89cbbfff62b72bf347b4b0ee8c62baef751 100644
--- a/runtime/interpreter/mterp/arm/fbinop.S
+++ b/runtime/interpreter/mterp/arm/fbinop.S
@@ -1,3 +1,4 @@
+%def fbinop(instr=""):
     /*
      * Generic 32-bit floating-point operation.  Provide an "instr" line that
      * specifies an instruction that performs "s2 = s0 op s1".  Because we
diff --git a/runtime/interpreter/mterp/arm/fbinop2addr.S b/runtime/interpreter/mterp/arm/fbinop2addr.S
index 53c87a08f399a463b0f427fe8ab7d7fd3bad1cc4..a5162a13b21ce41c6a65e1f903bade640ba08403 100644
--- a/runtime/interpreter/mterp/arm/fbinop2addr.S
+++ b/runtime/interpreter/mterp/arm/fbinop2addr.S
@@ -1,3 +1,4 @@
+%def fbinop2addr(instr=""):
     /*
      * Generic 32-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
diff --git a/runtime/interpreter/mterp/arm/fbinopWide.S b/runtime/interpreter/mterp/arm/fbinopWide.S
index ca13bfbab6d94ec883289b4992ce214f74ac06a9..e283feedd80fa8bb9c7da550e52d46a59187be9f 100644
--- a/runtime/interpreter/mterp/arm/fbinopWide.S
+++ b/runtime/interpreter/mterp/arm/fbinopWide.S
@@ -1,3 +1,4 @@
+%def fbinopWide(instr=""):
     /*
      * Generic 64-bit double-precision floating point binary operation.
      * Provide an "instr" line that specifies an instruction that performs
diff --git a/runtime/interpreter/mterp/arm/fbinopWide2addr.S b/runtime/interpreter/mterp/arm/fbinopWide2addr.S
index 9766e2c0c454aa1d7690d7f242433e2b4a31d408..639a7834f94d21683c28931eeedc77db3abc5e40 100644
--- a/runtime/interpreter/mterp/arm/fbinopWide2addr.S
+++ b/runtime/interpreter/mterp/arm/fbinopWide2addr.S
@@ -1,3 +1,4 @@
+%def fbinopWide2addr(instr=""):
     /*
      * Generic 64-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
diff --git a/runtime/interpreter/mterp/arm/field.S b/runtime/interpreter/mterp/arm/field.S
index c46878829e2c05f05f9d69e27b32c2af69e54b56..82e1638fcd5af773c1c87e65fe42a97550a9583f 100644
--- a/runtime/interpreter/mterp/arm/field.S
+++ b/runtime/interpreter/mterp/arm/field.S
@@ -1,4 +1,4 @@
-%default { }
+%def field(helper=""):
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
diff --git a/runtime/interpreter/mterp/arm/footer.S b/runtime/interpreter/mterp/arm/footer.S
index 8e9c3c22fe913adf501d6fbe5d9d7704dfa9b4c1..275584e4eabdf47f5b638d23d202f598237c3790 100644
--- a/runtime/interpreter/mterp/arm/footer.S
+++ b/runtime/interpreter/mterp/arm/footer.S
@@ -1,3 +1,4 @@
+%def footer():
 /*
  * ===========================================================================
  *  Common subroutines and data
diff --git a/runtime/interpreter/mterp/arm/funop.S b/runtime/interpreter/mterp/arm/funop.S
index 1b8bb8bac68c9c5f9a754ea26f211ee0169a0fcd..c4f2231938eab82b88cbfd17b724458dea2280a5 100644
--- a/runtime/interpreter/mterp/arm/funop.S
+++ b/runtime/interpreter/mterp/arm/funop.S
@@ -1,3 +1,4 @@
+%def funop(instr=""):
     /*
      * Generic 32-bit unary floating-point operation.  Provide an "instr"
      * line that specifies an instruction that performs "s1 = op s0".
diff --git a/runtime/interpreter/mterp/arm/funopNarrower.S b/runtime/interpreter/mterp/arm/funopNarrower.S
index b9f758ba867e64c8374235a8013871cc7a456de8..ce5e82ca892a7fc39cefce468f62f80708aab142 100644
--- a/runtime/interpreter/mterp/arm/funopNarrower.S
+++ b/runtime/interpreter/mterp/arm/funopNarrower.S
@@ -1,3 +1,4 @@
+%def funopNarrower(instr=""):
     /*
      * Generic 64bit-to-32bit unary floating point operation.  Provide an
      * "instr" line that specifies an instruction that performs "s0 = op d0".
diff --git a/runtime/interpreter/mterp/arm/funopWider.S b/runtime/interpreter/mterp/arm/funopWider.S
index 854cdc9b66304c12086416d1f67dcb7970ab3ab7..8df362f250452f9880bf2e7da5c2c456443d25aa 100644
--- a/runtime/interpreter/mterp/arm/funopWider.S
+++ b/runtime/interpreter/mterp/arm/funopWider.S
@@ -1,3 +1,4 @@
+%def funopWider(instr=""):
     /*
      * Generic 32bit-to-64bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "d0 = op s0".
diff --git a/runtime/interpreter/mterp/arm/header.S b/runtime/interpreter/mterp/arm/header.S
index 8d9cab5a2f14154ba5b1b8c3975e4124f559d08a..03f330a4e998bf9f2b90dedce449dbd386e763ae 100644
--- a/runtime/interpreter/mterp/arm/header.S
+++ b/runtime/interpreter/mterp/arm/header.S
@@ -1,3 +1,4 @@
+%def header():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
diff --git a/runtime/interpreter/mterp/arm/instruction_end.S b/runtime/interpreter/mterp/arm/instruction_end.S
index f90ebd0221f7ff35964753368888c2576917d112..cf30a9b0b02cd7351dbe58eeba0f8624894bf6b9 100644
--- a/runtime/interpreter/mterp/arm/instruction_end.S
+++ b/runtime/interpreter/mterp/arm/instruction_end.S
@@ -1,3 +1,4 @@
+%def instruction_end():
 
     .type artMterpAsmInstructionEnd, #object
     .hidden artMterpAsmInstructionEnd
diff --git a/runtime/interpreter/mterp/arm/instruction_end_alt.S b/runtime/interpreter/mterp/arm/instruction_end_alt.S
index 0b66dbb9479dd5600b5b69aeeb3ed91bcaa09e1f..9509a63b6a470a388306b2e9fe65994b9981652b 100644
--- a/runtime/interpreter/mterp/arm/instruction_end_alt.S
+++ b/runtime/interpreter/mterp/arm/instruction_end_alt.S
@@ -1,3 +1,4 @@
+%def instruction_end_alt():
 
     .type artMterpAsmAltInstructionEnd, #object
     .hidden artMterpAsmAltInstructionEnd
diff --git a/runtime/interpreter/mterp/arm/instruction_end_sister.S b/runtime/interpreter/mterp/arm/instruction_end_sister.S
index 71c0300f6d5a139f623fd1397be73b7a6cc01c34..18f1dbb38da8c191f28f7528a250744cd0f04b99 100644
--- a/runtime/interpreter/mterp/arm/instruction_end_sister.S
+++ b/runtime/interpreter/mterp/arm/instruction_end_sister.S
@@ -1,3 +1,4 @@
+%def instruction_end_sister():
 
     .type artMterpAsmSisterEnd, #object
     .hidden artMterpAsmSisterEnd
diff --git a/runtime/interpreter/mterp/arm/instruction_start.S b/runtime/interpreter/mterp/arm/instruction_start.S
index b7e9cf51e4ff0498942076b0a4de9d13c228a933..457dcf9617dca3684116418fdc0839a3451d8c24 100644
--- a/runtime/interpreter/mterp/arm/instruction_start.S
+++ b/runtime/interpreter/mterp/arm/instruction_start.S
@@ -1,3 +1,4 @@
+%def instruction_start():
 
     .type artMterpAsmInstructionStart, #object
     .hidden artMterpAsmInstructionStart
diff --git a/runtime/interpreter/mterp/arm/instruction_start_alt.S b/runtime/interpreter/mterp/arm/instruction_start_alt.S
index 7a67ba064c3171e55aad5cabf1458c58c184c5ff..40d2bf5dbe4d6395109ed366bc80dadafcdfc6b3 100644
--- a/runtime/interpreter/mterp/arm/instruction_start_alt.S
+++ b/runtime/interpreter/mterp/arm/instruction_start_alt.S
@@ -1,3 +1,4 @@
+%def instruction_start_alt():
 
     .type artMterpAsmAltInstructionStart, #object
     .hidden artMterpAsmAltInstructionStart
diff --git a/runtime/interpreter/mterp/arm/instruction_start_sister.S b/runtime/interpreter/mterp/arm/instruction_start_sister.S
index 00360616053f769913e829e97a698931958f6b9a..2bf24636eae105e4c918e7736d2954ff12d81ba5 100644
--- a/runtime/interpreter/mterp/arm/instruction_start_sister.S
+++ b/runtime/interpreter/mterp/arm/instruction_start_sister.S
@@ -1,3 +1,4 @@
+%def instruction_start_sister():
 
     .type artMterpAsmSisterStart, #object
     .hidden artMterpAsmSisterStart
diff --git a/runtime/interpreter/mterp/arm/invoke.S b/runtime/interpreter/mterp/arm/invoke.S
index e47dd1b3ca222a7c4a96b2cc7d79cacaa5cf89f2..812852ef57fde4ce1f329c8f547b027b94eab386 100644
--- a/runtime/interpreter/mterp/arm/invoke.S
+++ b/runtime/interpreter/mterp/arm/invoke.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke(helper="UndefinedInvokeHandler"):
     /*
      * Generic invoke handler wrapper.
      */
diff --git a/runtime/interpreter/mterp/arm/invoke_polymorphic.S b/runtime/interpreter/mterp/arm/invoke_polymorphic.S
index f569d61c0bad4d209c2e826a48e6f53443d3431f..b473616ad2f230b2b0a75638bf1b32737b858336 100644
--- a/runtime/interpreter/mterp/arm/invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/arm/invoke_polymorphic.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke_polymorphic(helper="UndefinedInvokeHandler"):
     /*
      * invoke-polymorphic handler wrapper.
      */
diff --git a/runtime/interpreter/mterp/arm/op_add_double.S b/runtime/interpreter/mterp/arm/op_add_double.S
index 9332bf2005fb815e435fe5bdb718c0f91d82327d..17aabcd8176792364172f3529fc84a5ae2bd8d2b 100644
--- a/runtime/interpreter/mterp/arm/op_add_double.S
+++ b/runtime/interpreter/mterp/arm/op_add_double.S
@@ -1 +1,2 @@
-%include "arm/fbinopWide.S" {"instr":"faddd   d2, d0, d1"}
+%def op_add_double():
+%  fbinopWide(instr="faddd   d2, d0, d1")
diff --git a/runtime/interpreter/mterp/arm/op_add_double_2addr.S b/runtime/interpreter/mterp/arm/op_add_double_2addr.S
index 3242c53f656b72e5d3c688fe5cef8fbc6f1b5d53..97d17574687166a30439b55d51559b820507b04e 100644
--- a/runtime/interpreter/mterp/arm/op_add_double_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_add_double_2addr.S
@@ -1 +1,2 @@
-%include "arm/fbinopWide2addr.S" {"instr":"faddd   d2, d0, d1"}
+%def op_add_double_2addr():
+%  fbinopWide2addr(instr="faddd   d2, d0, d1")
diff --git a/runtime/interpreter/mterp/arm/op_add_float.S b/runtime/interpreter/mterp/arm/op_add_float.S
index afb7967eb7a17967e720dc18bda4b80151557ea8..9ca8cadc340bd343f20dbad48fd3b6dfb4c0d966 100644
--- a/runtime/interpreter/mterp/arm/op_add_float.S
+++ b/runtime/interpreter/mterp/arm/op_add_float.S
@@ -1 +1,2 @@
-%include "arm/fbinop.S" {"instr":"fadds   s2, s0, s1"}
+%def op_add_float():
+%  fbinop(instr="fadds   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm/op_add_float_2addr.S b/runtime/interpreter/mterp/arm/op_add_float_2addr.S
index 0067b6a010dd08a5a9d000e2f328d13a0aaa36fe..abe1989778b6ae841ac86bef189fe087ee55e0ee 100644
--- a/runtime/interpreter/mterp/arm/op_add_float_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_add_float_2addr.S
@@ -1 +1,2 @@
-%include "arm/fbinop2addr.S" {"instr":"fadds   s2, s0, s1"}
+%def op_add_float_2addr():
+%  fbinop2addr(instr="fadds   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm/op_add_int.S b/runtime/interpreter/mterp/arm/op_add_int.S
index 1dcae7eab31e861a28f31fa01a950992a5d44432..e18601c71b3a18ca33d408f3651ac4e766cb90ec 100644
--- a/runtime/interpreter/mterp/arm/op_add_int.S
+++ b/runtime/interpreter/mterp/arm/op_add_int.S
@@ -1 +1,2 @@
-%include "arm/binop.S" {"instr":"add     r0, r0, r1"}
+%def op_add_int():
+%  binop(instr="add     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_add_int_2addr.S b/runtime/interpreter/mterp/arm/op_add_int_2addr.S
index 9ea98f1928aa13e69acf0adbd717557a1cdb7649..10ea9435838c119b33113da7c3d50aa4df7bc4af 100644
--- a/runtime/interpreter/mterp/arm/op_add_int_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_add_int_2addr.S
@@ -1 +1,2 @@
-%include "arm/binop2addr.S" {"instr":"add     r0, r0, r1"}
+%def op_add_int_2addr():
+%  binop2addr(instr="add     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_add_int_lit16.S b/runtime/interpreter/mterp/arm/op_add_int_lit16.S
index 5763ab849bbcf88a447db5615668fc297d193c86..63febf20daa4bda37df637ca5758a4b6c1d6de3c 100644
--- a/runtime/interpreter/mterp/arm/op_add_int_lit16.S
+++ b/runtime/interpreter/mterp/arm/op_add_int_lit16.S
@@ -1 +1,2 @@
-%include "arm/binopLit16.S" {"instr":"add     r0, r0, r1"}
+%def op_add_int_lit16():
+%  binopLit16(instr="add     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_add_int_lit8.S b/runtime/interpreter/mterp/arm/op_add_int_lit8.S
index 035510d062c3803e8f0828631f0065133a1ce06a..4393e668614268cf90770c98a2534582abbc0d03 100644
--- a/runtime/interpreter/mterp/arm/op_add_int_lit8.S
+++ b/runtime/interpreter/mterp/arm/op_add_int_lit8.S
@@ -1 +1,2 @@
-%include "arm/binopLit8.S" {"extract":"", "instr":"add     r0, r0, r3, asr #8"}
+%def op_add_int_lit8():
+%  binopLit8(extract="", instr="add     r0, r0, r3, asr #8")
diff --git a/runtime/interpreter/mterp/arm/op_add_long.S b/runtime/interpreter/mterp/arm/op_add_long.S
index 093223e755a4951d81c6c8e64bf7a7b53385a7c0..88994d40e5b440b6508c7ee49f4f7e83537fb2fd 100644
--- a/runtime/interpreter/mterp/arm/op_add_long.S
+++ b/runtime/interpreter/mterp/arm/op_add_long.S
@@ -1 +1,2 @@
-%include "arm/binopWide.S" {"preinstr":"adds    r0, r0, r2", "instr":"adc     r1, r1, r3"}
+%def op_add_long():
+%  binopWide(preinstr="adds    r0, r0, r2", instr="adc     r1, r1, r3")
diff --git a/runtime/interpreter/mterp/arm/op_add_long_2addr.S b/runtime/interpreter/mterp/arm/op_add_long_2addr.S
index c11e0aff44905d1d4952b831085251cd3809ed82..bfe7447c92093c1cb959d59682d8d345313c6934 100644
--- a/runtime/interpreter/mterp/arm/op_add_long_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_add_long_2addr.S
@@ -1 +1,2 @@
-%include "arm/binopWide2addr.S" {"preinstr":"adds    r0, r0, r2", "instr":"adc     r1, r1, r3"}
+%def op_add_long_2addr():
+%  binopWide2addr(preinstr="adds    r0, r0, r2", instr="adc     r1, r1, r3")
diff --git a/runtime/interpreter/mterp/arm/op_aget.S b/runtime/interpreter/mterp/arm/op_aget.S
index 11f7079c3fbb24326c632887d440cd407dba20ac..bf265b4819b7f176e319b4cf3306f513cd6c052b 100644
--- a/runtime/interpreter/mterp/arm/op_aget.S
+++ b/runtime/interpreter/mterp/arm/op_aget.S
@@ -1,4 +1,4 @@
-%default { "load":"ldr", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
+%def op_aget(load="ldr", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"):
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/arm/op_aget_boolean.S b/runtime/interpreter/mterp/arm/op_aget_boolean.S
index 8f678dc14f02f647402800a15785bf5f85726970..d6e0a1bbd9c2e1c9077793a6ac30208349f85489 100644
--- a/runtime/interpreter/mterp/arm/op_aget_boolean.S
+++ b/runtime/interpreter/mterp/arm/op_aget_boolean.S
@@ -1 +1,2 @@
-%include "arm/op_aget.S" { "load":"ldrb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aget_boolean():
+%  op_aget(load="ldrb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm/op_aget_byte.S b/runtime/interpreter/mterp/arm/op_aget_byte.S
index a30465068880cac7be29e5844ecba74672731f9a..6c9f1b78fa747ccd8f92ea0192fc0e918bbaa3e5 100644
--- a/runtime/interpreter/mterp/arm/op_aget_byte.S
+++ b/runtime/interpreter/mterp/arm/op_aget_byte.S
@@ -1 +1,2 @@
-%include "arm/op_aget.S" { "load":"ldrsb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aget_byte():
+%  op_aget(load="ldrsb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm/op_aget_char.S b/runtime/interpreter/mterp/arm/op_aget_char.S
index 490830620e4102582b2242d1b8845c116fc89e8a..c5812e3aff0d275d5df30f9b66ffec225847617f 100644
--- a/runtime/interpreter/mterp/arm/op_aget_char.S
+++ b/runtime/interpreter/mterp/arm/op_aget_char.S
@@ -1 +1,2 @@
-%include "arm/op_aget.S" { "load":"ldrh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aget_char():
+%  op_aget(load="ldrh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm/op_aget_object.S b/runtime/interpreter/mterp/arm/op_aget_object.S
index 4e0aab5d13ca6dc2ac4da8d1d06102b3b602deab..3b25086dce0d0b7bd9b6bfc0f971e02268b361ac 100644
--- a/runtime/interpreter/mterp/arm/op_aget_object.S
+++ b/runtime/interpreter/mterp/arm/op_aget_object.S
@@ -1,3 +1,4 @@
+%def op_aget_object():
     /*
      * Array object get.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/arm/op_aget_short.S b/runtime/interpreter/mterp/arm/op_aget_short.S
index b71e659a4a4a2354d142af2c566a48e2fda230df..9727560fe40453725ea4c52b1a0ac80e68ed6fdb 100644
--- a/runtime/interpreter/mterp/arm/op_aget_short.S
+++ b/runtime/interpreter/mterp/arm/op_aget_short.S
@@ -1 +1,2 @@
-%include "arm/op_aget.S" { "load":"ldrsh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aget_short():
+%  op_aget(load="ldrsh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm/op_aget_wide.S b/runtime/interpreter/mterp/arm/op_aget_wide.S
index 66ec950531286bdf163a7b96616a4998640ec30d..28437e71f24a485d121cdea82d5f992e93246c9e 100644
--- a/runtime/interpreter/mterp/arm/op_aget_wide.S
+++ b/runtime/interpreter/mterp/arm/op_aget_wide.S
@@ -1,3 +1,4 @@
+%def op_aget_wide():
     /*
      * Array get, 64 bits.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/arm/op_and_int.S b/runtime/interpreter/mterp/arm/op_and_int.S
index 7c16d376be0d8eb4f98f73d37cdc12f28272ea42..ac0ae6670d1c5c9a2926829a07fe5ee9b8e4ea30 100644
--- a/runtime/interpreter/mterp/arm/op_and_int.S
+++ b/runtime/interpreter/mterp/arm/op_and_int.S
@@ -1 +1,2 @@
-%include "arm/binop.S" {"instr":"and     r0, r0, r1"}
+%def op_and_int():
+%  binop(instr="and     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_and_int_2addr.S b/runtime/interpreter/mterp/arm/op_and_int_2addr.S
index 0fbab0286340cf72a0cea13db3d7e98b08f67948..28a668a1a0800a519ca62bfbc56bb4ae22e68933 100644
--- a/runtime/interpreter/mterp/arm/op_and_int_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_and_int_2addr.S
@@ -1 +1,2 @@
-%include "arm/binop2addr.S" {"instr":"and     r0, r0, r1"}
+%def op_and_int_2addr():
+%  binop2addr(instr="and     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_and_int_lit16.S b/runtime/interpreter/mterp/arm/op_and_int_lit16.S
index 541e9b781492b841a4c220b05992ca0119f4f7f9..4b9a4c947a7c4bc0c8f6ee12cdf67fc82f06adcd 100644
--- a/runtime/interpreter/mterp/arm/op_and_int_lit16.S
+++ b/runtime/interpreter/mterp/arm/op_and_int_lit16.S
@@ -1 +1,2 @@
-%include "arm/binopLit16.S" {"instr":"and     r0, r0, r1"}
+%def op_and_int_lit16():
+%  binopLit16(instr="and     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_and_int_lit8.S b/runtime/interpreter/mterp/arm/op_and_int_lit8.S
index af746b5447cd0a9686fe1e2f347b742ff7898b0b..b26bfe42275fcc621ed49aa1016cc4c2aa107ef2 100644
--- a/runtime/interpreter/mterp/arm/op_and_int_lit8.S
+++ b/runtime/interpreter/mterp/arm/op_and_int_lit8.S
@@ -1 +1,2 @@
-%include "arm/binopLit8.S" {"extract":"", "instr":"and     r0, r0, r3, asr #8"}
+%def op_and_int_lit8():
+%  binopLit8(extract="", instr="and     r0, r0, r3, asr #8")
diff --git a/runtime/interpreter/mterp/arm/op_and_long.S b/runtime/interpreter/mterp/arm/op_and_long.S
index 4ad5158da711354b703e49e39e6e60b03edee871..3af7897fb2501c7444224215b1b705b35376c9e4 100644
--- a/runtime/interpreter/mterp/arm/op_and_long.S
+++ b/runtime/interpreter/mterp/arm/op_and_long.S
@@ -1 +1,2 @@
-%include "arm/binopWide.S" {"preinstr":"and     r0, r0, r2", "instr":"and     r1, r1, r3"}
+%def op_and_long():
+%  binopWide(preinstr="and     r0, r0, r2", instr="and     r1, r1, r3")
diff --git a/runtime/interpreter/mterp/arm/op_and_long_2addr.S b/runtime/interpreter/mterp/arm/op_and_long_2addr.S
index e23ea447ba433e975411ba525fb82a20d2b8a51c..78e5d8816216df3a77f6a3230b1e868239838005 100644
--- a/runtime/interpreter/mterp/arm/op_and_long_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_and_long_2addr.S
@@ -1 +1,2 @@
-%include "arm/binopWide2addr.S" {"preinstr":"and     r0, r0, r2", "instr":"and     r1, r1, r3"}
+%def op_and_long_2addr():
+%  binopWide2addr(preinstr="and     r0, r0, r2", instr="and     r1, r1, r3")
diff --git a/runtime/interpreter/mterp/arm/op_aput.S b/runtime/interpreter/mterp/arm/op_aput.S
index a511fa59e02a86e53d0912116b8047fa46e7945a..7b5da541f645b32775d4026117510bb924ca5c3c 100644
--- a/runtime/interpreter/mterp/arm/op_aput.S
+++ b/runtime/interpreter/mterp/arm/op_aput.S
@@ -1,4 +1,4 @@
-%default { "store":"str", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
+%def op_aput(store="str", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"):
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
diff --git a/runtime/interpreter/mterp/arm/op_aput_boolean.S b/runtime/interpreter/mterp/arm/op_aput_boolean.S
index e86663f19988034fd4fcbc1bb8964a01c7cf3efc..467cc4bf20f85f653e699148f96e62a79c5b0700 100644
--- a/runtime/interpreter/mterp/arm/op_aput_boolean.S
+++ b/runtime/interpreter/mterp/arm/op_aput_boolean.S
@@ -1 +1,2 @@
-%include "arm/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aput_boolean():
+%  op_aput(store="strb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm/op_aput_byte.S b/runtime/interpreter/mterp/arm/op_aput_byte.S
index 83694b788d82521c1a28f286ed57deff844a9b25..2b4c0ba389e7adc8a01028fffb93628a90e45144 100644
--- a/runtime/interpreter/mterp/arm/op_aput_byte.S
+++ b/runtime/interpreter/mterp/arm/op_aput_byte.S
@@ -1 +1,2 @@
-%include "arm/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aput_byte():
+%  op_aput(store="strb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm/op_aput_char.S b/runtime/interpreter/mterp/arm/op_aput_char.S
index 3551cace334aab72f3aedd8de14bfdac4bae435d..cb7dcbad4df997fd1c96f4c8e966aed9ebfc2a28 100644
--- a/runtime/interpreter/mterp/arm/op_aput_char.S
+++ b/runtime/interpreter/mterp/arm/op_aput_char.S
@@ -1 +1,2 @@
-%include "arm/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aput_char():
+%  op_aput(store="strh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm/op_aput_object.S b/runtime/interpreter/mterp/arm/op_aput_object.S
index c5399163e313aa5a146aee7984ea93c4a5881ab7..83b7e5a2fb37d228fe28bbf203bd7a0593ca3b67 100644
--- a/runtime/interpreter/mterp/arm/op_aput_object.S
+++ b/runtime/interpreter/mterp/arm/op_aput_object.S
@@ -1,3 +1,4 @@
+%def op_aput_object():
     /*
      * Store an object into an array.  vBB[vCC] <- vAA.
      */
diff --git a/runtime/interpreter/mterp/arm/op_aput_short.S b/runtime/interpreter/mterp/arm/op_aput_short.S
index 0a0590ec369fd525bef8ce7ea5926410484aaa14..f624163087bae7b6ff6ff75ca7c2c909e9676b67 100644
--- a/runtime/interpreter/mterp/arm/op_aput_short.S
+++ b/runtime/interpreter/mterp/arm/op_aput_short.S
@@ -1 +1,2 @@
-%include "arm/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aput_short():
+%  op_aput(store="strh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm/op_aput_wide.S b/runtime/interpreter/mterp/arm/op_aput_wide.S
index 005750752f8dfbf3f62bc9cfa89fae58e1c166c6..769522a5ec97427c363681b7db9d6f692bea9965 100644
--- a/runtime/interpreter/mterp/arm/op_aput_wide.S
+++ b/runtime/interpreter/mterp/arm/op_aput_wide.S
@@ -1,3 +1,4 @@
+%def op_aput_wide():
     /*
      * Array put, 64 bits.  vBB[vCC] <- vAA.
      *
diff --git a/runtime/interpreter/mterp/arm/op_array_length.S b/runtime/interpreter/mterp/arm/op_array_length.S
index 43b1682a9d9599c3bae35964a311e749eb318543..3ec24b8a3bb957cd0a954d9d4eae0f008bbe96cb 100644
--- a/runtime/interpreter/mterp/arm/op_array_length.S
+++ b/runtime/interpreter/mterp/arm/op_array_length.S
@@ -1,3 +1,4 @@
+%def op_array_length():
     /*
      * Return the length of an array.
      */
diff --git a/runtime/interpreter/mterp/arm/op_check_cast.S b/runtime/interpreter/mterp/arm/op_check_cast.S
index 24eba45a692dcbd2df04391c364e68ff7d8ccfec..a56451b5dfb2e6868f3721e1eaddbd8c618597f5 100644
--- a/runtime/interpreter/mterp/arm/op_check_cast.S
+++ b/runtime/interpreter/mterp/arm/op_check_cast.S
@@ -1,3 +1,4 @@
+%def op_check_cast():
     /*
      * Check to see if a cast from one class to another is allowed.
      */
diff --git a/runtime/interpreter/mterp/arm/op_cmp_long.S b/runtime/interpreter/mterp/arm/op_cmp_long.S
index 6626ff0f492c3a0f7628812ee33f7521a99c526c..2f87716df7974a7ef16abe84abf588c04da2ba8d 100644
--- a/runtime/interpreter/mterp/arm/op_cmp_long.S
+++ b/runtime/interpreter/mterp/arm/op_cmp_long.S
@@ -1,3 +1,4 @@
+%def op_cmp_long():
     /*
      * Compare two 64-bit values.  Puts 0, 1, or -1 into the destination
      * register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/arm/op_cmpg_double.S b/runtime/interpreter/mterp/arm/op_cmpg_double.S
index 602a4b1bfd62931d9ad73c138f689f32f838d857..a166d1625693e2ec1c7650cfd4623894ab4f103f 100644
--- a/runtime/interpreter/mterp/arm/op_cmpg_double.S
+++ b/runtime/interpreter/mterp/arm/op_cmpg_double.S
@@ -1,3 +1,4 @@
+%def op_cmpg_double():
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/arm/op_cmpg_float.S b/runtime/interpreter/mterp/arm/op_cmpg_float.S
index 965091f82d0db1327d9c88da0b56d9d28314102d..e14f4ec1a2f0d3e6b403b7af49aba040fa4442e2 100644
--- a/runtime/interpreter/mterp/arm/op_cmpg_float.S
+++ b/runtime/interpreter/mterp/arm/op_cmpg_float.S
@@ -1,3 +1,4 @@
+%def op_cmpg_float():
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/arm/op_cmpl_double.S b/runtime/interpreter/mterp/arm/op_cmpl_double.S
index 8a5e509ee8aa1bc5565772e5e50f5519ff477b5e..44c827a9a3199e8af6681bf104983fb6103efbdc 100644
--- a/runtime/interpreter/mterp/arm/op_cmpl_double.S
+++ b/runtime/interpreter/mterp/arm/op_cmpl_double.S
@@ -1,3 +1,4 @@
+%def op_cmpl_double():
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/arm/op_cmpl_float.S b/runtime/interpreter/mterp/arm/op_cmpl_float.S
index 9df0c2c17199daa9c09e1cf2c0d5ce5b41b7b0bc..c2026634e2445028e77fbf80923e8a26e6a44ca2 100644
--- a/runtime/interpreter/mterp/arm/op_cmpl_float.S
+++ b/runtime/interpreter/mterp/arm/op_cmpl_float.S
@@ -1,3 +1,4 @@
+%def op_cmpl_float():
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/arm/op_const.S b/runtime/interpreter/mterp/arm/op_const.S
index 39890a085a8443c742e248404e10c3e65526b6d4..e5ef50e91281a45800bd5611908cfc1da46a8445 100644
--- a/runtime/interpreter/mterp/arm/op_const.S
+++ b/runtime/interpreter/mterp/arm/op_const.S
@@ -1,3 +1,4 @@
+%def op_const():
     /* const vAA, #+BBBBbbbb */
     mov     r3, rINST, lsr #8           @ r3<- AA
     FETCH r0, 1                         @ r0<- bbbb (low)
diff --git a/runtime/interpreter/mterp/arm/op_const_16.S b/runtime/interpreter/mterp/arm/op_const_16.S
index a30cf3a0dbb310f7b37d35d92f4759cac97bf9aa..3bb89d08adf4ba0a992ea34628e058d6aca66c6e 100644
--- a/runtime/interpreter/mterp/arm/op_const_16.S
+++ b/runtime/interpreter/mterp/arm/op_const_16.S
@@ -1,3 +1,4 @@
+%def op_const_16():
     /* const/16 vAA, #+BBBB */
     FETCH_S r0, 1                       @ r0<- ssssBBBB (sign-extended)
     mov     r3, rINST, lsr #8           @ r3<- AA
diff --git a/runtime/interpreter/mterp/arm/op_const_4.S b/runtime/interpreter/mterp/arm/op_const_4.S
index c97b0e91f52f705810cc61087716b2f262dabb6f..bfb4246b0b1d409c05888e41c238148436c3d2d8 100644
--- a/runtime/interpreter/mterp/arm/op_const_4.S
+++ b/runtime/interpreter/mterp/arm/op_const_4.S
@@ -1,3 +1,4 @@
+%def op_const_4():
     /* const/4 vA, #+B */
     sbfx    r1, rINST, #12, #4          @ r1<- sssssssB (sign-extended)
     ubfx    r0, rINST, #8, #4           @ r0<- A
diff --git a/runtime/interpreter/mterp/arm/op_const_class.S b/runtime/interpreter/mterp/arm/op_const_class.S
index ff5c98c7432937caec67f5e6b065c06141ab91b8..db12ec31414690de6acb180ce962f6676f3ab2f5 100644
--- a/runtime/interpreter/mterp/arm/op_const_class.S
+++ b/runtime/interpreter/mterp/arm/op_const_class.S
@@ -1 +1,2 @@
-%include "arm/const.S" { "helper":"MterpConstClass" }
+%def op_const_class():
+%  const(helper="MterpConstClass")
diff --git a/runtime/interpreter/mterp/arm/op_const_high16.S b/runtime/interpreter/mterp/arm/op_const_high16.S
index 536276d52d76ce971d125bdee373543678c047be..7f20e11f4c129977e36d5883d146c86e15b9ab94 100644
--- a/runtime/interpreter/mterp/arm/op_const_high16.S
+++ b/runtime/interpreter/mterp/arm/op_const_high16.S
@@ -1,3 +1,4 @@
+%def op_const_high16():
     /* const/high16 vAA, #+BBBB0000 */
     FETCH r0, 1                         @ r0<- 0000BBBB (zero-extended)
     mov     r3, rINST, lsr #8           @ r3<- AA
diff --git a/runtime/interpreter/mterp/arm/op_const_method_handle.S b/runtime/interpreter/mterp/arm/op_const_method_handle.S
index 71f05501e7e952cf591f13406352a6edbb5acc90..2680c17aad5d6f537298bc455177da35df137274 100644
--- a/runtime/interpreter/mterp/arm/op_const_method_handle.S
+++ b/runtime/interpreter/mterp/arm/op_const_method_handle.S
@@ -1 +1,2 @@
-%include "arm/const.S" { "helper":"MterpConstMethodHandle" }
+%def op_const_method_handle():
+%  const(helper="MterpConstMethodHandle")
diff --git a/runtime/interpreter/mterp/arm/op_const_method_type.S b/runtime/interpreter/mterp/arm/op_const_method_type.S
index 2cccdafef4966cf199bc3f1ed2ee62da40bc4e71..ea814bf64826079ab9f55e43e47f42180c3ad420 100644
--- a/runtime/interpreter/mterp/arm/op_const_method_type.S
+++ b/runtime/interpreter/mterp/arm/op_const_method_type.S
@@ -1 +1,2 @@
-%include "arm/const.S" { "helper":"MterpConstMethodType" }
+%def op_const_method_type():
+%  const(helper="MterpConstMethodType")
diff --git a/runtime/interpreter/mterp/arm/op_const_string.S b/runtime/interpreter/mterp/arm/op_const_string.S
index 75ec34ffb4dc6970e37da53963e05de7ecd3d850..41376f870340354594a5a218b1d2379e08042008 100644
--- a/runtime/interpreter/mterp/arm/op_const_string.S
+++ b/runtime/interpreter/mterp/arm/op_const_string.S
@@ -1 +1,2 @@
-%include "arm/const.S" { "helper":"MterpConstString" }
+%def op_const_string():
+%  const(helper="MterpConstString")
diff --git a/runtime/interpreter/mterp/arm/op_const_string_jumbo.S b/runtime/interpreter/mterp/arm/op_const_string_jumbo.S
index 1255c0768d1b9796f6ea23ada9601a43dffaf21d..29c9854f44c89404c6b4f5f2281e197134a11411 100644
--- a/runtime/interpreter/mterp/arm/op_const_string_jumbo.S
+++ b/runtime/interpreter/mterp/arm/op_const_string_jumbo.S
@@ -1,3 +1,4 @@
+%def op_const_string_jumbo():
     /* const/string vAA, String@BBBBBBBB */
     EXPORT_PC
     FETCH r0, 1                         @ r0<- bbbb (low)
diff --git a/runtime/interpreter/mterp/arm/op_const_wide.S b/runtime/interpreter/mterp/arm/op_const_wide.S
index 8310a4c129e5db089264e07489aabfc2ce31c286..40bac6d72bcce576e6826ff7fd13be064fc07ec3 100644
--- a/runtime/interpreter/mterp/arm/op_const_wide.S
+++ b/runtime/interpreter/mterp/arm/op_const_wide.S
@@ -1,3 +1,4 @@
+%def op_const_wide():
     /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
     FETCH r0, 1                         @ r0<- bbbb (low)
     FETCH r1, 2                         @ r1<- BBBB (low middle)
diff --git a/runtime/interpreter/mterp/arm/op_const_wide_16.S b/runtime/interpreter/mterp/arm/op_const_wide_16.S
index 28abb512f02e256dbe93e3108dd725a128e6da22..7d334c997f73ba81f37a3569265eb9124dfe80bd 100644
--- a/runtime/interpreter/mterp/arm/op_const_wide_16.S
+++ b/runtime/interpreter/mterp/arm/op_const_wide_16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_16():
     /* const-wide/16 vAA, #+BBBB */
     FETCH_S r0, 1                       @ r0<- ssssBBBB (sign-extended)
     mov     r3, rINST, lsr #8           @ r3<- AA
diff --git a/runtime/interpreter/mterp/arm/op_const_wide_32.S b/runtime/interpreter/mterp/arm/op_const_wide_32.S
index c10bb0461ac428a71e083f6e9d24f3f3ebeb0aa6..eeb5fa510e513a8e6c6bbaf3b1880e492e878f03 100644
--- a/runtime/interpreter/mterp/arm/op_const_wide_32.S
+++ b/runtime/interpreter/mterp/arm/op_const_wide_32.S
@@ -1,3 +1,4 @@
+%def op_const_wide_32():
     /* const-wide/32 vAA, #+BBBBbbbb */
     FETCH r0, 1                         @ r0<- 0000bbbb (low)
     mov     r3, rINST, lsr #8           @ r3<- AA
diff --git a/runtime/interpreter/mterp/arm/op_const_wide_high16.S b/runtime/interpreter/mterp/arm/op_const_wide_high16.S
index d7e38ecc20670f1cd0e82d3096a7509249927938..57ce0242a1adfeeb3f86e10acb52567d48c8b644 100644
--- a/runtime/interpreter/mterp/arm/op_const_wide_high16.S
+++ b/runtime/interpreter/mterp/arm/op_const_wide_high16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_high16():
     /* const-wide/high16 vAA, #+BBBB000000000000 */
     FETCH r1, 1                         @ r1<- 0000BBBB (zero-extended)
     mov     r3, rINST, lsr #8           @ r3<- AA
diff --git a/runtime/interpreter/mterp/arm/op_div_double.S b/runtime/interpreter/mterp/arm/op_div_double.S
index 5147550b97ecb6f848c847e5ad914b04785c2b10..d90969495d4b4d23ce85e5f10e30d55fffa1487a 100644
--- a/runtime/interpreter/mterp/arm/op_div_double.S
+++ b/runtime/interpreter/mterp/arm/op_div_double.S
@@ -1 +1,2 @@
-%include "arm/fbinopWide.S" {"instr":"fdivd   d2, d0, d1"}
+%def op_div_double():
+%  fbinopWide(instr="fdivd   d2, d0, d1")
diff --git a/runtime/interpreter/mterp/arm/op_div_double_2addr.S b/runtime/interpreter/mterp/arm/op_div_double_2addr.S
index b812f17ac9c37eebf04f89de090075d9091f78e8..499c87b1e620d4e3079329a6fd0d5000a1bbc212 100644
--- a/runtime/interpreter/mterp/arm/op_div_double_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_div_double_2addr.S
@@ -1 +1,2 @@
-%include "arm/fbinopWide2addr.S" {"instr":"fdivd   d2, d0, d1"}
+%def op_div_double_2addr():
+%  fbinopWide2addr(instr="fdivd   d2, d0, d1")
diff --git a/runtime/interpreter/mterp/arm/op_div_float.S b/runtime/interpreter/mterp/arm/op_div_float.S
index 0f24d11e54d419f0684e15122a044dcc840f961b..11369095be492ef90033bd6ceef401125d8cae77 100644
--- a/runtime/interpreter/mterp/arm/op_div_float.S
+++ b/runtime/interpreter/mterp/arm/op_div_float.S
@@ -1 +1,2 @@
-%include "arm/fbinop.S" {"instr":"fdivs   s2, s0, s1"}
+%def op_div_float():
+%  fbinop(instr="fdivs   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm/op_div_float_2addr.S b/runtime/interpreter/mterp/arm/op_div_float_2addr.S
index a1dbf01713eaa8212d3b12605624881ffb2c6b4a..5198bc778f1682ae910836ce33013999f301c2d0 100644
--- a/runtime/interpreter/mterp/arm/op_div_float_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_div_float_2addr.S
@@ -1 +1,2 @@
-%include "arm/fbinop2addr.S" {"instr":"fdivs   s2, s0, s1"}
+%def op_div_float_2addr():
+%  fbinop2addr(instr="fdivs   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm/op_div_int.S b/runtime/interpreter/mterp/arm/op_div_int.S
index 251064be0dbd3bf26d31fdc02b9bd8fe0886ea40..211ac772960f931cd09059723e958f45de7f9650 100644
--- a/runtime/interpreter/mterp/arm/op_div_int.S
+++ b/runtime/interpreter/mterp/arm/op_div_int.S
@@ -1,4 +1,4 @@
-%default {}
+%def op_div_int():
     /*
      * Specialized 32-bit binary operation
      *
diff --git a/runtime/interpreter/mterp/arm/op_div_int_2addr.S b/runtime/interpreter/mterp/arm/op_div_int_2addr.S
index 9be4cd8b140f7268e4a12fad71d1f5500ac1f061..968a4991fa20a54e4f631520b79ea014d950a34e 100644
--- a/runtime/interpreter/mterp/arm/op_div_int_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_div_int_2addr.S
@@ -1,4 +1,4 @@
-%default {}
+%def op_div_int_2addr():
     /*
      * Specialized 32-bit binary operation
      *
diff --git a/runtime/interpreter/mterp/arm/op_div_int_lit16.S b/runtime/interpreter/mterp/arm/op_div_int_lit16.S
index d9bc7d65ce4affff40445f374097b862f798b872..f1e21269c75852dedad25e3af0b826f473be767c 100644
--- a/runtime/interpreter/mterp/arm/op_div_int_lit16.S
+++ b/runtime/interpreter/mterp/arm/op_div_int_lit16.S
@@ -1,4 +1,4 @@
-%default {}
+%def op_div_int_lit16():
     /*
      * Specialized 32-bit binary operation
      *
diff --git a/runtime/interpreter/mterp/arm/op_div_int_lit8.S b/runtime/interpreter/mterp/arm/op_div_int_lit8.S
index 5d2dbd3ecbd198f65fcad6a65dbae73d9b0cdb22..e0d88f80df4c2a54e05a72a2b044bf1bc79078be 100644
--- a/runtime/interpreter/mterp/arm/op_div_int_lit8.S
+++ b/runtime/interpreter/mterp/arm/op_div_int_lit8.S
@@ -1,4 +1,4 @@
-%default {}
+%def op_div_int_lit8():
     /*
      * Specialized 32-bit binary operation
      *
diff --git a/runtime/interpreter/mterp/arm/op_div_long.S b/runtime/interpreter/mterp/arm/op_div_long.S
index 0f21a845d4c79a2f3012950431f155d7a26429f3..7423f5bfa84acd0fe5cfe78bb59b37ff69cd39b2 100644
--- a/runtime/interpreter/mterp/arm/op_div_long.S
+++ b/runtime/interpreter/mterp/arm/op_div_long.S
@@ -1 +1,2 @@
-%include "arm/binopWide.S" {"instr":"bl      __aeabi_ldivmod", "chkzero":"1"}
+%def op_div_long():
+%  binopWide(instr="bl      __aeabi_ldivmod", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm/op_div_long_2addr.S b/runtime/interpreter/mterp/arm/op_div_long_2addr.S
index e172b2949606dd05db0a9c73bbdb44cafdc9c0c4..fed8b8f3d73846dc110495f3adac44c6d969beed 100644
--- a/runtime/interpreter/mterp/arm/op_div_long_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_div_long_2addr.S
@@ -1 +1,2 @@
-%include "arm/binopWide2addr.S" {"instr":"bl      __aeabi_ldivmod", "chkzero":"1"}
+%def op_div_long_2addr():
+%  binopWide2addr(instr="bl      __aeabi_ldivmod", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm/op_double_to_float.S b/runtime/interpreter/mterp/arm/op_double_to_float.S
index 98fdfbc64ed521d6aaa231d11a1638c9daaef7da..dcd575e3f168137351a9c50ac6d549738ae5f1ce 100644
--- a/runtime/interpreter/mterp/arm/op_double_to_float.S
+++ b/runtime/interpreter/mterp/arm/op_double_to_float.S
@@ -1 +1,2 @@
-%include "arm/funopNarrower.S" {"instr":"vcvt.f32.f64  s0, d0"}
+%def op_double_to_float():
+%  funopNarrower(instr="vcvt.f32.f64  s0, d0")
diff --git a/runtime/interpreter/mterp/arm/op_double_to_int.S b/runtime/interpreter/mterp/arm/op_double_to_int.S
index aa035de63ac5ea537878649704a6f8f2773cda67..e11daad4953f684a91cf87052405945ac315d646 100644
--- a/runtime/interpreter/mterp/arm/op_double_to_int.S
+++ b/runtime/interpreter/mterp/arm/op_double_to_int.S
@@ -1 +1,2 @@
-%include "arm/funopNarrower.S" {"instr":"ftosizd  s0, d0"}
+%def op_double_to_int():
+%  funopNarrower(instr="ftosizd  s0, d0")
diff --git a/runtime/interpreter/mterp/arm/op_double_to_long.S b/runtime/interpreter/mterp/arm/op_double_to_long.S
index 19ff7235e03b5d246c03baf8ef3696d5988d05e7..c47570430eda8c0696b776013d121c0b8e7bbcc5 100644
--- a/runtime/interpreter/mterp/arm/op_double_to_long.S
+++ b/runtime/interpreter/mterp/arm/op_double_to_long.S
@@ -1,6 +1,7 @@
-%include "arm/unopWide.S" {"instr":"bl      d2l_doconv"}
+%def op_double_to_long():
+%  unopWide(instr="bl      d2l_doconv")
 
-%break
+%def op_double_to_long_sister_code():
 /*
  * Convert the double in r0/r1 to a long in r0/r1.
  *
diff --git a/runtime/interpreter/mterp/arm/op_fill_array_data.S b/runtime/interpreter/mterp/arm/op_fill_array_data.S
index e1ca85c8661e6fbbcbe8de67d8e5a5b7085aa132..ea0d39724d4fca06d21287a037b8bad6d477edbf 100644
--- a/runtime/interpreter/mterp/arm/op_fill_array_data.S
+++ b/runtime/interpreter/mterp/arm/op_fill_array_data.S
@@ -1,3 +1,4 @@
+%def op_fill_array_data():
     /* fill-array-data vAA, +BBBBBBBB */
     EXPORT_PC
     FETCH r0, 1                         @ r0<- bbbb (lo)
diff --git a/runtime/interpreter/mterp/arm/op_filled_new_array.S b/runtime/interpreter/mterp/arm/op_filled_new_array.S
index 1075f0c68371df874e59ac70bec50b1dcc6cdbb5..fb1c3c5dc30b787d5480edf7b75bda9c9cdab5b7 100644
--- a/runtime/interpreter/mterp/arm/op_filled_new_array.S
+++ b/runtime/interpreter/mterp/arm/op_filled_new_array.S
@@ -1,4 +1,4 @@
-%default { "helper":"MterpFilledNewArray" }
+%def op_filled_new_array(helper="MterpFilledNewArray"):
     /*
      * Create a new array with elements filled from registers.
      *
diff --git a/runtime/interpreter/mterp/arm/op_filled_new_array_range.S b/runtime/interpreter/mterp/arm/op_filled_new_array_range.S
index 16567af567406c206d868cc6b9b4b9136106d1c9..1667de149ace0bdaaafcd36c43724422682df424 100644
--- a/runtime/interpreter/mterp/arm/op_filled_new_array_range.S
+++ b/runtime/interpreter/mterp/arm/op_filled_new_array_range.S
@@ -1 +1,2 @@
-%include "arm/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" }
+%def op_filled_new_array_range():
+%  op_filled_new_array(helper="MterpFilledNewArrayRange")
diff --git a/runtime/interpreter/mterp/arm/op_float_to_double.S b/runtime/interpreter/mterp/arm/op_float_to_double.S
index b1e12bdc7a5db3943144acee403bf79bb882cf7a..760466eec91179ed05ce179983a32615d3818240 100644
--- a/runtime/interpreter/mterp/arm/op_float_to_double.S
+++ b/runtime/interpreter/mterp/arm/op_float_to_double.S
@@ -1 +1,2 @@
-%include "arm/funopWider.S" {"instr":"vcvt.f64.f32  d0, s0"}
+%def op_float_to_double():
+%  funopWider(instr="vcvt.f64.f32  d0, s0")
diff --git a/runtime/interpreter/mterp/arm/op_float_to_int.S b/runtime/interpreter/mterp/arm/op_float_to_int.S
index aab87167bb8729faa01525342b0d7ffc072eecf8..77837ba3d58d4fad2c1d847a491c853cd9c62d92 100644
--- a/runtime/interpreter/mterp/arm/op_float_to_int.S
+++ b/runtime/interpreter/mterp/arm/op_float_to_int.S
@@ -1 +1,2 @@
-%include "arm/funop.S" {"instr":"ftosizs s1, s0"}
+%def op_float_to_int():
+%  funop(instr="ftosizs s1, s0")
diff --git a/runtime/interpreter/mterp/arm/op_float_to_long.S b/runtime/interpreter/mterp/arm/op_float_to_long.S
index 42bd98dbc25fdabc0a33cdfe4492dc4250800924..482b18e69fb852025de0553c2bf12a227660cf7a 100644
--- a/runtime/interpreter/mterp/arm/op_float_to_long.S
+++ b/runtime/interpreter/mterp/arm/op_float_to_long.S
@@ -1,6 +1,7 @@
-%include "arm/unopWider.S" {"instr":"bl      f2l_doconv"}
+%def op_float_to_long():
+%  unopWider(instr="bl      f2l_doconv")
 
-%break
+%def op_float_to_long_sister_code():
 /*
  * Convert the float in r0 to a long in r0/r1.
  *
diff --git a/runtime/interpreter/mterp/arm/op_goto.S b/runtime/interpreter/mterp/arm/op_goto.S
index aa42dfd843cd55f9357c3a8e5cc0d638c49aa383..832a9893393f5af9da05ef7a5e4faacb05a8b796 100644
--- a/runtime/interpreter/mterp/arm/op_goto.S
+++ b/runtime/interpreter/mterp/arm/op_goto.S
@@ -1,3 +1,4 @@
+%def op_goto():
     /*
      * Unconditional branch, 8-bit offset.
      *
diff --git a/runtime/interpreter/mterp/arm/op_goto_16.S b/runtime/interpreter/mterp/arm/op_goto_16.S
index 12a6bc07f88b617d3f04307945d31e93a6851bfd..4324a8d666779536c74b8a2ee89633d7a24658ec 100644
--- a/runtime/interpreter/mterp/arm/op_goto_16.S
+++ b/runtime/interpreter/mterp/arm/op_goto_16.S
@@ -1,3 +1,4 @@
+%def op_goto_16():
     /*
      * Unconditional branch, 16-bit offset.
      *
diff --git a/runtime/interpreter/mterp/arm/op_goto_32.S b/runtime/interpreter/mterp/arm/op_goto_32.S
index 7325a1c2d68071844a6204ca3bf518ab23214a18..b01d2fa71977a508fab0964db779db63b1605545 100644
--- a/runtime/interpreter/mterp/arm/op_goto_32.S
+++ b/runtime/interpreter/mterp/arm/op_goto_32.S
@@ -1,3 +1,4 @@
+%def op_goto_32():
     /*
      * Unconditional branch, 32-bit offset.
      *
diff --git a/runtime/interpreter/mterp/arm/op_if_eq.S b/runtime/interpreter/mterp/arm/op_if_eq.S
index b8b6a6eec1596e3cd741b8df2f7e6e0e27c83703..da58674fd4f81861aefae860c94e933f33d6cb26 100644
--- a/runtime/interpreter/mterp/arm/op_if_eq.S
+++ b/runtime/interpreter/mterp/arm/op_if_eq.S
@@ -1 +1,2 @@
-%include "arm/bincmp.S" { "condition":"eq" }
+%def op_if_eq():
+%  bincmp(condition="eq")
diff --git a/runtime/interpreter/mterp/arm/op_if_eqz.S b/runtime/interpreter/mterp/arm/op_if_eqz.S
index 7012f61c699e544fadf32da719680a669e27c194..0639664d474160ca776be5174315d4e6c5a89f75 100644
--- a/runtime/interpreter/mterp/arm/op_if_eqz.S
+++ b/runtime/interpreter/mterp/arm/op_if_eqz.S
@@ -1 +1,2 @@
-%include "arm/zcmp.S" { "condition":"eq" }
+%def op_if_eqz():
+%  zcmp(condition="eq")
diff --git a/runtime/interpreter/mterp/arm/op_if_ge.S b/runtime/interpreter/mterp/arm/op_if_ge.S
index eb29e63f7cb8da6256b0b819b83efdab806af390..5b6ed2f9944653fb88329ebabee2b2799299ce5d 100644
--- a/runtime/interpreter/mterp/arm/op_if_ge.S
+++ b/runtime/interpreter/mterp/arm/op_if_ge.S
@@ -1 +1,2 @@
-%include "arm/bincmp.S" { "condition":"ge" }
+%def op_if_ge():
+%  bincmp(condition="ge")
diff --git a/runtime/interpreter/mterp/arm/op_if_gez.S b/runtime/interpreter/mterp/arm/op_if_gez.S
index d9da374199bf1b2890cc86b21ccf114fc4fc9389..ea6cda71fb81ab4dd62e1283b3dcdfeb44afefc4 100644
--- a/runtime/interpreter/mterp/arm/op_if_gez.S
+++ b/runtime/interpreter/mterp/arm/op_if_gez.S
@@ -1 +1,2 @@
-%include "arm/zcmp.S" { "condition":"ge" }
+%def op_if_gez():
+%  zcmp(condition="ge")
diff --git a/runtime/interpreter/mterp/arm/op_if_gt.S b/runtime/interpreter/mterp/arm/op_if_gt.S
index a35eab8f47dc1953363f74a41806c8493c1a23d3..201decff1a91a48790fa913ac1d3efddfe919764 100644
--- a/runtime/interpreter/mterp/arm/op_if_gt.S
+++ b/runtime/interpreter/mterp/arm/op_if_gt.S
@@ -1 +1,2 @@
-%include "arm/bincmp.S" { "condition":"gt" }
+%def op_if_gt():
+%  bincmp(condition="gt")
diff --git a/runtime/interpreter/mterp/arm/op_if_gtz.S b/runtime/interpreter/mterp/arm/op_if_gtz.S
index 4ef4d8ee19114d2186ed42e26265c2805f76d1b0..1fdbb6e8d2aeb22a7b97cde39b7604db087f79d6 100644
--- a/runtime/interpreter/mterp/arm/op_if_gtz.S
+++ b/runtime/interpreter/mterp/arm/op_if_gtz.S
@@ -1 +1,2 @@
-%include "arm/zcmp.S" { "condition":"gt" }
+%def op_if_gtz():
+%  zcmp(condition="gt")
diff --git a/runtime/interpreter/mterp/arm/op_if_le.S b/runtime/interpreter/mterp/arm/op_if_le.S
index c7c31bc089be58c447567888da51dbfb4b4fc166..e6024f2b3e68b7b5654e49affe5582d6bd5ad598 100644
--- a/runtime/interpreter/mterp/arm/op_if_le.S
+++ b/runtime/interpreter/mterp/arm/op_if_le.S
@@ -1 +1,2 @@
-%include "arm/bincmp.S" { "condition":"le" }
+%def op_if_le():
+%  bincmp(condition="le")
diff --git a/runtime/interpreter/mterp/arm/op_if_lez.S b/runtime/interpreter/mterp/arm/op_if_lez.S
index 9fbf6c9f02c145c1daefd3ab82c2e2e9d4d5bbe6..62c0d2cd397e5dc55985ed32576521001e2e97a8 100644
--- a/runtime/interpreter/mterp/arm/op_if_lez.S
+++ b/runtime/interpreter/mterp/arm/op_if_lez.S
@@ -1 +1,2 @@
-%include "arm/zcmp.S" { "condition":"le" }
+%def op_if_lez():
+%  zcmp(condition="le")
diff --git a/runtime/interpreter/mterp/arm/op_if_lt.S b/runtime/interpreter/mterp/arm/op_if_lt.S
index 9469fbb1efe9404408a5253548e9835605d41bd4..4ef22fd7987d9f7c113d65b85290703c9d60cfe2 100644
--- a/runtime/interpreter/mterp/arm/op_if_lt.S
+++ b/runtime/interpreter/mterp/arm/op_if_lt.S
@@ -1 +1,2 @@
-%include "arm/bincmp.S" { "condition":"lt" }
+%def op_if_lt():
+%  bincmp(condition="lt")
diff --git a/runtime/interpreter/mterp/arm/op_if_ltz.S b/runtime/interpreter/mterp/arm/op_if_ltz.S
index a4fc1b8f0b858a38a5c8c63f3d0403c80b2cf11f..84b2d0b53a30d05690425994dad613278898adc0 100644
--- a/runtime/interpreter/mterp/arm/op_if_ltz.S
+++ b/runtime/interpreter/mterp/arm/op_if_ltz.S
@@ -1 +1,2 @@
-%include "arm/zcmp.S" { "condition":"lt" }
+%def op_if_ltz():
+%  zcmp(condition="lt")
diff --git a/runtime/interpreter/mterp/arm/op_if_ne.S b/runtime/interpreter/mterp/arm/op_if_ne.S
index c945331a31cd2f614eeec36cc7dedfaf90569bf9..ec3a688b294d4e3ceff3e99a22de2ecd4dcb220f 100644
--- a/runtime/interpreter/mterp/arm/op_if_ne.S
+++ b/runtime/interpreter/mterp/arm/op_if_ne.S
@@ -1 +1,2 @@
-%include "arm/bincmp.S" { "condition":"ne" }
+%def op_if_ne():
+%  bincmp(condition="ne")
diff --git a/runtime/interpreter/mterp/arm/op_if_nez.S b/runtime/interpreter/mterp/arm/op_if_nez.S
index 2d81fda444a6e2efc6201d3a2ba097edd1b193f3..7009c3acaa9c76772c2db07ea0576d28edeca34c 100644
--- a/runtime/interpreter/mterp/arm/op_if_nez.S
+++ b/runtime/interpreter/mterp/arm/op_if_nez.S
@@ -1 +1,2 @@
-%include "arm/zcmp.S" { "condition":"ne" }
+%def op_if_nez():
+%  zcmp(condition="ne")
diff --git a/runtime/interpreter/mterp/arm/op_iget.S b/runtime/interpreter/mterp/arm/op_iget.S
index 1fa32faa9966602c3834a71676389ebb27d708f3..d09edc0a17c38245736a29f1cf55eb6f5272b87d 100644
--- a/runtime/interpreter/mterp/arm/op_iget.S
+++ b/runtime/interpreter/mterp/arm/op_iget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIGetU32"}
-%include "arm/field.S" { }
+%def op_iget(is_object="0", helper="MterpIGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/arm/op_iget_boolean.S b/runtime/interpreter/mterp/arm/op_iget_boolean.S
index f23cb3aa97e8f6abf4af825791010c84d8728429..cb8edeec773fb6468b5c331b435e409da634f505 100644
--- a/runtime/interpreter/mterp/arm/op_iget_boolean.S
+++ b/runtime/interpreter/mterp/arm/op_iget_boolean.S
@@ -1 +1,2 @@
-%include "arm/op_iget.S" { "helper":"MterpIGetU8" }
+%def op_iget_boolean():
+%  op_iget(helper="MterpIGetU8")
diff --git a/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S b/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S
index 0ae4843595151785935812b5f23737a3e9b78d08..7ac9fce5353c1d73c1407533eaab319c1f43f360 100644
--- a/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S
@@ -1 +1,2 @@
-%include "arm/op_iget_quick.S" { "load":"ldrb" }
+%def op_iget_boolean_quick():
+%  op_iget_quick(load="ldrb")
diff --git a/runtime/interpreter/mterp/arm/op_iget_byte.S b/runtime/interpreter/mterp/arm/op_iget_byte.S
index 9c4f37c8ac8b1b4dca46e557aa645c1447eddd46..2b87fb16b560430baefa05d3f6e20195cb963d23 100644
--- a/runtime/interpreter/mterp/arm/op_iget_byte.S
+++ b/runtime/interpreter/mterp/arm/op_iget_byte.S
@@ -1 +1,2 @@
-%include "arm/op_iget.S" { "helper":"MterpIGetI8" }
+%def op_iget_byte():
+%  op_iget(helper="MterpIGetI8")
diff --git a/runtime/interpreter/mterp/arm/op_iget_byte_quick.S b/runtime/interpreter/mterp/arm/op_iget_byte_quick.S
index e1b3083404519d95b755b72833c6ecdd73608506..bbccaffe94cc357bd501c794d5a7f141379430ae 100644
--- a/runtime/interpreter/mterp/arm/op_iget_byte_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iget_byte_quick.S
@@ -1 +1,2 @@
-%include "arm/op_iget_quick.S" { "load":"ldrsb" }
+%def op_iget_byte_quick():
+%  op_iget_quick(load="ldrsb")
diff --git a/runtime/interpreter/mterp/arm/op_iget_char.S b/runtime/interpreter/mterp/arm/op_iget_char.S
index 80c4227ed2fc9be6a99cb6a1e7f5a4767211ae7f..001bd03e2b85edc215b29789ba4fc55044b4a230 100644
--- a/runtime/interpreter/mterp/arm/op_iget_char.S
+++ b/runtime/interpreter/mterp/arm/op_iget_char.S
@@ -1 +1,2 @@
-%include "arm/op_iget.S" { "helper":"MterpIGetU16" }
+%def op_iget_char():
+%  op_iget(helper="MterpIGetU16")
diff --git a/runtime/interpreter/mterp/arm/op_iget_char_quick.S b/runtime/interpreter/mterp/arm/op_iget_char_quick.S
index b44d8f14d8d27fa8aa42a6d8ae3d0667ea04ce7e..71a9276a81e1c2d8d9892edbb8aa77b97c2af05a 100644
--- a/runtime/interpreter/mterp/arm/op_iget_char_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iget_char_quick.S
@@ -1 +1,2 @@
-%include "arm/op_iget_quick.S" { "load":"ldrh" }
+%def op_iget_char_quick():
+%  op_iget_quick(load="ldrh")
diff --git a/runtime/interpreter/mterp/arm/op_iget_object.S b/runtime/interpreter/mterp/arm/op_iget_object.S
index e30b129efe586bf16eb692e77b3b0d7c924053d3..4e5f769547b494ed962728edba2d102a106b332a 100644
--- a/runtime/interpreter/mterp/arm/op_iget_object.S
+++ b/runtime/interpreter/mterp/arm/op_iget_object.S
@@ -1 +1,2 @@
-%include "arm/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" }
+%def op_iget_object():
+%  op_iget(is_object="1", helper="MterpIGetObj")
diff --git a/runtime/interpreter/mterp/arm/op_iget_object_quick.S b/runtime/interpreter/mterp/arm/op_iget_object_quick.S
index 16cb1189ad3ca91a819b6e84b5dcc632e8714945..72b04b8bb0d7104c6de0766829ea4341c96b3592 100644
--- a/runtime/interpreter/mterp/arm/op_iget_object_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iget_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iget_object_quick():
     /* For: iget-object-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
diff --git a/runtime/interpreter/mterp/arm/op_iget_quick.S b/runtime/interpreter/mterp/arm/op_iget_quick.S
index 0eaf364f6b07ade23a6ac26751236a7723211ae6..989449867dad4ed34e0b683f7b27ced25a9f892e 100644
--- a/runtime/interpreter/mterp/arm/op_iget_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iget_quick.S
@@ -1,4 +1,4 @@
-%default { "load":"ldr" }
+%def op_iget_quick(load="ldr"):
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
diff --git a/runtime/interpreter/mterp/arm/op_iget_short.S b/runtime/interpreter/mterp/arm/op_iget_short.S
index dd6bc9991c9ee34a895fd7f716b1b66a955ddf44..a62c4d998f1d05ed2a3bb1c2f2bf2cca501dfdb8 100644
--- a/runtime/interpreter/mterp/arm/op_iget_short.S
+++ b/runtime/interpreter/mterp/arm/op_iget_short.S
@@ -1 +1,2 @@
-%include "arm/op_iget.S" { "helper":"MterpIGetI16" }
+%def op_iget_short():
+%  op_iget(helper="MterpIGetI16")
diff --git a/runtime/interpreter/mterp/arm/op_iget_short_quick.S b/runtime/interpreter/mterp/arm/op_iget_short_quick.S
index 1831b99ac3c4241e2930fc16bc97a71f690bb673..5dbdc4fa22ba4d6df0a46ce57380919994cc3411 100644
--- a/runtime/interpreter/mterp/arm/op_iget_short_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iget_short_quick.S
@@ -1 +1,2 @@
-%include "arm/op_iget_quick.S" { "load":"ldrsh" }
+%def op_iget_short_quick():
+%  op_iget_quick(load="ldrsh")
diff --git a/runtime/interpreter/mterp/arm/op_iget_wide.S b/runtime/interpreter/mterp/arm/op_iget_wide.S
index ede21ebd35079ac2104ce7fb6006492036af9b0e..9643cc340313b657f2485df521ed0ee0cba25f7b 100644
--- a/runtime/interpreter/mterp/arm/op_iget_wide.S
+++ b/runtime/interpreter/mterp/arm/op_iget_wide.S
@@ -1 +1,2 @@
-%include "arm/op_iget.S" { "helper":"MterpIGetU64" }
+%def op_iget_wide():
+%  op_iget(helper="MterpIGetU64")
diff --git a/runtime/interpreter/mterp/arm/op_iget_wide_quick.S b/runtime/interpreter/mterp/arm/op_iget_wide_quick.S
index 5a7177d8f5f86b385eb9e09f92c254f6ebbce5aa..e247fb264024d32427d494606b7312be40a95ce4 100644
--- a/runtime/interpreter/mterp/arm/op_iget_wide_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iget_wide_quick.S
@@ -1,3 +1,4 @@
+%def op_iget_wide_quick():
     /* iget-wide-quick vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
     FETCH ip, 1                         @ ip<- field byte offset
diff --git a/runtime/interpreter/mterp/arm/op_instance_of.S b/runtime/interpreter/mterp/arm/op_instance_of.S
index 019929edf910da5e06d7e0159f46922466a80fd7..020b4c5feadf64021f30805f92b5f889700a822e 100644
--- a/runtime/interpreter/mterp/arm/op_instance_of.S
+++ b/runtime/interpreter/mterp/arm/op_instance_of.S
@@ -1,3 +1,4 @@
+%def op_instance_of():
     /*
      * Check to see if an object reference is an instance of a class.
      *
diff --git a/runtime/interpreter/mterp/arm/op_int_to_byte.S b/runtime/interpreter/mterp/arm/op_int_to_byte.S
index 059d5c2cf5037556b740ff52f530a94b88362ca4..3229b5ecf7f9e243e5e7716e0c1884d450b44f09 100644
--- a/runtime/interpreter/mterp/arm/op_int_to_byte.S
+++ b/runtime/interpreter/mterp/arm/op_int_to_byte.S
@@ -1 +1,2 @@
-%include "arm/unop.S" {"instr":"sxtb    r0, r0"}
+%def op_int_to_byte():
+%  unop(instr="sxtb    r0, r0")
diff --git a/runtime/interpreter/mterp/arm/op_int_to_char.S b/runtime/interpreter/mterp/arm/op_int_to_char.S
index 83a0c196d642856a1ba6f6397f40fd2f7938aa3f..9ce13b8b6ee940392a83bed200260a56d48115a9 100644
--- a/runtime/interpreter/mterp/arm/op_int_to_char.S
+++ b/runtime/interpreter/mterp/arm/op_int_to_char.S
@@ -1 +1,2 @@
-%include "arm/unop.S" {"instr":"uxth    r0, r0"}
+%def op_int_to_char():
+%  unop(instr="uxth    r0, r0")
diff --git a/runtime/interpreter/mterp/arm/op_int_to_double.S b/runtime/interpreter/mterp/arm/op_int_to_double.S
index 810c2e49bbfd4c0cc19514855ef31c84b62bdb93..cc8065a9bc2dc25358607fed8f40889a102d62db 100644
--- a/runtime/interpreter/mterp/arm/op_int_to_double.S
+++ b/runtime/interpreter/mterp/arm/op_int_to_double.S
@@ -1 +1,2 @@
-%include "arm/funopWider.S" {"instr":"fsitod  d0, s0"}
+%def op_int_to_double():
+%  funopWider(instr="fsitod  d0, s0")
diff --git a/runtime/interpreter/mterp/arm/op_int_to_float.S b/runtime/interpreter/mterp/arm/op_int_to_float.S
index f41654c678db1305d96f9d0fd41f17ed7583963a..b19f3f3164a7fbda8ccb81f4641f10d61262dbe1 100644
--- a/runtime/interpreter/mterp/arm/op_int_to_float.S
+++ b/runtime/interpreter/mterp/arm/op_int_to_float.S
@@ -1 +1,2 @@
-%include "arm/funop.S" {"instr":"fsitos  s1, s0"}
+%def op_int_to_float():
+%  funop(instr="fsitos  s1, s0")
diff --git a/runtime/interpreter/mterp/arm/op_int_to_long.S b/runtime/interpreter/mterp/arm/op_int_to_long.S
index b5aed8e0565a244966f48102b38ad636fdd35177..8d678991a4c02f434a9e47fabdc7f5d0a2193ea8 100644
--- a/runtime/interpreter/mterp/arm/op_int_to_long.S
+++ b/runtime/interpreter/mterp/arm/op_int_to_long.S
@@ -1 +1,2 @@
-%include "arm/unopWider.S" {"instr":"mov     r1, r0, asr #31"}
+%def op_int_to_long():
+%  unopWider(instr="mov     r1, r0, asr #31")
diff --git a/runtime/interpreter/mterp/arm/op_int_to_short.S b/runtime/interpreter/mterp/arm/op_int_to_short.S
index 717bd96bd18b13149213adf1b5013710f52f7ce5..2332460e076b3f066eb2fe23e419b9c6a7a38146 100644
--- a/runtime/interpreter/mterp/arm/op_int_to_short.S
+++ b/runtime/interpreter/mterp/arm/op_int_to_short.S
@@ -1 +1,2 @@
-%include "arm/unop.S" {"instr":"sxth    r0, r0"}
+%def op_int_to_short():
+%  unop(instr="sxth    r0, r0")
diff --git a/runtime/interpreter/mterp/arm/op_invoke_custom.S b/runtime/interpreter/mterp/arm/op_invoke_custom.S
index 2af875c9dfebc9952e72b782b734b6c0f750a768..0bd29b453afc32903fed6c57d97c1ae4d7a2f98a 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_custom.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_custom.S
@@ -1,4 +1,5 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeCustom" }
+%def op_invoke_custom():
+%  invoke(helper="MterpInvokeCustom")
     /*
      * Handle an invoke-custom invocation.
      *
diff --git a/runtime/interpreter/mterp/arm/op_invoke_custom_range.S b/runtime/interpreter/mterp/arm/op_invoke_custom_range.S
index 32575c4d45cf7669504a636cea43bcc6d93742cc..57e61af1fa860d814a9da1eaab56b25f199771aa 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_custom_range.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_custom_range.S
@@ -1 +1,2 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeCustomRange" }
+%def op_invoke_custom_range():
+%  invoke(helper="MterpInvokeCustomRange")
diff --git a/runtime/interpreter/mterp/arm/op_invoke_direct.S b/runtime/interpreter/mterp/arm/op_invoke_direct.S
index 1edf2219142bc4ed7443f79b95d45b0dc6f799c5..d3139cf39b42aca474e7d18dcf526e32e80ced85 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_direct.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_direct.S
@@ -1 +1,2 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeDirect" }
+%def op_invoke_direct():
+%  invoke(helper="MterpInvokeDirect")
diff --git a/runtime/interpreter/mterp/arm/op_invoke_direct_range.S b/runtime/interpreter/mterp/arm/op_invoke_direct_range.S
index 3097b8e2c79b3c620a75287a3da9834f0002c818..b4a161f48bf8b90b0561e577cdf35f27feb71f23 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_direct_range.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_direct_range.S
@@ -1 +1,2 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeDirectRange" }
+%def op_invoke_direct_range():
+%  invoke(helper="MterpInvokeDirectRange")
diff --git a/runtime/interpreter/mterp/arm/op_invoke_interface.S b/runtime/interpreter/mterp/arm/op_invoke_interface.S
index f6d565b16822c73cba4b884d8763b34b012dcfc1..b0641262530cb4359c0a054e8307346f64537478 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_interface.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_interface.S
@@ -1,4 +1,5 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeInterface" }
+%def op_invoke_interface():
+%  invoke(helper="MterpInvokeInterface")
     /*
      * Handle an interface method call.
      *
diff --git a/runtime/interpreter/mterp/arm/op_invoke_interface_range.S b/runtime/interpreter/mterp/arm/op_invoke_interface_range.S
index c8443b0cdc59e12cad99f177f046e90511e5a332..298911537760c27944307413bb6bbc1a686768a5 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_interface_range.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_interface_range.S
@@ -1 +1,2 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeInterfaceRange" }
+%def op_invoke_interface_range():
+%  invoke(helper="MterpInvokeInterfaceRange")
diff --git a/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S b/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S
index 816a7ae21761333af6b17647dd232ea929728803..ce61f5aa0e6039481359af9e0d7de053a159fc79 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S
@@ -1 +1,2 @@
-%include "arm/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" }
+%def op_invoke_polymorphic():
+%  invoke_polymorphic(helper="MterpInvokePolymorphic")
diff --git a/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S
index 2541c270e29f5663c05ea59c9f63e3a154d5704f..16731bdb4040829bf0020b8524b4f70866b1f1e8 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S
@@ -1 +1,2 @@
-%include "arm/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" }
+%def op_invoke_polymorphic_range():
+%  invoke_polymorphic(helper="MterpInvokePolymorphicRange")
diff --git a/runtime/interpreter/mterp/arm/op_invoke_static.S b/runtime/interpreter/mterp/arm/op_invoke_static.S
index c3cefcff46302479b83647623cdfc701449b20b3..3e38d36a27a20c1d0f1481b80d6585a43343b6cb 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_static.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_static.S
@@ -1,2 +1,3 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeStatic" }
+%def op_invoke_static():
+%  invoke(helper="MterpInvokeStatic")
 
diff --git a/runtime/interpreter/mterp/arm/op_invoke_static_range.S b/runtime/interpreter/mterp/arm/op_invoke_static_range.S
index dd60d7bbfad742d2dbeaf1759bd4ccf48fa92966..e0a546c92b4be72a4a5040d03e0018b1b248f536 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_static_range.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_static_range.S
@@ -1 +1,2 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeStaticRange" }
+%def op_invoke_static_range():
+%  invoke(helper="MterpInvokeStaticRange")
diff --git a/runtime/interpreter/mterp/arm/op_invoke_super.S b/runtime/interpreter/mterp/arm/op_invoke_super.S
index 92ef2a4e3e2f685cdb756d4d0a8fd7f4e4ea8af9..3c34c9942ead4172f252ab73aa378fdea74a2bf3 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_super.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_super.S
@@ -1,4 +1,5 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeSuper" }
+%def op_invoke_super():
+%  invoke(helper="MterpInvokeSuper")
     /*
      * Handle a "super" method call.
      *
diff --git a/runtime/interpreter/mterp/arm/op_invoke_super_range.S b/runtime/interpreter/mterp/arm/op_invoke_super_range.S
index 9e4fb1c9a1b78a1cf88ad2a10f6665a85c985426..caeafaa13c91fddf7dd3751252e4daf3045dcd2e 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_super_range.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_super_range.S
@@ -1 +1,2 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeSuperRange" }
+%def op_invoke_super_range():
+%  invoke(helper="MterpInvokeSuperRange")
diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual.S b/runtime/interpreter/mterp/arm/op_invoke_virtual.S
index 5b893ff866e631c8d961e45edb6a2b81427374ae..249177b813d3ffb3300010c511e78ff279b0ce61 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_virtual.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_virtual.S
@@ -1,4 +1,5 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeVirtual" }
+%def op_invoke_virtual():
+%  invoke(helper="MterpInvokeVirtual")
     /*
      * Handle a virtual method call.
      *
diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S
index 020e8b81350e01462d8332b35a7b3ea4d965f609..ea72c171ecfedd9ddb94bc2e2202e2c56ab11e53 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S
@@ -1 +1,2 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeVirtualQuick" }
+%def op_invoke_virtual_quick():
+%  invoke(helper="MterpInvokeVirtualQuick")
diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S
index 2b42a7863a34366fd886fb8abdfaec7bcdf0b559..baa077959359e0dcfbfd3b3cd9814c31b3f6d727 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S
@@ -1 +1,2 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeVirtualRange" }
+%def op_invoke_virtual_range():
+%  invoke(helper="MterpInvokeVirtualRange")
diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S
index 42f2deda39052dd78ea0d9bcfce143a23d2ee5c5..1d961a0781a94d0087847bce02fcae1f37a75f29 100644
--- a/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S
+++ b/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S
@@ -1 +1,2 @@
-%include "arm/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" }
+%def op_invoke_virtual_range_quick():
+%  invoke(helper="MterpInvokeVirtualQuickRange")
diff --git a/runtime/interpreter/mterp/arm/op_iput.S b/runtime/interpreter/mterp/arm/op_iput.S
index 6201d805f0da8609b233384d7ec53eeab47804e5..e5351baf557fe295afb718387a6de58585ba5184 100644
--- a/runtime/interpreter/mterp/arm/op_iput.S
+++ b/runtime/interpreter/mterp/arm/op_iput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIPutU32" }
-%include "arm/field.S" { }
+%def op_iput(is_object="0", helper="MterpIPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/arm/op_iput_boolean.S b/runtime/interpreter/mterp/arm/op_iput_boolean.S
index 57edadddd73cec143a84c047de9e351fbeac24fc..9eb849877b6207d46a36c083b47c83ebbd7e5d00 100644
--- a/runtime/interpreter/mterp/arm/op_iput_boolean.S
+++ b/runtime/interpreter/mterp/arm/op_iput_boolean.S
@@ -1 +1,2 @@
-%include "arm/op_iput.S" { "helper":"MterpIPutU8" }
+%def op_iput_boolean():
+%  op_iput(helper="MterpIPutU8")
diff --git a/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S b/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S
index f0a2777821430bac778fa7bf279a76cc77166f98..fd077a7792e25caa03e912c74f1db064ced5b90b 100644
--- a/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S
@@ -1 +1,2 @@
-%include "arm/op_iput_quick.S" { "store":"strb" }
+%def op_iput_boolean_quick():
+%  op_iput_quick(store="strb")
diff --git a/runtime/interpreter/mterp/arm/op_iput_byte.S b/runtime/interpreter/mterp/arm/op_iput_byte.S
index ab283b90fb679cd52327dde7f6278377fe22e9cc..4b74f9fb0e3c8bfe5566574fae72b21f71cd2067 100644
--- a/runtime/interpreter/mterp/arm/op_iput_byte.S
+++ b/runtime/interpreter/mterp/arm/op_iput_byte.S
@@ -1 +1,2 @@
-%include "arm/op_iput.S" { "helper":"MterpIPutI8" }
+%def op_iput_byte():
+%  op_iput(helper="MterpIPutI8")
diff --git a/runtime/interpreter/mterp/arm/op_iput_byte_quick.S b/runtime/interpreter/mterp/arm/op_iput_byte_quick.S
index f0a2777821430bac778fa7bf279a76cc77166f98..30238cf354ee51a9290acafab6ce7ee0506df51e 100644
--- a/runtime/interpreter/mterp/arm/op_iput_byte_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iput_byte_quick.S
@@ -1 +1,2 @@
-%include "arm/op_iput_quick.S" { "store":"strb" }
+%def op_iput_byte_quick():
+%  op_iput_quick(store="strb")
diff --git a/runtime/interpreter/mterp/arm/op_iput_char.S b/runtime/interpreter/mterp/arm/op_iput_char.S
index 0fe5d964ccc42ee5c8f3df36ad49d4087db92a12..64a249fc122e7eb749561fbc7ef7b3cc1be67382 100644
--- a/runtime/interpreter/mterp/arm/op_iput_char.S
+++ b/runtime/interpreter/mterp/arm/op_iput_char.S
@@ -1 +1,2 @@
-%include "arm/op_iput.S" { "helper":"MterpIPutU16" }
+%def op_iput_char():
+%  op_iput(helper="MterpIPutU16")
diff --git a/runtime/interpreter/mterp/arm/op_iput_char_quick.S b/runtime/interpreter/mterp/arm/op_iput_char_quick.S
index 5212fc355bf17e0d4836932682e77fc6892ca57e..0deff565030dde3597a48c8a7912bbcd9482d747 100644
--- a/runtime/interpreter/mterp/arm/op_iput_char_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iput_char_quick.S
@@ -1 +1,2 @@
-%include "arm/op_iput_quick.S" { "store":"strh" }
+%def op_iput_char_quick():
+%  op_iput_quick(store="strh")
diff --git a/runtime/interpreter/mterp/arm/op_iput_object.S b/runtime/interpreter/mterp/arm/op_iput_object.S
index 1003d10d4f74c3cf8fdd90eae643a3ed11ea7ce1..131edd5dbdae914ae95c3220d01788eba1a7ffb2 100644
--- a/runtime/interpreter/mterp/arm/op_iput_object.S
+++ b/runtime/interpreter/mterp/arm/op_iput_object.S
@@ -1 +1,2 @@
-%include "arm/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" }
+%def op_iput_object():
+%  op_iput(is_object="1", helper="MterpIPutObj")
diff --git a/runtime/interpreter/mterp/arm/op_iput_object_quick.S b/runtime/interpreter/mterp/arm/op_iput_object_quick.S
index 876b3daad8c98e0161e70edc5a556af387ca4183..be90b840e6112698f8751334824c4d5c77a1d554 100644
--- a/runtime/interpreter/mterp/arm/op_iput_object_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iput_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_object_quick():
     EXPORT_PC
     add     r0, rFP, #OFF_FP_SHADOWFRAME
     mov     r1, rPC
diff --git a/runtime/interpreter/mterp/arm/op_iput_quick.S b/runtime/interpreter/mterp/arm/op_iput_quick.S
index 98c8150cd65928c22987071e059fcc03451a3c12..f84c0982f334e6a84ca78f2663ec16194486e4c9 100644
--- a/runtime/interpreter/mterp/arm/op_iput_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iput_quick.S
@@ -1,4 +1,4 @@
-%default { "store":"str" }
+%def op_iput_quick(store="str"):
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
diff --git a/runtime/interpreter/mterp/arm/op_iput_short.S b/runtime/interpreter/mterp/arm/op_iput_short.S
index cc983630ffccc6b96623698273f98803f9bdab72..e631a3b259e969ae8ae1222244d299fd0e4da3d7 100644
--- a/runtime/interpreter/mterp/arm/op_iput_short.S
+++ b/runtime/interpreter/mterp/arm/op_iput_short.S
@@ -1 +1,2 @@
-%include "arm/op_iput.S" { "helper":"MterpIPutI16" }
+%def op_iput_short():
+%  op_iput(helper="MterpIPutI16")
diff --git a/runtime/interpreter/mterp/arm/op_iput_short_quick.S b/runtime/interpreter/mterp/arm/op_iput_short_quick.S
index 5212fc355bf17e0d4836932682e77fc6892ca57e..6a1b65194e1c31c8b0b188470ea8f2eca90c1d58 100644
--- a/runtime/interpreter/mterp/arm/op_iput_short_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iput_short_quick.S
@@ -1 +1,2 @@
-%include "arm/op_iput_quick.S" { "store":"strh" }
+%def op_iput_short_quick():
+%  op_iput_quick(store="strh")
diff --git a/runtime/interpreter/mterp/arm/op_iput_wide.S b/runtime/interpreter/mterp/arm/op_iput_wide.S
index f2845ad29c4b9b7de0d3bd2a9e8ec5843a284ee7..2f34fd39f9ed2ca1104582178602a4dac83ee761 100644
--- a/runtime/interpreter/mterp/arm/op_iput_wide.S
+++ b/runtime/interpreter/mterp/arm/op_iput_wide.S
@@ -1 +1,2 @@
-%include "arm/op_iput.S" { "helper":"MterpIPutU64" }
+%def op_iput_wide():
+%  op_iput(helper="MterpIPutU64")
diff --git a/runtime/interpreter/mterp/arm/op_iput_wide_quick.S b/runtime/interpreter/mterp/arm/op_iput_wide_quick.S
index 88e6ea102c36b4bee7be78bea8527c3bc2636205..8408f0a924e29a1ae51235239d49ed446c7fbdb6 100644
--- a/runtime/interpreter/mterp/arm/op_iput_wide_quick.S
+++ b/runtime/interpreter/mterp/arm/op_iput_wide_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_wide_quick():
     /* iput-wide-quick vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
     FETCH r3, 1                         @ r3<- field byte offset
diff --git a/runtime/interpreter/mterp/arm/op_long_to_double.S b/runtime/interpreter/mterp/arm/op_long_to_double.S
index cac12d48d45386c0f2d44c4330562a8dc4823ff6..3228c70929a38675a97fd9e3e2fe141762a1f7d0 100644
--- a/runtime/interpreter/mterp/arm/op_long_to_double.S
+++ b/runtime/interpreter/mterp/arm/op_long_to_double.S
@@ -1,4 +1,4 @@
-%default {}
+%def op_long_to_double():
     /*
      * Specialised 64-bit floating point operation.
      *
diff --git a/runtime/interpreter/mterp/arm/op_long_to_float.S b/runtime/interpreter/mterp/arm/op_long_to_float.S
index efa5a669135aadd5804901263b48bead06a41442..c0219754450d5359dc10a851837f112ae95e785e 100644
--- a/runtime/interpreter/mterp/arm/op_long_to_float.S
+++ b/runtime/interpreter/mterp/arm/op_long_to_float.S
@@ -1 +1,2 @@
-%include "arm/unopNarrower.S" {"instr":"bl      __aeabi_l2f"}
+%def op_long_to_float():
+%  unopNarrower(instr="bl      __aeabi_l2f")
diff --git a/runtime/interpreter/mterp/arm/op_long_to_int.S b/runtime/interpreter/mterp/arm/op_long_to_int.S
index 3e91f230b7579ae9ee54b189d998633433329f4b..eacb8f59ec402cbb87d740022854981c341e9a09 100644
--- a/runtime/interpreter/mterp/arm/op_long_to_int.S
+++ b/runtime/interpreter/mterp/arm/op_long_to_int.S
@@ -1,2 +1,3 @@
+%def op_long_to_int():
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-%include "arm/op_move.S"
+%  op_move()
diff --git a/runtime/interpreter/mterp/arm/op_monitor_enter.S b/runtime/interpreter/mterp/arm/op_monitor_enter.S
index 3c34f75d9dc673a7e4e6ae75af7e54526fb13067..afe293cb1b782fb224dd7645bde6e6c37306f82b 100644
--- a/runtime/interpreter/mterp/arm/op_monitor_enter.S
+++ b/runtime/interpreter/mterp/arm/op_monitor_enter.S
@@ -1,3 +1,4 @@
+%def op_monitor_enter():
     /*
      * Synchronize on an object.
      */
diff --git a/runtime/interpreter/mterp/arm/op_monitor_exit.S b/runtime/interpreter/mterp/arm/op_monitor_exit.S
index fc7cef5395fb12d431b6b70b419e367453c84702..ddfa7744efe15cd6ac90f2a236718ecc549df0bf 100644
--- a/runtime/interpreter/mterp/arm/op_monitor_exit.S
+++ b/runtime/interpreter/mterp/arm/op_monitor_exit.S
@@ -1,3 +1,4 @@
+%def op_monitor_exit():
     /*
      * Unlock an object.
      *
diff --git a/runtime/interpreter/mterp/arm/op_move.S b/runtime/interpreter/mterp/arm/op_move.S
index dfecc2432d44710ec0383e6537d5e0d8ead07cf2..7dd893fa66d348002f9233898f2d72b21e504372 100644
--- a/runtime/interpreter/mterp/arm/op_move.S
+++ b/runtime/interpreter/mterp/arm/op_move.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move(is_object="0"):
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     mov     r1, rINST, lsr #12          @ r1<- B from 15:12
diff --git a/runtime/interpreter/mterp/arm/op_move_16.S b/runtime/interpreter/mterp/arm/op_move_16.S
index 78138a238cb175f5786f3d2ec202cc40f1118848..86601aa28b46cad4abde7978f79172d75d8e739f 100644
--- a/runtime/interpreter/mterp/arm/op_move_16.S
+++ b/runtime/interpreter/mterp/arm/op_move_16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_16(is_object="0"):
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     FETCH r1, 2                         @ r1<- BBBB
diff --git a/runtime/interpreter/mterp/arm/op_move_exception.S b/runtime/interpreter/mterp/arm/op_move_exception.S
index 0242e26ee57fcf4fd63872679d11a17f426dd19b..91362285213d3a4efcabf5e28403826b441d0fc4 100644
--- a/runtime/interpreter/mterp/arm/op_move_exception.S
+++ b/runtime/interpreter/mterp/arm/op_move_exception.S
@@ -1,3 +1,4 @@
+%def op_move_exception():
     /* move-exception vAA */
     mov     r2, rINST, lsr #8           @ r2<- AA
     ldr     r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
diff --git a/runtime/interpreter/mterp/arm/op_move_from16.S b/runtime/interpreter/mterp/arm/op_move_from16.S
index 3e79417307856c3287fdf73a73f962542dd4f56f..113909c9f743ce2b7d6c68081fe0175e6725e47c 100644
--- a/runtime/interpreter/mterp/arm/op_move_from16.S
+++ b/runtime/interpreter/mterp/arm/op_move_from16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_from16(is_object="0"):
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     FETCH r1, 1                         @ r1<- BBBB
diff --git a/runtime/interpreter/mterp/arm/op_move_object.S b/runtime/interpreter/mterp/arm/op_move_object.S
index 16de57bac06e7621f0a60c1c0cee4f01da3ef95c..dbb4d5971027d54f58728020aadfa71973fb509a 100644
--- a/runtime/interpreter/mterp/arm/op_move_object.S
+++ b/runtime/interpreter/mterp/arm/op_move_object.S
@@ -1 +1,2 @@
-%include "arm/op_move.S" {"is_object":"1"}
+%def op_move_object():
+%  op_move(is_object="1")
diff --git a/runtime/interpreter/mterp/arm/op_move_object_16.S b/runtime/interpreter/mterp/arm/op_move_object_16.S
index 25343006a3b7f18c72717b59bbd42700570aed23..40120379d51d6027f960ef7742f12d8d16773855 100644
--- a/runtime/interpreter/mterp/arm/op_move_object_16.S
+++ b/runtime/interpreter/mterp/arm/op_move_object_16.S
@@ -1 +1,2 @@
-%include "arm/op_move_16.S" {"is_object":"1"}
+%def op_move_object_16():
+%  op_move_16(is_object="1")
diff --git a/runtime/interpreter/mterp/arm/op_move_object_from16.S b/runtime/interpreter/mterp/arm/op_move_object_from16.S
index 9e0cf02d17e74b29d7eb375d1317595022084e30..c82698e81e6805ad74ebe1f6c8c36e3ff3a1bd4b 100644
--- a/runtime/interpreter/mterp/arm/op_move_object_from16.S
+++ b/runtime/interpreter/mterp/arm/op_move_object_from16.S
@@ -1 +1,2 @@
-%include "arm/op_move_from16.S" {"is_object":"1"}
+%def op_move_object_from16():
+%  op_move_from16(is_object="1")
diff --git a/runtime/interpreter/mterp/arm/op_move_result.S b/runtime/interpreter/mterp/arm/op_move_result.S
index f2586a0769d2f33954f3118e607092afdb2babfb..eee23f6e25d9dd89e1605004bb7fb74ed15f328a 100644
--- a/runtime/interpreter/mterp/arm/op_move_result.S
+++ b/runtime/interpreter/mterp/arm/op_move_result.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_result(is_object="0"):
     /* for: move-result, move-result-object */
     /* op vAA */
     mov     r2, rINST, lsr #8           @ r2<- AA
diff --git a/runtime/interpreter/mterp/arm/op_move_result_object.S b/runtime/interpreter/mterp/arm/op_move_result_object.S
index 643296a5dc33369673aa9ef0d2b06260bce4bed7..87aea2646a6b25bae7ee8970a973915a76557939 100644
--- a/runtime/interpreter/mterp/arm/op_move_result_object.S
+++ b/runtime/interpreter/mterp/arm/op_move_result_object.S
@@ -1 +1,2 @@
-%include "arm/op_move_result.S" {"is_object":"1"}
+%def op_move_result_object():
+%  op_move_result(is_object="1")
diff --git a/runtime/interpreter/mterp/arm/op_move_result_wide.S b/runtime/interpreter/mterp/arm/op_move_result_wide.S
index 87929eaeeb0bca5439d3e3fda5cb244efc99110c..8b4e98034a56afad3261a78b692554935666abb7 100644
--- a/runtime/interpreter/mterp/arm/op_move_result_wide.S
+++ b/runtime/interpreter/mterp/arm/op_move_result_wide.S
@@ -1,3 +1,4 @@
+%def op_move_result_wide():
     /* move-result-wide vAA */
     mov     rINST, rINST, lsr #8        @ rINST<- AA
     ldr     r3, [rFP, #OFF_FP_RESULT_REGISTER]
diff --git a/runtime/interpreter/mterp/arm/op_move_wide.S b/runtime/interpreter/mterp/arm/op_move_wide.S
index ff353ea5d928e3f9e558182cad2e810e535cb054..800f7f6faab2e8205c316582347d3503d4c986ec 100644
--- a/runtime/interpreter/mterp/arm/op_move_wide.S
+++ b/runtime/interpreter/mterp/arm/op_move_wide.S
@@ -1,3 +1,4 @@
+%def op_move_wide():
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     mov     r3, rINST, lsr #12          @ r3<- B
diff --git a/runtime/interpreter/mterp/arm/op_move_wide_16.S b/runtime/interpreter/mterp/arm/op_move_wide_16.S
index 9812b66e97065113ca753325474c7a7c7cbe3686..ef4f0a8f59d1a348d855b6a0bfed9a5a8918ae25 100644
--- a/runtime/interpreter/mterp/arm/op_move_wide_16.S
+++ b/runtime/interpreter/mterp/arm/op_move_wide_16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_16():
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     FETCH r3, 2                         @ r3<- BBBB
diff --git a/runtime/interpreter/mterp/arm/op_move_wide_from16.S b/runtime/interpreter/mterp/arm/op_move_wide_from16.S
index d2cc60ca9da597d140b51d0d3235a00113b952b7..aae5aa323cec6bea5edf9638a221bb7b25f59260 100644
--- a/runtime/interpreter/mterp/arm/op_move_wide_from16.S
+++ b/runtime/interpreter/mterp/arm/op_move_wide_from16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_from16():
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     FETCH r3, 1                         @ r3<- BBBB
diff --git a/runtime/interpreter/mterp/arm/op_mul_double.S b/runtime/interpreter/mterp/arm/op_mul_double.S
index 530e85a39ed9c1e7fa6e857963d789d1be40688b..72948c22b80f63ab9a37a7fbb2d838c68f34ead3 100644
--- a/runtime/interpreter/mterp/arm/op_mul_double.S
+++ b/runtime/interpreter/mterp/arm/op_mul_double.S
@@ -1 +1,2 @@
-%include "arm/fbinopWide.S" {"instr":"fmuld   d2, d0, d1"}
+%def op_mul_double():
+%  fbinopWide(instr="fmuld   d2, d0, d1")
diff --git a/runtime/interpreter/mterp/arm/op_mul_double_2addr.S b/runtime/interpreter/mterp/arm/op_mul_double_2addr.S
index da1abc6e0413a15d996a01558f9aa038afc25ea2..afa7fcf6cb9ffde396ab1604155d9cd85af3e384 100644
--- a/runtime/interpreter/mterp/arm/op_mul_double_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_mul_double_2addr.S
@@ -1 +1,2 @@
-%include "arm/fbinopWide2addr.S" {"instr":"fmuld   d2, d0, d1"}
+%def op_mul_double_2addr():
+%  fbinopWide2addr(instr="fmuld   d2, d0, d1")
diff --git a/runtime/interpreter/mterp/arm/op_mul_float.S b/runtime/interpreter/mterp/arm/op_mul_float.S
index 6a72e6f42cfe07c411869ab09d0e6a7f580da349..ecb3717b0d3f2fb99b1bd41c779559bb6c01ab7d 100644
--- a/runtime/interpreter/mterp/arm/op_mul_float.S
+++ b/runtime/interpreter/mterp/arm/op_mul_float.S
@@ -1 +1,2 @@
-%include "arm/fbinop.S" {"instr":"fmuls   s2, s0, s1"}
+%def op_mul_float():
+%  fbinop(instr="fmuls   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm/op_mul_float_2addr.S b/runtime/interpreter/mterp/arm/op_mul_float_2addr.S
index edb51016664ec713b5173234f0f3762de9e7b1de..d084b1171b0883da5021fb039ea7adb2d5bdb4bb 100644
--- a/runtime/interpreter/mterp/arm/op_mul_float_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_mul_float_2addr.S
@@ -1 +1,2 @@
-%include "arm/fbinop2addr.S" {"instr":"fmuls   s2, s0, s1"}
+%def op_mul_float_2addr():
+%  fbinop2addr(instr="fmuls   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm/op_mul_int.S b/runtime/interpreter/mterp/arm/op_mul_int.S
index d6151d4d4557cbf46d81cc0ddad29a375bd4fa22..8a7daf2c35e618c6e7f9e9d6d2c0da9c18e325a0 100644
--- a/runtime/interpreter/mterp/arm/op_mul_int.S
+++ b/runtime/interpreter/mterp/arm/op_mul_int.S
@@ -1,2 +1,3 @@
+%def op_mul_int():
 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
-%include "arm/binop.S" {"instr":"mul     r0, r1, r0"}
+%  binop(instr="mul     r0, r1, r0")
diff --git a/runtime/interpreter/mterp/arm/op_mul_int_2addr.S b/runtime/interpreter/mterp/arm/op_mul_int_2addr.S
index 66a797d9fef8ac40e182dc1270e2a74340307104..98bfb7a9d9dbae6864b47825e2e0ca16eb1f7c16 100644
--- a/runtime/interpreter/mterp/arm/op_mul_int_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_mul_int_2addr.S
@@ -1,2 +1,3 @@
+%def op_mul_int_2addr():
 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
-%include "arm/binop2addr.S" {"instr":"mul     r0, r1, r0"}
+%  binop2addr(instr="mul     r0, r1, r0")
diff --git a/runtime/interpreter/mterp/arm/op_mul_int_lit16.S b/runtime/interpreter/mterp/arm/op_mul_int_lit16.S
index 4e40c438f74e6e7c4b6a3aa04fe3a1aded12f5b7..ab3f36122c9fa572ae2937e8ee666b4b65788ffe 100644
--- a/runtime/interpreter/mterp/arm/op_mul_int_lit16.S
+++ b/runtime/interpreter/mterp/arm/op_mul_int_lit16.S
@@ -1,2 +1,3 @@
+%def op_mul_int_lit16():
 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
-%include "arm/binopLit16.S" {"instr":"mul     r0, r1, r0"}
+%  binopLit16(instr="mul     r0, r1, r0")
diff --git a/runtime/interpreter/mterp/arm/op_mul_int_lit8.S b/runtime/interpreter/mterp/arm/op_mul_int_lit8.S
index dbafae9d24d0c2ebe9a4b1c24a346cc5d7160609..6cc5b89652645893012cd723788299eb254ce0f0 100644
--- a/runtime/interpreter/mterp/arm/op_mul_int_lit8.S
+++ b/runtime/interpreter/mterp/arm/op_mul_int_lit8.S
@@ -1,2 +1,3 @@
+%def op_mul_int_lit8():
 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
-%include "arm/binopLit8.S" {"instr":"mul     r0, r1, r0"}
+%  binopLit8(instr="mul     r0, r1, r0")
diff --git a/runtime/interpreter/mterp/arm/op_mul_long.S b/runtime/interpreter/mterp/arm/op_mul_long.S
index 4f55280871a4a8b65ec267b4985efe1c75c8c789..c9f2e67323e4cc0a5434eb6979535a47bcc2a8fe 100644
--- a/runtime/interpreter/mterp/arm/op_mul_long.S
+++ b/runtime/interpreter/mterp/arm/op_mul_long.S
@@ -1,3 +1,4 @@
+%def op_mul_long():
     /*
      * Signed 64-bit integer multiply.
      *
diff --git a/runtime/interpreter/mterp/arm/op_mul_long_2addr.S b/runtime/interpreter/mterp/arm/op_mul_long_2addr.S
index 4c1f058260887ee3e9753060e8b8421a4a0dabd3..2fd9f5c34b311419ec6bc5c6ca496b4c5ed69feb 100644
--- a/runtime/interpreter/mterp/arm/op_mul_long_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_mul_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_mul_long_2addr():
     /*
      * Signed 64-bit integer multiply, "/2addr" version.
      *
diff --git a/runtime/interpreter/mterp/arm/op_neg_double.S b/runtime/interpreter/mterp/arm/op_neg_double.S
index 33e609cbfabd4a1e268236459176ea951d05ed56..df73341b5cfcf714b86795ec924c3eb6b5611b16 100644
--- a/runtime/interpreter/mterp/arm/op_neg_double.S
+++ b/runtime/interpreter/mterp/arm/op_neg_double.S
@@ -1 +1,2 @@
-%include "arm/unopWide.S" {"instr":"add     r1, r1, #0x80000000"}
+%def op_neg_double():
+%  unopWide(instr="add     r1, r1, #0x80000000")
diff --git a/runtime/interpreter/mterp/arm/op_neg_float.S b/runtime/interpreter/mterp/arm/op_neg_float.S
index 993583fc867f539209658ca14bf25c80603b89e1..4ed178fb29b75ba4c1f7e947d8e92cf99b332f1c 100644
--- a/runtime/interpreter/mterp/arm/op_neg_float.S
+++ b/runtime/interpreter/mterp/arm/op_neg_float.S
@@ -1 +1,2 @@
-%include "arm/unop.S" {"instr":"add     r0, r0, #0x80000000"}
+%def op_neg_float():
+%  unop(instr="add     r0, r0, #0x80000000")
diff --git a/runtime/interpreter/mterp/arm/op_neg_int.S b/runtime/interpreter/mterp/arm/op_neg_int.S
index ec0b253745d7b1738e4257e80b3d5b619ba12b64..08b72a168cb3f71d900f80e70d56249ce026ddb1 100644
--- a/runtime/interpreter/mterp/arm/op_neg_int.S
+++ b/runtime/interpreter/mterp/arm/op_neg_int.S
@@ -1 +1,2 @@
-%include "arm/unop.S" {"instr":"rsb     r0, r0, #0"}
+%def op_neg_int():
+%  unop(instr="rsb     r0, r0, #0")
diff --git a/runtime/interpreter/mterp/arm/op_neg_long.S b/runtime/interpreter/mterp/arm/op_neg_long.S
index dab2eb492ec95009787685c233b1d2a20d792595..716c6dc643a9a207704b16ad90b97ef893896b76 100644
--- a/runtime/interpreter/mterp/arm/op_neg_long.S
+++ b/runtime/interpreter/mterp/arm/op_neg_long.S
@@ -1 +1,2 @@
-%include "arm/unopWide.S" {"preinstr":"rsbs    r0, r0, #0", "instr":"rsc     r1, r1, #0"}
+%def op_neg_long():
+%  unopWide(preinstr="rsbs    r0, r0, #0", instr="rsc     r1, r1, #0")
diff --git a/runtime/interpreter/mterp/arm/op_new_array.S b/runtime/interpreter/mterp/arm/op_new_array.S
index 8bb792c2173cd18e9a96f80c85ba0583b003a829..04b5fa4b118b5d5a16c09437d9b6760d1874c54a 100644
--- a/runtime/interpreter/mterp/arm/op_new_array.S
+++ b/runtime/interpreter/mterp/arm/op_new_array.S
@@ -1,3 +1,4 @@
+%def op_new_array():
     /*
      * Allocate an array of objects, specified with the array class
      * and a count.
diff --git a/runtime/interpreter/mterp/arm/op_new_instance.S b/runtime/interpreter/mterp/arm/op_new_instance.S
index 95d4be8762249c1a0110e933fbfbeb4f81f55f85..447a6cfc0fc670676388d7e44dd6eb9afcbfd5b9 100644
--- a/runtime/interpreter/mterp/arm/op_new_instance.S
+++ b/runtime/interpreter/mterp/arm/op_new_instance.S
@@ -1,3 +1,4 @@
+%def op_new_instance():
     /*
      * Create a new instance of a class.
      */
diff --git a/runtime/interpreter/mterp/arm/op_nop.S b/runtime/interpreter/mterp/arm/op_nop.S
index af0f88f7e37c6234be3a1f37ddfbf9bb0e39d200..8bfd1a3557cc390ef6b8176e981fbaa8142d6884 100644
--- a/runtime/interpreter/mterp/arm/op_nop.S
+++ b/runtime/interpreter/mterp/arm/op_nop.S
@@ -1,3 +1,4 @@
+%def op_nop():
     FETCH_ADVANCE_INST 1                @ advance to next instr, load rINST
     GET_INST_OPCODE ip                  @ ip<- opcode from rINST
     GOTO_OPCODE ip                      @ execute it
diff --git a/runtime/interpreter/mterp/arm/op_not_int.S b/runtime/interpreter/mterp/arm/op_not_int.S
index 816485ae6ac4779fe29cfba13c450401bf836bc8..90c4eed34b0c926d1096962a25ba0ed74565d399 100644
--- a/runtime/interpreter/mterp/arm/op_not_int.S
+++ b/runtime/interpreter/mterp/arm/op_not_int.S
@@ -1 +1,2 @@
-%include "arm/unop.S" {"instr":"mvn     r0, r0"}
+%def op_not_int():
+%  unop(instr="mvn     r0, r0")
diff --git a/runtime/interpreter/mterp/arm/op_not_long.S b/runtime/interpreter/mterp/arm/op_not_long.S
index 49a59056d51466d50988fd03d7213ec8aa60d845..29104f2ff7e3561bbcf6b6556944e2405ff8712f 100644
--- a/runtime/interpreter/mterp/arm/op_not_long.S
+++ b/runtime/interpreter/mterp/arm/op_not_long.S
@@ -1 +1,2 @@
-%include "arm/unopWide.S" {"preinstr":"mvn     r0, r0", "instr":"mvn     r1, r1"}
+%def op_not_long():
+%  unopWide(preinstr="mvn     r0, r0", instr="mvn     r1, r1")
diff --git a/runtime/interpreter/mterp/arm/op_or_int.S b/runtime/interpreter/mterp/arm/op_or_int.S
index b046e8d8d83a60cadc4c3a411cb97fe5242ba91d..6992d2ac3d6ddd1fa10a22d383bdec88bff83ec5 100644
--- a/runtime/interpreter/mterp/arm/op_or_int.S
+++ b/runtime/interpreter/mterp/arm/op_or_int.S
@@ -1 +1,2 @@
-%include "arm/binop.S" {"instr":"orr     r0, r0, r1"}
+%def op_or_int():
+%  binop(instr="orr     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_or_int_2addr.S b/runtime/interpreter/mterp/arm/op_or_int_2addr.S
index 493c59f285968c3df694caf933b16e02bbeb9922..805ca0916958bac272cce9fe03328ba34d6a8b4d 100644
--- a/runtime/interpreter/mterp/arm/op_or_int_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_or_int_2addr.S
@@ -1 +1,2 @@
-%include "arm/binop2addr.S" {"instr":"orr     r0, r0, r1"}
+%def op_or_int_2addr():
+%  binop2addr(instr="orr     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_or_int_lit16.S b/runtime/interpreter/mterp/arm/op_or_int_lit16.S
index 0a01db80521dd4d2bb6c3d27386df19d2bd645c9..03bf4edc5418c6df8df99c2c2c8b3391858ac506 100644
--- a/runtime/interpreter/mterp/arm/op_or_int_lit16.S
+++ b/runtime/interpreter/mterp/arm/op_or_int_lit16.S
@@ -1 +1,2 @@
-%include "arm/binopLit16.S" {"instr":"orr     r0, r0, r1"}
+%def op_or_int_lit16():
+%  binopLit16(instr="orr     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_or_int_lit8.S b/runtime/interpreter/mterp/arm/op_or_int_lit8.S
index 9882bfcf5ed427c01ab9072ced1d3b92c0653e3a..a29d73f322022838b420bbd826a3a6d5f97decd5 100644
--- a/runtime/interpreter/mterp/arm/op_or_int_lit8.S
+++ b/runtime/interpreter/mterp/arm/op_or_int_lit8.S
@@ -1 +1,2 @@
-%include "arm/binopLit8.S" {"extract":"", "instr":"orr     r0, r0, r3, asr #8"}
+%def op_or_int_lit8():
+%  binopLit8(extract="", instr="orr     r0, r0, r3, asr #8")
diff --git a/runtime/interpreter/mterp/arm/op_or_long.S b/runtime/interpreter/mterp/arm/op_or_long.S
index 048c45ccb52f5b5e69f06e38db08a89e1e5dced4..327870037589e1739c4e37329965b503467d4f1e 100644
--- a/runtime/interpreter/mterp/arm/op_or_long.S
+++ b/runtime/interpreter/mterp/arm/op_or_long.S
@@ -1 +1,2 @@
-%include "arm/binopWide.S" {"preinstr":"orr     r0, r0, r2", "instr":"orr     r1, r1, r3"}
+%def op_or_long():
+%  binopWide(preinstr="orr     r0, r0, r2", instr="orr     r1, r1, r3")
diff --git a/runtime/interpreter/mterp/arm/op_or_long_2addr.S b/runtime/interpreter/mterp/arm/op_or_long_2addr.S
index 93953461ba2f41c35c18a177827f36c50fbeed55..56ce5e628e3c2ec0961ac97c2af7aebd5eeb0dc9 100644
--- a/runtime/interpreter/mterp/arm/op_or_long_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_or_long_2addr.S
@@ -1 +1,2 @@
-%include "arm/binopWide2addr.S" {"preinstr":"orr     r0, r0, r2", "instr":"orr     r1, r1, r3"}
+%def op_or_long_2addr():
+%  binopWide2addr(preinstr="orr     r0, r0, r2", instr="orr     r1, r1, r3")
diff --git a/runtime/interpreter/mterp/arm/op_packed_switch.S b/runtime/interpreter/mterp/arm/op_packed_switch.S
index 412c58f1bcdc8831059cfb8105d5404087c90b07..26af19db2218fdd8b30af38224786111c80af9a5 100644
--- a/runtime/interpreter/mterp/arm/op_packed_switch.S
+++ b/runtime/interpreter/mterp/arm/op_packed_switch.S
@@ -1,4 +1,4 @@
-%default { "func":"MterpDoPackedSwitch" }
+%def op_packed_switch(func="MterpDoPackedSwitch"):
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
diff --git a/runtime/interpreter/mterp/arm/op_rem_double.S b/runtime/interpreter/mterp/arm/op_rem_double.S
index b539221eacee3b1959d570e2433dc431ea8d7c12..1e1e680d5f21f7e039faa9dc24f6c7592b46c672 100644
--- a/runtime/interpreter/mterp/arm/op_rem_double.S
+++ b/runtime/interpreter/mterp/arm/op_rem_double.S
@@ -1,2 +1,3 @@
+%def op_rem_double():
 /* EABI doesn't define a double remainder function, but libm does */
-%include "arm/binopWide.S" {"instr":"bl      fmod"}
+%  binopWide(instr="bl      fmod")
diff --git a/runtime/interpreter/mterp/arm/op_rem_double_2addr.S b/runtime/interpreter/mterp/arm/op_rem_double_2addr.S
index 372ef1dfe66b133b05985cf861af7c56c608bb30..8db1cdecbd2afbbb7edbd477a7c971634ac4dbb2 100644
--- a/runtime/interpreter/mterp/arm/op_rem_double_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_rem_double_2addr.S
@@ -1,2 +1,3 @@
+%def op_rem_double_2addr():
 /* EABI doesn't define a double remainder function, but libm does */
-%include "arm/binopWide2addr.S" {"instr":"bl      fmod"}
+%  binopWide2addr(instr="bl      fmod")
diff --git a/runtime/interpreter/mterp/arm/op_rem_float.S b/runtime/interpreter/mterp/arm/op_rem_float.S
index 7bd10deafed979b0ca275f860a8ff6e9cba86bec..5362e0a5f25981d550bc528fc51ebf88b3aea92d 100644
--- a/runtime/interpreter/mterp/arm/op_rem_float.S
+++ b/runtime/interpreter/mterp/arm/op_rem_float.S
@@ -1,2 +1,3 @@
+%def op_rem_float():
 /* EABI doesn't define a float remainder function, but libm does */
-%include "arm/binop.S" {"instr":"bl      fmodf"}
+%  binop(instr="bl      fmodf")
diff --git a/runtime/interpreter/mterp/arm/op_rem_float_2addr.S b/runtime/interpreter/mterp/arm/op_rem_float_2addr.S
index 93c5faef68704529984570160226b1904b5fa919..90ff391990741897d6ce8e6c1fbe992cfa753c63 100644
--- a/runtime/interpreter/mterp/arm/op_rem_float_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_rem_float_2addr.S
@@ -1,2 +1,3 @@
+%def op_rem_float_2addr():
 /* EABI doesn't define a float remainder function, but libm does */
-%include "arm/binop2addr.S" {"instr":"bl      fmodf"}
+%  binop2addr(instr="bl      fmodf")
diff --git a/runtime/interpreter/mterp/arm/op_rem_int.S b/runtime/interpreter/mterp/arm/op_rem_int.S
index ff6257340f66f8139c333e6e8c6660a51e88267d..068870e02c8ea9e9c9994613a1288b3d84b8ecb1 100644
--- a/runtime/interpreter/mterp/arm/op_rem_int.S
+++ b/runtime/interpreter/mterp/arm/op_rem_int.S
@@ -1,4 +1,4 @@
-%default {}
+%def op_rem_int():
     /*
      * Specialized 32-bit binary operation
      *
diff --git a/runtime/interpreter/mterp/arm/op_rem_int_2addr.S b/runtime/interpreter/mterp/arm/op_rem_int_2addr.S
index ba5751a2aec32bb6292ab34b496c5e8bc9043547..22ade95135433318f1b30013d576cd4ce00b10d5 100644
--- a/runtime/interpreter/mterp/arm/op_rem_int_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_rem_int_2addr.S
@@ -1,4 +1,4 @@
-%default {}
+%def op_rem_int_2addr():
     /*
      * Specialized 32-bit binary operation
      *
diff --git a/runtime/interpreter/mterp/arm/op_rem_int_lit16.S b/runtime/interpreter/mterp/arm/op_rem_int_lit16.S
index 4edb187f50dbed49a4cda998862f425791fe9a91..0605663ce23b34ab6b0bbedc018b952ed9150a56 100644
--- a/runtime/interpreter/mterp/arm/op_rem_int_lit16.S
+++ b/runtime/interpreter/mterp/arm/op_rem_int_lit16.S
@@ -1,4 +1,4 @@
-%default {}
+%def op_rem_int_lit16():
     /*
      * Specialized 32-bit binary operation
      *
diff --git a/runtime/interpreter/mterp/arm/op_rem_int_lit8.S b/runtime/interpreter/mterp/arm/op_rem_int_lit8.S
index 3888361bc5a0c04b83fbc9d17bd4e295ffdeafca..9b6867bac37081b14fd1f06bca74d22fca91fe20 100644
--- a/runtime/interpreter/mterp/arm/op_rem_int_lit8.S
+++ b/runtime/interpreter/mterp/arm/op_rem_int_lit8.S
@@ -1,4 +1,4 @@
-%default {}
+%def op_rem_int_lit8():
     /*
      * Specialized 32-bit binary operation
      *
diff --git a/runtime/interpreter/mterp/arm/op_rem_long.S b/runtime/interpreter/mterp/arm/op_rem_long.S
index b2b1c2418783dbe3749159f55d9b324381ba1e79..a44827f8a153b804e652395193970e78e752ff01 100644
--- a/runtime/interpreter/mterp/arm/op_rem_long.S
+++ b/runtime/interpreter/mterp/arm/op_rem_long.S
@@ -1,2 +1,3 @@
+%def op_rem_long():
 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
-%include "arm/binopWide.S" {"instr":"bl      __aeabi_ldivmod", "result0":"r2", "result1":"r3", "chkzero":"1"}
+%  binopWide(instr="bl      __aeabi_ldivmod", result0="r2", result1="r3", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm/op_rem_long_2addr.S b/runtime/interpreter/mterp/arm/op_rem_long_2addr.S
index f87d493a9126ab83f3a94ccf97946824f2783014..cf3496466708414dd45fd14b578cf634091eba6b 100644
--- a/runtime/interpreter/mterp/arm/op_rem_long_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_rem_long_2addr.S
@@ -1,2 +1,3 @@
+%def op_rem_long_2addr():
 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
-%include "arm/binopWide2addr.S" {"instr":"bl      __aeabi_ldivmod", "result0":"r2", "result1":"r3", "chkzero":"1"}
+%  binopWide2addr(instr="bl      __aeabi_ldivmod", result0="r2", result1="r3", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm/op_return.S b/runtime/interpreter/mterp/arm/op_return.S
index f9c0f0fa1966ec0d1ccb98f5297c95419a4939ac..fe35ec903570c18f1d8d1f73db18bfb031a1c9f2 100644
--- a/runtime/interpreter/mterp/arm/op_return.S
+++ b/runtime/interpreter/mterp/arm/op_return.S
@@ -1,3 +1,4 @@
+%def op_return():
     /*
      * Return a 32-bit value.
      *
diff --git a/runtime/interpreter/mterp/arm/op_return_object.S b/runtime/interpreter/mterp/arm/op_return_object.S
index c4907302c9c809aa9873b8547a6605f3e1315d8a..2eeec0b94824884ff1b3c0aeccbfa0948268f9ab 100644
--- a/runtime/interpreter/mterp/arm/op_return_object.S
+++ b/runtime/interpreter/mterp/arm/op_return_object.S
@@ -1 +1,2 @@
-%include "arm/op_return.S"
+%def op_return_object():
+%  op_return()
diff --git a/runtime/interpreter/mterp/arm/op_return_void.S b/runtime/interpreter/mterp/arm/op_return_void.S
index a91ccb31f5cec8e97ffbebd8d8b05088825b05df..2418c6a1f74785ed191d91e4e7d78faf6e677222 100644
--- a/runtime/interpreter/mterp/arm/op_return_void.S
+++ b/runtime/interpreter/mterp/arm/op_return_void.S
@@ -1,3 +1,4 @@
+%def op_return_void():
     .extern MterpThreadFenceForConstructor
     bl      MterpThreadFenceForConstructor
     ldr     lr, [rSELF, #THREAD_FLAGS_OFFSET]
diff --git a/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S b/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S
index b953f4c7fd1f44db39e04270ec3000a54b082757..fa4cc0abeec8f0108dd6c8191aa16d1f19d270cd 100644
--- a/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S
+++ b/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S
@@ -1,3 +1,4 @@
+%def op_return_void_no_barrier():
     ldr     lr, [rSELF, #THREAD_FLAGS_OFFSET]
     mov     r0, rSELF
     ands    lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
diff --git a/runtime/interpreter/mterp/arm/op_return_wide.S b/runtime/interpreter/mterp/arm/op_return_wide.S
index df582c08316dbabee0d150ffec133980e6161c0f..a2a3be41ef67e71d481919fa609faa845d41dcf6 100644
--- a/runtime/interpreter/mterp/arm/op_return_wide.S
+++ b/runtime/interpreter/mterp/arm/op_return_wide.S
@@ -1,3 +1,4 @@
+%def op_return_wide():
     /*
      * Return a 64-bit value.
      */
diff --git a/runtime/interpreter/mterp/arm/op_rsub_int.S b/runtime/interpreter/mterp/arm/op_rsub_int.S
index 1508dd437325736a81db19fc00a4336af7a10883..5d41f6d63b9135e217fba7399518be75afc5d1bf 100644
--- a/runtime/interpreter/mterp/arm/op_rsub_int.S
+++ b/runtime/interpreter/mterp/arm/op_rsub_int.S
@@ -1,2 +1,3 @@
+%def op_rsub_int():
 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
-%include "arm/binopLit16.S" {"instr":"rsb     r0, r0, r1"}
+%  binopLit16(instr="rsb     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S b/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S
index dc953dcc4ad79829160ff514de731aa1ea3662ce..5ce759de4db95ba6b4c585f9e145a2e8fa369a98 100644
--- a/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S
+++ b/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S
@@ -1 +1,2 @@
-%include "arm/binopLit8.S" {"extract":"", "instr":"rsb     r0, r0, r3, asr #8"}
+%def op_rsub_int_lit8():
+%  binopLit8(extract="", instr="rsb     r0, r0, r3, asr #8")
diff --git a/runtime/interpreter/mterp/arm/op_sget.S b/runtime/interpreter/mterp/arm/op_sget.S
index b382de4c8defbc43b84cc8f386368409b1ed30ac..8a6a66ab6032f5a140fcaa4cb0f85af9cb84bd7a 100644
--- a/runtime/interpreter/mterp/arm/op_sget.S
+++ b/runtime/interpreter/mterp/arm/op_sget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSGetU32" }
-%include "arm/field.S" { }
+%def op_sget(is_object="0", helper="MterpSGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/arm/op_sget_boolean.S b/runtime/interpreter/mterp/arm/op_sget_boolean.S
index df1a0246b58867a83c185d836388d3b084ca69c0..d9c12c9b280100ec8c517e2c264d9c99022bb429 100644
--- a/runtime/interpreter/mterp/arm/op_sget_boolean.S
+++ b/runtime/interpreter/mterp/arm/op_sget_boolean.S
@@ -1 +1,2 @@
-%include "arm/op_sget.S" {"helper":"MterpSGetU8"}
+%def op_sget_boolean():
+%  op_sget(helper="MterpSGetU8")
diff --git a/runtime/interpreter/mterp/arm/op_sget_byte.S b/runtime/interpreter/mterp/arm/op_sget_byte.S
index 8ad3ff0e651a43f0798da2449f039398cee956bb..37c6879cd4b02e1fe323434a8f0e490352d4d391 100644
--- a/runtime/interpreter/mterp/arm/op_sget_byte.S
+++ b/runtime/interpreter/mterp/arm/op_sget_byte.S
@@ -1 +1,2 @@
-%include "arm/op_sget.S" {"helper":"MterpSGetI8"}
+%def op_sget_byte():
+%  op_sget(helper="MterpSGetI8")
diff --git a/runtime/interpreter/mterp/arm/op_sget_char.S b/runtime/interpreter/mterp/arm/op_sget_char.S
index 523951490a8acb0718de78bca44d2a3a51e53aa2..003bcd16833da0b4c77b8ef60e71ee9bbb01e8da 100644
--- a/runtime/interpreter/mterp/arm/op_sget_char.S
+++ b/runtime/interpreter/mterp/arm/op_sget_char.S
@@ -1 +1,2 @@
-%include "arm/op_sget.S" {"helper":"MterpSGetU16"}
+%def op_sget_char():
+%  op_sget(helper="MterpSGetU16")
diff --git a/runtime/interpreter/mterp/arm/op_sget_object.S b/runtime/interpreter/mterp/arm/op_sget_object.S
index e61a5a7b2137add30d4b34e2e6282db3ad56a1fd..7cf3597f44f59b999d828d0749f53401e98cfee6 100644
--- a/runtime/interpreter/mterp/arm/op_sget_object.S
+++ b/runtime/interpreter/mterp/arm/op_sget_object.S
@@ -1 +1,2 @@
-%include "arm/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"}
+%def op_sget_object():
+%  op_sget(is_object="1", helper="MterpSGetObj")
diff --git a/runtime/interpreter/mterp/arm/op_sget_short.S b/runtime/interpreter/mterp/arm/op_sget_short.S
index 49493ebc68b2718280703128b4fe9bff4b983f07..afacb578d90caf9455c969edfe13663d0927cb03 100644
--- a/runtime/interpreter/mterp/arm/op_sget_short.S
+++ b/runtime/interpreter/mterp/arm/op_sget_short.S
@@ -1 +1,2 @@
-%include "arm/op_sget.S" {"helper":"MterpSGetI16"}
+%def op_sget_short():
+%  op_sget(helper="MterpSGetI16")
diff --git a/runtime/interpreter/mterp/arm/op_sget_wide.S b/runtime/interpreter/mterp/arm/op_sget_wide.S
index d6905df7d8e238b288b0dcab87636554f2ed8501..fff2be6945510278d990141764285ab694e302ed 100644
--- a/runtime/interpreter/mterp/arm/op_sget_wide.S
+++ b/runtime/interpreter/mterp/arm/op_sget_wide.S
@@ -1 +1,2 @@
-%include "arm/op_sget.S" {"helper":"MterpSGetU64"}
+%def op_sget_wide():
+%  op_sget(helper="MterpSGetU64")
diff --git a/runtime/interpreter/mterp/arm/op_shl_int.S b/runtime/interpreter/mterp/arm/op_shl_int.S
index 7e4c768888c873627e51cb1fda5c500707e177bd..948a520e8e3a52bdfde2b972690664589b7ba0b4 100644
--- a/runtime/interpreter/mterp/arm/op_shl_int.S
+++ b/runtime/interpreter/mterp/arm/op_shl_int.S
@@ -1 +1,2 @@
-%include "arm/binop.S" {"preinstr":"and     r1, r1, #31", "instr":"mov     r0, r0, asl r1"}
+%def op_shl_int():
+%  binop(preinstr="and     r1, r1, #31", instr="mov     r0, r0, asl r1")
diff --git a/runtime/interpreter/mterp/arm/op_shl_int_2addr.S b/runtime/interpreter/mterp/arm/op_shl_int_2addr.S
index 4286577e19bccf35410b0ccd614d288e36a85893..89b16da2244ac528cc06180108e6b170543c10f9 100644
--- a/runtime/interpreter/mterp/arm/op_shl_int_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_shl_int_2addr.S
@@ -1 +1,2 @@
-%include "arm/binop2addr.S" {"preinstr":"and     r1, r1, #31", "instr":"mov     r0, r0, asl r1"}
+%def op_shl_int_2addr():
+%  binop2addr(preinstr="and     r1, r1, #31", instr="mov     r0, r0, asl r1")
diff --git a/runtime/interpreter/mterp/arm/op_shl_int_lit8.S b/runtime/interpreter/mterp/arm/op_shl_int_lit8.S
index 60a149880f13c2a4e693741c57fe90a79178a7e2..d6f81e779ac3ba0abaa52fc6f17190945826325b 100644
--- a/runtime/interpreter/mterp/arm/op_shl_int_lit8.S
+++ b/runtime/interpreter/mterp/arm/op_shl_int_lit8.S
@@ -1 +1,2 @@
-%include "arm/binopLit8.S" {"extract":"ubfx    r1, r3, #8, #5", "instr":"mov     r0, r0, asl r1"}
+%def op_shl_int_lit8():
+%  binopLit8(extract="ubfx    r1, r3, #8, #5", instr="mov     r0, r0, asl r1")
diff --git a/runtime/interpreter/mterp/arm/op_shl_long.S b/runtime/interpreter/mterp/arm/op_shl_long.S
index 82ec6ed09f628ba6212578b35afc524a6ea654f5..d11fee24f4a40c33a04f318234f5171981ea8394 100644
--- a/runtime/interpreter/mterp/arm/op_shl_long.S
+++ b/runtime/interpreter/mterp/arm/op_shl_long.S
@@ -1,3 +1,4 @@
+%def op_shl_long():
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
diff --git a/runtime/interpreter/mterp/arm/op_shl_long_2addr.S b/runtime/interpreter/mterp/arm/op_shl_long_2addr.S
index f361a7d29c3e000163559db9fe43f1f1deeb0553..e636d2e330ca1e983fb9cc0c9a1087db26602764 100644
--- a/runtime/interpreter/mterp/arm/op_shl_long_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_shl_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_shl_long_2addr():
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
diff --git a/runtime/interpreter/mterp/arm/op_shr_int.S b/runtime/interpreter/mterp/arm/op_shr_int.S
index 6317605c6d8e764618e8c78c94da925800d63185..4d94d1f55027b14cf146ee053145791be00ee620 100644
--- a/runtime/interpreter/mterp/arm/op_shr_int.S
+++ b/runtime/interpreter/mterp/arm/op_shr_int.S
@@ -1 +1,2 @@
-%include "arm/binop.S" {"preinstr":"and     r1, r1, #31", "instr":"mov     r0, r0, asr r1"}
+%def op_shr_int():
+%  binop(preinstr="and     r1, r1, #31", instr="mov     r0, r0, asr r1")
diff --git a/runtime/interpreter/mterp/arm/op_shr_int_2addr.S b/runtime/interpreter/mterp/arm/op_shr_int_2addr.S
index cc8632f4bd3fb0806a47802fba8bac4dcf2b3735..786b409921afc4571b9a61c9931bf2bac0dc3662 100644
--- a/runtime/interpreter/mterp/arm/op_shr_int_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_shr_int_2addr.S
@@ -1 +1,2 @@
-%include "arm/binop2addr.S" {"preinstr":"and     r1, r1, #31", "instr":"mov     r0, r0, asr r1"}
+%def op_shr_int_2addr():
+%  binop2addr(preinstr="and     r1, r1, #31", instr="mov     r0, r0, asr r1")
diff --git a/runtime/interpreter/mterp/arm/op_shr_int_lit8.S b/runtime/interpreter/mterp/arm/op_shr_int_lit8.S
index c2f6cb05032a11b4bc2864aa3363ccefc2b27fd4..f5550b1d4b5f8d9914aac1d64f809b892c6e3f12 100644
--- a/runtime/interpreter/mterp/arm/op_shr_int_lit8.S
+++ b/runtime/interpreter/mterp/arm/op_shr_int_lit8.S
@@ -1 +1,2 @@
-%include "arm/binopLit8.S" {"extract":"ubfx    r1, r3, #8, #5", "instr":"mov     r0, r0, asr r1"}
+%def op_shr_int_lit8():
+%  binopLit8(extract="ubfx    r1, r3, #8, #5", instr="mov     r0, r0, asr r1")
diff --git a/runtime/interpreter/mterp/arm/op_shr_long.S b/runtime/interpreter/mterp/arm/op_shr_long.S
index a0afe5b04047a1fec0eff8cef0182e64dd76d35b..eec8d32c8cf1045f002f462d9b0e22493e23d39a 100644
--- a/runtime/interpreter/mterp/arm/op_shr_long.S
+++ b/runtime/interpreter/mterp/arm/op_shr_long.S
@@ -1,3 +1,4 @@
+%def op_shr_long():
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
diff --git a/runtime/interpreter/mterp/arm/op_shr_long_2addr.S b/runtime/interpreter/mterp/arm/op_shr_long_2addr.S
index 976110efd4140bba28ba64e9041deb2c0da3f060..ac40d36327f4cb13428cb57af4fda9d1cac3f49e 100644
--- a/runtime/interpreter/mterp/arm/op_shr_long_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_shr_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_shr_long_2addr():
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
diff --git a/runtime/interpreter/mterp/arm/op_sparse_switch.S b/runtime/interpreter/mterp/arm/op_sparse_switch.S
index 9f7a42b96eb5449031e3ce51ff5b6e5d29c0869a..b74d7da81633f307dbf7c07ffaada2d14f131ec3 100644
--- a/runtime/interpreter/mterp/arm/op_sparse_switch.S
+++ b/runtime/interpreter/mterp/arm/op_sparse_switch.S
@@ -1 +1,2 @@
-%include "arm/op_packed_switch.S" { "func":"MterpDoSparseSwitch" }
+%def op_sparse_switch():
+%  op_packed_switch(func="MterpDoSparseSwitch")
diff --git a/runtime/interpreter/mterp/arm/op_sput.S b/runtime/interpreter/mterp/arm/op_sput.S
index 171f02444bcae60e5adce2c14f871eb3bc0b15d0..cbd6ee96d345758221edb4c7f71dd2dda57ac8f0 100644
--- a/runtime/interpreter/mterp/arm/op_sput.S
+++ b/runtime/interpreter/mterp/arm/op_sput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSPutU32"}
-%include "arm/field.S" { }
+%def op_sput(is_object="0", helper="MterpSPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/arm/op_sput_boolean.S b/runtime/interpreter/mterp/arm/op_sput_boolean.S
index 0c37623fb6e806a0e0464c13ca69592b5c5e6330..36fba8448b478323ce47a26f2a4d79accbf9964d 100644
--- a/runtime/interpreter/mterp/arm/op_sput_boolean.S
+++ b/runtime/interpreter/mterp/arm/op_sput_boolean.S
@@ -1 +1,2 @@
-%include "arm/op_sput.S" {"helper":"MterpSPutU8"}
+%def op_sput_boolean():
+%  op_sput(helper="MterpSPutU8")
diff --git a/runtime/interpreter/mterp/arm/op_sput_byte.S b/runtime/interpreter/mterp/arm/op_sput_byte.S
index 8d4e7542291b9262ff7c5d58426c6debc7d7092a..84ad4a0ff86ccfcd1159672dac902ee99cfc37d9 100644
--- a/runtime/interpreter/mterp/arm/op_sput_byte.S
+++ b/runtime/interpreter/mterp/arm/op_sput_byte.S
@@ -1 +1,2 @@
-%include "arm/op_sput.S" {"helper":"MterpSPutI8"}
+%def op_sput_byte():
+%  op_sput(helper="MterpSPutI8")
diff --git a/runtime/interpreter/mterp/arm/op_sput_char.S b/runtime/interpreter/mterp/arm/op_sput_char.S
index 442b56f7b1e28ed96730923c1ebf9535a0727ee1..9b8eeba578f555750ab9497c8fc21ce4a52e8b89 100644
--- a/runtime/interpreter/mterp/arm/op_sput_char.S
+++ b/runtime/interpreter/mterp/arm/op_sput_char.S
@@ -1 +1,2 @@
-%include "arm/op_sput.S" {"helper":"MterpSPutU16"}
+%def op_sput_char():
+%  op_sput(helper="MterpSPutU16")
diff --git a/runtime/interpreter/mterp/arm/op_sput_object.S b/runtime/interpreter/mterp/arm/op_sput_object.S
index 8fcd52e2c4ff5f268a433a42c87f7ead040924eb..081360c40fb12c03e3a48c24a3677ee55a609758 100644
--- a/runtime/interpreter/mterp/arm/op_sput_object.S
+++ b/runtime/interpreter/mterp/arm/op_sput_object.S
@@ -1 +1,2 @@
-%include "arm/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"}
+%def op_sput_object():
+%  op_sput(is_object="1", helper="MterpSPutObj")
diff --git a/runtime/interpreter/mterp/arm/op_sput_short.S b/runtime/interpreter/mterp/arm/op_sput_short.S
index 0eb533fe3c95ddff1955f29218056745e94503d8..ee16513486189f1a65fe9922285fe9ae08606b97 100644
--- a/runtime/interpreter/mterp/arm/op_sput_short.S
+++ b/runtime/interpreter/mterp/arm/op_sput_short.S
@@ -1 +1,2 @@
-%include "arm/op_sput.S" {"helper":"MterpSPutI16"}
+%def op_sput_short():
+%  op_sput(helper="MterpSPutI16")
diff --git a/runtime/interpreter/mterp/arm/op_sput_wide.S b/runtime/interpreter/mterp/arm/op_sput_wide.S
index c254f7834c85cb7f4862beeaa0c5ecd96b032634..44c1a188edf6bb3cf29011f1b361701ae71aaf9c 100644
--- a/runtime/interpreter/mterp/arm/op_sput_wide.S
+++ b/runtime/interpreter/mterp/arm/op_sput_wide.S
@@ -1 +1,2 @@
-%include "arm/op_sput.S" {"helper":"MterpSPutU64"}
+%def op_sput_wide():
+%  op_sput(helper="MterpSPutU64")
diff --git a/runtime/interpreter/mterp/arm/op_sub_double.S b/runtime/interpreter/mterp/arm/op_sub_double.S
index 69bcc6736cf5ff3144af7cbcebf670a2bc078059..418f93098a347d35f698304e2926777fea2899dd 100644
--- a/runtime/interpreter/mterp/arm/op_sub_double.S
+++ b/runtime/interpreter/mterp/arm/op_sub_double.S
@@ -1 +1,2 @@
-%include "arm/fbinopWide.S" {"instr":"fsubd   d2, d0, d1"}
+%def op_sub_double():
+%  fbinopWide(instr="fsubd   d2, d0, d1")
diff --git a/runtime/interpreter/mterp/arm/op_sub_double_2addr.S b/runtime/interpreter/mterp/arm/op_sub_double_2addr.S
index 2ea59fe854e075e20eb607a89b30cf8ea5dc25ce..2bd03703f5ace71f603402f9a03bd0e982b6de97 100644
--- a/runtime/interpreter/mterp/arm/op_sub_double_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_sub_double_2addr.S
@@ -1 +1,2 @@
-%include "arm/fbinopWide2addr.S" {"instr":"fsubd   d2, d0, d1"}
+%def op_sub_double_2addr():
+%  fbinopWide2addr(instr="fsubd   d2, d0, d1")
diff --git a/runtime/interpreter/mterp/arm/op_sub_float.S b/runtime/interpreter/mterp/arm/op_sub_float.S
index 3f17a0dfe372aae5e8ab910157f46ad8ad657dc4..c0b09ff0933612b18385b7d5167454f2fdece2fe 100644
--- a/runtime/interpreter/mterp/arm/op_sub_float.S
+++ b/runtime/interpreter/mterp/arm/op_sub_float.S
@@ -1 +1,2 @@
-%include "arm/fbinop.S" {"instr":"fsubs   s2, s0, s1"}
+%def op_sub_float():
+%  fbinop(instr="fsubs   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm/op_sub_float_2addr.S b/runtime/interpreter/mterp/arm/op_sub_float_2addr.S
index 2f4aac4ad87ac1c3b5ffe1b5f974938606b43e86..c5ffec7be4dd45734dc09788d02b4582a089051b 100644
--- a/runtime/interpreter/mterp/arm/op_sub_float_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_sub_float_2addr.S
@@ -1 +1,2 @@
-%include "arm/fbinop2addr.S" {"instr":"fsubs   s2, s0, s1"}
+%def op_sub_float_2addr():
+%  fbinop2addr(instr="fsubs   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm/op_sub_int.S b/runtime/interpreter/mterp/arm/op_sub_int.S
index efb9e10035c1b28d4109174b73b144180a204537..0932989efcd84f75dd01ae7eed4cde6ed389d41c 100644
--- a/runtime/interpreter/mterp/arm/op_sub_int.S
+++ b/runtime/interpreter/mterp/arm/op_sub_int.S
@@ -1 +1,2 @@
-%include "arm/binop.S" {"instr":"sub     r0, r0, r1"}
+%def op_sub_int():
+%  binop(instr="sub     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_sub_int_2addr.S b/runtime/interpreter/mterp/arm/op_sub_int_2addr.S
index 4d3036b82c2666f9f6763cc9eecf6fcfb634a766..c6fa2e46b3746d4503cad99ec0fd45e0239b4000 100644
--- a/runtime/interpreter/mterp/arm/op_sub_int_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_sub_int_2addr.S
@@ -1 +1,2 @@
-%include "arm/binop2addr.S" {"instr":"sub     r0, r0, r1"}
+%def op_sub_int_2addr():
+%  binop2addr(instr="sub     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_sub_long.S b/runtime/interpreter/mterp/arm/op_sub_long.S
index 6f1eb6ed77f981708d5289ae59f701a254602e25..85d9a9f52869d40d4bf9ea127900304e9dc53579 100644
--- a/runtime/interpreter/mterp/arm/op_sub_long.S
+++ b/runtime/interpreter/mterp/arm/op_sub_long.S
@@ -1 +1,2 @@
-%include "arm/binopWide.S" {"preinstr":"subs    r0, r0, r2", "instr":"sbc     r1, r1, r3"}
+%def op_sub_long():
+%  binopWide(preinstr="subs    r0, r0, r2", instr="sbc     r1, r1, r3")
diff --git a/runtime/interpreter/mterp/arm/op_sub_long_2addr.S b/runtime/interpreter/mterp/arm/op_sub_long_2addr.S
index 8e9da055257143905f0e5e25165588596cc7cc18..8a782aa5bfc7d61e8681ca4d82c30b6da487d645 100644
--- a/runtime/interpreter/mterp/arm/op_sub_long_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_sub_long_2addr.S
@@ -1 +1,2 @@
-%include "arm/binopWide2addr.S" {"preinstr":"subs    r0, r0, r2", "instr":"sbc     r1, r1, r3"}
+%def op_sub_long_2addr():
+%  binopWide2addr(preinstr="subs    r0, r0, r2", instr="sbc     r1, r1, r3")
diff --git a/runtime/interpreter/mterp/arm/op_throw.S b/runtime/interpreter/mterp/arm/op_throw.S
index be49ada424ae5377ad52cd8540e54931c4d4433d..0d3fe379342d62d2eb46b7a36c68c5f75730a579 100644
--- a/runtime/interpreter/mterp/arm/op_throw.S
+++ b/runtime/interpreter/mterp/arm/op_throw.S
@@ -1,3 +1,4 @@
+%def op_throw():
     /*
      * Throw an exception object in the current thread.
      */
diff --git a/runtime/interpreter/mterp/arm/op_unused_3e.S b/runtime/interpreter/mterp/arm/op_unused_3e.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..d889f1a5fb4be366ce5101882ae40577a9b0b90b 100644
--- a/runtime/interpreter/mterp/arm/op_unused_3e.S
+++ b/runtime/interpreter/mterp/arm/op_unused_3e.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_3e():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_3f.S b/runtime/interpreter/mterp/arm/op_unused_3f.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..b3ebcfaeaa402ba263610b3f305daf92cc23bebb 100644
--- a/runtime/interpreter/mterp/arm/op_unused_3f.S
+++ b/runtime/interpreter/mterp/arm/op_unused_3f.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_3f():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_40.S b/runtime/interpreter/mterp/arm/op_unused_40.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..7920fb350f2f93b310d33ec19166b6b8445bb0eb 100644
--- a/runtime/interpreter/mterp/arm/op_unused_40.S
+++ b/runtime/interpreter/mterp/arm/op_unused_40.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_40():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_41.S b/runtime/interpreter/mterp/arm/op_unused_41.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..5ed03b85065e78c670f3d26c62b6c56f58338d44 100644
--- a/runtime/interpreter/mterp/arm/op_unused_41.S
+++ b/runtime/interpreter/mterp/arm/op_unused_41.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_41():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_42.S b/runtime/interpreter/mterp/arm/op_unused_42.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..ac32521add543fb2f858aa858af6c3d5594f187e 100644
--- a/runtime/interpreter/mterp/arm/op_unused_42.S
+++ b/runtime/interpreter/mterp/arm/op_unused_42.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_42():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_43.S b/runtime/interpreter/mterp/arm/op_unused_43.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..33e2aa10f8bec8407ff8090cfd81dda49b2a19b8 100644
--- a/runtime/interpreter/mterp/arm/op_unused_43.S
+++ b/runtime/interpreter/mterp/arm/op_unused_43.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_43():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_73.S b/runtime/interpreter/mterp/arm/op_unused_73.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..e3267a30a120e465d19d0a578e37174df1bf8e21 100644
--- a/runtime/interpreter/mterp/arm/op_unused_73.S
+++ b/runtime/interpreter/mterp/arm/op_unused_73.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_73():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_79.S b/runtime/interpreter/mterp/arm/op_unused_79.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..3c6dafc7898855a1034ff93b17bed71a07df1e51 100644
--- a/runtime/interpreter/mterp/arm/op_unused_79.S
+++ b/runtime/interpreter/mterp/arm/op_unused_79.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_79():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_7a.S b/runtime/interpreter/mterp/arm/op_unused_7a.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..9c03cd55355a41369dc85dbea7e07e7bd8e96383 100644
--- a/runtime/interpreter/mterp/arm/op_unused_7a.S
+++ b/runtime/interpreter/mterp/arm/op_unused_7a.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_7a():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_f3.S b/runtime/interpreter/mterp/arm/op_unused_f3.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..ab10b78be2a0b681652d52185cf7c39d3403a41e 100644
--- a/runtime/interpreter/mterp/arm/op_unused_f3.S
+++ b/runtime/interpreter/mterp/arm/op_unused_f3.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_f3():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_f4.S b/runtime/interpreter/mterp/arm/op_unused_f4.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..09229d6d99f58a24b923c56b2937662a10e16de6 100644
--- a/runtime/interpreter/mterp/arm/op_unused_f4.S
+++ b/runtime/interpreter/mterp/arm/op_unused_f4.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_f4():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_f5.S b/runtime/interpreter/mterp/arm/op_unused_f5.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..0d6149b5fd6eeb0221067adb660d453080ba1fd2 100644
--- a/runtime/interpreter/mterp/arm/op_unused_f5.S
+++ b/runtime/interpreter/mterp/arm/op_unused_f5.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_f5():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_f6.S b/runtime/interpreter/mterp/arm/op_unused_f6.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..117b03de6d321ace7f917fe69b79b9f182081e11 100644
--- a/runtime/interpreter/mterp/arm/op_unused_f6.S
+++ b/runtime/interpreter/mterp/arm/op_unused_f6.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_f6():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_f7.S b/runtime/interpreter/mterp/arm/op_unused_f7.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..4e3a0f3c9a6eef078506555805a72056272abfc1 100644
--- a/runtime/interpreter/mterp/arm/op_unused_f7.S
+++ b/runtime/interpreter/mterp/arm/op_unused_f7.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_f7():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_f8.S b/runtime/interpreter/mterp/arm/op_unused_f8.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..d1220752d7b5b191c0712bf975e90ac7777e4303 100644
--- a/runtime/interpreter/mterp/arm/op_unused_f8.S
+++ b/runtime/interpreter/mterp/arm/op_unused_f8.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_f8():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_f9.S b/runtime/interpreter/mterp/arm/op_unused_f9.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..7d09a0ebcfce77f4a1bd8b19865ac5d782e382dd 100644
--- a/runtime/interpreter/mterp/arm/op_unused_f9.S
+++ b/runtime/interpreter/mterp/arm/op_unused_f9.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_f9():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_fc.S b/runtime/interpreter/mterp/arm/op_unused_fc.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..06978191ebbcceb51b9820b3e650a0baf767a507 100644
--- a/runtime/interpreter/mterp/arm/op_unused_fc.S
+++ b/runtime/interpreter/mterp/arm/op_unused_fc.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_fc():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_unused_fd.S b/runtime/interpreter/mterp/arm/op_unused_fd.S
index 10948dc06c75b94fe3313bfcd1fe63766427b719..4bc2b4bdb6516467406cb88476e1d993a3f0c749 100644
--- a/runtime/interpreter/mterp/arm/op_unused_fd.S
+++ b/runtime/interpreter/mterp/arm/op_unused_fd.S
@@ -1 +1,2 @@
-%include "arm/unused.S"
+%def op_unused_fd():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm/op_ushr_int.S b/runtime/interpreter/mterp/arm/op_ushr_int.S
index a74361b64c91d53e67e16dc5bc76e3a4131af4f1..7716bebcbb91c4c08b51c0fefb9ce7b11d306e5b 100644
--- a/runtime/interpreter/mterp/arm/op_ushr_int.S
+++ b/runtime/interpreter/mterp/arm/op_ushr_int.S
@@ -1 +1,2 @@
-%include "arm/binop.S" {"preinstr":"and     r1, r1, #31", "instr":"mov     r0, r0, lsr r1"}
+%def op_ushr_int():
+%  binop(preinstr="and     r1, r1, #31", instr="mov     r0, r0, lsr r1")
diff --git a/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S b/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S
index f2d1d13881533d9b447ceed56ca2bd1476a05209..8e435a738ca2732e0590390a783f6ef11cfd983d 100644
--- a/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S
@@ -1 +1,2 @@
-%include "arm/binop2addr.S" {"preinstr":"and     r1, r1, #31", "instr":"mov     r0, r0, lsr r1"}
+%def op_ushr_int_2addr():
+%  binop2addr(preinstr="and     r1, r1, #31", instr="mov     r0, r0, lsr r1")
diff --git a/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S b/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S
index 5554eb06f72cf56f274dc9c612efade7124fa4df..40783de326808b9c51460a54f3a19dd2b2a01c66 100644
--- a/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S
+++ b/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S
@@ -1 +1,2 @@
-%include "arm/binopLit8.S" {"extract":"ubfx    r1, r3, #8, #5", "instr":"mov     r0, r0, lsr r1"}
+%def op_ushr_int_lit8():
+%  binopLit8(extract="ubfx    r1, r3, #8, #5", instr="mov     r0, r0, lsr r1")
diff --git a/runtime/interpreter/mterp/arm/op_ushr_long.S b/runtime/interpreter/mterp/arm/op_ushr_long.S
index c817bc9fb958f9e27f60656980e7d2b16a971773..2ab31ff216ec5b700bba8e99e7fed6a2fbf0591a 100644
--- a/runtime/interpreter/mterp/arm/op_ushr_long.S
+++ b/runtime/interpreter/mterp/arm/op_ushr_long.S
@@ -1,3 +1,4 @@
+%def op_ushr_long():
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
diff --git a/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S b/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S
index 2735f8733aafba2f3b9aba192e28c655ffb4eade..e86161b0f571d0c87bced8605baaf13442a6b309 100644
--- a/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_ushr_long_2addr():
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
diff --git a/runtime/interpreter/mterp/arm/op_xor_int.S b/runtime/interpreter/mterp/arm/op_xor_int.S
index fd7a4b7a025665530f7c99f14eeb0634f04b40c9..89a6450b0156fca4b709bec1a887d4f8c0d3fc3f 100644
--- a/runtime/interpreter/mterp/arm/op_xor_int.S
+++ b/runtime/interpreter/mterp/arm/op_xor_int.S
@@ -1 +1,2 @@
-%include "arm/binop.S" {"instr":"eor     r0, r0, r1"}
+%def op_xor_int():
+%  binop(instr="eor     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_xor_int_2addr.S b/runtime/interpreter/mterp/arm/op_xor_int_2addr.S
index 196a6657245c6d30c8db5d93c96c824f26011b36..af7e85ede6c8f8c0230be80097b2321c74e2c738 100644
--- a/runtime/interpreter/mterp/arm/op_xor_int_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_xor_int_2addr.S
@@ -1 +1,2 @@
-%include "arm/binop2addr.S" {"instr":"eor     r0, r0, r1"}
+%def op_xor_int_2addr():
+%  binop2addr(instr="eor     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_xor_int_lit16.S b/runtime/interpreter/mterp/arm/op_xor_int_lit16.S
index 39f2a47bfac016b0099d9d98b50283d50374988a..a970e01357aebcf4758323eb70e559150b2b49a4 100644
--- a/runtime/interpreter/mterp/arm/op_xor_int_lit16.S
+++ b/runtime/interpreter/mterp/arm/op_xor_int_lit16.S
@@ -1 +1,2 @@
-%include "arm/binopLit16.S" {"instr":"eor     r0, r0, r1"}
+%def op_xor_int_lit16():
+%  binopLit16(instr="eor     r0, r0, r1")
diff --git a/runtime/interpreter/mterp/arm/op_xor_int_lit8.S b/runtime/interpreter/mterp/arm/op_xor_int_lit8.S
index 97d0b9ee14a99c0582473bbe2bfd5902dd17a26f..2241f3176bbecd149670226e66731d3afe0a9566 100644
--- a/runtime/interpreter/mterp/arm/op_xor_int_lit8.S
+++ b/runtime/interpreter/mterp/arm/op_xor_int_lit8.S
@@ -1 +1,2 @@
-%include "arm/binopLit8.S" {"extract":"", "instr":"eor     r0, r0, r3, asr #8"}
+%def op_xor_int_lit8():
+%  binopLit8(extract="", instr="eor     r0, r0, r3, asr #8")
diff --git a/runtime/interpreter/mterp/arm/op_xor_long.S b/runtime/interpreter/mterp/arm/op_xor_long.S
index 4f830d01be6bd8ae090021927b649a405856e27f..3700a4a30885146e780910b71c19b06ad07c1c12 100644
--- a/runtime/interpreter/mterp/arm/op_xor_long.S
+++ b/runtime/interpreter/mterp/arm/op_xor_long.S
@@ -1 +1,2 @@
-%include "arm/binopWide.S" {"preinstr":"eor     r0, r0, r2", "instr":"eor     r1, r1, r3"}
+%def op_xor_long():
+%  binopWide(preinstr="eor     r0, r0, r2", instr="eor     r1, r1, r3")
diff --git a/runtime/interpreter/mterp/arm/op_xor_long_2addr.S b/runtime/interpreter/mterp/arm/op_xor_long_2addr.S
index 5b5ed88059b444a04e266f87d31edea2d8817c98..6558a4eb394dfacccfeb0bcfe4b711b1f8af4931 100644
--- a/runtime/interpreter/mterp/arm/op_xor_long_2addr.S
+++ b/runtime/interpreter/mterp/arm/op_xor_long_2addr.S
@@ -1 +1,2 @@
-%include "arm/binopWide2addr.S" {"preinstr":"eor     r0, r0, r2", "instr":"eor     r1, r1, r3"}
+%def op_xor_long_2addr():
+%  binopWide2addr(preinstr="eor     r0, r0, r2", instr="eor     r1, r1, r3")
diff --git a/runtime/interpreter/mterp/arm/unop.S b/runtime/interpreter/mterp/arm/unop.S
index 56518b5b2b95b0dcfaf9ea5334e29c1dedf93767..a0b095411e73c2a0e2cd815a387b92ee13734c89 100644
--- a/runtime/interpreter/mterp/arm/unop.S
+++ b/runtime/interpreter/mterp/arm/unop.S
@@ -1,4 +1,4 @@
-%default {"preinstr":""}
+%def unop(preinstr="", instr=""):
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0".
diff --git a/runtime/interpreter/mterp/arm/unopNarrower.S b/runtime/interpreter/mterp/arm/unopNarrower.S
index 2d0453aeb1a991d78773bb1b1b30303cb976a2fc..4d1bdb90a6d66f3769779c6883ff23e8f7599189 100644
--- a/runtime/interpreter/mterp/arm/unopNarrower.S
+++ b/runtime/interpreter/mterp/arm/unopNarrower.S
@@ -1,4 +1,4 @@
-%default {"preinstr":""}
+%def unopNarrower(preinstr="", instr=""):
     /*
      * Generic 64bit-to-32bit unary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = op r0/r1", where
diff --git a/runtime/interpreter/mterp/arm/unopWide.S b/runtime/interpreter/mterp/arm/unopWide.S
index cd5defd616dbc05d333edddb3289d8c469a2cc56..658c2073d9743b777d411789dbc237e2047e1f5a 100644
--- a/runtime/interpreter/mterp/arm/unopWide.S
+++ b/runtime/interpreter/mterp/arm/unopWide.S
@@ -1,4 +1,4 @@
-%default {"preinstr":""}
+%def unopWide(preinstr="", instr=""):
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0/r1".
diff --git a/runtime/interpreter/mterp/arm/unopWider.S b/runtime/interpreter/mterp/arm/unopWider.S
index 9d504899b838138ef06101beedf2f7152a229758..8b3292719de59ca944926b2d39f2065bf98097df 100644
--- a/runtime/interpreter/mterp/arm/unopWider.S
+++ b/runtime/interpreter/mterp/arm/unopWider.S
@@ -1,4 +1,4 @@
-%default {"preinstr":""}
+%def unopWider(preinstr="", instr=""):
     /*
      * Generic 32bit-to-64bit unary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = op r0", where
diff --git a/runtime/interpreter/mterp/arm/unused.S b/runtime/interpreter/mterp/arm/unused.S
index ffa00becfdb2bb4ba58ee7659a0609978599110e..3f37e74bb4752ad0c5af7cc91b0202f5f00429cd 100644
--- a/runtime/interpreter/mterp/arm/unused.S
+++ b/runtime/interpreter/mterp/arm/unused.S
@@ -1,3 +1,4 @@
+%def unused():
 /*
  * Bail to reference interpreter to throw.
  */
diff --git a/runtime/interpreter/mterp/arm/zcmp.S b/runtime/interpreter/mterp/arm/zcmp.S
index 5db8b6cdd7f42d0584038562d74b1cb74ad53b1f..6905a3249970a00c660262896f1c84603e6f8716 100644
--- a/runtime/interpreter/mterp/arm/zcmp.S
+++ b/runtime/interpreter/mterp/arm/zcmp.S
@@ -1,3 +1,4 @@
+%def zcmp(condition=""):
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
diff --git a/runtime/interpreter/mterp/arm64/alt_stub.S b/runtime/interpreter/mterp/arm64/alt_stub.S
index 3a463feb415c7898894f6a7ffa40a0c59bd75d1f..33434633cf17dd71c442554324b55df69494be7c 100644
--- a/runtime/interpreter/mterp/arm64/alt_stub.S
+++ b/runtime/interpreter/mterp/arm64/alt_stub.S
@@ -1,3 +1,4 @@
+%def alt_stub():
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
diff --git a/runtime/interpreter/mterp/arm64/bincmp.S b/runtime/interpreter/mterp/arm64/bincmp.S
index 8dd4fed7ca38ac7cedf4a9ea4344dc64311d6398..80ffbc5f3ba357b98466b9023929b6d67ece2864 100644
--- a/runtime/interpreter/mterp/arm64/bincmp.S
+++ b/runtime/interpreter/mterp/arm64/bincmp.S
@@ -1,3 +1,4 @@
+%def bincmp(condition=""):
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
diff --git a/runtime/interpreter/mterp/arm64/binop.S b/runtime/interpreter/mterp/arm64/binop.S
index b629b0b37e9342e10d4d473bbf8d2a5744b14839..be4db175158c1b7984803ac47ecd0ba68bcf453f 100644
--- a/runtime/interpreter/mterp/arm64/binop.S
+++ b/runtime/interpreter/mterp/arm64/binop.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"w0", "chkzero":"0"}
+%def binop(preinstr="", result="w0", chkzero="0", instr=""):
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
diff --git a/runtime/interpreter/mterp/arm64/binop2addr.S b/runtime/interpreter/mterp/arm64/binop2addr.S
index a480a7d55134717d5c6e98c5c0ba2fcde8e1892e..5b46b1215782ed230f9a8a2e2abb3caffcb294a2 100644
--- a/runtime/interpreter/mterp/arm64/binop2addr.S
+++ b/runtime/interpreter/mterp/arm64/binop2addr.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"w0", "chkzero":"0"}
+%def binop2addr(preinstr="", result="w0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
diff --git a/runtime/interpreter/mterp/arm64/binopLit16.S b/runtime/interpreter/mterp/arm64/binopLit16.S
index 4f9d205b38a84fc44dd31f90009e77c14fbb5a14..b8af7d18fc347af0dba1ec245331dd8156b1a093 100644
--- a/runtime/interpreter/mterp/arm64/binopLit16.S
+++ b/runtime/interpreter/mterp/arm64/binopLit16.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"w0", "chkzero":"0"}
+%def binopLit16(preinstr="", result="w0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
diff --git a/runtime/interpreter/mterp/arm64/binopLit8.S b/runtime/interpreter/mterp/arm64/binopLit8.S
index dfa316990523753e61aedf868313147694615fbc..e7161a7d4ba2959e38f87946ac74ab7a86c65711 100644
--- a/runtime/interpreter/mterp/arm64/binopLit8.S
+++ b/runtime/interpreter/mterp/arm64/binopLit8.S
@@ -1,4 +1,4 @@
-%default {"extract": "asr     w1, w3, #8", "preinstr":"", "result":"w0", "chkzero":"0"}
+%def binopLit8(extract="asr     w1, w3, #8", preinstr="", result="w0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
diff --git a/runtime/interpreter/mterp/arm64/binopWide.S b/runtime/interpreter/mterp/arm64/binopWide.S
index 9de24f1c229e4c856806e125b8f47ec591acc47a..829b53067ff12a478dffadd53b2cc87cbab617e1 100644
--- a/runtime/interpreter/mterp/arm64/binopWide.S
+++ b/runtime/interpreter/mterp/arm64/binopWide.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "instr":"add x0, x1, x2", "result":"x0", "r1":"x1", "r2":"x2", "chkzero":"0"}
+%def binopWide(preinstr="", instr="add x0, x1, x2", result="x0", r1="x1", r2="x2", chkzero="0"):
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
diff --git a/runtime/interpreter/mterp/arm64/binopWide2addr.S b/runtime/interpreter/mterp/arm64/binopWide2addr.S
index d9927a2ca88fa64d4a7ce345a530359800475726..dbd6b3b85339fcf18a808611e125ea9741dd149d 100644
--- a/runtime/interpreter/mterp/arm64/binopWide2addr.S
+++ b/runtime/interpreter/mterp/arm64/binopWide2addr.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "instr":"add x0, x0, x1", "r0":"x0", "r1":"x1", "chkzero":"0"}
+%def binopWide2addr(preinstr="", instr="add x0, x0, x1", r0="x0", r1="x1", chkzero="0"):
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
diff --git a/runtime/interpreter/mterp/arm64/close_cfi.S b/runtime/interpreter/mterp/arm64/close_cfi.S
index 7ba0486079e56f3778b6daeec65f14b91b5767a2..8f651b18f0af4373fc81fa18eefade715a0590b5 100644
--- a/runtime/interpreter/mterp/arm64/close_cfi.S
+++ b/runtime/interpreter/mterp/arm64/close_cfi.S
@@ -1,3 +1,4 @@
+%def close_cfi():
 // Close out the cfi info.  We're treating mterp as a single function.
 
 END ExecuteMterpImpl
diff --git a/runtime/interpreter/mterp/arm64/const.S b/runtime/interpreter/mterp/arm64/const.S
index 6f82bbf0ba113d6ca49c3f7dcb63448cc88f91ae..f8477a8b12e1be8d491699bd2e34e96c197b442b 100644
--- a/runtime/interpreter/mterp/arm64/const.S
+++ b/runtime/interpreter/mterp/arm64/const.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedConstHandler" }
+%def const(helper="UndefinedConstHandler"):
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
diff --git a/runtime/interpreter/mterp/arm64/entry.S b/runtime/interpreter/mterp/arm64/entry.S
index cf38a2992d5c5554d5fb4560693090ebf2ed4161..baf8afce6ec9dd37ea84e8c8be58eef5ecb9039e 100644
--- a/runtime/interpreter/mterp/arm64/entry.S
+++ b/runtime/interpreter/mterp/arm64/entry.S
@@ -1,3 +1,4 @@
+%def entry():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
diff --git a/runtime/interpreter/mterp/arm64/fallback.S b/runtime/interpreter/mterp/arm64/fallback.S
index 44e7e1220d841247a99eb6ff9ae11f11f0a1ea8e..3685700dec0c663d42de39d9698f2f39a64da74a 100644
--- a/runtime/interpreter/mterp/arm64/fallback.S
+++ b/runtime/interpreter/mterp/arm64/fallback.S
@@ -1,3 +1,4 @@
+%def fallback():
 /* Transfer stub to alternate interpreter */
     b    MterpFallback
 
diff --git a/runtime/interpreter/mterp/arm64/fbinop.S b/runtime/interpreter/mterp/arm64/fbinop.S
index 926d0783dad22421833383a35b8646cdf2774765..e3fb25a8da38b939b2b7a27325c31c70fa48196c 100644
--- a/runtime/interpreter/mterp/arm64/fbinop.S
+++ b/runtime/interpreter/mterp/arm64/fbinop.S
@@ -1,4 +1,4 @@
-%default {}
+%def fbinop(instr=""):
     /*:
      * Generic 32-bit floating-point operation.
      *
diff --git a/runtime/interpreter/mterp/arm64/fbinop2addr.S b/runtime/interpreter/mterp/arm64/fbinop2addr.S
index 04236adb812dc7e3cbe3548dabb810d3ffb7e013..9f235d94b617ec7ecb4577d009934f444de3c349 100644
--- a/runtime/interpreter/mterp/arm64/fbinop2addr.S
+++ b/runtime/interpreter/mterp/arm64/fbinop2addr.S
@@ -1,3 +1,4 @@
+%def fbinop2addr(instr=""):
     /*
      * Generic 32-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
diff --git a/runtime/interpreter/mterp/arm64/fcmp.S b/runtime/interpreter/mterp/arm64/fcmp.S
index cad63189af3c93e261618dd14257990b89eab532..c0cc33afcdf157916f864a2839972bf68dba4564 100644
--- a/runtime/interpreter/mterp/arm64/fcmp.S
+++ b/runtime/interpreter/mterp/arm64/fcmp.S
@@ -1,4 +1,4 @@
-%default {"wide":"", "r1":"s1", "r2":"s2", "cond":"lt"}
+%def fcmp(wide="", r1="s1", r2="s2", cond="lt"):
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/arm64/field.S b/runtime/interpreter/mterp/arm64/field.S
index 631c8d191bb0a4d7c9f03e6546b656968b058110..8a6699272438408e7dfffa3ad923e48b3bea6d32 100644
--- a/runtime/interpreter/mterp/arm64/field.S
+++ b/runtime/interpreter/mterp/arm64/field.S
@@ -1,4 +1,4 @@
-%default { }
+%def field(helper=""):
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
diff --git a/runtime/interpreter/mterp/arm64/footer.S b/runtime/interpreter/mterp/arm64/footer.S
index 0ce35439116b9f46daebafda83338c9fb4736f53..ba17f5e8975a245c33b902d83c6eafd281093077 100644
--- a/runtime/interpreter/mterp/arm64/footer.S
+++ b/runtime/interpreter/mterp/arm64/footer.S
@@ -1,10 +1,10 @@
+%def footer():
 /*
  * ===========================================================================
  *  Common subroutines and data
  * ===========================================================================
  */
 
-
 /*
  * We've detected a condition that will result in an exception, but the exception
  * has not yet been thrown.  Just bail out to the reference interpreter to deal with it.
@@ -207,7 +207,6 @@ MterpCommonTakenBranchNoFlags:
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /*
  * Check for suspend check request.  Assumes wINST already loaded, xPC advanced and
  * still needs to get the opcode and branch to it, and flags are in lr.
diff --git a/runtime/interpreter/mterp/arm64/funopNarrow.S b/runtime/interpreter/mterp/arm64/funopNarrow.S
index aed830bc23b0d5294c5d234249a8dfaa79be5596..f08e87fb3c6cb304d417cb744b544d5912de18d6 100644
--- a/runtime/interpreter/mterp/arm64/funopNarrow.S
+++ b/runtime/interpreter/mterp/arm64/funopNarrow.S
@@ -1,4 +1,4 @@
-%default {"srcreg":"s0", "tgtreg":"d0"}
+%def funopNarrow(srcreg="s0", tgtreg="d0", instr=""):
     /*
      * Generic 32bit-to-32bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg".
diff --git a/runtime/interpreter/mterp/arm64/funopNarrower.S b/runtime/interpreter/mterp/arm64/funopNarrower.S
index 6fddfea979f357b311f8e2e2c818f5c7c35dbb72..e1a1214f113bb75252b46bea9a43b07fe0aafd09 100644
--- a/runtime/interpreter/mterp/arm64/funopNarrower.S
+++ b/runtime/interpreter/mterp/arm64/funopNarrower.S
@@ -1,4 +1,4 @@
-%default {"srcreg":"s0", "tgtreg":"d0"}
+%def funopNarrower(srcreg="s0", tgtreg="d0", instr=""):
     /*
      * Generic 64bit-to-32bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg".
diff --git a/runtime/interpreter/mterp/arm64/funopWide.S b/runtime/interpreter/mterp/arm64/funopWide.S
index 409e26b6ecc42af2c45f4a0044324c6683d01080..83e55be206fbccfff5036a35ebac39b26bb86091 100644
--- a/runtime/interpreter/mterp/arm64/funopWide.S
+++ b/runtime/interpreter/mterp/arm64/funopWide.S
@@ -1,4 +1,4 @@
-%default {"srcreg":"s0", "tgtreg":"d0"}
+%def funopWide(srcreg="s0", tgtreg="d0", instr=""):
     /*
      * Generic 64bit-to-64bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg".
diff --git a/runtime/interpreter/mterp/arm64/funopWider.S b/runtime/interpreter/mterp/arm64/funopWider.S
index 4c91ebcdc64254487c7f475bc66f9c04f1094003..825698ebf7f88fb624811bbc3af8e9e0bdb666a1 100644
--- a/runtime/interpreter/mterp/arm64/funopWider.S
+++ b/runtime/interpreter/mterp/arm64/funopWider.S
@@ -1,4 +1,4 @@
-%default {"srcreg":"s0", "tgtreg":"d0"}
+%def funopWider(srcreg="s0", tgtreg="d0", instr=""):
     /*
      * Generic 32bit-to-64bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg".
diff --git a/runtime/interpreter/mterp/arm64/header.S b/runtime/interpreter/mterp/arm64/header.S
index 072280426560a32c22ca415b4f237f49c23a7332..41029729ca779078d1cf948a3d84fc0767455c60 100644
--- a/runtime/interpreter/mterp/arm64/header.S
+++ b/runtime/interpreter/mterp/arm64/header.S
@@ -1,3 +1,4 @@
+%def header():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
diff --git a/runtime/interpreter/mterp/arm64/instruction_end.S b/runtime/interpreter/mterp/arm64/instruction_end.S
index f90ebd0221f7ff35964753368888c2576917d112..cf30a9b0b02cd7351dbe58eeba0f8624894bf6b9 100644
--- a/runtime/interpreter/mterp/arm64/instruction_end.S
+++ b/runtime/interpreter/mterp/arm64/instruction_end.S
@@ -1,3 +1,4 @@
+%def instruction_end():
 
     .type artMterpAsmInstructionEnd, #object
     .hidden artMterpAsmInstructionEnd
diff --git a/runtime/interpreter/mterp/arm64/instruction_end_alt.S b/runtime/interpreter/mterp/arm64/instruction_end_alt.S
index 0b66dbb9479dd5600b5b69aeeb3ed91bcaa09e1f..9509a63b6a470a388306b2e9fe65994b9981652b 100644
--- a/runtime/interpreter/mterp/arm64/instruction_end_alt.S
+++ b/runtime/interpreter/mterp/arm64/instruction_end_alt.S
@@ -1,3 +1,4 @@
+%def instruction_end_alt():
 
     .type artMterpAsmAltInstructionEnd, #object
     .hidden artMterpAsmAltInstructionEnd
diff --git a/runtime/interpreter/mterp/arm64/instruction_end_sister.S b/runtime/interpreter/mterp/arm64/instruction_end_sister.S
index 71c0300f6d5a139f623fd1397be73b7a6cc01c34..18f1dbb38da8c191f28f7528a250744cd0f04b99 100644
--- a/runtime/interpreter/mterp/arm64/instruction_end_sister.S
+++ b/runtime/interpreter/mterp/arm64/instruction_end_sister.S
@@ -1,3 +1,4 @@
+%def instruction_end_sister():
 
     .type artMterpAsmSisterEnd, #object
     .hidden artMterpAsmSisterEnd
diff --git a/runtime/interpreter/mterp/arm64/instruction_start.S b/runtime/interpreter/mterp/arm64/instruction_start.S
index b7e9cf51e4ff0498942076b0a4de9d13c228a933..457dcf9617dca3684116418fdc0839a3451d8c24 100644
--- a/runtime/interpreter/mterp/arm64/instruction_start.S
+++ b/runtime/interpreter/mterp/arm64/instruction_start.S
@@ -1,3 +1,4 @@
+%def instruction_start():
 
     .type artMterpAsmInstructionStart, #object
     .hidden artMterpAsmInstructionStart
diff --git a/runtime/interpreter/mterp/arm64/instruction_start_alt.S b/runtime/interpreter/mterp/arm64/instruction_start_alt.S
index 7a67ba064c3171e55aad5cabf1458c58c184c5ff..40d2bf5dbe4d6395109ed366bc80dadafcdfc6b3 100644
--- a/runtime/interpreter/mterp/arm64/instruction_start_alt.S
+++ b/runtime/interpreter/mterp/arm64/instruction_start_alt.S
@@ -1,3 +1,4 @@
+%def instruction_start_alt():
 
     .type artMterpAsmAltInstructionStart, #object
     .hidden artMterpAsmAltInstructionStart
diff --git a/runtime/interpreter/mterp/arm64/instruction_start_sister.S b/runtime/interpreter/mterp/arm64/instruction_start_sister.S
index 00360616053f769913e829e97a698931958f6b9a..2bf24636eae105e4c918e7736d2954ff12d81ba5 100644
--- a/runtime/interpreter/mterp/arm64/instruction_start_sister.S
+++ b/runtime/interpreter/mterp/arm64/instruction_start_sister.S
@@ -1,3 +1,4 @@
+%def instruction_start_sister():
 
     .type artMterpAsmSisterStart, #object
     .hidden artMterpAsmSisterStart
diff --git a/runtime/interpreter/mterp/arm64/invoke.S b/runtime/interpreter/mterp/arm64/invoke.S
index 7a32df7bcafe44ceb70e2d48e1accad45efd6143..9e5b5b725a979e929a7b6af6ff70ee2a8c16082b 100644
--- a/runtime/interpreter/mterp/arm64/invoke.S
+++ b/runtime/interpreter/mterp/arm64/invoke.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke(helper="UndefinedInvokeHandler"):
     /*
      * Generic invoke handler wrapper.
      */
diff --git a/runtime/interpreter/mterp/arm64/invoke_polymorphic.S b/runtime/interpreter/mterp/arm64/invoke_polymorphic.S
index 7906f0ada047ace8a0627b44dca534fe4652b2c5..08ffb9cae79da997ae5717acf2ea1c1db29b0372 100644
--- a/runtime/interpreter/mterp/arm64/invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/arm64/invoke_polymorphic.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke_polymorphic(helper="UndefinedInvokeHandler"):
     /*
      * invoke-polymorphic handler wrapper.
      */
diff --git a/runtime/interpreter/mterp/arm64/op_add_double.S b/runtime/interpreter/mterp/arm64/op_add_double.S
index 8509f70309a0052ddeda5ca318f87fb9cd15fd46..8d31342b38305c5bdda92cf5fbcdb8bf8002b1c2 100644
--- a/runtime/interpreter/mterp/arm64/op_add_double.S
+++ b/runtime/interpreter/mterp/arm64/op_add_double.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"instr":"fadd d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"}
+%def op_add_double():
+%  binopWide(instr="fadd d0, d1, d2", result="d0", r1="d1", r2="d2")
diff --git a/runtime/interpreter/mterp/arm64/op_add_double_2addr.S b/runtime/interpreter/mterp/arm64/op_add_double_2addr.S
index 61fd58f4b65c89294375b2d112c46301cb9cfc45..88c1d5e0bd04da736f5a4de13273ed2e0c956978 100644
--- a/runtime/interpreter/mterp/arm64/op_add_double_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_add_double_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"instr":"fadd     d0, d0, d1", "r0":"d0", "r1":"d1"}
+%def op_add_double_2addr():
+%  binopWide2addr(instr="fadd     d0, d0, d1", r0="d0", r1="d1")
diff --git a/runtime/interpreter/mterp/arm64/op_add_float.S b/runtime/interpreter/mterp/arm64/op_add_float.S
index 7d09fef10ad7cd752b1990fa9fae4c3b25f82726..388732e34eb17047763b43f2a698a1264a6213b0 100644
--- a/runtime/interpreter/mterp/arm64/op_add_float.S
+++ b/runtime/interpreter/mterp/arm64/op_add_float.S
@@ -1 +1,2 @@
-%include "arm64/fbinop.S" {"instr":"fadd   s0, s0, s1"}
+%def op_add_float():
+%  fbinop(instr="fadd   s0, s0, s1")
diff --git a/runtime/interpreter/mterp/arm64/op_add_float_2addr.S b/runtime/interpreter/mterp/arm64/op_add_float_2addr.S
index 7b378e2889e6145782f0994b13ba3b4357a5c63e..061c9d52ae2bf382a2e7e1fd9016902a3c08f764 100644
--- a/runtime/interpreter/mterp/arm64/op_add_float_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_add_float_2addr.S
@@ -1 +1,2 @@
-%include "arm64/fbinop2addr.S" {"instr":"fadd   s2, s0, s1"}
+%def op_add_float_2addr():
+%  fbinop2addr(instr="fadd   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm64/op_add_int.S b/runtime/interpreter/mterp/arm64/op_add_int.S
index 6eadb5441d2fb50462b3ddbcc0ad9a1d22c95c8e..99953ee83759d983a8e523bc1273f89dd4980a8c 100644
--- a/runtime/interpreter/mterp/arm64/op_add_int.S
+++ b/runtime/interpreter/mterp/arm64/op_add_int.S
@@ -1 +1,2 @@
-%include "arm64/binop.S" {"instr":"add     w0, w0, w1"}
+%def op_add_int():
+%  binop(instr="add     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_add_int_2addr.S b/runtime/interpreter/mterp/arm64/op_add_int_2addr.S
index d35bc8ecc91c9eaed1f165b04808734c1a167883..d61fcce27d7c8a49366769702c94b1c025893feb 100644
--- a/runtime/interpreter/mterp/arm64/op_add_int_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_add_int_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binop2addr.S" {"instr":"add     w0, w0, w1"}
+%def op_add_int_2addr():
+%  binop2addr(instr="add     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_add_int_lit16.S b/runtime/interpreter/mterp/arm64/op_add_int_lit16.S
index 4930ad77162e7d8b6f7f7beb43b119c71e63dd0b..37bf2e8621387710bb3545e05b1bb1be5a5ba64f 100644
--- a/runtime/interpreter/mterp/arm64/op_add_int_lit16.S
+++ b/runtime/interpreter/mterp/arm64/op_add_int_lit16.S
@@ -1 +1,2 @@
-%include "arm64/binopLit16.S" {"instr":"add     w0, w0, w1"}
+%def op_add_int_lit16():
+%  binopLit16(instr="add     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_add_int_lit8.S b/runtime/interpreter/mterp/arm64/op_add_int_lit8.S
index 2dfb8b9b56a9453d958631d74bdbe95750d82ae1..f4cab96fec380e2d7055f9e2e3de54a886da0fb4 100644
--- a/runtime/interpreter/mterp/arm64/op_add_int_lit8.S
+++ b/runtime/interpreter/mterp/arm64/op_add_int_lit8.S
@@ -1 +1,2 @@
-%include "arm64/binopLit8.S" {"extract":"", "instr":"add     w0, w0, w3, asr #8"}
+%def op_add_int_lit8():
+%  binopLit8(extract="", instr="add     w0, w0, w3, asr #8")
diff --git a/runtime/interpreter/mterp/arm64/op_add_long.S b/runtime/interpreter/mterp/arm64/op_add_long.S
index bc334aa3b246d62eaa3e56d66c1c3f50bf1d9af3..0ac32466bc87ad6a8cf66c7e8be3d60538c3a3f3 100644
--- a/runtime/interpreter/mterp/arm64/op_add_long.S
+++ b/runtime/interpreter/mterp/arm64/op_add_long.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"instr":"add x0, x1, x2"}
+%def op_add_long():
+%  binopWide(instr="add x0, x1, x2")
diff --git a/runtime/interpreter/mterp/arm64/op_add_long_2addr.S b/runtime/interpreter/mterp/arm64/op_add_long_2addr.S
index 5e5dbce73becd9fcbbf5a615a7000e754cb5fe7e..03987eb5c678130223f39776f2e076d4e57c18e7 100644
--- a/runtime/interpreter/mterp/arm64/op_add_long_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_add_long_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"instr":"add     x0, x0, x1"}
+%def op_add_long_2addr():
+%  binopWide2addr(instr="add     x0, x0, x1")
diff --git a/runtime/interpreter/mterp/arm64/op_aget.S b/runtime/interpreter/mterp/arm64/op_aget.S
index 662c9cc7cc4303ae18234120cf2fbb8523add040..edc62f5cbb0661590ea7f2a883bba84d61d3aff1 100644
--- a/runtime/interpreter/mterp/arm64/op_aget.S
+++ b/runtime/interpreter/mterp/arm64/op_aget.S
@@ -1,4 +1,4 @@
-%default { "load":"ldr", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
+%def op_aget(load="ldr", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"):
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/arm64/op_aget_boolean.S b/runtime/interpreter/mterp/arm64/op_aget_boolean.S
index 6ab6cc1bff296e5191aed3ef0bb77a33f0da1744..d6e0a1bbd9c2e1c9077793a6ac30208349f85489 100644
--- a/runtime/interpreter/mterp/arm64/op_aget_boolean.S
+++ b/runtime/interpreter/mterp/arm64/op_aget_boolean.S
@@ -1 +1,2 @@
-%include "arm64/op_aget.S" { "load":"ldrb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aget_boolean():
+%  op_aget(load="ldrb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm64/op_aget_byte.S b/runtime/interpreter/mterp/arm64/op_aget_byte.S
index c7f5b23ebfa24ebbb2fc36d77e9fad8cc01b8e9e..6c9f1b78fa747ccd8f92ea0192fc0e918bbaa3e5 100644
--- a/runtime/interpreter/mterp/arm64/op_aget_byte.S
+++ b/runtime/interpreter/mterp/arm64/op_aget_byte.S
@@ -1 +1,2 @@
-%include "arm64/op_aget.S" { "load":"ldrsb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aget_byte():
+%  op_aget(load="ldrsb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm64/op_aget_char.S b/runtime/interpreter/mterp/arm64/op_aget_char.S
index 9fddf1787ace54dc3c46d4d8a0dfaae728d70f12..c5812e3aff0d275d5df30f9b66ffec225847617f 100644
--- a/runtime/interpreter/mterp/arm64/op_aget_char.S
+++ b/runtime/interpreter/mterp/arm64/op_aget_char.S
@@ -1 +1,2 @@
-%include "arm64/op_aget.S" { "load":"ldrh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aget_char():
+%  op_aget(load="ldrh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm64/op_aget_object.S b/runtime/interpreter/mterp/arm64/op_aget_object.S
index 1bbe3e8a3a432b6fe04517e09cdfde5d5f8472b1..0c5d2c394d94ce8dc005a6a2cc45e43367fb57ec 100644
--- a/runtime/interpreter/mterp/arm64/op_aget_object.S
+++ b/runtime/interpreter/mterp/arm64/op_aget_object.S
@@ -1,3 +1,4 @@
+%def op_aget_object():
     /*
      * Array object get.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/arm64/op_aget_short.S b/runtime/interpreter/mterp/arm64/op_aget_short.S
index 39554de6e6ec667fcf4c727dbdee23a699191c04..9727560fe40453725ea4c52b1a0ac80e68ed6fdb 100644
--- a/runtime/interpreter/mterp/arm64/op_aget_short.S
+++ b/runtime/interpreter/mterp/arm64/op_aget_short.S
@@ -1 +1,2 @@
-%include "arm64/op_aget.S" { "load":"ldrsh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aget_short():
+%  op_aget(load="ldrsh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm64/op_aget_wide.S b/runtime/interpreter/mterp/arm64/op_aget_wide.S
index 6f990ba0cc02b653c5bd38dab659ae82787dd579..e9bccd6e4e20ef5b569880b40d5243db72cc6926 100644
--- a/runtime/interpreter/mterp/arm64/op_aget_wide.S
+++ b/runtime/interpreter/mterp/arm64/op_aget_wide.S
@@ -1,3 +1,4 @@
+%def op_aget_wide():
     /*
      * Array get, 64 bits.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/arm64/op_and_int.S b/runtime/interpreter/mterp/arm64/op_and_int.S
index 31f3f73e7a11458a97c89db4a77aebf9a940efb1..364e6158436591d4fce4e55dffcaad0beb20fc93 100644
--- a/runtime/interpreter/mterp/arm64/op_and_int.S
+++ b/runtime/interpreter/mterp/arm64/op_and_int.S
@@ -1 +1,2 @@
-%include "arm64/binop.S" {"instr":"and     w0, w0, w1"}
+%def op_and_int():
+%  binop(instr="and     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_and_int_2addr.S b/runtime/interpreter/mterp/arm64/op_and_int_2addr.S
index e59632cd06bea134609e30fe41aff1e2e095317a..98a5c5db3af2fae56d22f4fe0272aa3aa3f42eeb 100644
--- a/runtime/interpreter/mterp/arm64/op_and_int_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_and_int_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binop2addr.S" {"instr":"and     w0, w0, w1"}
+%def op_and_int_2addr():
+%  binop2addr(instr="and     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_and_int_lit16.S b/runtime/interpreter/mterp/arm64/op_and_int_lit16.S
index 6540f81554285781555836bfd39b1656f7f2d35d..add2ecc83b39bbe4d246c1a3aab9da596e5440ad 100644
--- a/runtime/interpreter/mterp/arm64/op_and_int_lit16.S
+++ b/runtime/interpreter/mterp/arm64/op_and_int_lit16.S
@@ -1 +1,2 @@
-%include "arm64/binopLit16.S" {"instr":"and     w0, w0, w1"}
+%def op_and_int_lit16():
+%  binopLit16(instr="and     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_and_int_lit8.S b/runtime/interpreter/mterp/arm64/op_and_int_lit8.S
index 495b5cddd6f512aa54fb655e2ecfa1d403dc8160..bf68c2a5ccd6c5e0f642d37c5f03eec53815819b 100644
--- a/runtime/interpreter/mterp/arm64/op_and_int_lit8.S
+++ b/runtime/interpreter/mterp/arm64/op_and_int_lit8.S
@@ -1 +1,2 @@
-%include "arm64/binopLit8.S" {"extract":"", "instr":"and     w0, w0, w3, asr #8"}
+%def op_and_int_lit8():
+%  binopLit8(extract="", instr="and     w0, w0, w3, asr #8")
diff --git a/runtime/interpreter/mterp/arm64/op_and_long.S b/runtime/interpreter/mterp/arm64/op_and_long.S
index ede047d0883b99a1ab8a618d7a1ca522bfb4484c..aff5eadd0561ebda43a9112da285d9e0cdc9336f 100644
--- a/runtime/interpreter/mterp/arm64/op_and_long.S
+++ b/runtime/interpreter/mterp/arm64/op_and_long.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"instr":"and x0, x1, x2"}
+%def op_and_long():
+%  binopWide(instr="and x0, x1, x2")
diff --git a/runtime/interpreter/mterp/arm64/op_and_long_2addr.S b/runtime/interpreter/mterp/arm64/op_and_long_2addr.S
index d62ccef8919cf3bce201f3fefdbdccaa4521fb73..ba71e5cec1ddac9df0b881bf281556813c9961f3 100644
--- a/runtime/interpreter/mterp/arm64/op_and_long_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_and_long_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"instr":"and     x0, x0, x1"}
+%def op_and_long_2addr():
+%  binopWide2addr(instr="and     x0, x0, x1")
diff --git a/runtime/interpreter/mterp/arm64/op_aput.S b/runtime/interpreter/mterp/arm64/op_aput.S
index 175b483d7d7ca56904d63caf6ab8f691407b00ac..85dd5564a93da0f512b64192df3f67163e7ed608 100644
--- a/runtime/interpreter/mterp/arm64/op_aput.S
+++ b/runtime/interpreter/mterp/arm64/op_aput.S
@@ -1,4 +1,4 @@
-%default { "store":"str", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
+%def op_aput(store="str", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"):
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_aput_boolean.S b/runtime/interpreter/mterp/arm64/op_aput_boolean.S
index 5e7a86f15c46c8bee72563f558eba02f415c9d82..467cc4bf20f85f653e699148f96e62a79c5b0700 100644
--- a/runtime/interpreter/mterp/arm64/op_aput_boolean.S
+++ b/runtime/interpreter/mterp/arm64/op_aput_boolean.S
@@ -1 +1,2 @@
-%include "arm64/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aput_boolean():
+%  op_aput(store="strb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm64/op_aput_byte.S b/runtime/interpreter/mterp/arm64/op_aput_byte.S
index d659ebc3d026dab82128ea247b25d946dfb25ab3..2b4c0ba389e7adc8a01028fffb93628a90e45144 100644
--- a/runtime/interpreter/mterp/arm64/op_aput_byte.S
+++ b/runtime/interpreter/mterp/arm64/op_aput_byte.S
@@ -1 +1,2 @@
-%include "arm64/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aput_byte():
+%  op_aput(store="strb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm64/op_aput_char.S b/runtime/interpreter/mterp/arm64/op_aput_char.S
index 7547c808705030eec6796ba744ce01885952d615..cb7dcbad4df997fd1c96f4c8e966aed9ebfc2a28 100644
--- a/runtime/interpreter/mterp/arm64/op_aput_char.S
+++ b/runtime/interpreter/mterp/arm64/op_aput_char.S
@@ -1 +1,2 @@
-%include "arm64/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aput_char():
+%  op_aput(store="strh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm64/op_aput_object.S b/runtime/interpreter/mterp/arm64/op_aput_object.S
index 0146fdc95c2f440ed5d6475d1d2f1730a15d3ef4..4d1ee65f7f224c73698011b2780278675d884418 100644
--- a/runtime/interpreter/mterp/arm64/op_aput_object.S
+++ b/runtime/interpreter/mterp/arm64/op_aput_object.S
@@ -1,3 +1,4 @@
+%def op_aput_object():
     /*
      * Store an object into an array.  vBB[vCC] <- vAA.
      */
diff --git a/runtime/interpreter/mterp/arm64/op_aput_short.S b/runtime/interpreter/mterp/arm64/op_aput_short.S
index 8631e280709689116ce8c463512dfb8d0c9037c6..f624163087bae7b6ff6ff75ca7c2c909e9676b67 100644
--- a/runtime/interpreter/mterp/arm64/op_aput_short.S
+++ b/runtime/interpreter/mterp/arm64/op_aput_short.S
@@ -1 +1,2 @@
-%include "arm64/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aput_short():
+%  op_aput(store="strh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/arm64/op_aput_wide.S b/runtime/interpreter/mterp/arm64/op_aput_wide.S
index e1cf9c1c2f78cffbc7b9967ceae5046a1ee16048..8498783f81cf2724a8fa2fc6c5b664ec41a888ea 100644
--- a/runtime/interpreter/mterp/arm64/op_aput_wide.S
+++ b/runtime/interpreter/mterp/arm64/op_aput_wide.S
@@ -1,3 +1,4 @@
+%def op_aput_wide():
     /*
      * Array put, 64 bits.  vBB[vCC] <- vAA.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_array_length.S b/runtime/interpreter/mterp/arm64/op_array_length.S
index 0cce917ff7dea0cfba4fd3220060665ca0be0fc9..26979b837f5e4d7ae4b52b08f1540806bd631954 100644
--- a/runtime/interpreter/mterp/arm64/op_array_length.S
+++ b/runtime/interpreter/mterp/arm64/op_array_length.S
@@ -1,3 +1,4 @@
+%def op_array_length():
     /*
      * Return the length of an array.
      */
diff --git a/runtime/interpreter/mterp/arm64/op_check_cast.S b/runtime/interpreter/mterp/arm64/op_check_cast.S
index cb9f6068e0e3f028b75aa10b9a6368d2bd479a2c..359c860e485043d172b49f903c097fbd721fa5c5 100644
--- a/runtime/interpreter/mterp/arm64/op_check_cast.S
+++ b/runtime/interpreter/mterp/arm64/op_check_cast.S
@@ -1,3 +1,4 @@
+%def op_check_cast():
     /*
      * Check to see if a cast from one class to another is allowed.
      */
diff --git a/runtime/interpreter/mterp/arm64/op_cmp_long.S b/runtime/interpreter/mterp/arm64/op_cmp_long.S
index c4ad984084cde170c2ff4907f73aae34393423c0..636262c2f755374946d14ad5fba5bd072a2baab8 100644
--- a/runtime/interpreter/mterp/arm64/op_cmp_long.S
+++ b/runtime/interpreter/mterp/arm64/op_cmp_long.S
@@ -1,3 +1,4 @@
+%def op_cmp_long():
     FETCH w0, 1                         // w0<- CCBB
     lsr     w4, wINST, #8               // w4<- AA
     and     w2, w0, #255                // w2<- BB
diff --git a/runtime/interpreter/mterp/arm64/op_cmpg_double.S b/runtime/interpreter/mterp/arm64/op_cmpg_double.S
index 30cb7ebbe2a9afb3f88abe7ae54ff56fbe9383e9..4527873eb1ee5bbe9505fc28bc3a8b88114d2d18 100644
--- a/runtime/interpreter/mterp/arm64/op_cmpg_double.S
+++ b/runtime/interpreter/mterp/arm64/op_cmpg_double.S
@@ -1 +1,2 @@
-%include "arm64/fcmp.S" {"wide":"_WIDE", "r1":"d1", "r2":"d2", "cond":"cc"}
+%def op_cmpg_double():
+%  fcmp(wide="_WIDE", r1="d1", r2="d2", cond="cc")
diff --git a/runtime/interpreter/mterp/arm64/op_cmpg_float.S b/runtime/interpreter/mterp/arm64/op_cmpg_float.S
index ba23f434620a16f91b117379c0954f0473815685..395d1862f72eca8f1208651a343aae0d8191ba45 100644
--- a/runtime/interpreter/mterp/arm64/op_cmpg_float.S
+++ b/runtime/interpreter/mterp/arm64/op_cmpg_float.S
@@ -1 +1,2 @@
-%include "arm64/fcmp.S" {"wide":"", "r1":"s1", "r2":"s2", "cond":"cc"}
+%def op_cmpg_float():
+%  fcmp(wide="", r1="s1", r2="s2", cond="cc")
diff --git a/runtime/interpreter/mterp/arm64/op_cmpl_double.S b/runtime/interpreter/mterp/arm64/op_cmpl_double.S
index c73968588e451f7dbfd0f896c21bb3a82aebf3bf..67b69c8b65d2272989b35f122e13b5bafd9a5470 100644
--- a/runtime/interpreter/mterp/arm64/op_cmpl_double.S
+++ b/runtime/interpreter/mterp/arm64/op_cmpl_double.S
@@ -1 +1,2 @@
-%include "arm64/fcmp.S" {"wide":"_WIDE", "r1":"d1", "r2":"d2", "cond":"lt"}
+%def op_cmpl_double():
+%  fcmp(wide="_WIDE", r1="d1", r2="d2", cond="lt")
diff --git a/runtime/interpreter/mterp/arm64/op_cmpl_float.S b/runtime/interpreter/mterp/arm64/op_cmpl_float.S
index 32a931935b5aac894dfcfc6e016d120908dd5c92..7574f4cec7be2cd71ae9fd754bfd4f36cf88a16b 100644
--- a/runtime/interpreter/mterp/arm64/op_cmpl_float.S
+++ b/runtime/interpreter/mterp/arm64/op_cmpl_float.S
@@ -1 +1,2 @@
-%include "arm64/fcmp.S" {"wide":"", "r1":"s1", "r2":"s2", "cond":"lt"}
+%def op_cmpl_float():
+%  fcmp(wide="", r1="s1", r2="s2", cond="lt")
diff --git a/runtime/interpreter/mterp/arm64/op_const.S b/runtime/interpreter/mterp/arm64/op_const.S
index 031ede1fb23d6111b7cc051e14bf47d73cf775d8..493611e473a0b489a1265d80f81282de241dcd1f 100644
--- a/runtime/interpreter/mterp/arm64/op_const.S
+++ b/runtime/interpreter/mterp/arm64/op_const.S
@@ -1,3 +1,4 @@
+%def op_const():
     /* const vAA, #+BBBBbbbb */
     lsr     w3, wINST, #8               // w3<- AA
     FETCH w0, 1                         // w0<- bbbb (low
diff --git a/runtime/interpreter/mterp/arm64/op_const_16.S b/runtime/interpreter/mterp/arm64/op_const_16.S
index f0e81923c5c17136fb37f7953d400f8f3de681ac..75e69364a798e681b774306fb82a017afa343ba5 100644
--- a/runtime/interpreter/mterp/arm64/op_const_16.S
+++ b/runtime/interpreter/mterp/arm64/op_const_16.S
@@ -1,3 +1,4 @@
+%def op_const_16():
     /* const/16 vAA, #+BBBB */
     FETCH_S w0, 1                       // w0<- ssssBBBB (sign-extended)
     lsr     w3, wINST, #8               // w3<- AA
diff --git a/runtime/interpreter/mterp/arm64/op_const_4.S b/runtime/interpreter/mterp/arm64/op_const_4.S
index 9a36115288617f4b099ea4f6590bdd9e0e0c3c1a..e6281ed82c684147a9a41ed6a699ea3f00032a24 100644
--- a/runtime/interpreter/mterp/arm64/op_const_4.S
+++ b/runtime/interpreter/mterp/arm64/op_const_4.S
@@ -1,3 +1,4 @@
+%def op_const_4():
     /* const/4 vA, #+B */
     sbfx    w1, wINST, #12, #4          // w1<- sssssssB
     ubfx    w0, wINST, #8, #4           // w0<- A
diff --git a/runtime/interpreter/mterp/arm64/op_const_class.S b/runtime/interpreter/mterp/arm64/op_const_class.S
index 7228245b8fe76d6cd1a5af10cb901cf334b117d9..db12ec31414690de6acb180ce962f6676f3ab2f5 100644
--- a/runtime/interpreter/mterp/arm64/op_const_class.S
+++ b/runtime/interpreter/mterp/arm64/op_const_class.S
@@ -1 +1,2 @@
-%include "arm64/const.S" { "helper":"MterpConstClass" }
+%def op_const_class():
+%  const(helper="MterpConstClass")
diff --git a/runtime/interpreter/mterp/arm64/op_const_high16.S b/runtime/interpreter/mterp/arm64/op_const_high16.S
index 3a9edfff91676f703a91e09497adb89e0d168eb5..8a8558f0fcc955a57c6acbf988efe9c6e2d456d7 100644
--- a/runtime/interpreter/mterp/arm64/op_const_high16.S
+++ b/runtime/interpreter/mterp/arm64/op_const_high16.S
@@ -1,3 +1,4 @@
+%def op_const_high16():
     /* const/high16 vAA, #+BBBB0000 */
     FETCH   w0, 1                       // r0<- 0000BBBB (zero-extended)
     lsr     w3, wINST, #8               // r3<- AA
diff --git a/runtime/interpreter/mterp/arm64/op_const_method_handle.S b/runtime/interpreter/mterp/arm64/op_const_method_handle.S
index 0df0fa67988b361a2982a47dd63ec10efdbb96d0..2680c17aad5d6f537298bc455177da35df137274 100644
--- a/runtime/interpreter/mterp/arm64/op_const_method_handle.S
+++ b/runtime/interpreter/mterp/arm64/op_const_method_handle.S
@@ -1 +1,2 @@
-%include "arm64/const.S" { "helper":"MterpConstMethodHandle" }
+%def op_const_method_handle():
+%  const(helper="MterpConstMethodHandle")
diff --git a/runtime/interpreter/mterp/arm64/op_const_method_type.S b/runtime/interpreter/mterp/arm64/op_const_method_type.S
index 1adfe5ad659badc90010c2cc3dafcf37f0cb7086..ea814bf64826079ab9f55e43e47f42180c3ad420 100644
--- a/runtime/interpreter/mterp/arm64/op_const_method_type.S
+++ b/runtime/interpreter/mterp/arm64/op_const_method_type.S
@@ -1 +1,2 @@
-%include "arm64/const.S" { "helper":"MterpConstMethodType" }
+%def op_const_method_type():
+%  const(helper="MterpConstMethodType")
diff --git a/runtime/interpreter/mterp/arm64/op_const_string.S b/runtime/interpreter/mterp/arm64/op_const_string.S
index 8cf0d6dc358996e7080f34883236a49b3c75b13b..41376f870340354594a5a218b1d2379e08042008 100644
--- a/runtime/interpreter/mterp/arm64/op_const_string.S
+++ b/runtime/interpreter/mterp/arm64/op_const_string.S
@@ -1 +1,2 @@
-%include "arm64/const.S" { "helper":"MterpConstString" }
+%def op_const_string():
+%  const(helper="MterpConstString")
diff --git a/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S b/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S
index e1a733987d3be2706c87040c111c336446a8fba6..1a78bcb7999190f1fb266411e529112ef8dc64f6 100644
--- a/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S
+++ b/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S
@@ -1,3 +1,4 @@
+%def op_const_string_jumbo():
     /* const/string vAA, String//BBBBBBBB */
     EXPORT_PC
     FETCH w0, 1                         // w0<- bbbb (low
diff --git a/runtime/interpreter/mterp/arm64/op_const_wide.S b/runtime/interpreter/mterp/arm64/op_const_wide.S
index 8f57ddacfd84acda953ec214262b8e1a374e2995..6d3be6b127d79e8c7c18c21d08fb8cee0efdaed8 100644
--- a/runtime/interpreter/mterp/arm64/op_const_wide.S
+++ b/runtime/interpreter/mterp/arm64/op_const_wide.S
@@ -1,3 +1,4 @@
+%def op_const_wide():
     /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
     FETCH w0, 1                         // w0<- bbbb (low)
     FETCH w1, 2                         // w1<- BBBB (low middle)
diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_16.S b/runtime/interpreter/mterp/arm64/op_const_wide_16.S
index 553d4815418c4389233f8788424cf12908571281..04615e1d4ea9ed4a1a3c66a40f48e46e84060eb8 100644
--- a/runtime/interpreter/mterp/arm64/op_const_wide_16.S
+++ b/runtime/interpreter/mterp/arm64/op_const_wide_16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_16():
     /* const-wide/16 vAA, #+BBBB */
     FETCH_S x0, 1                       // x0<- ssssssssssssBBBB (sign-extended)
     lsr     w3, wINST, #8               // w3<- AA
diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_32.S b/runtime/interpreter/mterp/arm64/op_const_wide_32.S
index 9dc4fc3867b5a926db67cd4e29d94f97bb25dbf9..627ddea3ead559f0ffcf087f1fb6998b47c9fc11 100644
--- a/runtime/interpreter/mterp/arm64/op_const_wide_32.S
+++ b/runtime/interpreter/mterp/arm64/op_const_wide_32.S
@@ -1,3 +1,4 @@
+%def op_const_wide_32():
     /* const-wide/32 vAA, #+BBBBbbbb */
     FETCH   w0, 1                       // x0<- 000000000000bbbb (low)
     lsr     w3, wINST, #8               // w3<- AA
diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_high16.S b/runtime/interpreter/mterp/arm64/op_const_wide_high16.S
index 94ab9876c8ea3729a27805a4fb18e0727a885a2d..d51d25f3e11be789d05bf3ab19143c895c234bf8 100644
--- a/runtime/interpreter/mterp/arm64/op_const_wide_high16.S
+++ b/runtime/interpreter/mterp/arm64/op_const_wide_high16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_high16():
     /* const-wide/high16 vAA, #+BBBB000000000000 */
     FETCH w0, 1                         // w0<- 0000BBBB (zero-extended)
     lsr     w1, wINST, #8               // w1<- AA
diff --git a/runtime/interpreter/mterp/arm64/op_div_double.S b/runtime/interpreter/mterp/arm64/op_div_double.S
index 1f7dad0917fa4c39953bde8daa0991b0b01375c2..ec5b1f5bbbfef85463682c8e24c64140668086a3 100644
--- a/runtime/interpreter/mterp/arm64/op_div_double.S
+++ b/runtime/interpreter/mterp/arm64/op_div_double.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"instr":"fdiv d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"}
+%def op_div_double():
+%  binopWide(instr="fdiv d0, d1, d2", result="d0", r1="d1", r2="d2")
diff --git a/runtime/interpreter/mterp/arm64/op_div_double_2addr.S b/runtime/interpreter/mterp/arm64/op_div_double_2addr.S
index 414a17565842dd338f6f0c9bfe6a6560a98f5cb7..e2781b884f6c654bb87c1baaaae9e8a6b7a16852 100644
--- a/runtime/interpreter/mterp/arm64/op_div_double_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_div_double_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"instr":"fdiv     d0, d0, d1", "r0":"d0", "r1":"d1"}
+%def op_div_double_2addr():
+%  binopWide2addr(instr="fdiv     d0, d0, d1", r0="d0", r1="d1")
diff --git a/runtime/interpreter/mterp/arm64/op_div_float.S b/runtime/interpreter/mterp/arm64/op_div_float.S
index f24a26c09bad97e329538e5694542f47a5239032..f0e72c43f95f4119ca0a32f53bd7b15db1312dd3 100644
--- a/runtime/interpreter/mterp/arm64/op_div_float.S
+++ b/runtime/interpreter/mterp/arm64/op_div_float.S
@@ -1 +1,2 @@
-%include "arm64/fbinop.S" {"instr":"fdiv   s0, s0, s1"}
+%def op_div_float():
+%  fbinop(instr="fdiv   s0, s0, s1")
diff --git a/runtime/interpreter/mterp/arm64/op_div_float_2addr.S b/runtime/interpreter/mterp/arm64/op_div_float_2addr.S
index 2888049c9ea732dfe03a0f51b9001a15b5e4960c..aa73950ce5676a7c016778f4069ca1926008931a 100644
--- a/runtime/interpreter/mterp/arm64/op_div_float_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_div_float_2addr.S
@@ -1 +1,2 @@
-%include "arm64/fbinop2addr.S" {"instr":"fdiv   s2, s0, s1"}
+%def op_div_float_2addr():
+%  fbinop2addr(instr="fdiv   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm64/op_div_int.S b/runtime/interpreter/mterp/arm64/op_div_int.S
index 88371c08d9a31a418623fb9efbc0719427e9a812..6f4cbf327f63253f34948c06b6a5f72fe2d8bdc3 100644
--- a/runtime/interpreter/mterp/arm64/op_div_int.S
+++ b/runtime/interpreter/mterp/arm64/op_div_int.S
@@ -1 +1,2 @@
-%include "arm64/binop.S" {"instr":"sdiv     w0, w0, w1", "chkzero":"1"}
+%def op_div_int():
+%  binop(instr="sdiv     w0, w0, w1", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_div_int_2addr.S b/runtime/interpreter/mterp/arm64/op_div_int_2addr.S
index 5f5a80fe524a26462e3c1d22e378598a57cd54db..eb0106662162055b82f982234934bc40b67fbc56 100644
--- a/runtime/interpreter/mterp/arm64/op_div_int_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_div_int_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binop2addr.S" {"instr":"sdiv     w0, w0, w1", "chkzero":"1"}
+%def op_div_int_2addr():
+%  binop2addr(instr="sdiv     w0, w0, w1", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_div_int_lit16.S b/runtime/interpreter/mterp/arm64/op_div_int_lit16.S
index dc7a484c6ab1a122c3629d2321d227b81f53eb30..c5cdb96fcf77d992b8e4c275ee76be5c9849e193 100644
--- a/runtime/interpreter/mterp/arm64/op_div_int_lit16.S
+++ b/runtime/interpreter/mterp/arm64/op_div_int_lit16.S
@@ -1 +1,2 @@
-%include "arm64/binopLit16.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"}
+%def op_div_int_lit16():
+%  binopLit16(instr="sdiv w0, w0, w1", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_div_int_lit8.S b/runtime/interpreter/mterp/arm64/op_div_int_lit8.S
index c06521c4bc728dfb11a5565c8ed96698bd3f5493..3842cd92b1306952edbc27ac3123a511bd97df26 100644
--- a/runtime/interpreter/mterp/arm64/op_div_int_lit8.S
+++ b/runtime/interpreter/mterp/arm64/op_div_int_lit8.S
@@ -1 +1,2 @@
-%include "arm64/binopLit8.S" {"instr":"sdiv     w0, w0, w1", "chkzero":"1"}
+%def op_div_int_lit8():
+%  binopLit8(instr="sdiv     w0, w0, w1", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_div_long.S b/runtime/interpreter/mterp/arm64/op_div_long.S
index 820ae3db6831cab582fb62a3d314cfe523d6a339..696a91f13404fe7749e6fab63f8cb9890b481224 100644
--- a/runtime/interpreter/mterp/arm64/op_div_long.S
+++ b/runtime/interpreter/mterp/arm64/op_div_long.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"instr":"sdiv x0, x1, x2", "chkzero":"1"}
+%def op_div_long():
+%  binopWide(instr="sdiv x0, x1, x2", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_div_long_2addr.S b/runtime/interpreter/mterp/arm64/op_div_long_2addr.S
index da7eabdc9d9f449e211e36d8be650a36d036a286..cac878c41c3359d66636d0d301e5ba254a6f5dbe 100644
--- a/runtime/interpreter/mterp/arm64/op_div_long_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_div_long_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"instr":"sdiv     x0, x0, x1", "chkzero":"1"}
+%def op_div_long_2addr():
+%  binopWide2addr(instr="sdiv     x0, x0, x1", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_double_to_float.S b/runtime/interpreter/mterp/arm64/op_double_to_float.S
index c1555fdaf9416fcd5d92be0cb68be4665fba23a0..292dcc78a61180ef8be497355d4271a12d786e32 100644
--- a/runtime/interpreter/mterp/arm64/op_double_to_float.S
+++ b/runtime/interpreter/mterp/arm64/op_double_to_float.S
@@ -1 +1,2 @@
-%include "arm64/funopNarrower.S" {"instr":"fcvt s0, d0", "srcreg":"d0", "tgtreg":"s0"}
+%def op_double_to_float():
+%  funopNarrower(instr="fcvt s0, d0", srcreg="d0", tgtreg="s0")
diff --git a/runtime/interpreter/mterp/arm64/op_double_to_int.S b/runtime/interpreter/mterp/arm64/op_double_to_int.S
index 7244bac2fc182c373528e7d6cfe84cbee5c1d5f6..640e6daa8145b165e09362b328736839377fb08d 100644
--- a/runtime/interpreter/mterp/arm64/op_double_to_int.S
+++ b/runtime/interpreter/mterp/arm64/op_double_to_int.S
@@ -1 +1,2 @@
-%include "arm64/funopNarrower.S" {"instr":"fcvtzs w0, d0", "srcreg":"d0", "tgtreg":"w0"}
+%def op_double_to_int():
+%  funopNarrower(instr="fcvtzs w0, d0", srcreg="d0", tgtreg="w0")
diff --git a/runtime/interpreter/mterp/arm64/op_double_to_long.S b/runtime/interpreter/mterp/arm64/op_double_to_long.S
index 741160b564449bed0f0aec852b18916e77278e26..99c15eb601474317e13d94a45ef4df405f8c5112 100644
--- a/runtime/interpreter/mterp/arm64/op_double_to_long.S
+++ b/runtime/interpreter/mterp/arm64/op_double_to_long.S
@@ -1 +1,2 @@
-%include "arm64/funopWide.S" {"instr":"fcvtzs x0, d0", "srcreg":"d0", "tgtreg":"x0"}
+%def op_double_to_long():
+%  funopWide(instr="fcvtzs x0, d0", srcreg="d0", tgtreg="x0")
diff --git a/runtime/interpreter/mterp/arm64/op_fill_array_data.S b/runtime/interpreter/mterp/arm64/op_fill_array_data.S
index 86fa6dbbd2775f20a4b60a7da0ea9c70857ad775..2ae444cc29dd65ce34e831425ad488c2055dc42b 100644
--- a/runtime/interpreter/mterp/arm64/op_fill_array_data.S
+++ b/runtime/interpreter/mterp/arm64/op_fill_array_data.S
@@ -1,3 +1,4 @@
+%def op_fill_array_data():
     /* fill-array-data vAA, +BBBBBBBB */
     EXPORT_PC
     FETCH   w0, 1                       // x0<- 000000000000bbbb (lo)
diff --git a/runtime/interpreter/mterp/arm64/op_filled_new_array.S b/runtime/interpreter/mterp/arm64/op_filled_new_array.S
index 806a1b1201862872aad7b472f2718152c3e0a83f..2be627c3afbea88a2f26d3a0dd4cd2b866ac2eb3 100644
--- a/runtime/interpreter/mterp/arm64/op_filled_new_array.S
+++ b/runtime/interpreter/mterp/arm64/op_filled_new_array.S
@@ -1,4 +1,4 @@
-%default { "helper":"MterpFilledNewArray" }
+%def op_filled_new_array(helper="MterpFilledNewArray"):
     /*
      * Create a new array with elements filled from registers.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S b/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S
index 3c9a419628eef7f011d15e97c9389680ff84df0b..1667de149ace0bdaaafcd36c43724422682df424 100644
--- a/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S
+++ b/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S
@@ -1 +1,2 @@
-%include "arm64/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" }
+%def op_filled_new_array_range():
+%  op_filled_new_array(helper="MterpFilledNewArrayRange")
diff --git a/runtime/interpreter/mterp/arm64/op_float_to_double.S b/runtime/interpreter/mterp/arm64/op_float_to_double.S
index 892feca21b91012fb666048642f24241bc7d3493..c3dff392834dd37ca9aa692d519f9199d6b3ca30 100644
--- a/runtime/interpreter/mterp/arm64/op_float_to_double.S
+++ b/runtime/interpreter/mterp/arm64/op_float_to_double.S
@@ -1 +1,2 @@
-%include "arm64/funopWider.S" {"instr":"fcvt  d0, s0", "srcreg":"s0", "tgtreg":"d0"}
+%def op_float_to_double():
+%  funopWider(instr="fcvt  d0, s0", srcreg="s0", tgtreg="d0")
diff --git a/runtime/interpreter/mterp/arm64/op_float_to_int.S b/runtime/interpreter/mterp/arm64/op_float_to_int.S
index c849d8165d191375ba9ba88d9633bed05cfb259b..ed784e2e144be29f318fd076156bdb8ae8b0fdba 100644
--- a/runtime/interpreter/mterp/arm64/op_float_to_int.S
+++ b/runtime/interpreter/mterp/arm64/op_float_to_int.S
@@ -1 +1,2 @@
-%include "arm64/funopNarrow.S" {"instr":"fcvtzs w0, s0", "srcreg":"s0", "tgtreg":"w0"}
+%def op_float_to_int():
+%  funopNarrow(instr="fcvtzs w0, s0", srcreg="s0", tgtreg="w0")
diff --git a/runtime/interpreter/mterp/arm64/op_float_to_long.S b/runtime/interpreter/mterp/arm64/op_float_to_long.S
index c3de16f9ffa8b1856892bb6fca505703e691ea63..14912493b5bf21af563b92485b1d5eee0d252f49 100644
--- a/runtime/interpreter/mterp/arm64/op_float_to_long.S
+++ b/runtime/interpreter/mterp/arm64/op_float_to_long.S
@@ -1 +1,2 @@
-%include "arm64/funopWider.S" {"instr":"fcvtzs x0, s0", "srcreg":"s0", "tgtreg":"x0"}
+%def op_float_to_long():
+%  funopWider(instr="fcvtzs x0, s0", srcreg="s0", tgtreg="x0")
diff --git a/runtime/interpreter/mterp/arm64/op_goto.S b/runtime/interpreter/mterp/arm64/op_goto.S
index 6381e94fb5167b601487bd50096449c2b6e76b8a..722eec60a3fc8bcaed02098548e70914e2dffb37 100644
--- a/runtime/interpreter/mterp/arm64/op_goto.S
+++ b/runtime/interpreter/mterp/arm64/op_goto.S
@@ -1,3 +1,4 @@
+%def op_goto():
     /*
      * Unconditional branch, 8-bit offset.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_goto_16.S b/runtime/interpreter/mterp/arm64/op_goto_16.S
index fb9a80a3c18ff847469f88c6befaad493d7ef12d..b5cfa71fceced8acbc96b1397c883a34768e72be 100644
--- a/runtime/interpreter/mterp/arm64/op_goto_16.S
+++ b/runtime/interpreter/mterp/arm64/op_goto_16.S
@@ -1,3 +1,4 @@
+%def op_goto_16():
     /*
      * Unconditional branch, 16-bit offset.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_goto_32.S b/runtime/interpreter/mterp/arm64/op_goto_32.S
index b13cb41bc71e260d6e338bb2915a525525a501b0..3843ba2af31a79510db8be8acc41bed91c7446fd 100644
--- a/runtime/interpreter/mterp/arm64/op_goto_32.S
+++ b/runtime/interpreter/mterp/arm64/op_goto_32.S
@@ -1,3 +1,4 @@
+%def op_goto_32():
     /*
      * Unconditional branch, 32-bit offset.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_if_eq.S b/runtime/interpreter/mterp/arm64/op_if_eq.S
index aa4a0f16a73628b6c0af071a5ad9e0ed824f804d..da58674fd4f81861aefae860c94e933f33d6cb26 100644
--- a/runtime/interpreter/mterp/arm64/op_if_eq.S
+++ b/runtime/interpreter/mterp/arm64/op_if_eq.S
@@ -1 +1,2 @@
-%include "arm64/bincmp.S" { "condition":"eq" }
+%def op_if_eq():
+%  bincmp(condition="eq")
diff --git a/runtime/interpreter/mterp/arm64/op_if_eqz.S b/runtime/interpreter/mterp/arm64/op_if_eqz.S
index 47c1dee8cfdff1765fcac9dbdcd736c54ed545ca..8241db82873f8c932d198ce14d9c22d2831ea25d 100644
--- a/runtime/interpreter/mterp/arm64/op_if_eqz.S
+++ b/runtime/interpreter/mterp/arm64/op_if_eqz.S
@@ -1 +1,2 @@
-%include "arm64/zcmp.S" { "compare":"0", "branch":"cbz     w2," }
+%def op_if_eqz():
+%  zcmp(compare="0", branch="cbz     w2,")
diff --git a/runtime/interpreter/mterp/arm64/op_if_ge.S b/runtime/interpreter/mterp/arm64/op_if_ge.S
index d6ec761bfe9ee3e2b521dae593af5a08826e0fcf..5b6ed2f9944653fb88329ebabee2b2799299ce5d 100644
--- a/runtime/interpreter/mterp/arm64/op_if_ge.S
+++ b/runtime/interpreter/mterp/arm64/op_if_ge.S
@@ -1 +1,2 @@
-%include "arm64/bincmp.S" { "condition":"ge" }
+%def op_if_ge():
+%  bincmp(condition="ge")
diff --git a/runtime/interpreter/mterp/arm64/op_if_gez.S b/runtime/interpreter/mterp/arm64/op_if_gez.S
index 087e094a7632c10294a342c67c379cbbcddbe358..f7903b8b1da8ac050dbb915de0d73a318cc6c5de 100644
--- a/runtime/interpreter/mterp/arm64/op_if_gez.S
+++ b/runtime/interpreter/mterp/arm64/op_if_gez.S
@@ -1 +1,2 @@
-%include "arm64/zcmp.S" { "compare":"0", "branch":"tbz     w2, #31," }
+%def op_if_gez():
+%  zcmp(compare="0", branch="tbz     w2, #31,")
diff --git a/runtime/interpreter/mterp/arm64/op_if_gt.S b/runtime/interpreter/mterp/arm64/op_if_gt.S
index 7db8e9d911c6f1e9c1fd5b10ef4aff405537b2bf..201decff1a91a48790fa913ac1d3efddfe919764 100644
--- a/runtime/interpreter/mterp/arm64/op_if_gt.S
+++ b/runtime/interpreter/mterp/arm64/op_if_gt.S
@@ -1 +1,2 @@
-%include "arm64/bincmp.S" { "condition":"gt" }
+%def op_if_gt():
+%  bincmp(condition="gt")
diff --git a/runtime/interpreter/mterp/arm64/op_if_gtz.S b/runtime/interpreter/mterp/arm64/op_if_gtz.S
index 476b26543144ffe0e8389a4600b9e13cec2a4377..e0663a0206e400491d0978056531117f8c6abec5 100644
--- a/runtime/interpreter/mterp/arm64/op_if_gtz.S
+++ b/runtime/interpreter/mterp/arm64/op_if_gtz.S
@@ -1 +1,2 @@
-%include "arm64/zcmp.S" { "branch":"b.gt" }
+%def op_if_gtz():
+%  zcmp(branch="b.gt")
diff --git a/runtime/interpreter/mterp/arm64/op_if_le.S b/runtime/interpreter/mterp/arm64/op_if_le.S
index ca3a83fff7697b04ec94b7429992c99e70b3636e..e6024f2b3e68b7b5654e49affe5582d6bd5ad598 100644
--- a/runtime/interpreter/mterp/arm64/op_if_le.S
+++ b/runtime/interpreter/mterp/arm64/op_if_le.S
@@ -1 +1,2 @@
-%include "arm64/bincmp.S" { "condition":"le" }
+%def op_if_le():
+%  bincmp(condition="le")
diff --git a/runtime/interpreter/mterp/arm64/op_if_lez.S b/runtime/interpreter/mterp/arm64/op_if_lez.S
index 2717a60ebfa59cb8e298d67134675e4ad194eae8..7ec4a9ee2641c472bf525dbddc4c23e16bc70e58 100644
--- a/runtime/interpreter/mterp/arm64/op_if_lez.S
+++ b/runtime/interpreter/mterp/arm64/op_if_lez.S
@@ -1 +1,2 @@
-%include "arm64/zcmp.S" { "branch":"b.le" }
+%def op_if_lez():
+%  zcmp(branch="b.le")
diff --git a/runtime/interpreter/mterp/arm64/op_if_lt.S b/runtime/interpreter/mterp/arm64/op_if_lt.S
index 56450a15ca7a9607a9848722820ac68953e80ae1..4ef22fd7987d9f7c113d65b85290703c9d60cfe2 100644
--- a/runtime/interpreter/mterp/arm64/op_if_lt.S
+++ b/runtime/interpreter/mterp/arm64/op_if_lt.S
@@ -1 +1,2 @@
-%include "arm64/bincmp.S" { "condition":"lt" }
+%def op_if_lt():
+%  bincmp(condition="lt")
diff --git a/runtime/interpreter/mterp/arm64/op_if_ltz.S b/runtime/interpreter/mterp/arm64/op_if_ltz.S
index 86089c10ba10f5266d0feb05e87b0adbf9262e9d..a9f04ee47824cf384378607fda6947ae94638f75 100644
--- a/runtime/interpreter/mterp/arm64/op_if_ltz.S
+++ b/runtime/interpreter/mterp/arm64/op_if_ltz.S
@@ -1 +1,2 @@
-%include "arm64/zcmp.S" { "compare":"0", "branch":"tbnz    w2, #31," }
+%def op_if_ltz():
+%  zcmp(compare="0", branch="tbnz    w2, #31,")
diff --git a/runtime/interpreter/mterp/arm64/op_if_ne.S b/runtime/interpreter/mterp/arm64/op_if_ne.S
index 14d9e13dcf4534a50d9f398b8d708234b23225b4..ec3a688b294d4e3ceff3e99a22de2ecd4dcb220f 100644
--- a/runtime/interpreter/mterp/arm64/op_if_ne.S
+++ b/runtime/interpreter/mterp/arm64/op_if_ne.S
@@ -1 +1,2 @@
-%include "arm64/bincmp.S" { "condition":"ne" }
+%def op_if_ne():
+%  bincmp(condition="ne")
diff --git a/runtime/interpreter/mterp/arm64/op_if_nez.S b/runtime/interpreter/mterp/arm64/op_if_nez.S
index efacc88806de959d0280e0864ff09282c73fbe4a..c4bb3b3bdf7ca518662fab118988008c10b4e4d8 100644
--- a/runtime/interpreter/mterp/arm64/op_if_nez.S
+++ b/runtime/interpreter/mterp/arm64/op_if_nez.S
@@ -1 +1,2 @@
-%include "arm64/zcmp.S" { "compare":"0", "branch":"cbnz    w2," }
+%def op_if_nez():
+%  zcmp(compare="0", branch="cbnz    w2,")
diff --git a/runtime/interpreter/mterp/arm64/op_iget.S b/runtime/interpreter/mterp/arm64/op_iget.S
index 48b9cad44bd039138c5040232dba399814afacbb..d09edc0a17c38245736a29f1cf55eb6f5272b87d 100644
--- a/runtime/interpreter/mterp/arm64/op_iget.S
+++ b/runtime/interpreter/mterp/arm64/op_iget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIGetU32"}
-%include "arm64/field.S" { }
+%def op_iget(is_object="0", helper="MterpIGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/arm64/op_iget_boolean.S b/runtime/interpreter/mterp/arm64/op_iget_boolean.S
index 9a83b2a596e63d58bd31e5a8b2c69978ea22d070..cb8edeec773fb6468b5c331b435e409da634f505 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_boolean.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_boolean.S
@@ -1 +1,2 @@
-%include "arm64/op_iget.S" { "helper":"MterpIGetU8" }
+%def op_iget_boolean():
+%  op_iget(helper="MterpIGetU8")
diff --git a/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S
index 2ceccb9ef0b9cf2cbd7d0355bcaf872fb1a8e4ee..7ac9fce5353c1d73c1407533eaab319c1f43f360 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S
@@ -1 +1,2 @@
-%include "arm64/op_iget_quick.S" { "load":"ldrb" }
+%def op_iget_boolean_quick():
+%  op_iget_quick(load="ldrb")
diff --git a/runtime/interpreter/mterp/arm64/op_iget_byte.S b/runtime/interpreter/mterp/arm64/op_iget_byte.S
index f73e634621bed16174ee7a2e67f15d82b8a61c52..2b87fb16b560430baefa05d3f6e20195cb963d23 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_byte.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_byte.S
@@ -1 +1,2 @@
-%include "arm64/op_iget.S" { "helper":"MterpIGetI8" }
+%def op_iget_byte():
+%  op_iget(helper="MterpIGetI8")
diff --git a/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S b/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S
index 6e97b721839121a404bd95201eb81c5d0b2a09f9..bbccaffe94cc357bd501c794d5a7f141379430ae 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S
@@ -1 +1,2 @@
-%include "arm64/op_iget_quick.S" { "load":"ldrsb" }
+%def op_iget_byte_quick():
+%  op_iget_quick(load="ldrsb")
diff --git a/runtime/interpreter/mterp/arm64/op_iget_char.S b/runtime/interpreter/mterp/arm64/op_iget_char.S
index a5efd9e3ed27ec0fb7a0c12b7d988ce5a6bc6c9b..001bd03e2b85edc215b29789ba4fc55044b4a230 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_char.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_char.S
@@ -1 +1,2 @@
-%include "arm64/op_iget.S" { "helper":"MterpIGetU16" }
+%def op_iget_char():
+%  op_iget(helper="MterpIGetU16")
diff --git a/runtime/interpreter/mterp/arm64/op_iget_char_quick.S b/runtime/interpreter/mterp/arm64/op_iget_char_quick.S
index 325dd1cf9e5b05aecf0718ac368617dafb987b93..71a9276a81e1c2d8d9892edbb8aa77b97c2af05a 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_char_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_char_quick.S
@@ -1 +1,2 @@
-%include "arm64/op_iget_quick.S" { "load":"ldrh" }
+%def op_iget_char_quick():
+%  op_iget_quick(load="ldrh")
diff --git a/runtime/interpreter/mterp/arm64/op_iget_object.S b/runtime/interpreter/mterp/arm64/op_iget_object.S
index 40ddadd97111ce1d542dc18fb3bf0861d08c708f..4e5f769547b494ed962728edba2d102a106b332a 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_object.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_object.S
@@ -1 +1,2 @@
-%include "arm64/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" }
+%def op_iget_object():
+%  op_iget(is_object="1", helper="MterpIGetObj")
diff --git a/runtime/interpreter/mterp/arm64/op_iget_object_quick.S b/runtime/interpreter/mterp/arm64/op_iget_object_quick.S
index e9a797dfe18abd6769ab0fa875973f1bc31571d2..f55b08f909eb3e959aa326cf70969aa4fa430774 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_object_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iget_object_quick():
     /* For: iget-object-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
diff --git a/runtime/interpreter/mterp/arm64/op_iget_quick.S b/runtime/interpreter/mterp/arm64/op_iget_quick.S
index 699b2c42293ed3f04a152d37fd270c4844558f9e..641bfab7dfd37d60956bba37c8a039a1a98179c2 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_quick.S
@@ -1,4 +1,4 @@
-%default { "load":"ldr", "extend":"" }
+%def op_iget_quick(load="ldr", extend=""):
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
diff --git a/runtime/interpreter/mterp/arm64/op_iget_short.S b/runtime/interpreter/mterp/arm64/op_iget_short.S
index bb81c1708eea2b1f75289a116925887c15122232..a62c4d998f1d05ed2a3bb1c2f2bf2cca501dfdb8 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_short.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_short.S
@@ -1 +1,2 @@
-%include "arm64/op_iget.S" { "helper":"MterpIGetI16" }
+%def op_iget_short():
+%  op_iget(helper="MterpIGetI16")
diff --git a/runtime/interpreter/mterp/arm64/op_iget_short_quick.S b/runtime/interpreter/mterp/arm64/op_iget_short_quick.S
index 83670701c1000d8912e73ec141803ea249f706e9..5dbdc4fa22ba4d6df0a46ce57380919994cc3411 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_short_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_short_quick.S
@@ -1 +1,2 @@
-%include "arm64/op_iget_quick.S" { "load":"ldrsh" }
+%def op_iget_short_quick():
+%  op_iget_quick(load="ldrsh")
diff --git a/runtime/interpreter/mterp/arm64/op_iget_wide.S b/runtime/interpreter/mterp/arm64/op_iget_wide.S
index 70061d65771fcabe99f7d5097a872db38ac4c549..9643cc340313b657f2485df521ed0ee0cba25f7b 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_wide.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_wide.S
@@ -1 +1,2 @@
-%include "arm64/op_iget.S" { "helper":"MterpIGetU64" }
+%def op_iget_wide():
+%  op_iget(helper="MterpIGetU64")
diff --git a/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S b/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S
index e9388e477db41de5375decdda7240641b84342ff..9f7a61b4b21f1f3de4efe2732bfb1183913f7bc2 100644
--- a/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S
@@ -1,3 +1,4 @@
+%def op_iget_wide_quick():
     /* iget-wide-quick vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
     FETCH w4, 1                         // w4<- field byte offset
diff --git a/runtime/interpreter/mterp/arm64/op_instance_of.S b/runtime/interpreter/mterp/arm64/op_instance_of.S
index a56705a68b37ba33e237e5c0cde8596878254240..9c337d12fe2751b09e7f78d3335a94dc58196d15 100644
--- a/runtime/interpreter/mterp/arm64/op_instance_of.S
+++ b/runtime/interpreter/mterp/arm64/op_instance_of.S
@@ -1,3 +1,4 @@
+%def op_instance_of():
     /*
      * Check to see if an object reference is an instance of a class.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_int_to_byte.S b/runtime/interpreter/mterp/arm64/op_int_to_byte.S
index 43f814820a4d7d9daa6eedef804e5ccff41f5de8..8174978f48d613c6081d33536397eddf1893b153 100644
--- a/runtime/interpreter/mterp/arm64/op_int_to_byte.S
+++ b/runtime/interpreter/mterp/arm64/op_int_to_byte.S
@@ -1 +1,2 @@
-%include "arm64/unop.S" {"instr":"sxtb    w0, w0"}
+%def op_int_to_byte():
+%  unop(instr="sxtb    w0, w0")
diff --git a/runtime/interpreter/mterp/arm64/op_int_to_char.S b/runtime/interpreter/mterp/arm64/op_int_to_char.S
index f092170681ac6394b9e6cfdeb4bf73add48d65e9..bbf32394b755eead99354b9e82b428a1a2b7a3ea 100644
--- a/runtime/interpreter/mterp/arm64/op_int_to_char.S
+++ b/runtime/interpreter/mterp/arm64/op_int_to_char.S
@@ -1 +1,2 @@
-%include "arm64/unop.S" {"instr":"uxth    w0, w0"}
+%def op_int_to_char():
+%  unop(instr="uxth    w0, w0")
diff --git a/runtime/interpreter/mterp/arm64/op_int_to_double.S b/runtime/interpreter/mterp/arm64/op_int_to_double.S
index 3dee75a1416d8ca83548e34f3104da6f3a25eea5..f2b9dc0c9f671717573c4741e81f5469cfb9f467 100644
--- a/runtime/interpreter/mterp/arm64/op_int_to_double.S
+++ b/runtime/interpreter/mterp/arm64/op_int_to_double.S
@@ -1 +1,2 @@
-%include "arm64/funopWider.S" {"instr":"scvtf d0, w0", "srcreg":"w0", "tgtreg":"d0"}
+%def op_int_to_double():
+%  funopWider(instr="scvtf d0, w0", srcreg="w0", tgtreg="d0")
diff --git a/runtime/interpreter/mterp/arm64/op_int_to_float.S b/runtime/interpreter/mterp/arm64/op_int_to_float.S
index 3ebbdc7cb9b76657135f3e0f7c2e81975db80cb6..ffe873de81c36e95f8f5c4a0fd7ae18bc73e9246 100644
--- a/runtime/interpreter/mterp/arm64/op_int_to_float.S
+++ b/runtime/interpreter/mterp/arm64/op_int_to_float.S
@@ -1 +1,2 @@
-%include "arm64/funopNarrow.S" {"instr":"scvtf s0, w0", "srcreg":"w0", "tgtreg":"s0"}
+%def op_int_to_float():
+%  funopNarrow(instr="scvtf s0, w0", srcreg="w0", tgtreg="s0")
diff --git a/runtime/interpreter/mterp/arm64/op_int_to_long.S b/runtime/interpreter/mterp/arm64/op_int_to_long.S
index 45e31124ff3d55c5a0a829b14e71fe3cb7a625f2..d7e5b463e6a52f7a756cadd69b12f0404d54e4d1 100644
--- a/runtime/interpreter/mterp/arm64/op_int_to_long.S
+++ b/runtime/interpreter/mterp/arm64/op_int_to_long.S
@@ -1,3 +1,4 @@
+%def op_int_to_long():
     /* int-to-long vA, vB */
     lsr     w3, wINST, #12              // w3<- B
     ubfx    w4, wINST, #8, #4           // w4<- A
diff --git a/runtime/interpreter/mterp/arm64/op_int_to_short.S b/runtime/interpreter/mterp/arm64/op_int_to_short.S
index 87fb8046682eef0caa126c7455d1fe5f6e938f29..0c51c76dc538a5223b3d0c81364034d50510bab8 100644
--- a/runtime/interpreter/mterp/arm64/op_int_to_short.S
+++ b/runtime/interpreter/mterp/arm64/op_int_to_short.S
@@ -1 +1,2 @@
-%include "arm64/unop.S" {"instr":"sxth    w0, w0"}
+%def op_int_to_short():
+%  unop(instr="sxth    w0, w0")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_custom.S b/runtime/interpreter/mterp/arm64/op_invoke_custom.S
index 3686584950ccb68f245fb94125efda68cb95ee3e..4bba9ee5241061aa29e63ea32bb9d575e34286ea 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_custom.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_custom.S
@@ -1 +1,2 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeCustom" }
+%def op_invoke_custom():
+%  invoke(helper="MterpInvokeCustom")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S b/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S
index 06de86a6a06e5752bcafad172385d332746e884f..57e61af1fa860d814a9da1eaab56b25f199771aa 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S
@@ -1 +1,2 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeCustomRange" }
+%def op_invoke_custom_range():
+%  invoke(helper="MterpInvokeCustomRange")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_direct.S b/runtime/interpreter/mterp/arm64/op_invoke_direct.S
index c117232d9cad68f98a8c9466616a43260b523840..d3139cf39b42aca474e7d18dcf526e32e80ced85 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_direct.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_direct.S
@@ -1 +1,2 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeDirect" }
+%def op_invoke_direct():
+%  invoke(helper="MterpInvokeDirect")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S b/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S
index efc54c71d92572c8b94dd2060168938cf331eb68..b4a161f48bf8b90b0561e577cdf35f27feb71f23 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S
@@ -1 +1,2 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeDirectRange" }
+%def op_invoke_direct_range():
+%  invoke(helper="MterpInvokeDirectRange")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_interface.S b/runtime/interpreter/mterp/arm64/op_invoke_interface.S
index 12dfa592d50190086ae10aab4deda8cdf94f163f..b0641262530cb4359c0a054e8307346f64537478 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_interface.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_interface.S
@@ -1,4 +1,5 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeInterface" }
+%def op_invoke_interface():
+%  invoke(helper="MterpInvokeInterface")
     /*
      * Handle an interface method call.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S b/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S
index 61caaf47e38be8e0f7bacb1fc2814f18e488a79e..298911537760c27944307413bb6bbc1a686768a5 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S
@@ -1 +1,2 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeInterfaceRange" }
+%def op_invoke_interface_range():
+%  invoke(helper="MterpInvokeInterfaceRange")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S
index aace98f1a203b073df911487c35f38331f805541..ce61f5aa0e6039481359af9e0d7de053a159fc79 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S
@@ -1 +1,2 @@
-%include "arm64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" }
+%def op_invoke_polymorphic():
+%  invoke_polymorphic(helper="MterpInvokePolymorphic")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S
index 30c8c09cce199f8ff6b9c405763dac5cf54866be..16731bdb4040829bf0020b8524b4f70866b1f1e8 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S
@@ -1 +1,2 @@
-%include "arm64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" }
+%def op_invoke_polymorphic_range():
+%  invoke_polymorphic(helper="MterpInvokePolymorphicRange")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_static.S b/runtime/interpreter/mterp/arm64/op_invoke_static.S
index 634eda2736e829f10a39b0159831ba375092cd2b..3e38d36a27a20c1d0f1481b80d6585a43343b6cb 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_static.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_static.S
@@ -1,2 +1,3 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeStatic" }
+%def op_invoke_static():
+%  invoke(helper="MterpInvokeStatic")
 
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_static_range.S b/runtime/interpreter/mterp/arm64/op_invoke_static_range.S
index 32cdcddaa489c8df8cb9b79600a508f92921b485..e0a546c92b4be72a4a5040d03e0018b1b248f536 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_static_range.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_static_range.S
@@ -1 +1,2 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeStaticRange" }
+%def op_invoke_static_range():
+%  invoke(helper="MterpInvokeStaticRange")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_super.S b/runtime/interpreter/mterp/arm64/op_invoke_super.S
index def2c552fd0301289631b09008afd97be66702e3..3c34c9942ead4172f252ab73aa378fdea74a2bf3 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_super.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_super.S
@@ -1,4 +1,5 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeSuper" }
+%def op_invoke_super():
+%  invoke(helper="MterpInvokeSuper")
     /*
      * Handle a "super" method call.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_super_range.S b/runtime/interpreter/mterp/arm64/op_invoke_super_range.S
index 27fb8591a4c42650d13c16880d73b537a14a407a..caeafaa13c91fddf7dd3751252e4daf3045dcd2e 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_super_range.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_super_range.S
@@ -1 +1,2 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeSuperRange" }
+%def op_invoke_super_range():
+%  invoke(helper="MterpInvokeSuperRange")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual.S
index 66d050217d5d3d5426129bd443a92cef46300e5c..249177b813d3ffb3300010c511e78ff279b0ce61 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_virtual.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_virtual.S
@@ -1,4 +1,5 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeVirtual" }
+%def op_invoke_virtual():
+%  invoke(helper="MterpInvokeVirtual")
     /*
      * Handle a virtual method call.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S
index 4300c34646d82694b5eabd35dc3629a67146f0c6..ea72c171ecfedd9ddb94bc2e2202e2c56ab11e53 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S
@@ -1 +1,2 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeVirtualQuick" }
+%def op_invoke_virtual_quick():
+%  invoke(helper="MterpInvokeVirtualQuick")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S
index b43955c6d8f891ecab153dbbe715779959b34800..baa077959359e0dcfbfd3b3cd9814c31b3f6d727 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S
@@ -1 +1,2 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeVirtualRange" }
+%def op_invoke_virtual_range():
+%  invoke(helper="MterpInvokeVirtualRange")
diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S
index 90c7b657471fb23013dc215259a0a2c5c0cde741..1d961a0781a94d0087847bce02fcae1f37a75f29 100644
--- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S
@@ -1 +1,2 @@
-%include "arm64/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" }
+%def op_invoke_virtual_range_quick():
+%  invoke(helper="MterpInvokeVirtualQuickRange")
diff --git a/runtime/interpreter/mterp/arm64/op_iput.S b/runtime/interpreter/mterp/arm64/op_iput.S
index 2bc3db9050ca996ce8a756567ee0d5fb5e83605a..e5351baf557fe295afb718387a6de58585ba5184 100644
--- a/runtime/interpreter/mterp/arm64/op_iput.S
+++ b/runtime/interpreter/mterp/arm64/op_iput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIPutU32" }
-%include "arm64/field.S" { }
+%def op_iput(is_object="0", helper="MterpIPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/arm64/op_iput_boolean.S b/runtime/interpreter/mterp/arm64/op_iput_boolean.S
index 12a278ccba3e112b2c2363bda6a9a94d85a0922b..9eb849877b6207d46a36c083b47c83ebbd7e5d00 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_boolean.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_boolean.S
@@ -1 +1,2 @@
-%include "arm64/op_iput.S" { "helper":"MterpIPutU8" }
+%def op_iput_boolean():
+%  op_iput(helper="MterpIPutU8")
diff --git a/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S
index 25c61d7c2e118e278e2189ff1cce6a66e518d584..fd077a7792e25caa03e912c74f1db064ced5b90b 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S
@@ -1 +1,2 @@
-%include "arm64/op_iput_quick.S" { "store":"strb" }
+%def op_iput_boolean_quick():
+%  op_iput_quick(store="strb")
diff --git a/runtime/interpreter/mterp/arm64/op_iput_byte.S b/runtime/interpreter/mterp/arm64/op_iput_byte.S
index 82b99e976547c25d3ad2900260927c19c3bf4efb..4b74f9fb0e3c8bfe5566574fae72b21f71cd2067 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_byte.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_byte.S
@@ -1 +1,2 @@
-%include "arm64/op_iput.S" { "helper":"MterpIPutI8" }
+%def op_iput_byte():
+%  op_iput(helper="MterpIPutI8")
diff --git a/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S b/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S
index 25c61d7c2e118e278e2189ff1cce6a66e518d584..30238cf354ee51a9290acafab6ce7ee0506df51e 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S
@@ -1 +1,2 @@
-%include "arm64/op_iput_quick.S" { "store":"strb" }
+%def op_iput_byte_quick():
+%  op_iput_quick(store="strb")
diff --git a/runtime/interpreter/mterp/arm64/op_iput_char.S b/runtime/interpreter/mterp/arm64/op_iput_char.S
index 427d92d9c0e51076a1a030f0b0df0c22e904ff1a..64a249fc122e7eb749561fbc7ef7b3cc1be67382 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_char.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_char.S
@@ -1 +1,2 @@
-%include "arm64/op_iput.S" { "helper":"MterpIPutU16" }
+%def op_iput_char():
+%  op_iput(helper="MterpIPutU16")
diff --git a/runtime/interpreter/mterp/arm64/op_iput_char_quick.S b/runtime/interpreter/mterp/arm64/op_iput_char_quick.S
index c6ef46ab87a95b617c0c57211c1ae90ada5d7bd6..0deff565030dde3597a48c8a7912bbcd9482d747 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_char_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_char_quick.S
@@ -1 +1,2 @@
-%include "arm64/op_iput_quick.S" { "store":"strh" }
+%def op_iput_char_quick():
+%  op_iput_quick(store="strh")
diff --git a/runtime/interpreter/mterp/arm64/op_iput_object.S b/runtime/interpreter/mterp/arm64/op_iput_object.S
index e9bb93f0a5e59894919afadff4006b419798b194..131edd5dbdae914ae95c3220d01788eba1a7ffb2 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_object.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_object.S
@@ -1 +1,2 @@
-%include "arm64/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" }
+%def op_iput_object():
+%  op_iput(is_object="1", helper="MterpIPutObj")
diff --git a/runtime/interpreter/mterp/arm64/op_iput_object_quick.S b/runtime/interpreter/mterp/arm64/op_iput_object_quick.S
index 6fbf2b1da311d16b84f5d6af9186a69ece98d563..58c10266588638f01be0b50ab70ceaa657acdd0e 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_object_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_object_quick():
     EXPORT_PC
     add     x0, xFP, #OFF_FP_SHADOWFRAME
     mov     x1, xPC
diff --git a/runtime/interpreter/mterp/arm64/op_iput_quick.S b/runtime/interpreter/mterp/arm64/op_iput_quick.S
index e95da76283ff90ef216819bd1b0d396506a8d0dc..1d9910826fc9fe6a3def9e0590025134e8cfe1e9 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_quick.S
@@ -1,4 +1,4 @@
-%default { "store":"str" }
+%def op_iput_quick(store="str"):
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
diff --git a/runtime/interpreter/mterp/arm64/op_iput_short.S b/runtime/interpreter/mterp/arm64/op_iput_short.S
index 67f1ace8bf569840fe7169f592b78a9e980acd74..e631a3b259e969ae8ae1222244d299fd0e4da3d7 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_short.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_short.S
@@ -1 +1,2 @@
-%include "arm64/op_iput.S" { "helper":"MterpIPutI16" }
+%def op_iput_short():
+%  op_iput(helper="MterpIPutI16")
diff --git a/runtime/interpreter/mterp/arm64/op_iput_short_quick.S b/runtime/interpreter/mterp/arm64/op_iput_short_quick.S
index c6ef46ab87a95b617c0c57211c1ae90ada5d7bd6..6a1b65194e1c31c8b0b188470ea8f2eca90c1d58 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_short_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_short_quick.S
@@ -1 +1,2 @@
-%include "arm64/op_iput_quick.S" { "store":"strh" }
+%def op_iput_short_quick():
+%  op_iput_quick(store="strh")
diff --git a/runtime/interpreter/mterp/arm64/op_iput_wide.S b/runtime/interpreter/mterp/arm64/op_iput_wide.S
index e1fafad5a7257771ca250f1eec35ec241d1cc452..2f34fd39f9ed2ca1104582178602a4dac83ee761 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_wide.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_wide.S
@@ -1 +1,2 @@
-%include "arm64/op_iput.S" { "helper":"MterpIPutU64" }
+%def op_iput_wide():
+%  op_iput(helper="MterpIPutU64")
diff --git a/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S b/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S
index 28e831a5f8f438419a41f1abc6a79df7a84b6867..a78918819b044b94bc36cabc7b3f1fafa09a9d8c 100644
--- a/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S
+++ b/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_wide_quick():
     /* iput-wide-quick vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
     FETCH w3, 1                         // w3<- field byte offset
diff --git a/runtime/interpreter/mterp/arm64/op_long_to_double.S b/runtime/interpreter/mterp/arm64/op_long_to_double.S
index a3f59c2048b2d2a30ec6f779b422c2481ebd8725..b1b7b4e694e3e99b642f1a98d0f25cbe110b5d88 100644
--- a/runtime/interpreter/mterp/arm64/op_long_to_double.S
+++ b/runtime/interpreter/mterp/arm64/op_long_to_double.S
@@ -1 +1,2 @@
-%include "arm64/funopWide.S" {"instr":"scvtf d0, x0", "srcreg":"x0", "tgtreg":"d0"}
+%def op_long_to_double():
+%  funopWide(instr="scvtf d0, x0", srcreg="x0", tgtreg="d0")
diff --git a/runtime/interpreter/mterp/arm64/op_long_to_float.S b/runtime/interpreter/mterp/arm64/op_long_to_float.S
index e9c9145cee25ba5fb6276f8ad4440923cd065d8a..424dea09642dd6e4e96bbe027c06da96c693e6c6 100644
--- a/runtime/interpreter/mterp/arm64/op_long_to_float.S
+++ b/runtime/interpreter/mterp/arm64/op_long_to_float.S
@@ -1 +1,2 @@
-%include "arm64/funopNarrower.S" {"instr":"scvtf s0, x0", "srcreg":"x0", "tgtreg":"s0"}
+%def op_long_to_float():
+%  funopNarrower(instr="scvtf s0, x0", srcreg="x0", tgtreg="s0")
diff --git a/runtime/interpreter/mterp/arm64/op_long_to_int.S b/runtime/interpreter/mterp/arm64/op_long_to_int.S
index 73f58d896740e4f6e4c25ae97ab70292a3f51e37..eacb8f59ec402cbb87d740022854981c341e9a09 100644
--- a/runtime/interpreter/mterp/arm64/op_long_to_int.S
+++ b/runtime/interpreter/mterp/arm64/op_long_to_int.S
@@ -1,2 +1,3 @@
+%def op_long_to_int():
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-%include "arm64/op_move.S"
+%  op_move()
diff --git a/runtime/interpreter/mterp/arm64/op_monitor_enter.S b/runtime/interpreter/mterp/arm64/op_monitor_enter.S
index 6fbd9ae725bd681cab619d12a30d4b3cb62c2da7..9d167a25da019a61a6711cfbfe8478157212c294 100644
--- a/runtime/interpreter/mterp/arm64/op_monitor_enter.S
+++ b/runtime/interpreter/mterp/arm64/op_monitor_enter.S
@@ -1,3 +1,4 @@
+%def op_monitor_enter():
     /*
      * Synchronize on an object.
      */
diff --git a/runtime/interpreter/mterp/arm64/op_monitor_exit.S b/runtime/interpreter/mterp/arm64/op_monitor_exit.S
index 26e2d8d7b124c3639fe7eac0eb8b665eb14b9282..985769f15b98bc288335d2aeceeb6b836ffe0f97 100644
--- a/runtime/interpreter/mterp/arm64/op_monitor_exit.S
+++ b/runtime/interpreter/mterp/arm64/op_monitor_exit.S
@@ -1,3 +1,4 @@
+%def op_monitor_exit():
     /*
      * Unlock an object.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_move.S b/runtime/interpreter/mterp/arm64/op_move.S
index 195b7eb62d9f05fb9c221b4dae5175e1758c28e4..d3324f11583c44d573d640f9a7da4c590404ee42 100644
--- a/runtime/interpreter/mterp/arm64/op_move.S
+++ b/runtime/interpreter/mterp/arm64/op_move.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move(is_object="0"):
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     lsr     w1, wINST, #12              // x1<- B from 15:12
diff --git a/runtime/interpreter/mterp/arm64/op_move_16.S b/runtime/interpreter/mterp/arm64/op_move_16.S
index 5146e3d6e701e17eaef666356c4e79f810e4f0f3..0dc862d5df31706899354323758c2175baaf4aa4 100644
--- a/runtime/interpreter/mterp/arm64/op_move_16.S
+++ b/runtime/interpreter/mterp/arm64/op_move_16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_16(is_object="0"):
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     FETCH w1, 2                         // w1<- BBBB
diff --git a/runtime/interpreter/mterp/arm64/op_move_exception.S b/runtime/interpreter/mterp/arm64/op_move_exception.S
index b29298fd1498e0b50f6b8cf504fb1f84b16598d6..2ae5ca898cbd91532dc6c41d52d14408f5b6519d 100644
--- a/runtime/interpreter/mterp/arm64/op_move_exception.S
+++ b/runtime/interpreter/mterp/arm64/op_move_exception.S
@@ -1,3 +1,4 @@
+%def op_move_exception():
     /* move-exception vAA */
     lsr     w2, wINST, #8               // w2<- AA
     ldr     x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
diff --git a/runtime/interpreter/mterp/arm64/op_move_from16.S b/runtime/interpreter/mterp/arm64/op_move_from16.S
index 78f344db6ba17a0d566d11fea28dcef837189b2f..5c7344504d0a0e5c699488ded75e0055b03a623c 100644
--- a/runtime/interpreter/mterp/arm64/op_move_from16.S
+++ b/runtime/interpreter/mterp/arm64/op_move_from16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_from16(is_object="0"):
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     FETCH w1, 1                         // r1<- BBBB
diff --git a/runtime/interpreter/mterp/arm64/op_move_object.S b/runtime/interpreter/mterp/arm64/op_move_object.S
index a5adc59e81d2b89c8ec29c8f57d4d71a8ad40670..dbb4d5971027d54f58728020aadfa71973fb509a 100644
--- a/runtime/interpreter/mterp/arm64/op_move_object.S
+++ b/runtime/interpreter/mterp/arm64/op_move_object.S
@@ -1 +1,2 @@
-%include "arm64/op_move.S" {"is_object":"1"}
+%def op_move_object():
+%  op_move(is_object="1")
diff --git a/runtime/interpreter/mterp/arm64/op_move_object_16.S b/runtime/interpreter/mterp/arm64/op_move_object_16.S
index ef86c4508b40b1d86d5f463dad2c34a182388f89..40120379d51d6027f960ef7742f12d8d16773855 100644
--- a/runtime/interpreter/mterp/arm64/op_move_object_16.S
+++ b/runtime/interpreter/mterp/arm64/op_move_object_16.S
@@ -1 +1,2 @@
-%include "arm64/op_move_16.S" {"is_object":"1"}
+%def op_move_object_16():
+%  op_move_16(is_object="1")
diff --git a/runtime/interpreter/mterp/arm64/op_move_object_from16.S b/runtime/interpreter/mterp/arm64/op_move_object_from16.S
index 0c73b3b045d0d2de31f69a025cadfab6702cd3ba..c82698e81e6805ad74ebe1f6c8c36e3ff3a1bd4b 100644
--- a/runtime/interpreter/mterp/arm64/op_move_object_from16.S
+++ b/runtime/interpreter/mterp/arm64/op_move_object_from16.S
@@ -1 +1,2 @@
-%include "arm64/op_move_from16.S" {"is_object":"1"}
+%def op_move_object_from16():
+%  op_move_from16(is_object="1")
diff --git a/runtime/interpreter/mterp/arm64/op_move_result.S b/runtime/interpreter/mterp/arm64/op_move_result.S
index 06fe96269b6f9d3a4ae38626f05954cb2eb6670f..9c048f05a1c70bd53a505824f80689e005f3d53c 100644
--- a/runtime/interpreter/mterp/arm64/op_move_result.S
+++ b/runtime/interpreter/mterp/arm64/op_move_result.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_result(is_object="0"):
     /* for: move-result, move-result-object */
     /* op vAA */
     lsr     w2, wINST, #8               // r2<- AA
diff --git a/runtime/interpreter/mterp/arm64/op_move_result_object.S b/runtime/interpreter/mterp/arm64/op_move_result_object.S
index da2bbee665282b088061c78f04a327bf15a093e0..87aea2646a6b25bae7ee8970a973915a76557939 100644
--- a/runtime/interpreter/mterp/arm64/op_move_result_object.S
+++ b/runtime/interpreter/mterp/arm64/op_move_result_object.S
@@ -1 +1,2 @@
-%include "arm64/op_move_result.S" {"is_object":"1"}
+%def op_move_result_object():
+%  op_move_result(is_object="1")
diff --git a/runtime/interpreter/mterp/arm64/op_move_result_wide.S b/runtime/interpreter/mterp/arm64/op_move_result_wide.S
index f90a33f01f26a5c530ed0c4a87d9d4d182db5d8d..96347ea2d08e23a02438bb0d1ad171c77a99ecb5 100644
--- a/runtime/interpreter/mterp/arm64/op_move_result_wide.S
+++ b/runtime/interpreter/mterp/arm64/op_move_result_wide.S
@@ -1,3 +1,4 @@
+%def op_move_result_wide():
     /* for: move-result-wide */
     /* op vAA */
     lsr     w2, wINST, #8               // r2<- AA
diff --git a/runtime/interpreter/mterp/arm64/op_move_wide.S b/runtime/interpreter/mterp/arm64/op_move_wide.S
index 538f0797366ba844ea02884995937c0bf94d957a..4576987b90d9d073de8d70915d60a706f986e2e2 100644
--- a/runtime/interpreter/mterp/arm64/op_move_wide.S
+++ b/runtime/interpreter/mterp/arm64/op_move_wide.S
@@ -1,3 +1,4 @@
+%def op_move_wide():
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     lsr     w3, wINST, #12              // w3<- B
diff --git a/runtime/interpreter/mterp/arm64/op_move_wide_16.S b/runtime/interpreter/mterp/arm64/op_move_wide_16.S
index c79cdc50073f6e8ff51f1bd48ac405a06e0af431..09f7a61c55efe3abbd000683e232d9723f8366a2 100644
--- a/runtime/interpreter/mterp/arm64/op_move_wide_16.S
+++ b/runtime/interpreter/mterp/arm64/op_move_wide_16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_16():
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     FETCH w3, 2                         // w3<- BBBB
diff --git a/runtime/interpreter/mterp/arm64/op_move_wide_from16.S b/runtime/interpreter/mterp/arm64/op_move_wide_from16.S
index 70dbe99039353ac3bf3cfbb09e5174d6a93bfa79..6afc20a8c0ca172d8a9454583fec0ee9aa4c9833 100644
--- a/runtime/interpreter/mterp/arm64/op_move_wide_from16.S
+++ b/runtime/interpreter/mterp/arm64/op_move_wide_from16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_from16():
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     FETCH w3, 1                         // w3<- BBBB
diff --git a/runtime/interpreter/mterp/arm64/op_mul_double.S b/runtime/interpreter/mterp/arm64/op_mul_double.S
index 8d35b81b12940518549824ea0d2c8a0197db2eaf..30ca309997fe1ffce62bbb2bb77675e8bbccfd00 100644
--- a/runtime/interpreter/mterp/arm64/op_mul_double.S
+++ b/runtime/interpreter/mterp/arm64/op_mul_double.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"instr":"fmul d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"}
+%def op_mul_double():
+%  binopWide(instr="fmul d0, d1, d2", result="d0", r1="d1", r2="d2")
diff --git a/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S
index 526cb3bccc23214eca30fd6c8c4b01f4b0170943..dedecb5be81bf5974be31d3c38661e4a3d9cd9f9 100644
--- a/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"instr":"fmul     d0, d0, d1", "r0":"d0", "r1":"d1"}
+%def op_mul_double_2addr():
+%  binopWide2addr(instr="fmul     d0, d0, d1", r0="d0", r1="d1")
diff --git a/runtime/interpreter/mterp/arm64/op_mul_float.S b/runtime/interpreter/mterp/arm64/op_mul_float.S
index eea7733dbfce283182aeb1d64f4ae116f9a6a946..3bbbe7305b1202e465452acd3d27423e8aa9423e 100644
--- a/runtime/interpreter/mterp/arm64/op_mul_float.S
+++ b/runtime/interpreter/mterp/arm64/op_mul_float.S
@@ -1 +1,2 @@
-%include "arm64/fbinop.S" {"instr":"fmul   s0, s0, s1"}
+%def op_mul_float():
+%  fbinop(instr="fmul   s0, s0, s1")
diff --git a/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S
index c1f23765aa70df1c21f0c0ce39c3607c412fef6e..035a1fb66286c729920669df68c3888525a1bb26 100644
--- a/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S
@@ -1 +1,2 @@
-%include "arm64/fbinop2addr.S" {"instr":"fmul   s2, s0, s1"}
+%def op_mul_float_2addr():
+%  fbinop2addr(instr="fmul   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm64/op_mul_int.S b/runtime/interpreter/mterp/arm64/op_mul_int.S
index d14cae12e42198483e0f2a405f3046e113c56916..267623d1f5d8c4299cae259d3f09417881e645e0 100644
--- a/runtime/interpreter/mterp/arm64/op_mul_int.S
+++ b/runtime/interpreter/mterp/arm64/op_mul_int.S
@@ -1,2 +1,3 @@
+%def op_mul_int():
 /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */
-%include "arm64/binop.S" {"instr":"mul     w0, w1, w0"}
+%  binop(instr="mul     w0, w1, w0")
diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S
index f079118172239b0ff2b42671eca4ea7b6b479582..c0f533a0c1f828621a821a368b77a45a2cab0988 100644
--- a/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S
@@ -1,2 +1,3 @@
+%def op_mul_int_2addr():
 /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */
-%include "arm64/binop2addr.S" {"instr":"mul     w0, w1, w0"}
+%  binop2addr(instr="mul     w0, w1, w0")
diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S b/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S
index a3785595415f3bea6b5c948b7cea36672aa37d79..d309c8629979ab3137bfddd5dab9b73568e18867 100644
--- a/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S
+++ b/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S
@@ -1,2 +1,3 @@
+%def op_mul_int_lit16():
 /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */
-%include "arm64/binopLit16.S" {"instr":"mul     w0, w1, w0"}
+%  binopLit16(instr="mul     w0, w1, w0")
diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S b/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S
index b3d40141ae0523e6c353289abde1838498e82ffe..b3368416d10e21571a6454d7a046a0280336c1be 100644
--- a/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S
+++ b/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S
@@ -1,2 +1,3 @@
+%def op_mul_int_lit8():
 /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */
-%include "arm64/binopLit8.S" {"instr":"mul     w0, w1, w0"}
+%  binopLit8(instr="mul     w0, w1, w0")
diff --git a/runtime/interpreter/mterp/arm64/op_mul_long.S b/runtime/interpreter/mterp/arm64/op_mul_long.S
index bc0dcbd14b72011210518befe46841d4cdbea9c4..5056c0e4c1aa4d40bffe1b6c36e62523ec31ba5d 100644
--- a/runtime/interpreter/mterp/arm64/op_mul_long.S
+++ b/runtime/interpreter/mterp/arm64/op_mul_long.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"instr":"mul x0, x1, x2"}
+%def op_mul_long():
+%  binopWide(instr="mul x0, x1, x2")
diff --git a/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S
index fa1cdf8a7233edd9d003080ea4bafa6268473813..e69d40aadfc9db4e7d0473d802bdcb67b122e917 100644
--- a/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"instr":"mul     x0, x0, x1"}
+%def op_mul_long_2addr():
+%  binopWide2addr(instr="mul     x0, x0, x1")
diff --git a/runtime/interpreter/mterp/arm64/op_neg_double.S b/runtime/interpreter/mterp/arm64/op_neg_double.S
index d77859d5701f4965b8b2e2afe32da8845d57a10e..a56eff5493bd6ef2213a19e9d9ef927670f915dc 100644
--- a/runtime/interpreter/mterp/arm64/op_neg_double.S
+++ b/runtime/interpreter/mterp/arm64/op_neg_double.S
@@ -1 +1,2 @@
-%include "arm64/unopWide.S" {"instr":"eor     x0, x0, #0x8000000000000000"}
+%def op_neg_double():
+%  unopWide(instr="eor     x0, x0, #0x8000000000000000")
diff --git a/runtime/interpreter/mterp/arm64/op_neg_float.S b/runtime/interpreter/mterp/arm64/op_neg_float.S
index 6652aec0ffe08845ccfb6bd82816c71a24967720..1366168defb4f551729a15cfbad5e75320f5ade8 100644
--- a/runtime/interpreter/mterp/arm64/op_neg_float.S
+++ b/runtime/interpreter/mterp/arm64/op_neg_float.S
@@ -1 +1,2 @@
-%include "arm64/unop.S" {"instr":"eor     w0, w0, #0x80000000"}
+%def op_neg_float():
+%  unop(instr="eor     w0, w0, #0x80000000")
diff --git a/runtime/interpreter/mterp/arm64/op_neg_int.S b/runtime/interpreter/mterp/arm64/op_neg_int.S
index 59c14a9087aad4e21e42a916bfe6c1ca2cff6bb0..be56dd2acacd715aa53879c0d26d0054a124397f 100644
--- a/runtime/interpreter/mterp/arm64/op_neg_int.S
+++ b/runtime/interpreter/mterp/arm64/op_neg_int.S
@@ -1 +1,2 @@
-%include "arm64/unop.S" {"instr":"sub     w0, wzr, w0"}
+%def op_neg_int():
+%  unop(instr="sub     w0, wzr, w0")
diff --git a/runtime/interpreter/mterp/arm64/op_neg_long.S b/runtime/interpreter/mterp/arm64/op_neg_long.S
index 0c71ea7de65e958c4a9cc6dfdc4dc401b37a97a3..eb2882c9a72cff53a124e530ef0f4b54d2977d2a 100644
--- a/runtime/interpreter/mterp/arm64/op_neg_long.S
+++ b/runtime/interpreter/mterp/arm64/op_neg_long.S
@@ -1 +1,2 @@
-%include "arm64/unopWide.S" {"instr":"sub x0, xzr, x0"}
+%def op_neg_long():
+%  unopWide(instr="sub x0, xzr, x0")
diff --git a/runtime/interpreter/mterp/arm64/op_new_array.S b/runtime/interpreter/mterp/arm64/op_new_array.S
index 886120a94ebb98fd4a853ea5e090b4e7effcd1e8..34729a7aeb82444ab6b1c19a6620723d2f619ceb 100644
--- a/runtime/interpreter/mterp/arm64/op_new_array.S
+++ b/runtime/interpreter/mterp/arm64/op_new_array.S
@@ -1,3 +1,4 @@
+%def op_new_array():
     /*
      * Allocate an array of objects, specified with the array class
      * and a count.
diff --git a/runtime/interpreter/mterp/arm64/op_new_instance.S b/runtime/interpreter/mterp/arm64/op_new_instance.S
index c171ac58f6b5c54ef936f7aa16a69a0b0f9081cd..beb1f6e2e00cd43fb1fdaa75fb1f4c0615e052ae 100644
--- a/runtime/interpreter/mterp/arm64/op_new_instance.S
+++ b/runtime/interpreter/mterp/arm64/op_new_instance.S
@@ -1,3 +1,4 @@
+%def op_new_instance():
     /*
      * Create a new instance of a class.
      */
diff --git a/runtime/interpreter/mterp/arm64/op_nop.S b/runtime/interpreter/mterp/arm64/op_nop.S
index 80c2d452f81d3ee6273d875ced07934dd04e05fd..9702c5cd4814287745880402abad66e2c1ba6d39 100644
--- a/runtime/interpreter/mterp/arm64/op_nop.S
+++ b/runtime/interpreter/mterp/arm64/op_nop.S
@@ -1,3 +1,4 @@
+%def op_nop():
     FETCH_ADVANCE_INST 1                // advance to next instr, load rINST
     GET_INST_OPCODE ip                  // ip<- opcode from rINST
     GOTO_OPCODE ip                      // execute it
diff --git a/runtime/interpreter/mterp/arm64/op_not_int.S b/runtime/interpreter/mterp/arm64/op_not_int.S
index 55d77502aa430843b7c71d4ae3caf882c2f09a6b..d2fc20531840c32b84a30bf6c9754919c4766bea 100644
--- a/runtime/interpreter/mterp/arm64/op_not_int.S
+++ b/runtime/interpreter/mterp/arm64/op_not_int.S
@@ -1 +1,2 @@
-%include "arm64/unop.S" {"instr":"mvn     w0, w0"}
+%def op_not_int():
+%  unop(instr="mvn     w0, w0")
diff --git a/runtime/interpreter/mterp/arm64/op_not_long.S b/runtime/interpreter/mterp/arm64/op_not_long.S
index e5ebdd6e65a559a7c9e0810ddd3abe3d76cd0bde..014a60dc406355aea3b1ef7ddfe9b9890dd03692 100644
--- a/runtime/interpreter/mterp/arm64/op_not_long.S
+++ b/runtime/interpreter/mterp/arm64/op_not_long.S
@@ -1 +1,2 @@
-%include "arm64/unopWide.S" {"instr":"mvn     x0, x0"}
+%def op_not_long():
+%  unopWide(instr="mvn     x0, x0")
diff --git a/runtime/interpreter/mterp/arm64/op_or_int.S b/runtime/interpreter/mterp/arm64/op_or_int.S
index 648c1e68503778cfbb40bca20bdefa5c68850b46..8041c6d8053d9a6b66409672d51f2facfb115798 100644
--- a/runtime/interpreter/mterp/arm64/op_or_int.S
+++ b/runtime/interpreter/mterp/arm64/op_or_int.S
@@ -1 +1,2 @@
-%include "arm64/binop.S" {"instr":"orr     w0, w0, w1"}
+%def op_or_int():
+%  binop(instr="orr     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_or_int_2addr.S b/runtime/interpreter/mterp/arm64/op_or_int_2addr.S
index abdf599fe9372f08e609cc84e0937dad0ce31039..918c5233ee1608f8e420622c053b949e50a7b064 100644
--- a/runtime/interpreter/mterp/arm64/op_or_int_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_or_int_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binop2addr.S" {"instr":"orr     w0, w0, w1"}
+%def op_or_int_2addr():
+%  binop2addr(instr="orr     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_or_int_lit16.S b/runtime/interpreter/mterp/arm64/op_or_int_lit16.S
index db7f4ffb0a92f693634f25f3500047e08a2eaef5..dda068bbbf96a886c2bada4499a4e38e60aa41cd 100644
--- a/runtime/interpreter/mterp/arm64/op_or_int_lit16.S
+++ b/runtime/interpreter/mterp/arm64/op_or_int_lit16.S
@@ -1 +1,2 @@
-%include "arm64/binopLit16.S" {"instr":"orr     w0, w0, w1"}
+%def op_or_int_lit16():
+%  binopLit16(instr="orr     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_or_int_lit8.S b/runtime/interpreter/mterp/arm64/op_or_int_lit8.S
index 7cb26b7796039df60ec169657d6140123aca5552..0fe6122e7959ec58e3995446ee3aa6d25a1bda73 100644
--- a/runtime/interpreter/mterp/arm64/op_or_int_lit8.S
+++ b/runtime/interpreter/mterp/arm64/op_or_int_lit8.S
@@ -1 +1,2 @@
-%include "arm64/binopLit8.S" {"extract":"", "instr":"orr     w0, w0, w3, asr #8"}
+%def op_or_int_lit8():
+%  binopLit8(extract="", instr="orr     w0, w0, w3, asr #8")
diff --git a/runtime/interpreter/mterp/arm64/op_or_long.S b/runtime/interpreter/mterp/arm64/op_or_long.S
index dd137ce85b76ba62116d997d817b48232a9aecbb..f434d3fae9a6a7f40640d06b4e8a0b44ef786ab1 100644
--- a/runtime/interpreter/mterp/arm64/op_or_long.S
+++ b/runtime/interpreter/mterp/arm64/op_or_long.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"instr":"orr x0, x1, x2"}
+%def op_or_long():
+%  binopWide(instr="orr x0, x1, x2")
diff --git a/runtime/interpreter/mterp/arm64/op_or_long_2addr.S b/runtime/interpreter/mterp/arm64/op_or_long_2addr.S
index f785230e1c53c71daebe533d4b639561f8b7cd41..4186ce9ef9bc08b05f6c1aa0f1899321a174ab32 100644
--- a/runtime/interpreter/mterp/arm64/op_or_long_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_or_long_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"instr":"orr     x0, x0, x1"}
+%def op_or_long_2addr():
+%  binopWide2addr(instr="orr     x0, x0, x1")
diff --git a/runtime/interpreter/mterp/arm64/op_packed_switch.S b/runtime/interpreter/mterp/arm64/op_packed_switch.S
index 408e03069b5aaa13e52bed9caec2f067e2e931e3..9e4eb9bd37d08bf9160e0fde36b012603a9daaef 100644
--- a/runtime/interpreter/mterp/arm64/op_packed_switch.S
+++ b/runtime/interpreter/mterp/arm64/op_packed_switch.S
@@ -1,4 +1,4 @@
-%default { "func":"MterpDoPackedSwitch" }
+%def op_packed_switch(func="MterpDoPackedSwitch"):
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
diff --git a/runtime/interpreter/mterp/arm64/op_rem_double.S b/runtime/interpreter/mterp/arm64/op_rem_double.S
index c631ddbfe591378158008d424b385921730f239a..3d43467e63b66a45a74d8b3c36bceae170dbb853 100644
--- a/runtime/interpreter/mterp/arm64/op_rem_double.S
+++ b/runtime/interpreter/mterp/arm64/op_rem_double.S
@@ -1,3 +1,4 @@
+%def op_rem_double():
     /* rem vAA, vBB, vCC */
     FETCH w0, 1                         // w0<- CCBB
     lsr     w2, w0, #8                  // w2<- CC
diff --git a/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S
index 9868f4123aef727a7975be301dddfc6dcb8433e1..179886d46b2f591eeee75e3f17cb121c550b08f6 100644
--- a/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S
@@ -1,3 +1,4 @@
+%def op_rem_double_2addr():
     /* rem vA, vB */
     lsr     w1, wINST, #12              // w1<- B
     ubfx    w2, wINST, #8, #4           // w2<- A
diff --git a/runtime/interpreter/mterp/arm64/op_rem_float.S b/runtime/interpreter/mterp/arm64/op_rem_float.S
index 73f7060cf547fd32c1985b20fb90477e04207c09..29241e5722bf1007272f59f6b863a5594f1eae95 100644
--- a/runtime/interpreter/mterp/arm64/op_rem_float.S
+++ b/runtime/interpreter/mterp/arm64/op_rem_float.S
@@ -1,2 +1,3 @@
+%def op_rem_float():
 /* EABI doesn't define a float remainder function, but libm does */
-%include "arm64/fbinop.S" {"instr":"bl      fmodf"}
+%  fbinop(instr="bl      fmodf")
diff --git a/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S
index 95f81c5a237dd24e5df92f63f7bfb4c4aaa0323a..49bf8ea320f06d8d4b3bbd17973d0b0396a1f6ef 100644
--- a/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S
@@ -1,3 +1,4 @@
+%def op_rem_float_2addr():
     /* rem vA, vB */
     lsr     w3, wINST, #12              // w3<- B
     ubfx    w9, wINST, #8, #4           // w9<- A
diff --git a/runtime/interpreter/mterp/arm64/op_rem_int.S b/runtime/interpreter/mterp/arm64/op_rem_int.S
index dd9dfda0883c9e63829f656c8f209cb8a1702477..6f2f999f3ff024f9453d11ad9bad306d8dd9c1d4 100644
--- a/runtime/interpreter/mterp/arm64/op_rem_int.S
+++ b/runtime/interpreter/mterp/arm64/op_rem_int.S
@@ -1 +1,2 @@
-%include "arm64/binop.S" {"preinstr":"sdiv     w2, w0, w1", "instr":"msub w0, w2, w1, w0", "chkzero":"1"}
+%def op_rem_int():
+%  binop(preinstr="sdiv     w2, w0, w1", instr="msub w0, w2, w1, w0", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S
index 57fc4971b9fb87dfd0b2b775099a44c31930ba8d..dc46b2feb45a28db7fd1580cbcfcdda361c94bc8 100644
--- a/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binop2addr.S" {"preinstr":"sdiv     w2, w0, w1", "instr":"msub w0, w2, w1, w0", "chkzero":"1"}
+%def op_rem_int_2addr():
+%  binop2addr(preinstr="sdiv     w2, w0, w1", instr="msub w0, w2, w1, w0", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S b/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S
index b51a739d2e7bb1264390a1cf4989951fe9d0f6e1..75be3343baaff6281ae679c871313d8c4014dbde 100644
--- a/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S
+++ b/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S
@@ -1 +1,2 @@
-%include "arm64/binopLit16.S" {"preinstr":"sdiv w3, w0, w1", "instr":"msub w0, w3, w1, w0", "chkzero":"1"}
+%def op_rem_int_lit16():
+%  binopLit16(preinstr="sdiv w3, w0, w1", instr="msub w0, w3, w1, w0", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S b/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S
index 03ea32420b4a631ef509688df549062875d94e82..c5fef4be0195488e92f5ddae0f4f429e16335231 100644
--- a/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S
+++ b/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S
@@ -1 +1,2 @@
-%include "arm64/binopLit8.S" {"preinstr":"sdiv w3, w0, w1", "instr":"msub w0, w3, w1, w0", "chkzero":"1"}
+%def op_rem_int_lit8():
+%  binopLit8(preinstr="sdiv w3, w0, w1", instr="msub w0, w3, w1, w0", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_rem_long.S b/runtime/interpreter/mterp/arm64/op_rem_long.S
index f133f86a6cc190506950b51edc2db96bd5fc18af..31dd6bec52ff62754332431fabb2bf600f069a9c 100644
--- a/runtime/interpreter/mterp/arm64/op_rem_long.S
+++ b/runtime/interpreter/mterp/arm64/op_rem_long.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"preinstr":"sdiv x3, x1, x2","instr":"msub x0, x3, x2, x1", "chkzero":"1"}
+%def op_rem_long():
+%  binopWide(preinstr="sdiv x3, x1, x2", instr="msub x0, x3, x2, x1", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S
index b45e2a95c19495ea59aca960e8e7d2d61937f215..b30ef674b37b1fc64ec53a65ae6627433db29069 100644
--- a/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"preinstr":"sdiv x3, x0, x1", "instr":"msub x0, x3, x1, x0", "chkzero":"1"}
+%def op_rem_long_2addr():
+%  binopWide2addr(preinstr="sdiv x3, x0, x1", instr="msub x0, x3, x1, x0", chkzero="1")
diff --git a/runtime/interpreter/mterp/arm64/op_return.S b/runtime/interpreter/mterp/arm64/op_return.S
index 9f125c7fef5e7ea80a9465447fe9c87f29e3bb36..eedae64d4e2388a222cc4f32e7421538b0645a54 100644
--- a/runtime/interpreter/mterp/arm64/op_return.S
+++ b/runtime/interpreter/mterp/arm64/op_return.S
@@ -1,3 +1,4 @@
+%def op_return():
     /*
      * Return a 32-bit value.
      *
diff --git a/runtime/interpreter/mterp/arm64/op_return_object.S b/runtime/interpreter/mterp/arm64/op_return_object.S
index b6cb532b53140913d14aeab6c5a71552d4b0542b..2eeec0b94824884ff1b3c0aeccbfa0948268f9ab 100644
--- a/runtime/interpreter/mterp/arm64/op_return_object.S
+++ b/runtime/interpreter/mterp/arm64/op_return_object.S
@@ -1 +1,2 @@
-%include "arm64/op_return.S"
+%def op_return_object():
+%  op_return()
diff --git a/runtime/interpreter/mterp/arm64/op_return_void.S b/runtime/interpreter/mterp/arm64/op_return_void.S
index b2530062e8a32669db15a79cefb1010c4457e833..6962bb21d011d9eab3c1af8b4389f6af0726a093 100644
--- a/runtime/interpreter/mterp/arm64/op_return_void.S
+++ b/runtime/interpreter/mterp/arm64/op_return_void.S
@@ -1,3 +1,4 @@
+%def op_return_void():
     .extern MterpThreadFenceForConstructor
     bl      MterpThreadFenceForConstructor
     ldr     w7, [xSELF, #THREAD_FLAGS_OFFSET]
diff --git a/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S
index c8171690705e6bdd2b69972668356c48c91ac92f..8d872d1faa878356164a0028d693c4cb43db212c 100644
--- a/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S
+++ b/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S
@@ -1,3 +1,4 @@
+%def op_return_void_no_barrier():
     ldr     w7, [xSELF, #THREAD_FLAGS_OFFSET]
     mov     x0, xSELF
     ands    w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
diff --git a/runtime/interpreter/mterp/arm64/op_return_wide.S b/runtime/interpreter/mterp/arm64/op_return_wide.S
index c47661cd5471cc768de61896fe5b9909a78ac8af..5d31c6a5ab1ee548599959a0bec500e4458e3cdd 100644
--- a/runtime/interpreter/mterp/arm64/op_return_wide.S
+++ b/runtime/interpreter/mterp/arm64/op_return_wide.S
@@ -1,3 +1,4 @@
+%def op_return_wide():
     /*
      * Return a 64-bit value.
      */
diff --git a/runtime/interpreter/mterp/arm64/op_rsub_int.S b/runtime/interpreter/mterp/arm64/op_rsub_int.S
index 3bf45fe654edef5b2a994bada553a7f3ed4d1804..dc2342d018b28dffd8192fb438385d2d958e3b0d 100644
--- a/runtime/interpreter/mterp/arm64/op_rsub_int.S
+++ b/runtime/interpreter/mterp/arm64/op_rsub_int.S
@@ -1,2 +1,3 @@
+%def op_rsub_int():
 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
-%include "arm64/binopLit16.S" {"instr":"sub     w0, w1, w0"}
+%  binopLit16(instr="sub     w0, w1, w0")
diff --git a/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S
index 7a3572b364b7d1c11f14355d5b7516fa37b3df37..51a48fb9bd6f87be1703507ffdcb81e831143133 100644
--- a/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S
+++ b/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S
@@ -1 +1,2 @@
-%include "arm64/binopLit8.S" {"instr":"sub     w0, w1, w0"}
+%def op_rsub_int_lit8():
+%  binopLit8(instr="sub     w0, w1, w0")
diff --git a/runtime/interpreter/mterp/arm64/op_sget.S b/runtime/interpreter/mterp/arm64/op_sget.S
index 78e95b2e7c6d40f3cf4842192d45d14d72c748f1..8a6a66ab6032f5a140fcaa4cb0f85af9cb84bd7a 100644
--- a/runtime/interpreter/mterp/arm64/op_sget.S
+++ b/runtime/interpreter/mterp/arm64/op_sget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSGetU32" }
-%include "arm64/field.S" { }
+%def op_sget(is_object="0", helper="MterpSGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/arm64/op_sget_boolean.S b/runtime/interpreter/mterp/arm64/op_sget_boolean.S
index 0cf9f09681ddcb4e099f2a54ad65ae66bbe3f8b8..d9c12c9b280100ec8c517e2c264d9c99022bb429 100644
--- a/runtime/interpreter/mterp/arm64/op_sget_boolean.S
+++ b/runtime/interpreter/mterp/arm64/op_sget_boolean.S
@@ -1 +1,2 @@
-%include "arm64/op_sget.S" {"helper":"MterpSGetU8"}
+%def op_sget_boolean():
+%  op_sget(helper="MterpSGetU8")
diff --git a/runtime/interpreter/mterp/arm64/op_sget_byte.S b/runtime/interpreter/mterp/arm64/op_sget_byte.S
index 7c88a81faa58c57624fca81a59421b58a6169b6a..37c6879cd4b02e1fe323434a8f0e490352d4d391 100644
--- a/runtime/interpreter/mterp/arm64/op_sget_byte.S
+++ b/runtime/interpreter/mterp/arm64/op_sget_byte.S
@@ -1 +1,2 @@
-%include "arm64/op_sget.S" {"helper":"MterpSGetI8"}
+%def op_sget_byte():
+%  op_sget(helper="MterpSGetI8")
diff --git a/runtime/interpreter/mterp/arm64/op_sget_char.S b/runtime/interpreter/mterp/arm64/op_sget_char.S
index 883e944ce5f3728df08d58204cfc3c8386984186..003bcd16833da0b4c77b8ef60e71ee9bbb01e8da 100644
--- a/runtime/interpreter/mterp/arm64/op_sget_char.S
+++ b/runtime/interpreter/mterp/arm64/op_sget_char.S
@@ -1 +1,2 @@
-%include "arm64/op_sget.S" {"helper":"MterpSGetU16"}
+%def op_sget_char():
+%  op_sget(helper="MterpSGetU16")
diff --git a/runtime/interpreter/mterp/arm64/op_sget_object.S b/runtime/interpreter/mterp/arm64/op_sget_object.S
index 69d6adb54972da322866bcd476ccd79ee7723bd8..7cf3597f44f59b999d828d0749f53401e98cfee6 100644
--- a/runtime/interpreter/mterp/arm64/op_sget_object.S
+++ b/runtime/interpreter/mterp/arm64/op_sget_object.S
@@ -1 +1,2 @@
-%include "arm64/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"}
+%def op_sget_object():
+%  op_sget(is_object="1", helper="MterpSGetObj")
diff --git a/runtime/interpreter/mterp/arm64/op_sget_short.S b/runtime/interpreter/mterp/arm64/op_sget_short.S
index 6cb918433d31d75c9fc0b17c8d568fdee2526700..afacb578d90caf9455c969edfe13663d0927cb03 100644
--- a/runtime/interpreter/mterp/arm64/op_sget_short.S
+++ b/runtime/interpreter/mterp/arm64/op_sget_short.S
@@ -1 +1,2 @@
-%include "arm64/op_sget.S" {"helper":"MterpSGetI16"}
+%def op_sget_short():
+%  op_sget(helper="MterpSGetI16")
diff --git a/runtime/interpreter/mterp/arm64/op_sget_wide.S b/runtime/interpreter/mterp/arm64/op_sget_wide.S
index f5d182e96d07e55cf0d891a15ac79daabe996e12..fff2be6945510278d990141764285ab694e302ed 100644
--- a/runtime/interpreter/mterp/arm64/op_sget_wide.S
+++ b/runtime/interpreter/mterp/arm64/op_sget_wide.S
@@ -1 +1,2 @@
-%include "arm64/op_sget.S" {"helper":"MterpSGetU64"}
+%def op_sget_wide():
+%  op_sget(helper="MterpSGetU64")
diff --git a/runtime/interpreter/mterp/arm64/op_shl_int.S b/runtime/interpreter/mterp/arm64/op_shl_int.S
index 3062a3fad87e13069ac6e17f9cd56dc43f670463..673d4a0a7437a9cdb2d2523496e8c9e43d98375c 100644
--- a/runtime/interpreter/mterp/arm64/op_shl_int.S
+++ b/runtime/interpreter/mterp/arm64/op_shl_int.S
@@ -1 +1,2 @@
-%include "arm64/binop.S" {"instr":"lsl     w0, w0, w1"}
+%def op_shl_int():
+%  binop(instr="lsl     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S b/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S
index 9a7e09f016e605cf8ca045be12ed689ec834cfb7..f4c2f8ceca031b0df82c989edde5aeb94290d463 100644
--- a/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binop2addr.S" {"instr":"lsl     w0, w0, w1"}
+%def op_shl_int_2addr():
+%  binop2addr(instr="lsl     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S b/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S
index 9c19b55550af21620b4358712fc23f1cf3a7f83f..38f3f8edcba6a420f2f687bc74442c2a00fe1521 100644
--- a/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S
+++ b/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S
@@ -1 +1,2 @@
-%include "arm64/binopLit8.S" {"extract":"ubfx    w1, w3, #8, #5", "instr":"lsl     w0, w0, w1"}
+%def op_shl_int_lit8():
+%  binopLit8(extract="ubfx    w1, w3, #8, #5", instr="lsl     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_shl_long.S b/runtime/interpreter/mterp/arm64/op_shl_long.S
index bbf96009539974c1868f6aaf9f16b3fa2526c04b..c56b59fb3c831b1b38303388d83981cf505bc177 100644
--- a/runtime/interpreter/mterp/arm64/op_shl_long.S
+++ b/runtime/interpreter/mterp/arm64/op_shl_long.S
@@ -1 +1,2 @@
-%include "arm64/shiftWide.S" {"opcode":"lsl"}
+%def op_shl_long():
+%  shiftWide(opcode="lsl")
diff --git a/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S b/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S
index a5c4013bf74fa2405a777a4150076436d98716dd..ed10db2fd8f48642d952a4533b28e265afdeaa10 100644
--- a/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S
@@ -1 +1,2 @@
-%include "arm64/shiftWide2addr.S" {"opcode":"lsl"}
+%def op_shl_long_2addr():
+%  shiftWide2addr(opcode="lsl")
diff --git a/runtime/interpreter/mterp/arm64/op_shr_int.S b/runtime/interpreter/mterp/arm64/op_shr_int.S
index 493b7407f7b4a248fd1e1da8f17dc98062223b1f..9dab83d5534560974e0cfda5c21fae04d603568b 100644
--- a/runtime/interpreter/mterp/arm64/op_shr_int.S
+++ b/runtime/interpreter/mterp/arm64/op_shr_int.S
@@ -1 +1,2 @@
-%include "arm64/binop.S" {"instr":"asr     w0, w0, w1"}
+%def op_shr_int():
+%  binop(instr="asr     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S b/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S
index 6efe8ee010c5dc338aea75cad94dc42f37d950ca..8bdcc11b702f9e16a6475e5b69c2401b6dbcf9a7 100644
--- a/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binop2addr.S" {"instr":"asr     w0, w0, w1"}
+%def op_shr_int_2addr():
+%  binop2addr(instr="asr     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S b/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S
index c7b61df13d58f9d724628a7ecf53283be1e9dc2b..7f58bca4e9d4823351f4bb8c902c8dccf276fce3 100644
--- a/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S
+++ b/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S
@@ -1 +1,2 @@
-%include "arm64/binopLit8.S" {"extract":"ubfx    w1, w3, #8, #5", "instr":"asr     w0, w0, w1"}
+%def op_shr_int_lit8():
+%  binopLit8(extract="ubfx    w1, w3, #8, #5", instr="asr     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_shr_long.S b/runtime/interpreter/mterp/arm64/op_shr_long.S
index 4d332359abb41d7669e2f57f7f224234f5110e83..fcaf0ec45dee4e4240af78be951491df4e69c721 100644
--- a/runtime/interpreter/mterp/arm64/op_shr_long.S
+++ b/runtime/interpreter/mterp/arm64/op_shr_long.S
@@ -1 +1,2 @@
-%include "arm64/shiftWide.S" {"opcode":"asr"}
+%def op_shr_long():
+%  shiftWide(opcode="asr")
diff --git a/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S b/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S
index 0a4a386c9552e7498257b908ace1c839a175cb90..359778ab5350d882b1ac05c66cc50244fd07cf97 100644
--- a/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S
@@ -1 +1,2 @@
-%include "arm64/shiftWide2addr.S" {"opcode":"asr"}
+%def op_shr_long_2addr():
+%  shiftWide2addr(opcode="asr")
diff --git a/runtime/interpreter/mterp/arm64/op_sparse_switch.S b/runtime/interpreter/mterp/arm64/op_sparse_switch.S
index 5a8d7489bc662bc7e67d010a9486abec0503c316..b74d7da81633f307dbf7c07ffaada2d14f131ec3 100644
--- a/runtime/interpreter/mterp/arm64/op_sparse_switch.S
+++ b/runtime/interpreter/mterp/arm64/op_sparse_switch.S
@@ -1 +1,2 @@
-%include "arm64/op_packed_switch.S" { "func":"MterpDoSparseSwitch" }
+%def op_sparse_switch():
+%  op_packed_switch(func="MterpDoSparseSwitch")
diff --git a/runtime/interpreter/mterp/arm64/op_sput.S b/runtime/interpreter/mterp/arm64/op_sput.S
index d229d0d8994e5daf43a3f06efdaea37c9b2a267d..cbd6ee96d345758221edb4c7f71dd2dda57ac8f0 100644
--- a/runtime/interpreter/mterp/arm64/op_sput.S
+++ b/runtime/interpreter/mterp/arm64/op_sput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSPutU32"}
-%include "arm64/field.S" { }
+%def op_sput(is_object="0", helper="MterpSPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/arm64/op_sput_boolean.S b/runtime/interpreter/mterp/arm64/op_sput_boolean.S
index 3d0c7c02621ddd21addb7331b94948d2de8b1774..36fba8448b478323ce47a26f2a4d79accbf9964d 100644
--- a/runtime/interpreter/mterp/arm64/op_sput_boolean.S
+++ b/runtime/interpreter/mterp/arm64/op_sput_boolean.S
@@ -1 +1,2 @@
-%include "arm64/op_sput.S" {"helper":"MterpSPutU8"}
+%def op_sput_boolean():
+%  op_sput(helper="MterpSPutU8")
diff --git a/runtime/interpreter/mterp/arm64/op_sput_byte.S b/runtime/interpreter/mterp/arm64/op_sput_byte.S
index 489cf92149d87cfcfd1b450aa6da342b3eb44f8c..84ad4a0ff86ccfcd1159672dac902ee99cfc37d9 100644
--- a/runtime/interpreter/mterp/arm64/op_sput_byte.S
+++ b/runtime/interpreter/mterp/arm64/op_sput_byte.S
@@ -1 +1,2 @@
-%include "arm64/op_sput.S" {"helper":"MterpSPutI8"}
+%def op_sput_byte():
+%  op_sput(helper="MterpSPutI8")
diff --git a/runtime/interpreter/mterp/arm64/op_sput_char.S b/runtime/interpreter/mterp/arm64/op_sput_char.S
index f79d311c1783954be8d5fc5acedaa95a717d4acf..9b8eeba578f555750ab9497c8fc21ce4a52e8b89 100644
--- a/runtime/interpreter/mterp/arm64/op_sput_char.S
+++ b/runtime/interpreter/mterp/arm64/op_sput_char.S
@@ -1 +1,2 @@
-%include "arm64/op_sput.S" {"helper":"MterpSPutU16"}
+%def op_sput_char():
+%  op_sput(helper="MterpSPutU16")
diff --git a/runtime/interpreter/mterp/arm64/op_sput_object.S b/runtime/interpreter/mterp/arm64/op_sput_object.S
index 536f1b16b8cd5ff4af178c56d49add8ba5fb020b..081360c40fb12c03e3a48c24a3677ee55a609758 100644
--- a/runtime/interpreter/mterp/arm64/op_sput_object.S
+++ b/runtime/interpreter/mterp/arm64/op_sput_object.S
@@ -1 +1,2 @@
-%include "arm64/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"}
+%def op_sput_object():
+%  op_sput(is_object="1", helper="MterpSPutObj")
diff --git a/runtime/interpreter/mterp/arm64/op_sput_short.S b/runtime/interpreter/mterp/arm64/op_sput_short.S
index 06482cd7a003c60bafecb858ce117f2cdfc333e0..ee16513486189f1a65fe9922285fe9ae08606b97 100644
--- a/runtime/interpreter/mterp/arm64/op_sput_short.S
+++ b/runtime/interpreter/mterp/arm64/op_sput_short.S
@@ -1 +1,2 @@
-%include "arm64/op_sput.S" {"helper":"MterpSPutI16"}
+%def op_sput_short():
+%  op_sput(helper="MterpSPutI16")
diff --git a/runtime/interpreter/mterp/arm64/op_sput_wide.S b/runtime/interpreter/mterp/arm64/op_sput_wide.S
index b4be6b29877933cc94c73440d8f56fd0ab3de17f..44c1a188edf6bb3cf29011f1b361701ae71aaf9c 100644
--- a/runtime/interpreter/mterp/arm64/op_sput_wide.S
+++ b/runtime/interpreter/mterp/arm64/op_sput_wide.S
@@ -1 +1,2 @@
-%include "arm64/op_sput.S" {"helper":"MterpSPutU64"}
+%def op_sput_wide():
+%  op_sput(helper="MterpSPutU64")
diff --git a/runtime/interpreter/mterp/arm64/op_sub_double.S b/runtime/interpreter/mterp/arm64/op_sub_double.S
index e8e3401e17a2b07d1d6f19481e4d3ed93ac425f2..cca75564dad41e2890bebb583e5a524d2b34cfdf 100644
--- a/runtime/interpreter/mterp/arm64/op_sub_double.S
+++ b/runtime/interpreter/mterp/arm64/op_sub_double.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"instr":"fsub d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"}
+%def op_sub_double():
+%  binopWide(instr="fsub d0, d1, d2", result="d0", r1="d1", r2="d2")
diff --git a/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S
index ddab55e9fe13b0b9f7f6a703e785da7d28999745..6d425fc29dd95478a1121e04fac7a5d6e5161200 100644
--- a/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"instr":"fsub     d0, d0, d1", "r0":"d0", "r1":"d1"}
+%def op_sub_double_2addr():
+%  binopWide2addr(instr="fsub     d0, d0, d1", r0="d0", r1="d1")
diff --git a/runtime/interpreter/mterp/arm64/op_sub_float.S b/runtime/interpreter/mterp/arm64/op_sub_float.S
index 227b15fdf3719cc5ec33cbcf5d602fc3642d8668..e1c469b95c950735d620639c2253ce50dc4daa8a 100644
--- a/runtime/interpreter/mterp/arm64/op_sub_float.S
+++ b/runtime/interpreter/mterp/arm64/op_sub_float.S
@@ -1 +1,2 @@
-%include "arm64/fbinop.S" {"instr":"fsub   s0, s0, s1"}
+%def op_sub_float():
+%  fbinop(instr="fsub   s0, s0, s1")
diff --git a/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S
index 19ac8d56162bbbd8232b5eb5bc048dabe37dcf7e..91b8346985cc777c39791c7e1410ac70cca792a5 100644
--- a/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S
@@ -1 +1,2 @@
-%include "arm64/fbinop2addr.S" {"instr":"fsub   s2, s0, s1"}
+%def op_sub_float_2addr():
+%  fbinop2addr(instr="fsub   s2, s0, s1")
diff --git a/runtime/interpreter/mterp/arm64/op_sub_int.S b/runtime/interpreter/mterp/arm64/op_sub_int.S
index 0e7ce0e6e57e197cc2db7991df97f919c4fd1cb1..895146324b0ee828b0b5e87f2b2903dad93569c9 100644
--- a/runtime/interpreter/mterp/arm64/op_sub_int.S
+++ b/runtime/interpreter/mterp/arm64/op_sub_int.S
@@ -1 +1,2 @@
-%include "arm64/binop.S" {"instr":"sub     w0, w0, w1"}
+%def op_sub_int():
+%  binop(instr="sub     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S
index d2c1bd307aadf90b07d15eb6a81d59bc3a19302e..a450ce499cd82497cdb0b723557816c091588ab5 100644
--- a/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binop2addr.S" {"instr":"sub     w0, w0, w1"}
+%def op_sub_int_2addr():
+%  binop2addr(instr="sub     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_sub_long.S b/runtime/interpreter/mterp/arm64/op_sub_long.S
index 263c70d6e7fc7c0b3cd0a7a4f67b656cf0a82284..696e79a77ffe54d3d39786d3881d74a82d86c283 100644
--- a/runtime/interpreter/mterp/arm64/op_sub_long.S
+++ b/runtime/interpreter/mterp/arm64/op_sub_long.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"instr":"sub x0, x1, x2"}
+%def op_sub_long():
+%  binopWide(instr="sub x0, x1, x2")
diff --git a/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S
index 5be3772670f3db4ba0b33c5309b42593b1ce54db..a6224516691868d455e1d9e7890a48fa031df188 100644
--- a/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"instr":"sub     x0, x0, x1"}
+%def op_sub_long_2addr():
+%  binopWide2addr(instr="sub     x0, x0, x1")
diff --git a/runtime/interpreter/mterp/arm64/op_throw.S b/runtime/interpreter/mterp/arm64/op_throw.S
index 9a951af30207b3a5ad8881a71542b9805dafeff8..ed5a19effd1cbc1b382b281820e4bb53a120455f 100644
--- a/runtime/interpreter/mterp/arm64/op_throw.S
+++ b/runtime/interpreter/mterp/arm64/op_throw.S
@@ -1,3 +1,4 @@
+%def op_throw():
     /*
      * Throw an exception object in the current thread.
      */
diff --git a/runtime/interpreter/mterp/arm64/op_unused_3e.S b/runtime/interpreter/mterp/arm64/op_unused_3e.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..d889f1a5fb4be366ce5101882ae40577a9b0b90b 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_3e.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_3e.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_3e():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_3f.S b/runtime/interpreter/mterp/arm64/op_unused_3f.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..b3ebcfaeaa402ba263610b3f305daf92cc23bebb 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_3f.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_3f.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_3f():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_40.S b/runtime/interpreter/mterp/arm64/op_unused_40.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..7920fb350f2f93b310d33ec19166b6b8445bb0eb 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_40.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_40.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_40():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_41.S b/runtime/interpreter/mterp/arm64/op_unused_41.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..5ed03b85065e78c670f3d26c62b6c56f58338d44 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_41.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_41.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_41():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_42.S b/runtime/interpreter/mterp/arm64/op_unused_42.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..ac32521add543fb2f858aa858af6c3d5594f187e 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_42.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_42.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_42():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_43.S b/runtime/interpreter/mterp/arm64/op_unused_43.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..33e2aa10f8bec8407ff8090cfd81dda49b2a19b8 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_43.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_43.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_43():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_73.S b/runtime/interpreter/mterp/arm64/op_unused_73.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..e3267a30a120e465d19d0a578e37174df1bf8e21 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_73.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_73.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_73():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_79.S b/runtime/interpreter/mterp/arm64/op_unused_79.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..3c6dafc7898855a1034ff93b17bed71a07df1e51 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_79.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_79.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_79():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_7a.S b/runtime/interpreter/mterp/arm64/op_unused_7a.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..9c03cd55355a41369dc85dbea7e07e7bd8e96383 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_7a.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_7a.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_7a():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_f3.S b/runtime/interpreter/mterp/arm64/op_unused_f3.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..ab10b78be2a0b681652d52185cf7c39d3403a41e 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_f3.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_f3.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_f3():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_f4.S b/runtime/interpreter/mterp/arm64/op_unused_f4.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..09229d6d99f58a24b923c56b2937662a10e16de6 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_f4.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_f4.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_f4():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_f5.S b/runtime/interpreter/mterp/arm64/op_unused_f5.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0d6149b5fd6eeb0221067adb660d453080ba1fd2 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_f5.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_f5.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_f5():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_f6.S b/runtime/interpreter/mterp/arm64/op_unused_f6.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..117b03de6d321ace7f917fe69b79b9f182081e11 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_f6.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_f6.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_f6():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_f7.S b/runtime/interpreter/mterp/arm64/op_unused_f7.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..4e3a0f3c9a6eef078506555805a72056272abfc1 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_f7.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_f7.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_f7():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_f8.S b/runtime/interpreter/mterp/arm64/op_unused_f8.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..d1220752d7b5b191c0712bf975e90ac7777e4303 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_f8.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_f8.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_f8():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_f9.S b/runtime/interpreter/mterp/arm64/op_unused_f9.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..7d09a0ebcfce77f4a1bd8b19865ac5d782e382dd 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_f9.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_f9.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_f9():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_fc.S b/runtime/interpreter/mterp/arm64/op_unused_fc.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..06978191ebbcceb51b9820b3e650a0baf767a507 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_fc.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_fc.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_fc():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_unused_fd.S b/runtime/interpreter/mterp/arm64/op_unused_fd.S
index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..4bc2b4bdb6516467406cb88476e1d993a3f0c749 100644
--- a/runtime/interpreter/mterp/arm64/op_unused_fd.S
+++ b/runtime/interpreter/mterp/arm64/op_unused_fd.S
@@ -1 +1,2 @@
-%include "arm64/unused.S"
+%def op_unused_fd():
+%  unused()
diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int.S b/runtime/interpreter/mterp/arm64/op_ushr_int.S
index 005452b5540c6824adb8bfb53af58173e60468a8..5f6ad2d8fdcf69a87e65524ab482b9f29bc8d498 100644
--- a/runtime/interpreter/mterp/arm64/op_ushr_int.S
+++ b/runtime/interpreter/mterp/arm64/op_ushr_int.S
@@ -1 +1,2 @@
-%include "arm64/binop.S" {"instr":"lsr     w0, w0, w1"}
+%def op_ushr_int():
+%  binop(instr="lsr     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S
index 1cb8cb74422faaf2603bb6f02a0689c07a7e5925..47527b182ffff21612b7451876a2ef3d9c1aef24 100644
--- a/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binop2addr.S" {"instr":"lsr     w0, w0, w1"}
+%def op_ushr_int_2addr():
+%  binop2addr(instr="lsr     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S
index 555ed4eb296d7b5e1abe9e14bf3aa43c7ba75959..abc5898bcb49950fb4450100e00046a884a2d587 100644
--- a/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S
+++ b/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S
@@ -1 +1,2 @@
-%include "arm64/binopLit8.S" {"extract":"ubfx    w1, w3, #8, #5", "instr":"lsr     w0, w0, w1"}
+%def op_ushr_int_lit8():
+%  binopLit8(extract="ubfx    w1, w3, #8, #5", instr="lsr     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_ushr_long.S b/runtime/interpreter/mterp/arm64/op_ushr_long.S
index e13c86a48bb55de4fa94acb21106e19dbff12b1c..4f3e941872d11394286c22743b7216c0e88afa8d 100644
--- a/runtime/interpreter/mterp/arm64/op_ushr_long.S
+++ b/runtime/interpreter/mterp/arm64/op_ushr_long.S
@@ -1 +1,2 @@
-%include "arm64/shiftWide.S" {"opcode":"lsr"}
+%def op_ushr_long():
+%  shiftWide(opcode="lsr")
diff --git a/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S
index 67ec91e967d0e092e686b357d49ae70c5230c35c..5606d12a21f802e299d4e13a7c40896019a78407 100644
--- a/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S
@@ -1 +1,2 @@
-%include "arm64/shiftWide2addr.S" {"opcode":"lsr"}
+%def op_ushr_long_2addr():
+%  shiftWide2addr(opcode="lsr")
diff --git a/runtime/interpreter/mterp/arm64/op_xor_int.S b/runtime/interpreter/mterp/arm64/op_xor_int.S
index 74836635fe8f598881f7ed17911ad46082cb1050..369af7dc11a362945f5de95e67d5cc2083b1b4fb 100644
--- a/runtime/interpreter/mterp/arm64/op_xor_int.S
+++ b/runtime/interpreter/mterp/arm64/op_xor_int.S
@@ -1 +1,2 @@
-%include "arm64/binop.S" {"instr":"eor     w0, w0, w1"}
+%def op_xor_int():
+%  binop(instr="eor     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S b/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S
index 2f9a2c73594454c60d6996981fe49c0c42b16b70..f8e87b359f7a8b3a6133c8800c5e81d3f852d9ec 100644
--- a/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binop2addr.S" {"instr":"eor     w0, w0, w1"}
+%def op_xor_int_2addr():
+%  binop2addr(instr="eor     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S b/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S
index 6b72c560f994d466e6af65e031ca200617f913a8..bcfc6e20b3dea041f4d7e9b10a143588dbd6d152 100644
--- a/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S
+++ b/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S
@@ -1 +1,2 @@
-%include "arm64/binopLit16.S" {"instr":"eor     w0, w0, w1"}
+%def op_xor_int_lit16():
+%  binopLit16(instr="eor     w0, w0, w1")
diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S b/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S
index 1d3d93e3f74c86ba06a5518a9d56ab566b4ecf9f..bd59c4cdbd79eb96d6d741a4332679dbbbea7a81 100644
--- a/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S
+++ b/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S
@@ -1 +1,2 @@
-%include "arm64/binopLit8.S" {"extract":"", "instr":"eor     w0, w0, w3, asr #8"}
+%def op_xor_int_lit8():
+%  binopLit8(extract="", instr="eor     w0, w0, w3, asr #8")
diff --git a/runtime/interpreter/mterp/arm64/op_xor_long.S b/runtime/interpreter/mterp/arm64/op_xor_long.S
index 3880d5d19f70d9b670639213b5cf1480338ea4e8..58b97bd247f233f8e2cd8c35f8a41136019e3a8b 100644
--- a/runtime/interpreter/mterp/arm64/op_xor_long.S
+++ b/runtime/interpreter/mterp/arm64/op_xor_long.S
@@ -1 +1,2 @@
-%include "arm64/binopWide.S" {"instr":"eor x0, x1, x2"}
+%def op_xor_long():
+%  binopWide(instr="eor x0, x1, x2")
diff --git a/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S b/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S
index 36905529d514f49f5fef364189dd7519bf232949..5877665de73efedbb96bd1147cf553f11d285603 100644
--- a/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S
+++ b/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S
@@ -1 +1,2 @@
-%include "arm64/binopWide2addr.S" {"instr":"eor     x0, x0, x1"}
+%def op_xor_long_2addr():
+%  binopWide2addr(instr="eor     x0, x0, x1")
diff --git a/runtime/interpreter/mterp/arm64/shiftWide.S b/runtime/interpreter/mterp/arm64/shiftWide.S
index dcb2fb701a79454129812d2afa5378d87f9e40d8..46922c86264b405618ea53595f88fb0ef66585ea 100644
--- a/runtime/interpreter/mterp/arm64/shiftWide.S
+++ b/runtime/interpreter/mterp/arm64/shiftWide.S
@@ -1,4 +1,4 @@
-%default {"opcode":"shl"}
+%def shiftWide(opcode="shl"):
     /*
      * 64-bit shift operation.
      *
diff --git a/runtime/interpreter/mterp/arm64/shiftWide2addr.S b/runtime/interpreter/mterp/arm64/shiftWide2addr.S
index b860dfddd3e749a4fa54672757a4b38d15411886..2780d455e3c535bf94fe4cb731cece0f9e657970 100644
--- a/runtime/interpreter/mterp/arm64/shiftWide2addr.S
+++ b/runtime/interpreter/mterp/arm64/shiftWide2addr.S
@@ -1,4 +1,4 @@
-%default {"opcode":"lsl"}
+%def shiftWide2addr(opcode="lsl"):
     /*
      * Generic 64-bit shift operation.
      */
diff --git a/runtime/interpreter/mterp/arm64/unop.S b/runtime/interpreter/mterp/arm64/unop.S
index e681968a9fedd0cdc669168902c51d498b1248ae..65faf665ab651f13891ce087bc9e0ecc9ca96d27 100644
--- a/runtime/interpreter/mterp/arm64/unop.S
+++ b/runtime/interpreter/mterp/arm64/unop.S
@@ -1,3 +1,4 @@
+%def unop(instr=""):
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op w0".
diff --git a/runtime/interpreter/mterp/arm64/unopWide.S b/runtime/interpreter/mterp/arm64/unopWide.S
index 6ee4f922e19262c93460ab4b9b7eb5c61fc19615..6a16dfa9f05abab6428d8ebe59bed65ccde231e6 100644
--- a/runtime/interpreter/mterp/arm64/unopWide.S
+++ b/runtime/interpreter/mterp/arm64/unopWide.S
@@ -1,4 +1,4 @@
-%default {"instr":"sub x0, xzr, x0"}
+%def unopWide(instr="sub x0, xzr, x0"):
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op x0".
diff --git a/runtime/interpreter/mterp/arm64/unused.S b/runtime/interpreter/mterp/arm64/unused.S
index ffa00becfdb2bb4ba58ee7659a0609978599110e..3f37e74bb4752ad0c5af7cc91b0202f5f00429cd 100644
--- a/runtime/interpreter/mterp/arm64/unused.S
+++ b/runtime/interpreter/mterp/arm64/unused.S
@@ -1,3 +1,4 @@
+%def unused():
 /*
  * Bail to reference interpreter to throw.
  */
diff --git a/runtime/interpreter/mterp/arm64/zcmp.S b/runtime/interpreter/mterp/arm64/zcmp.S
index 510a3c10cd1bfb36619e75866e5895bd51fac637..4435854d1432dfacf250cbf7ffe8b07ed97f1320 100644
--- a/runtime/interpreter/mterp/arm64/zcmp.S
+++ b/runtime/interpreter/mterp/arm64/zcmp.S
@@ -1,4 +1,4 @@
-%default { "compare":"1" }
+%def zcmp(compare="1", branch=""):
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
diff --git a/runtime/interpreter/mterp/common/gen_setup.py b/runtime/interpreter/mterp/common/gen_setup.py
new file mode 100644
index 0000000000000000000000000000000000000000..b2e62f6ea0222ff6be1e2857bb7b2df398ef5d30
--- /dev/null
+++ b/runtime/interpreter/mterp/common/gen_setup.py
@@ -0,0 +1,85 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# Common global variables and helper methods for the in-memory python script.
+
+import sys, re
+from cStringIO import StringIO
+
+out = StringIO()  # File-like in-memory buffer.
+handler_size_bytes = "128"
+handler_size_bits = "7"
+opcode = ""
+opnum = ""
+
+def write_line(line):
+  out.write(line + "\n")
+
+def balign():
+  write_line("    .balign {}".format(handler_size_bytes))
+
+def write_opcode(num, name, write_method, is_alt):
+  global opnum, opcode
+  opnum, opcode = str(num), name
+  if is_alt:
+    name = "ALT_" + name
+  write_line("/* ------------------------------ */")
+  balign()
+  write_line(".L_{1}: /* {0:#04x} */".format(num, name))
+  if is_alt:
+    alt_stub()
+  else:
+    write_method()
+  write_line("")
+  opnum, opcode = None, None
+
+def generate():
+  out.seek(0)
+  out.truncate()
+  write_line("/* DO NOT EDIT: This file was generated by gen-mterp.py. */")
+  header()
+  entry()
+
+  instruction_start()
+  opcodes(is_alt = False)
+  balign()
+  instruction_end()
+
+  instruction_start_sister()
+  write_sister()
+  instruction_end_sister()
+
+  # We need to footer sooner so that branch instruction can reach it.
+  # TODO: Clean up.
+  if arch == "arm64":
+    footer()
+
+  instruction_start_alt()
+  opcodes(is_alt = True)
+  balign()
+  instruction_end_alt()
+
+  if arch == "arm64":
+    close_cfi()
+  else:
+    footer()
+
+  out.seek(0)
+  # Squash consequtive empty lines.
+  text = re.sub(r"(\n\n)(\n)+", r"\1", out.read())
+  with open('out/mterp_' + arch + '.S', 'w') as output_file:
+    output_file.write(text)
+
diff --git a/runtime/interpreter/mterp/config_arm b/runtime/interpreter/mterp/config_arm
deleted file mode 100644
index a45efd999ba1c3a6a67af470b6e1d465fd1290c7..0000000000000000000000000000000000000000
--- a/runtime/interpreter/mterp/config_arm
+++ /dev/null
@@ -1,298 +0,0 @@
-# Copyright (C) 2015 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-#
-# Configuration for ARMv7-A targets.
-#
-
-handler-style computed-goto
-handler-size 128
-
-# source for alternate entry stub
-asm-alt-stub arm/alt_stub.S
-
-# file header and basic definitions
-import arm/header.S
-
-# arch-specific entry point to interpreter
-import arm/entry.S
-
-# Stub to switch to alternate interpreter
-fallback-stub arm/fallback.S
-
-# opcode list; argument to op-start is default directory
-op-start arm
-    # (override example:) op op_sub_float_2addr arm-vfp
-    # (fallback example:) op op_sub_float_2addr FALLBACK
-
-    # op op_nop FALLBACK
-    # op op_move FALLBACK
-    # op op_move_from16 FALLBACK
-    # op op_move_16 FALLBACK
-    # op op_move_wide FALLBACK
-    # op op_move_wide_from16 FALLBACK
-    # op op_move_wide_16 FALLBACK
-    # op op_move_object FALLBACK
-    # op op_move_object_from16 FALLBACK
-    # op op_move_object_16 FALLBACK
-    # op op_move_result FALLBACK
-    # op op_move_result_wide FALLBACK
-    # op op_move_result_object FALLBACK
-    # op op_move_exception FALLBACK
-    # op op_return_void FALLBACK
-    # op op_return FALLBACK
-    # op op_return_wide FALLBACK
-    # op op_return_object FALLBACK
-    # op op_const_4 FALLBACK
-    # op op_const_16 FALLBACK
-    # op op_const FALLBACK
-    # op op_const_high16 FALLBACK
-    # op op_const_wide_16 FALLBACK
-    # op op_const_wide_32 FALLBACK
-    # op op_const_wide FALLBACK
-    # op op_const_wide_high16 FALLBACK
-    # op op_const_string FALLBACK
-    # op op_const_string_jumbo FALLBACK
-    # op op_const_class FALLBACK
-    # op op_monitor_enter FALLBACK
-    # op op_monitor_exit FALLBACK
-    # op op_check_cast FALLBACK
-    # op op_instance_of FALLBACK
-    # op op_array_length FALLBACK
-    # op op_new_instance FALLBACK
-    # op op_new_array FALLBACK
-    # op op_filled_new_array FALLBACK
-    # op op_filled_new_array_range FALLBACK
-    # op op_fill_array_data FALLBACK
-    # op op_throw FALLBACK
-    # op op_goto FALLBACK
-    # op op_goto_16 FALLBACK
-    # op op_goto_32 FALLBACK
-    # op op_packed_switch FALLBACK
-    # op op_sparse_switch FALLBACK
-    # op op_cmpl_float FALLBACK
-    # op op_cmpg_float FALLBACK
-    # op op_cmpl_double FALLBACK
-    # op op_cmpg_double FALLBACK
-    # op op_cmp_long FALLBACK
-    # op op_if_eq FALLBACK
-    # op op_if_ne FALLBACK
-    # op op_if_lt FALLBACK
-    # op op_if_ge FALLBACK
-    # op op_if_gt FALLBACK
-    # op op_if_le FALLBACK
-    # op op_if_eqz FALLBACK
-    # op op_if_nez FALLBACK
-    # op op_if_ltz FALLBACK
-    # op op_if_gez FALLBACK
-    # op op_if_gtz FALLBACK
-    # op op_if_lez FALLBACK
-    # op op_unused_3e FALLBACK
-    # op op_unused_3f FALLBACK
-    # op op_unused_40 FALLBACK
-    # op op_unused_41 FALLBACK
-    # op op_unused_42 FALLBACK
-    # op op_unused_43 FALLBACK
-    # op op_aget FALLBACK
-    # op op_aget_wide FALLBACK
-    # op op_aget_object FALLBACK
-    # op op_aget_boolean FALLBACK
-    # op op_aget_byte FALLBACK
-    # op op_aget_char FALLBACK
-    # op op_aget_short FALLBACK
-    # op op_aput FALLBACK
-    # op op_aput_wide FALLBACK
-    # op op_aput_object FALLBACK
-    # op op_aput_boolean FALLBACK
-    # op op_aput_byte FALLBACK
-    # op op_aput_char FALLBACK
-    # op op_aput_short FALLBACK
-    # op op_iget FALLBACK
-    # op op_iget_wide FALLBACK
-    # op op_iget_object FALLBACK
-    # op op_iget_boolean FALLBACK
-    # op op_iget_byte FALLBACK
-    # op op_iget_char FALLBACK
-    # op op_iget_short FALLBACK
-    # op op_iput FALLBACK
-    # op op_iput_wide FALLBACK
-    # op op_iput_object FALLBACK
-    # op op_iput_boolean FALLBACK
-    # op op_iput_byte FALLBACK
-    # op op_iput_char FALLBACK
-    # op op_iput_short FALLBACK
-    # op op_sget FALLBACK
-    # op op_sget_wide FALLBACK
-    # op op_sget_object FALLBACK
-    # op op_sget_boolean FALLBACK
-    # op op_sget_byte FALLBACK
-    # op op_sget_char FALLBACK
-    # op op_sget_short FALLBACK
-    # op op_sput FALLBACK
-    # op op_sput_wide FALLBACK
-    # op op_sput_object FALLBACK
-    # op op_sput_boolean FALLBACK
-    # op op_sput_byte FALLBACK
-    # op op_sput_char FALLBACK
-    # op op_sput_short FALLBACK
-    # op op_invoke_virtual FALLBACK
-    # op op_invoke_super FALLBACK
-    # op op_invoke_direct FALLBACK
-    # op op_invoke_static FALLBACK
-    # op op_invoke_interface FALLBACK
-    # op op_return_void_no_barrier FALLBACK
-    # op op_invoke_virtual_range FALLBACK
-    # op op_invoke_super_range FALLBACK
-    # op op_invoke_direct_range FALLBACK
-    # op op_invoke_static_range FALLBACK
-    # op op_invoke_interface_range FALLBACK
-    # op op_unused_79 FALLBACK
-    # op op_unused_7a FALLBACK
-    # op op_neg_int FALLBACK
-    # op op_not_int FALLBACK
-    # op op_neg_long FALLBACK
-    # op op_not_long FALLBACK
-    # op op_neg_float FALLBACK
-    # op op_neg_double FALLBACK
-    # op op_int_to_long FALLBACK
-    # op op_int_to_float FALLBACK
-    # op op_int_to_double FALLBACK
-    # op op_long_to_int FALLBACK
-    # op op_long_to_float FALLBACK
-    # op op_long_to_double FALLBACK
-    # op op_float_to_int FALLBACK
-    # op op_float_to_long FALLBACK
-    # op op_float_to_double FALLBACK
-    # op op_double_to_int FALLBACK
-    # op op_double_to_long FALLBACK
-    # op op_double_to_float FALLBACK
-    # op op_int_to_byte FALLBACK
-    # op op_int_to_char FALLBACK
-    # op op_int_to_short FALLBACK
-    # op op_add_int FALLBACK
-    # op op_sub_int FALLBACK
-    # op op_mul_int FALLBACK
-    # op op_div_int FALLBACK
-    # op op_rem_int FALLBACK
-    # op op_and_int FALLBACK
-    # op op_or_int FALLBACK
-    # op op_xor_int FALLBACK
-    # op op_shl_int FALLBACK
-    # op op_shr_int FALLBACK
-    # op op_ushr_int FALLBACK
-    # op op_add_long FALLBACK
-    # op op_sub_long FALLBACK
-    # op op_mul_long FALLBACK
-    # op op_div_long FALLBACK
-    # op op_rem_long FALLBACK
-    # op op_and_long FALLBACK
-    # op op_or_long FALLBACK
-    # op op_xor_long FALLBACK
-    # op op_shl_long FALLBACK
-    # op op_shr_long FALLBACK
-    # op op_ushr_long FALLBACK
-    # op op_add_float FALLBACK
-    # op op_sub_float FALLBACK
-    # op op_mul_float FALLBACK
-    # op op_div_float FALLBACK
-    # op op_rem_float FALLBACK
-    # op op_add_double FALLBACK
-    # op op_sub_double FALLBACK
-    # op op_mul_double FALLBACK
-    # op op_div_double FALLBACK
-    # op op_rem_double FALLBACK
-    # op op_add_int_2addr FALLBACK
-    # op op_sub_int_2addr FALLBACK
-    # op op_mul_int_2addr FALLBACK
-    # op op_div_int_2addr FALLBACK
-    # op op_rem_int_2addr FALLBACK
-    # op op_and_int_2addr FALLBACK
-    # op op_or_int_2addr FALLBACK
-    # op op_xor_int_2addr FALLBACK
-    # op op_shl_int_2addr FALLBACK
-    # op op_shr_int_2addr FALLBACK
-    # op op_ushr_int_2addr FALLBACK
-    # op op_add_long_2addr FALLBACK
-    # op op_sub_long_2addr FALLBACK
-    # op op_mul_long_2addr FALLBACK
-    # op op_div_long_2addr FALLBACK
-    # op op_rem_long_2addr FALLBACK
-    # op op_and_long_2addr FALLBACK
-    # op op_or_long_2addr FALLBACK
-    # op op_xor_long_2addr FALLBACK
-    # op op_shl_long_2addr FALLBACK
-    # op op_shr_long_2addr FALLBACK
-    # op op_ushr_long_2addr FALLBACK
-    # op op_add_float_2addr FALLBACK
-    # op op_sub_float_2addr FALLBACK
-    # op op_mul_float_2addr FALLBACK
-    # op op_div_float_2addr FALLBACK
-    # op op_rem_float_2addr FALLBACK
-    # op op_add_double_2addr FALLBACK
-    # op op_sub_double_2addr FALLBACK
-    # op op_mul_double_2addr FALLBACK
-    # op op_div_double_2addr FALLBACK
-    # op op_rem_double_2addr FALLBACK
-    # op op_add_int_lit16 FALLBACK
-    # op op_rsub_int FALLBACK
-    # op op_mul_int_lit16 FALLBACK
-    # op op_div_int_lit16 FALLBACK
-    # op op_rem_int_lit16 FALLBACK
-    # op op_and_int_lit16 FALLBACK
-    # op op_or_int_lit16 FALLBACK
-    # op op_xor_int_lit16 FALLBACK
-    # op op_add_int_lit8 FALLBACK
-    # op op_rsub_int_lit8 FALLBACK
-    # op op_mul_int_lit8 FALLBACK
-    # op op_div_int_lit8 FALLBACK
-    # op op_rem_int_lit8 FALLBACK
-    # op op_and_int_lit8 FALLBACK
-    # op op_or_int_lit8 FALLBACK
-    # op op_xor_int_lit8 FALLBACK
-    # op op_shl_int_lit8 FALLBACK
-    # op op_shr_int_lit8 FALLBACK
-    # op op_ushr_int_lit8 FALLBACK
-    # op op_iget_quick FALLBACK
-    # op op_iget_wide_quick FALLBACK
-    # op op_iget_object_quick FALLBACK
-    # op op_iput_quick FALLBACK
-    # op op_iput_wide_quick FALLBACK
-    # op op_iput_object_quick FALLBACK
-    # op op_invoke_virtual_quick FALLBACK
-    # op op_invoke_virtual_range_quick FALLBACK
-    # op op_iput_boolean_quick FALLBACK
-    # op op_iput_byte_quick FALLBACK
-    # op op_iput_char_quick FALLBACK
-    # op op_iput_short_quick FALLBACK
-    # op op_iget_boolean_quick FALLBACK
-    # op op_iget_byte_quick FALLBACK
-    # op op_iget_char_quick FALLBACK
-    # op op_iget_short_quick FALLBACK
-    # op op_unused_f3 FALLBACK
-    # op op_unused_f4 FALLBACK
-    # op op_unused_f5 FALLBACK
-    # op op_unused_f6 FALLBACK
-    # op op_unused_f7 FALLBACK
-    # op op_unused_f8 FALLBACK
-    # op op_unused_f9 FALLBACK
-    # op op_invoke_polymorphic FALLBACK
-    # op op_invoke_polymorphic_range FALLBACK
-    # op op_invoke_custom FALLBACK
-    # op op_invoke_custom_range FALLBACK
-    # op op_const_method_handle FALLBACK
-    # op op_const_method_type FALLBACK
-op-end
-
-# common subroutines for asm
-import arm/footer.S
diff --git a/runtime/interpreter/mterp/config_arm64 b/runtime/interpreter/mterp/config_arm64
deleted file mode 100644
index 590363f6e420510b7c7cab163378991d544a08c3..0000000000000000000000000000000000000000
--- a/runtime/interpreter/mterp/config_arm64
+++ /dev/null
@@ -1,306 +0,0 @@
-
-# Copyright (C) 2015 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-#
-# Configuration for ARM64
-#
-
-handler-style computed-goto
-handler-size 128
-
-# file header and basic definitions
-import arm64/header.S
-
-# arch-specific entry point to interpreter
-import arm64/entry.S
-
-# Stub to switch to alternate interpreter
-fallback-stub arm64/fallback.S
-
-# opcode list; argument to op-start is default directory
-op-start arm64
-    # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp
-    # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK
-
-    # op op_nop FALLBACK
-    # op op_move FALLBACK
-    # op op_move_from16 FALLBACK
-    # op op_move_16 FALLBACK
-    # op op_move_wide FALLBACK
-    # op op_move_wide_from16 FALLBACK
-    # op op_move_wide_16 FALLBACK
-    # op op_move_object FALLBACK
-    # op op_move_object_from16 FALLBACK
-    # op op_move_object_16 FALLBACK
-    # op op_move_result FALLBACK
-    # op op_move_result_wide FALLBACK
-    # op op_move_result_object FALLBACK
-    # op op_move_exception FALLBACK
-    # op op_return_void FALLBACK
-    # op op_return FALLBACK
-    # op op_return_wide FALLBACK
-    # op op_return_object FALLBACK
-    # op op_const_4 FALLBACK
-    # op op_const_16 FALLBACK
-    # op op_const FALLBACK
-    # op op_const_high16 FALLBACK
-    # op op_const_wide_16 FALLBACK
-    # op op_const_wide_32 FALLBACK
-    # op op_const_wide FALLBACK
-    # op op_const_wide_high16 FALLBACK
-    # op op_const_string FALLBACK
-    # op op_const_string_jumbo FALLBACK
-    # op op_const_class FALLBACK
-    # op op_monitor_enter FALLBACK
-    # op op_monitor_exit FALLBACK
-    # op op_check_cast FALLBACK
-    # op op_instance_of FALLBACK
-    # op op_array_length FALLBACK
-    # op op_new_instance FALLBACK
-    # op op_new_array FALLBACK
-    # op op_filled_new_array FALLBACK
-    # op op_filled_new_array_range FALLBACK
-    # op op_fill_array_data FALLBACK
-    # op op_throw FALLBACK
-    # op op_goto FALLBACK
-    # op op_goto_16 FALLBACK
-    # op op_goto_32 FALLBACK
-    # op op_packed_switch FALLBACK
-    # op op_sparse_switch FALLBACK
-    # op op_cmpl_float FALLBACK
-    # op op_cmpg_float FALLBACK
-    # op op_cmpl_double FALLBACK
-    # op op_cmpg_double FALLBACK
-    # op op_cmp_long FALLBACK
-    # op op_if_eq FALLBACK
-    # op op_if_ne FALLBACK
-    # op op_if_lt FALLBACK
-    # op op_if_ge FALLBACK
-    # op op_if_gt FALLBACK
-    # op op_if_le FALLBACK
-    # op op_if_eqz FALLBACK
-    # op op_if_nez FALLBACK
-    # op op_if_ltz FALLBACK
-    # op op_if_gez FALLBACK
-    # op op_if_gtz FALLBACK
-    # op op_if_lez FALLBACK
-    # op op_unused_3e FALLBACK
-    # op op_unused_3f FALLBACK
-    # op op_unused_40 FALLBACK
-    # op op_unused_41 FALLBACK
-    # op op_unused_42 FALLBACK
-    # op op_unused_43 FALLBACK
-    # op op_aget FALLBACK
-    # op op_aget_wide FALLBACK
-    # op op_aget_object FALLBACK
-    # op op_aget_boolean FALLBACK
-    # op op_aget_byte FALLBACK
-    # op op_aget_char FALLBACK
-    # op op_aget_short FALLBACK
-    # op op_aput FALLBACK
-    # op op_aput_wide FALLBACK
-    # op op_aput_object FALLBACK
-    # op op_aput_boolean FALLBACK
-    # op op_aput_byte FALLBACK
-    # op op_aput_char FALLBACK
-    # op op_aput_short FALLBACK
-    # op op_iget FALLBACK
-    # op op_iget_wide FALLBACK
-    # op op_iget_object FALLBACK
-    # op op_iget_boolean FALLBACK
-    # op op_iget_byte FALLBACK
-    # op op_iget_char FALLBACK
-    # op op_iget_short FALLBACK
-    # op op_iput FALLBACK
-    # op op_iput_wide FALLBACK
-    # op op_iput_object FALLBACK
-    # op op_iput_boolean FALLBACK
-    # op op_iput_byte FALLBACK
-    # op op_iput_char FALLBACK
-    # op op_iput_short FALLBACK
-    # op op_sget FALLBACK
-    # op op_sget_wide FALLBACK
-    # op op_sget_object FALLBACK
-    # op op_sget_boolean FALLBACK
-    # op op_sget_byte FALLBACK
-    # op op_sget_char FALLBACK
-    # op op_sget_short FALLBACK
-    # op op_sput FALLBACK
-    # op op_sput_wide FALLBACK
-    # op op_sput_object FALLBACK
-    # op op_sput_boolean FALLBACK
-    # op op_sput_byte FALLBACK
-    # op op_sput_char FALLBACK
-    # op op_sput_short FALLBACK
-    # op op_invoke_virtual FALLBACK
-    # op op_invoke_super FALLBACK
-    # op op_invoke_direct FALLBACK
-    # op op_invoke_static FALLBACK
-    # op op_invoke_interface FALLBACK
-    # op op_return_void_no_barrier FALLBACK
-    # op op_invoke_virtual_range FALLBACK
-    # op op_invoke_super_range FALLBACK
-    # op op_invoke_direct_range FALLBACK
-    # op op_invoke_static_range FALLBACK
-    # op op_invoke_interface_range FALLBACK
-    # op op_unused_79 FALLBACK
-    # op op_unused_7a FALLBACK
-    # op op_neg_int FALLBACK
-    # op op_not_int FALLBACK
-    # op op_neg_long FALLBACK
-    # op op_not_long FALLBACK
-    # op op_neg_float FALLBACK
-    # op op_neg_double FALLBACK
-    # op op_int_to_long FALLBACK
-    # op op_int_to_float FALLBACK
-    # op op_int_to_double FALLBACK
-    # op op_long_to_int FALLBACK
-    # op op_long_to_float FALLBACK
-    # op op_long_to_double FALLBACK
-    # op op_float_to_int FALLBACK
-    # op op_float_to_long FALLBACK
-    # op op_float_to_double FALLBACK
-    # op op_double_to_int FALLBACK
-    # op op_double_to_long FALLBACK
-    # op op_double_to_float FALLBACK
-    # op op_int_to_byte FALLBACK
-    # op op_int_to_char FALLBACK
-    # op op_int_to_short FALLBACK
-    # op op_add_int FALLBACK
-    # op op_sub_int FALLBACK
-    # op op_mul_int FALLBACK
-    # op op_div_int FALLBACK
-    # op op_rem_int FALLBACK
-    # op op_and_int FALLBACK
-    # op op_or_int FALLBACK
-    # op op_xor_int FALLBACK
-    # op op_shl_int FALLBACK
-    # op op_shr_int FALLBACK
-    # op op_ushr_int FALLBACK
-    # op op_add_long FALLBACK
-    # op op_sub_long FALLBACK
-    # op op_mul_long FALLBACK
-    # op op_div_long FALLBACK
-    # op op_rem_long FALLBACK
-    # op op_and_long FALLBACK
-    # op op_or_long FALLBACK
-    # op op_xor_long FALLBACK
-    # op op_shl_long FALLBACK
-    # op op_shr_long FALLBACK
-    # op op_ushr_long FALLBACK
-    # op op_add_float FALLBACK
-    # op op_sub_float FALLBACK
-    # op op_mul_float FALLBACK
-    # op op_div_float FALLBACK
-    # op op_rem_float FALLBACK
-    # op op_add_double FALLBACK
-    # op op_sub_double FALLBACK
-    # op op_mul_double FALLBACK
-    # op op_div_double FALLBACK
-    # op op_rem_double FALLBACK
-    # op op_add_int_2addr FALLBACK
-    # op op_sub_int_2addr FALLBACK
-    # op op_mul_int_2addr FALLBACK
-    # op op_div_int_2addr FALLBACK
-    # op op_rem_int_2addr FALLBACK
-    # op op_and_int_2addr FALLBACK
-    # op op_or_int_2addr FALLBACK
-    # op op_xor_int_2addr FALLBACK
-    # op op_shl_int_2addr FALLBACK
-    # op op_shr_int_2addr FALLBACK
-    # op op_ushr_int_2addr FALLBACK
-    # op op_add_long_2addr FALLBACK
-    # op op_sub_long_2addr FALLBACK
-    # op op_mul_long_2addr FALLBACK
-    # op op_div_long_2addr FALLBACK
-    # op op_rem_long_2addr FALLBACK
-    # op op_and_long_2addr FALLBACK
-    # op op_or_long_2addr FALLBACK
-    # op op_xor_long_2addr FALLBACK
-    # op op_shl_long_2addr FALLBACK
-    # op op_shr_long_2addr FALLBACK
-    # op op_ushr_long_2addr FALLBACK
-    # op op_add_float_2addr FALLBACK
-    # op op_sub_float_2addr FALLBACK
-    # op op_mul_float_2addr FALLBACK
-    # op op_div_float_2addr FALLBACK
-    # op op_rem_float_2addr FALLBACK
-    # op op_add_double_2addr FALLBACK
-    # op op_sub_double_2addr FALLBACK
-    # op op_mul_double_2addr FALLBACK
-    # op op_div_double_2addr FALLBACK
-    # op op_rem_double_2addr FALLBACK
-    # op op_add_int_lit16 FALLBACK
-    # op op_rsub_int FALLBACK
-    # op op_mul_int_lit16 FALLBACK
-    # op op_div_int_lit16 FALLBACK
-    # op op_rem_int_lit16 FALLBACK
-    # op op_and_int_lit16 FALLBACK
-    # op op_or_int_lit16 FALLBACK
-    # op op_xor_int_lit16 FALLBACK
-    # op op_add_int_lit8 FALLBACK
-    # op op_rsub_int_lit8 FALLBACK
-    # op op_mul_int_lit8 FALLBACK
-    # op op_div_int_lit8 FALLBACK
-    # op op_rem_int_lit8 FALLBACK
-    # op op_and_int_lit8 FALLBACK
-    # op op_or_int_lit8 FALLBACK
-    # op op_xor_int_lit8 FALLBACK
-    # op op_shl_int_lit8 FALLBACK
-    # op op_shr_int_lit8 FALLBACK
-    # op op_ushr_int_lit8 FALLBACK
-    # op op_iget_quick FALLBACK
-    # op op_iget_wide_quick FALLBACK
-    # op op_iget_object_quick FALLBACK
-    # op op_iput_quick FALLBACK
-    # op op_iput_wide_quick FALLBACK
-    # op op_iput_object_quick FALLBACK
-    # op op_invoke_virtual_quick FALLBACK
-    # op op_invoke_virtual_range_quick FALLBACK
-    # op op_iput_boolean_quick FALLBACK
-    # op op_iput_byte_quick FALLBACK
-    # op op_iput_char_quick FALLBACK
-    # op op_iput_short_quick FALLBACK
-    # op op_iget_boolean_quick FALLBACK
-    # op op_iget_byte_quick FALLBACK
-    # op op_iget_char_quick FALLBACK
-    # op op_iget_short_quick FALLBACK
-    # op op_unused_f3 FALLBACK
-    # op op_unused_f4 FALLBACK
-    # op op_unused_f5 FALLBACK
-    # op op_unused_f6 FALLBACK
-    # op op_unused_f7 FALLBACK
-    # op op_unused_f8 FALLBACK
-    # op op_unused_f9 FALLBACK
-    # op op_invoke_polymorphic FALLBACK
-    # op op_invoke_polymorphic_range FALLBACK
-    # op op_invoke_custom FALLBACK
-    # op op_invoke_custom_range FALLBACK
-    # op op_const_method_handle FALLBACK
-    # op op_const_method_type FALLBACK
-op-end
-
-# common subroutines for asm; we emit the footer before alternate
-# entry stubs, so that TBZ/TBNZ from ops can reach targets in footer
-import arm64/footer.S
-
-# source for alternate entry stub
-asm-alt-stub arm64/alt_stub.S
-
-# emit alternate entry stubs
-alt-ops
-
-# finish by closing .cfi info
-import arm64/close_cfi.S
diff --git a/runtime/interpreter/mterp/config_mips b/runtime/interpreter/mterp/config_mips
deleted file mode 100644
index d6173daf2ccd62e50e77d591fbbc4468530220cb..0000000000000000000000000000000000000000
--- a/runtime/interpreter/mterp/config_mips
+++ /dev/null
@@ -1,298 +0,0 @@
-# Copyright (C) 2016 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-#
-# Configuration for MIPS_32 targets.
-#
-
-handler-style computed-goto
-handler-size 128
-
-# source for alternate entry stub
-asm-alt-stub mips/alt_stub.S
-
-# file header and basic definitions
-import mips/header.S
-
-# arch-specific entry point to interpreter
-import mips/entry.S
-
-# Stub to switch to alternate interpreter
-fallback-stub mips/fallback.S
-
-# opcode list; argument to op-start is default directory
-op-start mips
-    # (override example:) op op_sub_float_2addr arm-vfp
-    # (fallback example:) op op_sub_float_2addr FALLBACK
-
-    # op op_nop FALLBACK
-    # op op_move FALLBACK
-    # op op_move_from16 FALLBACK
-    # op op_move_16 FALLBACK
-    # op op_move_wide FALLBACK
-    # op op_move_wide_from16 FALLBACK
-    # op op_move_wide_16 FALLBACK
-    # op op_move_object FALLBACK
-    # op op_move_object_from16 FALLBACK
-    # op op_move_object_16 FALLBACK
-    # op op_move_result FALLBACK
-    # op op_move_result_wide FALLBACK
-    # op op_move_result_object FALLBACK
-    # op op_move_exception FALLBACK
-    # op op_return_void FALLBACK
-    # op op_return FALLBACK
-    # op op_return_wide FALLBACK
-    # op op_return_object FALLBACK
-    # op op_const_4 FALLBACK
-    # op op_const_16 FALLBACK
-    # op op_const FALLBACK
-    # op op_const_high16 FALLBACK
-    # op op_const_wide_16 FALLBACK
-    # op op_const_wide_32 FALLBACK
-    # op op_const_wide FALLBACK
-    # op op_const_wide_high16 FALLBACK
-    # op op_const_string FALLBACK
-    # op op_const_string_jumbo FALLBACK
-    # op op_const_class FALLBACK
-    # op op_monitor_enter FALLBACK
-    # op op_monitor_exit FALLBACK
-    # op op_check_cast FALLBACK
-    # op op_instance_of FALLBACK
-    # op op_array_length FALLBACK
-    # op op_new_instance FALLBACK
-    # op op_new_array FALLBACK
-    # op op_filled_new_array FALLBACK
-    # op op_filled_new_array_range FALLBACK
-    # op op_fill_array_data FALLBACK
-    # op op_throw FALLBACK
-    # op op_goto FALLBACK
-    # op op_goto_16 FALLBACK
-    # op op_goto_32 FALLBACK
-    # op op_packed_switch FALLBACK
-    # op op_sparse_switch FALLBACK
-    # op op_cmpl_float FALLBACK
-    # op op_cmpg_float FALLBACK
-    # op op_cmpl_double FALLBACK
-    # op op_cmpg_double FALLBACK
-    # op op_cmp_long FALLBACK
-    # op op_if_eq FALLBACK
-    # op op_if_ne FALLBACK
-    # op op_if_lt FALLBACK
-    # op op_if_ge FALLBACK
-    # op op_if_gt FALLBACK
-    # op op_if_le FALLBACK
-    # op op_if_eqz FALLBACK
-    # op op_if_nez FALLBACK
-    # op op_if_ltz FALLBACK
-    # op op_if_gez FALLBACK
-    # op op_if_gtz FALLBACK
-    # op op_if_lez FALLBACK
-    # op op_unused_3e FALLBACK
-    # op op_unused_3f FALLBACK
-    # op op_unused_40 FALLBACK
-    # op op_unused_41 FALLBACK
-    # op op_unused_42 FALLBACK
-    # op op_unused_43 FALLBACK
-    # op op_aget FALLBACK
-    # op op_aget_wide FALLBACK
-    # op op_aget_object FALLBACK
-    # op op_aget_boolean FALLBACK
-    # op op_aget_byte FALLBACK
-    # op op_aget_char FALLBACK
-    # op op_aget_short FALLBACK
-    # op op_aput FALLBACK
-    # op op_aput_wide FALLBACK
-    # op op_aput_object FALLBACK
-    # op op_aput_boolean FALLBACK
-    # op op_aput_byte FALLBACK
-    # op op_aput_char FALLBACK
-    # op op_aput_short FALLBACK
-    # op op_iget FALLBACK
-    # op op_iget_wide FALLBACK
-    # op op_iget_object FALLBACK
-    # op op_iget_boolean FALLBACK
-    # op op_iget_byte FALLBACK
-    # op op_iget_char FALLBACK
-    # op op_iget_short FALLBACK
-    # op op_iput FALLBACK
-    # op op_iput_wide FALLBACK
-    # op op_iput_object FALLBACK
-    # op op_iput_boolean FALLBACK
-    # op op_iput_byte FALLBACK
-    # op op_iput_char FALLBACK
-    # op op_iput_short FALLBACK
-    # op op_sget FALLBACK
-    # op op_sget_wide FALLBACK
-    # op op_sget_object FALLBACK
-    # op op_sget_boolean FALLBACK
-    # op op_sget_byte FALLBACK
-    # op op_sget_char FALLBACK
-    # op op_sget_short FALLBACK
-    # op op_sput FALLBACK
-    # op op_sput_wide FALLBACK
-    # op op_sput_object FALLBACK
-    # op op_sput_boolean FALLBACK
-    # op op_sput_byte FALLBACK
-    # op op_sput_char FALLBACK
-    # op op_sput_short FALLBACK
-    # op op_invoke_virtual FALLBACK
-    # op op_invoke_super FALLBACK
-    # op op_invoke_direct FALLBACK
-    # op op_invoke_static FALLBACK
-    # op op_invoke_interface FALLBACK
-    # op op_return_void_no_barrier FALLBACK
-    # op op_invoke_virtual_range FALLBACK
-    # op op_invoke_super_range FALLBACK
-    # op op_invoke_direct_range FALLBACK
-    # op op_invoke_static_range FALLBACK
-    # op op_invoke_interface_range FALLBACK
-    # op op_unused_79 FALLBACK
-    # op op_unused_7a FALLBACK
-    # op op_neg_int FALLBACK
-    # op op_not_int FALLBACK
-    # op op_neg_long FALLBACK
-    # op op_not_long FALLBACK
-    # op op_neg_float FALLBACK
-    # op op_neg_double FALLBACK
-    # op op_int_to_long FALLBACK
-    # op op_int_to_float FALLBACK
-    # op op_int_to_double FALLBACK
-    # op op_long_to_int FALLBACK
-    # op op_long_to_float FALLBACK
-    # op op_long_to_double FALLBACK
-    # op op_float_to_int FALLBACK
-    # op op_float_to_long FALLBACK
-    # op op_float_to_double FALLBACK
-    # op op_double_to_int FALLBACK
-    # op op_double_to_long FALLBACK
-    # op op_double_to_float FALLBACK
-    # op op_int_to_byte FALLBACK
-    # op op_int_to_char FALLBACK
-    # op op_int_to_short FALLBACK
-    # op op_add_int FALLBACK
-    # op op_sub_int FALLBACK
-    # op op_mul_int FALLBACK
-    # op op_div_int FALLBACK
-    # op op_rem_int FALLBACK
-    # op op_and_int FALLBACK
-    # op op_or_int FALLBACK
-    # op op_xor_int FALLBACK
-    # op op_shl_int FALLBACK
-    # op op_shr_int FALLBACK
-    # op op_ushr_int FALLBACK
-    # op op_add_long FALLBACK
-    # op op_sub_long FALLBACK
-    # op op_mul_long FALLBACK
-    # op op_div_long FALLBACK
-    # op op_rem_long FALLBACK
-    # op op_and_long FALLBACK
-    # op op_or_long FALLBACK
-    # op op_xor_long FALLBACK
-    # op op_shl_long FALLBACK
-    # op op_shr_long FALLBACK
-    # op op_ushr_long FALLBACK
-    # op op_add_float FALLBACK
-    # op op_sub_float FALLBACK
-    # op op_mul_float FALLBACK
-    # op op_div_float FALLBACK
-    # op op_rem_float FALLBACK
-    # op op_add_double FALLBACK
-    # op op_sub_double FALLBACK
-    # op op_mul_double FALLBACK
-    # op op_div_double FALLBACK
-    # op op_rem_double FALLBACK
-    # op op_add_int_2addr FALLBACK
-    # op op_sub_int_2addr FALLBACK
-    # op op_mul_int_2addr FALLBACK
-    # op op_div_int_2addr FALLBACK
-    # op op_rem_int_2addr FALLBACK
-    # op op_and_int_2addr FALLBACK
-    # op op_or_int_2addr FALLBACK
-    # op op_xor_int_2addr FALLBACK
-    # op op_shl_int_2addr FALLBACK
-    # op op_shr_int_2addr FALLBACK
-    # op op_ushr_int_2addr FALLBACK
-    # op op_add_long_2addr FALLBACK
-    # op op_sub_long_2addr FALLBACK
-    # op op_mul_long_2addr FALLBACK
-    # op op_div_long_2addr FALLBACK
-    # op op_rem_long_2addr FALLBACK
-    # op op_and_long_2addr FALLBACK
-    # op op_or_long_2addr FALLBACK
-    # op op_xor_long_2addr FALLBACK
-    # op op_shl_long_2addr FALLBACK
-    # op op_shr_long_2addr FALLBACK
-    # op op_ushr_long_2addr FALLBACK
-    # op op_add_float_2addr FALLBACK
-    # op op_sub_float_2addr FALLBACK
-    # op op_mul_float_2addr FALLBACK
-    # op op_div_float_2addr FALLBACK
-    # op op_rem_float_2addr FALLBACK
-    # op op_add_double_2addr FALLBACK
-    # op op_sub_double_2addr FALLBACK
-    # op op_mul_double_2addr FALLBACK
-    # op op_div_double_2addr FALLBACK
-    # op op_rem_double_2addr FALLBACK
-    # op op_add_int_lit16 FALLBACK
-    # op op_rsub_int FALLBACK
-    # op op_mul_int_lit16 FALLBACK
-    # op op_div_int_lit16 FALLBACK
-    # op op_rem_int_lit16 FALLBACK
-    # op op_and_int_lit16 FALLBACK
-    # op op_or_int_lit16 FALLBACK
-    # op op_xor_int_lit16 FALLBACK
-    # op op_add_int_lit8 FALLBACK
-    # op op_rsub_int_lit8 FALLBACK
-    # op op_mul_int_lit8 FALLBACK
-    # op op_div_int_lit8 FALLBACK
-    # op op_rem_int_lit8 FALLBACK
-    # op op_and_int_lit8 FALLBACK
-    # op op_or_int_lit8 FALLBACK
-    # op op_xor_int_lit8 FALLBACK
-    # op op_shl_int_lit8 FALLBACK
-    # op op_shr_int_lit8 FALLBACK
-    # op op_ushr_int_lit8 FALLBACK
-    # op op_iget_quick FALLBACK
-    # op op_iget_wide_quick FALLBACK
-    # op op_iget_object_quick FALLBACK
-    # op op_iput_quick FALLBACK
-    # op op_iput_wide_quick FALLBACK
-    # op op_iput_object_quick FALLBACK
-    # op op_invoke_virtual_quick FALLBACK
-    # op op_invoke_virtual_range_quick FALLBACK
-    # op op_iput_boolean_quick FALLBACK
-    # op op_iput_byte_quick FALLBACK
-    # op op_iput_char_quick FALLBACK
-    # op op_iput_short_quick FALLBACK
-    # op op_iget_boolean_quick FALLBACK
-    # op op_iget_byte_quick FALLBACK
-    # op op_iget_char_quick FALLBACK
-    # op op_iget_short_quick FALLBACK
-    # op op_unused_f3 FALLBACK
-    # op op_unused_f4 FALLBACK
-    # op op_unused_f5 FALLBACK
-    # op op_unused_f6 FALLBACK
-    # op op_unused_f7 FALLBACK
-    # op op_unused_f8 FALLBACK
-    # op op_unused_f9 FALLBACK
-    # op op_invoke_polymorphic FALLBACK
-    # op op_invoke_polymorphic_range FALLBACK
-    # op op_invoke_custom FALLBACK
-    # op op_invoke_custom_range FALLBACK
-    # op op_const_method_handle FALLBACK
-    # op op_const_method_type FALLBACK
-op-end
-
-# common subroutines for asm
-import mips/footer.S
diff --git a/runtime/interpreter/mterp/config_mips64 b/runtime/interpreter/mterp/config_mips64
deleted file mode 100644
index a9bf362ec3f9daa594d17abaa07ed1069b2d9c9a..0000000000000000000000000000000000000000
--- a/runtime/interpreter/mterp/config_mips64
+++ /dev/null
@@ -1,298 +0,0 @@
-# Copyright (C) 2015 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-#
-# Configuration for MIPS_64
-#
-
-handler-style computed-goto
-handler-size 128
-
-# source for alternate entry stub
-asm-alt-stub mips64/alt_stub.S
-
-# file header and basic definitions
-import mips64/header.S
-
-# arch-specific entry point to interpreter
-import mips64/entry.S
-
-# Stub to switch to alternate interpreter
-fallback-stub mips64/fallback.S
-
-# opcode list; argument to op-start is default directory
-op-start mips64
-    # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp
-    # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK
-
-    # op op_nop FALLBACK
-    # op op_move FALLBACK
-    # op op_move_from16 FALLBACK
-    # op op_move_16 FALLBACK
-    # op op_move_wide FALLBACK
-    # op op_move_wide_from16 FALLBACK
-    # op op_move_wide_16 FALLBACK
-    # op op_move_object FALLBACK
-    # op op_move_object_from16 FALLBACK
-    # op op_move_object_16 FALLBACK
-    # op op_move_result FALLBACK
-    # op op_move_result_wide FALLBACK
-    # op op_move_result_object FALLBACK
-    # op op_move_exception FALLBACK
-    # op op_return_void FALLBACK
-    # op op_return FALLBACK
-    # op op_return_wide FALLBACK
-    # op op_return_object FALLBACK
-    # op op_const_4 FALLBACK
-    # op op_const_16 FALLBACK
-    # op op_const FALLBACK
-    # op op_const_high16 FALLBACK
-    # op op_const_wide_16 FALLBACK
-    # op op_const_wide_32 FALLBACK
-    # op op_const_wide FALLBACK
-    # op op_const_wide_high16 FALLBACK
-    # op op_const_string FALLBACK
-    # op op_const_string_jumbo FALLBACK
-    # op op_const_class FALLBACK
-    # op op_monitor_enter FALLBACK
-    # op op_monitor_exit FALLBACK
-    # op op_check_cast FALLBACK
-    # op op_instance_of FALLBACK
-    # op op_array_length FALLBACK
-    # op op_new_instance FALLBACK
-    # op op_new_array FALLBACK
-    # op op_filled_new_array FALLBACK
-    # op op_filled_new_array_range FALLBACK
-    # op op_fill_array_data FALLBACK
-    # op op_throw FALLBACK
-    # op op_goto FALLBACK
-    # op op_goto_16 FALLBACK
-    # op op_goto_32 FALLBACK
-    # op op_packed_switch FALLBACK
-    # op op_sparse_switch FALLBACK
-    # op op_cmpl_float FALLBACK
-    # op op_cmpg_float FALLBACK
-    # op op_cmpl_double FALLBACK
-    # op op_cmpg_double FALLBACK
-    # op op_cmp_long FALLBACK
-    # op op_if_eq FALLBACK
-    # op op_if_ne FALLBACK
-    # op op_if_lt FALLBACK
-    # op op_if_ge FALLBACK
-    # op op_if_gt FALLBACK
-    # op op_if_le FALLBACK
-    # op op_if_eqz FALLBACK
-    # op op_if_nez FALLBACK
-    # op op_if_ltz FALLBACK
-    # op op_if_gez FALLBACK
-    # op op_if_gtz FALLBACK
-    # op op_if_lez FALLBACK
-    # op op_unused_3e FALLBACK
-    # op op_unused_3f FALLBACK
-    # op op_unused_40 FALLBACK
-    # op op_unused_41 FALLBACK
-    # op op_unused_42 FALLBACK
-    # op op_unused_43 FALLBACK
-    # op op_aget FALLBACK
-    # op op_aget_wide FALLBACK
-    # op op_aget_object FALLBACK
-    # op op_aget_boolean FALLBACK
-    # op op_aget_byte FALLBACK
-    # op op_aget_char FALLBACK
-    # op op_aget_short FALLBACK
-    # op op_aput FALLBACK
-    # op op_aput_wide FALLBACK
-    # op op_aput_object FALLBACK
-    # op op_aput_boolean FALLBACK
-    # op op_aput_byte FALLBACK
-    # op op_aput_char FALLBACK
-    # op op_aput_short FALLBACK
-    # op op_iget FALLBACK
-    # op op_iget_wide FALLBACK
-    # op op_iget_object FALLBACK
-    # op op_iget_boolean FALLBACK
-    # op op_iget_byte FALLBACK
-    # op op_iget_char FALLBACK
-    # op op_iget_short FALLBACK
-    # op op_iput FALLBACK
-    # op op_iput_wide FALLBACK
-    # op op_iput_object FALLBACK
-    # op op_iput_boolean FALLBACK
-    # op op_iput_byte FALLBACK
-    # op op_iput_char FALLBACK
-    # op op_iput_short FALLBACK
-    # op op_sget FALLBACK
-    # op op_sget_wide FALLBACK
-    # op op_sget_object FALLBACK
-    # op op_sget_boolean FALLBACK
-    # op op_sget_byte FALLBACK
-    # op op_sget_char FALLBACK
-    # op op_sget_short FALLBACK
-    # op op_sput FALLBACK
-    # op op_sput_wide FALLBACK
-    # op op_sput_object FALLBACK
-    # op op_sput_boolean FALLBACK
-    # op op_sput_byte FALLBACK
-    # op op_sput_char FALLBACK
-    # op op_sput_short FALLBACK
-    # op op_invoke_virtual FALLBACK
-    # op op_invoke_super FALLBACK
-    # op op_invoke_direct FALLBACK
-    # op op_invoke_static FALLBACK
-    # op op_invoke_interface FALLBACK
-    # op op_return_void_no_barrier FALLBACK
-    # op op_invoke_virtual_range FALLBACK
-    # op op_invoke_super_range FALLBACK
-    # op op_invoke_direct_range FALLBACK
-    # op op_invoke_static_range FALLBACK
-    # op op_invoke_interface_range FALLBACK
-    # op op_unused_79 FALLBACK
-    # op op_unused_7a FALLBACK
-    # op op_neg_int FALLBACK
-    # op op_not_int FALLBACK
-    # op op_neg_long FALLBACK
-    # op op_not_long FALLBACK
-    # op op_neg_float FALLBACK
-    # op op_neg_double FALLBACK
-    # op op_int_to_long FALLBACK
-    # op op_int_to_float FALLBACK
-    # op op_int_to_double FALLBACK
-    # op op_long_to_int FALLBACK
-    # op op_long_to_float FALLBACK
-    # op op_long_to_double FALLBACK
-    # op op_float_to_int FALLBACK
-    # op op_float_to_long FALLBACK
-    # op op_float_to_double FALLBACK
-    # op op_double_to_int FALLBACK
-    # op op_double_to_long FALLBACK
-    # op op_double_to_float FALLBACK
-    # op op_int_to_byte FALLBACK
-    # op op_int_to_char FALLBACK
-    # op op_int_to_short FALLBACK
-    # op op_add_int FALLBACK
-    # op op_sub_int FALLBACK
-    # op op_mul_int FALLBACK
-    # op op_div_int FALLBACK
-    # op op_rem_int FALLBACK
-    # op op_and_int FALLBACK
-    # op op_or_int FALLBACK
-    # op op_xor_int FALLBACK
-    # op op_shl_int FALLBACK
-    # op op_shr_int FALLBACK
-    # op op_ushr_int FALLBACK
-    # op op_add_long FALLBACK
-    # op op_sub_long FALLBACK
-    # op op_mul_long FALLBACK
-    # op op_div_long FALLBACK
-    # op op_rem_long FALLBACK
-    # op op_and_long FALLBACK
-    # op op_or_long FALLBACK
-    # op op_xor_long FALLBACK
-    # op op_shl_long FALLBACK
-    # op op_shr_long FALLBACK
-    # op op_ushr_long FALLBACK
-    # op op_add_float FALLBACK
-    # op op_sub_float FALLBACK
-    # op op_mul_float FALLBACK
-    # op op_div_float FALLBACK
-    # op op_rem_float FALLBACK
-    # op op_add_double FALLBACK
-    # op op_sub_double FALLBACK
-    # op op_mul_double FALLBACK
-    # op op_div_double FALLBACK
-    # op op_rem_double FALLBACK
-    # op op_add_int_2addr FALLBACK
-    # op op_sub_int_2addr FALLBACK
-    # op op_mul_int_2addr FALLBACK
-    # op op_div_int_2addr FALLBACK
-    # op op_rem_int_2addr FALLBACK
-    # op op_and_int_2addr FALLBACK
-    # op op_or_int_2addr FALLBACK
-    # op op_xor_int_2addr FALLBACK
-    # op op_shl_int_2addr FALLBACK
-    # op op_shr_int_2addr FALLBACK
-    # op op_ushr_int_2addr FALLBACK
-    # op op_add_long_2addr FALLBACK
-    # op op_sub_long_2addr FALLBACK
-    # op op_mul_long_2addr FALLBACK
-    # op op_div_long_2addr FALLBACK
-    # op op_rem_long_2addr FALLBACK
-    # op op_and_long_2addr FALLBACK
-    # op op_or_long_2addr FALLBACK
-    # op op_xor_long_2addr FALLBACK
-    # op op_shl_long_2addr FALLBACK
-    # op op_shr_long_2addr FALLBACK
-    # op op_ushr_long_2addr FALLBACK
-    # op op_add_float_2addr FALLBACK
-    # op op_sub_float_2addr FALLBACK
-    # op op_mul_float_2addr FALLBACK
-    # op op_div_float_2addr FALLBACK
-    # op op_rem_float_2addr FALLBACK
-    # op op_add_double_2addr FALLBACK
-    # op op_sub_double_2addr FALLBACK
-    # op op_mul_double_2addr FALLBACK
-    # op op_div_double_2addr FALLBACK
-    # op op_rem_double_2addr FALLBACK
-    # op op_add_int_lit16 FALLBACK
-    # op op_rsub_int FALLBACK
-    # op op_mul_int_lit16 FALLBACK
-    # op op_div_int_lit16 FALLBACK
-    # op op_rem_int_lit16 FALLBACK
-    # op op_and_int_lit16 FALLBACK
-    # op op_or_int_lit16 FALLBACK
-    # op op_xor_int_lit16 FALLBACK
-    # op op_add_int_lit8 FALLBACK
-    # op op_rsub_int_lit8 FALLBACK
-    # op op_mul_int_lit8 FALLBACK
-    # op op_div_int_lit8 FALLBACK
-    # op op_rem_int_lit8 FALLBACK
-    # op op_and_int_lit8 FALLBACK
-    # op op_or_int_lit8 FALLBACK
-    # op op_xor_int_lit8 FALLBACK
-    # op op_shl_int_lit8 FALLBACK
-    # op op_shr_int_lit8 FALLBACK
-    # op op_ushr_int_lit8 FALLBACK
-    # op op_iget_quick FALLBACK
-    # op op_iget_wide_quick FALLBACK
-    # op op_iget_object_quick FALLBACK
-    # op op_iput_quick FALLBACK
-    # op op_iput_wide_quick FALLBACK
-    # op op_iput_object_quick FALLBACK
-    # op op_invoke_virtual_quick FALLBACK
-    # op op_invoke_virtual_range_quick FALLBACK
-    # op op_iput_boolean_quick FALLBACK
-    # op op_iput_byte_quick FALLBACK
-    # op op_iput_char_quick FALLBACK
-    # op op_iput_short_quick FALLBACK
-    # op op_iget_boolean_quick FALLBACK
-    # op op_iget_byte_quick FALLBACK
-    # op op_iget_char_quick FALLBACK
-    # op op_iget_short_quick FALLBACK
-    # op op_unused_f3 FALLBACK
-    # op op_unused_f4 FALLBACK
-    # op op_unused_f5 FALLBACK
-    # op op_unused_f6 FALLBACK
-    # op op_unused_f7 FALLBACK
-    # op op_unused_f8 FALLBACK
-    # op op_unused_f9 FALLBACK
-    # op op_invoke_polymorphic FALLBACK
-    # op op_invoke_polymorphic_range FALLBACK
-    # op op_invoke_custom FALLBACK
-    # op op_invoke_custom_range FALLBACK
-    # op op_const_method_handle FALLBACK
-    # op op_const_method_type FALLBACK
-op-end
-
-# common subroutines for asm
-import mips64/footer.S
diff --git a/runtime/interpreter/mterp/config_x86 b/runtime/interpreter/mterp/config_x86
deleted file mode 100644
index 2417851c11bc14c7a530a6726c43dbfd63b12147..0000000000000000000000000000000000000000
--- a/runtime/interpreter/mterp/config_x86
+++ /dev/null
@@ -1,302 +0,0 @@
-# Copyright (C) 2015 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-#
-# Configuration for X86
-#
-
-handler-style computed-goto
-handler-size 128
-
-function-type-format FUNCTION_TYPE(%s)
-function-size-format SIZE(%s,%s)
-global-name-format SYMBOL(%s)
-
-# source for alternate entry stub
-asm-alt-stub x86/alt_stub.S
-
-# file header and basic definitions
-import x86/header.S
-
-# arch-specific entry point to interpreter
-import x86/entry.S
-
-# Stub to switch to alternate interpreter
-fallback-stub x86/fallback.S
-
-# opcode list; argument to op-start is default directory
-op-start x86
-    # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp
-    # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK
-
-    # op op_nop FALLBACK
-    # op op_move FALLBACK
-    # op op_move_from16 FALLBACK
-    # op op_move_16 FALLBACK
-    # op op_move_wide FALLBACK
-    # op op_move_wide_from16 FALLBACK
-    # op op_move_wide_16 FALLBACK
-    # op op_move_object FALLBACK
-    # op op_move_object_from16 FALLBACK
-    # op op_move_object_16 FALLBACK
-    # op op_move_result FALLBACK
-    # op op_move_result_wide FALLBACK
-    # op op_move_result_object FALLBACK
-    # op op_move_exception FALLBACK
-    # op op_return_void FALLBACK
-    # op op_return FALLBACK
-    # op op_return_wide FALLBACK
-    # op op_return_object FALLBACK
-    # op op_const_4 FALLBACK
-    # op op_const_16 FALLBACK
-    # op op_const FALLBACK
-    # op op_const_high16 FALLBACK
-    # op op_const_wide_16 FALLBACK
-    # op op_const_wide_32 FALLBACK
-    # op op_const_wide FALLBACK
-    # op op_const_wide_high16 FALLBACK
-    # op op_const_string FALLBACK
-    # op op_const_string_jumbo FALLBACK
-    # op op_const_class FALLBACK
-    # op op_monitor_enter FALLBACK
-    # op op_monitor_exit FALLBACK
-    # op op_check_cast FALLBACK
-    # op op_instance_of FALLBACK
-    # op op_array_length FALLBACK
-    # op op_new_instance FALLBACK
-    # op op_new_array FALLBACK
-    # op op_filled_new_array FALLBACK
-    # op op_filled_new_array_range FALLBACK
-    # op op_fill_array_data FALLBACK
-    # op op_throw FALLBACK
-    # op op_goto FALLBACK
-    # op op_goto_16 FALLBACK
-    # op op_goto_32 FALLBACK
-    # op op_packed_switch FALLBACK
-    # op op_sparse_switch FALLBACK
-    # op op_cmpl_float FALLBACK
-    # op op_cmpg_float FALLBACK
-    # op op_cmpl_double FALLBACK
-    # op op_cmpg_double FALLBACK
-    # op op_cmp_long FALLBACK
-    # op op_if_eq FALLBACK
-    # op op_if_ne FALLBACK
-    # op op_if_lt FALLBACK
-    # op op_if_ge FALLBACK
-    # op op_if_gt FALLBACK
-    # op op_if_le FALLBACK
-    # op op_if_eqz FALLBACK
-    # op op_if_nez FALLBACK
-    # op op_if_ltz FALLBACK
-    # op op_if_gez FALLBACK
-    # op op_if_gtz FALLBACK
-    # op op_if_lez FALLBACK
-    # op op_unused_3e FALLBACK
-    # op op_unused_3f FALLBACK
-    # op op_unused_40 FALLBACK
-    # op op_unused_41 FALLBACK
-    # op op_unused_42 FALLBACK
-    # op op_unused_43 FALLBACK
-    # op op_aget FALLBACK
-    # op op_aget_wide FALLBACK
-    # op op_aget_object FALLBACK
-    # op op_aget_boolean FALLBACK
-    # op op_aget_byte FALLBACK
-    # op op_aget_char FALLBACK
-    # op op_aget_short FALLBACK
-    # op op_aput FALLBACK
-    # op op_aput_wide FALLBACK
-    # op op_aput_object FALLBACK
-    # op op_aput_boolean FALLBACK
-    # op op_aput_byte FALLBACK
-    # op op_aput_char FALLBACK
-    # op op_aput_short FALLBACK
-    # op op_iget FALLBACK
-    # op op_iget_wide FALLBACK
-    # op op_iget_object FALLBACK
-    # op op_iget_boolean FALLBACK
-    # op op_iget_byte FALLBACK
-    # op op_iget_char FALLBACK
-    # op op_iget_short FALLBACK
-    # op op_iput FALLBACK
-    # op op_iput_wide FALLBACK
-    # op op_iput_object FALLBACK
-    # op op_iput_boolean FALLBACK
-    # op op_iput_byte FALLBACK
-    # op op_iput_char FALLBACK
-    # op op_iput_short FALLBACK
-    # op op_sget FALLBACK
-    # op op_sget_wide FALLBACK
-    # op op_sget_object FALLBACK
-    # op op_sget_boolean FALLBACK
-    # op op_sget_byte FALLBACK
-    # op op_sget_char FALLBACK
-    # op op_sget_short FALLBACK
-    # op op_sput FALLBACK
-    # op op_sput_wide FALLBACK
-    # op op_sput_object FALLBACK
-    # op op_sput_boolean FALLBACK
-    # op op_sput_byte FALLBACK
-    # op op_sput_char FALLBACK
-    # op op_sput_short FALLBACK
-    # op op_invoke_virtual FALLBACK
-    # op op_invoke_super FALLBACK
-    # op op_invoke_direct FALLBACK
-    # op op_invoke_static FALLBACK
-    # op op_invoke_interface FALLBACK
-    # op op_return_void_no_barrier FALLBACK
-    # op op_invoke_virtual_range FALLBACK
-    # op op_invoke_super_range FALLBACK
-    # op op_invoke_direct_range FALLBACK
-    # op op_invoke_static_range FALLBACK
-    # op op_invoke_interface_range FALLBACK
-    # op op_unused_79 FALLBACK
-    # op op_unused_7a FALLBACK
-    # op op_neg_int FALLBACK
-    # op op_not_int FALLBACK
-    # op op_neg_long FALLBACK
-    # op op_not_long FALLBACK
-    # op op_neg_float FALLBACK
-    # op op_neg_double FALLBACK
-    # op op_int_to_long FALLBACK
-    # op op_int_to_float FALLBACK
-    # op op_int_to_double FALLBACK
-    # op op_long_to_int FALLBACK
-    # op op_long_to_float FALLBACK
-    # op op_long_to_double FALLBACK
-    # op op_float_to_int FALLBACK
-    # op op_float_to_long FALLBACK
-    # op op_float_to_double FALLBACK
-    # op op_double_to_int FALLBACK
-    # op op_double_to_long FALLBACK
-    # op op_double_to_float FALLBACK
-    # op op_int_to_byte FALLBACK
-    # op op_int_to_char FALLBACK
-    # op op_int_to_short FALLBACK
-    # op op_add_int FALLBACK
-    # op op_sub_int FALLBACK
-    # op op_mul_int FALLBACK
-    # op op_div_int FALLBACK
-    # op op_rem_int FALLBACK
-    # op op_and_int FALLBACK
-    # op op_or_int FALLBACK
-    # op op_xor_int FALLBACK
-    # op op_shl_int FALLBACK
-    # op op_shr_int FALLBACK
-    # op op_ushr_int FALLBACK
-    # op op_add_long FALLBACK
-    # op op_sub_long FALLBACK
-    # op op_mul_long FALLBACK
-    # op op_div_long FALLBACK
-    # op op_rem_long FALLBACK
-    # op op_and_long FALLBACK
-    # op op_or_long FALLBACK
-    # op op_xor_long FALLBACK
-    # op op_shl_long FALLBACK
-    # op op_shr_long FALLBACK
-    # op op_ushr_long FALLBACK
-    # op op_add_float FALLBACK
-    # op op_sub_float FALLBACK
-    # op op_mul_float FALLBACK
-    # op op_div_float FALLBACK
-    # op op_rem_float FALLBACK
-    # op op_add_double FALLBACK
-    # op op_sub_double FALLBACK
-    # op op_mul_double FALLBACK
-    # op op_div_double FALLBACK
-    # op op_rem_double FALLBACK
-    # op op_add_int_2addr FALLBACK
-    # op op_sub_int_2addr FALLBACK
-    # op op_mul_int_2addr FALLBACK
-    # op op_div_int_2addr FALLBACK
-    # op op_rem_int_2addr FALLBACK
-    # op op_and_int_2addr FALLBACK
-    # op op_or_int_2addr FALLBACK
-    # op op_xor_int_2addr FALLBACK
-    # op op_shl_int_2addr FALLBACK
-    # op op_shr_int_2addr FALLBACK
-    # op op_ushr_int_2addr FALLBACK
-    # op op_add_long_2addr FALLBACK
-    # op op_sub_long_2addr FALLBACK
-    # op op_mul_long_2addr FALLBACK
-    # op op_div_long_2addr FALLBACK
-    # op op_rem_long_2addr FALLBACK
-    # op op_and_long_2addr FALLBACK
-    # op op_or_long_2addr FALLBACK
-    # op op_xor_long_2addr FALLBACK
-    # op op_shl_long_2addr FALLBACK
-    # op op_shr_long_2addr FALLBACK
-    # op op_ushr_long_2addr FALLBACK
-    # op op_add_float_2addr FALLBACK
-    # op op_sub_float_2addr FALLBACK
-    # op op_mul_float_2addr FALLBACK
-    # op op_div_float_2addr FALLBACK
-    # op op_rem_float_2addr FALLBACK
-    # op op_add_double_2addr FALLBACK
-    # op op_sub_double_2addr FALLBACK
-    # op op_mul_double_2addr FALLBACK
-    # op op_div_double_2addr FALLBACK
-    # op op_rem_double_2addr FALLBACK
-    # op op_add_int_lit16 FALLBACK
-    # op op_rsub_int FALLBACK
-    # op op_mul_int_lit16 FALLBACK
-    # op op_div_int_lit16 FALLBACK
-    # op op_rem_int_lit16 FALLBACK
-    # op op_and_int_lit16 FALLBACK
-    # op op_or_int_lit16 FALLBACK
-    # op op_xor_int_lit16 FALLBACK
-    # op op_add_int_lit8 FALLBACK
-    # op op_rsub_int_lit8 FALLBACK
-    # op op_mul_int_lit8 FALLBACK
-    # op op_div_int_lit8 FALLBACK
-    # op op_rem_int_lit8 FALLBACK
-    # op op_and_int_lit8 FALLBACK
-    # op op_or_int_lit8 FALLBACK
-    # op op_xor_int_lit8 FALLBACK
-    # op op_shl_int_lit8 FALLBACK
-    # op op_shr_int_lit8 FALLBACK
-    # op op_ushr_int_lit8 FALLBACK
-    # op op_iget_quick FALLBACK
-    # op op_iget_wide_quick FALLBACK
-    # op op_iget_object_quick FALLBACK
-    # op op_iput_quick FALLBACK
-    # op op_iput_wide_quick FALLBACK
-    # op op_iput_object_quick FALLBACK
-    # op op_invoke_virtual_quick FALLBACK
-    # op op_invoke_virtual_range_quick FALLBACK
-    # op op_iput_boolean_quick FALLBACK
-    # op op_iput_byte_quick FALLBACK
-    # op op_iput_char_quick FALLBACK
-    # op op_iput_short_quick FALLBACK
-    # op op_iget_boolean_quick FALLBACK
-    # op op_iget_byte_quick FALLBACK
-    # op op_iget_char_quick FALLBACK
-    # op op_iget_short_quick FALLBACK
-    # op op_unused_f3 FALLBACK
-    # op op_unused_f4 FALLBACK
-    # op op_unused_f5 FALLBACK
-    # op op_unused_f6 FALLBACK
-    # op op_unused_f7 FALLBACK
-    # op op_unused_f8 FALLBACK
-    # op op_unused_f9 FALLBACK
-    # op op_invoke_polymorphic FALLBACK
-    # op op_invoke_polymorphic_range FALLBACK
-    # op op_invoke_custom FALLBACK
-    # op op_invoke_custom_range FALLBACK
-    # op op_const_method_handle FALLBACK
-    # op op_const_method_type FALLBACK
-op-end
-
-# common subroutines for asm
-import x86/footer.S
diff --git a/runtime/interpreter/mterp/config_x86_64 b/runtime/interpreter/mterp/config_x86_64
deleted file mode 100644
index 89fbf43444dc6b18f1111073970a763a87064188..0000000000000000000000000000000000000000
--- a/runtime/interpreter/mterp/config_x86_64
+++ /dev/null
@@ -1,302 +0,0 @@
-# Copyright (C) 2015 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-#
-# Configuration for X86_64
-#
-
-handler-style computed-goto
-handler-size 128
-
-function-type-format FUNCTION_TYPE(%s)
-function-size-format SIZE(%s,%s)
-global-name-format SYMBOL(%s)
-
-# source for alternate entry stub
-asm-alt-stub x86_64/alt_stub.S
-
-# file header and basic definitions
-import x86_64/header.S
-
-# arch-specific entry point to interpreter
-import x86_64/entry.S
-
-# Stub to switch to alternate interpreter
-fallback-stub x86_64/fallback.S
-
-# opcode list; argument to op-start is default directory
-op-start x86_64
-    # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp
-    # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK
-
-    # op op_nop FALLBACK
-    # op op_move FALLBACK
-    # op op_move_from16 FALLBACK
-    # op op_move_16 FALLBACK
-    # op op_move_wide FALLBACK
-    # op op_move_wide_from16 FALLBACK
-    # op op_move_wide_16 FALLBACK
-    # op op_move_object FALLBACK
-    # op op_move_object_from16 FALLBACK
-    # op op_move_object_16 FALLBACK
-    # op op_move_result FALLBACK
-    # op op_move_result_wide FALLBACK
-    # op op_move_result_object FALLBACK
-    # op op_move_exception FALLBACK
-    # op op_return_void FALLBACK
-    # op op_return FALLBACK
-    # op op_return_wide FALLBACK
-    # op op_return_object FALLBACK
-    # op op_const_4 FALLBACK
-    # op op_const_16 FALLBACK
-    # op op_const FALLBACK
-    # op op_const_high16 FALLBACK
-    # op op_const_wide_16 FALLBACK
-    # op op_const_wide_32 FALLBACK
-    # op op_const_wide FALLBACK
-    # op op_const_wide_high16 FALLBACK
-    # op op_const_string FALLBACK
-    # op op_const_string_jumbo FALLBACK
-    # op op_const_class FALLBACK
-    # op op_monitor_enter FALLBACK
-    # op op_monitor_exit FALLBACK
-    # op op_check_cast FALLBACK
-    # op op_instance_of FALLBACK
-    # op op_array_length FALLBACK
-    # op op_new_instance FALLBACK
-    # op op_new_array FALLBACK
-    # op op_filled_new_array FALLBACK
-    # op op_filled_new_array_range FALLBACK
-    # op op_fill_array_data FALLBACK
-    # op op_throw FALLBACK
-    # op op_goto FALLBACK
-    # op op_goto_16 FALLBACK
-    # op op_goto_32 FALLBACK
-    # op op_packed_switch FALLBACK
-    # op op_sparse_switch FALLBACK
-    # op op_cmpl_float FALLBACK
-    # op op_cmpg_float FALLBACK
-    # op op_cmpl_double FALLBACK
-    # op op_cmpg_double FALLBACK
-    # op op_cmp_long FALLBACK
-    # op op_if_eq FALLBACK
-    # op op_if_ne FALLBACK
-    # op op_if_lt FALLBACK
-    # op op_if_ge FALLBACK
-    # op op_if_gt FALLBACK
-    # op op_if_le FALLBACK
-    # op op_if_eqz FALLBACK
-    # op op_if_nez FALLBACK
-    # op op_if_ltz FALLBACK
-    # op op_if_gez FALLBACK
-    # op op_if_gtz FALLBACK
-    # op op_if_lez FALLBACK
-    # op op_unused_3e FALLBACK
-    # op op_unused_3f FALLBACK
-    # op op_unused_40 FALLBACK
-    # op op_unused_41 FALLBACK
-    # op op_unused_42 FALLBACK
-    # op op_unused_43 FALLBACK
-    # op op_aget FALLBACK
-    # op op_aget_wide FALLBACK
-    # op op_aget_object FALLBACK
-    # op op_aget_boolean FALLBACK
-    # op op_aget_byte FALLBACK
-    # op op_aget_char FALLBACK
-    # op op_aget_short FALLBACK
-    # op op_aput FALLBACK
-    # op op_aput_wide FALLBACK
-    # op op_aput_object FALLBACK
-    # op op_aput_boolean FALLBACK
-    # op op_aput_byte FALLBACK
-    # op op_aput_char FALLBACK
-    # op op_aput_short FALLBACK
-    # op op_iget FALLBACK
-    # op op_iget_wide FALLBACK
-    # op op_iget_object FALLBACK
-    # op op_iget_boolean FALLBACK
-    # op op_iget_byte FALLBACK
-    # op op_iget_char FALLBACK
-    # op op_iget_short FALLBACK
-    # op op_iput FALLBACK
-    # op op_iput_wide FALLBACK
-    # op op_iput_object FALLBACK
-    # op op_iput_boolean FALLBACK
-    # op op_iput_byte FALLBACK
-    # op op_iput_char FALLBACK
-    # op op_iput_short FALLBACK
-    # op op_sget FALLBACK
-    # op op_sget_wide FALLBACK
-    # op op_sget_object FALLBACK
-    # op op_sget_boolean FALLBACK
-    # op op_sget_byte FALLBACK
-    # op op_sget_char FALLBACK
-    # op op_sget_short FALLBACK
-    # op op_sput FALLBACK
-    # op op_sput_wide FALLBACK
-    # op op_sput_object FALLBACK
-    # op op_sput_boolean FALLBACK
-    # op op_sput_byte FALLBACK
-    # op op_sput_char FALLBACK
-    # op op_sput_short FALLBACK
-    # op op_invoke_virtual FALLBACK
-    # op op_invoke_super FALLBACK
-    # op op_invoke_direct FALLBACK
-    # op op_invoke_static FALLBACK
-    # op op_invoke_interface FALLBACK
-    # op op_return_void_no_barrier FALLBACK
-    # op op_invoke_virtual_range FALLBACK
-    # op op_invoke_super_range FALLBACK
-    # op op_invoke_direct_range FALLBACK
-    # op op_invoke_static_range FALLBACK
-    # op op_invoke_interface_range FALLBACK
-    # op op_unused_79 FALLBACK
-    # op op_unused_7a FALLBACK
-    # op op_neg_int FALLBACK
-    # op op_not_int FALLBACK
-    # op op_neg_long FALLBACK
-    # op op_not_long FALLBACK
-    # op op_neg_float FALLBACK
-    # op op_neg_double FALLBACK
-    # op op_int_to_long FALLBACK
-    # op op_int_to_float FALLBACK
-    # op op_int_to_double FALLBACK
-    # op op_long_to_int FALLBACK
-    # op op_long_to_float FALLBACK
-    # op op_long_to_double FALLBACK
-    # op op_float_to_int FALLBACK
-    # op op_float_to_long FALLBACK
-    # op op_float_to_double FALLBACK
-    # op op_double_to_int FALLBACK
-    # op op_double_to_long FALLBACK
-    # op op_double_to_float FALLBACK
-    # op op_int_to_byte FALLBACK
-    # op op_int_to_char FALLBACK
-    # op op_int_to_short FALLBACK
-    # op op_add_int FALLBACK
-    # op op_sub_int FALLBACK
-    # op op_mul_int FALLBACK
-    # op op_div_int FALLBACK
-    # op op_rem_int FALLBACK
-    # op op_and_int FALLBACK
-    # op op_or_int FALLBACK
-    # op op_xor_int FALLBACK
-    # op op_shl_int FALLBACK
-    # op op_shr_int FALLBACK
-    # op op_ushr_int FALLBACK
-    # op op_add_long FALLBACK
-    # op op_sub_long FALLBACK
-    # op op_mul_long FALLBACK
-    # op op_div_long FALLBACK
-    # op op_rem_long FALLBACK
-    # op op_and_long FALLBACK
-    # op op_or_long FALLBACK
-    # op op_xor_long FALLBACK
-    # op op_shl_long FALLBACK
-    # op op_shr_long FALLBACK
-    # op op_ushr_long FALLBACK
-    # op op_add_float FALLBACK
-    # op op_sub_float FALLBACK
-    # op op_mul_float FALLBACK
-    # op op_div_float FALLBACK
-    # op op_rem_float FALLBACK
-    # op op_add_double FALLBACK
-    # op op_sub_double FALLBACK
-    # op op_mul_double FALLBACK
-    # op op_div_double FALLBACK
-    # op op_rem_double FALLBACK
-    # op op_add_int_2addr FALLBACK
-    # op op_sub_int_2addr FALLBACK
-    # op op_mul_int_2addr FALLBACK
-    # op op_div_int_2addr FALLBACK
-    # op op_rem_int_2addr FALLBACK
-    # op op_and_int_2addr FALLBACK
-    # op op_or_int_2addr FALLBACK
-    # op op_xor_int_2addr FALLBACK
-    # op op_shl_int_2addr FALLBACK
-    # op op_shr_int_2addr FALLBACK
-    # op op_ushr_int_2addr FALLBACK
-    # op op_add_long_2addr FALLBACK
-    # op op_sub_long_2addr FALLBACK
-    # op op_mul_long_2addr FALLBACK
-    # op op_div_long_2addr FALLBACK
-    # op op_rem_long_2addr FALLBACK
-    # op op_and_long_2addr FALLBACK
-    # op op_or_long_2addr FALLBACK
-    # op op_xor_long_2addr FALLBACK
-    # op op_shl_long_2addr FALLBACK
-    # op op_shr_long_2addr FALLBACK
-    # op op_ushr_long_2addr FALLBACK
-    # op op_add_float_2addr FALLBACK
-    # op op_sub_float_2addr FALLBACK
-    # op op_mul_float_2addr FALLBACK
-    # op op_div_float_2addr FALLBACK
-    # op op_rem_float_2addr FALLBACK
-    # op op_add_double_2addr FALLBACK
-    # op op_sub_double_2addr FALLBACK
-    # op op_mul_double_2addr FALLBACK
-    # op op_div_double_2addr FALLBACK
-    # op op_rem_double_2addr FALLBACK
-    # op op_add_int_lit16 FALLBACK
-    # op op_rsub_int FALLBACK
-    # op op_mul_int_lit16 FALLBACK
-    # op op_div_int_lit16 FALLBACK
-    # op op_rem_int_lit16 FALLBACK
-    # op op_and_int_lit16 FALLBACK
-    # op op_or_int_lit16 FALLBACK
-    # op op_xor_int_lit16 FALLBACK
-    # op op_add_int_lit8 FALLBACK
-    # op op_rsub_int_lit8 FALLBACK
-    # op op_mul_int_lit8 FALLBACK
-    # op op_div_int_lit8 FALLBACK
-    # op op_rem_int_lit8 FALLBACK
-    # op op_and_int_lit8 FALLBACK
-    # op op_or_int_lit8 FALLBACK
-    # op op_xor_int_lit8 FALLBACK
-    # op op_shl_int_lit8 FALLBACK
-    # op op_shr_int_lit8 FALLBACK
-    # op op_ushr_int_lit8 FALLBACK
-    # op op_iget_quick FALLBACK
-    # op op_iget_wide_quick FALLBACK
-    # op op_iget_object_quick FALLBACK
-    # op op_iput_quick FALLBACK
-    # op op_iput_wide_quick FALLBACK
-    # op op_iput_object_quick FALLBACK
-    # op op_invoke_virtual_quick FALLBACK
-    # op op_invoke_virtual_range_quick FALLBACK
-    # op op_iput_boolean_quick FALLBACK
-    # op op_iput_byte_quick FALLBACK
-    # op op_iput_char_quick FALLBACK
-    # op op_iput_short_quick FALLBACK
-    # op op_iget_boolean_quick FALLBACK
-    # op op_iget_byte_quick FALLBACK
-    # op op_iget_char_quick FALLBACK
-    # op op_iget_short_quick FALLBACK
-    # op op_unused_f3 FALLBACK
-    # op op_unused_f4 FALLBACK
-    # op op_unused_f5 FALLBACK
-    # op op_unused_f6 FALLBACK
-    # op op_unused_f7 FALLBACK
-    # op op_unused_f8 FALLBACK
-    # op op_unused_f9 FALLBACK
-    # op op_invoke_polymorphic FALLBACK
-    # op op_invoke_polymorphic_range FALLBACK
-    # op op_invoke_custom FALLBACK
-    # op op_invoke_custom_range FALLBACK
-    # op op_const_method_handle FALLBACK
-    # op op_const_method_type FALLBACK
-op-end
-
-# common subroutines for asm
-import x86_64/footer.S
diff --git a/runtime/interpreter/mterp/gen_mterp.py b/runtime/interpreter/mterp/gen_mterp.py
index 75c5174bcbc487cc29639c0b7f9620d4b5e71130..cf69bcecc3db38f13f56d177b46636e11827cb5e 100755
--- a/runtime/interpreter/mterp/gen_mterp.py
+++ b/runtime/interpreter/mterp/gen_mterp.py
@@ -14,605 +14,108 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-#
-# Using instructions from an architecture-specific config file, generate C
-# and assembly source files for the Dalvik interpreter.
-#
-
-import sys, string, re, time
-from string import Template
-
-interp_defs_file = "../../../libdexfile/dex/dex_instruction_list.h" # need opcode list
-kNumPackedOpcodes = 256
-
-splitops = False
-verbose = False
-handler_size_bits = -1000
-handler_size_bytes = -1000
-in_op_start = 0             # 0=not started, 1=started, 2=ended
-in_alt_op_start = 0         # 0=not started, 1=started, 2=ended
-default_op_dir = None
-default_alt_stub = None
-opcode_locations = {}
-alt_opcode_locations = {}
-asm_stub_text = []
-fallback_stub_text = []
-label_prefix = ".L"         # use ".L" to hide labels from gdb
-alt_label_prefix = ".L_ALT" # use ".L" to hide labels from gdb
-style = None                # interpreter style
-generate_alt_table = False
-function_type_format = ".type   %s, %%function"
-function_size_format = ".size   %s, .-%s"
-global_name_format = "%s"
-
-# Exception class.
-class DataParseError(SyntaxError):
-    "Failure when parsing data file"
-
-#
-# Set any omnipresent substitution values.
-#
-def getGlobalSubDict():
-    return { "handler_size_bits":handler_size_bits,
-             "handler_size_bytes":handler_size_bytes }
-
-#
-# Parse arch config file --
-# Set interpreter style.
-#
-def setHandlerStyle(tokens):
-    global style
-    if len(tokens) != 2:
-        raise DataParseError("handler-style requires one argument")
-    style = tokens[1]
-    if style != "computed-goto":
-        raise DataParseError("handler-style (%s) invalid" % style)
-
-#
-# Parse arch config file --
-# Set handler_size_bytes to the value of tokens[1], and handler_size_bits to
-# log2(handler_size_bytes).  Throws an exception if "bytes" is not 0 or
-# a power of two.
-#
-def setHandlerSize(tokens):
-    global handler_size_bits, handler_size_bytes
-    if style != "computed-goto":
-        print "Warning: handler-size valid only for computed-goto interpreters"
-    if len(tokens) != 2:
-        raise DataParseError("handler-size requires one argument")
-    if handler_size_bits != -1000:
-        raise DataParseError("handler-size may only be set once")
-
-    # compute log2(n), and make sure n is 0 or a power of 2
-    handler_size_bytes = bytes = int(tokens[1])
-    bits = -1
-    while bytes > 0:
-        bytes //= 2     # halve with truncating division
-        bits += 1
-
-    if handler_size_bytes == 0 or handler_size_bytes != (1 << bits):
-        raise DataParseError("handler-size (%d) must be power of 2" \
-                % orig_bytes)
-    handler_size_bits = bits
-
-#
-# Parse arch config file --
-# Copy a file in to asm output file.
-#
-def importFile(tokens):
-    if len(tokens) != 2:
-        raise DataParseError("import requires one argument")
-    source = tokens[1]
-    if source.endswith(".S"):
-        appendSourceFile(tokens[1], getGlobalSubDict(), asm_fp, None)
-    else:
-        raise DataParseError("don't know how to import %s (expecting .cpp/.S)"
-                % source)
-
-#
-# Parse arch config file --
-# Copy a file in to the C or asm output file.
-#
-def setAsmStub(tokens):
-    global asm_stub_text
-    if len(tokens) != 2:
-        raise DataParseError("import requires one argument")
-    try:
-        stub_fp = open(tokens[1])
-        asm_stub_text = stub_fp.readlines()
-    except IOError, err:
-        stub_fp.close()
-        raise DataParseError("unable to load asm-stub: %s" % str(err))
-    stub_fp.close()
-
-#
-# Parse arch config file --
-# Copy a file in to the C or asm output file.
-#
-def setFallbackStub(tokens):
-    global fallback_stub_text
-    if len(tokens) != 2:
-        raise DataParseError("import requires one argument")
-    try:
-        stub_fp = open(tokens[1])
-        fallback_stub_text = stub_fp.readlines()
-    except IOError, err:
-        stub_fp.close()
-        raise DataParseError("unable to load fallback-stub: %s" % str(err))
-    stub_fp.close()
-#
-# Parse arch config file --
-# Record location of default alt stub
-#
-def setAsmAltStub(tokens):
-    global default_alt_stub, generate_alt_table
-    if len(tokens) != 2:
-        raise DataParseError("import requires one argument")
-    default_alt_stub = tokens[1]
-    generate_alt_table = True
-#
-# Change the default function type format
-#
-def setFunctionTypeFormat(tokens):
-    global function_type_format
-    function_type_format = tokens[1]
-#
-# Change the default function size format
-#
-def setFunctionSizeFormat(tokens):
-    global function_size_format
-    function_size_format = tokens[1]
-#
-# Change the global name format
-#
-def setGlobalNameFormat(tokens):
-    global global_name_format
-    global_name_format = tokens[1]
-#
-# Parse arch config file --
-# Start of opcode list.
-#
-def opStart(tokens):
-    global in_op_start
-    global default_op_dir
-    if len(tokens) != 2:
-        raise DataParseError("opStart takes a directory name argument")
-    if in_op_start != 0:
-        raise DataParseError("opStart can only be specified once")
-    default_op_dir = tokens[1]
-    in_op_start = 1
+import sys, re
+from os import listdir
+from cStringIO import StringIO
 
-#
-# Parse arch config file --
-# Set location of a single alt opcode's source file.
-#
-def altEntry(tokens):
-    global generate_alt_table
-    if len(tokens) != 3:
-        raise DataParseError("alt requires exactly two arguments")
-    if in_op_start != 1:
-        raise DataParseError("alt statements must be between opStart/opEnd")
-    try:
-        index = opcodes.index(tokens[1])
-    except ValueError:
-        raise DataParseError("unknown opcode %s" % tokens[1])
-    if alt_opcode_locations.has_key(tokens[1]):
-        print "Note: alt overrides earlier %s (%s -> %s)" \
-                % (tokens[1], alt_opcode_locations[tokens[1]], tokens[2])
-    alt_opcode_locations[tokens[1]] = tokens[2]
-    generate_alt_table = True
+# This file is included verbatim at the start of the in-memory python script.
+SCRIPT_SETUP_CODE = "common/gen_setup.py"
 
-#
-# Parse arch config file --
-# Set location of a single opcode's source file.
-#
-def opEntry(tokens):
-    #global opcode_locations
-    if len(tokens) != 3:
-        raise DataParseError("op requires exactly two arguments")
-    if in_op_start != 1:
-        raise DataParseError("op statements must be between opStart/opEnd")
-    try:
-        index = opcodes.index(tokens[1])
-    except ValueError:
-        raise DataParseError("unknown opcode %s" % tokens[1])
-    if opcode_locations.has_key(tokens[1]):
-        print "Note: op overrides earlier %s (%s -> %s)" \
-                % (tokens[1], opcode_locations[tokens[1]], tokens[2])
-    opcode_locations[tokens[1]] = tokens[2]
+INTERP_DEFS_FILE = "../../../libdexfile/dex/dex_instruction_list.h" # need opcode list
+NUM_PACKED_OPCODES = 256
 
-#
-# Parse arch config file --
-# End of opcode list; emit instruction blocks.
-#
-def opEnd(tokens):
-    global in_op_start
-    if len(tokens) != 1:
-        raise DataParseError("opEnd takes no arguments")
-    if in_op_start != 1:
-        raise DataParseError("opEnd must follow opStart, and only appear once")
-    in_op_start = 2
-
-    loadAndEmitOpcodes()
-    if splitops == False:
-        if generate_alt_table:
-            loadAndEmitAltOpcodes()
-
-def genaltop(tokens):
-    if in_op_start != 2:
-       raise DataParseError("alt-op can be specified only after op-end")
-    if len(tokens) != 1:
-        raise DataParseError("opEnd takes no arguments")
-    if generate_alt_table:
-        loadAndEmitAltOpcodes()
-
-#
 # Extract an ordered list of instructions from the VM sources.  We use the
-# "goto table" definition macro, which has exactly kNumPackedOpcodes
-# entries.
-#
+# "goto table" definition macro, which has exactly NUM_PACKED_OPCODES entries.
 def getOpcodeList():
-    opcodes = []
-    opcode_fp = open(interp_defs_file)
-    opcode_re = re.compile(r"^\s*V\((....), (\w+),.*", re.DOTALL)
-    for line in opcode_fp:
-        match = opcode_re.match(line)
-        if not match:
-            continue
-        opcodes.append("op_" + match.group(2).lower())
-    opcode_fp.close()
-
-    if len(opcodes) != kNumPackedOpcodes:
-        print "ERROR: found %d opcodes in Interp.h (expected %d)" \
-                % (len(opcodes), kNumPackedOpcodes)
-        raise SyntaxError, "bad opcode count"
-    return opcodes
-
-def emitAlign():
-    if style == "computed-goto":
-        asm_fp.write("    .balign %d\n" % handler_size_bytes)
-
-#
-# Load and emit opcodes for all kNumPackedOpcodes instructions.
-#
-def loadAndEmitOpcodes():
-    sister_list = []
-    assert len(opcodes) == kNumPackedOpcodes
-    need_dummy_start = False
-
-    loadAndEmitGenericAsm("instruction_start")
-
-    for i in xrange(kNumPackedOpcodes):
-        op = opcodes[i]
-
-        if opcode_locations.has_key(op):
-            location = opcode_locations[op]
-        else:
-            location = default_op_dir
-
-        if location == "FALLBACK":
-            emitFallback(i)
-        else:
-            loadAndEmitAsm(location, i, sister_list)
-
-    # For a 100% C implementation, there are no asm handlers or stubs.  We
-    # need to have the MterpAsmInstructionStart label point at op_nop, and it's
-    # too annoying to try to slide it in after the alignment psuedo-op, so
-    # we take the low road and just emit a dummy op_nop here.
-    if need_dummy_start:
-        emitAlign()
-        asm_fp.write(label_prefix + "_op_nop:   /* dummy */\n");
-
-    emitAlign()
-
-    loadAndEmitGenericAsm("instruction_end")
-
-    if style == "computed-goto":
-        emitSectionComment("Sister implementations", asm_fp)
-        loadAndEmitGenericAsm("instruction_start_sister")
-        asm_fp.writelines(sister_list)
-        loadAndEmitGenericAsm("instruction_end_sister")
-
-#
-# Load an alternate entry stub
-#
-def loadAndEmitAltStub(source, opindex):
-    op = opcodes[opindex]
-    if verbose:
-        print " alt emit %s --> stub" % source
-    dict = getGlobalSubDict()
-    dict.update({ "opcode":op, "opnum":opindex })
-
-    emitAsmHeader(asm_fp, dict, alt_label_prefix)
-    appendSourceFile(source, dict, asm_fp, None)
-
-#
-# Load and emit alternate opcodes for all kNumPackedOpcodes instructions.
-#
-def loadAndEmitAltOpcodes():
-    assert len(opcodes) == kNumPackedOpcodes
-    start_label = global_name_format % "artMterpAsmAltInstructionStart"
-    end_label = global_name_format % "artMterpAsmAltInstructionEnd"
-
-    loadAndEmitGenericAsm("instruction_start_alt")
-
-    for i in xrange(kNumPackedOpcodes):
-        op = opcodes[i]
-        if alt_opcode_locations.has_key(op):
-            source = "%s/alt_%s.S" % (alt_opcode_locations[op], op)
-        else:
-            source = default_alt_stub
-        loadAndEmitAltStub(source, i)
-
-    emitAlign()
-
-    loadAndEmitGenericAsm("instruction_end_alt")
-
-#
-# Load an assembly fragment and emit it.
-#
-def loadAndEmitAsm(location, opindex, sister_list):
-    op = opcodes[opindex]
-    source = "%s/%s.S" % (location, op)
-    dict = getGlobalSubDict()
-    dict.update({ "opcode":op, "opnum":opindex })
-    if verbose:
-        print " emit %s --> asm" % source
-
-    emitAsmHeader(asm_fp, dict, label_prefix)
-    appendSourceFile(source, dict, asm_fp, sister_list)
-
-#
-# Load a non-handler assembly fragment and emit it.
-#
-def loadAndEmitGenericAsm(name):
-    source = "%s/%s.S" % (default_op_dir, name)
-    dict = getGlobalSubDict()
-    appendSourceFile(source, dict, asm_fp, None)
-
-#
-# Emit fallback fragment
-#
-def emitFallback(opindex):
-    op = opcodes[opindex]
-    dict = getGlobalSubDict()
-    dict.update({ "opcode":op, "opnum":opindex })
-    emitAsmHeader(asm_fp, dict, label_prefix)
-    for line in fallback_stub_text:
-        asm_fp.write(line)
-    asm_fp.write("\n")
-
-#
-# Output the alignment directive and label for an assembly piece.
-#
-def emitAsmHeader(outfp, dict, prefix):
-    outfp.write("/* ------------------------------ */\n")
-    # The alignment directive ensures that the handler occupies
-    # at least the correct amount of space.  We don't try to deal
-    # with overflow here.
-    emitAlign()
-    # Emit a label so that gdb will say the right thing.  We prepend an
-    # underscore so the symbol name doesn't clash with the Opcode enum.
-    outfp.write(prefix + "_%(opcode)s: /* 0x%(opnum)02x */\n" % dict)
-
-#
-# Output a generic instruction stub that updates the "glue" struct and
-# calls the C implementation.
-#
-def emitAsmStub(outfp, dict):
-    emitAsmHeader(outfp, dict, label_prefix)
-    for line in asm_stub_text:
-        templ = Template(line)
-        outfp.write(templ.substitute(dict))
-
-#
-# Append the file specified by "source" to the open "outfp".  Each line will
-# be template-replaced using the substitution dictionary "dict".
-#
-# If the first line of the file starts with "%" it is taken as a directive.
-# A "%include" line contains a filename and, optionally, a Python-style
-# dictionary declaration with substitution strings.  (This is implemented
-# with recursion.)
-#
-# If "sister_list" is provided, and we find a line that contains only "&",
-# all subsequent lines from the file will be appended to sister_list instead
-# of copied to the output.
-#
-# This may modify "dict".
-#
-def appendSourceFile(source, dict, outfp, sister_list):
-    outfp.write("/* File: %s */\n" % source)
-    infp = open(source, "r")
-    in_sister = False
-    for line in infp:
-        if line.startswith("%include"):
-            # Parse the "include" line
-            tokens = line.strip().split(' ', 2)
-            if len(tokens) < 2:
-                raise DataParseError("malformed %%include in %s" % source)
-
-            alt_source = tokens[1].strip("\"")
-            if alt_source == source:
-                raise DataParseError("self-referential %%include in %s"
-                        % source)
-
-            new_dict = dict.copy()
-            if len(tokens) == 3:
-                new_dict.update(eval(tokens[2]))
-            #print " including src=%s dict=%s" % (alt_source, new_dict)
-            appendSourceFile(alt_source, new_dict, outfp, sister_list)
-            continue
-
-        elif line.startswith("%default"):
-            # copy keywords into dictionary
-            tokens = line.strip().split(' ', 1)
-            if len(tokens) < 2:
-                raise DataParseError("malformed %%default in %s" % source)
-            defaultValues = eval(tokens[1])
-            for entry in defaultValues:
-                dict.setdefault(entry, defaultValues[entry])
-            continue
-
-        elif line.startswith("%break") and sister_list != None:
-            # allow more than one %break, ignoring all following the first
-            if style == "computed-goto" and not in_sister:
-                in_sister = True
-                sister_list.append("\n/* continuation for %(opcode)s */\n"%dict)
-            continue
-
-        # perform keyword substitution if a dictionary was provided
-        if dict != None:
-            templ = Template(line)
-            try:
-                subline = templ.substitute(dict)
-            except KeyError, err:
-                raise DataParseError("keyword substitution failed in %s: %s"
-                        % (source, str(err)))
-            except:
-                print "ERROR: substitution failed: " + line
-                raise
-        else:
-            subline = line
-
-        # write output to appropriate file
-        if in_sister:
-            sister_list.append(subline)
-        else:
-            outfp.write(subline)
-    outfp.write("\n")
-    infp.close()
-
-#
-# Emit a C-style section header comment.
-#
-def emitSectionComment(str, fp):
-    equals = "========================================" \
-             "==================================="
-
-    fp.write("\n/*\n * %s\n *  %s\n * %s\n */\n" %
-        (equals, str, equals))
-
-
-#
-# ===========================================================================
-# "main" code
-#
-
-#
-# Check args.
-#
-if len(sys.argv) != 3:
-    print "Usage: %s target-arch output-dir" % sys.argv[0]
-    sys.exit(2)
-
-target_arch = sys.argv[1]
-output_dir = sys.argv[2]
-
-#
-# Extract opcode list.
-#
-opcodes = getOpcodeList()
-#for op in opcodes:
-#    print "  %s" % op
-
-#
-# Open config file.
-#
-try:
-    config_fp = open("config_%s" % target_arch)
-except:
-    print "Unable to open config file 'config_%s'" % target_arch
-    sys.exit(1)
-
-#
-# Open and prepare output files.
-#
-try:
-    asm_fp = open("%s/mterp_%s.S" % (output_dir, target_arch), "w")
-except:
-    print "Unable to open output files"
-    print "Make sure directory '%s' exists and existing files are writable" \
-            % output_dir
-    # Ideally we'd remove the files to avoid confusing "make", but if they
-    # failed to open we probably won't be able to remove them either.
-    sys.exit(1)
-
-print "Generating %s" % (asm_fp.name)
-
-file_header = """/*
- * This file was generated automatically by gen-mterp.py for '%s'.
- *
- * --> DO NOT EDIT <--
- */
-
-""" % (target_arch)
-
-asm_fp.write(file_header)
-
-#
-# Process the config file.
-#
-failed = False
-try:
-    for line in config_fp:
-        line = line.strip()         # remove CRLF, leading spaces
-        tokens = line.split(' ')    # tokenize
-        #print "%d: %s" % (len(tokens), tokens)
-        if len(tokens[0]) == 0:
-            #print "  blank"
-            pass
-        elif tokens[0][0] == '#':
-            #print "  comment"
-            pass
-        else:
-            if tokens[0] == "handler-size":
-                setHandlerSize(tokens)
-            elif tokens[0] == "import":
-                importFile(tokens)
-            elif tokens[0] == "asm-stub":
-                setAsmStub(tokens)
-            elif tokens[0] == "asm-alt-stub":
-                setAsmAltStub(tokens)
-            elif tokens[0] == "op-start":
-                opStart(tokens)
-            elif tokens[0] == "op-end":
-                opEnd(tokens)
-            elif tokens[0] == "alt":
-                altEntry(tokens)
-            elif tokens[0] == "op":
-                opEntry(tokens)
-            elif tokens[0] == "handler-style":
-                setHandlerStyle(tokens)
-            elif tokens[0] == "alt-ops":
-                genaltop(tokens)
-            elif tokens[0] == "split-ops":
-                splitops = True
-            elif tokens[0] == "fallback-stub":
-               setFallbackStub(tokens)
-            elif tokens[0] == "function-type-format":
-               setFunctionTypeFormat(tokens)
-            elif tokens[0] == "function-size-format":
-               setFunctionSizeFormat(tokens)
-            elif tokens[0] == "global-name-format":
-               setGlobalNameFormat(tokens)
-            else:
-                raise DataParseError, "unrecognized command '%s'" % tokens[0]
-            if style == None:
-                print "tokens[0] = %s" % tokens[0]
-                raise DataParseError, "handler-style must be first command"
-except DataParseError, err:
-    print "Failed: " + str(err)
-    # TODO: remove output files so "make" doesn't get confused
-    failed = True
-    asm_fp.close()
-    asm_fp = None
-
-config_fp.close()
-
-#
-# Done!
-#
-if asm_fp:
-    asm_fp.close()
-
-sys.exit(failed)
+  opcodes = []
+  opcode_fp = open(INTERP_DEFS_FILE)
+  opcode_re = re.compile(r"^\s*V\((....), (\w+),.*", re.DOTALL)
+  for line in opcode_fp:
+    match = opcode_re.match(line)
+    if not match:
+      continue
+    opcodes.append("op_" + match.group(2).lower())
+  opcode_fp.close()
+
+  if len(opcodes) != NUM_PACKED_OPCODES:
+    print "ERROR: found %d opcodes in Interp.h (expected %d)" \
+        % (len(opcodes), NUM_PACKED_OPCODES)
+    raise SyntaxError, "bad opcode count"
+  return opcodes
+
+indent_re = re.compile(r"^%( *)")
+
+# Finds variable references in text: $foo or ${foo}
+escape_re = re.compile(r'''
+  (?<!\$)        # Look-back: must not be preceded by another $.
+  \$
+  (\{)?          # May be enclosed by { } pair.
+  (?P<name>\w+)  # Save the symbol in named group.
+  (?(1)\})       # Expect } if and only if { was present.
+''', re.VERBOSE)
+
+def generate_script(arch, setup_code):
+  # Create new python script and write the initial setup code.
+  script = StringIO()  # File-like in-memory buffer.
+  script.write("# DO NOT EDIT: This file was generated by gen-mterp.py.\n")
+  script.write('arch = "' + arch + '"\n')
+  script.write(setup_code)
+  opcodes = getOpcodeList()
+  script.write("def opcodes(is_alt):\n")
+  for i in xrange(NUM_PACKED_OPCODES):
+    script.write('  write_opcode({0}, "{1}", {1}, is_alt)\n'.format(i, opcodes[i]))
+
+  # Find all template files and translate them into python code.
+  files = listdir(arch)
+  for file in sorted(files):
+    f = open(arch + "/" + file, "r")
+    indent = ""
+    for line in f.readlines():
+      line = line.rstrip()
+      if line.startswith("%"):
+        script.write(line.lstrip("%") + "\n")
+        indent = indent_re.match(line).group(1)
+        if line.endswith(":"):
+          indent += "  "
+      else:
+        line = escape_re.sub(r"''' + \g<name> + '''", line)
+        line = line.replace("\\", "\\\\")
+        line = line.replace("$$", "$")
+        script.write(indent + "write_line('''" + line + "''')\n")
+    script.write("\n")
+    f.close()
+
+  # TODO: Remove the concept of sister snippets. It is barely used.
+  script.write("def write_sister():\n")
+  if arch == "arm":
+    script.write("  op_float_to_long_sister_code()\n")
+    script.write("  op_double_to_long_sister_code()\n")
+  if arch == "mips":
+    script.write("  global opnum, opcode\n")
+    names = [
+      "op_float_to_long",
+      "op_double_to_long",
+      "op_mul_long",
+      "op_shl_long",
+      "op_shr_long",
+      "op_ushr_long",
+      "op_shl_long_2addr",
+      "op_shr_long_2addr",
+      "op_ushr_long_2addr"
+    ]
+    for name in names:
+      script.write('  opcode = "' + name + '"\n')
+      script.write("  " + name + "_sister_code()\n")
+  script.write("  pass\n")
+
+  script.write('generate()\n')
+  script.seek(0)
+  return script.read()
+
+# Generate the script for each architecture and execute it.
+for arch in ["arm", "arm64", "mips", "mips64", "x86", "x86_64"]:
+  with open(SCRIPT_SETUP_CODE, "r") as setup_code_file:
+    script = generate_script(arch, setup_code_file.read())
+  filename = "out/mterp_" + arch + ".py"  # Name to report in error messages.
+  # open(filename, "w").write(script)  # Write the script to disk for debugging.
+  exec(compile(script, filename, mode='exec'))
diff --git a/runtime/interpreter/mterp/mips/alt_stub.S b/runtime/interpreter/mterp/mips/alt_stub.S
index de133136e00768f720e36a256c1a1a9e2aba41ed..1ce75617a0fbe30a22227a0160059b7e647a1eb8 100644
--- a/runtime/interpreter/mterp/mips/alt_stub.S
+++ b/runtime/interpreter/mterp/mips/alt_stub.S
@@ -1,3 +1,4 @@
+%def alt_stub():
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
diff --git a/runtime/interpreter/mterp/mips/bincmp.S b/runtime/interpreter/mterp/mips/bincmp.S
index 68df5c3ff09c1a7288fc6531b6cb5d8befa2a7b3..b4b671fd9532c49bb8e8513d720f7f8ec2827d50 100644
--- a/runtime/interpreter/mterp/mips/bincmp.S
+++ b/runtime/interpreter/mterp/mips/bincmp.S
@@ -1,3 +1,4 @@
+%def bincmp(condition=""):
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
diff --git a/runtime/interpreter/mterp/mips/binop.S b/runtime/interpreter/mterp/mips/binop.S
index 862d95a736560f5aa68d7c7aa6ef2cff02456688..062b22da878a25aab2d395575c9b517d8baf86dc 100644
--- a/runtime/interpreter/mterp/mips/binop.S
+++ b/runtime/interpreter/mterp/mips/binop.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"a0", "chkzero":"0"}
+%def binop(preinstr="", result="a0", chkzero="0", instr=""):
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
diff --git a/runtime/interpreter/mterp/mips/binop2addr.S b/runtime/interpreter/mterp/mips/binop2addr.S
index 17aa8eba220f3ebb05401764903cab306fe7d2f9..89af6e1eea82b61cfa46c2049c481a1b74c07a5f 100644
--- a/runtime/interpreter/mterp/mips/binop2addr.S
+++ b/runtime/interpreter/mterp/mips/binop2addr.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"a0", "chkzero":"0"}
+%def binop2addr(preinstr="", result="a0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
diff --git a/runtime/interpreter/mterp/mips/binopLit16.S b/runtime/interpreter/mterp/mips/binopLit16.S
index 0696e7ab9296c1564d49719ef2e68a194fa9f7f4..9ae0da79e913809867031849e6c5c96442f06476 100644
--- a/runtime/interpreter/mterp/mips/binopLit16.S
+++ b/runtime/interpreter/mterp/mips/binopLit16.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"a0", "chkzero":"0"}
+%def binopLit16(preinstr="", result="a0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
diff --git a/runtime/interpreter/mterp/mips/binopLit8.S b/runtime/interpreter/mterp/mips/binopLit8.S
index 382dd2b4cdaf6c70477c627865a58946ccab70e7..ecf08c2d0cd48b8ce6e8ef06b83b38b436955409 100644
--- a/runtime/interpreter/mterp/mips/binopLit8.S
+++ b/runtime/interpreter/mterp/mips/binopLit8.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"a0", "chkzero":"0"}
+%def binopLit8(preinstr="", result="a0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
diff --git a/runtime/interpreter/mterp/mips/binopWide.S b/runtime/interpreter/mterp/mips/binopWide.S
index 604134d25293d9354e7248574ca0d8f8a36068b9..5768e95c489f6cf3bb4950e68af2390457821f03 100644
--- a/runtime/interpreter/mterp/mips/binopWide.S
+++ b/runtime/interpreter/mterp/mips/binopWide.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result0":"a0", "result1":"a1", "chkzero":"0", "arg0":"a0", "arg1":"a1", "arg2":"a2", "arg3":"a3"}
+%def binopWide(preinstr="", result0="a0", result1="a1", chkzero="0", arg0="a0", arg1="a1", arg2="a2", arg3="a3", instr=""):
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0-a1 op a2-a3".
diff --git a/runtime/interpreter/mterp/mips/binopWide2addr.S b/runtime/interpreter/mterp/mips/binopWide2addr.S
index f96fdb23f07b60da064feb66f220fd89c3e3e3db..4e00c81961eb5aaa4ccadad70a33b2bf4d66451e 100644
--- a/runtime/interpreter/mterp/mips/binopWide2addr.S
+++ b/runtime/interpreter/mterp/mips/binopWide2addr.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result0":"a0", "result1":"a1", "chkzero":"0", "arg0":"a0", "arg1":"a1", "arg2":"a2", "arg3":"a3"}
+%def binopWide2addr(preinstr="", result0="a0", result1="a1", chkzero="0", arg0="a0", arg1="a1", arg2="a2", arg3="a3", instr=""):
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0-a1 op a2-a3".
diff --git a/runtime/interpreter/mterp/mips/const.S b/runtime/interpreter/mterp/mips/const.S
index 5d8379dfb7a14cfad6a2a7572889948ae794a380..403dfc7389102a874ffd91ed6fc717aa427d1700 100644
--- a/runtime/interpreter/mterp/mips/const.S
+++ b/runtime/interpreter/mterp/mips/const.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedConstHandler" }
+%def const(helper="UndefinedConstHandler"):
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
diff --git a/runtime/interpreter/mterp/mips/entry.S b/runtime/interpreter/mterp/mips/entry.S
index d342354969647d211507a47e5537e30399f847f6..e40fc0203f2ac893d41098c600822e9172efe5c8 100644
--- a/runtime/interpreter/mterp/mips/entry.S
+++ b/runtime/interpreter/mterp/mips/entry.S
@@ -1,3 +1,4 @@
+%def entry():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
diff --git a/runtime/interpreter/mterp/mips/fallback.S b/runtime/interpreter/mterp/mips/fallback.S
index 82cbc6348064dc1fd6484f90d00d85c68406ce49..6133d9f825fa926e7d0370f23c2afa1095ed1899 100644
--- a/runtime/interpreter/mterp/mips/fallback.S
+++ b/runtime/interpreter/mterp/mips/fallback.S
@@ -1,2 +1,3 @@
+%def fallback():
 /* Transfer stub to alternate interpreter */
     b    MterpFallback
diff --git a/runtime/interpreter/mterp/mips/fbinop.S b/runtime/interpreter/mterp/mips/fbinop.S
index 6c1468ccfa08def159b1fff3b2b12ef8803057b9..7cbf73fda87486c1fb26ab630585568728dde350 100644
--- a/runtime/interpreter/mterp/mips/fbinop.S
+++ b/runtime/interpreter/mterp/mips/fbinop.S
@@ -1,3 +1,4 @@
+%def fbinop(instr=""):
     /*
      * Generic 32-bit binary float operation.
      *
diff --git a/runtime/interpreter/mterp/mips/fbinop2addr.S b/runtime/interpreter/mterp/mips/fbinop2addr.S
index 2caaf9cbbb046678e4481c9cab208cf2a4b14347..ea9970fb0b1392c22c4e14ce79e041a5b67330f0 100644
--- a/runtime/interpreter/mterp/mips/fbinop2addr.S
+++ b/runtime/interpreter/mterp/mips/fbinop2addr.S
@@ -1,3 +1,4 @@
+%def fbinop2addr(instr=""):
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr"
      * that specifies an instruction that performs "fv0 = fa0 op fa1".
diff --git a/runtime/interpreter/mterp/mips/fbinopWide.S b/runtime/interpreter/mterp/mips/fbinopWide.S
index a1fe91e25c52a1464dd6e313f5bbf0f1bf3fd5b8..1b5c0c13879daddbb24bf37e430627f95049f707 100644
--- a/runtime/interpreter/mterp/mips/fbinopWide.S
+++ b/runtime/interpreter/mterp/mips/fbinopWide.S
@@ -1,3 +1,4 @@
+%def fbinopWide(instr=""):
     /*
      * Generic 64-bit floating-point binary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = fa0 op fa1".
diff --git a/runtime/interpreter/mterp/mips/fbinopWide2addr.S b/runtime/interpreter/mterp/mips/fbinopWide2addr.S
index 73034411e13c5253bf9b24de1313a22c8161cf6c..e36f1f874d18482a5b92dab5e4c8fff92c6fd7f1 100644
--- a/runtime/interpreter/mterp/mips/fbinopWide2addr.S
+++ b/runtime/interpreter/mterp/mips/fbinopWide2addr.S
@@ -1,3 +1,4 @@
+%def fbinopWide2addr(instr=""):
     /*
      * Generic 64-bit floating-point "/2addr" binary operation.
      * Provide an "instr" line that specifies an instruction that
diff --git a/runtime/interpreter/mterp/mips/field.S b/runtime/interpreter/mterp/mips/field.S
index 1333ed77b7e1ed056329cae96075dc558158ee69..d61b06afd4bd42c6a791a1f76755241740e3e292 100644
--- a/runtime/interpreter/mterp/mips/field.S
+++ b/runtime/interpreter/mterp/mips/field.S
@@ -1 +1,2 @@
+%def field(helper=""):
 TODO
diff --git a/runtime/interpreter/mterp/mips/footer.S b/runtime/interpreter/mterp/mips/footer.S
index 1c784ef188c564748f782e32da03481420c748d1..0f641d213b560f37a3ab1970310f2642bc287ae6 100644
--- a/runtime/interpreter/mterp/mips/footer.S
+++ b/runtime/interpreter/mterp/mips/footer.S
@@ -1,3 +1,4 @@
+%def footer():
 /*
  * ===========================================================================
  *  Common subroutines and data
diff --git a/runtime/interpreter/mterp/mips/funop.S b/runtime/interpreter/mterp/mips/funop.S
index b2b22c97946fd692e2680073fc8157661821fafd..64f40ac23baa0eee6e3bd72400171aa8984b248b 100644
--- a/runtime/interpreter/mterp/mips/funop.S
+++ b/runtime/interpreter/mterp/mips/funop.S
@@ -1,3 +1,4 @@
+%def funop(instr=""):
     /*
      * Generic 32-bit floating-point unary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = op fa0".
diff --git a/runtime/interpreter/mterp/mips/funopWider.S b/runtime/interpreter/mterp/mips/funopWider.S
index 6862e245309782007fcdff23dc759c89a69ab03f..afc45ee9f53194c32ae24b133c6f49ac6b3f020a 100644
--- a/runtime/interpreter/mterp/mips/funopWider.S
+++ b/runtime/interpreter/mterp/mips/funopWider.S
@@ -1,3 +1,4 @@
+%def funopWider(instr=""):
     /*
      * Generic 32bit-to-64bit floating-point unary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = op fa0".
diff --git a/runtime/interpreter/mterp/mips/header.S b/runtime/interpreter/mterp/mips/header.S
index bef9eeb7f2d30c74546774bcc33a43dafd034555..57339d0f7f03daf08c2b48a4e435bc01ea962e99 100644
--- a/runtime/interpreter/mterp/mips/header.S
+++ b/runtime/interpreter/mterp/mips/header.S
@@ -1,3 +1,4 @@
+%def header():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -663,7 +664,6 @@
 #define STORE64_F(rlo, rhi, rbase) STORE64_off_F(rlo, rhi, rbase, 0)
 #define LOAD64_F(rlo, rhi, rbase) LOAD64_off_F(rlo, rhi, rbase, 0)
 
-
 #define LOAD_base_offMirrorArray_length(rd, rbase) LOAD_RB_OFF(rd, rbase, MIRROR_ARRAY_LENGTH_OFFSET)
 
 #define STACK_STORE(rd, off) sw rd, off(sp)
diff --git a/runtime/interpreter/mterp/mips/instruction_end.S b/runtime/interpreter/mterp/mips/instruction_end.S
index 32c725c7d9655633fcd95e67023080ff36bdc515..3d4429365a51b236997a9924cef40702e4711f8a 100644
--- a/runtime/interpreter/mterp/mips/instruction_end.S
+++ b/runtime/interpreter/mterp/mips/instruction_end.S
@@ -1,3 +1,4 @@
+%def instruction_end():
 
     .global artMterpAsmInstructionEnd
 artMterpAsmInstructionEnd:
diff --git a/runtime/interpreter/mterp/mips/instruction_end_alt.S b/runtime/interpreter/mterp/mips/instruction_end_alt.S
index f90916fc02cda411d0a0c9c40c77bb3c6848793c..86a1068f10fea62c2e4d86c7611ba97923262949 100644
--- a/runtime/interpreter/mterp/mips/instruction_end_alt.S
+++ b/runtime/interpreter/mterp/mips/instruction_end_alt.S
@@ -1,3 +1,4 @@
+%def instruction_end_alt():
 
     .global artMterpAsmAltInstructionEnd
 artMterpAsmAltInstructionEnd:
diff --git a/runtime/interpreter/mterp/mips/instruction_end_sister.S b/runtime/interpreter/mterp/mips/instruction_end_sister.S
index c5f4886697bb135e2a6a8bd74cf2fb7df2e5fab0..8cc4513025aada024f3baeb754a5881917ec0367 100644
--- a/runtime/interpreter/mterp/mips/instruction_end_sister.S
+++ b/runtime/interpreter/mterp/mips/instruction_end_sister.S
@@ -1,3 +1,4 @@
+%def instruction_end_sister():
 
     .global artMterpAsmSisterEnd
 artMterpAsmSisterEnd:
diff --git a/runtime/interpreter/mterp/mips/instruction_start.S b/runtime/interpreter/mterp/mips/instruction_start.S
index 8874c205404d9f5012a99d67dfd2ef472160d109..4b777f2fd5d44ff7f931b89d5c9e7ce9dee9bffd 100644
--- a/runtime/interpreter/mterp/mips/instruction_start.S
+++ b/runtime/interpreter/mterp/mips/instruction_start.S
@@ -1,3 +1,4 @@
+%def instruction_start():
 
     .global artMterpAsmInstructionStart
 artMterpAsmInstructionStart = .L_op_nop
diff --git a/runtime/interpreter/mterp/mips/instruction_start_alt.S b/runtime/interpreter/mterp/mips/instruction_start_alt.S
index 0c9ffdb7d6c01b8470682ee5715d27a475517e5b..e7731b75054dc5875240da6add6a8d16c56e8cfe 100644
--- a/runtime/interpreter/mterp/mips/instruction_start_alt.S
+++ b/runtime/interpreter/mterp/mips/instruction_start_alt.S
@@ -1,3 +1,4 @@
+%def instruction_start_alt():
 
     .global artMterpAsmAltInstructionStart
 artMterpAsmAltInstructionStart = .L_ALT_op_nop
diff --git a/runtime/interpreter/mterp/mips/instruction_start_sister.S b/runtime/interpreter/mterp/mips/instruction_start_sister.S
index 2ec51f7261de40fd2ad0d3ba9ed6826bf532d43e..e09ea90b8e7a911aa8f790d100687a87da50b328 100644
--- a/runtime/interpreter/mterp/mips/instruction_start_sister.S
+++ b/runtime/interpreter/mterp/mips/instruction_start_sister.S
@@ -1,3 +1,4 @@
+%def instruction_start_sister():
 
     .global artMterpAsmSisterStart
     .text
diff --git a/runtime/interpreter/mterp/mips/invoke.S b/runtime/interpreter/mterp/mips/invoke.S
index db3b8af73a7fd69dd7bd0472ade2b451799f7cd9..fa744527de763807f7de628c202e768766ccec25 100644
--- a/runtime/interpreter/mterp/mips/invoke.S
+++ b/runtime/interpreter/mterp/mips/invoke.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke(helper="UndefinedInvokeHandler"):
     /*
      * Generic invoke handler wrapper.
      */
diff --git a/runtime/interpreter/mterp/mips/invoke_polymorphic.S b/runtime/interpreter/mterp/mips/invoke_polymorphic.S
index 5c963f0314d62a7b1102dafde28619e095ec8984..f2532e7b2b2a36b4075795259027def64bc3f6e7 100644
--- a/runtime/interpreter/mterp/mips/invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/mips/invoke_polymorphic.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke_polymorphic(helper="UndefinedInvokeHandler"):
     /*
      * invoke-polymorphic handler wrapper.
      */
diff --git a/runtime/interpreter/mterp/mips/op_add_double.S b/runtime/interpreter/mterp/mips/op_add_double.S
index 12ef0cf3cd7f8539b4860d7c6adbd9a5eeddb20d..8308cdc4dd9fbfdb6fd440abbd8a00a8e366675b 100644
--- a/runtime/interpreter/mterp/mips/op_add_double.S
+++ b/runtime/interpreter/mterp/mips/op_add_double.S
@@ -1 +1,2 @@
-%include "mips/fbinopWide.S" {"instr":"add.d fv0, fa0, fa1"}
+%def op_add_double():
+%  fbinopWide(instr="add.d fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_add_double_2addr.S b/runtime/interpreter/mterp/mips/op_add_double_2addr.S
index c57add572c980efd79a9d48e94edfecd33bc72f9..41b099676c3e3baa0ba98cd6a1ae14ab61e7820b 100644
--- a/runtime/interpreter/mterp/mips/op_add_double_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_add_double_2addr.S
@@ -1 +1,2 @@
-%include "mips/fbinopWide2addr.S" {"instr":"add.d fv0, fa0, fa1"}
+%def op_add_double_2addr():
+%  fbinopWide2addr(instr="add.d fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_add_float.S b/runtime/interpreter/mterp/mips/op_add_float.S
index 6a46cf0ab9b4d03bfe2508bc5cf5ce364a65fb3e..807ea97481c89b1f458a8795fb1a5466aa02e807 100644
--- a/runtime/interpreter/mterp/mips/op_add_float.S
+++ b/runtime/interpreter/mterp/mips/op_add_float.S
@@ -1 +1,2 @@
-%include "mips/fbinop.S" {"instr":"add.s fv0, fa0, fa1"}
+%def op_add_float():
+%  fbinop(instr="add.s fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_add_float_2addr.S b/runtime/interpreter/mterp/mips/op_add_float_2addr.S
index 6ab5cc17309f867594133fbcd7ea5c398b29f0ea..c5735ae2e028a43ef72ad0d00a5640e1bed5cf50 100644
--- a/runtime/interpreter/mterp/mips/op_add_float_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_add_float_2addr.S
@@ -1 +1,2 @@
-%include "mips/fbinop2addr.S" {"instr":"add.s fv0, fa0, fa1"}
+%def op_add_float_2addr():
+%  fbinop2addr(instr="add.s fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_add_int.S b/runtime/interpreter/mterp/mips/op_add_int.S
index 53a0cb128fd1dfd880580c0a6a86524b75224939..ed0fc012b8a63f0849d04b5a4169d676d983134d 100644
--- a/runtime/interpreter/mterp/mips/op_add_int.S
+++ b/runtime/interpreter/mterp/mips/op_add_int.S
@@ -1 +1,2 @@
-%include "mips/binop.S" {"instr":"addu a0, a0, a1"}
+%def op_add_int():
+%  binop(instr="addu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_add_int_2addr.S b/runtime/interpreter/mterp/mips/op_add_int_2addr.S
index ddd92145c343513f7e5e04b9e2d43fe4bf9f422e..ed0b1314ef973ed789d594293573cc825334cf1c 100644
--- a/runtime/interpreter/mterp/mips/op_add_int_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_add_int_2addr.S
@@ -1 +1,2 @@
-%include "mips/binop2addr.S" {"instr":"addu a0, a0, a1"}
+%def op_add_int_2addr():
+%  binop2addr(instr="addu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_add_int_lit16.S b/runtime/interpreter/mterp/mips/op_add_int_lit16.S
index 05535c15dc451e058a9934100a781ac59f0f61fc..126807a303a50bdb24d6180891a9d9eb17ae2b35 100644
--- a/runtime/interpreter/mterp/mips/op_add_int_lit16.S
+++ b/runtime/interpreter/mterp/mips/op_add_int_lit16.S
@@ -1 +1,2 @@
-%include "mips/binopLit16.S" {"instr":"addu a0, a0, a1"}
+%def op_add_int_lit16():
+%  binopLit16(instr="addu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_add_int_lit8.S b/runtime/interpreter/mterp/mips/op_add_int_lit8.S
index fd021b31a964d15a5dfa21e417bf1b9112c40df9..30184c40f555cbed6243c9c9448e665dcf878b92 100644
--- a/runtime/interpreter/mterp/mips/op_add_int_lit8.S
+++ b/runtime/interpreter/mterp/mips/op_add_int_lit8.S
@@ -1 +1,2 @@
-%include "mips/binopLit8.S" {"instr":"addu a0, a0, a1"}
+%def op_add_int_lit8():
+%  binopLit8(instr="addu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_add_long.S b/runtime/interpreter/mterp/mips/op_add_long.S
index faacc6a3cc7ce3f4c5abb76e1918f6da6d74a03f..32205068bac23bfe783ae7fc13e4cef08672d46b 100644
--- a/runtime/interpreter/mterp/mips/op_add_long.S
+++ b/runtime/interpreter/mterp/mips/op_add_long.S
@@ -1,3 +1,4 @@
+%def op_add_long():
 /*
  *  The compiler generates the following sequence for
  *  [v1 v0] =  [a1 a0] + [a3 a2];
@@ -6,4 +7,4 @@
  *    sltu v1,v0,a2
  *    addu v1,v1,a1
  */
-%include "mips/binopWide.S" { "result0":"v0", "result1":"v1", "preinstr":"addu v0, a2, a0", "instr":"addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1" }
+%  binopWide(result0="v0", result1="v1", preinstr="addu v0, a2, a0", instr="addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1")
diff --git a/runtime/interpreter/mterp/mips/op_add_long_2addr.S b/runtime/interpreter/mterp/mips/op_add_long_2addr.S
index bf827c10d4e3202d59f7fcf1f8a28079e5d3cd8a..3bbc1f393d7f6cd5c584fe04f0e165c792ba70bc 100644
--- a/runtime/interpreter/mterp/mips/op_add_long_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_add_long_2addr.S
@@ -1,4 +1,5 @@
+%def op_add_long_2addr():
 /*
  * See op_add_long.S for details
  */
-%include "mips/binopWide2addr.S" { "result0":"v0", "result1":"v1", "preinstr":"addu v0, a2, a0", "instr":"addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1" }
+%  binopWide2addr(result0="v0", result1="v1", preinstr="addu v0, a2, a0", instr="addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1")
diff --git a/runtime/interpreter/mterp/mips/op_aget.S b/runtime/interpreter/mterp/mips/op_aget.S
index e88402c710253e5b072d306de8c2c12695f55cc9..026095f7acbeb18e937c6a871fa1d0575e373b63 100644
--- a/runtime/interpreter/mterp/mips/op_aget.S
+++ b/runtime/interpreter/mterp/mips/op_aget.S
@@ -1,4 +1,4 @@
-%default { "load":"lw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
+%def op_aget(load="lw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"):
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/mips/op_aget_boolean.S b/runtime/interpreter/mterp/mips/op_aget_boolean.S
index 59f7f82a84e5490a51b555a6110981f0c0fabcfd..7b28bc8e06f4762a02bd210e370457d5c0a4a6d7 100644
--- a/runtime/interpreter/mterp/mips/op_aget_boolean.S
+++ b/runtime/interpreter/mterp/mips/op_aget_boolean.S
@@ -1 +1,2 @@
-%include "mips/op_aget.S" { "load":"lbu", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aget_boolean():
+%  op_aget(load="lbu", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips/op_aget_byte.S b/runtime/interpreter/mterp/mips/op_aget_byte.S
index 11038fa7e10296c54347f87288a3469a0705fb35..a4a0b7e9b7d7f56dc3545a04621f63bb391db465 100644
--- a/runtime/interpreter/mterp/mips/op_aget_byte.S
+++ b/runtime/interpreter/mterp/mips/op_aget_byte.S
@@ -1 +1,2 @@
-%include "mips/op_aget.S" { "load":"lb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aget_byte():
+%  op_aget(load="lb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips/op_aget_char.S b/runtime/interpreter/mterp/mips/op_aget_char.S
index 96f2ab65dc533867267f68db1c739074dcdb9fef..465de097cd1a5f0f358050d97bc7b0336d7e3666 100644
--- a/runtime/interpreter/mterp/mips/op_aget_char.S
+++ b/runtime/interpreter/mterp/mips/op_aget_char.S
@@ -1 +1,2 @@
-%include "mips/op_aget.S" { "load":"lhu", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aget_char():
+%  op_aget(load="lhu", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips/op_aget_object.S b/runtime/interpreter/mterp/mips/op_aget_object.S
index 9c49dfeed710833adebc588baf7be73e5bc18a35..17a1e0ca8c424f5a1a238ec68defdde67d2bbf04 100644
--- a/runtime/interpreter/mterp/mips/op_aget_object.S
+++ b/runtime/interpreter/mterp/mips/op_aget_object.S
@@ -1,3 +1,4 @@
+%def op_aget_object():
     /*
      * Array object get.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/mips/op_aget_short.S b/runtime/interpreter/mterp/mips/op_aget_short.S
index cd7f7bf62f968b8c202042660bbb629de270ff9f..4faa9ad358295031e8c4aadcd23b188cf60c247a 100644
--- a/runtime/interpreter/mterp/mips/op_aget_short.S
+++ b/runtime/interpreter/mterp/mips/op_aget_short.S
@@ -1 +1,2 @@
-%include "mips/op_aget.S" { "load":"lh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aget_short():
+%  op_aget(load="lh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips/op_aget_wide.S b/runtime/interpreter/mterp/mips/op_aget_wide.S
index 08822f56c32a141e6fd348a6fef1e67838873a96..4045c11dbee3b310e7e96d60f2066cc0963b72a1 100644
--- a/runtime/interpreter/mterp/mips/op_aget_wide.S
+++ b/runtime/interpreter/mterp/mips/op_aget_wide.S
@@ -1,3 +1,4 @@
+%def op_aget_wide():
     /*
      * Array get, 64 bits.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/mips/op_and_int.S b/runtime/interpreter/mterp/mips/op_and_int.S
index 98fe4af7d22032dfc858d3f6a1e112656edf6dfc..740411ddf7ed8458a14bd85293bec4efa2b69d13 100644
--- a/runtime/interpreter/mterp/mips/op_and_int.S
+++ b/runtime/interpreter/mterp/mips/op_and_int.S
@@ -1 +1,2 @@
-%include "mips/binop.S" {"instr":"and a0, a0, a1"}
+%def op_and_int():
+%  binop(instr="and a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_and_int_2addr.S b/runtime/interpreter/mterp/mips/op_and_int_2addr.S
index 7f90ed45350b0905b4d4f33edd87d73fb87b1fb2..8224e5f18aa55c509f48b4dfcf3e3dcf4a361544 100644
--- a/runtime/interpreter/mterp/mips/op_and_int_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_and_int_2addr.S
@@ -1 +1,2 @@
-%include "mips/binop2addr.S" {"instr":"and a0, a0, a1"}
+%def op_and_int_2addr():
+%  binop2addr(instr="and a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_and_int_lit16.S b/runtime/interpreter/mterp/mips/op_and_int_lit16.S
index e46f23ba2e487f4f8e61e28f4eea807e70e8e342..5031f500ce6261fd23559da21709b2296891a053 100644
--- a/runtime/interpreter/mterp/mips/op_and_int_lit16.S
+++ b/runtime/interpreter/mterp/mips/op_and_int_lit16.S
@@ -1 +1,2 @@
-%include "mips/binopLit16.S" {"instr":"and a0, a0, a1"}
+%def op_and_int_lit16():
+%  binopLit16(instr="and a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_and_int_lit8.S b/runtime/interpreter/mterp/mips/op_and_int_lit8.S
index 3332883dc229507d59f1460c600e2885bb92c636..7a7b8b5d5a7ff51cc86235e13b88a12e53f95e17 100644
--- a/runtime/interpreter/mterp/mips/op_and_int_lit8.S
+++ b/runtime/interpreter/mterp/mips/op_and_int_lit8.S
@@ -1 +1,2 @@
-%include "mips/binopLit8.S" {"instr":"and a0, a0, a1"}
+%def op_and_int_lit8():
+%  binopLit8(instr="and a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_and_long.S b/runtime/interpreter/mterp/mips/op_and_long.S
index a98a6dfbd8f8d76772300397961783dff895c2b1..210e6a1acc09e3e78dc15c5fdfb3a0f01f79d4d7 100644
--- a/runtime/interpreter/mterp/mips/op_and_long.S
+++ b/runtime/interpreter/mterp/mips/op_and_long.S
@@ -1 +1,2 @@
-%include "mips/binopWide.S" {"preinstr":"and a0, a0, a2", "instr":"and a1, a1, a3"}
+%def op_and_long():
+%  binopWide(preinstr="and a0, a0, a2", instr="and a1, a1, a3")
diff --git a/runtime/interpreter/mterp/mips/op_and_long_2addr.S b/runtime/interpreter/mterp/mips/op_and_long_2addr.S
index 350c044f986c13fa3011e78cae57d7a5c9ec032e..c76a5af69568a08a5ccdbf9aab82a919e5da2a80 100644
--- a/runtime/interpreter/mterp/mips/op_and_long_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_and_long_2addr.S
@@ -1 +1,2 @@
-%include "mips/binopWide2addr.S" {"preinstr":"and a0, a0, a2", "instr":"and a1, a1, a3"}
+%def op_and_long_2addr():
+%  binopWide2addr(preinstr="and a0, a0, a2", instr="and a1, a1, a3")
diff --git a/runtime/interpreter/mterp/mips/op_aput.S b/runtime/interpreter/mterp/mips/op_aput.S
index 46dcaee3a917200e5b7825eb030478be1a22c1a2..6561f8f79f304c29fa722d9aca050c690780621f 100644
--- a/runtime/interpreter/mterp/mips/op_aput.S
+++ b/runtime/interpreter/mterp/mips/op_aput.S
@@ -1,4 +1,4 @@
-%default { "store":"sw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
+%def op_aput(store="sw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"):
 
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
diff --git a/runtime/interpreter/mterp/mips/op_aput_boolean.S b/runtime/interpreter/mterp/mips/op_aput_boolean.S
index 9cae5efbaf4f0bc0b3fcd79352b3437edeebba48..098bbcd1c4ce02d819be6404530115ee65ea6817 100644
--- a/runtime/interpreter/mterp/mips/op_aput_boolean.S
+++ b/runtime/interpreter/mterp/mips/op_aput_boolean.S
@@ -1 +1,2 @@
-%include "mips/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aput_boolean():
+%  op_aput(store="sb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips/op_aput_byte.S b/runtime/interpreter/mterp/mips/op_aput_byte.S
index 3bbd12cec110f9346205256b2d40e2d1f7caf166..f4b42ee6e85f8b1a94cf7fa26355fe90e44e5393 100644
--- a/runtime/interpreter/mterp/mips/op_aput_byte.S
+++ b/runtime/interpreter/mterp/mips/op_aput_byte.S
@@ -1 +1,2 @@
-%include "mips/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aput_byte():
+%  op_aput(store="sb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips/op_aput_char.S b/runtime/interpreter/mterp/mips/op_aput_char.S
index ae697173d79aaab670a315437c59bef3f8c8a10b..18eedae68dab57b018fc95db0971d39dee86ebb0 100644
--- a/runtime/interpreter/mterp/mips/op_aput_char.S
+++ b/runtime/interpreter/mterp/mips/op_aput_char.S
@@ -1 +1,2 @@
-%include "mips/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aput_char():
+%  op_aput(store="sh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips/op_aput_object.S b/runtime/interpreter/mterp/mips/op_aput_object.S
index 55b13b1449ae7b5ae4b64fc488d56f5d4a9def7d..89c72bac4e84152b7e362f4d86d409e3030dc0cb 100644
--- a/runtime/interpreter/mterp/mips/op_aput_object.S
+++ b/runtime/interpreter/mterp/mips/op_aput_object.S
@@ -1,3 +1,4 @@
+%def op_aput_object():
     /*
      * Store an object into an array.  vBB[vCC] <- vAA.
      *
diff --git a/runtime/interpreter/mterp/mips/op_aput_short.S b/runtime/interpreter/mterp/mips/op_aput_short.S
index 9586259a240aa68d263d8464594e97acbeaeea18..61a3c0d6ea59e023aaea7aa81e974e76db5969aa 100644
--- a/runtime/interpreter/mterp/mips/op_aput_short.S
+++ b/runtime/interpreter/mterp/mips/op_aput_short.S
@@ -1 +1,2 @@
-%include "mips/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aput_short():
+%  op_aput(store="sh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips/op_aput_wide.S b/runtime/interpreter/mterp/mips/op_aput_wide.S
index c3cff56aaab3b505406d31971ec51b0ed265538a..2fd0cbb932487cba267d9fe407dfaa801d8e5821 100644
--- a/runtime/interpreter/mterp/mips/op_aput_wide.S
+++ b/runtime/interpreter/mterp/mips/op_aput_wide.S
@@ -1,3 +1,4 @@
+%def op_aput_wide():
     /*
      * Array put, 64 bits.  vBB[vCC] <- vAA.
      */
diff --git a/runtime/interpreter/mterp/mips/op_array_length.S b/runtime/interpreter/mterp/mips/op_array_length.S
index ae2fe68322298c1f560927801178377042b0cd29..12348bd3f2158666b55077a960b8bdc3321d61f2 100644
--- a/runtime/interpreter/mterp/mips/op_array_length.S
+++ b/runtime/interpreter/mterp/mips/op_array_length.S
@@ -1,3 +1,4 @@
+%def op_array_length():
     /*
      * Return the length of an array.
      */
diff --git a/runtime/interpreter/mterp/mips/op_check_cast.S b/runtime/interpreter/mterp/mips/op_check_cast.S
index 3875ce6fc7c8a4ea6ed12567618587725d3d11f4..4d0f28681c2925002c3244077fcfceba060c9895 100644
--- a/runtime/interpreter/mterp/mips/op_check_cast.S
+++ b/runtime/interpreter/mterp/mips/op_check_cast.S
@@ -1,3 +1,4 @@
+%def op_check_cast():
     /*
      * Check to see if a cast from one class to another is allowed.
      */
diff --git a/runtime/interpreter/mterp/mips/op_cmp_long.S b/runtime/interpreter/mterp/mips/op_cmp_long.S
index 44806c3d067006ae82682f759be45f0ecfdede61..7d40b0e459ed6535b8ff80664d7251e9241821db 100644
--- a/runtime/interpreter/mterp/mips/op_cmp_long.S
+++ b/runtime/interpreter/mterp/mips/op_cmp_long.S
@@ -1,3 +1,4 @@
+%def op_cmp_long():
     /*
      * Compare two 64-bit values
      *    x = y     return  0
diff --git a/runtime/interpreter/mterp/mips/op_cmpg_double.S b/runtime/interpreter/mterp/mips/op_cmpg_double.S
index b2e753219c5263c2c186f1c94a7f8fb0047afd9e..8e3d18185005b25af1b2da178e4020fc648e1f40 100644
--- a/runtime/interpreter/mterp/mips/op_cmpg_double.S
+++ b/runtime/interpreter/mterp/mips/op_cmpg_double.S
@@ -1 +1,2 @@
-%include "mips/op_cmpl_double.S" { "gt_bias":"1" }
+%def op_cmpg_double():
+%  op_cmpl_double(gt_bias="1")
diff --git a/runtime/interpreter/mterp/mips/op_cmpg_float.S b/runtime/interpreter/mterp/mips/op_cmpg_float.S
index 76550b56b057d8714091665824e0668a313b8c57..d8afa2a1f48d6715add36f052e476f7dc62e8628 100644
--- a/runtime/interpreter/mterp/mips/op_cmpg_float.S
+++ b/runtime/interpreter/mterp/mips/op_cmpg_float.S
@@ -1 +1,2 @@
-%include "mips/op_cmpl_float.S" { "gt_bias":"1" }
+%def op_cmpg_float():
+%  op_cmpl_float(gt_bias="1")
diff --git a/runtime/interpreter/mterp/mips/op_cmpl_double.S b/runtime/interpreter/mterp/mips/op_cmpl_double.S
index 369e5b30fd6b4fcc10115d8eebd3e441112a7f8d..ab6dd49a5d9e6365d8e6b0266e0a933e274096f1 100644
--- a/runtime/interpreter/mterp/mips/op_cmpl_double.S
+++ b/runtime/interpreter/mterp/mips/op_cmpl_double.S
@@ -1,4 +1,4 @@
-%default { "gt_bias":"0" }
+%def op_cmpl_double(gt_bias="0"):
     /*
      * Compare two floating-point values. Puts 0(==), 1(>), or -1(<)
      * into the destination register based on the comparison results.
diff --git a/runtime/interpreter/mterp/mips/op_cmpl_float.S b/runtime/interpreter/mterp/mips/op_cmpl_float.S
index 1dd55067e985b44c70976efe7611441983c61bfd..6542844215a6fcdfdc8022430187f709c473199c 100644
--- a/runtime/interpreter/mterp/mips/op_cmpl_float.S
+++ b/runtime/interpreter/mterp/mips/op_cmpl_float.S
@@ -1,4 +1,4 @@
-%default { "gt_bias":"0" }
+%def op_cmpl_float(gt_bias="0"):
     /*
      * Compare two floating-point values. Puts 0(==), 1(>), or -1(<)
      * into the destination register based on the comparison results.
diff --git a/runtime/interpreter/mterp/mips/op_const.S b/runtime/interpreter/mterp/mips/op_const.S
index bd9f873fb501dc734398555044fc18d028befc44..5b429d4b5429a9a48998d1160e8d86cf85007507 100644
--- a/runtime/interpreter/mterp/mips/op_const.S
+++ b/runtime/interpreter/mterp/mips/op_const.S
@@ -1,3 +1,4 @@
+%def op_const():
     /* const vAA, +BBBBbbbb */
     GET_OPA(a3)                            #  a3 <- AA
     FETCH(a0, 1)                           #  a0 <- bbbb (low)
diff --git a/runtime/interpreter/mterp/mips/op_const_16.S b/runtime/interpreter/mterp/mips/op_const_16.S
index 2ffb30f6f11ace01b77d35daae99b04178d8e757..85669a91b3b1ec3ea53cf2b0f64f8a3071004ae2 100644
--- a/runtime/interpreter/mterp/mips/op_const_16.S
+++ b/runtime/interpreter/mterp/mips/op_const_16.S
@@ -1,3 +1,4 @@
+%def op_const_16():
     /* const/16 vAA, +BBBB */
     FETCH_S(a0, 1)                         #  a0 <- ssssBBBB (sign-extended)
     GET_OPA(a3)                            #  a3 <- AA
diff --git a/runtime/interpreter/mterp/mips/op_const_4.S b/runtime/interpreter/mterp/mips/op_const_4.S
index 6866c784170177ec45b95739a580f01a3653fc89..158a24658a22f3a9a02a6ae80bdf2ccaafcae98e 100644
--- a/runtime/interpreter/mterp/mips/op_const_4.S
+++ b/runtime/interpreter/mterp/mips/op_const_4.S
@@ -1,3 +1,4 @@
+%def op_const_4():
     /* const/4 vA, +B */
     sll       a1, rINST, 16                #  a1 <- Bxxx0000
     GET_OPA(a0)                            #  a0 <- A+
diff --git a/runtime/interpreter/mterp/mips/op_const_class.S b/runtime/interpreter/mterp/mips/op_const_class.S
index 5b3c96819a331471f232a3dba8d9423ec75c7e93..db12ec31414690de6acb180ce962f6676f3ab2f5 100644
--- a/runtime/interpreter/mterp/mips/op_const_class.S
+++ b/runtime/interpreter/mterp/mips/op_const_class.S
@@ -1 +1,2 @@
-%include "mips/const.S" { "helper":"MterpConstClass" }
+%def op_const_class():
+%  const(helper="MterpConstClass")
diff --git a/runtime/interpreter/mterp/mips/op_const_high16.S b/runtime/interpreter/mterp/mips/op_const_high16.S
index 51624022603e42932af07abe8182e8a25d90d0e6..fee52963204f22cec7ccb3e70ccfb90e5e30110b 100644
--- a/runtime/interpreter/mterp/mips/op_const_high16.S
+++ b/runtime/interpreter/mterp/mips/op_const_high16.S
@@ -1,3 +1,4 @@
+%def op_const_high16():
     /* const/high16 vAA, +BBBB0000 */
     FETCH(a0, 1)                           #  a0 <- 0000BBBB (zero-extended)
     GET_OPA(a3)                            #  a3 <- AA
diff --git a/runtime/interpreter/mterp/mips/op_const_method_handle.S b/runtime/interpreter/mterp/mips/op_const_method_handle.S
index 4011e435c4839acf758e19ff415e593bdd12849f..2680c17aad5d6f537298bc455177da35df137274 100644
--- a/runtime/interpreter/mterp/mips/op_const_method_handle.S
+++ b/runtime/interpreter/mterp/mips/op_const_method_handle.S
@@ -1 +1,2 @@
-%include "mips/const.S" { "helper":"MterpConstMethodHandle" }
+%def op_const_method_handle():
+%  const(helper="MterpConstMethodHandle")
diff --git a/runtime/interpreter/mterp/mips/op_const_method_type.S b/runtime/interpreter/mterp/mips/op_const_method_type.S
index 18a5e0f68804c91c1ca06da3328bcb8028f2afb0..ea814bf64826079ab9f55e43e47f42180c3ad420 100644
--- a/runtime/interpreter/mterp/mips/op_const_method_type.S
+++ b/runtime/interpreter/mterp/mips/op_const_method_type.S
@@ -1 +1,2 @@
-%include "mips/const.S" { "helper":"MterpConstMethodType" }
+%def op_const_method_type():
+%  const(helper="MterpConstMethodType")
diff --git a/runtime/interpreter/mterp/mips/op_const_string.S b/runtime/interpreter/mterp/mips/op_const_string.S
index 0bab6b40687b41d9a685169ec5039ec6f17b847a..41376f870340354594a5a218b1d2379e08042008 100644
--- a/runtime/interpreter/mterp/mips/op_const_string.S
+++ b/runtime/interpreter/mterp/mips/op_const_string.S
@@ -1 +1,2 @@
-%include "mips/const.S" { "helper":"MterpConstString" }
+%def op_const_string():
+%  const(helper="MterpConstString")
diff --git a/runtime/interpreter/mterp/mips/op_const_string_jumbo.S b/runtime/interpreter/mterp/mips/op_const_string_jumbo.S
index 54cec977d3fcfaadffd140e282a74ed951022ae0..0a031f33567a7fa24e86ec9716f6ea8ebc8a3ba9 100644
--- a/runtime/interpreter/mterp/mips/op_const_string_jumbo.S
+++ b/runtime/interpreter/mterp/mips/op_const_string_jumbo.S
@@ -1,3 +1,4 @@
+%def op_const_string_jumbo():
     /* const/string vAA, string@BBBBBBBB */
     EXPORT_PC()
     FETCH(a0, 1)                        # a0 <- bbbb (low)
diff --git a/runtime/interpreter/mterp/mips/op_const_wide.S b/runtime/interpreter/mterp/mips/op_const_wide.S
index f8911e3a68465f07e7b85246101321aa680a28a0..b424237135db1a2c24371a2bfc359388d2151bf6 100644
--- a/runtime/interpreter/mterp/mips/op_const_wide.S
+++ b/runtime/interpreter/mterp/mips/op_const_wide.S
@@ -1,3 +1,4 @@
+%def op_const_wide():
     /* const-wide vAA, +HHHHhhhhBBBBbbbb */
     FETCH(a0, 1)                           #  a0 <- bbbb (low)
     FETCH(a1, 2)                           #  a1 <- BBBB (low middle)
diff --git a/runtime/interpreter/mterp/mips/op_const_wide_16.S b/runtime/interpreter/mterp/mips/op_const_wide_16.S
index 2ca5ab927f924c8050ad30a4487c7b5b7a18edb2..d89a2b629cf78fc1bca8b1578eaba76921659fc0 100644
--- a/runtime/interpreter/mterp/mips/op_const_wide_16.S
+++ b/runtime/interpreter/mterp/mips/op_const_wide_16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_16():
     /* const-wide/16 vAA, +BBBB */
     FETCH_S(a0, 1)                         #  a0 <- ssssBBBB (sign-extended)
     GET_OPA(a3)                            #  a3 <- AA
diff --git a/runtime/interpreter/mterp/mips/op_const_wide_32.S b/runtime/interpreter/mterp/mips/op_const_wide_32.S
index bf802ca17062bd55aae414586df5d872d39a1eb2..f9db95367a3081ce2e98952aff23765a069cda10 100644
--- a/runtime/interpreter/mterp/mips/op_const_wide_32.S
+++ b/runtime/interpreter/mterp/mips/op_const_wide_32.S
@@ -1,3 +1,4 @@
+%def op_const_wide_32():
     /* const-wide/32 vAA, +BBBBbbbb */
     FETCH(a0, 1)                           #  a0 <- 0000bbbb (low)
     GET_OPA(a3)                            #  a3 <- AA
diff --git a/runtime/interpreter/mterp/mips/op_const_wide_high16.S b/runtime/interpreter/mterp/mips/op_const_wide_high16.S
index 04b90fa152544b7dec80e16432da6b8e2b98563e..dd0cd947f2338550c183a1554bee399857c091c8 100644
--- a/runtime/interpreter/mterp/mips/op_const_wide_high16.S
+++ b/runtime/interpreter/mterp/mips/op_const_wide_high16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_high16():
     /* const-wide/high16 vAA, +BBBB000000000000 */
     FETCH(a1, 1)                           #  a1 <- 0000BBBB (zero-extended)
     GET_OPA(a3)                            #  a3 <- AA
diff --git a/runtime/interpreter/mterp/mips/op_div_double.S b/runtime/interpreter/mterp/mips/op_div_double.S
index 84e4c4e3174774b3caa4a5dcee50abf55efe65c3..e1324d0dc75559c39ae3a37ea04f25a8f5b65c4b 100644
--- a/runtime/interpreter/mterp/mips/op_div_double.S
+++ b/runtime/interpreter/mterp/mips/op_div_double.S
@@ -1 +1,2 @@
-%include "mips/fbinopWide.S" {"instr":"div.d fv0, fa0, fa1"}
+%def op_div_double():
+%  fbinopWide(instr="div.d fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_div_double_2addr.S b/runtime/interpreter/mterp/mips/op_div_double_2addr.S
index 65b92e37db357125247e7252c07ce6c92421db37..aa6d16d4a95cf12d0055fec232c4068f83a7a52e 100644
--- a/runtime/interpreter/mterp/mips/op_div_double_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_div_double_2addr.S
@@ -1 +1,2 @@
-%include "mips/fbinopWide2addr.S" {"instr":"div.d fv0, fa0, fa1"}
+%def op_div_double_2addr():
+%  fbinopWide2addr(instr="div.d fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_div_float.S b/runtime/interpreter/mterp/mips/op_div_float.S
index 44b8d47e0b951ce9b7c4fb9cc4067f967d4e9835..b00c44c5456835d8a9396a2d35ca3a998f1b66c5 100644
--- a/runtime/interpreter/mterp/mips/op_div_float.S
+++ b/runtime/interpreter/mterp/mips/op_div_float.S
@@ -1 +1,2 @@
-%include "mips/fbinop.S" {"instr":"div.s fv0, fa0, fa1"}
+%def op_div_float():
+%  fbinop(instr="div.s fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_div_float_2addr.S b/runtime/interpreter/mterp/mips/op_div_float_2addr.S
index e5fff92c8c5006478954aebc20dca9e2e2c6d1e0..5201603e425e039e488e8a241fe64c185c1f5ba1 100644
--- a/runtime/interpreter/mterp/mips/op_div_float_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_div_float_2addr.S
@@ -1 +1,2 @@
-%include "mips/fbinop2addr.S" {"instr":"div.s fv0, fa0, fa1"}
+%def op_div_float_2addr():
+%  fbinop2addr(instr="div.s fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_div_int.S b/runtime/interpreter/mterp/mips/op_div_int.S
index 5d28c84d6b09b6c5be52d8707e2139e7c4908515..2b49fd25e727f69c8071f60a2fc1b9ca1c1ebae2 100644
--- a/runtime/interpreter/mterp/mips/op_div_int.S
+++ b/runtime/interpreter/mterp/mips/op_div_int.S
@@ -1,5 +1,6 @@
+%def op_div_int():
 #ifdef MIPS32REVGE6
-%include "mips/binop.S" {"instr":"div a0, a0, a1", "chkzero":"1"}
+%  binop(instr="div a0, a0, a1", chkzero="1")
 #else
-%include "mips/binop.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"}
+%  binop(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1")
 #endif
diff --git a/runtime/interpreter/mterp/mips/op_div_int_2addr.S b/runtime/interpreter/mterp/mips/op_div_int_2addr.S
index 6c079e04c4f9576a8cf2a04a53c24ca39f163ee3..325a5e6b0ace1130466b84779289697fcfd6bb84 100644
--- a/runtime/interpreter/mterp/mips/op_div_int_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_div_int_2addr.S
@@ -1,5 +1,6 @@
+%def op_div_int_2addr():
 #ifdef MIPS32REVGE6
-%include "mips/binop2addr.S" {"instr":"div a0, a0, a1", "chkzero":"1"}
+%  binop2addr(instr="div a0, a0, a1", chkzero="1")
 #else
-%include "mips/binop2addr.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"}
+%  binop2addr(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1")
 #endif
diff --git a/runtime/interpreter/mterp/mips/op_div_int_lit16.S b/runtime/interpreter/mterp/mips/op_div_int_lit16.S
index ee7452ce1a910f138744c8374f3d78786e79ffdf..7eaf340a4b9df10690a4643bb7255151e35deeef 100644
--- a/runtime/interpreter/mterp/mips/op_div_int_lit16.S
+++ b/runtime/interpreter/mterp/mips/op_div_int_lit16.S
@@ -1,5 +1,6 @@
+%def op_div_int_lit16():
 #ifdef MIPS32REVGE6
-%include "mips/binopLit16.S" {"instr":"div a0, a0, a1", "chkzero":"1"}
+%  binopLit16(instr="div a0, a0, a1", chkzero="1")
 #else
-%include "mips/binopLit16.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"}
+%  binopLit16(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1")
 #endif
diff --git a/runtime/interpreter/mterp/mips/op_div_int_lit8.S b/runtime/interpreter/mterp/mips/op_div_int_lit8.S
index d2964b8065e07ef3f4b2b3ffaab6f9eb9caedad6..b6aebb72be5bc77b44dee91818c367daf8efb0da 100644
--- a/runtime/interpreter/mterp/mips/op_div_int_lit8.S
+++ b/runtime/interpreter/mterp/mips/op_div_int_lit8.S
@@ -1,5 +1,6 @@
+%def op_div_int_lit8():
 #ifdef MIPS32REVGE6
-%include "mips/binopLit8.S" {"instr":"div a0, a0, a1", "chkzero":"1"}
+%  binopLit8(instr="div a0, a0, a1", chkzero="1")
 #else
-%include "mips/binopLit8.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"}
+%  binopLit8(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1")
 #endif
diff --git a/runtime/interpreter/mterp/mips/op_div_long.S b/runtime/interpreter/mterp/mips/op_div_long.S
index 2097866886cfa51aeb90b40516de94097b2ce2fb..631125927cfced66a48a455e349fe77625d73a69 100644
--- a/runtime/interpreter/mterp/mips/op_div_long.S
+++ b/runtime/interpreter/mterp/mips/op_div_long.S
@@ -1 +1,2 @@
-%include "mips/binopWide.S" {"result0":"v0", "result1":"v1", "instr":"JAL(__divdi3)", "chkzero":"1"}
+%def op_div_long():
+%  binopWide(result0="v0", result1="v1", instr="JAL(__divdi3)", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips/op_div_long_2addr.S b/runtime/interpreter/mterp/mips/op_div_long_2addr.S
index c27930514233808c2069587f8ea7ccb067ce017b..b3f72932d693a544248f6e34dbb7093b5cf22de7 100644
--- a/runtime/interpreter/mterp/mips/op_div_long_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_div_long_2addr.S
@@ -1 +1,2 @@
-%include "mips/binopWide2addr.S" {"result0":"v0", "result1":"v1", "instr":"JAL(__divdi3)", "chkzero":"1"}
+%def op_div_long_2addr():
+%  binopWide2addr(result0="v0", result1="v1", instr="JAL(__divdi3)", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips/op_double_to_float.S b/runtime/interpreter/mterp/mips/op_double_to_float.S
index 1d32c2e1e4b84c556f2cdaae433dc4a30a245d9b..c3f2fedb0330cec0bb85a39e09d42066d3dccc65 100644
--- a/runtime/interpreter/mterp/mips/op_double_to_float.S
+++ b/runtime/interpreter/mterp/mips/op_double_to_float.S
@@ -1 +1,2 @@
-%include "mips/unopNarrower.S" {"instr":"cvt.s.d fv0, fa0"}
+%def op_double_to_float():
+%  unopNarrower(instr="cvt.s.d fv0, fa0")
diff --git a/runtime/interpreter/mterp/mips/op_double_to_int.S b/runtime/interpreter/mterp/mips/op_double_to_int.S
index 6d7c6cae61f1caefa11c3c96ec9e1d3317cf121f..a522c9c5425a42dc106e7b340d2c123a1fbcb577 100644
--- a/runtime/interpreter/mterp/mips/op_double_to_int.S
+++ b/runtime/interpreter/mterp/mips/op_double_to_int.S
@@ -1,3 +1,4 @@
+%def op_double_to_int():
     /*
      * double-to-int
      *
diff --git a/runtime/interpreter/mterp/mips/op_double_to_long.S b/runtime/interpreter/mterp/mips/op_double_to_long.S
index 459ab7eed09215592ac1f6274713871b3c103f9a..bfc17f51ce91ee2db70a6e193ba7be8188185c11 100644
--- a/runtime/interpreter/mterp/mips/op_double_to_long.S
+++ b/runtime/interpreter/mterp/mips/op_double_to_long.S
@@ -1,3 +1,4 @@
+%def op_double_to_long():
     /*
      * double-to-long
      *
@@ -40,7 +41,7 @@
     GET_INST_OPCODE(t1)                    #  extract opcode from rINST
     b         .L${opcode}_set_vreg
 #endif
-%break
+%def op_double_to_long_sister_code():
 
 #ifndef MIPS32REVGE6
 .L${opcode}_get_opcode:
diff --git a/runtime/interpreter/mterp/mips/op_fill_array_data.S b/runtime/interpreter/mterp/mips/op_fill_array_data.S
index c3cd371636289f776c2731bbab5940899f024673..558f68e5b8aa13de423ab1c412395c2966b46041 100644
--- a/runtime/interpreter/mterp/mips/op_fill_array_data.S
+++ b/runtime/interpreter/mterp/mips/op_fill_array_data.S
@@ -1,3 +1,4 @@
+%def op_fill_array_data():
     /* fill-array-data vAA, +BBBBBBBB */
     EXPORT_PC()
     FETCH(a1, 1)                           #  a1 <- bbbb (lo)
diff --git a/runtime/interpreter/mterp/mips/op_filled_new_array.S b/runtime/interpreter/mterp/mips/op_filled_new_array.S
index 9511578289f02edac729c9c9b0b191dac312a18c..6ac6314bf8287a462f0fe2e9119a974d789f4f29 100644
--- a/runtime/interpreter/mterp/mips/op_filled_new_array.S
+++ b/runtime/interpreter/mterp/mips/op_filled_new_array.S
@@ -1,4 +1,4 @@
-%default { "helper":"MterpFilledNewArray" }
+%def op_filled_new_array(helper="MterpFilledNewArray"):
     /*
      * Create a new array with elements filled from registers.
      *
diff --git a/runtime/interpreter/mterp/mips/op_filled_new_array_range.S b/runtime/interpreter/mterp/mips/op_filled_new_array_range.S
index f8dcb0e03783bd7a7e0d69391174da688c7d2d66..1667de149ace0bdaaafcd36c43724422682df424 100644
--- a/runtime/interpreter/mterp/mips/op_filled_new_array_range.S
+++ b/runtime/interpreter/mterp/mips/op_filled_new_array_range.S
@@ -1 +1,2 @@
-%include "mips/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" }
+%def op_filled_new_array_range():
+%  op_filled_new_array(helper="MterpFilledNewArrayRange")
diff --git a/runtime/interpreter/mterp/mips/op_float_to_double.S b/runtime/interpreter/mterp/mips/op_float_to_double.S
index 1315255b5c64e4aa47acd1b68cda2d170c5c82d3..c0235a88e71ca6ddca519c167d456739bf2b9616 100644
--- a/runtime/interpreter/mterp/mips/op_float_to_double.S
+++ b/runtime/interpreter/mterp/mips/op_float_to_double.S
@@ -1 +1,2 @@
-%include "mips/funopWider.S" {"instr":"cvt.d.s fv0, fa0"}
+%def op_float_to_double():
+%  funopWider(instr="cvt.d.s fv0, fa0")
diff --git a/runtime/interpreter/mterp/mips/op_float_to_int.S b/runtime/interpreter/mterp/mips/op_float_to_int.S
index 26a0988082a300cd25f114d0409aacb984df02da..2c0c41832368f0555b32fb81958d66de9841ee0f 100644
--- a/runtime/interpreter/mterp/mips/op_float_to_int.S
+++ b/runtime/interpreter/mterp/mips/op_float_to_int.S
@@ -1,3 +1,4 @@
+%def op_float_to_int():
     /*
      * float-to-int
      *
diff --git a/runtime/interpreter/mterp/mips/op_float_to_long.S b/runtime/interpreter/mterp/mips/op_float_to_long.S
index b8f8efbdcbc495a251e15ec82fae45883c291fa6..2134e630ae2965fe6bb3f90c033a9d45a7705423 100644
--- a/runtime/interpreter/mterp/mips/op_float_to_long.S
+++ b/runtime/interpreter/mterp/mips/op_float_to_long.S
@@ -1,3 +1,4 @@
+%def op_float_to_long():
     /*
      * float-to-long
      *
@@ -38,7 +39,7 @@
     GET_INST_OPCODE(t1)                    #  extract opcode from rINST
     b         .L${opcode}_set_vreg
 #endif
-%break
+%def op_float_to_long_sister_code():
 
 #ifndef MIPS32REVGE6
 .L${opcode}_get_opcode:
diff --git a/runtime/interpreter/mterp/mips/op_goto.S b/runtime/interpreter/mterp/mips/op_goto.S
index 57182a5b590a870e6c6c1f0335f3c9c9f9c0b798..8da1339257b3b4ce85df57154f7d35040cefb9d8 100644
--- a/runtime/interpreter/mterp/mips/op_goto.S
+++ b/runtime/interpreter/mterp/mips/op_goto.S
@@ -1,3 +1,4 @@
+%def op_goto():
     /*
      * Unconditional branch, 8-bit offset.
      *
diff --git a/runtime/interpreter/mterp/mips/op_goto_16.S b/runtime/interpreter/mterp/mips/op_goto_16.S
index 06c96cd5451644324a18d1748520e67371a0b381..55a055b329fb9f6aae810c09ca84f68995dbff03 100644
--- a/runtime/interpreter/mterp/mips/op_goto_16.S
+++ b/runtime/interpreter/mterp/mips/op_goto_16.S
@@ -1,3 +1,4 @@
+%def op_goto_16():
     /*
      * Unconditional branch, 16-bit offset.
      *
diff --git a/runtime/interpreter/mterp/mips/op_goto_32.S b/runtime/interpreter/mterp/mips/op_goto_32.S
index ef5bf6bc8228bca989a6c532cf8f31c641a11b03..e969bd2048af5ce20a186db5e72f8c271ea626b0 100644
--- a/runtime/interpreter/mterp/mips/op_goto_32.S
+++ b/runtime/interpreter/mterp/mips/op_goto_32.S
@@ -1,3 +1,4 @@
+%def op_goto_32():
     /*
      * Unconditional branch, 32-bit offset.
      *
diff --git a/runtime/interpreter/mterp/mips/op_if_eq.S b/runtime/interpreter/mterp/mips/op_if_eq.S
index d6f99871865a1e2d34f7bb0bbf2462d6908f7713..da58674fd4f81861aefae860c94e933f33d6cb26 100644
--- a/runtime/interpreter/mterp/mips/op_if_eq.S
+++ b/runtime/interpreter/mterp/mips/op_if_eq.S
@@ -1 +1,2 @@
-%include "mips/bincmp.S" { "condition":"eq" }
+%def op_if_eq():
+%  bincmp(condition="eq")
diff --git a/runtime/interpreter/mterp/mips/op_if_eqz.S b/runtime/interpreter/mterp/mips/op_if_eqz.S
index c52b76a755999a93323f309eb670d121c0b8b428..0639664d474160ca776be5174315d4e6c5a89f75 100644
--- a/runtime/interpreter/mterp/mips/op_if_eqz.S
+++ b/runtime/interpreter/mterp/mips/op_if_eqz.S
@@ -1 +1,2 @@
-%include "mips/zcmp.S" { "condition":"eq" }
+%def op_if_eqz():
+%  zcmp(condition="eq")
diff --git a/runtime/interpreter/mterp/mips/op_if_ge.S b/runtime/interpreter/mterp/mips/op_if_ge.S
index bd06ff5ad49dd61077db9b4de3f175e0e46380c5..5b6ed2f9944653fb88329ebabee2b2799299ce5d 100644
--- a/runtime/interpreter/mterp/mips/op_if_ge.S
+++ b/runtime/interpreter/mterp/mips/op_if_ge.S
@@ -1 +1,2 @@
-%include "mips/bincmp.S" { "condition":"ge" }
+%def op_if_ge():
+%  bincmp(condition="ge")
diff --git a/runtime/interpreter/mterp/mips/op_if_gez.S b/runtime/interpreter/mterp/mips/op_if_gez.S
index 549231a15ff0f5662495c3be463228f538444403..ea6cda71fb81ab4dd62e1283b3dcdfeb44afefc4 100644
--- a/runtime/interpreter/mterp/mips/op_if_gez.S
+++ b/runtime/interpreter/mterp/mips/op_if_gez.S
@@ -1 +1,2 @@
-%include "mips/zcmp.S" { "condition":"ge" }
+%def op_if_gez():
+%  zcmp(condition="ge")
diff --git a/runtime/interpreter/mterp/mips/op_if_gt.S b/runtime/interpreter/mterp/mips/op_if_gt.S
index 0be30912edd940b409321963483b282ced27cf41..201decff1a91a48790fa913ac1d3efddfe919764 100644
--- a/runtime/interpreter/mterp/mips/op_if_gt.S
+++ b/runtime/interpreter/mterp/mips/op_if_gt.S
@@ -1 +1,2 @@
-%include "mips/bincmp.S" { "condition":"gt" }
+%def op_if_gt():
+%  bincmp(condition="gt")
diff --git a/runtime/interpreter/mterp/mips/op_if_gtz.S b/runtime/interpreter/mterp/mips/op_if_gtz.S
index 5c7bcc48b5d247d7c2e8933a4b574ac7b2bf180a..1fdbb6e8d2aeb22a7b97cde39b7604db087f79d6 100644
--- a/runtime/interpreter/mterp/mips/op_if_gtz.S
+++ b/runtime/interpreter/mterp/mips/op_if_gtz.S
@@ -1 +1,2 @@
-%include "mips/zcmp.S" { "condition":"gt" }
+%def op_if_gtz():
+%  zcmp(condition="gt")
diff --git a/runtime/interpreter/mterp/mips/op_if_le.S b/runtime/interpreter/mterp/mips/op_if_le.S
index c35c1a24b7975a2727dc409581e832b2fb2ee551..e6024f2b3e68b7b5654e49affe5582d6bd5ad598 100644
--- a/runtime/interpreter/mterp/mips/op_if_le.S
+++ b/runtime/interpreter/mterp/mips/op_if_le.S
@@ -1 +1,2 @@
-%include "mips/bincmp.S" { "condition":"le" }
+%def op_if_le():
+%  bincmp(condition="le")
diff --git a/runtime/interpreter/mterp/mips/op_if_lez.S b/runtime/interpreter/mterp/mips/op_if_lez.S
index 3dc6543d900cd678cfee225218b0ef65772517ea..62c0d2cd397e5dc55985ed32576521001e2e97a8 100644
--- a/runtime/interpreter/mterp/mips/op_if_lez.S
+++ b/runtime/interpreter/mterp/mips/op_if_lez.S
@@ -1 +1,2 @@
-%include "mips/zcmp.S" { "condition":"le" }
+%def op_if_lez():
+%  zcmp(condition="le")
diff --git a/runtime/interpreter/mterp/mips/op_if_lt.S b/runtime/interpreter/mterp/mips/op_if_lt.S
index 3f3386c9d266e31b0ee9c838eb0f1ba772a5c732..4ef22fd7987d9f7c113d65b85290703c9d60cfe2 100644
--- a/runtime/interpreter/mterp/mips/op_if_lt.S
+++ b/runtime/interpreter/mterp/mips/op_if_lt.S
@@ -1 +1,2 @@
-%include "mips/bincmp.S" { "condition":"lt" }
+%def op_if_lt():
+%  bincmp(condition="lt")
diff --git a/runtime/interpreter/mterp/mips/op_if_ltz.S b/runtime/interpreter/mterp/mips/op_if_ltz.S
index e6d6ed6aa6ce73a38695f29fefea67a7ea28c929..84b2d0b53a30d05690425994dad613278898adc0 100644
--- a/runtime/interpreter/mterp/mips/op_if_ltz.S
+++ b/runtime/interpreter/mterp/mips/op_if_ltz.S
@@ -1 +1,2 @@
-%include "mips/zcmp.S" { "condition":"lt" }
+%def op_if_ltz():
+%  zcmp(condition="lt")
diff --git a/runtime/interpreter/mterp/mips/op_if_ne.S b/runtime/interpreter/mterp/mips/op_if_ne.S
index 3d7bf350f19217d713eca694280f83ab4a0db0a8..ec3a688b294d4e3ceff3e99a22de2ecd4dcb220f 100644
--- a/runtime/interpreter/mterp/mips/op_if_ne.S
+++ b/runtime/interpreter/mterp/mips/op_if_ne.S
@@ -1 +1,2 @@
-%include "mips/bincmp.S" { "condition":"ne" }
+%def op_if_ne():
+%  bincmp(condition="ne")
diff --git a/runtime/interpreter/mterp/mips/op_if_nez.S b/runtime/interpreter/mterp/mips/op_if_nez.S
index d121eae930fdd07ed3f7791641dafb8795462d8b..7009c3acaa9c76772c2db07ea0576d28edeca34c 100644
--- a/runtime/interpreter/mterp/mips/op_if_nez.S
+++ b/runtime/interpreter/mterp/mips/op_if_nez.S
@@ -1 +1,2 @@
-%include "mips/zcmp.S" { "condition":"ne" }
+%def op_if_nez():
+%  zcmp(condition="ne")
diff --git a/runtime/interpreter/mterp/mips/op_iget.S b/runtime/interpreter/mterp/mips/op_iget.S
index e21827219632a71bdcf296251fc14def5bee1fbb..d09edc0a17c38245736a29f1cf55eb6f5272b87d 100644
--- a/runtime/interpreter/mterp/mips/op_iget.S
+++ b/runtime/interpreter/mterp/mips/op_iget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIGetU32"}
-%include "mips/field.S" { }
+%def op_iget(is_object="0", helper="MterpIGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/mips/op_iget_boolean.S b/runtime/interpreter/mterp/mips/op_iget_boolean.S
index f2ef68d8b25cac4d015890957fd3a976b245ce50..cb8edeec773fb6468b5c331b435e409da634f505 100644
--- a/runtime/interpreter/mterp/mips/op_iget_boolean.S
+++ b/runtime/interpreter/mterp/mips/op_iget_boolean.S
@@ -1 +1,2 @@
-%include "mips/op_iget.S" { "helper":"MterpIGetU8" }
+%def op_iget_boolean():
+%  op_iget(helper="MterpIGetU8")
diff --git a/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S b/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S
index f3032b3d8432cbe52185b7bdb361b5590d417253..f3d2cb1e97ab4109190c1d237b807e9671017217 100644
--- a/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S
@@ -1 +1,2 @@
-%include "mips/op_iget_quick.S" { "load":"lbu" }
+%def op_iget_boolean_quick():
+%  op_iget_quick(load="lbu")
diff --git a/runtime/interpreter/mterp/mips/op_iget_byte.S b/runtime/interpreter/mterp/mips/op_iget_byte.S
index 0c8fb7cf2c7695e1e141220a776fc363f85565fe..2b87fb16b560430baefa05d3f6e20195cb963d23 100644
--- a/runtime/interpreter/mterp/mips/op_iget_byte.S
+++ b/runtime/interpreter/mterp/mips/op_iget_byte.S
@@ -1 +1,2 @@
-%include "mips/op_iget.S" { "helper":"MterpIGetI8" }
+%def op_iget_byte():
+%  op_iget(helper="MterpIGetI8")
diff --git a/runtime/interpreter/mterp/mips/op_iget_byte_quick.S b/runtime/interpreter/mterp/mips/op_iget_byte_quick.S
index d93f84486d52a0b33c254917b359d9e1ce939ca0..ddb469b3de462032bd244bc0a1306aa89999efee 100644
--- a/runtime/interpreter/mterp/mips/op_iget_byte_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iget_byte_quick.S
@@ -1 +1,2 @@
-%include "mips/op_iget_quick.S" { "load":"lb" }
+%def op_iget_byte_quick():
+%  op_iget_quick(load="lb")
diff --git a/runtime/interpreter/mterp/mips/op_iget_char.S b/runtime/interpreter/mterp/mips/op_iget_char.S
index 69d04c4fa89a306b7e44f6cdcbdefffa257f3226..001bd03e2b85edc215b29789ba4fc55044b4a230 100644
--- a/runtime/interpreter/mterp/mips/op_iget_char.S
+++ b/runtime/interpreter/mterp/mips/op_iget_char.S
@@ -1 +1,2 @@
-%include "mips/op_iget.S" { "helper":"MterpIGetU16" }
+%def op_iget_char():
+%  op_iget(helper="MterpIGetU16")
diff --git a/runtime/interpreter/mterp/mips/op_iget_char_quick.S b/runtime/interpreter/mterp/mips/op_iget_char_quick.S
index 6f6d6088e04474495ceed7535c390aad0e2a067c..ef0b350d4e631e9fe52f891809f797d1f7250cc5 100644
--- a/runtime/interpreter/mterp/mips/op_iget_char_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iget_char_quick.S
@@ -1 +1,2 @@
-%include "mips/op_iget_quick.S" { "load":"lhu" }
+%def op_iget_char_quick():
+%  op_iget_quick(load="lhu")
diff --git a/runtime/interpreter/mterp/mips/op_iget_object.S b/runtime/interpreter/mterp/mips/op_iget_object.S
index bea330a14b69dd2fe2b14c95a4205d18df753802..4e5f769547b494ed962728edba2d102a106b332a 100644
--- a/runtime/interpreter/mterp/mips/op_iget_object.S
+++ b/runtime/interpreter/mterp/mips/op_iget_object.S
@@ -1 +1,2 @@
-%include "mips/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" }
+%def op_iget_object():
+%  op_iget(is_object="1", helper="MterpIGetObj")
diff --git a/runtime/interpreter/mterp/mips/op_iget_object_quick.S b/runtime/interpreter/mterp/mips/op_iget_object_quick.S
index 95c34d7b3f60ebd4df3685fddf577f9866a377b0..8bfd40b44c30786e31efab636bcc7c24b316ccec 100644
--- a/runtime/interpreter/mterp/mips/op_iget_object_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iget_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iget_object_quick():
     /* For: iget-object-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
diff --git a/runtime/interpreter/mterp/mips/op_iget_quick.S b/runtime/interpreter/mterp/mips/op_iget_quick.S
index 46277d30cbfb4ec33e826c6b6c3ed30b04e8a413..b8892fdb91e49a75b41f7616fa4538d50a145571 100644
--- a/runtime/interpreter/mterp/mips/op_iget_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iget_quick.S
@@ -1,4 +1,4 @@
-%default { "load":"lw" }
+%def op_iget_quick(load="lw"):
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
diff --git a/runtime/interpreter/mterp/mips/op_iget_short.S b/runtime/interpreter/mterp/mips/op_iget_short.S
index 357c7918e43150a1b967a51e75367bfdf7cda073..a62c4d998f1d05ed2a3bb1c2f2bf2cca501dfdb8 100644
--- a/runtime/interpreter/mterp/mips/op_iget_short.S
+++ b/runtime/interpreter/mterp/mips/op_iget_short.S
@@ -1 +1,2 @@
-%include "mips/op_iget.S" { "helper":"MterpIGetI16" }
+%def op_iget_short():
+%  op_iget(helper="MterpIGetI16")
diff --git a/runtime/interpreter/mterp/mips/op_iget_short_quick.S b/runtime/interpreter/mterp/mips/op_iget_short_quick.S
index 899a0feb656acdaefe7b404832959bbeaf2188ce..5957cb4600af924890ced3b0cf3ace62b69d24e2 100644
--- a/runtime/interpreter/mterp/mips/op_iget_short_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iget_short_quick.S
@@ -1 +1,2 @@
-%include "mips/op_iget_quick.S" { "load":"lh" }
+%def op_iget_short_quick():
+%  op_iget_quick(load="lh")
diff --git a/runtime/interpreter/mterp/mips/op_iget_wide.S b/runtime/interpreter/mterp/mips/op_iget_wide.S
index 885372a529b089dd9d0a6bfc80bcdd6375c484b1..9643cc340313b657f2485df521ed0ee0cba25f7b 100644
--- a/runtime/interpreter/mterp/mips/op_iget_wide.S
+++ b/runtime/interpreter/mterp/mips/op_iget_wide.S
@@ -1 +1,2 @@
-%include "mips/op_iget.S" { "helper":"MterpIGetU64" }
+%def op_iget_wide():
+%  op_iget(helper="MterpIGetU64")
diff --git a/runtime/interpreter/mterp/mips/op_iget_wide_quick.S b/runtime/interpreter/mterp/mips/op_iget_wide_quick.S
index 128be571f8eee86a6d500c0fcecba4134354b59c..5bc90762ddf06aabf6e74977dbb248767492276c 100644
--- a/runtime/interpreter/mterp/mips/op_iget_wide_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iget_wide_quick.S
@@ -1,3 +1,4 @@
+%def op_iget_wide_quick():
     /* iget-wide-quick vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
     GET_VREG(a3, a2)                       #  a3 <- object we're operating on
diff --git a/runtime/interpreter/mterp/mips/op_instance_of.S b/runtime/interpreter/mterp/mips/op_instance_of.S
index 706dcf37a1e85d778a6bbd8071bbae5409fd780c..9312e72a1050d7ab0685db678cba45ebac97f85d 100644
--- a/runtime/interpreter/mterp/mips/op_instance_of.S
+++ b/runtime/interpreter/mterp/mips/op_instance_of.S
@@ -1,3 +1,4 @@
+%def op_instance_of():
     /*
      * Check to see if an object reference is an instance of a class.
      *
diff --git a/runtime/interpreter/mterp/mips/op_int_to_byte.S b/runtime/interpreter/mterp/mips/op_int_to_byte.S
index 9266aab020cbf9c744789d3d68c29521c563f7a6..584172583a156795aabf21263fb84e6a80cc5d35 100644
--- a/runtime/interpreter/mterp/mips/op_int_to_byte.S
+++ b/runtime/interpreter/mterp/mips/op_int_to_byte.S
@@ -1 +1,2 @@
-%include "mips/unop.S" {"instr":"SEB(a0, a0)"}
+%def op_int_to_byte():
+%  unop(instr="SEB(a0, a0)")
diff --git a/runtime/interpreter/mterp/mips/op_int_to_char.S b/runtime/interpreter/mterp/mips/op_int_to_char.S
index 1b74a6e2494bb7a5f4a23e08bec5a2f17ae70b14..7fda63792c87aad920737d2df7734a6befc35ec6 100644
--- a/runtime/interpreter/mterp/mips/op_int_to_char.S
+++ b/runtime/interpreter/mterp/mips/op_int_to_char.S
@@ -1 +1,2 @@
-%include "mips/unop.S" {"preinstr":"", "instr":"and a0, 0xffff"}
+%def op_int_to_char():
+%  unop(preinstr="", instr="and a0, 0xffff")
diff --git a/runtime/interpreter/mterp/mips/op_int_to_double.S b/runtime/interpreter/mterp/mips/op_int_to_double.S
index 89484ce34ffa12a98f25c4b91f1c5a1169f8eff3..736ebb3053a1114b91a4473da011be65c79c05bf 100644
--- a/runtime/interpreter/mterp/mips/op_int_to_double.S
+++ b/runtime/interpreter/mterp/mips/op_int_to_double.S
@@ -1 +1,2 @@
-%include "mips/funopWider.S" {"instr":"cvt.d.w fv0, fa0"}
+%def op_int_to_double():
+%  funopWider(instr="cvt.d.w fv0, fa0")
diff --git a/runtime/interpreter/mterp/mips/op_int_to_float.S b/runtime/interpreter/mterp/mips/op_int_to_float.S
index d6f4b3609f893ad71f9b1dcc89a3a9a3d94a7ef3..45ab4c8f8ba1c407be3c74b31c9162ae0774888e 100644
--- a/runtime/interpreter/mterp/mips/op_int_to_float.S
+++ b/runtime/interpreter/mterp/mips/op_int_to_float.S
@@ -1 +1,2 @@
-%include "mips/funop.S" {"instr":"cvt.s.w fv0, fa0"}
+%def op_int_to_float():
+%  funop(instr="cvt.s.w fv0, fa0")
diff --git a/runtime/interpreter/mterp/mips/op_int_to_long.S b/runtime/interpreter/mterp/mips/op_int_to_long.S
index 99074639508a73da979508bfe0e1648bfebbaed2..093f181eda4cf8040b55ea0544780f37335b046b 100644
--- a/runtime/interpreter/mterp/mips/op_int_to_long.S
+++ b/runtime/interpreter/mterp/mips/op_int_to_long.S
@@ -1 +1,2 @@
-%include "mips/unopWider.S" {"instr":"sra a1, a0, 31"}
+%def op_int_to_long():
+%  unopWider(instr="sra a1, a0, 31")
diff --git a/runtime/interpreter/mterp/mips/op_int_to_short.S b/runtime/interpreter/mterp/mips/op_int_to_short.S
index 8749cd87173c7cd2f9c939ece4da0713098ae117..38bc4518864ddb21415245886eee6fcc5bc6d295 100644
--- a/runtime/interpreter/mterp/mips/op_int_to_short.S
+++ b/runtime/interpreter/mterp/mips/op_int_to_short.S
@@ -1 +1,2 @@
-%include "mips/unop.S" {"instr":"SEH(a0, a0)"}
+%def op_int_to_short():
+%  unop(instr="SEH(a0, a0)")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_custom.S b/runtime/interpreter/mterp/mips/op_invoke_custom.S
index f9241c43c6a086a4fa45cbf0218bc6d7c10a75ae..4bba9ee5241061aa29e63ea32bb9d575e34286ea 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_custom.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_custom.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeCustom" }
+%def op_invoke_custom():
+%  invoke(helper="MterpInvokeCustom")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_custom_range.S b/runtime/interpreter/mterp/mips/op_invoke_custom_range.S
index 862a6144044889985e8389538f01e0e5b7a08a10..57e61af1fa860d814a9da1eaab56b25f199771aa 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_custom_range.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_custom_range.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeCustomRange" }
+%def op_invoke_custom_range():
+%  invoke(helper="MterpInvokeCustomRange")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_direct.S b/runtime/interpreter/mterp/mips/op_invoke_direct.S
index 1ef198a43462db4b1b30b8146d9ebc2614627476..d3139cf39b42aca474e7d18dcf526e32e80ced85 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_direct.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_direct.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeDirect" }
+%def op_invoke_direct():
+%  invoke(helper="MterpInvokeDirect")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_direct_range.S b/runtime/interpreter/mterp/mips/op_invoke_direct_range.S
index af7477f2cd82d73cf4d65e0e02d97442ed1c13bd..b4a161f48bf8b90b0561e577cdf35f27feb71f23 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_direct_range.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_direct_range.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeDirectRange" }
+%def op_invoke_direct_range():
+%  invoke(helper="MterpInvokeDirectRange")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_interface.S b/runtime/interpreter/mterp/mips/op_invoke_interface.S
index 80a485a077924dfca16e6dc3279ae29d4a9e2269..2e749aa2632cc74567c1314187340cf1a4695ac7 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_interface.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_interface.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeInterface" }
+%def op_invoke_interface():
+%  invoke(helper="MterpInvokeInterface")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_interface_range.S b/runtime/interpreter/mterp/mips/op_invoke_interface_range.S
index 8d725dc2049da7cbd0d0ed6fbd8acee20a54b941..298911537760c27944307413bb6bbc1a686768a5 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_interface_range.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_interface_range.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeInterfaceRange" }
+%def op_invoke_interface_range():
+%  invoke(helper="MterpInvokeInterfaceRange")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S b/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S
index 85e01e7221f4d63a2dc6415323581350e9258f1b..ce61f5aa0e6039481359af9e0d7de053a159fc79 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S
@@ -1 +1,2 @@
-%include "mips/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" }
+%def op_invoke_polymorphic():
+%  invoke_polymorphic(helper="MterpInvokePolymorphic")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S
index ce6397837be73c1440636d53b44b7ddd48f8dae3..16731bdb4040829bf0020b8524b4f70866b1f1e8 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S
@@ -1 +1,2 @@
-%include "mips/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" }
+%def op_invoke_polymorphic_range():
+%  invoke_polymorphic(helper="MterpInvokePolymorphicRange")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_static.S b/runtime/interpreter/mterp/mips/op_invoke_static.S
index 46253cb3a7ee137169954a6dbb0ad04e55e112ca..8b104a66b0b8edd8a28e180d8084e6ce4469e031 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_static.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_static.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeStatic" }
+%def op_invoke_static():
+%  invoke(helper="MterpInvokeStatic")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_static_range.S b/runtime/interpreter/mterp/mips/op_invoke_static_range.S
index 96abafe41d9418d88239c7ec21cb1ca84059c621..e0a546c92b4be72a4a5040d03e0018b1b248f536 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_static_range.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_static_range.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeStaticRange" }
+%def op_invoke_static_range():
+%  invoke(helper="MterpInvokeStaticRange")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_super.S b/runtime/interpreter/mterp/mips/op_invoke_super.S
index 473951bcce4ac2366da46483c8fd88e4764da73d..e5921f3d43aa9dda4f5738bc3956055d79d39aa6 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_super.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_super.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeSuper" }
+%def op_invoke_super():
+%  invoke(helper="MterpInvokeSuper")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_super_range.S b/runtime/interpreter/mterp/mips/op_invoke_super_range.S
index 963ff27ec5b47896c6aa8b45b971d7afee4000de..caeafaa13c91fddf7dd3751252e4daf3045dcd2e 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_super_range.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_super_range.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeSuperRange" }
+%def op_invoke_super_range():
+%  invoke(helper="MterpInvokeSuperRange")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual.S b/runtime/interpreter/mterp/mips/op_invoke_virtual.S
index ea51e98abc20d7dbd4d90618466eab1fb2288c84..8767741f287b5a4803d4dbb51122b50cad909ba3 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_virtual.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_virtual.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeVirtual" }
+%def op_invoke_virtual():
+%  invoke(helper="MterpInvokeVirtual")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S
index 0c00091219e4a6d56757714a2635a49e674e28bd..ea72c171ecfedd9ddb94bc2e2202e2c56ab11e53 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeVirtualQuick" }
+%def op_invoke_virtual_quick():
+%  invoke(helper="MterpInvokeVirtualQuick")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S
index 82201e726e45d470db2be51cc1525a5d094f772e..baa077959359e0dcfbfd3b3cd9814c31b3f6d727 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeVirtualRange" }
+%def op_invoke_virtual_range():
+%  invoke(helper="MterpInvokeVirtualRange")
diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S
index c783675dae9dbf4fe391f1a0b0ba52734f40bdb8..1d961a0781a94d0087847bce02fcae1f37a75f29 100644
--- a/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S
+++ b/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S
@@ -1 +1,2 @@
-%include "mips/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" }
+%def op_invoke_virtual_range_quick():
+%  invoke(helper="MterpInvokeVirtualQuickRange")
diff --git a/runtime/interpreter/mterp/mips/op_iput.S b/runtime/interpreter/mterp/mips/op_iput.S
index efbdfbad78948916a8071c57a5c773319baf2dd3..e5351baf557fe295afb718387a6de58585ba5184 100644
--- a/runtime/interpreter/mterp/mips/op_iput.S
+++ b/runtime/interpreter/mterp/mips/op_iput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIPutU32" }
-%include "mips/field.S" { }
+%def op_iput(is_object="0", helper="MterpIPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/mips/op_iput_boolean.S b/runtime/interpreter/mterp/mips/op_iput_boolean.S
index 55ac4cedaaa7a81461fa6d18fa21d15cf63253d1..9eb849877b6207d46a36c083b47c83ebbd7e5d00 100644
--- a/runtime/interpreter/mterp/mips/op_iput_boolean.S
+++ b/runtime/interpreter/mterp/mips/op_iput_boolean.S
@@ -1 +1,2 @@
-%include "mips/op_iput.S" { "helper":"MterpIPutU8" }
+%def op_iput_boolean():
+%  op_iput(helper="MterpIPutU8")
diff --git a/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S b/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S
index 7d5caf6d6af22ac015214277200152d40eec78b8..3d818a5a69426d17fdb687a73121fe89a8c79b42 100644
--- a/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S
@@ -1 +1,2 @@
-%include "mips/op_iput_quick.S" { "store":"sb" }
+%def op_iput_boolean_quick():
+%  op_iput_quick(store="sb")
diff --git a/runtime/interpreter/mterp/mips/op_iput_byte.S b/runtime/interpreter/mterp/mips/op_iput_byte.S
index 61e489be11ed4e128dc885b6be785aeacf73711a..4b74f9fb0e3c8bfe5566574fae72b21f71cd2067 100644
--- a/runtime/interpreter/mterp/mips/op_iput_byte.S
+++ b/runtime/interpreter/mterp/mips/op_iput_byte.S
@@ -1 +1,2 @@
-%include "mips/op_iput.S" { "helper":"MterpIPutI8" }
+%def op_iput_byte():
+%  op_iput(helper="MterpIPutI8")
diff --git a/runtime/interpreter/mterp/mips/op_iput_byte_quick.S b/runtime/interpreter/mterp/mips/op_iput_byte_quick.S
index 7d5caf6d6af22ac015214277200152d40eec78b8..06dc24e0959e6eca8ebf7ae20d54fa41b37604a3 100644
--- a/runtime/interpreter/mterp/mips/op_iput_byte_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iput_byte_quick.S
@@ -1 +1,2 @@
-%include "mips/op_iput_quick.S" { "store":"sb" }
+%def op_iput_byte_quick():
+%  op_iput_quick(store="sb")
diff --git a/runtime/interpreter/mterp/mips/op_iput_char.S b/runtime/interpreter/mterp/mips/op_iput_char.S
index 2caad1e0a63040058adfb9d8dd6d29e3415e852e..64a249fc122e7eb749561fbc7ef7b3cc1be67382 100644
--- a/runtime/interpreter/mterp/mips/op_iput_char.S
+++ b/runtime/interpreter/mterp/mips/op_iput_char.S
@@ -1 +1,2 @@
-%include "mips/op_iput.S" { "helper":"MterpIPutU16" }
+%def op_iput_char():
+%  op_iput(helper="MterpIPutU16")
diff --git a/runtime/interpreter/mterp/mips/op_iput_char_quick.S b/runtime/interpreter/mterp/mips/op_iput_char_quick.S
index 4bc84eb581eb55096654695dc85fc876b99e320a..3b6af5b9fea6ca86225ab18712760c5b69284a0a 100644
--- a/runtime/interpreter/mterp/mips/op_iput_char_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iput_char_quick.S
@@ -1 +1,2 @@
-%include "mips/op_iput_quick.S" { "store":"sh" }
+%def op_iput_char_quick():
+%  op_iput_quick(store="sh")
diff --git a/runtime/interpreter/mterp/mips/op_iput_object.S b/runtime/interpreter/mterp/mips/op_iput_object.S
index 6f7e7b760f2fbb453a1f1cbd78ef137249f85f8c..131edd5dbdae914ae95c3220d01788eba1a7ffb2 100644
--- a/runtime/interpreter/mterp/mips/op_iput_object.S
+++ b/runtime/interpreter/mterp/mips/op_iput_object.S
@@ -1 +1,2 @@
-%include "mips/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" }
+%def op_iput_object():
+%  op_iput(is_object="1", helper="MterpIPutObj")
diff --git a/runtime/interpreter/mterp/mips/op_iput_object_quick.S b/runtime/interpreter/mterp/mips/op_iput_object_quick.S
index 82044f51c8a776037f287f920b3a71111545ebe5..bb3cbe88ece1c8d7862241ba88e2ef71fe1a3c51 100644
--- a/runtime/interpreter/mterp/mips/op_iput_object_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iput_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_object_quick():
     /* For: iput-object-quick */
     /* op vA, vB, offset@CCCC */
     EXPORT_PC()
diff --git a/runtime/interpreter/mterp/mips/op_iput_quick.S b/runtime/interpreter/mterp/mips/op_iput_quick.S
index d9753b1409d0d22d608cdc16ae4512e25169e009..55067bea2261bd4e082116f6ba64052269fb06b3 100644
--- a/runtime/interpreter/mterp/mips/op_iput_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iput_quick.S
@@ -1,4 +1,4 @@
-%default { "store":"sw" }
+%def op_iput_quick(store="sw"):
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
diff --git a/runtime/interpreter/mterp/mips/op_iput_short.S b/runtime/interpreter/mterp/mips/op_iput_short.S
index 414a15bd70a8e24295fe7df108c2e88682cd95fb..e631a3b259e969ae8ae1222244d299fd0e4da3d7 100644
--- a/runtime/interpreter/mterp/mips/op_iput_short.S
+++ b/runtime/interpreter/mterp/mips/op_iput_short.S
@@ -1 +1,2 @@
-%include "mips/op_iput.S" { "helper":"MterpIPutI16" }
+%def op_iput_short():
+%  op_iput(helper="MterpIPutI16")
diff --git a/runtime/interpreter/mterp/mips/op_iput_short_quick.S b/runtime/interpreter/mterp/mips/op_iput_short_quick.S
index 4bc84eb581eb55096654695dc85fc876b99e320a..fade093fc18d1efec725e06fa834fc989a95ddb8 100644
--- a/runtime/interpreter/mterp/mips/op_iput_short_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iput_short_quick.S
@@ -1 +1,2 @@
-%include "mips/op_iput_quick.S" { "store":"sh" }
+%def op_iput_short_quick():
+%  op_iput_quick(store="sh")
diff --git a/runtime/interpreter/mterp/mips/op_iput_wide.S b/runtime/interpreter/mterp/mips/op_iput_wide.S
index fc862e4fa741ad342c98231395112346d9938ec0..2f34fd39f9ed2ca1104582178602a4dac83ee761 100644
--- a/runtime/interpreter/mterp/mips/op_iput_wide.S
+++ b/runtime/interpreter/mterp/mips/op_iput_wide.S
@@ -1 +1,2 @@
-%include "mips/op_iput.S" { "helper":"MterpIPutU64" }
+%def op_iput_wide():
+%  op_iput(helper="MterpIPutU64")
diff --git a/runtime/interpreter/mterp/mips/op_iput_wide_quick.S b/runtime/interpreter/mterp/mips/op_iput_wide_quick.S
index 0eb228d005ddc55a6ede4ca014f21d52a185459e..7b8e632be0a3fc59db3bfca68ceb31247ddadba7 100644
--- a/runtime/interpreter/mterp/mips/op_iput_wide_quick.S
+++ b/runtime/interpreter/mterp/mips/op_iput_wide_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_wide_quick():
     /* iput-wide-quick vA, vB, offset@CCCC */
     GET_OPA4(a0)                           #  a0 <- A(+)
     GET_OPB(a1)                            #  a1 <- B
diff --git a/runtime/interpreter/mterp/mips/op_long_to_double.S b/runtime/interpreter/mterp/mips/op_long_to_double.S
index 153f58210adea0c4038a97cc83c2a70296abea4e..5dfc76b0cfaa26fc37918668a32f72cbc2ae37c0 100644
--- a/runtime/interpreter/mterp/mips/op_long_to_double.S
+++ b/runtime/interpreter/mterp/mips/op_long_to_double.S
@@ -1,3 +1,4 @@
+%def op_long_to_double():
     /*
      * long-to-double
      */
diff --git a/runtime/interpreter/mterp/mips/op_long_to_float.S b/runtime/interpreter/mterp/mips/op_long_to_float.S
index dd1ab81f4dca88b95ea73a01104834df647a0a32..fcf2a2e22a384bba9864692c60eb5c657a985e51 100644
--- a/runtime/interpreter/mterp/mips/op_long_to_float.S
+++ b/runtime/interpreter/mterp/mips/op_long_to_float.S
@@ -1,3 +1,4 @@
+%def op_long_to_float():
     /*
      * long-to-float
      */
diff --git a/runtime/interpreter/mterp/mips/op_long_to_int.S b/runtime/interpreter/mterp/mips/op_long_to_int.S
index 949c180f3121797f275dc426dc5e52164638b457..eacb8f59ec402cbb87d740022854981c341e9a09 100644
--- a/runtime/interpreter/mterp/mips/op_long_to_int.S
+++ b/runtime/interpreter/mterp/mips/op_long_to_int.S
@@ -1,2 +1,3 @@
+%def op_long_to_int():
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-%include "mips/op_move.S"
+%  op_move()
diff --git a/runtime/interpreter/mterp/mips/op_monitor_enter.S b/runtime/interpreter/mterp/mips/op_monitor_enter.S
index 20d90294ac7fabdf6a6a2089dc19d80056c89907..66e3af5847f80b40afbf563ce67bd25ed5baecb1 100644
--- a/runtime/interpreter/mterp/mips/op_monitor_enter.S
+++ b/runtime/interpreter/mterp/mips/op_monitor_enter.S
@@ -1,3 +1,4 @@
+%def op_monitor_enter():
     /*
      * Synchronize on an object.
      */
diff --git a/runtime/interpreter/mterp/mips/op_monitor_exit.S b/runtime/interpreter/mterp/mips/op_monitor_exit.S
index 1eadff923b4df419853b79ea6284bf454766c5bd..d32d75ccc074986745671923d9a03985df297672 100644
--- a/runtime/interpreter/mterp/mips/op_monitor_exit.S
+++ b/runtime/interpreter/mterp/mips/op_monitor_exit.S
@@ -1,3 +1,4 @@
+%def op_monitor_exit():
     /*
      * Unlock an object.
      *
diff --git a/runtime/interpreter/mterp/mips/op_move.S b/runtime/interpreter/mterp/mips/op_move.S
index 547ea3a18517bf6e4a887dd5fd8196487a52a7e3..a0c1c31016d6ab6a7cfad3108962fc91d1dc79d1 100644
--- a/runtime/interpreter/mterp/mips/op_move.S
+++ b/runtime/interpreter/mterp/mips/op_move.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move(is_object="0"):
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     GET_OPB(a1)                            #  a1 <- B from 15:12
diff --git a/runtime/interpreter/mterp/mips/op_move_16.S b/runtime/interpreter/mterp/mips/op_move_16.S
index 91b73996b5ed7d03423e88756add8a0cbc20743e..273858ec5a49647291bdec5deccf9cf9976373ae 100644
--- a/runtime/interpreter/mterp/mips/op_move_16.S
+++ b/runtime/interpreter/mterp/mips/op_move_16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_16(is_object="0"):
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     FETCH(a1, 2)                           #  a1 <- BBBB
diff --git a/runtime/interpreter/mterp/mips/op_move_exception.S b/runtime/interpreter/mterp/mips/op_move_exception.S
index f1bece7be8448d720f34833bded0fb5590da46ea..80c554b3c1abd60d1e5ca898221e1b8b6a1d9ef2 100644
--- a/runtime/interpreter/mterp/mips/op_move_exception.S
+++ b/runtime/interpreter/mterp/mips/op_move_exception.S
@@ -1,3 +1,4 @@
+%def op_move_exception():
     /* move-exception vAA */
     GET_OPA(a2)                                 #  a2 <- AA
     lw    a3, THREAD_EXCEPTION_OFFSET(rSELF)    #  get exception obj
diff --git a/runtime/interpreter/mterp/mips/op_move_from16.S b/runtime/interpreter/mterp/mips/op_move_from16.S
index 90c25c970569f000b95a692591c8dd121e2c3b7d..7306ed85ad4aae9767a5307989aaadb2ca4db168 100644
--- a/runtime/interpreter/mterp/mips/op_move_from16.S
+++ b/runtime/interpreter/mterp/mips/op_move_from16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_from16(is_object="0"):
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     FETCH(a1, 1)                           #  a1 <- BBBB
diff --git a/runtime/interpreter/mterp/mips/op_move_object.S b/runtime/interpreter/mterp/mips/op_move_object.S
index 9420ff359f13a729053bf6094be03726082e0670..dbb4d5971027d54f58728020aadfa71973fb509a 100644
--- a/runtime/interpreter/mterp/mips/op_move_object.S
+++ b/runtime/interpreter/mterp/mips/op_move_object.S
@@ -1 +1,2 @@
-%include "mips/op_move.S" {"is_object":"1"}
+%def op_move_object():
+%  op_move(is_object="1")
diff --git a/runtime/interpreter/mterp/mips/op_move_object_16.S b/runtime/interpreter/mterp/mips/op_move_object_16.S
index d6454c222d4528831731000ae7a945ce9d137a36..40120379d51d6027f960ef7742f12d8d16773855 100644
--- a/runtime/interpreter/mterp/mips/op_move_object_16.S
+++ b/runtime/interpreter/mterp/mips/op_move_object_16.S
@@ -1 +1,2 @@
-%include "mips/op_move_16.S" {"is_object":"1"}
+%def op_move_object_16():
+%  op_move_16(is_object="1")
diff --git a/runtime/interpreter/mterp/mips/op_move_object_from16.S b/runtime/interpreter/mterp/mips/op_move_object_from16.S
index db0aca1f83a0d4d1963da2d2d8e165c836647055..c82698e81e6805ad74ebe1f6c8c36e3ff3a1bd4b 100644
--- a/runtime/interpreter/mterp/mips/op_move_object_from16.S
+++ b/runtime/interpreter/mterp/mips/op_move_object_from16.S
@@ -1 +1,2 @@
-%include "mips/op_move_from16.S" {"is_object":"1"}
+%def op_move_object_from16():
+%  op_move_from16(is_object="1")
diff --git a/runtime/interpreter/mterp/mips/op_move_result.S b/runtime/interpreter/mterp/mips/op_move_result.S
index a4d5bfef6a1c4cc61b894386e12da3833a694e6c..20651d9185d455773bf90a9d5d7f70913aa81fbf 100644
--- a/runtime/interpreter/mterp/mips/op_move_result.S
+++ b/runtime/interpreter/mterp/mips/op_move_result.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_result(is_object="0"):
     /* for: move-result, move-result-object */
     /* op vAA */
     GET_OPA(a2)                            #  a2 <- AA
diff --git a/runtime/interpreter/mterp/mips/op_move_result_object.S b/runtime/interpreter/mterp/mips/op_move_result_object.S
index fcbffee28111d1c09edc3df2e9d2d1c73084219a..87aea2646a6b25bae7ee8970a973915a76557939 100644
--- a/runtime/interpreter/mterp/mips/op_move_result_object.S
+++ b/runtime/interpreter/mterp/mips/op_move_result_object.S
@@ -1 +1,2 @@
-%include "mips/op_move_result.S" {"is_object":"1"}
+%def op_move_result_object():
+%  op_move_result(is_object="1")
diff --git a/runtime/interpreter/mterp/mips/op_move_result_wide.S b/runtime/interpreter/mterp/mips/op_move_result_wide.S
index 1259218c3485f05e4f480c62cb1ac853e42a6001..205f1741209c6064c6c470ac390798291d3cd183 100644
--- a/runtime/interpreter/mterp/mips/op_move_result_wide.S
+++ b/runtime/interpreter/mterp/mips/op_move_result_wide.S
@@ -1,3 +1,4 @@
+%def op_move_result_wide():
     /* move-result-wide vAA */
     GET_OPA(a2)                            #  a2 <- AA
     lw    a3, OFF_FP_RESULT_REGISTER(rFP)  #  get pointer to result JType
diff --git a/runtime/interpreter/mterp/mips/op_move_wide.S b/runtime/interpreter/mterp/mips/op_move_wide.S
index 01d094914bbf7fce34e949281eb739c6cd2320aa..ad7102210896920f887f4aff524232f8fec99a85 100644
--- a/runtime/interpreter/mterp/mips/op_move_wide.S
+++ b/runtime/interpreter/mterp/mips/op_move_wide.S
@@ -1,3 +1,4 @@
+%def op_move_wide():
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */
     GET_OPA4(a2)                           #  a2 <- A(+)
diff --git a/runtime/interpreter/mterp/mips/op_move_wide_16.S b/runtime/interpreter/mterp/mips/op_move_wide_16.S
index 587ba04b9d1f0819375065ba131f81e20e94844e..60d41a5734694ac9efa6d25ded9d28a06cd856b2 100644
--- a/runtime/interpreter/mterp/mips/op_move_wide_16.S
+++ b/runtime/interpreter/mterp/mips/op_move_wide_16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_16():
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */
     FETCH(a3, 2)                           #  a3 <- BBBB
diff --git a/runtime/interpreter/mterp/mips/op_move_wide_from16.S b/runtime/interpreter/mterp/mips/op_move_wide_from16.S
index 5003fbdb2476600b598d1dc893b70b415514aa62..0a970ef61166a9bef382cf2e5998852a1350cae8 100644
--- a/runtime/interpreter/mterp/mips/op_move_wide_from16.S
+++ b/runtime/interpreter/mterp/mips/op_move_wide_from16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_from16():
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */
     FETCH(a3, 1)                           #  a3 <- BBBB
diff --git a/runtime/interpreter/mterp/mips/op_mul_double.S b/runtime/interpreter/mterp/mips/op_mul_double.S
index 44a473bac108ff9a8a9e77d09153cd53dc32e0e9..609a462a326b1324418c986a27e03703c6dd5a2f 100644
--- a/runtime/interpreter/mterp/mips/op_mul_double.S
+++ b/runtime/interpreter/mterp/mips/op_mul_double.S
@@ -1 +1,2 @@
-%include "mips/fbinopWide.S" {"instr":"mul.d fv0, fa0, fa1"}
+%def op_mul_double():
+%  fbinopWide(instr="mul.d fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_mul_double_2addr.S b/runtime/interpreter/mterp/mips/op_mul_double_2addr.S
index 4e5c230bc5da0344e12b7a010ae1c0e6c560b8b3..ae0b13f1e9f1c5a9c0356347c56f4885474e4029 100644
--- a/runtime/interpreter/mterp/mips/op_mul_double_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_mul_double_2addr.S
@@ -1 +1,2 @@
-%include "mips/fbinopWide2addr.S" {"instr":"mul.d fv0, fa0, fa1"}
+%def op_mul_double_2addr():
+%  fbinopWide2addr(instr="mul.d fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_mul_float.S b/runtime/interpreter/mterp/mips/op_mul_float.S
index abc939054382ba5465fcb4b59a51e9a9eceec0a2..e4a578e7a92063122fcf177436f27ef38a701a94 100644
--- a/runtime/interpreter/mterp/mips/op_mul_float.S
+++ b/runtime/interpreter/mterp/mips/op_mul_float.S
@@ -1 +1,2 @@
-%include "mips/fbinop.S" {"instr":"mul.s fv0, fa0, fa1"}
+%def op_mul_float():
+%  fbinop(instr="mul.s fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_mul_float_2addr.S b/runtime/interpreter/mterp/mips/op_mul_float_2addr.S
index 24691095185ada93609a6cfd2aa13499e8c0ebb2..38b2a88ebd1b80bb14578a9fbda6f85daad89905 100644
--- a/runtime/interpreter/mterp/mips/op_mul_float_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_mul_float_2addr.S
@@ -1 +1,2 @@
-%include "mips/fbinop2addr.S" {"instr":"mul.s fv0, fa0, fa1"}
+%def op_mul_float_2addr():
+%  fbinop2addr(instr="mul.s fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_mul_int.S b/runtime/interpreter/mterp/mips/op_mul_int.S
index 266823c2c7c03013fa03e9897f980940d9a68195..34e42f0783aa5b9beeb66a6037c6421da821e957 100644
--- a/runtime/interpreter/mterp/mips/op_mul_int.S
+++ b/runtime/interpreter/mterp/mips/op_mul_int.S
@@ -1 +1,2 @@
-%include "mips/binop.S" {"instr":"mul a0, a0, a1"}
+%def op_mul_int():
+%  binop(instr="mul a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_mul_int_2addr.S b/runtime/interpreter/mterp/mips/op_mul_int_2addr.S
index b7dc5d3fb1ba37234ad79f0fc2a664ce61e0dc12..0224a6e2c14210a0180270f6b44ef5de1252d49a 100644
--- a/runtime/interpreter/mterp/mips/op_mul_int_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_mul_int_2addr.S
@@ -1 +1,2 @@
-%include "mips/binop2addr.S" {"instr":"mul a0, a0, a1"}
+%def op_mul_int_2addr():
+%  binop2addr(instr="mul a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_mul_int_lit16.S b/runtime/interpreter/mterp/mips/op_mul_int_lit16.S
index fb4c8ec27d2583eec69b540646067508a3769d4e..935d632e119074677397b812287a07a1e1ad918c 100644
--- a/runtime/interpreter/mterp/mips/op_mul_int_lit16.S
+++ b/runtime/interpreter/mterp/mips/op_mul_int_lit16.S
@@ -1 +1,2 @@
-%include "mips/binopLit16.S" {"instr":"mul a0, a0, a1"}
+%def op_mul_int_lit16():
+%  binopLit16(instr="mul a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_mul_int_lit8.S b/runtime/interpreter/mterp/mips/op_mul_int_lit8.S
index 6d2e7ded0cccb920bc6e1909ceb5f82442279706..4a2bfca5c16fcc4cc28dcd3ddc847e15469069ea 100644
--- a/runtime/interpreter/mterp/mips/op_mul_int_lit8.S
+++ b/runtime/interpreter/mterp/mips/op_mul_int_lit8.S
@@ -1 +1,2 @@
-%include "mips/binopLit8.S" {"instr":"mul a0, a0, a1"}
+%def op_mul_int_lit8():
+%  binopLit8(instr="mul a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_mul_long.S b/runtime/interpreter/mterp/mips/op_mul_long.S
index 74b049a0283bda895a55ce50d3507beabbc6f98a..ae31e1910f2d26a26adaaf2138b7397a06f68902 100644
--- a/runtime/interpreter/mterp/mips/op_mul_long.S
+++ b/runtime/interpreter/mterp/mips/op_mul_long.S
@@ -1,3 +1,4 @@
+%def op_mul_long():
     /*
      * Signed 64-bit integer multiply.
      *         a1   a0
@@ -35,7 +36,7 @@
     GET_OPA(a0)                            #  a0 <- AA
     FETCH_ADVANCE_INST(2)                  #  advance rPC, load rINST
     b         .L${opcode}_finish
-%break
+%def op_mul_long_sister_code():
 
 .L${opcode}_finish:
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
diff --git a/runtime/interpreter/mterp/mips/op_mul_long_2addr.S b/runtime/interpreter/mterp/mips/op_mul_long_2addr.S
index 683b055e8495855b03f6b38f35817824d244bdbb..ef5325418097ab3262544d1ae1472f1222d495af 100644
--- a/runtime/interpreter/mterp/mips/op_mul_long_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_mul_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_mul_long_2addr():
     /*
      * See op_mul_long.S for more details
      */
diff --git a/runtime/interpreter/mterp/mips/op_neg_double.S b/runtime/interpreter/mterp/mips/op_neg_double.S
index 89cc918b8048b87644276ed9cd4eb9345a6f90c9..b53ccbb63ad09d7c5f2577b1730d356be98b7dc4 100644
--- a/runtime/interpreter/mterp/mips/op_neg_double.S
+++ b/runtime/interpreter/mterp/mips/op_neg_double.S
@@ -1 +1,2 @@
-%include "mips/unopWide.S" {"instr":"addu a1, a1, 0x80000000"}
+%def op_neg_double():
+%  unopWide(instr="addu a1, a1, 0x80000000")
diff --git a/runtime/interpreter/mterp/mips/op_neg_float.S b/runtime/interpreter/mterp/mips/op_neg_float.S
index e702755f11284770e12a424fc3519d834da1bbc0..655d827d22508dfe2beca10efeaf817b73204868 100644
--- a/runtime/interpreter/mterp/mips/op_neg_float.S
+++ b/runtime/interpreter/mterp/mips/op_neg_float.S
@@ -1 +1,2 @@
-%include "mips/unop.S" {"instr":"addu a0, a0, 0x80000000"}
+%def op_neg_float():
+%  unop(instr="addu a0, a0, 0x80000000")
diff --git a/runtime/interpreter/mterp/mips/op_neg_int.S b/runtime/interpreter/mterp/mips/op_neg_int.S
index 44617314659e9a80be8b8b836b9cbb616ce56c31..acc3440a33d022d3fa340f265d3b7b2d9d5c2240 100644
--- a/runtime/interpreter/mterp/mips/op_neg_int.S
+++ b/runtime/interpreter/mterp/mips/op_neg_int.S
@@ -1 +1,2 @@
-%include "mips/unop.S" {"instr":"negu a0, a0"}
+%def op_neg_int():
+%  unop(instr="negu a0, a0")
diff --git a/runtime/interpreter/mterp/mips/op_neg_long.S b/runtime/interpreter/mterp/mips/op_neg_long.S
index 71e60f59be8b9fafd881901dd18d4c4fa1edbd75..9108b2b0ed8a141e528c232616c20a58f37c4caa 100644
--- a/runtime/interpreter/mterp/mips/op_neg_long.S
+++ b/runtime/interpreter/mterp/mips/op_neg_long.S
@@ -1 +1,2 @@
-%include "mips/unopWide.S" {"result0":"v0", "result1":"v1", "preinstr":"negu v0, a0", "instr":"negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0"}
+%def op_neg_long():
+%  unopWide(result0="v0", result1="v1", preinstr="negu v0, a0", instr="negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0")
diff --git a/runtime/interpreter/mterp/mips/op_new_array.S b/runtime/interpreter/mterp/mips/op_new_array.S
index 4a6512d7c5f3e9fdaefaf8020fa049532404c262..6ae04cc32beeb670c6f39d96bc5a0769f5410024 100644
--- a/runtime/interpreter/mterp/mips/op_new_array.S
+++ b/runtime/interpreter/mterp/mips/op_new_array.S
@@ -1,3 +1,4 @@
+%def op_new_array():
     /*
      * Allocate an array of objects, specified with the array class
      * and a count.
diff --git a/runtime/interpreter/mterp/mips/op_new_instance.S b/runtime/interpreter/mterp/mips/op_new_instance.S
index 3c9e83f9b81bc0dd54eb62a5699b03c707fd4326..0c98c93aaa06026f566dcc0f35526bb3ee5cd9cb 100644
--- a/runtime/interpreter/mterp/mips/op_new_instance.S
+++ b/runtime/interpreter/mterp/mips/op_new_instance.S
@@ -1,3 +1,4 @@
+%def op_new_instance():
     /*
      * Create a new instance of a class.
      */
diff --git a/runtime/interpreter/mterp/mips/op_nop.S b/runtime/interpreter/mterp/mips/op_nop.S
index 3565631e03bc2b728515bfbe3cc974bc967d42e3..10f607478f151d0c7740d7624f1b583fe704dce6 100644
--- a/runtime/interpreter/mterp/mips/op_nop.S
+++ b/runtime/interpreter/mterp/mips/op_nop.S
@@ -1,3 +1,4 @@
+%def op_nop():
     FETCH_ADVANCE_INST(1)                  #  advance rPC, load rINST
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
diff --git a/runtime/interpreter/mterp/mips/op_not_int.S b/runtime/interpreter/mterp/mips/op_not_int.S
index 55d8cc11d175d2087f989d11c1bcaaa815634e1e..7dc7aebc5cb94960232e8054821aac74c7fb6dde 100644
--- a/runtime/interpreter/mterp/mips/op_not_int.S
+++ b/runtime/interpreter/mterp/mips/op_not_int.S
@@ -1 +1,2 @@
-%include "mips/unop.S" {"instr":"not a0, a0"}
+%def op_not_int():
+%  unop(instr="not a0, a0")
diff --git a/runtime/interpreter/mterp/mips/op_not_long.S b/runtime/interpreter/mterp/mips/op_not_long.S
index 9e7c95bcea19c08fa952750bf106e53954df1770..0bca4bde59fd105217e1223142184572484a5917 100644
--- a/runtime/interpreter/mterp/mips/op_not_long.S
+++ b/runtime/interpreter/mterp/mips/op_not_long.S
@@ -1 +1,2 @@
-%include "mips/unopWide.S" {"preinstr":"not a0, a0", "instr":"not a1, a1"}
+%def op_not_long():
+%  unopWide(preinstr="not a0, a0", instr="not a1, a1")
diff --git a/runtime/interpreter/mterp/mips/op_or_int.S b/runtime/interpreter/mterp/mips/op_or_int.S
index c7ce760a73cd134850c3a3ade4d5bc216c94a086..df60be5896ee88d843f037e37d91cd39d44092b4 100644
--- a/runtime/interpreter/mterp/mips/op_or_int.S
+++ b/runtime/interpreter/mterp/mips/op_or_int.S
@@ -1 +1,2 @@
-%include "mips/binop.S" {"instr":"or a0, a0, a1"}
+%def op_or_int():
+%  binop(instr="or a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_or_int_2addr.S b/runtime/interpreter/mterp/mips/op_or_int_2addr.S
index 192d611e8d826ce4565b2b9852553be8b21980ec..c202e6799b595c00dac0889570bf6d125aa1cdcb 100644
--- a/runtime/interpreter/mterp/mips/op_or_int_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_or_int_2addr.S
@@ -1 +1,2 @@
-%include "mips/binop2addr.S" {"instr":"or a0, a0, a1"}
+%def op_or_int_2addr():
+%  binop2addr(instr="or a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_or_int_lit16.S b/runtime/interpreter/mterp/mips/op_or_int_lit16.S
index f4ef75fff8713f44c9a0d751338e041653ea83f6..09961e88453d0d05ad76a0d41e0d76e53aa40e15 100644
--- a/runtime/interpreter/mterp/mips/op_or_int_lit16.S
+++ b/runtime/interpreter/mterp/mips/op_or_int_lit16.S
@@ -1 +1,2 @@
-%include "mips/binopLit16.S" {"instr":"or a0, a0, a1"}
+%def op_or_int_lit16():
+%  binopLit16(instr="or a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_or_int_lit8.S b/runtime/interpreter/mterp/mips/op_or_int_lit8.S
index f6212e217d6d3b69e60b6eafb5445a0128666bb8..1bd6809d90a3d7831e519c8f0527294409d0e7d8 100644
--- a/runtime/interpreter/mterp/mips/op_or_int_lit8.S
+++ b/runtime/interpreter/mterp/mips/op_or_int_lit8.S
@@ -1 +1,2 @@
-%include "mips/binopLit8.S" {"instr":"or a0, a0, a1"}
+%def op_or_int_lit8():
+%  binopLit8(instr="or a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_or_long.S b/runtime/interpreter/mterp/mips/op_or_long.S
index 0f94486e421770fb73c0790a239a269671ba09cb..5f53085e0d7d99c37da3c37320b49e1bd17a615e 100644
--- a/runtime/interpreter/mterp/mips/op_or_long.S
+++ b/runtime/interpreter/mterp/mips/op_or_long.S
@@ -1 +1,2 @@
-%include "mips/binopWide.S" {"preinstr":"or a0, a0, a2", "instr":"or a1, a1, a3"}
+%def op_or_long():
+%  binopWide(preinstr="or a0, a0, a2", instr="or a1, a1, a3")
diff --git a/runtime/interpreter/mterp/mips/op_or_long_2addr.S b/runtime/interpreter/mterp/mips/op_or_long_2addr.S
index 43c3d05d41667add386de2ffe2d82420cc4fac89..f9b2f9c13e686d1a7e8fe021f0cf2f2a6d95dbcc 100644
--- a/runtime/interpreter/mterp/mips/op_or_long_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_or_long_2addr.S
@@ -1 +1,2 @@
-%include "mips/binopWide2addr.S" {"preinstr":"or a0, a0, a2", "instr":"or a1, a1, a3"}
+%def op_or_long_2addr():
+%  binopWide2addr(preinstr="or a0, a0, a2", instr="or a1, a1, a3")
diff --git a/runtime/interpreter/mterp/mips/op_packed_switch.S b/runtime/interpreter/mterp/mips/op_packed_switch.S
index 0a1ff989c1fdb35eeada087deefb6f77b0981b77..e18a652f65026383190bae427d11ebda41b31d61 100644
--- a/runtime/interpreter/mterp/mips/op_packed_switch.S
+++ b/runtime/interpreter/mterp/mips/op_packed_switch.S
@@ -1,4 +1,4 @@
-%default { "func":"MterpDoPackedSwitch" }
+%def op_packed_switch(func="MterpDoPackedSwitch"):
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
diff --git a/runtime/interpreter/mterp/mips/op_rem_double.S b/runtime/interpreter/mterp/mips/op_rem_double.S
index a6890a8029ee8430d5bbc2825c625d31af9d61a7..99857a383f69afc581b55413f6b1f9257b5927f3 100644
--- a/runtime/interpreter/mterp/mips/op_rem_double.S
+++ b/runtime/interpreter/mterp/mips/op_rem_double.S
@@ -1 +1,2 @@
-%include "mips/fbinopWide.S" {"instr":"JAL(fmod)"}
+%def op_rem_double():
+%  fbinopWide(instr="JAL(fmod)")
diff --git a/runtime/interpreter/mterp/mips/op_rem_double_2addr.S b/runtime/interpreter/mterp/mips/op_rem_double_2addr.S
index a24e1604fac707642b924536ce566101ce10c0c7..cf2d3a7456103408146a098291284f1030bcf3fb 100644
--- a/runtime/interpreter/mterp/mips/op_rem_double_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_rem_double_2addr.S
@@ -1 +1,2 @@
-%include "mips/fbinopWide2addr.S" {"instr":"JAL(fmod)"}
+%def op_rem_double_2addr():
+%  fbinopWide2addr(instr="JAL(fmod)")
diff --git a/runtime/interpreter/mterp/mips/op_rem_float.S b/runtime/interpreter/mterp/mips/op_rem_float.S
index ac3d50ce75f02afa20a08833289543345cf505d0..2295ae58ed2821c15403ac59eb14cd240b6c4069 100644
--- a/runtime/interpreter/mterp/mips/op_rem_float.S
+++ b/runtime/interpreter/mterp/mips/op_rem_float.S
@@ -1 +1,2 @@
-%include "mips/fbinop.S" {"instr":"JAL(fmodf)"}
+%def op_rem_float():
+%  fbinop(instr="JAL(fmodf)")
diff --git a/runtime/interpreter/mterp/mips/op_rem_float_2addr.S b/runtime/interpreter/mterp/mips/op_rem_float_2addr.S
index 7f0a9320c82fda042d1ba808f5f74bf7e6e4c471..9f6abee39019ea56d4d2b42f43a711be2a996a43 100644
--- a/runtime/interpreter/mterp/mips/op_rem_float_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_rem_float_2addr.S
@@ -1 +1,2 @@
-%include "mips/fbinop2addr.S" {"instr":"JAL(fmodf)"}
+%def op_rem_float_2addr():
+%  fbinop2addr(instr="JAL(fmodf)")
diff --git a/runtime/interpreter/mterp/mips/op_rem_int.S b/runtime/interpreter/mterp/mips/op_rem_int.S
index c2a334a8791a811201c12d5c9ec4647129b52cc6..2f67adc1c70ce52648386a37f788a17518dbace0 100644
--- a/runtime/interpreter/mterp/mips/op_rem_int.S
+++ b/runtime/interpreter/mterp/mips/op_rem_int.S
@@ -1,5 +1,6 @@
+%def op_rem_int():
 #ifdef MIPS32REVGE6
-%include "mips/binop.S" {"instr":"mod a0, a0, a1", "chkzero":"1"}
+%  binop(instr="mod a0, a0, a1", chkzero="1")
 #else
-%include "mips/binop.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"}
+%  binop(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1")
 #endif
diff --git a/runtime/interpreter/mterp/mips/op_rem_int_2addr.S b/runtime/interpreter/mterp/mips/op_rem_int_2addr.S
index 46c353fa83f574d79f7a9ff732b6ff104c7397ca..78766a7b55c1267bca3b8e794451111505eec2a5 100644
--- a/runtime/interpreter/mterp/mips/op_rem_int_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_rem_int_2addr.S
@@ -1,5 +1,6 @@
+%def op_rem_int_2addr():
 #ifdef MIPS32REVGE6
-%include "mips/binop2addr.S" {"instr":"mod a0, a0, a1", "chkzero":"1"}
+%  binop2addr(instr="mod a0, a0, a1", chkzero="1")
 #else
-%include "mips/binop2addr.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"}
+%  binop2addr(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1")
 #endif
diff --git a/runtime/interpreter/mterp/mips/op_rem_int_lit16.S b/runtime/interpreter/mterp/mips/op_rem_int_lit16.S
index 2894ad37a29c14fcfe63651a37dcc68b74d1d998..ce136cbf3742f0f62f799177f08ef5c83b3fa849 100644
--- a/runtime/interpreter/mterp/mips/op_rem_int_lit16.S
+++ b/runtime/interpreter/mterp/mips/op_rem_int_lit16.S
@@ -1,5 +1,6 @@
+%def op_rem_int_lit16():
 #ifdef MIPS32REVGE6
-%include "mips/binopLit16.S" {"instr":"mod a0, a0, a1", "chkzero":"1"}
+%  binopLit16(instr="mod a0, a0, a1", chkzero="1")
 #else
-%include "mips/binopLit16.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"}
+%  binopLit16(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1")
 #endif
diff --git a/runtime/interpreter/mterp/mips/op_rem_int_lit8.S b/runtime/interpreter/mterp/mips/op_rem_int_lit8.S
index 582248ba8fe4e70ec50afe53f02ce259f0c7c54f..0a5084449dde8820c095a9c8e30d76a44c4571af 100644
--- a/runtime/interpreter/mterp/mips/op_rem_int_lit8.S
+++ b/runtime/interpreter/mterp/mips/op_rem_int_lit8.S
@@ -1,5 +1,6 @@
+%def op_rem_int_lit8():
 #ifdef MIPS32REVGE6
-%include "mips/binopLit8.S" {"instr":"mod a0, a0, a1", "chkzero":"1"}
+%  binopLit8(instr="mod a0, a0, a1", chkzero="1")
 #else
-%include "mips/binopLit8.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"}
+%  binopLit8(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1")
 #endif
diff --git a/runtime/interpreter/mterp/mips/op_rem_long.S b/runtime/interpreter/mterp/mips/op_rem_long.S
index e3eb19bed4a5ac0ef5a2749050575a5eac9fe030..2403deccc29cbbdea9f2a57db3af363a43cdc8e5 100644
--- a/runtime/interpreter/mterp/mips/op_rem_long.S
+++ b/runtime/interpreter/mterp/mips/op_rem_long.S
@@ -1 +1,2 @@
-%include "mips/binopWide.S" { "result0":"v0", "result1":"v1", "instr":"JAL(__moddi3)", "chkzero":"1"}
+%def op_rem_long():
+%  binopWide(result0="v0", result1="v1", instr="JAL(__moddi3)", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips/op_rem_long_2addr.S b/runtime/interpreter/mterp/mips/op_rem_long_2addr.S
index 8fc9fdb15f5a1d5983f563719061024c455b470c..6cf3c09cea3c57ca1b2fca8a6e7e95c5f87f5b76 100644
--- a/runtime/interpreter/mterp/mips/op_rem_long_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_rem_long_2addr.S
@@ -1 +1,2 @@
-%include "mips/binopWide2addr.S" { "result0":"v0", "result1":"v1", "instr":"JAL(__moddi3)", "chkzero":"1"}
+%def op_rem_long_2addr():
+%  binopWide2addr(result0="v0", result1="v1", instr="JAL(__moddi3)", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips/op_return.S b/runtime/interpreter/mterp/mips/op_return.S
index 44b93958d2fd3ca8224b2af9bd1c561874894ab0..4e422d29993c76a7619a2d930d78245d732b0e38 100644
--- a/runtime/interpreter/mterp/mips/op_return.S
+++ b/runtime/interpreter/mterp/mips/op_return.S
@@ -1,3 +1,4 @@
+%def op_return():
     /*
      * Return a 32-bit value.
      *
diff --git a/runtime/interpreter/mterp/mips/op_return_object.S b/runtime/interpreter/mterp/mips/op_return_object.S
index 7350e008c552a98cf1a7e5aa167cba4309e842cf..2eeec0b94824884ff1b3c0aeccbfa0948268f9ab 100644
--- a/runtime/interpreter/mterp/mips/op_return_object.S
+++ b/runtime/interpreter/mterp/mips/op_return_object.S
@@ -1 +1,2 @@
-%include "mips/op_return.S"
+%def op_return_object():
+%  op_return()
diff --git a/runtime/interpreter/mterp/mips/op_return_void.S b/runtime/interpreter/mterp/mips/op_return_void.S
index 1f616ea198b7cb6828052251f92e53e1f0943db5..14e532b6f9fbf1e55305aefc3ced1515f0668fbf 100644
--- a/runtime/interpreter/mterp/mips/op_return_void.S
+++ b/runtime/interpreter/mterp/mips/op_return_void.S
@@ -1,3 +1,4 @@
+%def op_return_void():
     .extern MterpThreadFenceForConstructor
     JAL(MterpThreadFenceForConstructor)
     lw        ra, THREAD_FLAGS_OFFSET(rSELF)
diff --git a/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S b/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S
index e670c2867ff4a7a8116c6a3f5949a9f2064a0a19..a74f0855d1f17953d80fc36ec21f43a751ff281b 100644
--- a/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S
+++ b/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S
@@ -1,3 +1,4 @@
+%def op_return_void_no_barrier():
     lw     ra, THREAD_FLAGS_OFFSET(rSELF)
     move   a0, rSELF
     and    ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
diff --git a/runtime/interpreter/mterp/mips/op_return_wide.S b/runtime/interpreter/mterp/mips/op_return_wide.S
index f0f679dbde11c50677269772ace410e2c27ea2c9..fb065a56d60acf31ccb875b852683e1d54f308f8 100644
--- a/runtime/interpreter/mterp/mips/op_return_wide.S
+++ b/runtime/interpreter/mterp/mips/op_return_wide.S
@@ -1,3 +1,4 @@
+%def op_return_wide():
     /*
      * Return a 64-bit value.
      */
diff --git a/runtime/interpreter/mterp/mips/op_rsub_int.S b/runtime/interpreter/mterp/mips/op_rsub_int.S
index f7e61bb2e91b5841b28b3bfd87541ebab9221975..21ead06dbf698df2945c13b83bf712af4ff2d576 100644
--- a/runtime/interpreter/mterp/mips/op_rsub_int.S
+++ b/runtime/interpreter/mterp/mips/op_rsub_int.S
@@ -1,2 +1,3 @@
+%def op_rsub_int():
 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
-%include "mips/binopLit16.S" {"instr":"subu a0, a1, a0"}
+%  binopLit16(instr="subu a0, a1, a0")
diff --git a/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S b/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S
index 3968a5ef8ca2e2ac26c20c2a6df8bb6d0a0e11a2..b9b214da945fbd6e0383695c1337751d0168e3fd 100644
--- a/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S
+++ b/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S
@@ -1 +1,2 @@
-%include "mips/binopLit8.S" {"instr":"subu a0, a1, a0"}
+%def op_rsub_int_lit8():
+%  binopLit8(instr="subu a0, a1, a0")
diff --git a/runtime/interpreter/mterp/mips/op_sget.S b/runtime/interpreter/mterp/mips/op_sget.S
index 92d667335b9d361a5590f547b71d760a194195a3..8a6a66ab6032f5a140fcaa4cb0f85af9cb84bd7a 100644
--- a/runtime/interpreter/mterp/mips/op_sget.S
+++ b/runtime/interpreter/mterp/mips/op_sget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSGetU32" }
-%include "mips/field.S" { }
+%def op_sget(is_object="0", helper="MterpSGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/mips/op_sget_boolean.S b/runtime/interpreter/mterp/mips/op_sget_boolean.S
index 7a7012e81f43bee8e36a8303aec3f2aa3691a9fc..d9c12c9b280100ec8c517e2c264d9c99022bb429 100644
--- a/runtime/interpreter/mterp/mips/op_sget_boolean.S
+++ b/runtime/interpreter/mterp/mips/op_sget_boolean.S
@@ -1 +1,2 @@
-%include "mips/op_sget.S" {"helper":"MterpSGetU8"}
+%def op_sget_boolean():
+%  op_sget(helper="MterpSGetU8")
diff --git a/runtime/interpreter/mterp/mips/op_sget_byte.S b/runtime/interpreter/mterp/mips/op_sget_byte.S
index a2f1dbf606fd79c8dd7a90f83623834d18f23add..37c6879cd4b02e1fe323434a8f0e490352d4d391 100644
--- a/runtime/interpreter/mterp/mips/op_sget_byte.S
+++ b/runtime/interpreter/mterp/mips/op_sget_byte.S
@@ -1 +1,2 @@
-%include "mips/op_sget.S" {"helper":"MterpSGetI8"}
+%def op_sget_byte():
+%  op_sget(helper="MterpSGetI8")
diff --git a/runtime/interpreter/mterp/mips/op_sget_char.S b/runtime/interpreter/mterp/mips/op_sget_char.S
index 07d40416a3dd06852725dcc13a1d42769ed17eea..003bcd16833da0b4c77b8ef60e71ee9bbb01e8da 100644
--- a/runtime/interpreter/mterp/mips/op_sget_char.S
+++ b/runtime/interpreter/mterp/mips/op_sget_char.S
@@ -1 +1,2 @@
-%include "mips/op_sget.S" {"helper":"MterpSGetU16"}
+%def op_sget_char():
+%  op_sget(helper="MterpSGetU16")
diff --git a/runtime/interpreter/mterp/mips/op_sget_object.S b/runtime/interpreter/mterp/mips/op_sget_object.S
index 0a3c9eef886a556058d534a3d60fc17050dd6531..7cf3597f44f59b999d828d0749f53401e98cfee6 100644
--- a/runtime/interpreter/mterp/mips/op_sget_object.S
+++ b/runtime/interpreter/mterp/mips/op_sget_object.S
@@ -1 +1,2 @@
-%include "mips/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"}
+%def op_sget_object():
+%  op_sget(is_object="1", helper="MterpSGetObj")
diff --git a/runtime/interpreter/mterp/mips/op_sget_short.S b/runtime/interpreter/mterp/mips/op_sget_short.S
index 29604430f2369f2212c2dd112b8609c8358c6d63..afacb578d90caf9455c969edfe13663d0927cb03 100644
--- a/runtime/interpreter/mterp/mips/op_sget_short.S
+++ b/runtime/interpreter/mterp/mips/op_sget_short.S
@@ -1 +1,2 @@
-%include "mips/op_sget.S" {"helper":"MterpSGetI16"}
+%def op_sget_short():
+%  op_sget(helper="MterpSGetI16")
diff --git a/runtime/interpreter/mterp/mips/op_sget_wide.S b/runtime/interpreter/mterp/mips/op_sget_wide.S
index be4ae027cb2fefff4cfe796ee0d2a06ce3bfdf1b..fff2be6945510278d990141764285ab694e302ed 100644
--- a/runtime/interpreter/mterp/mips/op_sget_wide.S
+++ b/runtime/interpreter/mterp/mips/op_sget_wide.S
@@ -1 +1,2 @@
-%include "mips/op_sget.S" {"helper":"MterpSGetU64"}
+%def op_sget_wide():
+%  op_sget(helper="MterpSGetU64")
diff --git a/runtime/interpreter/mterp/mips/op_shl_int.S b/runtime/interpreter/mterp/mips/op_shl_int.S
index 15cbe94113794a170266f9cb638707e46ea570f0..efd213c09a5fa761c0d90192f6a3cee89518d231 100644
--- a/runtime/interpreter/mterp/mips/op_shl_int.S
+++ b/runtime/interpreter/mterp/mips/op_shl_int.S
@@ -1 +1,2 @@
-%include "mips/binop.S" {"instr":"sll a0, a0, a1"}
+%def op_shl_int():
+%  binop(instr="sll a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_shl_int_2addr.S b/runtime/interpreter/mterp/mips/op_shl_int_2addr.S
index ef9bd655ab71fc20df673187430685ca03d49b1f..0901e6b65a2aa3182a34be7ed5c066740532dc07 100644
--- a/runtime/interpreter/mterp/mips/op_shl_int_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_shl_int_2addr.S
@@ -1 +1,2 @@
-%include "mips/binop2addr.S" {"instr":"sll a0, a0, a1"}
+%def op_shl_int_2addr():
+%  binop2addr(instr="sll a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_shl_int_lit8.S b/runtime/interpreter/mterp/mips/op_shl_int_lit8.S
index d2afb53e14e64359f760501779928554deba2be1..2263ec70c23fcc6c00bbda107bc6e34f481de74c 100644
--- a/runtime/interpreter/mterp/mips/op_shl_int_lit8.S
+++ b/runtime/interpreter/mterp/mips/op_shl_int_lit8.S
@@ -1 +1,2 @@
-%include "mips/binopLit8.S" {"instr":"sll a0, a0, a1"}
+%def op_shl_int_lit8():
+%  binopLit8(instr="sll a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_shl_long.S b/runtime/interpreter/mterp/mips/op_shl_long.S
index cc0811295b777e6a76b4e518295217a8dfac1fcb..8bb4216425841df771a6e54ee790be70664d42d7 100644
--- a/runtime/interpreter/mterp/mips/op_shl_long.S
+++ b/runtime/interpreter/mterp/mips/op_shl_long.S
@@ -1,3 +1,4 @@
+%def op_shl_long():
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -25,7 +26,7 @@
     sll     v1, a1, a2                     #  rhi<- ahi << (shift&31)
     or      v1, a0                         #  rhi<- rhi | alo
     SET_VREG64_GOTO(v0, v1, t2, t0)        #  vAA/vAA+1 <- v0/v1
-%break
+%def op_shl_long_sister_code():
 
 .L${opcode}_finish:
     SET_VREG64_GOTO(zero, v0, t2, t0)      #  vAA/vAA+1 <- rlo/rhi
diff --git a/runtime/interpreter/mterp/mips/op_shl_long_2addr.S b/runtime/interpreter/mterp/mips/op_shl_long_2addr.S
index 93c578353ee74091a8dda75ac7e00c72a90ca530..12015f5b153cff7df8d604ee1946eed84fd55654 100644
--- a/runtime/interpreter/mterp/mips/op_shl_long_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_shl_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_shl_long_2addr():
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
@@ -21,7 +22,7 @@
     sll     v1, a1, a2                     #  rhi<- ahi << (shift&31)
     or      v1, a0                         #  rhi<- rhi | alo
     SET_VREG64_GOTO(v0, v1, rOBJ, t0)      #  vA/vA+1 <- v0/v1
-%break
+%def op_shl_long_2addr_sister_code():
 
 .L${opcode}_finish:
     SET_VREG64_GOTO(zero, v0, rOBJ, t0)    #  vA/vA+1 <- rlo/rhi
diff --git a/runtime/interpreter/mterp/mips/op_shr_int.S b/runtime/interpreter/mterp/mips/op_shr_int.S
index 611083999946fa2ab3a9d28171855393ea0e6232..8d55e7afa9a0597d94652c61518b2e3e6a9e4c5e 100644
--- a/runtime/interpreter/mterp/mips/op_shr_int.S
+++ b/runtime/interpreter/mterp/mips/op_shr_int.S
@@ -1 +1,2 @@
-%include "mips/binop.S" {"instr":"sra a0, a0, a1"}
+%def op_shr_int():
+%  binop(instr="sra a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_shr_int_2addr.S b/runtime/interpreter/mterp/mips/op_shr_int_2addr.S
index e00ff5b2e6387c829286837c19d5e753a8eade97..e102baa99f545cbb45da064672ddae74c4d7dcd4 100644
--- a/runtime/interpreter/mterp/mips/op_shr_int_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_shr_int_2addr.S
@@ -1 +1,2 @@
-%include "mips/binop2addr.S" {"instr":"sra a0, a0, a1"}
+%def op_shr_int_2addr():
+%  binop2addr(instr="sra a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_shr_int_lit8.S b/runtime/interpreter/mterp/mips/op_shr_int_lit8.S
index d058f5862cfbbb9419b1a31925b03a8631c68507..437c5c49a6730ed184795e3aa091c640a23b1766 100644
--- a/runtime/interpreter/mterp/mips/op_shr_int_lit8.S
+++ b/runtime/interpreter/mterp/mips/op_shr_int_lit8.S
@@ -1 +1,2 @@
-%include "mips/binopLit8.S" {"instr":"sra a0, a0, a1"}
+%def op_shr_int_lit8():
+%  binopLit8(instr="sra a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_shr_long.S b/runtime/interpreter/mterp/mips/op_shr_long.S
index ea032fe9a072f4b7047cb9665173e8eaaad1b049..adffa615a1efd609e6b2fc227d5880b5c6afb31f 100644
--- a/runtime/interpreter/mterp/mips/op_shr_long.S
+++ b/runtime/interpreter/mterp/mips/op_shr_long.S
@@ -1,3 +1,4 @@
+%def op_shr_long():
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -24,7 +25,7 @@
     sll     a1, a0                         #  ahi<- ahi << (32-(shift&31))
     or      v0, a1                         #  rlo<- rlo | ahi
     SET_VREG64_GOTO(v0, v1, t3, t0)        #  vAA/VAA+1 <- v0/v1
-%break
+%def op_shr_long_sister_code():
 
 .L${opcode}_finish:
     sra     a3, a1, 31                     #  a3<- sign(ah)
diff --git a/runtime/interpreter/mterp/mips/op_shr_long_2addr.S b/runtime/interpreter/mterp/mips/op_shr_long_2addr.S
index c805ea424fb254f65a231a07f5682411bcc8222b..d8acb790b6d4958371a48f1c63b44a64d4903c17 100644
--- a/runtime/interpreter/mterp/mips/op_shr_long_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_shr_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_shr_long_2addr():
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
@@ -20,7 +21,7 @@
     sll     a1, a0                         #  ahi<- ahi << (32-(shift&31))
     or      v0, a1                         #  rlo<- rlo | ahi
     SET_VREG64_GOTO(v0, v1, t2, t0)        #  vA/vA+1 <- v0/v1
-%break
+%def op_shr_long_2addr_sister_code():
 
 .L${opcode}_finish:
     sra     a3, a1, 31                     #  a3<- sign(ah)
diff --git a/runtime/interpreter/mterp/mips/op_sparse_switch.S b/runtime/interpreter/mterp/mips/op_sparse_switch.S
index 670f4648a8595df099bde21167e0bf68571885c4..b74d7da81633f307dbf7c07ffaada2d14f131ec3 100644
--- a/runtime/interpreter/mterp/mips/op_sparse_switch.S
+++ b/runtime/interpreter/mterp/mips/op_sparse_switch.S
@@ -1 +1,2 @@
-%include "mips/op_packed_switch.S" { "func":"MterpDoSparseSwitch" }
+%def op_sparse_switch():
+%  op_packed_switch(func="MterpDoSparseSwitch")
diff --git a/runtime/interpreter/mterp/mips/op_sput.S b/runtime/interpreter/mterp/mips/op_sput.S
index c858679762d85e9940901f7ce23b52ee3035d464..cbd6ee96d345758221edb4c7f71dd2dda57ac8f0 100644
--- a/runtime/interpreter/mterp/mips/op_sput.S
+++ b/runtime/interpreter/mterp/mips/op_sput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSPutU32"}
-%include "mips/field.S" { }
+%def op_sput(is_object="0", helper="MterpSPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/mips/op_sput_boolean.S b/runtime/interpreter/mterp/mips/op_sput_boolean.S
index 0137430acce9cde80365f99d48d649d9e11bf031..36fba8448b478323ce47a26f2a4d79accbf9964d 100644
--- a/runtime/interpreter/mterp/mips/op_sput_boolean.S
+++ b/runtime/interpreter/mterp/mips/op_sput_boolean.S
@@ -1 +1,2 @@
-%include "mips/op_sput.S" {"helper":"MterpSPutU8"}
+%def op_sput_boolean():
+%  op_sput(helper="MterpSPutU8")
diff --git a/runtime/interpreter/mterp/mips/op_sput_byte.S b/runtime/interpreter/mterp/mips/op_sput_byte.S
index 5ae4256a989f6aa64676cb853f37fc30aa21cc5f..84ad4a0ff86ccfcd1159672dac902ee99cfc37d9 100644
--- a/runtime/interpreter/mterp/mips/op_sput_byte.S
+++ b/runtime/interpreter/mterp/mips/op_sput_byte.S
@@ -1 +1,2 @@
-%include "mips/op_sput.S" {"helper":"MterpSPutI8"}
+%def op_sput_byte():
+%  op_sput(helper="MterpSPutI8")
diff --git a/runtime/interpreter/mterp/mips/op_sput_char.S b/runtime/interpreter/mterp/mips/op_sput_char.S
index 83787a7753a44c2cb131204246baeea876a58a63..9b8eeba578f555750ab9497c8fc21ce4a52e8b89 100644
--- a/runtime/interpreter/mterp/mips/op_sput_char.S
+++ b/runtime/interpreter/mterp/mips/op_sput_char.S
@@ -1 +1,2 @@
-%include "mips/op_sput.S" {"helper":"MterpSPutU16"}
+%def op_sput_char():
+%  op_sput(helper="MterpSPutU16")
diff --git a/runtime/interpreter/mterp/mips/op_sput_object.S b/runtime/interpreter/mterp/mips/op_sput_object.S
index 683b76789d084f9248f0362d7cd8a632cdd9211f..081360c40fb12c03e3a48c24a3677ee55a609758 100644
--- a/runtime/interpreter/mterp/mips/op_sput_object.S
+++ b/runtime/interpreter/mterp/mips/op_sput_object.S
@@ -1 +1,2 @@
-%include "mips/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"}
+%def op_sput_object():
+%  op_sput(is_object="1", helper="MterpSPutObj")
diff --git a/runtime/interpreter/mterp/mips/op_sput_short.S b/runtime/interpreter/mterp/mips/op_sput_short.S
index df99b4414d7f94c8ed6d6460b7f5631ee34def3b..ee16513486189f1a65fe9922285fe9ae08606b97 100644
--- a/runtime/interpreter/mterp/mips/op_sput_short.S
+++ b/runtime/interpreter/mterp/mips/op_sput_short.S
@@ -1 +1,2 @@
-%include "mips/op_sput.S" {"helper":"MterpSPutI16"}
+%def op_sput_short():
+%  op_sput(helper="MterpSPutI16")
diff --git a/runtime/interpreter/mterp/mips/op_sput_wide.S b/runtime/interpreter/mterp/mips/op_sput_wide.S
index 1d2ed196f30c58e4829c43a4cec4c72dc103d4de..44c1a188edf6bb3cf29011f1b361701ae71aaf9c 100644
--- a/runtime/interpreter/mterp/mips/op_sput_wide.S
+++ b/runtime/interpreter/mterp/mips/op_sput_wide.S
@@ -1 +1,2 @@
-%include "mips/op_sput.S" {"helper":"MterpSPutU64"}
+%def op_sput_wide():
+%  op_sput(helper="MterpSPutU64")
diff --git a/runtime/interpreter/mterp/mips/op_sub_double.S b/runtime/interpreter/mterp/mips/op_sub_double.S
index 9473218e89324e45b4a6c77fce31ce3bed4483f0..ad8f12cfb3578bde83db8700938f3aeeb83cb411 100644
--- a/runtime/interpreter/mterp/mips/op_sub_double.S
+++ b/runtime/interpreter/mterp/mips/op_sub_double.S
@@ -1 +1,2 @@
-%include "mips/fbinopWide.S" {"instr":"sub.d fv0, fa0, fa1"}
+%def op_sub_double():
+%  fbinopWide(instr="sub.d fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_sub_double_2addr.S b/runtime/interpreter/mterp/mips/op_sub_double_2addr.S
index 7ce7c74330aa83cb4b0849108f43746e557e84a2..ed5598d2a43086782b1a569d9a65c5e94922084e 100644
--- a/runtime/interpreter/mterp/mips/op_sub_double_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_sub_double_2addr.S
@@ -1 +1,2 @@
-%include "mips/fbinopWide2addr.S" {"instr":"sub.d fv0, fa0, fa1"}
+%def op_sub_double_2addr():
+%  fbinopWide2addr(instr="sub.d fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_sub_float.S b/runtime/interpreter/mterp/mips/op_sub_float.S
index 04650d9125b24f5fae4ed6d1c7c1d56764795114..402fa2cfd79771c2b6704802eb7105d2bcd5d191 100644
--- a/runtime/interpreter/mterp/mips/op_sub_float.S
+++ b/runtime/interpreter/mterp/mips/op_sub_float.S
@@ -1 +1,2 @@
-%include "mips/fbinop.S" {"instr":"sub.s fv0, fa0, fa1"}
+%def op_sub_float():
+%  fbinop(instr="sub.s fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_sub_float_2addr.S b/runtime/interpreter/mterp/mips/op_sub_float_2addr.S
index dfe935c8cfec5878c0fdf639585dffc47abeafa8..1d381880480c8f0ba309803774d701107db241af 100644
--- a/runtime/interpreter/mterp/mips/op_sub_float_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_sub_float_2addr.S
@@ -1 +1,2 @@
-%include "mips/fbinop2addr.S" {"instr":"sub.s fv0, fa0, fa1"}
+%def op_sub_float_2addr():
+%  fbinop2addr(instr="sub.s fv0, fa0, fa1")
diff --git a/runtime/interpreter/mterp/mips/op_sub_int.S b/runtime/interpreter/mterp/mips/op_sub_int.S
index 43da1b617a853384abdc4122a88edc8f751de104..57f618d65a1a53e485bbd7505ca5ec9b7c07c70c 100644
--- a/runtime/interpreter/mterp/mips/op_sub_int.S
+++ b/runtime/interpreter/mterp/mips/op_sub_int.S
@@ -1 +1,2 @@
-%include "mips/binop.S" {"instr":"subu a0, a0, a1"}
+%def op_sub_int():
+%  binop(instr="subu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_sub_int_2addr.S b/runtime/interpreter/mterp/mips/op_sub_int_2addr.S
index cf34aa69dc4ae5c9980b3943774dd6ddfe693885..445ffca50fe09d1fb39791ac1aca6e585cdf37a7 100644
--- a/runtime/interpreter/mterp/mips/op_sub_int_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_sub_int_2addr.S
@@ -1 +1,2 @@
-%include "mips/binop2addr.S" {"instr":"subu a0, a0, a1"}
+%def op_sub_int_2addr():
+%  binop2addr(instr="subu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_sub_long.S b/runtime/interpreter/mterp/mips/op_sub_long.S
index 0f58e8e891b41a14884d3721374cc5087b7dbe33..a54460b3b2fd97bc20adac09fd0062fdc2a5e9af 100644
--- a/runtime/interpreter/mterp/mips/op_sub_long.S
+++ b/runtime/interpreter/mterp/mips/op_sub_long.S
@@ -1,3 +1,4 @@
+%def op_sub_long():
 /*
  * For little endian the code sequence looks as follows:
  *    subu    v0,a0,a2
@@ -5,4 +6,4 @@
  *    sltu    a0,a0,v0
  *    subu    v1,v1,a0
  */
-%include "mips/binopWide.S" { "result0":"v0", "result1":"v1", "preinstr":"subu v0, a0, a2", "instr":"subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0" }
+%  binopWide(result0="v0", result1="v1", preinstr="subu v0, a0, a2", instr="subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0")
diff --git a/runtime/interpreter/mterp/mips/op_sub_long_2addr.S b/runtime/interpreter/mterp/mips/op_sub_long_2addr.S
index aa256c20f86951c95f11de8cec47e31c5c3cb774..b3dd6b2cd2ba62ebe734e0f2eb08c5fad8ec0cc6 100644
--- a/runtime/interpreter/mterp/mips/op_sub_long_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_sub_long_2addr.S
@@ -1,4 +1,5 @@
+%def op_sub_long_2addr():
 /*
  * See op_sub_long.S for more details
  */
-%include "mips/binopWide2addr.S" { "result0":"v0", "result1":"v1", "preinstr":"subu v0, a0, a2", "instr":"subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0" }
+%  binopWide2addr(result0="v0", result1="v1", preinstr="subu v0, a0, a2", instr="subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0")
diff --git a/runtime/interpreter/mterp/mips/op_throw.S b/runtime/interpreter/mterp/mips/op_throw.S
index adc8b047cae0cc133f2cc5e362297e9d261e6a24..84b9e5ecfc884f2c879cad4f493afc6f299762fc 100644
--- a/runtime/interpreter/mterp/mips/op_throw.S
+++ b/runtime/interpreter/mterp/mips/op_throw.S
@@ -1,3 +1,4 @@
+%def op_throw():
     /*
      * Throw an exception object in the current thread.
      */
diff --git a/runtime/interpreter/mterp/mips/op_unused_3e.S b/runtime/interpreter/mterp/mips/op_unused_3e.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..d889f1a5fb4be366ce5101882ae40577a9b0b90b 100644
--- a/runtime/interpreter/mterp/mips/op_unused_3e.S
+++ b/runtime/interpreter/mterp/mips/op_unused_3e.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_3e():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_3f.S b/runtime/interpreter/mterp/mips/op_unused_3f.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..b3ebcfaeaa402ba263610b3f305daf92cc23bebb 100644
--- a/runtime/interpreter/mterp/mips/op_unused_3f.S
+++ b/runtime/interpreter/mterp/mips/op_unused_3f.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_3f():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_40.S b/runtime/interpreter/mterp/mips/op_unused_40.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..7920fb350f2f93b310d33ec19166b6b8445bb0eb 100644
--- a/runtime/interpreter/mterp/mips/op_unused_40.S
+++ b/runtime/interpreter/mterp/mips/op_unused_40.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_40():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_41.S b/runtime/interpreter/mterp/mips/op_unused_41.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..5ed03b85065e78c670f3d26c62b6c56f58338d44 100644
--- a/runtime/interpreter/mterp/mips/op_unused_41.S
+++ b/runtime/interpreter/mterp/mips/op_unused_41.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_41():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_42.S b/runtime/interpreter/mterp/mips/op_unused_42.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..ac32521add543fb2f858aa858af6c3d5594f187e 100644
--- a/runtime/interpreter/mterp/mips/op_unused_42.S
+++ b/runtime/interpreter/mterp/mips/op_unused_42.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_42():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_43.S b/runtime/interpreter/mterp/mips/op_unused_43.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..33e2aa10f8bec8407ff8090cfd81dda49b2a19b8 100644
--- a/runtime/interpreter/mterp/mips/op_unused_43.S
+++ b/runtime/interpreter/mterp/mips/op_unused_43.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_43():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_73.S b/runtime/interpreter/mterp/mips/op_unused_73.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..e3267a30a120e465d19d0a578e37174df1bf8e21 100644
--- a/runtime/interpreter/mterp/mips/op_unused_73.S
+++ b/runtime/interpreter/mterp/mips/op_unused_73.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_73():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_79.S b/runtime/interpreter/mterp/mips/op_unused_79.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..3c6dafc7898855a1034ff93b17bed71a07df1e51 100644
--- a/runtime/interpreter/mterp/mips/op_unused_79.S
+++ b/runtime/interpreter/mterp/mips/op_unused_79.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_79():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_7a.S b/runtime/interpreter/mterp/mips/op_unused_7a.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..9c03cd55355a41369dc85dbea7e07e7bd8e96383 100644
--- a/runtime/interpreter/mterp/mips/op_unused_7a.S
+++ b/runtime/interpreter/mterp/mips/op_unused_7a.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_7a():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_f3.S b/runtime/interpreter/mterp/mips/op_unused_f3.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..ab10b78be2a0b681652d52185cf7c39d3403a41e 100644
--- a/runtime/interpreter/mterp/mips/op_unused_f3.S
+++ b/runtime/interpreter/mterp/mips/op_unused_f3.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_f3():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_f4.S b/runtime/interpreter/mterp/mips/op_unused_f4.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..09229d6d99f58a24b923c56b2937662a10e16de6 100644
--- a/runtime/interpreter/mterp/mips/op_unused_f4.S
+++ b/runtime/interpreter/mterp/mips/op_unused_f4.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_f4():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_f5.S b/runtime/interpreter/mterp/mips/op_unused_f5.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..0d6149b5fd6eeb0221067adb660d453080ba1fd2 100644
--- a/runtime/interpreter/mterp/mips/op_unused_f5.S
+++ b/runtime/interpreter/mterp/mips/op_unused_f5.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_f5():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_f6.S b/runtime/interpreter/mterp/mips/op_unused_f6.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..117b03de6d321ace7f917fe69b79b9f182081e11 100644
--- a/runtime/interpreter/mterp/mips/op_unused_f6.S
+++ b/runtime/interpreter/mterp/mips/op_unused_f6.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_f6():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_f7.S b/runtime/interpreter/mterp/mips/op_unused_f7.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..4e3a0f3c9a6eef078506555805a72056272abfc1 100644
--- a/runtime/interpreter/mterp/mips/op_unused_f7.S
+++ b/runtime/interpreter/mterp/mips/op_unused_f7.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_f7():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_f8.S b/runtime/interpreter/mterp/mips/op_unused_f8.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..d1220752d7b5b191c0712bf975e90ac7777e4303 100644
--- a/runtime/interpreter/mterp/mips/op_unused_f8.S
+++ b/runtime/interpreter/mterp/mips/op_unused_f8.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_f8():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_f9.S b/runtime/interpreter/mterp/mips/op_unused_f9.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..7d09a0ebcfce77f4a1bd8b19865ac5d782e382dd 100644
--- a/runtime/interpreter/mterp/mips/op_unused_f9.S
+++ b/runtime/interpreter/mterp/mips/op_unused_f9.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_f9():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_fc.S b/runtime/interpreter/mterp/mips/op_unused_fc.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..06978191ebbcceb51b9820b3e650a0baf767a507 100644
--- a/runtime/interpreter/mterp/mips/op_unused_fc.S
+++ b/runtime/interpreter/mterp/mips/op_unused_fc.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_fc():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_unused_fd.S b/runtime/interpreter/mterp/mips/op_unused_fd.S
index 99ef3cf3082af1624b138c623dd253b795e84c52..4bc2b4bdb6516467406cb88476e1d993a3f0c749 100644
--- a/runtime/interpreter/mterp/mips/op_unused_fd.S
+++ b/runtime/interpreter/mterp/mips/op_unused_fd.S
@@ -1 +1,2 @@
-%include "mips/unused.S"
+%def op_unused_fd():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips/op_ushr_int.S b/runtime/interpreter/mterp/mips/op_ushr_int.S
index b95472b30e6fe396f4d68d25020562c3b2de6d34..98d2dfbc9c63cf1ef0c1321180c1ec7f6acdc9ca 100644
--- a/runtime/interpreter/mterp/mips/op_ushr_int.S
+++ b/runtime/interpreter/mterp/mips/op_ushr_int.S
@@ -1 +1,2 @@
-%include "mips/binop.S" {"instr":"srl a0, a0, a1"}
+%def op_ushr_int():
+%  binop(instr="srl a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S b/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S
index fc1777810099328e64836a6aa56f06fa172f89e6..4b09cacabc04ac6f29f8d7466f06398cfc7d96b8 100644
--- a/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S
@@ -1 +1,2 @@
-%include "mips/binop2addr.S" {"instr":"srl a0, a0, a1 "}
+%def op_ushr_int_2addr():
+%  binop2addr(instr="srl a0, a0, a1 ")
diff --git a/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S b/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S
index c82cfba15c37e67b5a6cba15f27976d7dd410242..531c30a000f3c42e6d17add7d952b4a51a402c3e 100644
--- a/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S
+++ b/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S
@@ -1 +1,2 @@
-%include "mips/binopLit8.S" {"instr":"srl a0, a0, a1"}
+%def op_ushr_int_lit8():
+%  binopLit8(instr="srl a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_ushr_long.S b/runtime/interpreter/mterp/mips/op_ushr_long.S
index 2e227a94af674d9a9185aa9f4fa220fbc542000b..b09e7b3c6afad3a96f09adfca2859b9fb87da740 100644
--- a/runtime/interpreter/mterp/mips/op_ushr_long.S
+++ b/runtime/interpreter/mterp/mips/op_ushr_long.S
@@ -1,3 +1,4 @@
+%def op_ushr_long():
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -25,7 +26,7 @@
     sll       a1, a0                       #  ahi<- ahi << (32-(shift&31))
     or        v0, a1                       #  rlo<- rlo | ahi
     SET_VREG64_GOTO(v0, v1, rOBJ, t0)      #  vAA/vAA+1 <- v0/v1
-%break
+%def op_ushr_long_sister_code():
 
 .L${opcode}_finish:
     SET_VREG64_GOTO(v1, zero, rOBJ, t0)    #  vAA/vAA+1 <- rlo/rhi
diff --git a/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S b/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S
index 9e93f34cdb6f354ce8f907a9afb1fd1610fad3fb..0da2011e6acabcdf82d36e6ddaf5c7e7804cc2be 100644
--- a/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_ushr_long_2addr():
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
@@ -21,7 +22,7 @@
     sll       a1, a0                       #  ahi<- ahi << (32-(shift&31))
     or        v0, a1                       #  rlo<- rlo | ahi
     SET_VREG64_GOTO(v0, v1, t3, t0)        #  vA/vA+1 <- v0/v1
-%break
+%def op_ushr_long_2addr_sister_code():
 
 .L${opcode}_finish:
     SET_VREG64_GOTO(v1, zero, t3, t0)      #  vA/vA+1 <- rlo/rhi
diff --git a/runtime/interpreter/mterp/mips/op_xor_int.S b/runtime/interpreter/mterp/mips/op_xor_int.S
index 6c23f1f3786ac8a4f1770970b8519ab5b7353dc6..1379a344e0e76feedb47ce67e11d712331def065 100644
--- a/runtime/interpreter/mterp/mips/op_xor_int.S
+++ b/runtime/interpreter/mterp/mips/op_xor_int.S
@@ -1 +1,2 @@
-%include "mips/binop.S" {"instr":"xor a0, a0, a1"}
+%def op_xor_int():
+%  binop(instr="xor a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_xor_int_2addr.S b/runtime/interpreter/mterp/mips/op_xor_int_2addr.S
index 5ee1667f8d76feb88be87031cab86796da2b96fb..6dbe11c3a8de505522b11bb85a7e4596bca990fd 100644
--- a/runtime/interpreter/mterp/mips/op_xor_int_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_xor_int_2addr.S
@@ -1 +1,2 @@
-%include "mips/binop2addr.S" {"instr":"xor a0, a0, a1"}
+%def op_xor_int_2addr():
+%  binop2addr(instr="xor a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_xor_int_lit16.S b/runtime/interpreter/mterp/mips/op_xor_int_lit16.S
index 2af37a611636261e6be2ed69c9edd5ec1507f487..f8cbce04f426f0ac2db2e4e2a69a1b5142eec4cd 100644
--- a/runtime/interpreter/mterp/mips/op_xor_int_lit16.S
+++ b/runtime/interpreter/mterp/mips/op_xor_int_lit16.S
@@ -1 +1,2 @@
-%include "mips/binopLit16.S" {"instr":"xor a0, a0, a1"}
+%def op_xor_int_lit16():
+%  binopLit16(instr="xor a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_xor_int_lit8.S b/runtime/interpreter/mterp/mips/op_xor_int_lit8.S
index 944ed692317d743d075b40b898666584a7553e39..268a43aac84dd24f14ee336d7b16844eb47ad8f3 100644
--- a/runtime/interpreter/mterp/mips/op_xor_int_lit8.S
+++ b/runtime/interpreter/mterp/mips/op_xor_int_lit8.S
@@ -1 +1,2 @@
-%include "mips/binopLit8.S" {"instr":"xor a0, a0, a1"}
+%def op_xor_int_lit8():
+%  binopLit8(instr="xor a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips/op_xor_long.S b/runtime/interpreter/mterp/mips/op_xor_long.S
index 93f8f70a2143033ce6436c474e081bae7039ca1f..5c0c64124318676878e64068e04790cf4ab64f6a 100644
--- a/runtime/interpreter/mterp/mips/op_xor_long.S
+++ b/runtime/interpreter/mterp/mips/op_xor_long.S
@@ -1 +1,2 @@
-%include "mips/binopWide.S" {"preinstr":"xor a0, a0, a2", "instr":"xor a1, a1, a3"}
+%def op_xor_long():
+%  binopWide(preinstr="xor a0, a0, a2", instr="xor a1, a1, a3")
diff --git a/runtime/interpreter/mterp/mips/op_xor_long_2addr.S b/runtime/interpreter/mterp/mips/op_xor_long_2addr.S
index 49f3fa42f44166ff1fe16b29270ca3e8cd1e300d..a84e9f05e0de31c612fa60cd610501826cef7fca 100644
--- a/runtime/interpreter/mterp/mips/op_xor_long_2addr.S
+++ b/runtime/interpreter/mterp/mips/op_xor_long_2addr.S
@@ -1 +1,2 @@
-%include "mips/binopWide2addr.S" {"preinstr":"xor a0, a0, a2", "instr":"xor a1, a1, a3"}
+%def op_xor_long_2addr():
+%  binopWide2addr(preinstr="xor a0, a0, a2", instr="xor a1, a1, a3")
diff --git a/runtime/interpreter/mterp/mips/unop.S b/runtime/interpreter/mterp/mips/unop.S
index bc99263adb61bcc71de1a11d119480c820baeb69..34eb1189463b61a0637b0ae51d20cf56b41aff9d 100644
--- a/runtime/interpreter/mterp/mips/unop.S
+++ b/runtime/interpreter/mterp/mips/unop.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result0":"a0"}
+%def unop(preinstr="", result0="a0", instr=""):
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result0 = op a0".
diff --git a/runtime/interpreter/mterp/mips/unopNarrower.S b/runtime/interpreter/mterp/mips/unopNarrower.S
index 0196e27e36fb9be499f5a238f64ed2d64c277589..4f0bb1dc1b7c76c66a438fd1cae87b34dd87d423 100644
--- a/runtime/interpreter/mterp/mips/unopNarrower.S
+++ b/runtime/interpreter/mterp/mips/unopNarrower.S
@@ -1,4 +1,4 @@
-%default {"load":"LOAD64_F(fa0, fa0f, a3)"}
+%def unopNarrower(load="LOAD64_F(fa0, fa0f, a3)", instr=""):
     /*
      * Generic 64bit-to-32bit floating-point unary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = op fa0".
diff --git a/runtime/interpreter/mterp/mips/unopWide.S b/runtime/interpreter/mterp/mips/unopWide.S
index 135d9facdf8a29e019e4df8ac0f4c35afade5cfa..269a29651f276416befb7cf619ca4a71ff8c8bf5 100644
--- a/runtime/interpreter/mterp/mips/unopWide.S
+++ b/runtime/interpreter/mterp/mips/unopWide.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result0":"a0", "result1":"a1"}
+%def unopWide(preinstr="", result0="a0", result1="a1", instr=""):
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result0/result1 = op a0/a1".
diff --git a/runtime/interpreter/mterp/mips/unopWider.S b/runtime/interpreter/mterp/mips/unopWider.S
index ca888ad3fb8cac5f64d188811a9205ae52af880b..7767d6ee50af8e8b382de6d6454a75f4b1c7c033 100644
--- a/runtime/interpreter/mterp/mips/unopWider.S
+++ b/runtime/interpreter/mterp/mips/unopWider.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result0":"a0", "result1":"a1"}
+%def unopWider(preinstr="", result0="a0", result1="a1", instr=""):
     /*
      * Generic 32bit-to-64bit unary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result0/result1 = op a0".
diff --git a/runtime/interpreter/mterp/mips/unused.S b/runtime/interpreter/mterp/mips/unused.S
index ffa00becfdb2bb4ba58ee7659a0609978599110e..3f37e74bb4752ad0c5af7cc91b0202f5f00429cd 100644
--- a/runtime/interpreter/mterp/mips/unused.S
+++ b/runtime/interpreter/mterp/mips/unused.S
@@ -1,3 +1,4 @@
+%def unused():
 /*
  * Bail to reference interpreter to throw.
  */
diff --git a/runtime/interpreter/mterp/mips/zcmp.S b/runtime/interpreter/mterp/mips/zcmp.S
index 8d3a198891ba1fc0b68f195398268dca4e5c8ff4..eb23eea744c21b8dfc80f2a26e6ab7fb3f4f39f6 100644
--- a/runtime/interpreter/mterp/mips/zcmp.S
+++ b/runtime/interpreter/mterp/mips/zcmp.S
@@ -1,3 +1,4 @@
+%def zcmp(condition=""):
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
diff --git a/runtime/interpreter/mterp/mips64/alt_stub.S b/runtime/interpreter/mterp/mips64/alt_stub.S
index 12fa84d7d2691db36d400869cbdc863d415a8dfc..17558bb4c2b751efd5fce5cb2e971c67fca2d3ff 100644
--- a/runtime/interpreter/mterp/mips64/alt_stub.S
+++ b/runtime/interpreter/mterp/mips64/alt_stub.S
@@ -1,3 +1,4 @@
+%def alt_stub():
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
diff --git a/runtime/interpreter/mterp/mips64/bincmp.S b/runtime/interpreter/mterp/mips64/bincmp.S
index c2bca91ebfaf4c32f19ba6a8a69440b6ffc7f49c..bdf01dc5e3cfc289d71ed50789cd3d79c58c2dcb 100644
--- a/runtime/interpreter/mterp/mips64/bincmp.S
+++ b/runtime/interpreter/mterp/mips64/bincmp.S
@@ -1,3 +1,4 @@
+%def bincmp(condition=""):
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
diff --git a/runtime/interpreter/mterp/mips64/binop.S b/runtime/interpreter/mterp/mips64/binop.S
index fab48b73b3d73e93f6ef4e9ec748adf3fde5c5de..9332fadd5fe493c90ac1d8354235620fd2ddd3c1 100644
--- a/runtime/interpreter/mterp/mips64/binop.S
+++ b/runtime/interpreter/mterp/mips64/binop.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"a0", "chkzero":"0"}
+%def binop(preinstr="", result="a0", chkzero="0", instr=""):
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
diff --git a/runtime/interpreter/mterp/mips64/binop2addr.S b/runtime/interpreter/mterp/mips64/binop2addr.S
index 1ae73f51d45ef2910998a691f096cae627b88374..19f18151eb217f9d0913debc2f9664380d8ef796 100644
--- a/runtime/interpreter/mterp/mips64/binop2addr.S
+++ b/runtime/interpreter/mterp/mips64/binop2addr.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"a0", "chkzero":"0"}
+%def binop2addr(preinstr="", result="a0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
diff --git a/runtime/interpreter/mterp/mips64/binopLit16.S b/runtime/interpreter/mterp/mips64/binopLit16.S
index 925775824cb41eaac65dc757e48a2b48965e7182..7cb2b9760575933552c0429bb04789f40192b312 100644
--- a/runtime/interpreter/mterp/mips64/binopLit16.S
+++ b/runtime/interpreter/mterp/mips64/binopLit16.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"a0", "chkzero":"0"}
+%def binopLit16(preinstr="", result="a0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
diff --git a/runtime/interpreter/mterp/mips64/binopLit8.S b/runtime/interpreter/mterp/mips64/binopLit8.S
index f4a0bba9b919eef9b75f6e5ed9e41501ad8f0094..3c0449f17942fdfb9667d03286b6056c24b6aa50 100644
--- a/runtime/interpreter/mterp/mips64/binopLit8.S
+++ b/runtime/interpreter/mterp/mips64/binopLit8.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"a0", "chkzero":"0"}
+%def binopLit8(preinstr="", result="a0", chkzero="0", instr=""):
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
diff --git a/runtime/interpreter/mterp/mips64/binopWide.S b/runtime/interpreter/mterp/mips64/binopWide.S
index 732f0d60f9da4172d7034daee7f55f56ba8c2b5b..2206b3163030a78baa06b0e93b6366ab365bb88b 100644
--- a/runtime/interpreter/mterp/mips64/binopWide.S
+++ b/runtime/interpreter/mterp/mips64/binopWide.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"a0", "chkzero":"0"}
+%def binopWide(preinstr="", result="a0", chkzero="0", instr=""):
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
diff --git a/runtime/interpreter/mterp/mips64/binopWide2addr.S b/runtime/interpreter/mterp/mips64/binopWide2addr.S
index 45d8d829602aec518809939610e2eba9bf5d9896..8758a806db7175b057ace529c10ad11da94531be 100644
--- a/runtime/interpreter/mterp/mips64/binopWide2addr.S
+++ b/runtime/interpreter/mterp/mips64/binopWide2addr.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "result":"a0", "chkzero":"0"}
+%def binopWide2addr(preinstr="", result="a0", chkzero="0", instr=""):
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
diff --git a/runtime/interpreter/mterp/mips64/const.S b/runtime/interpreter/mterp/mips64/const.S
index 2ec1173a7cc6cae2a1a648359882179e824a08f1..5de2404fc751c8cdbd0cb341eeec184b3b2acded 100644
--- a/runtime/interpreter/mterp/mips64/const.S
+++ b/runtime/interpreter/mterp/mips64/const.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedConstHandler" }
+%def const(helper="UndefinedConstHandler"):
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
diff --git a/runtime/interpreter/mterp/mips64/entry.S b/runtime/interpreter/mterp/mips64/entry.S
index ed965aa2018ddd062c8e40e24c0a9256d46fd7b0..0c64137fa8315f4aca4dea094e4a4db0878e0d8c 100644
--- a/runtime/interpreter/mterp/mips64/entry.S
+++ b/runtime/interpreter/mterp/mips64/entry.S
@@ -1,3 +1,4 @@
+%def entry():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
diff --git a/runtime/interpreter/mterp/mips64/fallback.S b/runtime/interpreter/mterp/mips64/fallback.S
index 560b994b08e568c787b931292a937db1f8ec3ff9..71abfeb23dfa3107b8b47efd322a05a5c8eadff1 100644
--- a/runtime/interpreter/mterp/mips64/fallback.S
+++ b/runtime/interpreter/mterp/mips64/fallback.S
@@ -1,2 +1,3 @@
+%def fallback():
 /* Transfer stub to alternate interpreter */
     b       MterpFallback
diff --git a/runtime/interpreter/mterp/mips64/fbinop.S b/runtime/interpreter/mterp/mips64/fbinop.S
index f19dd1c3d9fefc6e8aa40813b583c48b0b25ca68..5090528201ce8723e9ca54340ddbe241a786ae88 100644
--- a/runtime/interpreter/mterp/mips64/fbinop.S
+++ b/runtime/interpreter/mterp/mips64/fbinop.S
@@ -1,4 +1,4 @@
-%default {}
+%def fbinop(instr=""):
     /*:
      * Generic 32-bit floating-point operation.
      *
diff --git a/runtime/interpreter/mterp/mips64/fbinop2addr.S b/runtime/interpreter/mterp/mips64/fbinop2addr.S
index 2e2cd7e8e9528447d5b578fee3d62c3cc95b1e97..fe5ad2bec4f25f225b38da25629cd51c3a61aba2 100644
--- a/runtime/interpreter/mterp/mips64/fbinop2addr.S
+++ b/runtime/interpreter/mterp/mips64/fbinop2addr.S
@@ -1,4 +1,4 @@
-%default {}
+%def fbinop2addr(instr=""):
     /*:
      * Generic 32-bit "/2addr" floating-point operation.
      *
diff --git a/runtime/interpreter/mterp/mips64/fbinopWide.S b/runtime/interpreter/mterp/mips64/fbinopWide.S
index 8915c9447cf9301f9634c60ed02e8ba4d6d1bbdd..ca7765bb821854bbbe00640f21e3a992a9d7877b 100644
--- a/runtime/interpreter/mterp/mips64/fbinopWide.S
+++ b/runtime/interpreter/mterp/mips64/fbinopWide.S
@@ -1,4 +1,4 @@
-%default {}
+%def fbinopWide(instr=""):
     /*:
      * Generic 64-bit floating-point operation.
      *
diff --git a/runtime/interpreter/mterp/mips64/fbinopWide2addr.S b/runtime/interpreter/mterp/mips64/fbinopWide2addr.S
index a3f4eaa8cca421ca7fb666ae45d41fa7753b9ffc..a4dfd4c7930324c0507061d9d894f7fa1197978b 100644
--- a/runtime/interpreter/mterp/mips64/fbinopWide2addr.S
+++ b/runtime/interpreter/mterp/mips64/fbinopWide2addr.S
@@ -1,4 +1,4 @@
-%default {}
+%def fbinopWide2addr(instr=""):
     /*:
      * Generic 64-bit "/2addr" floating-point operation.
      *
diff --git a/runtime/interpreter/mterp/mips64/fcmp.S b/runtime/interpreter/mterp/mips64/fcmp.S
index 2e1a3e4c3d581d736007046ed83b03ca4d3e4e20..bc40f9627ea46949a72bb691e3449cebe4df9608 100644
--- a/runtime/interpreter/mterp/mips64/fcmp.S
+++ b/runtime/interpreter/mterp/mips64/fcmp.S
@@ -1,4 +1,4 @@
-%default {}
+%def fcmp(gt_bias=""):
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/mips64/fcmpWide.S b/runtime/interpreter/mterp/mips64/fcmpWide.S
index 2a3a341a3d329198ba6066325b35d0196fb811f2..05f33e6afa994748af1a6de14f9715b94a5e5070 100644
--- a/runtime/interpreter/mterp/mips64/fcmpWide.S
+++ b/runtime/interpreter/mterp/mips64/fcmpWide.S
@@ -1,4 +1,4 @@
-%default {}
+%def fcmpWide(gt_bias=""):
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/mips64/fcvtFooter.S b/runtime/interpreter/mterp/mips64/fcvtFooter.S
index 06e9507817b8400d944a56f9166c153d8719aa0c..711f3f3e25bb49e7fbb9029cf0ce6d101afb6010 100644
--- a/runtime/interpreter/mterp/mips64/fcvtFooter.S
+++ b/runtime/interpreter/mterp/mips64/fcvtFooter.S
@@ -1,3 +1,4 @@
+%def fcvtFooter(suffix="", valreg=""):
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
diff --git a/runtime/interpreter/mterp/mips64/fcvtHeader.S b/runtime/interpreter/mterp/mips64/fcvtHeader.S
index 8742e42c393d22c97fefca8c000f4b2c083845f8..688b6be0f7bc640da1c25558455616c67c389a6a 100644
--- a/runtime/interpreter/mterp/mips64/fcvtHeader.S
+++ b/runtime/interpreter/mterp/mips64/fcvtHeader.S
@@ -1,3 +1,4 @@
+%def fcvtHeader(suffix="", valreg=""):
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
diff --git a/runtime/interpreter/mterp/mips64/field.S b/runtime/interpreter/mterp/mips64/field.S
index 1333ed77b7e1ed056329cae96075dc558158ee69..d61b06afd4bd42c6a791a1f76755241740e3e292 100644
--- a/runtime/interpreter/mterp/mips64/field.S
+++ b/runtime/interpreter/mterp/mips64/field.S
@@ -1 +1,2 @@
+%def field(helper=""):
 TODO
diff --git a/runtime/interpreter/mterp/mips64/footer.S b/runtime/interpreter/mterp/mips64/footer.S
index 779b1fb88fa42dd4544778614bf6c89ccdb61ded..5673151f1c20f159a3a95c359757eabd7589f78c 100644
--- a/runtime/interpreter/mterp/mips64/footer.S
+++ b/runtime/interpreter/mterp/mips64/footer.S
@@ -1,3 +1,4 @@
+%def footer():
 /*
  * We've detected a condition that will result in an exception, but the exception
  * has not yet been thrown.  Just bail out to the reference interpreter to deal with it.
diff --git a/runtime/interpreter/mterp/mips64/header.S b/runtime/interpreter/mterp/mips64/header.S
index 7e1446c0c62cc199b4c4161dd8f7202d37b2a0a3..42c712654d1522104b9a62b67f49b50fe08436a5 100644
--- a/runtime/interpreter/mterp/mips64/header.S
+++ b/runtime/interpreter/mterp/mips64/header.S
@@ -1,3 +1,4 @@
+%def header():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
diff --git a/runtime/interpreter/mterp/mips64/instruction_end.S b/runtime/interpreter/mterp/mips64/instruction_end.S
index 32c725c7d9655633fcd95e67023080ff36bdc515..3d4429365a51b236997a9924cef40702e4711f8a 100644
--- a/runtime/interpreter/mterp/mips64/instruction_end.S
+++ b/runtime/interpreter/mterp/mips64/instruction_end.S
@@ -1,3 +1,4 @@
+%def instruction_end():
 
     .global artMterpAsmInstructionEnd
 artMterpAsmInstructionEnd:
diff --git a/runtime/interpreter/mterp/mips64/instruction_end_alt.S b/runtime/interpreter/mterp/mips64/instruction_end_alt.S
index f90916fc02cda411d0a0c9c40c77bb3c6848793c..86a1068f10fea62c2e4d86c7611ba97923262949 100644
--- a/runtime/interpreter/mterp/mips64/instruction_end_alt.S
+++ b/runtime/interpreter/mterp/mips64/instruction_end_alt.S
@@ -1,3 +1,4 @@
+%def instruction_end_alt():
 
     .global artMterpAsmAltInstructionEnd
 artMterpAsmAltInstructionEnd:
diff --git a/runtime/interpreter/mterp/mips64/instruction_end_sister.S b/runtime/interpreter/mterp/mips64/instruction_end_sister.S
index c5f4886697bb135e2a6a8bd74cf2fb7df2e5fab0..8cc4513025aada024f3baeb754a5881917ec0367 100644
--- a/runtime/interpreter/mterp/mips64/instruction_end_sister.S
+++ b/runtime/interpreter/mterp/mips64/instruction_end_sister.S
@@ -1,3 +1,4 @@
+%def instruction_end_sister():
 
     .global artMterpAsmSisterEnd
 artMterpAsmSisterEnd:
diff --git a/runtime/interpreter/mterp/mips64/instruction_start.S b/runtime/interpreter/mterp/mips64/instruction_start.S
index 8874c205404d9f5012a99d67dfd2ef472160d109..4b777f2fd5d44ff7f931b89d5c9e7ce9dee9bffd 100644
--- a/runtime/interpreter/mterp/mips64/instruction_start.S
+++ b/runtime/interpreter/mterp/mips64/instruction_start.S
@@ -1,3 +1,4 @@
+%def instruction_start():
 
     .global artMterpAsmInstructionStart
 artMterpAsmInstructionStart = .L_op_nop
diff --git a/runtime/interpreter/mterp/mips64/instruction_start_alt.S b/runtime/interpreter/mterp/mips64/instruction_start_alt.S
index 0c9ffdb7d6c01b8470682ee5715d27a475517e5b..e7731b75054dc5875240da6add6a8d16c56e8cfe 100644
--- a/runtime/interpreter/mterp/mips64/instruction_start_alt.S
+++ b/runtime/interpreter/mterp/mips64/instruction_start_alt.S
@@ -1,3 +1,4 @@
+%def instruction_start_alt():
 
     .global artMterpAsmAltInstructionStart
 artMterpAsmAltInstructionStart = .L_ALT_op_nop
diff --git a/runtime/interpreter/mterp/mips64/instruction_start_sister.S b/runtime/interpreter/mterp/mips64/instruction_start_sister.S
index 2ec51f7261de40fd2ad0d3ba9ed6826bf532d43e..e09ea90b8e7a911aa8f790d100687a87da50b328 100644
--- a/runtime/interpreter/mterp/mips64/instruction_start_sister.S
+++ b/runtime/interpreter/mterp/mips64/instruction_start_sister.S
@@ -1,3 +1,4 @@
+%def instruction_start_sister():
 
     .global artMterpAsmSisterStart
     .text
diff --git a/runtime/interpreter/mterp/mips64/invoke.S b/runtime/interpreter/mterp/mips64/invoke.S
index be647b618ba946b1c5c3d5189ae584d9d3711859..caf5698f52268f85e45f43518c2195ea69c2c90c 100644
--- a/runtime/interpreter/mterp/mips64/invoke.S
+++ b/runtime/interpreter/mterp/mips64/invoke.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke(helper="UndefinedInvokeHandler"):
     /*
      * Generic invoke handler wrapper.
      */
diff --git a/runtime/interpreter/mterp/mips64/invoke_polymorphic.S b/runtime/interpreter/mterp/mips64/invoke_polymorphic.S
index fa82083276a41f5fec1425426094b2d01b423a81..3a10554b6698f5029864e3b3542d91546b59ec1e 100644
--- a/runtime/interpreter/mterp/mips64/invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/mips64/invoke_polymorphic.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke_polymorphic(helper="UndefinedInvokeHandler"):
     /*
      * invoke-polymorphic handler wrapper.
      */
diff --git a/runtime/interpreter/mterp/mips64/op_add_double.S b/runtime/interpreter/mterp/mips64/op_add_double.S
index 1520e325f7f9a8b791a7b0eebfd45358900d2388..0c1f6a28be7ff5da783356da173b63369c42ffa7 100644
--- a/runtime/interpreter/mterp/mips64/op_add_double.S
+++ b/runtime/interpreter/mterp/mips64/op_add_double.S
@@ -1 +1,2 @@
-%include "mips64/fbinopWide.S" {"instr":"add.d f0, f0, f1"}
+%def op_add_double():
+%  fbinopWide(instr="add.d f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_add_double_2addr.S b/runtime/interpreter/mterp/mips64/op_add_double_2addr.S
index c14382ef20e275e6ba2d90ed06b9d2892596c67a..f66799624325bb36c278fe2e6f7b0241a9e254c4 100644
--- a/runtime/interpreter/mterp/mips64/op_add_double_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_add_double_2addr.S
@@ -1 +1,2 @@
-%include "mips64/fbinopWide2addr.S" {"instr":"add.d f0, f0, f1"}
+%def op_add_double_2addr():
+%  fbinopWide2addr(instr="add.d f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_add_float.S b/runtime/interpreter/mterp/mips64/op_add_float.S
index c6ed558dc3b46e8fd0a5d3b714b08709009d28a8..4c0f88c71a3431eda74b583e359e662255be174e 100644
--- a/runtime/interpreter/mterp/mips64/op_add_float.S
+++ b/runtime/interpreter/mterp/mips64/op_add_float.S
@@ -1 +1,2 @@
-%include "mips64/fbinop.S" {"instr":"add.s f0, f0, f1"}
+%def op_add_float():
+%  fbinop(instr="add.s f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_add_float_2addr.S b/runtime/interpreter/mterp/mips64/op_add_float_2addr.S
index 4c20547b227d7979e9a87cc9b753c32c44234fb5..0bcc91aa270876f391acec876f82d8f05aa4d30e 100644
--- a/runtime/interpreter/mterp/mips64/op_add_float_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_add_float_2addr.S
@@ -1 +1,2 @@
-%include "mips64/fbinop2addr.S" {"instr":"add.s f0, f0, f1"}
+%def op_add_float_2addr():
+%  fbinop2addr(instr="add.s f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_add_int.S b/runtime/interpreter/mterp/mips64/op_add_int.S
index 6e569de71a5d8061cff7e809a7010647146fff63..ed0fc012b8a63f0849d04b5a4169d676d983134d 100644
--- a/runtime/interpreter/mterp/mips64/op_add_int.S
+++ b/runtime/interpreter/mterp/mips64/op_add_int.S
@@ -1 +1,2 @@
-%include "mips64/binop.S" {"instr":"addu a0, a0, a1"}
+%def op_add_int():
+%  binop(instr="addu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_add_int_2addr.S b/runtime/interpreter/mterp/mips64/op_add_int_2addr.S
index 2a84124a3a802371d2f22c7f9b8d14491f1d9e0a..ed0b1314ef973ed789d594293573cc825334cf1c 100644
--- a/runtime/interpreter/mterp/mips64/op_add_int_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_add_int_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binop2addr.S" {"instr":"addu a0, a0, a1"}
+%def op_add_int_2addr():
+%  binop2addr(instr="addu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_add_int_lit16.S b/runtime/interpreter/mterp/mips64/op_add_int_lit16.S
index 94b053bba3b64e2ead7e4e3649e7019f512c2868..126807a303a50bdb24d6180891a9d9eb17ae2b35 100644
--- a/runtime/interpreter/mterp/mips64/op_add_int_lit16.S
+++ b/runtime/interpreter/mterp/mips64/op_add_int_lit16.S
@@ -1 +1,2 @@
-%include "mips64/binopLit16.S" {"instr":"addu a0, a0, a1"}
+%def op_add_int_lit16():
+%  binopLit16(instr="addu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_add_int_lit8.S b/runtime/interpreter/mterp/mips64/op_add_int_lit8.S
index 3b6d734723c1b750b95b2ab0f91556ed37b5f1f4..30184c40f555cbed6243c9c9448e665dcf878b92 100644
--- a/runtime/interpreter/mterp/mips64/op_add_int_lit8.S
+++ b/runtime/interpreter/mterp/mips64/op_add_int_lit8.S
@@ -1 +1,2 @@
-%include "mips64/binopLit8.S" {"instr":"addu a0, a0, a1"}
+%def op_add_int_lit8():
+%  binopLit8(instr="addu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_add_long.S b/runtime/interpreter/mterp/mips64/op_add_long.S
index c8d702f29fdf93ec94c7e37c1988233aa9604abf..72a1f24abbe5031dbec1d826683bd61da838801a 100644
--- a/runtime/interpreter/mterp/mips64/op_add_long.S
+++ b/runtime/interpreter/mterp/mips64/op_add_long.S
@@ -1 +1,2 @@
-%include "mips64/binopWide.S" {"instr":"daddu a0, a0, a1"}
+%def op_add_long():
+%  binopWide(instr="daddu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_add_long_2addr.S b/runtime/interpreter/mterp/mips64/op_add_long_2addr.S
index 928ff545659b06e61fb7503e8ec3af02196352e0..caf29e230d5414f95f4b920355f5a7ec742529ee 100644
--- a/runtime/interpreter/mterp/mips64/op_add_long_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_add_long_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binopWide2addr.S" {"instr":"daddu a0, a0, a1"}
+%def op_add_long_2addr():
+%  binopWide2addr(instr="daddu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_aget.S b/runtime/interpreter/mterp/mips64/op_aget.S
index 0472a0616bcaab47442574a33d2e8e0004472d88..60be23dc7a655d7c13e495e99e94e73a841d1374 100644
--- a/runtime/interpreter/mterp/mips64/op_aget.S
+++ b/runtime/interpreter/mterp/mips64/op_aget.S
@@ -1,4 +1,4 @@
-%default { "load":"lw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
+%def op_aget(load="lw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"):
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/mips64/op_aget_boolean.S b/runtime/interpreter/mterp/mips64/op_aget_boolean.S
index d5be01b7c5b1b7c1d1ca9e8d208d0207e477b7dd..7b28bc8e06f4762a02bd210e370457d5c0a4a6d7 100644
--- a/runtime/interpreter/mterp/mips64/op_aget_boolean.S
+++ b/runtime/interpreter/mterp/mips64/op_aget_boolean.S
@@ -1 +1,2 @@
-%include "mips64/op_aget.S" { "load":"lbu", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aget_boolean():
+%  op_aget(load="lbu", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips64/op_aget_byte.S b/runtime/interpreter/mterp/mips64/op_aget_byte.S
index 084de8d4df54bbce503b5db306d4f588ef6cbe3f..a4a0b7e9b7d7f56dc3545a04621f63bb391db465 100644
--- a/runtime/interpreter/mterp/mips64/op_aget_byte.S
+++ b/runtime/interpreter/mterp/mips64/op_aget_byte.S
@@ -1 +1,2 @@
-%include "mips64/op_aget.S" { "load":"lb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aget_byte():
+%  op_aget(load="lb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips64/op_aget_char.S b/runtime/interpreter/mterp/mips64/op_aget_char.S
index 6c99ed52ade1dfeb21e6b8a48fec150045b4d966..465de097cd1a5f0f358050d97bc7b0336d7e3666 100644
--- a/runtime/interpreter/mterp/mips64/op_aget_char.S
+++ b/runtime/interpreter/mterp/mips64/op_aget_char.S
@@ -1 +1,2 @@
-%include "mips64/op_aget.S" { "load":"lhu", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aget_char():
+%  op_aget(load="lhu", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips64/op_aget_object.S b/runtime/interpreter/mterp/mips64/op_aget_object.S
index 6374a05e7b8b32e9b9e03088a12fc67096768641..48d751b197e905a50244ddf652d4d0c92edc2ef3 100644
--- a/runtime/interpreter/mterp/mips64/op_aget_object.S
+++ b/runtime/interpreter/mterp/mips64/op_aget_object.S
@@ -1,3 +1,4 @@
+%def op_aget_object():
     /*
      * Array object get.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/mips64/op_aget_short.S b/runtime/interpreter/mterp/mips64/op_aget_short.S
index 0158b0a1a171a6d12f96954412deaef183ba5add..4faa9ad358295031e8c4aadcd23b188cf60c247a 100644
--- a/runtime/interpreter/mterp/mips64/op_aget_short.S
+++ b/runtime/interpreter/mterp/mips64/op_aget_short.S
@@ -1 +1,2 @@
-%include "mips64/op_aget.S" { "load":"lh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aget_short():
+%  op_aget(load="lh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips64/op_aget_wide.S b/runtime/interpreter/mterp/mips64/op_aget_wide.S
index 0945acae5a6d87b8c98f8cadd9bb984736da2fb8..99b0de9b64f218b17f18602a2f3c622d52d0bd3c 100644
--- a/runtime/interpreter/mterp/mips64/op_aget_wide.S
+++ b/runtime/interpreter/mterp/mips64/op_aget_wide.S
@@ -1,3 +1,4 @@
+%def op_aget_wide():
     /*
      * Array get, 64 bits.  vAA <- vBB[vCC].
      *
diff --git a/runtime/interpreter/mterp/mips64/op_and_int.S b/runtime/interpreter/mterp/mips64/op_and_int.S
index f0792a8351653a2629a7b5dfc7e9df03db1b845b..740411ddf7ed8458a14bd85293bec4efa2b69d13 100644
--- a/runtime/interpreter/mterp/mips64/op_and_int.S
+++ b/runtime/interpreter/mterp/mips64/op_and_int.S
@@ -1 +1,2 @@
-%include "mips64/binop.S" {"instr":"and a0, a0, a1"}
+%def op_and_int():
+%  binop(instr="and a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_and_int_2addr.S b/runtime/interpreter/mterp/mips64/op_and_int_2addr.S
index 08dc615518989987eed96af039f6ed721df4ccb3..8224e5f18aa55c509f48b4dfcf3e3dcf4a361544 100644
--- a/runtime/interpreter/mterp/mips64/op_and_int_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_and_int_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binop2addr.S" {"instr":"and a0, a0, a1"}
+%def op_and_int_2addr():
+%  binop2addr(instr="and a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_and_int_lit16.S b/runtime/interpreter/mterp/mips64/op_and_int_lit16.S
index 65d28ad20cf6703dbb34c5de13f7645c19f6d97c..5031f500ce6261fd23559da21709b2296891a053 100644
--- a/runtime/interpreter/mterp/mips64/op_and_int_lit16.S
+++ b/runtime/interpreter/mterp/mips64/op_and_int_lit16.S
@@ -1 +1,2 @@
-%include "mips64/binopLit16.S" {"instr":"and a0, a0, a1"}
+%def op_and_int_lit16():
+%  binopLit16(instr="and a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_and_int_lit8.S b/runtime/interpreter/mterp/mips64/op_and_int_lit8.S
index ab84bb7ce25d121ffb8d40e142c5ddaf3b938ca4..7a7b8b5d5a7ff51cc86235e13b88a12e53f95e17 100644
--- a/runtime/interpreter/mterp/mips64/op_and_int_lit8.S
+++ b/runtime/interpreter/mterp/mips64/op_and_int_lit8.S
@@ -1 +1,2 @@
-%include "mips64/binopLit8.S" {"instr":"and a0, a0, a1"}
+%def op_and_int_lit8():
+%  binopLit8(instr="and a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_and_long.S b/runtime/interpreter/mterp/mips64/op_and_long.S
index e383ba00caab2778453f603d9cd3bd0f03b575ba..242ddf2e2ca0ffd860932de16dd4c030ffa11a99 100644
--- a/runtime/interpreter/mterp/mips64/op_and_long.S
+++ b/runtime/interpreter/mterp/mips64/op_and_long.S
@@ -1 +1,2 @@
-%include "mips64/binopWide.S" {"instr":"and a0, a0, a1"}
+%def op_and_long():
+%  binopWide(instr="and a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_and_long_2addr.S b/runtime/interpreter/mterp/mips64/op_and_long_2addr.S
index f863bb9275d0e7f293ff49c52465c28b16f77150..64b5a7e65ed51eaff56bf6180c2357362c943ed6 100644
--- a/runtime/interpreter/mterp/mips64/op_and_long_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_and_long_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binopWide2addr.S" {"instr":"and a0, a0, a1"}
+%def op_and_long_2addr():
+%  binopWide2addr(instr="and a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_aput.S b/runtime/interpreter/mterp/mips64/op_aput.S
index 9bfda97d05967530fcdfa7d2129685852375e23c..f4c04d01d06d3aaeeace4f0cf54bce1fec2aea16 100644
--- a/runtime/interpreter/mterp/mips64/op_aput.S
+++ b/runtime/interpreter/mterp/mips64/op_aput.S
@@ -1,4 +1,4 @@
-%default { "store":"sw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
+%def op_aput(store="sw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"):
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_aput_boolean.S b/runtime/interpreter/mterp/mips64/op_aput_boolean.S
index 6707a1f11da9c8c0e57755723ef63d1a8abc10eb..098bbcd1c4ce02d819be6404530115ee65ea6817 100644
--- a/runtime/interpreter/mterp/mips64/op_aput_boolean.S
+++ b/runtime/interpreter/mterp/mips64/op_aput_boolean.S
@@ -1 +1,2 @@
-%include "mips64/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aput_boolean():
+%  op_aput(store="sb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips64/op_aput_byte.S b/runtime/interpreter/mterp/mips64/op_aput_byte.S
index 7b9ce483799fb5d7268eb9bda5046b425c6da279..f4b42ee6e85f8b1a94cf7fa26355fe90e44e5393 100644
--- a/runtime/interpreter/mterp/mips64/op_aput_byte.S
+++ b/runtime/interpreter/mterp/mips64/op_aput_byte.S
@@ -1 +1,2 @@
-%include "mips64/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aput_byte():
+%  op_aput(store="sb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips64/op_aput_char.S b/runtime/interpreter/mterp/mips64/op_aput_char.S
index 82bc8f7818504603ad356b9f4ed2b6238562ab01..18eedae68dab57b018fc95db0971d39dee86ebb0 100644
--- a/runtime/interpreter/mterp/mips64/op_aput_char.S
+++ b/runtime/interpreter/mterp/mips64/op_aput_char.S
@@ -1 +1,2 @@
-%include "mips64/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aput_char():
+%  op_aput(store="sh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips64/op_aput_object.S b/runtime/interpreter/mterp/mips64/op_aput_object.S
index b132456a182fc183324e4d605a2ab83e7fe3609a..6b23e90e41085c39db032f36bec759a542acdc20 100644
--- a/runtime/interpreter/mterp/mips64/op_aput_object.S
+++ b/runtime/interpreter/mterp/mips64/op_aput_object.S
@@ -1,3 +1,4 @@
+%def op_aput_object():
     /*
      * Store an object into an array.  vBB[vCC] <- vAA.
      */
diff --git a/runtime/interpreter/mterp/mips64/op_aput_short.S b/runtime/interpreter/mterp/mips64/op_aput_short.S
index a7af2945b1ac21866e8d913904b95737979734be..61a3c0d6ea59e023aaea7aa81e974e76db5969aa 100644
--- a/runtime/interpreter/mterp/mips64/op_aput_short.S
+++ b/runtime/interpreter/mterp/mips64/op_aput_short.S
@@ -1 +1,2 @@
-%include "mips64/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aput_short():
+%  op_aput(store="sh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/mips64/op_aput_wide.S b/runtime/interpreter/mterp/mips64/op_aput_wide.S
index a1d7a3b51ea333857defaa2caedf983546d28b18..4fad5c462c4d6687311af268c6d1d0a3ba70d5ce 100644
--- a/runtime/interpreter/mterp/mips64/op_aput_wide.S
+++ b/runtime/interpreter/mterp/mips64/op_aput_wide.S
@@ -1,3 +1,4 @@
+%def op_aput_wide():
     /*
      * Array put, 64 bits.  vBB[vCC] <- vAA.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_array_length.S b/runtime/interpreter/mterp/mips64/op_array_length.S
index 2d9e172d1863f8eb38d1be287b71531007fdcdcf..13b9a13b9c007e19856759abed3fda873dc53d8c 100644
--- a/runtime/interpreter/mterp/mips64/op_array_length.S
+++ b/runtime/interpreter/mterp/mips64/op_array_length.S
@@ -1,3 +1,4 @@
+%def op_array_length():
     /*
      * Return the length of an array.
      */
diff --git a/runtime/interpreter/mterp/mips64/op_check_cast.S b/runtime/interpreter/mterp/mips64/op_check_cast.S
index 472595d8242f9f6948ee87c43c188174650546b0..b5f0f1fb27fc0dd796bde7522c7d565a759ddeda 100644
--- a/runtime/interpreter/mterp/mips64/op_check_cast.S
+++ b/runtime/interpreter/mterp/mips64/op_check_cast.S
@@ -1,3 +1,4 @@
+%def op_check_cast():
     /*
      * Check to see if a cast from one class to another is allowed.
      */
diff --git a/runtime/interpreter/mterp/mips64/op_cmp_long.S b/runtime/interpreter/mterp/mips64/op_cmp_long.S
index 6e9376cfabe84b4fde6a29d2bb5592094b283252..87eba4421ca4fd1d7cd2bdbdf5ab760050672876 100644
--- a/runtime/interpreter/mterp/mips64/op_cmp_long.S
+++ b/runtime/interpreter/mterp/mips64/op_cmp_long.S
@@ -1,3 +1,4 @@
+%def op_cmp_long():
     /* cmp-long vAA, vBB, vCC */
     lbu     a2, 2(rPC)                  # a2 <- BB
     lbu     a3, 3(rPC)                  # a3 <- CC
diff --git a/runtime/interpreter/mterp/mips64/op_cmpg_double.S b/runtime/interpreter/mterp/mips64/op_cmpg_double.S
index a8e2ef9867cdb3f8cd95454a52f9d7089246e343..4c3117b7e7387a1abbc46131521793a40ff3a4d4 100644
--- a/runtime/interpreter/mterp/mips64/op_cmpg_double.S
+++ b/runtime/interpreter/mterp/mips64/op_cmpg_double.S
@@ -1 +1,2 @@
-%include "mips64/fcmpWide.S" {"gt_bias":"1"}
+%def op_cmpg_double():
+%  fcmpWide(gt_bias="1")
diff --git a/runtime/interpreter/mterp/mips64/op_cmpg_float.S b/runtime/interpreter/mterp/mips64/op_cmpg_float.S
index 0c93eac7de11abe92dc221443e9f4bedf99d95b0..99c4530f829a40d00be7ec9d244be6ea52f2836e 100644
--- a/runtime/interpreter/mterp/mips64/op_cmpg_float.S
+++ b/runtime/interpreter/mterp/mips64/op_cmpg_float.S
@@ -1 +1,2 @@
-%include "mips64/fcmp.S" {"gt_bias":"1"}
+%def op_cmpg_float():
+%  fcmp(gt_bias="1")
diff --git a/runtime/interpreter/mterp/mips64/op_cmpl_double.S b/runtime/interpreter/mterp/mips64/op_cmpl_double.S
index 9111b067f63e8b98b34ff7d6896592672d76cd0e..4900bddffcebde95a30ae04ebe2036ac2556bd47 100644
--- a/runtime/interpreter/mterp/mips64/op_cmpl_double.S
+++ b/runtime/interpreter/mterp/mips64/op_cmpl_double.S
@@ -1 +1,2 @@
-%include "mips64/fcmpWide.S" {"gt_bias":"0"}
+%def op_cmpl_double():
+%  fcmpWide(gt_bias="0")
diff --git a/runtime/interpreter/mterp/mips64/op_cmpl_float.S b/runtime/interpreter/mterp/mips64/op_cmpl_float.S
index b047451842536f1ed97227e366ac12058bd0eaac..159c66dc0655f30639171ac086d43bf782f43823 100644
--- a/runtime/interpreter/mterp/mips64/op_cmpl_float.S
+++ b/runtime/interpreter/mterp/mips64/op_cmpl_float.S
@@ -1 +1,2 @@
-%include "mips64/fcmp.S" {"gt_bias":"0"}
+%def op_cmpl_float():
+%  fcmp(gt_bias="0")
diff --git a/runtime/interpreter/mterp/mips64/op_const.S b/runtime/interpreter/mterp/mips64/op_const.S
index 4b0d69b763ba4ce8249d3da814cddc1f5f4c4ed3..619304264f124890229faa94fa40abcd7e0d4c60 100644
--- a/runtime/interpreter/mterp/mips64/op_const.S
+++ b/runtime/interpreter/mterp/mips64/op_const.S
@@ -1,3 +1,4 @@
+%def op_const():
     /* const vAA, #+BBBBbbbb */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- bbbb (low)
diff --git a/runtime/interpreter/mterp/mips64/op_const_16.S b/runtime/interpreter/mterp/mips64/op_const_16.S
index 51e68a7df77d7f58be781af3e144abf79373a6dc..aac542d84760e6b04962a34968835c5ff3699924 100644
--- a/runtime/interpreter/mterp/mips64/op_const_16.S
+++ b/runtime/interpreter/mterp/mips64/op_const_16.S
@@ -1,3 +1,4 @@
+%def op_const_16():
     /* const/16 vAA, #+BBBB */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- sign-extended BBBB
diff --git a/runtime/interpreter/mterp/mips64/op_const_4.S b/runtime/interpreter/mterp/mips64/op_const_4.S
index 0a58bff7b7d65ac3866cc6e3ea5c8f93360f7509..d26f4e56b1a3c608b9b9d44af927f340bda07811 100644
--- a/runtime/interpreter/mterp/mips64/op_const_4.S
+++ b/runtime/interpreter/mterp/mips64/op_const_4.S
@@ -1,3 +1,4 @@
+%def op_const_4():
     /* const/4 vA, #+B */
     ext     a2, rINST, 8, 4             # a2 <- A
     seh     a0, rINST                   # sign extend B in rINST
diff --git a/runtime/interpreter/mterp/mips64/op_const_class.S b/runtime/interpreter/mterp/mips64/op_const_class.S
index 3f0c716d5ec344a925552129350a51aa39d0c1cd..db12ec31414690de6acb180ce962f6676f3ab2f5 100644
--- a/runtime/interpreter/mterp/mips64/op_const_class.S
+++ b/runtime/interpreter/mterp/mips64/op_const_class.S
@@ -1 +1,2 @@
-%include "mips64/const.S" { "helper":"MterpConstClass" }
+%def op_const_class():
+%  const(helper="MterpConstClass")
diff --git a/runtime/interpreter/mterp/mips64/op_const_high16.S b/runtime/interpreter/mterp/mips64/op_const_high16.S
index 43effb6f60a2f9b074f022330144e120fc104d7a..bf14ab690716b741f39b8ee4d1f807aec7665f1c 100644
--- a/runtime/interpreter/mterp/mips64/op_const_high16.S
+++ b/runtime/interpreter/mterp/mips64/op_const_high16.S
@@ -1,3 +1,4 @@
+%def op_const_high16():
     /* const/high16 vAA, #+BBBB0000 */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- BBBB
diff --git a/runtime/interpreter/mterp/mips64/op_const_method_handle.S b/runtime/interpreter/mterp/mips64/op_const_method_handle.S
index 43584d179c03a8e7815dc08aa428ea45601deb26..2680c17aad5d6f537298bc455177da35df137274 100644
--- a/runtime/interpreter/mterp/mips64/op_const_method_handle.S
+++ b/runtime/interpreter/mterp/mips64/op_const_method_handle.S
@@ -1 +1,2 @@
-%include "mips64/const.S" { "helper":"MterpConstMethodHandle" }
+%def op_const_method_handle():
+%  const(helper="MterpConstMethodHandle")
diff --git a/runtime/interpreter/mterp/mips64/op_const_method_type.S b/runtime/interpreter/mterp/mips64/op_const_method_type.S
index 553b28424a70fd7152f1c1c281ceac1d0a827b88..ea814bf64826079ab9f55e43e47f42180c3ad420 100644
--- a/runtime/interpreter/mterp/mips64/op_const_method_type.S
+++ b/runtime/interpreter/mterp/mips64/op_const_method_type.S
@@ -1 +1,2 @@
-%include "mips64/const.S" { "helper":"MterpConstMethodType" }
+%def op_const_method_type():
+%  const(helper="MterpConstMethodType")
diff --git a/runtime/interpreter/mterp/mips64/op_const_string.S b/runtime/interpreter/mterp/mips64/op_const_string.S
index 96cbb5a23ae706bb78a79d9a4dc13fb53f5e0376..41376f870340354594a5a218b1d2379e08042008 100644
--- a/runtime/interpreter/mterp/mips64/op_const_string.S
+++ b/runtime/interpreter/mterp/mips64/op_const_string.S
@@ -1 +1,2 @@
-%include "mips64/const.S" { "helper":"MterpConstString" }
+%def op_const_string():
+%  const(helper="MterpConstString")
diff --git a/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S b/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S
index 47f2101c881e128157a58bba36ff3ab597baf6f5..25ec0e2b8d00153211cb5004c361cb73d73bf79c 100644
--- a/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S
+++ b/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S
@@ -1,3 +1,4 @@
+%def op_const_string_jumbo():
     /* const/string vAA, String//BBBBBBBB */
     .extern MterpConstString
     EXPORT_PC
diff --git a/runtime/interpreter/mterp/mips64/op_const_wide.S b/runtime/interpreter/mterp/mips64/op_const_wide.S
index f7eaf7c23110fe5ed61328807b77c59dbcddf6df..7c4a99acac34f70e9ae9382d9f9ea8cb46e67fef 100644
--- a/runtime/interpreter/mterp/mips64/op_const_wide.S
+++ b/runtime/interpreter/mterp/mips64/op_const_wide.S
@@ -1,3 +1,4 @@
+%def op_const_wide():
     /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
     srl     a4, rINST, 8                # a4 <- AA
     lh      a0, 2(rPC)                  # a0 <- bbbb (low)
diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_16.S b/runtime/interpreter/mterp/mips64/op_const_wide_16.S
index 3a70937973202d341c05b304b276c41eab5b154d..65f30682a7565cd79c23824a90f6fdcf258b3e55 100644
--- a/runtime/interpreter/mterp/mips64/op_const_wide_16.S
+++ b/runtime/interpreter/mterp/mips64/op_const_wide_16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_16():
     /* const-wide/16 vAA, #+BBBB */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- sign-extended BBBB
diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_32.S b/runtime/interpreter/mterp/mips64/op_const_wide_32.S
index 867197ce139f90c0122ec8690763a7b055581c35..39fa0f9c0205394876640cd38537405a42caeecd 100644
--- a/runtime/interpreter/mterp/mips64/op_const_wide_32.S
+++ b/runtime/interpreter/mterp/mips64/op_const_wide_32.S
@@ -1,3 +1,4 @@
+%def op_const_wide_32():
     /* const-wide/32 vAA, #+BBBBbbbb */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- bbbb (low)
diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_high16.S b/runtime/interpreter/mterp/mips64/op_const_wide_high16.S
index d741631bcbfc4025079a725ec3dd11edb2c9df82..7c538c135da10ac03a57bc6efb6b0493666cb7c3 100644
--- a/runtime/interpreter/mterp/mips64/op_const_wide_high16.S
+++ b/runtime/interpreter/mterp/mips64/op_const_wide_high16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_high16():
     /* const-wide/high16 vAA, #+BBBB000000000000 */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- BBBB
diff --git a/runtime/interpreter/mterp/mips64/op_div_double.S b/runtime/interpreter/mterp/mips64/op_div_double.S
index 44998f0c29838742f1e1e74f25bfc67592c8e4ee..c134dfb7388daefc94b17f93d86901b2bed67404 100644
--- a/runtime/interpreter/mterp/mips64/op_div_double.S
+++ b/runtime/interpreter/mterp/mips64/op_div_double.S
@@ -1 +1,2 @@
-%include "mips64/fbinopWide.S" {"instr":"div.d f0, f0, f1"}
+%def op_div_double():
+%  fbinopWide(instr="div.d f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_div_double_2addr.S b/runtime/interpreter/mterp/mips64/op_div_double_2addr.S
index 396af798f6c2d849860804a0a71684a74059f118..6ac1d757dc3d92f4d9077f219f624da01975a8dc 100644
--- a/runtime/interpreter/mterp/mips64/op_div_double_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_div_double_2addr.S
@@ -1 +1,2 @@
-%include "mips64/fbinopWide2addr.S" {"instr":"div.d f0, f0, f1"}
+%def op_div_double_2addr():
+%  fbinopWide2addr(instr="div.d f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_div_float.S b/runtime/interpreter/mterp/mips64/op_div_float.S
index 7b09d52f02e8832d2bc864e14713f0b422e3f592..97530321b7bd1946c547bb8ae903bfdbb3022421 100644
--- a/runtime/interpreter/mterp/mips64/op_div_float.S
+++ b/runtime/interpreter/mterp/mips64/op_div_float.S
@@ -1 +1,2 @@
-%include "mips64/fbinop.S" {"instr":"div.s f0, f0, f1"}
+%def op_div_float():
+%  fbinop(instr="div.s f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_div_float_2addr.S b/runtime/interpreter/mterp/mips64/op_div_float_2addr.S
index e74fddae6dc56678da44dc5debadf11ef386ddf4..53421ce295199fca2084cd40efa954d65907e7b4 100644
--- a/runtime/interpreter/mterp/mips64/op_div_float_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_div_float_2addr.S
@@ -1 +1,2 @@
-%include "mips64/fbinop2addr.S" {"instr":"div.s f0, f0, f1"}
+%def op_div_float_2addr():
+%  fbinop2addr(instr="div.s f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_div_int.S b/runtime/interpreter/mterp/mips64/op_div_int.S
index fb04acbff8a86ffb25f0304634e2f70a99aafdd1..da9bfcbdb0eab885f7555f24a4fd146e56b70b6b 100644
--- a/runtime/interpreter/mterp/mips64/op_div_int.S
+++ b/runtime/interpreter/mterp/mips64/op_div_int.S
@@ -1 +1,2 @@
-%include "mips64/binop.S" {"instr":"div a0, a0, a1", "chkzero":"1"}
+%def op_div_int():
+%  binop(instr="div a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_div_int_2addr.S b/runtime/interpreter/mterp/mips64/op_div_int_2addr.S
index db29b844fb23b4e412fffab95aaa9643b5990a52..7c9444277e27ac09b1e14297b38ba5ad46c1ccfc 100644
--- a/runtime/interpreter/mterp/mips64/op_div_int_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_div_int_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binop2addr.S" {"instr":"div a0, a0, a1", "chkzero":"1"}
+%def op_div_int_2addr():
+%  binop2addr(instr="div a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_div_int_lit16.S b/runtime/interpreter/mterp/mips64/op_div_int_lit16.S
index e903ddee2c726874ad46bf6ab2546b9271d80983..4afe80e07d1fc0f2ed80a0ecc220dd59f8b97c81 100644
--- a/runtime/interpreter/mterp/mips64/op_div_int_lit16.S
+++ b/runtime/interpreter/mterp/mips64/op_div_int_lit16.S
@@ -1 +1,2 @@
-%include "mips64/binopLit16.S" {"instr":"div a0, a0, a1", "chkzero":"1"}
+%def op_div_int_lit16():
+%  binopLit16(instr="div a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_div_int_lit8.S b/runtime/interpreter/mterp/mips64/op_div_int_lit8.S
index 055960546fdb1bc71845a045d7b9069d55ae61d5..7e2df1b312992f80618ae20ff53e6665ccc20a99 100644
--- a/runtime/interpreter/mterp/mips64/op_div_int_lit8.S
+++ b/runtime/interpreter/mterp/mips64/op_div_int_lit8.S
@@ -1 +1,2 @@
-%include "mips64/binopLit8.S" {"instr":"div a0, a0, a1", "chkzero":"1"}
+%def op_div_int_lit8():
+%  binopLit8(instr="div a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_div_long.S b/runtime/interpreter/mterp/mips64/op_div_long.S
index 01fc2b281a50e2a9140afaa9caba469fc0a0625a..93c21874baa4123616064edf67398b5626642a3e 100644
--- a/runtime/interpreter/mterp/mips64/op_div_long.S
+++ b/runtime/interpreter/mterp/mips64/op_div_long.S
@@ -1 +1,2 @@
-%include "mips64/binopWide.S" {"instr":"ddiv a0, a0, a1", "chkzero":"1"}
+%def op_div_long():
+%  binopWide(instr="ddiv a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_div_long_2addr.S b/runtime/interpreter/mterp/mips64/op_div_long_2addr.S
index 9627ab8a2487a9b5e8a3d4a4a8e9c9ee5a6dfa2e..74ecb201547ed66578275131a3bbd0ff73a93304 100644
--- a/runtime/interpreter/mterp/mips64/op_div_long_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_div_long_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binopWide2addr.S" {"instr":"ddiv a0, a0, a1", "chkzero":"1"}
+%def op_div_long_2addr():
+%  binopWide2addr(instr="ddiv a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_double_to_float.S b/runtime/interpreter/mterp/mips64/op_double_to_float.S
index 2b2acee59147f8b8c6eb8482ebfa90dce3bf272f..f19b47fcaecabaa049c90bef76ed0377fc2073b0 100644
--- a/runtime/interpreter/mterp/mips64/op_double_to_float.S
+++ b/runtime/interpreter/mterp/mips64/op_double_to_float.S
@@ -1,8 +1,9 @@
+%def op_double_to_float():
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%  fcvtHeader(suffix="_DOUBLE", valreg="f0")
     cvt.s.d f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%  fcvtFooter(suffix="_FLOAT", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_double_to_int.S b/runtime/interpreter/mterp/mips64/op_double_to_int.S
index d09952233cbe1e4582904417231bea4d0021b1ab..ba370a26bbc6bd41542dc76a3aa5ed53faa03c55 100644
--- a/runtime/interpreter/mterp/mips64/op_double_to_int.S
+++ b/runtime/interpreter/mterp/mips64/op_double_to_int.S
@@ -1,3 +1,4 @@
-%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%def op_double_to_int():
+%  fcvtHeader(suffix="_DOUBLE", valreg="f0")
     trunc.w.d f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%  fcvtFooter(suffix="_FLOAT", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_double_to_long.S b/runtime/interpreter/mterp/mips64/op_double_to_long.S
index 9b65da56020ce3a3f93ffcd7e74212fff7800789..1050a725ab6d2fd11e03f83b658b8f1b078dbf98 100644
--- a/runtime/interpreter/mterp/mips64/op_double_to_long.S
+++ b/runtime/interpreter/mterp/mips64/op_double_to_long.S
@@ -1,3 +1,4 @@
-%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%def op_double_to_long():
+%  fcvtHeader(suffix="_DOUBLE", valreg="f0")
     trunc.l.d f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%  fcvtFooter(suffix="_DOUBLE", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_fill_array_data.S b/runtime/interpreter/mterp/mips64/op_fill_array_data.S
index c90f0b90ada33d3e6c269c8e1db221542d7570d9..5ccff911c9277b389e06c1e0208c848988e67375 100644
--- a/runtime/interpreter/mterp/mips64/op_fill_array_data.S
+++ b/runtime/interpreter/mterp/mips64/op_fill_array_data.S
@@ -1,3 +1,4 @@
+%def op_fill_array_data():
     /* fill-array-data vAA, +BBBBBBBB */
     .extern MterpFillArrayData
     EXPORT_PC
diff --git a/runtime/interpreter/mterp/mips64/op_filled_new_array.S b/runtime/interpreter/mterp/mips64/op_filled_new_array.S
index 35f55c27a6d6a02b72aacac56e2c22d7c345122b..d86ce16cce55b5d65d80fef0da5d3c3acf6c13c2 100644
--- a/runtime/interpreter/mterp/mips64/op_filled_new_array.S
+++ b/runtime/interpreter/mterp/mips64/op_filled_new_array.S
@@ -1,4 +1,4 @@
-%default { "helper":"MterpFilledNewArray" }
+%def op_filled_new_array(helper="MterpFilledNewArray"):
     /*
      * Create a new array with elements filled from registers.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S b/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S
index a4e18f68d6d70fe8c9d71fb45865144a6f7eef73..1667de149ace0bdaaafcd36c43724422682df424 100644
--- a/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S
+++ b/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S
@@ -1 +1,2 @@
-%include "mips64/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" }
+%def op_filled_new_array_range():
+%  op_filled_new_array(helper="MterpFilledNewArrayRange")
diff --git a/runtime/interpreter/mterp/mips64/op_float_to_double.S b/runtime/interpreter/mterp/mips64/op_float_to_double.S
index 6accfeeff6e8d76900f271f641f5afd04d523f50..feebdd8b1d68a055cb5d80cb8a8b27ec18d436c3 100644
--- a/runtime/interpreter/mterp/mips64/op_float_to_double.S
+++ b/runtime/interpreter/mterp/mips64/op_float_to_double.S
@@ -1,8 +1,9 @@
+%def op_float_to_double():
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%  fcvtHeader(suffix="_FLOAT", valreg="f0")
     cvt.d.s f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%  fcvtFooter(suffix="_DOUBLE", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_float_to_int.S b/runtime/interpreter/mterp/mips64/op_float_to_int.S
index 28069739354ed53a55aa070b6c840ab28ef7e7ac..cbfe85339c787050dae43152c6a22091947365b2 100644
--- a/runtime/interpreter/mterp/mips64/op_float_to_int.S
+++ b/runtime/interpreter/mterp/mips64/op_float_to_int.S
@@ -1,3 +1,4 @@
-%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%def op_float_to_int():
+%  fcvtHeader(suffix="_FLOAT", valreg="f0")
     trunc.w.s f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%  fcvtFooter(suffix="_FLOAT", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_float_to_long.S b/runtime/interpreter/mterp/mips64/op_float_to_long.S
index c40c8a6680e63ac82fd81cdc1c50ebc95ba334ab..ccf23b1006c6c59a518c53ee6be4d684387a8523 100644
--- a/runtime/interpreter/mterp/mips64/op_float_to_long.S
+++ b/runtime/interpreter/mterp/mips64/op_float_to_long.S
@@ -1,3 +1,4 @@
-%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%def op_float_to_long():
+%  fcvtHeader(suffix="_FLOAT", valreg="f0")
     trunc.l.s f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%  fcvtFooter(suffix="_DOUBLE", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_goto.S b/runtime/interpreter/mterp/mips64/op_goto.S
index 68fc83d0caf00a1f51f2c65bcc49bc247f6eb457..371bae7d1cce85ec27998b384c03cad1f94ffdcd 100644
--- a/runtime/interpreter/mterp/mips64/op_goto.S
+++ b/runtime/interpreter/mterp/mips64/op_goto.S
@@ -1,3 +1,4 @@
+%def op_goto():
     /*
      * Unconditional branch, 8-bit offset.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_goto_16.S b/runtime/interpreter/mterp/mips64/op_goto_16.S
index ae560663522183cf3f2d471d1da6e7eb5c333554..3b0b52a0ceb244f4c115c58f1061cbdfff93fa07 100644
--- a/runtime/interpreter/mterp/mips64/op_goto_16.S
+++ b/runtime/interpreter/mterp/mips64/op_goto_16.S
@@ -1,3 +1,4 @@
+%def op_goto_16():
     /*
      * Unconditional branch, 16-bit offset.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_goto_32.S b/runtime/interpreter/mterp/mips64/op_goto_32.S
index 498b6d60ae7270990a4fc3e9a0893af660cf46bd..d48f0a04d5f71b7c5eeb737f78a33ea5fa57fe95 100644
--- a/runtime/interpreter/mterp/mips64/op_goto_32.S
+++ b/runtime/interpreter/mterp/mips64/op_goto_32.S
@@ -1,3 +1,4 @@
+%def op_goto_32():
     /*
      * Unconditional branch, 32-bit offset.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_if_eq.S b/runtime/interpreter/mterp/mips64/op_if_eq.S
index aa35cadf17dbd00f1a0ff8862e345788ad0f0893..da58674fd4f81861aefae860c94e933f33d6cb26 100644
--- a/runtime/interpreter/mterp/mips64/op_if_eq.S
+++ b/runtime/interpreter/mterp/mips64/op_if_eq.S
@@ -1 +1,2 @@
-%include "mips64/bincmp.S" { "condition":"eq" }
+%def op_if_eq():
+%  bincmp(condition="eq")
diff --git a/runtime/interpreter/mterp/mips64/op_if_eqz.S b/runtime/interpreter/mterp/mips64/op_if_eqz.S
index 0fe34187a0fb51c86c06b3436b7d36c47ecd7a09..0639664d474160ca776be5174315d4e6c5a89f75 100644
--- a/runtime/interpreter/mterp/mips64/op_if_eqz.S
+++ b/runtime/interpreter/mterp/mips64/op_if_eqz.S
@@ -1 +1,2 @@
-%include "mips64/zcmp.S" { "condition":"eq" }
+%def op_if_eqz():
+%  zcmp(condition="eq")
diff --git a/runtime/interpreter/mterp/mips64/op_if_ge.S b/runtime/interpreter/mterp/mips64/op_if_ge.S
index 59fdcc5b3394f9ed51ddae2ef9d8e44fc4d0b153..5b6ed2f9944653fb88329ebabee2b2799299ce5d 100644
--- a/runtime/interpreter/mterp/mips64/op_if_ge.S
+++ b/runtime/interpreter/mterp/mips64/op_if_ge.S
@@ -1 +1,2 @@
-%include "mips64/bincmp.S" { "condition":"ge" }
+%def op_if_ge():
+%  bincmp(condition="ge")
diff --git a/runtime/interpreter/mterp/mips64/op_if_gez.S b/runtime/interpreter/mterp/mips64/op_if_gez.S
index 57f1f66ecdfaebe3f00fd54d4d3e3b340586566e..ea6cda71fb81ab4dd62e1283b3dcdfeb44afefc4 100644
--- a/runtime/interpreter/mterp/mips64/op_if_gez.S
+++ b/runtime/interpreter/mterp/mips64/op_if_gez.S
@@ -1 +1,2 @@
-%include "mips64/zcmp.S" { "condition":"ge" }
+%def op_if_gez():
+%  zcmp(condition="ge")
diff --git a/runtime/interpreter/mterp/mips64/op_if_gt.S b/runtime/interpreter/mterp/mips64/op_if_gt.S
index 26cc1195b5b35b721517e31ef5ad2ca27e9d0bfc..201decff1a91a48790fa913ac1d3efddfe919764 100644
--- a/runtime/interpreter/mterp/mips64/op_if_gt.S
+++ b/runtime/interpreter/mterp/mips64/op_if_gt.S
@@ -1 +1,2 @@
-%include "mips64/bincmp.S" { "condition":"gt" }
+%def op_if_gt():
+%  bincmp(condition="gt")
diff --git a/runtime/interpreter/mterp/mips64/op_if_gtz.S b/runtime/interpreter/mterp/mips64/op_if_gtz.S
index 69fcacb82dc07cebfb054b71f87a73e7f4e711f4..1fdbb6e8d2aeb22a7b97cde39b7604db087f79d6 100644
--- a/runtime/interpreter/mterp/mips64/op_if_gtz.S
+++ b/runtime/interpreter/mterp/mips64/op_if_gtz.S
@@ -1 +1,2 @@
-%include "mips64/zcmp.S" { "condition":"gt" }
+%def op_if_gtz():
+%  zcmp(condition="gt")
diff --git a/runtime/interpreter/mterp/mips64/op_if_le.S b/runtime/interpreter/mterp/mips64/op_if_le.S
index a7fce17c40750c2a5e1c9374e3dfaa4f7babb530..e6024f2b3e68b7b5654e49affe5582d6bd5ad598 100644
--- a/runtime/interpreter/mterp/mips64/op_if_le.S
+++ b/runtime/interpreter/mterp/mips64/op_if_le.S
@@ -1 +1,2 @@
-%include "mips64/bincmp.S" { "condition":"le" }
+%def op_if_le():
+%  bincmp(condition="le")
diff --git a/runtime/interpreter/mterp/mips64/op_if_lez.S b/runtime/interpreter/mterp/mips64/op_if_lez.S
index f3edcc6d994efc6b00bb7d6f0f94326badfa7aea..62c0d2cd397e5dc55985ed32576521001e2e97a8 100644
--- a/runtime/interpreter/mterp/mips64/op_if_lez.S
+++ b/runtime/interpreter/mterp/mips64/op_if_lez.S
@@ -1 +1,2 @@
-%include "mips64/zcmp.S" { "condition":"le" }
+%def op_if_lez():
+%  zcmp(condition="le")
diff --git a/runtime/interpreter/mterp/mips64/op_if_lt.S b/runtime/interpreter/mterp/mips64/op_if_lt.S
index a975a31b57b597b4d3026f160b24c1a52ffffba8..4ef22fd7987d9f7c113d65b85290703c9d60cfe2 100644
--- a/runtime/interpreter/mterp/mips64/op_if_lt.S
+++ b/runtime/interpreter/mterp/mips64/op_if_lt.S
@@ -1 +1,2 @@
-%include "mips64/bincmp.S" { "condition":"lt" }
+%def op_if_lt():
+%  bincmp(condition="lt")
diff --git a/runtime/interpreter/mterp/mips64/op_if_ltz.S b/runtime/interpreter/mterp/mips64/op_if_ltz.S
index c1d730d43f8a504099b1979abb0dd154f6175908..84b2d0b53a30d05690425994dad613278898adc0 100644
--- a/runtime/interpreter/mterp/mips64/op_if_ltz.S
+++ b/runtime/interpreter/mterp/mips64/op_if_ltz.S
@@ -1 +1,2 @@
-%include "mips64/zcmp.S" { "condition":"lt" }
+%def op_if_ltz():
+%  zcmp(condition="lt")
diff --git a/runtime/interpreter/mterp/mips64/op_if_ne.S b/runtime/interpreter/mterp/mips64/op_if_ne.S
index f143ee917e2e8a76593191c42ad88b6d24572c2c..ec3a688b294d4e3ceff3e99a22de2ecd4dcb220f 100644
--- a/runtime/interpreter/mterp/mips64/op_if_ne.S
+++ b/runtime/interpreter/mterp/mips64/op_if_ne.S
@@ -1 +1,2 @@
-%include "mips64/bincmp.S" { "condition":"ne" }
+%def op_if_ne():
+%  bincmp(condition="ne")
diff --git a/runtime/interpreter/mterp/mips64/op_if_nez.S b/runtime/interpreter/mterp/mips64/op_if_nez.S
index 1856b96dbcd8460b71fdb1116b320470ad29fa45..7009c3acaa9c76772c2db07ea0576d28edeca34c 100644
--- a/runtime/interpreter/mterp/mips64/op_if_nez.S
+++ b/runtime/interpreter/mterp/mips64/op_if_nez.S
@@ -1 +1,2 @@
-%include "mips64/zcmp.S" { "condition":"ne" }
+%def op_if_nez():
+%  zcmp(condition="ne")
diff --git a/runtime/interpreter/mterp/mips64/op_iget.S b/runtime/interpreter/mterp/mips64/op_iget.S
index e91f09923bb072bc42a5a86823dcdb0820040cf9..d09edc0a17c38245736a29f1cf55eb6f5272b87d 100644
--- a/runtime/interpreter/mterp/mips64/op_iget.S
+++ b/runtime/interpreter/mterp/mips64/op_iget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIGetU32"}
-%include "mips64/field.S" { }
+%def op_iget(is_object="0", helper="MterpIGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/mips64/op_iget_boolean.S b/runtime/interpreter/mterp/mips64/op_iget_boolean.S
index dc2a42ad7628f010a175fc5d89ec35af4990988b..cb8edeec773fb6468b5c331b435e409da634f505 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_boolean.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_boolean.S
@@ -1 +1,2 @@
-%include "mips64/op_iget.S" { "helper":"MterpIGetU8" }
+%def op_iget_boolean():
+%  op_iget(helper="MterpIGetU8")
diff --git a/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S
index 979dc7079e09a9bda6e2ad0699b4e9a75db0d313..f3d2cb1e97ab4109190c1d237b807e9671017217 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S
@@ -1 +1,2 @@
-%include "mips64/op_iget_quick.S" { "load":"lbu" }
+%def op_iget_boolean_quick():
+%  op_iget_quick(load="lbu")
diff --git a/runtime/interpreter/mterp/mips64/op_iget_byte.S b/runtime/interpreter/mterp/mips64/op_iget_byte.S
index c5bf6506e6c2086dbacbbb32439ae50005e5e62c..2b87fb16b560430baefa05d3f6e20195cb963d23 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_byte.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_byte.S
@@ -1 +1,2 @@
-%include "mips64/op_iget.S" { "helper":"MterpIGetI8" }
+%def op_iget_byte():
+%  op_iget(helper="MterpIGetI8")
diff --git a/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S b/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S
index cb355567216eea69e1a840fc89d40a2ce783a873..ddb469b3de462032bd244bc0a1306aa89999efee 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S
@@ -1 +1,2 @@
-%include "mips64/op_iget_quick.S" { "load":"lb" }
+%def op_iget_byte_quick():
+%  op_iget_quick(load="lb")
diff --git a/runtime/interpreter/mterp/mips64/op_iget_char.S b/runtime/interpreter/mterp/mips64/op_iget_char.S
index 3bf0c5aab9d29ac518a5abcf8b51266dbed0ef55..001bd03e2b85edc215b29789ba4fc55044b4a230 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_char.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_char.S
@@ -1 +1,2 @@
-%include "mips64/op_iget.S" { "helper":"MterpIGetU16" }
+%def op_iget_char():
+%  op_iget(helper="MterpIGetU16")
diff --git a/runtime/interpreter/mterp/mips64/op_iget_char_quick.S b/runtime/interpreter/mterp/mips64/op_iget_char_quick.S
index 603456775b89e17d81816c24914cc01a0681e62a..ef0b350d4e631e9fe52f891809f797d1f7250cc5 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_char_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_char_quick.S
@@ -1 +1,2 @@
-%include "mips64/op_iget_quick.S" { "load":"lhu" }
+%def op_iget_char_quick():
+%  op_iget_quick(load="lhu")
diff --git a/runtime/interpreter/mterp/mips64/op_iget_object.S b/runtime/interpreter/mterp/mips64/op_iget_object.S
index 23fa187192b8c37df805f944603320c150739304..4e5f769547b494ed962728edba2d102a106b332a 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_object.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_object.S
@@ -1 +1,2 @@
-%include "mips64/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" }
+%def op_iget_object():
+%  op_iget(is_object="1", helper="MterpIGetObj")
diff --git a/runtime/interpreter/mterp/mips64/op_iget_object_quick.S b/runtime/interpreter/mterp/mips64/op_iget_object_quick.S
index 171d54301b26f04e704a9662bfe08d97d8dc6d38..518b747e878c5dde663a75fdf740559bbc0247f3 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_object_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iget_object_quick():
     /* For: iget-object-quick */
     /* op vA, vB, offset//CCCC */
     .extern artIGetObjectFromMterp
diff --git a/runtime/interpreter/mterp/mips64/op_iget_quick.S b/runtime/interpreter/mterp/mips64/op_iget_quick.S
index fee6ab738c3d4c0775c8af962be4d65082c6d755..eb597969aaa52cf517cfd054f4024be163a9bac1 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_quick.S
@@ -1,4 +1,4 @@
-%default { "load":"lw" }
+%def op_iget_quick(load="lw"):
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
diff --git a/runtime/interpreter/mterp/mips64/op_iget_short.S b/runtime/interpreter/mterp/mips64/op_iget_short.S
index a9927fc982c67a9c7b394aeb392aff744fd27e0a..a62c4d998f1d05ed2a3bb1c2f2bf2cca501dfdb8 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_short.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_short.S
@@ -1 +1,2 @@
-%include "mips64/op_iget.S" { "helper":"MterpIGetI16" }
+%def op_iget_short():
+%  op_iget(helper="MterpIGetI16")
diff --git a/runtime/interpreter/mterp/mips64/op_iget_short_quick.S b/runtime/interpreter/mterp/mips64/op_iget_short_quick.S
index 6e152dbf48b539bd93040ad73488a1a2a5626910..5957cb4600af924890ced3b0cf3ace62b69d24e2 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_short_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_short_quick.S
@@ -1 +1,2 @@
-%include "mips64/op_iget_quick.S" { "load":"lh" }
+%def op_iget_short_quick():
+%  op_iget_quick(load="lh")
diff --git a/runtime/interpreter/mterp/mips64/op_iget_wide.S b/runtime/interpreter/mterp/mips64/op_iget_wide.S
index 40f364571fc6ad9b00f6be97d0e56a2f3b2323e3..9643cc340313b657f2485df521ed0ee0cba25f7b 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_wide.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_wide.S
@@ -1 +1,2 @@
-%include "mips64/op_iget.S" { "helper":"MterpIGetU64" }
+%def op_iget_wide():
+%  op_iget(helper="MterpIGetU64")
diff --git a/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S b/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S
index 2adc6adf15bfadea294a2946f4a7492a149f8d5a..e914e0d446b0d248581f3890a8ececd2a9d174e5 100644
--- a/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S
@@ -1,3 +1,4 @@
+%def op_iget_wide_quick():
     /* iget-wide-quick vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
     lhu     a4, 2(rPC)                  # a4 <- field byte offset
diff --git a/runtime/interpreter/mterp/mips64/op_instance_of.S b/runtime/interpreter/mterp/mips64/op_instance_of.S
index 39a5dc7c265977e398b85a40ca59dcbb245a6ff7..1929944d32ae17a2da46678948927cb12baf22a7 100644
--- a/runtime/interpreter/mterp/mips64/op_instance_of.S
+++ b/runtime/interpreter/mterp/mips64/op_instance_of.S
@@ -1,3 +1,4 @@
+%def op_instance_of():
     /*
      * Check to see if an object reference is an instance of a class.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_int_to_byte.S b/runtime/interpreter/mterp/mips64/op_int_to_byte.S
index 1993e076a6cc2bd5ce4ff16f6fb29d7d647a0ad7..47440c6f3a97e35e2b15ed9c8b93aec4c91374aa 100644
--- a/runtime/interpreter/mterp/mips64/op_int_to_byte.S
+++ b/runtime/interpreter/mterp/mips64/op_int_to_byte.S
@@ -1 +1,2 @@
-%include "mips64/unop.S" {"instr":"seb     a0, a0"}
+%def op_int_to_byte():
+%  unop(instr="seb     a0, a0")
diff --git a/runtime/interpreter/mterp/mips64/op_int_to_char.S b/runtime/interpreter/mterp/mips64/op_int_to_char.S
index 8f03acd3f60100d225d6d803a1f566c02bd9afde..bea4e9e81b5d90ce05559acfb8abf86648c5f21e 100644
--- a/runtime/interpreter/mterp/mips64/op_int_to_char.S
+++ b/runtime/interpreter/mterp/mips64/op_int_to_char.S
@@ -1 +1,2 @@
-%include "mips64/unop.S" {"instr":"and     a0, a0, 0xffff"}
+%def op_int_to_char():
+%  unop(instr="and     a0, a0, 0xffff")
diff --git a/runtime/interpreter/mterp/mips64/op_int_to_double.S b/runtime/interpreter/mterp/mips64/op_int_to_double.S
index 6df71be39486ac707da30852b9df717cf6218361..6cc83ae282b58fa9258f0d8e393a9c0cec533e92 100644
--- a/runtime/interpreter/mterp/mips64/op_int_to_double.S
+++ b/runtime/interpreter/mterp/mips64/op_int_to_double.S
@@ -1,8 +1,9 @@
+%def op_int_to_double():
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%  fcvtHeader(suffix="_FLOAT", valreg="f0")
     cvt.d.w f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%  fcvtFooter(suffix="_DOUBLE", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_int_to_float.S b/runtime/interpreter/mterp/mips64/op_int_to_float.S
index 77e9eba53ac0fd5e6141e9955787b1c9e1f2d4b4..837f8f9df3a438d4c50884505f18b844f153d0f8 100644
--- a/runtime/interpreter/mterp/mips64/op_int_to_float.S
+++ b/runtime/interpreter/mterp/mips64/op_int_to_float.S
@@ -1,8 +1,9 @@
+%def op_int_to_float():
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%  fcvtHeader(suffix="_FLOAT", valreg="f0")
     cvt.s.w f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%  fcvtFooter(suffix="_FLOAT", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_int_to_long.S b/runtime/interpreter/mterp/mips64/op_int_to_long.S
index 7b9ad86fdc8f9b2f427fc0ecf2d2ee03d8d603a3..c0cfd72f46cbbc0fa494a4b12353df883c31d821 100644
--- a/runtime/interpreter/mterp/mips64/op_int_to_long.S
+++ b/runtime/interpreter/mterp/mips64/op_int_to_long.S
@@ -1,3 +1,4 @@
+%def op_int_to_long():
     /* int-to-long vA, vB */
     ext     a3, rINST, 12, 4            # a3 <- B
     GET_VREG a0, a3                     # a0 <- vB (sign-extended to 64 bits)
diff --git a/runtime/interpreter/mterp/mips64/op_int_to_short.S b/runtime/interpreter/mterp/mips64/op_int_to_short.S
index 4a3f2346cf8ee49967e6e99eb8f1893ee9994e22..3d90de3e6a25d203e18839049ec0c4c1beb2d62f 100644
--- a/runtime/interpreter/mterp/mips64/op_int_to_short.S
+++ b/runtime/interpreter/mterp/mips64/op_int_to_short.S
@@ -1 +1,2 @@
-%include "mips64/unop.S" {"instr":"seh     a0, a0"}
+%def op_int_to_short():
+%  unop(instr="seh     a0, a0")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_custom.S b/runtime/interpreter/mterp/mips64/op_invoke_custom.S
index 964253d8b7fc58aa64783aa9271d36394d2684b3..4bba9ee5241061aa29e63ea32bb9d575e34286ea 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_custom.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_custom.S
@@ -1 +1,2 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeCustom" }
+%def op_invoke_custom():
+%  invoke(helper="MterpInvokeCustom")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S b/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S
index e6585e3646d497af3ce9258153b55d6c0dd5b14c..57e61af1fa860d814a9da1eaab56b25f199771aa 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S
@@ -1 +1,2 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeCustomRange" }
+%def op_invoke_custom_range():
+%  invoke(helper="MterpInvokeCustomRange")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_direct.S b/runtime/interpreter/mterp/mips64/op_invoke_direct.S
index 5047118e48aa7b3a51bb09eefbd1d1a6ba1f0f69..d3139cf39b42aca474e7d18dcf526e32e80ced85 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_direct.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_direct.S
@@ -1 +1,2 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeDirect" }
+%def op_invoke_direct():
+%  invoke(helper="MterpInvokeDirect")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S b/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S
index 5c9b95f5be6c47cfaa9b64d430d4b1c9438b6d8c..b4a161f48bf8b90b0561e577cdf35f27feb71f23 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S
@@ -1 +1,2 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeDirectRange" }
+%def op_invoke_direct_range():
+%  invoke(helper="MterpInvokeDirectRange")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_interface.S b/runtime/interpreter/mterp/mips64/op_invoke_interface.S
index ed148adcbb613d34db8001a22547e686e9553f6f..b0641262530cb4359c0a054e8307346f64537478 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_interface.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_interface.S
@@ -1,4 +1,5 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeInterface" }
+%def op_invoke_interface():
+%  invoke(helper="MterpInvokeInterface")
     /*
      * Handle an interface method call.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S b/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S
index 91c231e0f4d0138e1b5a754834f93c7c986d1e0d..298911537760c27944307413bb6bbc1a686768a5 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S
@@ -1 +1,2 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeInterfaceRange" }
+%def op_invoke_interface_range():
+%  invoke(helper="MterpInvokeInterfaceRange")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S
index d9324d73bfd4250613f419dd716f9446452e8e70..ce61f5aa0e6039481359af9e0d7de053a159fc79 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S
@@ -1 +1,2 @@
-%include "mips64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" }
+%def op_invoke_polymorphic():
+%  invoke_polymorphic(helper="MterpInvokePolymorphic")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S
index 8e0ecb570af580f4899a30ff47658a8c7513c768..16731bdb4040829bf0020b8524b4f70866b1f1e8 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S
@@ -1 +1,2 @@
-%include "mips64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" }
+%def op_invoke_polymorphic_range():
+%  invoke_polymorphic(helper="MterpInvokePolymorphicRange")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_static.S b/runtime/interpreter/mterp/mips64/op_invoke_static.S
index 44f5cb7a78a6407efd2d1fdf4394c1f0c5f171fb..8b104a66b0b8edd8a28e180d8084e6ce4469e031 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_static.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_static.S
@@ -1 +1,2 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeStatic" }
+%def op_invoke_static():
+%  invoke(helper="MterpInvokeStatic")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_static_range.S b/runtime/interpreter/mterp/mips64/op_invoke_static_range.S
index 289e5aa97750945bc5d032f50bf05d2bbfe51073..e0a546c92b4be72a4a5040d03e0018b1b248f536 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_static_range.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_static_range.S
@@ -1 +1,2 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeStaticRange" }
+%def op_invoke_static_range():
+%  invoke(helper="MterpInvokeStaticRange")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_super.S b/runtime/interpreter/mterp/mips64/op_invoke_super.S
index b13fffe7144ff3893b4b9b9202ffb5decea5786d..3c34c9942ead4172f252ab73aa378fdea74a2bf3 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_super.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_super.S
@@ -1,4 +1,5 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeSuper" }
+%def op_invoke_super():
+%  invoke(helper="MterpInvokeSuper")
     /*
      * Handle a "super" method call.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_super_range.S b/runtime/interpreter/mterp/mips64/op_invoke_super_range.S
index 350b9757ba9a59cc2ecf9cabf6393ccd535321d2..caeafaa13c91fddf7dd3751252e4daf3045dcd2e 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_super_range.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_super_range.S
@@ -1 +1,2 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeSuperRange" }
+%def op_invoke_super_range():
+%  invoke(helper="MterpInvokeSuperRange")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual.S
index 0d26cda812a369e7607dc9b4a0744466b5a5ac5b..249177b813d3ffb3300010c511e78ff279b0ce61 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_virtual.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_virtual.S
@@ -1,4 +1,5 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeVirtual" }
+%def op_invoke_virtual():
+%  invoke(helper="MterpInvokeVirtual")
     /*
      * Handle a virtual method call.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S
index f39562c199cfb937df89466a7139ef3f77b8b02c..ea72c171ecfedd9ddb94bc2e2202e2c56ab11e53 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S
@@ -1 +1,2 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeVirtualQuick" }
+%def op_invoke_virtual_quick():
+%  invoke(helper="MterpInvokeVirtualQuick")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S
index 0bb43f8fccf68066290bcaf0b844949079646968..baa077959359e0dcfbfd3b3cd9814c31b3f6d727 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S
@@ -1 +1,2 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeVirtualRange" }
+%def op_invoke_virtual_range():
+%  invoke(helper="MterpInvokeVirtualRange")
diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S
index c4488513bd9e12c4b7d0baf767e7d83c0797f3af..1d961a0781a94d0087847bce02fcae1f37a75f29 100644
--- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S
@@ -1 +1,2 @@
-%include "mips64/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" }
+%def op_invoke_virtual_range_quick():
+%  invoke(helper="MterpInvokeVirtualQuickRange")
diff --git a/runtime/interpreter/mterp/mips64/op_iput.S b/runtime/interpreter/mterp/mips64/op_iput.S
index 81ab911b5e7923dd571fab5c6fd6b4ba3db6ba82..e5351baf557fe295afb718387a6de58585ba5184 100644
--- a/runtime/interpreter/mterp/mips64/op_iput.S
+++ b/runtime/interpreter/mterp/mips64/op_iput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIPutU32" }
-%include "mips64/field.S" { }
+%def op_iput(is_object="0", helper="MterpIPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/mips64/op_iput_boolean.S b/runtime/interpreter/mterp/mips64/op_iput_boolean.S
index 8e1d08375993cdc1b8534767795a515e974659bf..9eb849877b6207d46a36c083b47c83ebbd7e5d00 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_boolean.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_boolean.S
@@ -1 +1,2 @@
-%include "mips64/op_iput.S" { "helper":"MterpIPutU8" }
+%def op_iput_boolean():
+%  op_iput(helper="MterpIPutU8")
diff --git a/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S
index df99948e4032f95628421366f3d1298ac31a2de9..3d818a5a69426d17fdb687a73121fe89a8c79b42 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S
@@ -1 +1,2 @@
-%include "mips64/op_iput_quick.S" { "store":"sb" }
+%def op_iput_boolean_quick():
+%  op_iput_quick(store="sb")
diff --git a/runtime/interpreter/mterp/mips64/op_iput_byte.S b/runtime/interpreter/mterp/mips64/op_iput_byte.S
index ce3b614b0cc47a1204526e359034261030436087..4b74f9fb0e3c8bfe5566574fae72b21f71cd2067 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_byte.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_byte.S
@@ -1 +1,2 @@
-%include "mips64/op_iput.S" { "helper":"MterpIPutI8" }
+%def op_iput_byte():
+%  op_iput(helper="MterpIPutI8")
diff --git a/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S b/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S
index df99948e4032f95628421366f3d1298ac31a2de9..06dc24e0959e6eca8ebf7ae20d54fa41b37604a3 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S
@@ -1 +1,2 @@
-%include "mips64/op_iput_quick.S" { "store":"sb" }
+%def op_iput_byte_quick():
+%  op_iput_quick(store="sb")
diff --git a/runtime/interpreter/mterp/mips64/op_iput_char.S b/runtime/interpreter/mterp/mips64/op_iput_char.S
index 1d587fad6b1311970980814576bb1714ff29e8d0..64a249fc122e7eb749561fbc7ef7b3cc1be67382 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_char.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_char.S
@@ -1 +1,2 @@
-%include "mips64/op_iput.S" { "helper":"MterpIPutU16" }
+%def op_iput_char():
+%  op_iput(helper="MterpIPutU16")
diff --git a/runtime/interpreter/mterp/mips64/op_iput_char_quick.S b/runtime/interpreter/mterp/mips64/op_iput_char_quick.S
index a6286b7b970fe268cfb8c78cc4dbb70e22f54582..3b6af5b9fea6ca86225ab18712760c5b69284a0a 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_char_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_char_quick.S
@@ -1 +1,2 @@
-%include "mips64/op_iput_quick.S" { "store":"sh" }
+%def op_iput_char_quick():
+%  op_iput_quick(store="sh")
diff --git a/runtime/interpreter/mterp/mips64/op_iput_object.S b/runtime/interpreter/mterp/mips64/op_iput_object.S
index d3316dd7567344e8170befe23a1472d38df9278d..131edd5dbdae914ae95c3220d01788eba1a7ffb2 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_object.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_object.S
@@ -1 +1,2 @@
-%include "mips64/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" }
+%def op_iput_object():
+%  op_iput(is_object="1", helper="MterpIPutObj")
diff --git a/runtime/interpreter/mterp/mips64/op_iput_object_quick.S b/runtime/interpreter/mterp/mips64/op_iput_object_quick.S
index 658ef42a190c466715c968eacbd86baf788b1079..0a15857398305f76f542f1174b7375df8f1b2a3f 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_object_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_object_quick():
     .extern MterpIputObjectQuick
     EXPORT_PC
     daddu   a0, rFP, OFF_FP_SHADOWFRAME
diff --git a/runtime/interpreter/mterp/mips64/op_iput_quick.S b/runtime/interpreter/mterp/mips64/op_iput_quick.S
index b95adfcd4fe8f14d1a7de9981fab3d5b9e2e1ae8..b38b75317f2fc1ead2d8df3a185fd5c6a863e253 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_quick.S
@@ -1,4 +1,4 @@
-%default { "store":"sw" }
+%def op_iput_quick(store="sw"):
     /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
diff --git a/runtime/interpreter/mterp/mips64/op_iput_short.S b/runtime/interpreter/mterp/mips64/op_iput_short.S
index dd68bbeaaa72b0068b3568991699e6a8d3be8467..e631a3b259e969ae8ae1222244d299fd0e4da3d7 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_short.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_short.S
@@ -1 +1,2 @@
-%include "mips64/op_iput.S" { "helper":"MterpIPutI16" }
+%def op_iput_short():
+%  op_iput(helper="MterpIPutI16")
diff --git a/runtime/interpreter/mterp/mips64/op_iput_short_quick.S b/runtime/interpreter/mterp/mips64/op_iput_short_quick.S
index a6286b7b970fe268cfb8c78cc4dbb70e22f54582..fade093fc18d1efec725e06fa834fc989a95ddb8 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_short_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_short_quick.S
@@ -1 +1,2 @@
-%include "mips64/op_iput_quick.S" { "store":"sh" }
+%def op_iput_short_quick():
+%  op_iput_quick(store="sh")
diff --git a/runtime/interpreter/mterp/mips64/op_iput_wide.S b/runtime/interpreter/mterp/mips64/op_iput_wide.S
index 05194b33f33c7846cf997682481ea27309a571f8..2f34fd39f9ed2ca1104582178602a4dac83ee761 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_wide.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_wide.S
@@ -1 +1,2 @@
-%include "mips64/op_iput.S" { "helper":"MterpIPutU64" }
+%def op_iput_wide():
+%  op_iput(helper="MterpIPutU64")
diff --git a/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S b/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S
index 95a8ad8f9c14178aee611081f6a27bacf69f99c0..240f90200ad8e01cb4550f43a5b1c1e8d0c72983 100644
--- a/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S
+++ b/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_wide_quick():
     /* iput-wide-quick vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
     lhu     a3, 2(rPC)                  # a3 <- field byte offset
diff --git a/runtime/interpreter/mterp/mips64/op_long_to_double.S b/runtime/interpreter/mterp/mips64/op_long_to_double.S
index 8503e769b9b6b20a7435203fee0556f178cf56cb..f4d346ca29c417005693bd74b61a3e5018a6ddef 100644
--- a/runtime/interpreter/mterp/mips64/op_long_to_double.S
+++ b/runtime/interpreter/mterp/mips64/op_long_to_double.S
@@ -1,8 +1,9 @@
+%def op_long_to_double():
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%  fcvtHeader(suffix="_DOUBLE", valreg="f0")
     cvt.d.l f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%  fcvtFooter(suffix="_DOUBLE", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_long_to_float.S b/runtime/interpreter/mterp/mips64/op_long_to_float.S
index 31f5c0e9b02653a342cc090ff6245edac42c747a..3c616d15e52bca0aaa567303ef6ef88fb63d9637 100644
--- a/runtime/interpreter/mterp/mips64/op_long_to_float.S
+++ b/runtime/interpreter/mterp/mips64/op_long_to_float.S
@@ -1,8 +1,9 @@
+%def op_long_to_float():
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%  fcvtHeader(suffix="_DOUBLE", valreg="f0")
     cvt.s.l f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%  fcvtFooter(suffix="_FLOAT", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_long_to_int.S b/runtime/interpreter/mterp/mips64/op_long_to_int.S
index 4ef4b512dce23f3433e0b65eda0bebbe6d8883d9..eacb8f59ec402cbb87d740022854981c341e9a09 100644
--- a/runtime/interpreter/mterp/mips64/op_long_to_int.S
+++ b/runtime/interpreter/mterp/mips64/op_long_to_int.S
@@ -1,2 +1,3 @@
+%def op_long_to_int():
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-%include "mips64/op_move.S"
+%  op_move()
diff --git a/runtime/interpreter/mterp/mips64/op_monitor_enter.S b/runtime/interpreter/mterp/mips64/op_monitor_enter.S
index 36ae50346e611bf6297b858763f9d6864feef1b5..47184f9a7bb88f877855057abad7fdd788b9b9ac 100644
--- a/runtime/interpreter/mterp/mips64/op_monitor_enter.S
+++ b/runtime/interpreter/mterp/mips64/op_monitor_enter.S
@@ -1,3 +1,4 @@
+%def op_monitor_enter():
     /*
      * Synchronize on an object.
      */
diff --git a/runtime/interpreter/mterp/mips64/op_monitor_exit.S b/runtime/interpreter/mterp/mips64/op_monitor_exit.S
index 99459520179587f907eeb0fdd2b24eff28028c85..58f8541aa2c995b88cb765ac61b44062141a7ca3 100644
--- a/runtime/interpreter/mterp/mips64/op_monitor_exit.S
+++ b/runtime/interpreter/mterp/mips64/op_monitor_exit.S
@@ -1,3 +1,4 @@
+%def op_monitor_exit():
     /*
      * Unlock an object.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_move.S b/runtime/interpreter/mterp/mips64/op_move.S
index c79f6cde8d4ccc632861a745bb3371fb2b047351..c6de44ccf55ab2c87b4e2bdb9f218eedf5fd4af4 100644
--- a/runtime/interpreter/mterp/mips64/op_move.S
+++ b/runtime/interpreter/mterp/mips64/op_move.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move(is_object="0"):
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     ext     a2, rINST, 8, 4             # a2 <- A
diff --git a/runtime/interpreter/mterp/mips64/op_move_16.S b/runtime/interpreter/mterp/mips64/op_move_16.S
index 9d5c4dce8cf2a60af2980f21c2858cc1617610da..68b7037939da99e3278001a7af526d73cce129d1 100644
--- a/runtime/interpreter/mterp/mips64/op_move_16.S
+++ b/runtime/interpreter/mterp/mips64/op_move_16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_16(is_object="0"):
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     lhu     a3, 4(rPC)                  # a3 <- BBBB
diff --git a/runtime/interpreter/mterp/mips64/op_move_exception.S b/runtime/interpreter/mterp/mips64/op_move_exception.S
index d226718c8f67cf80f40cc370a086d6615a239fe8..8f441c7f7a55e205bbf2293d4506657f572ab3aa 100644
--- a/runtime/interpreter/mterp/mips64/op_move_exception.S
+++ b/runtime/interpreter/mterp/mips64/op_move_exception.S
@@ -1,3 +1,4 @@
+%def op_move_exception():
     /* move-exception vAA */
     srl     a2, rINST, 8                # a2 <- AA
     ld      a0, THREAD_EXCEPTION_OFFSET(rSELF)  # load exception obj
diff --git a/runtime/interpreter/mterp/mips64/op_move_from16.S b/runtime/interpreter/mterp/mips64/op_move_from16.S
index 6d6bde007fd6a36dd0a64c68f92ab119abe87f5e..f4c254c6821daa3a2e64a27863fa24d97b7137e7 100644
--- a/runtime/interpreter/mterp/mips64/op_move_from16.S
+++ b/runtime/interpreter/mterp/mips64/op_move_from16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_from16(is_object="0"):
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     lhu     a3, 2(rPC)                  # a3 <- BBBB
diff --git a/runtime/interpreter/mterp/mips64/op_move_object.S b/runtime/interpreter/mterp/mips64/op_move_object.S
index 47e0272a6c4c22f7c5d47705e7bb23cb8f0dc19e..dbb4d5971027d54f58728020aadfa71973fb509a 100644
--- a/runtime/interpreter/mterp/mips64/op_move_object.S
+++ b/runtime/interpreter/mterp/mips64/op_move_object.S
@@ -1 +1,2 @@
-%include "mips64/op_move.S" {"is_object":"1"}
+%def op_move_object():
+%  op_move(is_object="1")
diff --git a/runtime/interpreter/mterp/mips64/op_move_object_16.S b/runtime/interpreter/mterp/mips64/op_move_object_16.S
index a777dcdaf863b807388dcc3dcc7c28bee1c976f3..40120379d51d6027f960ef7742f12d8d16773855 100644
--- a/runtime/interpreter/mterp/mips64/op_move_object_16.S
+++ b/runtime/interpreter/mterp/mips64/op_move_object_16.S
@@ -1 +1,2 @@
-%include "mips64/op_move_16.S" {"is_object":"1"}
+%def op_move_object_16():
+%  op_move_16(is_object="1")
diff --git a/runtime/interpreter/mterp/mips64/op_move_object_from16.S b/runtime/interpreter/mterp/mips64/op_move_object_from16.S
index ab55ebd646f5b916ff150d5785c095923297017a..c82698e81e6805ad74ebe1f6c8c36e3ff3a1bd4b 100644
--- a/runtime/interpreter/mterp/mips64/op_move_object_from16.S
+++ b/runtime/interpreter/mterp/mips64/op_move_object_from16.S
@@ -1 +1,2 @@
-%include "mips64/op_move_from16.S" {"is_object":"1"}
+%def op_move_object_from16():
+%  op_move_from16(is_object="1")
diff --git a/runtime/interpreter/mterp/mips64/op_move_result.S b/runtime/interpreter/mterp/mips64/op_move_result.S
index 1ec28cb6d8820be81703e18cf90cfcc4a2815118..9d4bdfe0f0bbb30b7fd846dd06d1531e82dcbbc0 100644
--- a/runtime/interpreter/mterp/mips64/op_move_result.S
+++ b/runtime/interpreter/mterp/mips64/op_move_result.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_result(is_object="0"):
     /* for: move-result, move-result-object */
     /* op vAA */
     srl     a2, rINST, 8                # a2 <- AA
diff --git a/runtime/interpreter/mterp/mips64/op_move_result_object.S b/runtime/interpreter/mterp/mips64/op_move_result_object.S
index e76bc22c1124d42304dd88fa69b256ca6e2b55c3..87aea2646a6b25bae7ee8970a973915a76557939 100644
--- a/runtime/interpreter/mterp/mips64/op_move_result_object.S
+++ b/runtime/interpreter/mterp/mips64/op_move_result_object.S
@@ -1 +1,2 @@
-%include "mips64/op_move_result.S" {"is_object":"1"}
+%def op_move_result_object():
+%  op_move_result(is_object="1")
diff --git a/runtime/interpreter/mterp/mips64/op_move_result_wide.S b/runtime/interpreter/mterp/mips64/op_move_result_wide.S
index 3ba0d7288b588cfe2f6a320f23989671e19942c4..048ab3fa942f116e2263085dd357e225e9b29911 100644
--- a/runtime/interpreter/mterp/mips64/op_move_result_wide.S
+++ b/runtime/interpreter/mterp/mips64/op_move_result_wide.S
@@ -1,3 +1,4 @@
+%def op_move_result_wide():
     /* for: move-result-wide */
     /* op vAA */
     srl     a2, rINST, 8                # a2 <- AA
diff --git a/runtime/interpreter/mterp/mips64/op_move_wide.S b/runtime/interpreter/mterp/mips64/op_move_wide.S
index ea23f87ff025daee4e3c3434bf16e0e10290a09f..94cfa47584519126eebff0e96236d639432ad5a0 100644
--- a/runtime/interpreter/mterp/mips64/op_move_wide.S
+++ b/runtime/interpreter/mterp/mips64/op_move_wide.S
@@ -1,3 +1,4 @@
+%def op_move_wide():
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     ext     a3, rINST, 12, 4            # a3 <- B
diff --git a/runtime/interpreter/mterp/mips64/op_move_wide_16.S b/runtime/interpreter/mterp/mips64/op_move_wide_16.S
index 8ec606834b9d0f5d6efb2cc2502ea13115e1bbb6..f3a923e33c1f53fe29ba0f887cf8af47d7df9a86 100644
--- a/runtime/interpreter/mterp/mips64/op_move_wide_16.S
+++ b/runtime/interpreter/mterp/mips64/op_move_wide_16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_16():
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     lhu     a3, 4(rPC)                  # a3 <- BBBB
diff --git a/runtime/interpreter/mterp/mips64/op_move_wide_from16.S b/runtime/interpreter/mterp/mips64/op_move_wide_from16.S
index 11d5603fe135b6cb33637ead73d3910fb8e7d8f3..822035e8fac40a7b03199f92c06881977352e03b 100644
--- a/runtime/interpreter/mterp/mips64/op_move_wide_from16.S
+++ b/runtime/interpreter/mterp/mips64/op_move_wide_from16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_from16():
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     lhu     a3, 2(rPC)                  # a3 <- BBBB
diff --git a/runtime/interpreter/mterp/mips64/op_mul_double.S b/runtime/interpreter/mterp/mips64/op_mul_double.S
index e7e17f7ece518e0fb02652b3c4bcb0f798365fe2..84cf5af93ea2cd12830e4bfeb15908e4f9e9248d 100644
--- a/runtime/interpreter/mterp/mips64/op_mul_double.S
+++ b/runtime/interpreter/mterp/mips64/op_mul_double.S
@@ -1 +1,2 @@
-%include "mips64/fbinopWide.S" {"instr":"mul.d f0, f0, f1"}
+%def op_mul_double():
+%  fbinopWide(instr="mul.d f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S
index f404d4688d3fbcc2ea79fc128bda136e7c5c42ed..1ba6740c1838ed91316361f6aa3a1aca94a66c0d 100644
--- a/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S
@@ -1 +1,2 @@
-%include "mips64/fbinopWide2addr.S" {"instr":"mul.d f0, f0, f1"}
+%def op_mul_double_2addr():
+%  fbinopWide2addr(instr="mul.d f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_mul_float.S b/runtime/interpreter/mterp/mips64/op_mul_float.S
index 9a695fca1682dd0a211cfee501e584e61240e70b..16594ede76b16ee5933ab769c3e38d27eb3dc77c 100644
--- a/runtime/interpreter/mterp/mips64/op_mul_float.S
+++ b/runtime/interpreter/mterp/mips64/op_mul_float.S
@@ -1 +1,2 @@
-%include "mips64/fbinop.S" {"instr":"mul.s f0, f0, f1"}
+%def op_mul_float():
+%  fbinop(instr="mul.s f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S
index a134a34253be231c0e1e58885611297035fc2bf7..318ddab015384451ad65e9662b246669d82f8ea0 100644
--- a/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S
@@ -1 +1,2 @@
-%include "mips64/fbinop2addr.S" {"instr":"mul.s f0, f0, f1"}
+%def op_mul_float_2addr():
+%  fbinop2addr(instr="mul.s f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_mul_int.S b/runtime/interpreter/mterp/mips64/op_mul_int.S
index e1b90ff4e920429e85f1c35f0fe33fb7a57cc830..34e42f0783aa5b9beeb66a6037c6421da821e957 100644
--- a/runtime/interpreter/mterp/mips64/op_mul_int.S
+++ b/runtime/interpreter/mterp/mips64/op_mul_int.S
@@ -1 +1,2 @@
-%include "mips64/binop.S" {"instr":"mul a0, a0, a1"}
+%def op_mul_int():
+%  binop(instr="mul a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S
index c0c4063d548ed1c9ea90e54a3369125db8df17d6..0224a6e2c14210a0180270f6b44ef5de1252d49a 100644
--- a/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binop2addr.S" {"instr":"mul a0, a0, a1"}
+%def op_mul_int_2addr():
+%  binop2addr(instr="mul a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S b/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S
index bb4fff874703c0832692252e10e203007a197e57..935d632e119074677397b812287a07a1e1ad918c 100644
--- a/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S
+++ b/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S
@@ -1 +1,2 @@
-%include "mips64/binopLit16.S" {"instr":"mul a0, a0, a1"}
+%def op_mul_int_lit16():
+%  binopLit16(instr="mul a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S b/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S
index da11ea9295738537ecf2ce06d8d0602fdd506f5b..4a2bfca5c16fcc4cc28dcd3ddc847e15469069ea 100644
--- a/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S
+++ b/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S
@@ -1 +1,2 @@
-%include "mips64/binopLit8.S" {"instr":"mul a0, a0, a1"}
+%def op_mul_int_lit8():
+%  binopLit8(instr="mul a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_mul_long.S b/runtime/interpreter/mterp/mips64/op_mul_long.S
index ec3285060632eb4a9e899f6df113cded816ea898..296138d66e85ea402f33195a28642d5bd3abc2d4 100644
--- a/runtime/interpreter/mterp/mips64/op_mul_long.S
+++ b/runtime/interpreter/mterp/mips64/op_mul_long.S
@@ -1 +1,2 @@
-%include "mips64/binopWide.S" {"instr":"dmul a0, a0, a1"}
+%def op_mul_long():
+%  binopWide(instr="dmul a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S
index eb50cda03ce18ee3e856063642f0e95e6914b4c3..a99eaa49b8e65f1e8a49f52a38952d7d35fe4eeb 100644
--- a/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binopWide2addr.S" {"instr":"dmul a0, a0, a1"}
+%def op_mul_long_2addr():
+%  binopWide2addr(instr="dmul a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_neg_double.S b/runtime/interpreter/mterp/mips64/op_neg_double.S
index a135d611730fe62fb785af5d59f18f6aa2a61a77..aa24c32791beb55c666997d4c9f0700898ee5805 100644
--- a/runtime/interpreter/mterp/mips64/op_neg_double.S
+++ b/runtime/interpreter/mterp/mips64/op_neg_double.S
@@ -1,3 +1,4 @@
-%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%def op_neg_double():
+%  fcvtHeader(suffix="_DOUBLE", valreg="f0")
     neg.d   f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" }
+%  fcvtFooter(suffix="_DOUBLE", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_neg_float.S b/runtime/interpreter/mterp/mips64/op_neg_float.S
index 78019f03d8ef872724a2d98ba896e29adab6ca4b..1554a4db3db4358d32df6475cdfd3753820535cd 100644
--- a/runtime/interpreter/mterp/mips64/op_neg_float.S
+++ b/runtime/interpreter/mterp/mips64/op_neg_float.S
@@ -1,3 +1,4 @@
-%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%def op_neg_float():
+%  fcvtHeader(suffix="_FLOAT", valreg="f0")
     neg.s   f0, f0
-%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" }
+%  fcvtFooter(suffix="_FLOAT", valreg="f0")
diff --git a/runtime/interpreter/mterp/mips64/op_neg_int.S b/runtime/interpreter/mterp/mips64/op_neg_int.S
index 31538c0caa2cf5ef1c4fc76be261f3be1af1160a..9243a2154f46e9f873ff2f187435a1c2a6b04928 100644
--- a/runtime/interpreter/mterp/mips64/op_neg_int.S
+++ b/runtime/interpreter/mterp/mips64/op_neg_int.S
@@ -1 +1,2 @@
-%include "mips64/unop.S" {"instr":"subu    a0, zero, a0"}
+%def op_neg_int():
+%  unop(instr="subu    a0, zero, a0")
diff --git a/runtime/interpreter/mterp/mips64/op_neg_long.S b/runtime/interpreter/mterp/mips64/op_neg_long.S
index bc80d0623f19576d16c7419d7750e8dae9d0ec1d..ad9d5599e523ae70816fd023ded4626c84a304e9 100644
--- a/runtime/interpreter/mterp/mips64/op_neg_long.S
+++ b/runtime/interpreter/mterp/mips64/op_neg_long.S
@@ -1 +1,2 @@
-%include "mips64/unopWide.S" {"instr":"dsubu   a0, zero, a0"}
+%def op_neg_long():
+%  unopWide(instr="dsubu   a0, zero, a0")
diff --git a/runtime/interpreter/mterp/mips64/op_new_array.S b/runtime/interpreter/mterp/mips64/op_new_array.S
index d78b4ac32ef4a0024cba32559fb6f1cf55641250..8da7d832fc0d8db925030d8e55aeff69e8232d69 100644
--- a/runtime/interpreter/mterp/mips64/op_new_array.S
+++ b/runtime/interpreter/mterp/mips64/op_new_array.S
@@ -1,3 +1,4 @@
+%def op_new_array():
     /*
      * Allocate an array of objects, specified with the array class
      * and a count.
diff --git a/runtime/interpreter/mterp/mips64/op_new_instance.S b/runtime/interpreter/mterp/mips64/op_new_instance.S
index cc5e13e00d201aeefc2c5f17b42f5b628ed8707d..a14fd8f8e7ba0b96d827b2c335c8dd5a7343d3be 100644
--- a/runtime/interpreter/mterp/mips64/op_new_instance.S
+++ b/runtime/interpreter/mterp/mips64/op_new_instance.S
@@ -1,3 +1,4 @@
+%def op_new_instance():
     /*
      * Create a new instance of a class.
      */
diff --git a/runtime/interpreter/mterp/mips64/op_nop.S b/runtime/interpreter/mterp/mips64/op_nop.S
index cc803a791a6e3100800aca2bbe461c2c78aa5f0c..925fe4c979ca80e25b8fffe6a2622567f032dc71 100644
--- a/runtime/interpreter/mterp/mips64/op_nop.S
+++ b/runtime/interpreter/mterp/mips64/op_nop.S
@@ -1,3 +1,4 @@
+%def op_nop():
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
diff --git a/runtime/interpreter/mterp/mips64/op_not_int.S b/runtime/interpreter/mterp/mips64/op_not_int.S
index 59540950cdb0efc5008007ef5775e7e9d2a038f6..2fc1dd76faec4f9ae7111398a2d592eae579fd1e 100644
--- a/runtime/interpreter/mterp/mips64/op_not_int.S
+++ b/runtime/interpreter/mterp/mips64/op_not_int.S
@@ -1 +1,2 @@
-%include "mips64/unop.S" {"instr":"nor     a0, zero, a0"}
+%def op_not_int():
+%  unop(instr="nor     a0, zero, a0")
diff --git a/runtime/interpreter/mterp/mips64/op_not_long.S b/runtime/interpreter/mterp/mips64/op_not_long.S
index c8f5da7e82aff11647de579c125e7a9d11e1c773..a551b3144c73790081c922763fb91de24fcf87ac 100644
--- a/runtime/interpreter/mterp/mips64/op_not_long.S
+++ b/runtime/interpreter/mterp/mips64/op_not_long.S
@@ -1 +1,2 @@
-%include "mips64/unopWide.S" {"instr":"nor     a0, zero, a0"}
+%def op_not_long():
+%  unopWide(instr="nor     a0, zero, a0")
diff --git a/runtime/interpreter/mterp/mips64/op_or_int.S b/runtime/interpreter/mterp/mips64/op_or_int.S
index 0102355c55d137d4b69f46e289f247056fa4d368..df60be5896ee88d843f037e37d91cd39d44092b4 100644
--- a/runtime/interpreter/mterp/mips64/op_or_int.S
+++ b/runtime/interpreter/mterp/mips64/op_or_int.S
@@ -1 +1,2 @@
-%include "mips64/binop.S" {"instr":"or a0, a0, a1"}
+%def op_or_int():
+%  binop(instr="or a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_or_int_2addr.S b/runtime/interpreter/mterp/mips64/op_or_int_2addr.S
index eed89008c048dc2e084b201d6720c868b507431e..c202e6799b595c00dac0889570bf6d125aa1cdcb 100644
--- a/runtime/interpreter/mterp/mips64/op_or_int_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_or_int_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binop2addr.S" {"instr":"or a0, a0, a1"}
+%def op_or_int_2addr():
+%  binop2addr(instr="or a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_or_int_lit16.S b/runtime/interpreter/mterp/mips64/op_or_int_lit16.S
index 16a0f3e1a22f7847bf963ed74b108fee4fade095..09961e88453d0d05ad76a0d41e0d76e53aa40e15 100644
--- a/runtime/interpreter/mterp/mips64/op_or_int_lit16.S
+++ b/runtime/interpreter/mterp/mips64/op_or_int_lit16.S
@@ -1 +1,2 @@
-%include "mips64/binopLit16.S" {"instr":"or a0, a0, a1"}
+%def op_or_int_lit16():
+%  binopLit16(instr="or a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_or_int_lit8.S b/runtime/interpreter/mterp/mips64/op_or_int_lit8.S
index dbbf7904c6a4a8b424d8cb557e931ecc78bd0a3f..1bd6809d90a3d7831e519c8f0527294409d0e7d8 100644
--- a/runtime/interpreter/mterp/mips64/op_or_int_lit8.S
+++ b/runtime/interpreter/mterp/mips64/op_or_int_lit8.S
@@ -1 +1,2 @@
-%include "mips64/binopLit8.S" {"instr":"or a0, a0, a1"}
+%def op_or_int_lit8():
+%  binopLit8(instr="or a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_or_long.S b/runtime/interpreter/mterp/mips64/op_or_long.S
index e6f8639e5258e71488d41cf57e70152124031557..65d4c44c5ac49b4560c4aab84ca9c7333fed63ac 100644
--- a/runtime/interpreter/mterp/mips64/op_or_long.S
+++ b/runtime/interpreter/mterp/mips64/op_or_long.S
@@ -1 +1,2 @@
-%include "mips64/binopWide.S" {"instr":"or a0, a0, a1"}
+%def op_or_long():
+%  binopWide(instr="or a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_or_long_2addr.S b/runtime/interpreter/mterp/mips64/op_or_long_2addr.S
index ad5e6c8e993d1625606df57ec4306a1a6a5017d0..5ad0113d4a71d0cfaf3d058435e7edd0770e1689 100644
--- a/runtime/interpreter/mterp/mips64/op_or_long_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_or_long_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binopWide2addr.S" {"instr":"or a0, a0, a1"}
+%def op_or_long_2addr():
+%  binopWide2addr(instr="or a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_packed_switch.S b/runtime/interpreter/mterp/mips64/op_packed_switch.S
index 44e77a41d89c62336e7d2dce5decf508097acd15..36c21077abee335d6df880e851cf751d044f8803 100644
--- a/runtime/interpreter/mterp/mips64/op_packed_switch.S
+++ b/runtime/interpreter/mterp/mips64/op_packed_switch.S
@@ -1,4 +1,4 @@
-%default { "func":"MterpDoPackedSwitch" }
+%def op_packed_switch(func="MterpDoPackedSwitch"):
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
diff --git a/runtime/interpreter/mterp/mips64/op_rem_double.S b/runtime/interpreter/mterp/mips64/op_rem_double.S
index ba61cfdc71a12078072b52ea13108e8aeda41086..16ad357a0a811a966cf06a568e4f844021931679 100644
--- a/runtime/interpreter/mterp/mips64/op_rem_double.S
+++ b/runtime/interpreter/mterp/mips64/op_rem_double.S
@@ -1,3 +1,4 @@
+%def op_rem_double():
     /* rem-double vAA, vBB, vCC */
     .extern fmod
     lbu     a2, 2(rPC)                  # a2 <- BB
diff --git a/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S
index c649f0d62cef2139ed0c7a4a8ad7210658088f26..230d70b37e20ed84cee64569094b57a0f5118b5f 100644
--- a/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S
@@ -1,3 +1,4 @@
+%def op_rem_double_2addr():
     /* rem-double/2addr vA, vB */
     .extern fmod
     ext     a2, rINST, 8, 4             # a2 <- A
diff --git a/runtime/interpreter/mterp/mips64/op_rem_float.S b/runtime/interpreter/mterp/mips64/op_rem_float.S
index 3967b0b02c2cfa73dee3e2290efad02419b58542..08c65164cd43605c3551a62e7baeb2249119af55 100644
--- a/runtime/interpreter/mterp/mips64/op_rem_float.S
+++ b/runtime/interpreter/mterp/mips64/op_rem_float.S
@@ -1,3 +1,4 @@
+%def op_rem_float():
     /* rem-float vAA, vBB, vCC */
     .extern fmodf
     lbu     a2, 2(rPC)                  # a2 <- BB
diff --git a/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S
index 3fed41e8510985d1fbd2c4b9959a3977ae81f266..d35a0f462300b18c5860d711b5c85cc49b049531 100644
--- a/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S
@@ -1,3 +1,4 @@
+%def op_rem_float_2addr():
     /* rem-float/2addr vA, vB */
     .extern fmodf
     ext     a2, rINST, 8, 4             # a2 <- A
diff --git a/runtime/interpreter/mterp/mips64/op_rem_int.S b/runtime/interpreter/mterp/mips64/op_rem_int.S
index c05e9c49fcf0b3ccbfc03743640e244f013a6207..542fe286ed4bd66af96575f33b68fa36c2dab46f 100644
--- a/runtime/interpreter/mterp/mips64/op_rem_int.S
+++ b/runtime/interpreter/mterp/mips64/op_rem_int.S
@@ -1 +1,2 @@
-%include "mips64/binop.S" {"instr":"mod a0, a0, a1", "chkzero":"1"}
+%def op_rem_int():
+%  binop(instr="mod a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S
index a4e162d3fa0d9a130b18bc959a4b1c4859584121..da405767e7a62e02f532eee5933b6d9d2ab9cadb 100644
--- a/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binop2addr.S" {"instr":"mod a0, a0, a1", "chkzero":"1"}
+%def op_rem_int_2addr():
+%  binop2addr(instr="mod a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S b/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S
index 3284f1473c7de5e54c0a3ca04546bcbe9684973b..2dc5173486409748a58b4cd534e1d783017c6be7 100644
--- a/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S
+++ b/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S
@@ -1 +1,2 @@
-%include "mips64/binopLit16.S" {"instr":"mod a0, a0, a1", "chkzero":"1"}
+%def op_rem_int_lit16():
+%  binopLit16(instr="mod a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S b/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S
index 1e6a584be52af5da3fb60b7c8144c5eed2fa82f9..4ea0ace7b573af16c20366cbd1b3dbc6cbc08932 100644
--- a/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S
+++ b/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S
@@ -1 +1,2 @@
-%include "mips64/binopLit8.S" {"instr":"mod a0, a0, a1", "chkzero":"1"}
+%def op_rem_int_lit8():
+%  binopLit8(instr="mod a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_rem_long.S b/runtime/interpreter/mterp/mips64/op_rem_long.S
index 32b2d1916dcde7cb454c4db4de4891c39b92210d..a10984ad0b536620b42ce3adbe05913bee7e12b4 100644
--- a/runtime/interpreter/mterp/mips64/op_rem_long.S
+++ b/runtime/interpreter/mterp/mips64/op_rem_long.S
@@ -1 +1,2 @@
-%include "mips64/binopWide.S" {"instr":"dmod a0, a0, a1", "chkzero":"1"}
+%def op_rem_long():
+%  binopWide(instr="dmod a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S
index ad658e1fde096e23b714004dd9517a02c63d2497..3cac4fba50aa9b6d75effb09679ed7a2d28ae76d 100644
--- a/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binopWide2addr.S" {"instr":"dmod a0, a0, a1", "chkzero":"1"}
+%def op_rem_long_2addr():
+%  binopWide2addr(instr="dmod a0, a0, a1", chkzero="1")
diff --git a/runtime/interpreter/mterp/mips64/op_return.S b/runtime/interpreter/mterp/mips64/op_return.S
index edd795f561e5451c8eb9211ca7340743bec84710..bfdf76a8e5664b2611d8a2c9c3f45b973cc6484a 100644
--- a/runtime/interpreter/mterp/mips64/op_return.S
+++ b/runtime/interpreter/mterp/mips64/op_return.S
@@ -1,4 +1,4 @@
-%default {"instr":"GET_VREG"}
+%def op_return(instr="GET_VREG"):
     /*
      * Return a 32-bit value.
      *
diff --git a/runtime/interpreter/mterp/mips64/op_return_object.S b/runtime/interpreter/mterp/mips64/op_return_object.S
index b69b8806d1c8ec8b474dd7d5da03eaa5caa48920..074c321ef7f180e668f54c14b84d8fb0c035d31c 100644
--- a/runtime/interpreter/mterp/mips64/op_return_object.S
+++ b/runtime/interpreter/mterp/mips64/op_return_object.S
@@ -1 +1,2 @@
-%include "mips64/op_return.S" {"instr":"GET_VREG_U"}
+%def op_return_object():
+%  op_return(instr="GET_VREG_U")
diff --git a/runtime/interpreter/mterp/mips64/op_return_void.S b/runtime/interpreter/mterp/mips64/op_return_void.S
index f6eee915a5c340d348b82a181fe3bdc928a312f8..b5aa76cb69b955b8c9b160c565db3ddbbe78dc85 100644
--- a/runtime/interpreter/mterp/mips64/op_return_void.S
+++ b/runtime/interpreter/mterp/mips64/op_return_void.S
@@ -1,3 +1,4 @@
+%def op_return_void():
     .extern MterpThreadFenceForConstructor
     .extern MterpSuspendCheck
     jal     MterpThreadFenceForConstructor
diff --git a/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S
index 4e9b6402268b25a4a2aaae0854642610402ea3f7..0baddbbaaf1a4e95c651af1b6845d9f4dd8f0093 100644
--- a/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S
+++ b/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S
@@ -1,3 +1,4 @@
+%def op_return_void_no_barrier():
     .extern MterpSuspendCheck
     lw      ra, THREAD_FLAGS_OFFSET(rSELF)
     move    a0, rSELF
diff --git a/runtime/interpreter/mterp/mips64/op_return_wide.S b/runtime/interpreter/mterp/mips64/op_return_wide.S
index 91ca1fae59e0b775d803c8c9b6c66d8e39055e9d..dbcb704eb684211924cb60514ac886fe30e02f37 100644
--- a/runtime/interpreter/mterp/mips64/op_return_wide.S
+++ b/runtime/interpreter/mterp/mips64/op_return_wide.S
@@ -1,3 +1,4 @@
+%def op_return_wide():
     /*
      * Return a 64-bit value.
      */
diff --git a/runtime/interpreter/mterp/mips64/op_rsub_int.S b/runtime/interpreter/mterp/mips64/op_rsub_int.S
index fa31a0af5fa14c92ca6b4277d04c05e2412050f3..2d61e869e1b7fc45c8e2144315049f514ffeaf5a 100644
--- a/runtime/interpreter/mterp/mips64/op_rsub_int.S
+++ b/runtime/interpreter/mterp/mips64/op_rsub_int.S
@@ -1 +1,2 @@
-%include "mips64/binopLit16.S" {"instr":"subu a0, a1, a0"}
+%def op_rsub_int():
+%  binopLit16(instr="subu a0, a1, a0")
diff --git a/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S
index c31ff32060ebf13c62b787a5f88ade40c00f7914..b9b214da945fbd6e0383695c1337751d0168e3fd 100644
--- a/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S
+++ b/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S
@@ -1 +1,2 @@
-%include "mips64/binopLit8.S" {"instr":"subu a0, a1, a0"}
+%def op_rsub_int_lit8():
+%  binopLit8(instr="subu a0, a1, a0")
diff --git a/runtime/interpreter/mterp/mips64/op_sget.S b/runtime/interpreter/mterp/mips64/op_sget.S
index 200da35a12ad640109be25f849609883c27150bd..8a6a66ab6032f5a140fcaa4cb0f85af9cb84bd7a 100644
--- a/runtime/interpreter/mterp/mips64/op_sget.S
+++ b/runtime/interpreter/mterp/mips64/op_sget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSGetU32" }
-%include "mips64/field.S" { }
+%def op_sget(is_object="0", helper="MterpSGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/mips64/op_sget_boolean.S b/runtime/interpreter/mterp/mips64/op_sget_boolean.S
index 8abb396c579fda7e209bebeb8c0a47177644510a..d9c12c9b280100ec8c517e2c264d9c99022bb429 100644
--- a/runtime/interpreter/mterp/mips64/op_sget_boolean.S
+++ b/runtime/interpreter/mterp/mips64/op_sget_boolean.S
@@ -1 +1,2 @@
-%include "mips64/op_sget.S" {"helper":"MterpSGetU8"}
+%def op_sget_boolean():
+%  op_sget(helper="MterpSGetU8")
diff --git a/runtime/interpreter/mterp/mips64/op_sget_byte.S b/runtime/interpreter/mterp/mips64/op_sget_byte.S
index 68623f604c450923aa455a32f3bf6e0a39b0b466..37c6879cd4b02e1fe323434a8f0e490352d4d391 100644
--- a/runtime/interpreter/mterp/mips64/op_sget_byte.S
+++ b/runtime/interpreter/mterp/mips64/op_sget_byte.S
@@ -1 +1,2 @@
-%include "mips64/op_sget.S" {"helper":"MterpSGetI8"}
+%def op_sget_byte():
+%  op_sget(helper="MterpSGetI8")
diff --git a/runtime/interpreter/mterp/mips64/op_sget_char.S b/runtime/interpreter/mterp/mips64/op_sget_char.S
index 3c7b9628135f76e0e75a3436e66981a82513a86e..003bcd16833da0b4c77b8ef60e71ee9bbb01e8da 100644
--- a/runtime/interpreter/mterp/mips64/op_sget_char.S
+++ b/runtime/interpreter/mterp/mips64/op_sget_char.S
@@ -1 +1,2 @@
-%include "mips64/op_sget.S" {"helper":"MterpSGetU16"}
+%def op_sget_char():
+%  op_sget(helper="MterpSGetU16")
diff --git a/runtime/interpreter/mterp/mips64/op_sget_object.S b/runtime/interpreter/mterp/mips64/op_sget_object.S
index 3b260e6ee200a2cec49f725c0a0c0bcb3ea3cc51..7cf3597f44f59b999d828d0749f53401e98cfee6 100644
--- a/runtime/interpreter/mterp/mips64/op_sget_object.S
+++ b/runtime/interpreter/mterp/mips64/op_sget_object.S
@@ -1 +1,2 @@
-%include "mips64/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"}
+%def op_sget_object():
+%  op_sget(is_object="1", helper="MterpSGetObj")
diff --git a/runtime/interpreter/mterp/mips64/op_sget_short.S b/runtime/interpreter/mterp/mips64/op_sget_short.S
index 9a8579ba5b00ee3312075c4d8596b037e6ea5e7d..afacb578d90caf9455c969edfe13663d0927cb03 100644
--- a/runtime/interpreter/mterp/mips64/op_sget_short.S
+++ b/runtime/interpreter/mterp/mips64/op_sget_short.S
@@ -1 +1,2 @@
-%include "mips64/op_sget.S" {"helper":"MterpSGetI16"}
+%def op_sget_short():
+%  op_sget(helper="MterpSGetI16")
diff --git a/runtime/interpreter/mterp/mips64/op_sget_wide.S b/runtime/interpreter/mterp/mips64/op_sget_wide.S
index 14f232c0739b24292042560d2bd1b9164fd2a0cb..fff2be6945510278d990141764285ab694e302ed 100644
--- a/runtime/interpreter/mterp/mips64/op_sget_wide.S
+++ b/runtime/interpreter/mterp/mips64/op_sget_wide.S
@@ -1 +1,2 @@
-%include "mips64/op_sget.S" {"helper":"MterpSGetU64"}
+%def op_sget_wide():
+%  op_sget(helper="MterpSGetU64")
diff --git a/runtime/interpreter/mterp/mips64/op_shl_int.S b/runtime/interpreter/mterp/mips64/op_shl_int.S
index 784481f335df310a6e90760bb53d9b52690c7130..efd213c09a5fa761c0d90192f6a3cee89518d231 100644
--- a/runtime/interpreter/mterp/mips64/op_shl_int.S
+++ b/runtime/interpreter/mterp/mips64/op_shl_int.S
@@ -1 +1,2 @@
-%include "mips64/binop.S" {"instr":"sll a0, a0, a1"}
+%def op_shl_int():
+%  binop(instr="sll a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S b/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S
index a6c8a78ff683eccdd6bc9a43f05a912528bd8176..0901e6b65a2aa3182a34be7ed5c066740532dc07 100644
--- a/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binop2addr.S" {"instr":"sll a0, a0, a1"}
+%def op_shl_int_2addr():
+%  binop2addr(instr="sll a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S b/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S
index 36ef207edf94e456a97c540c6b3715ffd5dea981..2263ec70c23fcc6c00bbda107bc6e34f481de74c 100644
--- a/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S
+++ b/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S
@@ -1 +1,2 @@
-%include "mips64/binopLit8.S" {"instr":"sll a0, a0, a1"}
+%def op_shl_int_lit8():
+%  binopLit8(instr="sll a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_shl_long.S b/runtime/interpreter/mterp/mips64/op_shl_long.S
index 225a2cbc2a945895c9cce3d7302afb48a6c9e1dc..9ef03d8cfa56469fae7a5a6a196213ac3179649b 100644
--- a/runtime/interpreter/mterp/mips64/op_shl_long.S
+++ b/runtime/interpreter/mterp/mips64/op_shl_long.S
@@ -1 +1,2 @@
-%include "mips64/binopWide.S" {"instr":"dsll a0, a0, a1"}
+%def op_shl_long():
+%  binopWide(instr="dsll a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S b/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S
index c04d8823f4fb4a352f9b9270f9ae47a5d2279f0a..f748c3b0452172d005915aeeb27fa6542555aafd 100644
--- a/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binopWide2addr.S" {"instr":"dsll a0, a0, a1"}
+%def op_shl_long_2addr():
+%  binopWide2addr(instr="dsll a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_shr_int.S b/runtime/interpreter/mterp/mips64/op_shr_int.S
index eded0373b14c04100c0e50f6d6fdf3d0e55bcc11..8d55e7afa9a0597d94652c61518b2e3e6a9e4c5e 100644
--- a/runtime/interpreter/mterp/mips64/op_shr_int.S
+++ b/runtime/interpreter/mterp/mips64/op_shr_int.S
@@ -1 +1,2 @@
-%include "mips64/binop.S" {"instr":"sra a0, a0, a1"}
+%def op_shr_int():
+%  binop(instr="sra a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S b/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S
index 5b4d96f187bb64837999bb68874c22bcf44e1ec2..e102baa99f545cbb45da064672ddae74c4d7dcd4 100644
--- a/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binop2addr.S" {"instr":"sra a0, a0, a1"}
+%def op_shr_int_2addr():
+%  binop2addr(instr="sra a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S b/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S
index 175eb8633af6e62b02f0a9df00a19abb3b502456..437c5c49a6730ed184795e3aa091c640a23b1766 100644
--- a/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S
+++ b/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S
@@ -1 +1,2 @@
-%include "mips64/binopLit8.S" {"instr":"sra a0, a0, a1"}
+%def op_shr_int_lit8():
+%  binopLit8(instr="sra a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_shr_long.S b/runtime/interpreter/mterp/mips64/op_shr_long.S
index 0db38c8510f4cf90ed4d8cc5052e81aa433f9e6b..1be48f299a0a97603b33ec2af1c330005bd9f0e2 100644
--- a/runtime/interpreter/mterp/mips64/op_shr_long.S
+++ b/runtime/interpreter/mterp/mips64/op_shr_long.S
@@ -1 +1,2 @@
-%include "mips64/binopWide.S" {"instr":"dsra a0, a0, a1"}
+%def op_shr_long():
+%  binopWide(instr="dsra a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S b/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S
index 48131ad7e47b7c93f3d7e7a5b32a098d2ae26c93..a15861fefd47bf937b082efda4a15120a60a7bbc 100644
--- a/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binopWide2addr.S" {"instr":"dsra a0, a0, a1"}
+%def op_shr_long_2addr():
+%  binopWide2addr(instr="dsra a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_sparse_switch.S b/runtime/interpreter/mterp/mips64/op_sparse_switch.S
index b065aaa95b3f915f2ecdf30b5ae52e47b2bce475..b74d7da81633f307dbf7c07ffaada2d14f131ec3 100644
--- a/runtime/interpreter/mterp/mips64/op_sparse_switch.S
+++ b/runtime/interpreter/mterp/mips64/op_sparse_switch.S
@@ -1 +1,2 @@
-%include "mips64/op_packed_switch.S" { "func":"MterpDoSparseSwitch" }
+%def op_sparse_switch():
+%  op_packed_switch(func="MterpDoSparseSwitch")
diff --git a/runtime/interpreter/mterp/mips64/op_sput.S b/runtime/interpreter/mterp/mips64/op_sput.S
index 0bd683767ff64fa3061650473e20c960adf02380..cbd6ee96d345758221edb4c7f71dd2dda57ac8f0 100644
--- a/runtime/interpreter/mterp/mips64/op_sput.S
+++ b/runtime/interpreter/mterp/mips64/op_sput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSPutU32"}
-%include "mips64/field.S" { }
+%def op_sput(is_object="0", helper="MterpSPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/mips64/op_sput_boolean.S b/runtime/interpreter/mterp/mips64/op_sput_boolean.S
index 2e769d5e1a98b91d54aa1025d8718a012b74833d..36fba8448b478323ce47a26f2a4d79accbf9964d 100644
--- a/runtime/interpreter/mterp/mips64/op_sput_boolean.S
+++ b/runtime/interpreter/mterp/mips64/op_sput_boolean.S
@@ -1 +1,2 @@
-%include "mips64/op_sput.S" {"helper":"MterpSPutU8"}
+%def op_sput_boolean():
+%  op_sput(helper="MterpSPutU8")
diff --git a/runtime/interpreter/mterp/mips64/op_sput_byte.S b/runtime/interpreter/mterp/mips64/op_sput_byte.S
index 0b04b590eebb22522699354d87ffb9e32e6e27bd..84ad4a0ff86ccfcd1159672dac902ee99cfc37d9 100644
--- a/runtime/interpreter/mterp/mips64/op_sput_byte.S
+++ b/runtime/interpreter/mterp/mips64/op_sput_byte.S
@@ -1 +1,2 @@
-%include "mips64/op_sput.S" {"helper":"MterpSPutI8"}
+%def op_sput_byte():
+%  op_sput(helper="MterpSPutI8")
diff --git a/runtime/interpreter/mterp/mips64/op_sput_char.S b/runtime/interpreter/mterp/mips64/op_sput_char.S
index 4a80375d659b0b8b77541aa96c57210a8d453b7a..9b8eeba578f555750ab9497c8fc21ce4a52e8b89 100644
--- a/runtime/interpreter/mterp/mips64/op_sput_char.S
+++ b/runtime/interpreter/mterp/mips64/op_sput_char.S
@@ -1 +1,2 @@
-%include "mips64/op_sput.S" {"helper":"MterpSPutU16"}
+%def op_sput_char():
+%  op_sput(helper="MterpSPutU16")
diff --git a/runtime/interpreter/mterp/mips64/op_sput_object.S b/runtime/interpreter/mterp/mips64/op_sput_object.S
index 09bd0fb7ba448cd1fcbeae604481cd36af07f92a..081360c40fb12c03e3a48c24a3677ee55a609758 100644
--- a/runtime/interpreter/mterp/mips64/op_sput_object.S
+++ b/runtime/interpreter/mterp/mips64/op_sput_object.S
@@ -1 +1,2 @@
-%include "mips64/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"}
+%def op_sput_object():
+%  op_sput(is_object="1", helper="MterpSPutObj")
diff --git a/runtime/interpreter/mterp/mips64/op_sput_short.S b/runtime/interpreter/mterp/mips64/op_sput_short.S
index c00043b6b7f04c9bfc58ea0e83fb7d7f65ff4545..ee16513486189f1a65fe9922285fe9ae08606b97 100644
--- a/runtime/interpreter/mterp/mips64/op_sput_short.S
+++ b/runtime/interpreter/mterp/mips64/op_sput_short.S
@@ -1 +1,2 @@
-%include "mips64/op_sput.S" {"helper":"MterpSPutI16"}
+%def op_sput_short():
+%  op_sput(helper="MterpSPutI16")
diff --git a/runtime/interpreter/mterp/mips64/op_sput_wide.S b/runtime/interpreter/mterp/mips64/op_sput_wide.S
index 070d17ff4d3498972abf70adf83bb8dbe0521c9c..44c1a188edf6bb3cf29011f1b361701ae71aaf9c 100644
--- a/runtime/interpreter/mterp/mips64/op_sput_wide.S
+++ b/runtime/interpreter/mterp/mips64/op_sput_wide.S
@@ -1 +1,2 @@
-%include "mips64/op_sput.S" {"helper":"MterpSPutU64"}
+%def op_sput_wide():
+%  op_sput(helper="MterpSPutU64")
diff --git a/runtime/interpreter/mterp/mips64/op_sub_double.S b/runtime/interpreter/mterp/mips64/op_sub_double.S
index 40a6c89a1002f8f61a418bb6ef4a830d666275a6..aeb1b0f0381a4704bedaffb1d19e6d389263b15d 100644
--- a/runtime/interpreter/mterp/mips64/op_sub_double.S
+++ b/runtime/interpreter/mterp/mips64/op_sub_double.S
@@ -1 +1,2 @@
-%include "mips64/fbinopWide.S" {"instr":"sub.d f0, f0, f1"}
+%def op_sub_double():
+%  fbinopWide(instr="sub.d f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S
index 984737e553a81fc67f8e6edd0754fe5bf91f79fb..03457ac32543c3b4f7b682fee5c5945dd9ea111a 100644
--- a/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S
@@ -1 +1,2 @@
-%include "mips64/fbinopWide2addr.S" {"instr":"sub.d f0, f0, f1"}
+%def op_sub_double_2addr():
+%  fbinopWide2addr(instr="sub.d f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_sub_float.S b/runtime/interpreter/mterp/mips64/op_sub_float.S
index 9010592116aba7e6afefccc0eab60654eb45fb90..4afd1adf3ed4041538dfee6697e4e30aa8b6e75a 100644
--- a/runtime/interpreter/mterp/mips64/op_sub_float.S
+++ b/runtime/interpreter/mterp/mips64/op_sub_float.S
@@ -1 +1,2 @@
-%include "mips64/fbinop.S" {"instr":"sub.s f0, f0, f1"}
+%def op_sub_float():
+%  fbinop(instr="sub.s f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S
index e7d4ffe1ae957bbede8d44d875039464f276928e..b4ade2c1638458cf81c8f337eaf4e5907a9ea9dc 100644
--- a/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S
@@ -1 +1,2 @@
-%include "mips64/fbinop2addr.S" {"instr":"sub.s f0, f0, f1"}
+%def op_sub_float_2addr():
+%  fbinop2addr(instr="sub.s f0, f0, f1")
diff --git a/runtime/interpreter/mterp/mips64/op_sub_int.S b/runtime/interpreter/mterp/mips64/op_sub_int.S
index 609ea0575dad3ec04beb83ab1f6f542dfa8adb0d..57f618d65a1a53e485bbd7505ca5ec9b7c07c70c 100644
--- a/runtime/interpreter/mterp/mips64/op_sub_int.S
+++ b/runtime/interpreter/mterp/mips64/op_sub_int.S
@@ -1 +1,2 @@
-%include "mips64/binop.S" {"instr":"subu a0, a0, a1"}
+%def op_sub_int():
+%  binop(instr="subu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S
index ba2f1e875b6f10724015491e85d6d80a2d72923d..445ffca50fe09d1fb39791ac1aca6e585cdf37a7 100644
--- a/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binop2addr.S" {"instr":"subu a0, a0, a1"}
+%def op_sub_int_2addr():
+%  binop2addr(instr="subu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_sub_long.S b/runtime/interpreter/mterp/mips64/op_sub_long.S
index 09a6afd26ec9756b29aaf30191d29fb125220aa6..ba5fe4960471e41f9e15f7978366933cc9942f87 100644
--- a/runtime/interpreter/mterp/mips64/op_sub_long.S
+++ b/runtime/interpreter/mterp/mips64/op_sub_long.S
@@ -1 +1,2 @@
-%include "mips64/binopWide.S" {"instr":"dsubu a0, a0, a1"}
+%def op_sub_long():
+%  binopWide(instr="dsubu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S
index b9ec82a19b782e631cc97bdc460208e48e11f914..e22b4f6cba4c5d92d0f9e62b9a5f54a08cdcad40 100644
--- a/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binopWide2addr.S" {"instr":"dsubu a0, a0, a1"}
+%def op_sub_long_2addr():
+%  binopWide2addr(instr="dsubu a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_throw.S b/runtime/interpreter/mterp/mips64/op_throw.S
index 6418d57ecc1e17840e3d7effe9b893f9b14f62b2..7f26d88b2f7150c6e3fe32c00a4c41c16e43bbf2 100644
--- a/runtime/interpreter/mterp/mips64/op_throw.S
+++ b/runtime/interpreter/mterp/mips64/op_throw.S
@@ -1,3 +1,4 @@
+%def op_throw():
     /*
      * Throw an exception object in the current thread.
      */
diff --git a/runtime/interpreter/mterp/mips64/op_unused_3e.S b/runtime/interpreter/mterp/mips64/op_unused_3e.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..d889f1a5fb4be366ce5101882ae40577a9b0b90b 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_3e.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_3e.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_3e():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_3f.S b/runtime/interpreter/mterp/mips64/op_unused_3f.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..b3ebcfaeaa402ba263610b3f305daf92cc23bebb 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_3f.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_3f.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_3f():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_40.S b/runtime/interpreter/mterp/mips64/op_unused_40.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..7920fb350f2f93b310d33ec19166b6b8445bb0eb 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_40.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_40.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_40():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_41.S b/runtime/interpreter/mterp/mips64/op_unused_41.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..5ed03b85065e78c670f3d26c62b6c56f58338d44 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_41.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_41.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_41():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_42.S b/runtime/interpreter/mterp/mips64/op_unused_42.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..ac32521add543fb2f858aa858af6c3d5594f187e 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_42.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_42.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_42():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_43.S b/runtime/interpreter/mterp/mips64/op_unused_43.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..33e2aa10f8bec8407ff8090cfd81dda49b2a19b8 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_43.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_43.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_43():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_79.S b/runtime/interpreter/mterp/mips64/op_unused_79.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..3c6dafc7898855a1034ff93b17bed71a07df1e51 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_79.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_79.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_79():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_7a.S b/runtime/interpreter/mterp/mips64/op_unused_7a.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..9c03cd55355a41369dc85dbea7e07e7bd8e96383 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_7a.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_7a.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_7a():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_f3.S b/runtime/interpreter/mterp/mips64/op_unused_f3.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..ab10b78be2a0b681652d52185cf7c39d3403a41e 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_f3.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_f3.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_f3():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_f4.S b/runtime/interpreter/mterp/mips64/op_unused_f4.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..09229d6d99f58a24b923c56b2937662a10e16de6 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_f4.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_f4.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_f4():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_f5.S b/runtime/interpreter/mterp/mips64/op_unused_f5.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0d6149b5fd6eeb0221067adb660d453080ba1fd2 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_f5.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_f5.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_f5():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_f6.S b/runtime/interpreter/mterp/mips64/op_unused_f6.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..117b03de6d321ace7f917fe69b79b9f182081e11 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_f6.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_f6.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_f6():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_f7.S b/runtime/interpreter/mterp/mips64/op_unused_f7.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..4e3a0f3c9a6eef078506555805a72056272abfc1 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_f7.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_f7.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_f7():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_f8.S b/runtime/interpreter/mterp/mips64/op_unused_f8.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..d1220752d7b5b191c0712bf975e90ac7777e4303 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_f8.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_f8.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_f8():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_f9.S b/runtime/interpreter/mterp/mips64/op_unused_f9.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..7d09a0ebcfce77f4a1bd8b19865ac5d782e382dd 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_f9.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_f9.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_f9():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_fc.S b/runtime/interpreter/mterp/mips64/op_unused_fc.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..06978191ebbcceb51b9820b3e650a0baf767a507 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_fc.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_fc.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_fc():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_unused_fd.S b/runtime/interpreter/mterp/mips64/op_unused_fd.S
index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..4bc2b4bdb6516467406cb88476e1d993a3f0c749 100644
--- a/runtime/interpreter/mterp/mips64/op_unused_fd.S
+++ b/runtime/interpreter/mterp/mips64/op_unused_fd.S
@@ -1 +1,2 @@
-%include "mips64/unused.S"
+%def op_unused_fd():
+%  unused()
diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int.S b/runtime/interpreter/mterp/mips64/op_ushr_int.S
index 37c90cb7ec4db6c72c6eafc5fb0a6c2b5747252c..98d2dfbc9c63cf1ef0c1321180c1ec7f6acdc9ca 100644
--- a/runtime/interpreter/mterp/mips64/op_ushr_int.S
+++ b/runtime/interpreter/mterp/mips64/op_ushr_int.S
@@ -1 +1,2 @@
-%include "mips64/binop.S" {"instr":"srl a0, a0, a1"}
+%def op_ushr_int():
+%  binop(instr="srl a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S
index d6bf4135dc5e6f4d8e55ad4051c2f3c8d6b22b4f..9b89e21643a58b17a1fb7d0bad6dfe8caac4ecb4 100644
--- a/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binop2addr.S" {"instr":"srl a0, a0, a1"}
+%def op_ushr_int_2addr():
+%  binop2addr(instr="srl a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S
index 2a2d843c8aadf3d149abe56368ee652c39325c14..531c30a000f3c42e6d17add7d952b4a51a402c3e 100644
--- a/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S
+++ b/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S
@@ -1 +1,2 @@
-%include "mips64/binopLit8.S" {"instr":"srl a0, a0, a1"}
+%def op_ushr_int_lit8():
+%  binopLit8(instr="srl a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_ushr_long.S b/runtime/interpreter/mterp/mips64/op_ushr_long.S
index e724405f1f9bf9251021429f9c69bb9fac95d233..e900f76f902d55291552710a5bc1728e785ee429 100644
--- a/runtime/interpreter/mterp/mips64/op_ushr_long.S
+++ b/runtime/interpreter/mterp/mips64/op_ushr_long.S
@@ -1 +1,2 @@
-%include "mips64/binopWide.S" {"instr":"dsrl a0, a0, a1"}
+%def op_ushr_long():
+%  binopWide(instr="dsrl a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S
index d2cf1355666e81758e5e784e926258fa75d2ef21..e13fc75612ec2b559f8b989eaa00ad7f7f001df3 100644
--- a/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binopWide2addr.S" {"instr":"dsrl a0, a0, a1"}
+%def op_ushr_long_2addr():
+%  binopWide2addr(instr="dsrl a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_xor_int.S b/runtime/interpreter/mterp/mips64/op_xor_int.S
index ee25ebc925375dd34097b592989c1394625de66d..1379a344e0e76feedb47ce67e11d712331def065 100644
--- a/runtime/interpreter/mterp/mips64/op_xor_int.S
+++ b/runtime/interpreter/mterp/mips64/op_xor_int.S
@@ -1 +1,2 @@
-%include "mips64/binop.S" {"instr":"xor a0, a0, a1"}
+%def op_xor_int():
+%  binop(instr="xor a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S b/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S
index 0f0496729aae7f18c3fbc2fbc2fa128f4583323c..6dbe11c3a8de505522b11bb85a7e4596bca990fd 100644
--- a/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binop2addr.S" {"instr":"xor a0, a0, a1"}
+%def op_xor_int_2addr():
+%  binop2addr(instr="xor a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S b/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S
index ecb21aee07e1c5e56cc18831b298f7a5ba244c88..f8cbce04f426f0ac2db2e4e2a69a1b5142eec4cd 100644
--- a/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S
+++ b/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S
@@ -1 +1,2 @@
-%include "mips64/binopLit16.S" {"instr":"xor a0, a0, a1"}
+%def op_xor_int_lit16():
+%  binopLit16(instr="xor a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S b/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S
index 115ae99917c06474806c37262f4521f92242a62d..268a43aac84dd24f14ee336d7b16844eb47ad8f3 100644
--- a/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S
+++ b/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S
@@ -1 +1,2 @@
-%include "mips64/binopLit8.S" {"instr":"xor a0, a0, a1"}
+%def op_xor_int_lit8():
+%  binopLit8(instr="xor a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_xor_long.S b/runtime/interpreter/mterp/mips64/op_xor_long.S
index 7ebabc2710bc131e83e0105a6a6da32b6733ac30..75d4c07984e177068fad5e805027d33e7a61971c 100644
--- a/runtime/interpreter/mterp/mips64/op_xor_long.S
+++ b/runtime/interpreter/mterp/mips64/op_xor_long.S
@@ -1 +1,2 @@
-%include "mips64/binopWide.S" {"instr":"xor a0, a0, a1"}
+%def op_xor_long():
+%  binopWide(instr="xor a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S b/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S
index 0f1919a21efcb34c641c8418f9ac59d14fc940af..2e76613168350b81ff36109d93258a6f5d1bd165 100644
--- a/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S
+++ b/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S
@@ -1 +1,2 @@
-%include "mips64/binopWide2addr.S" {"instr":"xor a0, a0, a1"}
+%def op_xor_long_2addr():
+%  binopWide2addr(instr="xor a0, a0, a1")
diff --git a/runtime/interpreter/mterp/mips64/unop.S b/runtime/interpreter/mterp/mips64/unop.S
index e3f7ea0eda286915f2ba2ad5f3565f6082f1cb6a..860e6bbb6a7d5362434c1be49c1282ab3e6d7448 100644
--- a/runtime/interpreter/mterp/mips64/unop.S
+++ b/runtime/interpreter/mterp/mips64/unop.S
@@ -1,4 +1,4 @@
-%default {"preinstr":""}
+%def unop(preinstr="", instr=""):
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "a0 = op a0".
diff --git a/runtime/interpreter/mterp/mips64/unopWide.S b/runtime/interpreter/mterp/mips64/unopWide.S
index c0dd1aa1d3e2c23722293974222ac23ff1d827ed..d0a6f5b76684e4c559a7ed9bb4413221dfd499f2 100644
--- a/runtime/interpreter/mterp/mips64/unopWide.S
+++ b/runtime/interpreter/mterp/mips64/unopWide.S
@@ -1,4 +1,4 @@
-%default {"preinstr":""}
+%def unopWide(preinstr="", instr=""):
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "a0 = op a0".
diff --git a/runtime/interpreter/mterp/mips64/unused.S b/runtime/interpreter/mterp/mips64/unused.S
index 30d38bd6cdcdde3096d36fbddfb6760de2ea9781..3d611d170bb3ad259c20fd00c828f6272d4497ed 100644
--- a/runtime/interpreter/mterp/mips64/unused.S
+++ b/runtime/interpreter/mterp/mips64/unused.S
@@ -1,3 +1,4 @@
+%def unused():
 /*
  * Bail to reference interpreter to throw.
  */
diff --git a/runtime/interpreter/mterp/mips64/zcmp.S b/runtime/interpreter/mterp/mips64/zcmp.S
index 75db49edd499c560256c17adf94febb6ebfdee46..a0d2832514e94fc2c4723834fd555796a9624b16 100644
--- a/runtime/interpreter/mterp/mips64/zcmp.S
+++ b/runtime/interpreter/mterp/mips64/zcmp.S
@@ -1,3 +1,4 @@
+%def zcmp(condition=""):
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
diff --git a/runtime/interpreter/mterp/out/mterp_arm.S b/runtime/interpreter/mterp/out/mterp_arm.S
index 25512aec375961a64705dc827042bdab8192981c..dc476b7ff813f367451bf3178a8b827a7018b03b 100644
--- a/runtime/interpreter/mterp/out/mterp_arm.S
+++ b/runtime/interpreter/mterp/out/mterp_arm.S
@@ -1,10 +1,4 @@
-/*
- * This file was generated automatically by gen-mterp.py for 'arm'.
- *
- * --> DO NOT EDIT <--
- */
-
-/* File: arm/header.S */
+/* DO NOT EDIT: This file was generated by gen-mterp.py. */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -317,8 +311,6 @@ unspecified registers or condition codes.
     .cfi_endproc
     .size \name, .-\name
 .endm
-
-/* File: arm/entry.S */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -396,18 +388,14 @@ ENTRY ExecuteMterpImpl
     GOTO_OPCODE ip                      @ jump to next instruction
     /* NOTE: no fallthrough */
 
-/* File: arm/instruction_start.S */
-
     .type artMterpAsmInstructionStart, #object
     .hidden artMterpAsmInstructionStart
     .global artMterpAsmInstructionStart
 artMterpAsmInstructionStart = .L_op_nop
     .text
-
 /* ------------------------------ */
     .balign 128
 .L_op_nop: /* 0x00 */
-/* File: arm/op_nop.S */
     FETCH_ADVANCE_INST 1                @ advance to next instr, load rINST
     GET_INST_OPCODE ip                  @ ip<- opcode from rINST
     GOTO_OPCODE ip                      @ execute it
@@ -415,7 +403,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move: /* 0x01 */
-/* File: arm/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     mov     r1, rINST, lsr #12          @ r1<- B from 15:12
@@ -433,7 +420,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_from16: /* 0x02 */
-/* File: arm/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     FETCH r1, 1                         @ r1<- BBBB
@@ -451,7 +437,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_16: /* 0x03 */
-/* File: arm/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     FETCH r1, 2                         @ r1<- BBBB
@@ -469,7 +454,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide: /* 0x04 */
-/* File: arm/op_move_wide.S */
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     mov     r3, rINST, lsr #12          @ r3<- B
@@ -486,7 +470,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_from16: /* 0x05 */
-/* File: arm/op_move_wide_from16.S */
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     FETCH r3, 1                         @ r3<- BBBB
@@ -503,7 +486,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_16: /* 0x06 */
-/* File: arm/op_move_wide_16.S */
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     FETCH r3, 2                         @ r3<- BBBB
@@ -520,8 +502,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_object: /* 0x07 */
-/* File: arm/op_move_object.S */
-/* File: arm/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     mov     r1, rINST, lsr #12          @ r1<- B from 15:12
@@ -536,12 +516,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE ip                      @ execute next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_from16: /* 0x08 */
-/* File: arm/op_move_object_from16.S */
-/* File: arm/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     FETCH r1, 1                         @ r1<- BBBB
@@ -556,12 +533,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_16: /* 0x09 */
-/* File: arm/op_move_object_16.S */
-/* File: arm/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     FETCH r1, 2                         @ r1<- BBBB
@@ -576,11 +550,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_result: /* 0x0a */
-/* File: arm/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     mov     r2, rINST, lsr #8           @ r2<- AA
@@ -598,7 +570,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_wide: /* 0x0b */
-/* File: arm/op_move_result_wide.S */
     /* move-result-wide vAA */
     mov     rINST, rINST, lsr #8        @ rINST<- AA
     ldr     r3, [rFP, #OFF_FP_RESULT_REGISTER]
@@ -613,8 +584,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_object: /* 0x0c */
-/* File: arm/op_move_result_object.S */
-/* File: arm/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     mov     r2, rINST, lsr #8           @ r2<- AA
@@ -629,11 +598,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_exception: /* 0x0d */
-/* File: arm/op_move_exception.S */
     /* move-exception vAA */
     mov     r2, rINST, lsr #8           @ r2<- AA
     ldr     r3, [rSELF, #THREAD_EXCEPTION_OFFSET]
@@ -647,7 +614,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_void: /* 0x0e */
-/* File: arm/op_return_void.S */
     .extern MterpThreadFenceForConstructor
     bl      MterpThreadFenceForConstructor
     ldr     lr, [rSELF, #THREAD_FLAGS_OFFSET]
@@ -661,7 +627,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return: /* 0x0f */
-/* File: arm/op_return.S */
     /*
      * Return a 32-bit value.
      *
@@ -682,7 +647,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_wide: /* 0x10 */
-/* File: arm/op_return_wide.S */
     /*
      * Return a 64-bit value.
      */
@@ -701,8 +665,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_object: /* 0x11 */
-/* File: arm/op_return_object.S */
-/* File: arm/op_return.S */
     /*
      * Return a 32-bit value.
      *
@@ -720,11 +682,9 @@ artMterpAsmInstructionStart = .L_op_nop
     mov     r1, #0
     b       MterpReturn
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_4: /* 0x12 */
-/* File: arm/op_const_4.S */
     /* const/4 vA, #+B */
     sbfx    r1, rINST, #12, #4          @ r1<- sssssssB (sign-extended)
     ubfx    r0, rINST, #8, #4           @ r0<- A
@@ -736,7 +696,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_16: /* 0x13 */
-/* File: arm/op_const_16.S */
     /* const/16 vAA, #+BBBB */
     FETCH_S r0, 1                       @ r0<- ssssBBBB (sign-extended)
     mov     r3, rINST, lsr #8           @ r3<- AA
@@ -748,7 +707,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const: /* 0x14 */
-/* File: arm/op_const.S */
     /* const vAA, #+BBBBbbbb */
     mov     r3, rINST, lsr #8           @ r3<- AA
     FETCH r0, 1                         @ r0<- bbbb (low)
@@ -762,7 +720,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_high16: /* 0x15 */
-/* File: arm/op_const_high16.S */
     /* const/high16 vAA, #+BBBB0000 */
     FETCH r0, 1                         @ r0<- 0000BBBB (zero-extended)
     mov     r3, rINST, lsr #8           @ r3<- AA
@@ -775,7 +732,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_16: /* 0x16 */
-/* File: arm/op_const_wide_16.S */
     /* const-wide/16 vAA, #+BBBB */
     FETCH_S r0, 1                       @ r0<- ssssBBBB (sign-extended)
     mov     r3, rINST, lsr #8           @ r3<- AA
@@ -790,7 +746,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_32: /* 0x17 */
-/* File: arm/op_const_wide_32.S */
     /* const-wide/32 vAA, #+BBBBbbbb */
     FETCH r0, 1                         @ r0<- 0000bbbb (low)
     mov     r3, rINST, lsr #8           @ r3<- AA
@@ -807,7 +762,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide: /* 0x18 */
-/* File: arm/op_const_wide.S */
     /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
     FETCH r0, 1                         @ r0<- bbbb (low)
     FETCH r1, 2                         @ r1<- BBBB (low middle)
@@ -826,7 +780,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_high16: /* 0x19 */
-/* File: arm/op_const_wide_high16.S */
     /* const-wide/high16 vAA, #+BBBB000000000000 */
     FETCH r1, 1                         @ r1<- 0000BBBB (zero-extended)
     mov     r3, rINST, lsr #8           @ r3<- AA
@@ -842,8 +795,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_string: /* 0x1a */
-/* File: arm/op_const_string.S */
-/* File: arm/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -862,11 +813,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_string_jumbo: /* 0x1b */
-/* File: arm/op_const_string_jumbo.S */
     /* const/string vAA, String@BBBBBBBB */
     EXPORT_PC
     FETCH r0, 1                         @ r0<- bbbb (low)
@@ -886,8 +835,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_class: /* 0x1c */
-/* File: arm/op_const_class.S */
-/* File: arm/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -906,11 +853,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_enter: /* 0x1d */
-/* File: arm/op_monitor_enter.S */
     /*
      * Synchronize on an object.
      */
@@ -929,7 +874,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_exit: /* 0x1e */
-/* File: arm/op_monitor_exit.S */
     /*
      * Unlock an object.
      *
@@ -952,7 +896,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_check_cast: /* 0x1f */
-/* File: arm/op_check_cast.S */
     /*
      * Check to see if a cast from one class to another is allowed.
      */
@@ -974,7 +917,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_instance_of: /* 0x20 */
-/* File: arm/op_instance_of.S */
     /*
      * Check to see if an object reference is an instance of a class.
      *
@@ -1002,7 +944,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_array_length: /* 0x21 */
-/* File: arm/op_array_length.S */
     /*
      * Return the length of an array.
      */
@@ -1020,7 +961,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_instance: /* 0x22 */
-/* File: arm/op_new_instance.S */
     /*
      * Create a new instance of a class.
      */
@@ -1039,7 +979,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_array: /* 0x23 */
-/* File: arm/op_new_array.S */
     /*
      * Allocate an array of objects, specified with the array class
      * and a count.
@@ -1063,7 +1002,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array: /* 0x24 */
-/* File: arm/op_filled_new_array.S */
     /*
      * Create a new array with elements filled from registers.
      *
@@ -1086,8 +1024,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array_range: /* 0x25 */
-/* File: arm/op_filled_new_array_range.S */
-/* File: arm/op_filled_new_array.S */
     /*
      * Create a new array with elements filled from registers.
      *
@@ -1107,11 +1043,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_fill_array_data: /* 0x26 */
-/* File: arm/op_fill_array_data.S */
     /* fill-array-data vAA, +BBBBBBBB */
     EXPORT_PC
     FETCH r0, 1                         @ r0<- bbbb (lo)
@@ -1130,7 +1064,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_throw: /* 0x27 */
-/* File: arm/op_throw.S */
     /*
      * Throw an exception object in the current thread.
      */
@@ -1146,7 +1079,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto: /* 0x28 */
-/* File: arm/op_goto.S */
     /*
      * Unconditional branch, 8-bit offset.
      *
@@ -1160,7 +1092,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_16: /* 0x29 */
-/* File: arm/op_goto_16.S */
     /*
      * Unconditional branch, 16-bit offset.
      *
@@ -1174,7 +1105,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_32: /* 0x2a */
-/* File: arm/op_goto_32.S */
     /*
      * Unconditional branch, 32-bit offset.
      *
@@ -1195,7 +1125,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_packed_switch: /* 0x2b */
-/* File: arm/op_packed_switch.S */
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
@@ -1219,8 +1148,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_sparse_switch: /* 0x2c */
-/* File: arm/op_sparse_switch.S */
-/* File: arm/op_packed_switch.S */
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
@@ -1241,11 +1168,9 @@ artMterpAsmInstructionStart = .L_op_nop
     movs    rINST, r0
     b       MterpCommonTakenBranch
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_float: /* 0x2d */
-/* File: arm/op_cmpl_float.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1284,7 +1209,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_float: /* 0x2e */
-/* File: arm/op_cmpg_float.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1323,7 +1247,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_double: /* 0x2f */
-/* File: arm/op_cmpl_double.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1362,7 +1285,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_double: /* 0x30 */
-/* File: arm/op_cmpg_double.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1401,7 +1323,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_cmp_long: /* 0x31 */
-/* File: arm/op_cmp_long.S */
     /*
      * Compare two 64-bit values.  Puts 0, 1, or -1 into the destination
      * register based on the results of the comparison.
@@ -1429,8 +1350,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_if_eq: /* 0x32 */
-/* File: arm/op_if_eq.S */
-/* File: arm/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1451,12 +1370,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ne: /* 0x33 */
-/* File: arm/op_if_ne.S */
-/* File: arm/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1477,12 +1393,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lt: /* 0x34 */
-/* File: arm/op_if_lt.S */
-/* File: arm/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1503,12 +1416,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ge: /* 0x35 */
-/* File: arm/op_if_ge.S */
-/* File: arm/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1529,12 +1439,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gt: /* 0x36 */
-/* File: arm/op_if_gt.S */
-/* File: arm/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1555,12 +1462,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_le: /* 0x37 */
-/* File: arm/op_if_le.S */
-/* File: arm/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1581,12 +1485,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_eqz: /* 0x38 */
-/* File: arm/op_if_eqz.S */
-/* File: arm/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1605,12 +1506,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_nez: /* 0x39 */
-/* File: arm/op_if_nez.S */
-/* File: arm/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1629,12 +1527,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ltz: /* 0x3a */
-/* File: arm/op_if_ltz.S */
-/* File: arm/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1653,12 +1548,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gez: /* 0x3b */
-/* File: arm/op_if_gez.S */
-/* File: arm/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1677,12 +1569,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gtz: /* 0x3c */
-/* File: arm/op_if_gtz.S */
-/* File: arm/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1701,12 +1590,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lez: /* 0x3d */
-/* File: arm/op_if_lez.S */
-/* File: arm/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1725,77 +1611,57 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3e: /* 0x3e */
-/* File: arm/op_unused_3e.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3f: /* 0x3f */
-/* File: arm/op_unused_3f.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_40: /* 0x40 */
-/* File: arm/op_unused_40.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_41: /* 0x41 */
-/* File: arm/op_unused_41.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_42: /* 0x42 */
-/* File: arm/op_unused_42.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_43: /* 0x43 */
-/* File: arm/op_unused_43.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget: /* 0x44 */
-/* File: arm/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1828,7 +1694,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_wide: /* 0x45 */
-/* File: arm/op_aget_wide.S */
     /*
      * Array get, 64 bits.  vAA <- vBB[vCC].
      *
@@ -1858,7 +1723,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_object: /* 0x46 */
-/* File: arm/op_aget_object.S */
     /*
      * Array object get.  vAA <- vBB[vCC].
      *
@@ -1884,8 +1748,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_boolean: /* 0x47 */
-/* File: arm/op_aget_boolean.S */
-/* File: arm/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1915,12 +1777,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG r2, r9                     @ vAA<- r2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_byte: /* 0x48 */
-/* File: arm/op_aget_byte.S */
-/* File: arm/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1950,12 +1809,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG r2, r9                     @ vAA<- r2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_char: /* 0x49 */
-/* File: arm/op_aget_char.S */
-/* File: arm/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1985,12 +1841,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG r2, r9                     @ vAA<- r2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_short: /* 0x4a */
-/* File: arm/op_aget_short.S */
-/* File: arm/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -2020,11 +1873,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG r2, r9                     @ vAA<- r2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput: /* 0x4b */
-/* File: arm/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2057,7 +1908,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_wide: /* 0x4c */
-/* File: arm/op_aput_wide.S */
     /*
      * Array put, 64 bits.  vBB[vCC] <- vAA.
      *
@@ -2086,7 +1936,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_object: /* 0x4d */
-/* File: arm/op_aput_object.S */
     /*
      * Store an object into an array.  vBB[vCC] <- vAA.
      */
@@ -2105,8 +1954,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_boolean: /* 0x4e */
-/* File: arm/op_aput_boolean.S */
-/* File: arm/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2136,12 +1983,9 @@ artMterpAsmInstructionStart = .L_op_nop
     strb  r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET]     @ vBB[vCC]<- r2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_byte: /* 0x4f */
-/* File: arm/op_aput_byte.S */
-/* File: arm/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2171,12 +2015,9 @@ artMterpAsmInstructionStart = .L_op_nop
     strb  r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET]     @ vBB[vCC]<- r2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_char: /* 0x50 */
-/* File: arm/op_aput_char.S */
-/* File: arm/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2206,12 +2047,9 @@ artMterpAsmInstructionStart = .L_op_nop
     strh  r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET]     @ vBB[vCC]<- r2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_short: /* 0x51 */
-/* File: arm/op_aput_short.S */
-/* File: arm/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2241,12 +2079,9 @@ artMterpAsmInstructionStart = .L_op_nop
     strh  r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET]     @ vBB[vCC]<- r2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget: /* 0x52 */
-/* File: arm/op_iget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2263,13 +2098,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide: /* 0x53 */
-/* File: arm/op_iget_wide.S */
-/* File: arm/op_iget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2286,14 +2117,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object: /* 0x54 */
-/* File: arm/op_iget_object.S */
-/* File: arm/op_iget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2310,14 +2136,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean: /* 0x55 */
-/* File: arm/op_iget_boolean.S */
-/* File: arm/op_iget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2334,14 +2155,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte: /* 0x56 */
-/* File: arm/op_iget_byte.S */
-/* File: arm/op_iget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2358,14 +2174,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char: /* 0x57 */
-/* File: arm/op_iget_char.S */
-/* File: arm/op_iget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2382,14 +2193,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short: /* 0x58 */
-/* File: arm/op_iget_short.S */
-/* File: arm/op_iget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2406,13 +2212,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput: /* 0x59 */
-/* File: arm/op_iput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2429,13 +2231,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide: /* 0x5a */
-/* File: arm/op_iput_wide.S */
-/* File: arm/op_iput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2452,14 +2250,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object: /* 0x5b */
-/* File: arm/op_iput_object.S */
-/* File: arm/op_iput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2476,14 +2269,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean: /* 0x5c */
-/* File: arm/op_iput_boolean.S */
-/* File: arm/op_iput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2500,14 +2288,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte: /* 0x5d */
-/* File: arm/op_iput_byte.S */
-/* File: arm/op_iput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2524,14 +2307,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char: /* 0x5e */
-/* File: arm/op_iput_char.S */
-/* File: arm/op_iput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2548,14 +2326,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short: /* 0x5f */
-/* File: arm/op_iput_short.S */
-/* File: arm/op_iput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2572,13 +2345,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget: /* 0x60 */
-/* File: arm/op_sget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2595,13 +2364,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_wide: /* 0x61 */
-/* File: arm/op_sget_wide.S */
-/* File: arm/op_sget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2618,14 +2383,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_object: /* 0x62 */
-/* File: arm/op_sget_object.S */
-/* File: arm/op_sget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2642,14 +2402,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_boolean: /* 0x63 */
-/* File: arm/op_sget_boolean.S */
-/* File: arm/op_sget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2666,14 +2421,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_byte: /* 0x64 */
-/* File: arm/op_sget_byte.S */
-/* File: arm/op_sget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2690,14 +2440,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_char: /* 0x65 */
-/* File: arm/op_sget_char.S */
-/* File: arm/op_sget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2714,14 +2459,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_short: /* 0x66 */
-/* File: arm/op_sget_short.S */
-/* File: arm/op_sget.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2738,13 +2478,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput: /* 0x67 */
-/* File: arm/op_sput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2761,13 +2497,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_wide: /* 0x68 */
-/* File: arm/op_sput_wide.S */
-/* File: arm/op_sput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2784,14 +2516,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_object: /* 0x69 */
-/* File: arm/op_sput_object.S */
-/* File: arm/op_sput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2808,14 +2535,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_boolean: /* 0x6a */
-/* File: arm/op_sput_boolean.S */
-/* File: arm/op_sput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2832,14 +2554,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_byte: /* 0x6b */
-/* File: arm/op_sput_byte.S */
-/* File: arm/op_sput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2856,14 +2573,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_char: /* 0x6c */
-/* File: arm/op_sput_char.S */
-/* File: arm/op_sput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2880,14 +2592,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_short: /* 0x6d */
-/* File: arm/op_sput_short.S */
-/* File: arm/op_sput.S */
-/* File: arm/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2904,13 +2611,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     @ extract opcode from rINST
     GOTO_OPCODE ip                         @ jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual: /* 0x6e */
-/* File: arm/op_invoke_virtual.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2932,7 +2635,6 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
     /*
      * Handle a virtual method call.
      *
@@ -2944,8 +2646,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super: /* 0x6f */
-/* File: arm/op_invoke_super.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2967,7 +2667,6 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
     /*
      * Handle a "super" method call.
      *
@@ -2979,8 +2678,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct: /* 0x70 */
-/* File: arm/op_invoke_direct.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3002,13 +2699,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static: /* 0x71 */
-/* File: arm/op_invoke_static.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3030,14 +2723,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface: /* 0x72 */
-/* File: arm/op_invoke_interface.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3059,7 +2747,6 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
     /*
      * Handle an interface method call.
      *
@@ -3071,7 +2758,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_void_no_barrier: /* 0x73 */
-/* File: arm/op_return_void_no_barrier.S */
     ldr     lr, [rSELF, #THREAD_FLAGS_OFFSET]
     mov     r0, rSELF
     ands    lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
@@ -3083,8 +2769,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range: /* 0x74 */
-/* File: arm/op_invoke_virtual_range.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3106,13 +2790,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super_range: /* 0x75 */
-/* File: arm/op_invoke_super_range.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3134,13 +2814,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct_range: /* 0x76 */
-/* File: arm/op_invoke_direct_range.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3162,13 +2838,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static_range: /* 0x77 */
-/* File: arm/op_invoke_static_range.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3190,13 +2862,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface_range: /* 0x78 */
-/* File: arm/op_invoke_interface_range.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3218,35 +2886,25 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_79: /* 0x79 */
-/* File: arm/op_unused_79.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_7a: /* 0x7a */
-/* File: arm/op_unused_7a.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_int: /* 0x7b */
-/* File: arm/op_neg_int.S */
-/* File: arm/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0".
@@ -3267,12 +2925,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_int: /* 0x7c */
-/* File: arm/op_not_int.S */
-/* File: arm/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0".
@@ -3293,12 +2948,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_long: /* 0x7d */
-/* File: arm/op_neg_long.S */
-/* File: arm/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0/r1".
@@ -3321,12 +2973,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-11 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_long: /* 0x7e */
-/* File: arm/op_not_long.S */
-/* File: arm/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0/r1".
@@ -3349,12 +2998,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-11 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_float: /* 0x7f */
-/* File: arm/op_neg_float.S */
-/* File: arm/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0".
@@ -3375,12 +3021,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_double: /* 0x80 */
-/* File: arm/op_neg_double.S */
-/* File: arm/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0/r1".
@@ -3403,12 +3046,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-11 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_long: /* 0x81 */
-/* File: arm/op_int_to_long.S */
-/* File: arm/unopWider.S */
     /*
      * Generic 32bit-to-64bit unary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = op r0", where
@@ -3430,12 +3070,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 9-10 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_float: /* 0x82 */
-/* File: arm/op_int_to_float.S */
-/* File: arm/funop.S */
     /*
      * Generic 32-bit unary floating-point operation.  Provide an "instr"
      * line that specifies an instruction that performs "s1 = op s0".
@@ -3454,12 +3091,9 @@ artMterpAsmInstructionStart = .L_op_nop
     fsts    s1, [r9]                    @ vA<- s1
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_double: /* 0x83 */
-/* File: arm/op_int_to_double.S */
-/* File: arm/funopWider.S */
     /*
      * Generic 32bit-to-64bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "d0 = op s0".
@@ -3479,13 +3113,10 @@ artMterpAsmInstructionStart = .L_op_nop
     fstd    d0, [r9]                    @ vA<- d0
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_int: /* 0x84 */
-/* File: arm/op_long_to_int.S */
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-/* File: arm/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     mov     r1, rINST, lsr #12          @ r1<- B from 15:12
@@ -3500,12 +3131,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE ip                      @ execute next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_float: /* 0x85 */
-/* File: arm/op_long_to_float.S */
-/* File: arm/unopNarrower.S */
     /*
      * Generic 64bit-to-32bit unary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = op r0/r1", where
@@ -3529,11 +3157,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 9-10 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_double: /* 0x86 */
-/* File: arm/op_long_to_double.S */
     /*
      * Specialised 64-bit floating point operation.
      *
@@ -3564,8 +3190,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_int: /* 0x87 */
-/* File: arm/op_float_to_int.S */
-/* File: arm/funop.S */
     /*
      * Generic 32-bit unary floating-point operation.  Provide an "instr"
      * line that specifies an instruction that performs "s1 = op s0".
@@ -3584,12 +3208,9 @@ constvalop_long_to_double:
     fsts    s1, [r9]                    @ vA<- s1
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_long: /* 0x88 */
-/* File: arm/op_float_to_long.S */
-/* File: arm/unopWider.S */
     /*
      * Generic 32bit-to-64bit unary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = op r0", where
@@ -3611,13 +3232,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 9-10 instructions */
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_double: /* 0x89 */
-/* File: arm/op_float_to_double.S */
-/* File: arm/funopWider.S */
     /*
      * Generic 32bit-to-64bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "d0 = op s0".
@@ -3637,12 +3254,9 @@ constvalop_long_to_double:
     fstd    d0, [r9]                    @ vA<- d0
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_int: /* 0x8a */
-/* File: arm/op_double_to_int.S */
-/* File: arm/funopNarrower.S */
     /*
      * Generic 64bit-to-32bit unary floating point operation.  Provide an
      * "instr" line that specifies an instruction that performs "s0 = op d0".
@@ -3661,12 +3275,9 @@ constvalop_long_to_double:
     fsts    s0, [r9]                    @ vA<- s0
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_long: /* 0x8b */
-/* File: arm/op_double_to_long.S */
-/* File: arm/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0/r1".
@@ -3689,13 +3300,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-11 instructions */
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_float: /* 0x8c */
-/* File: arm/op_double_to_float.S */
-/* File: arm/funopNarrower.S */
     /*
      * Generic 64bit-to-32bit unary floating point operation.  Provide an
      * "instr" line that specifies an instruction that performs "s0 = op d0".
@@ -3714,12 +3321,9 @@ constvalop_long_to_double:
     fsts    s0, [r9]                    @ vA<- s0
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_byte: /* 0x8d */
-/* File: arm/op_int_to_byte.S */
-/* File: arm/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0".
@@ -3740,12 +3344,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_char: /* 0x8e */
-/* File: arm/op_int_to_char.S */
-/* File: arm/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0".
@@ -3766,12 +3367,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_short: /* 0x8f */
-/* File: arm/op_int_to_short.S */
-/* File: arm/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op r0".
@@ -3792,12 +3390,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int: /* 0x90 */
-/* File: arm/op_add_int.S */
-/* File: arm/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0 op r1".
@@ -3833,12 +3428,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int: /* 0x91 */
-/* File: arm/op_sub_int.S */
-/* File: arm/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0 op r1".
@@ -3874,13 +3466,10 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int: /* 0x92 */
-/* File: arm/op_mul_int.S */
 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
-/* File: arm/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0 op r1".
@@ -3916,11 +3505,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int: /* 0x93 */
-/* File: arm/op_div_int.S */
     /*
      * Specialized 32-bit binary operation
      *
@@ -3954,7 +3541,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int: /* 0x94 */
-/* File: arm/op_rem_int.S */
     /*
      * Specialized 32-bit binary operation
      *
@@ -3991,8 +3577,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_and_int: /* 0x95 */
-/* File: arm/op_and_int.S */
-/* File: arm/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0 op r1".
@@ -4028,12 +3612,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int: /* 0x96 */
-/* File: arm/op_or_int.S */
-/* File: arm/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0 op r1".
@@ -4069,12 +3650,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int: /* 0x97 */
-/* File: arm/op_xor_int.S */
-/* File: arm/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0 op r1".
@@ -4110,12 +3688,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int: /* 0x98 */
-/* File: arm/op_shl_int.S */
-/* File: arm/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0 op r1".
@@ -4151,12 +3726,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int: /* 0x99 */
-/* File: arm/op_shr_int.S */
-/* File: arm/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0 op r1".
@@ -4192,12 +3764,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int: /* 0x9a */
-/* File: arm/op_ushr_int.S */
-/* File: arm/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0 op r1".
@@ -4233,12 +3802,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long: /* 0x9b */
-/* File: arm/op_add_long.S */
-/* File: arm/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -4277,12 +3843,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 14-17 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long: /* 0x9c */
-/* File: arm/op_sub_long.S */
-/* File: arm/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -4321,11 +3884,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 14-17 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long: /* 0x9d */
-/* File: arm/op_mul_long.S */
     /*
      * Signed 64-bit integer multiply.
      *
@@ -4367,8 +3928,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_div_long: /* 0x9e */
-/* File: arm/op_div_long.S */
-/* File: arm/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -4407,13 +3966,10 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 14-17 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long: /* 0x9f */
-/* File: arm/op_rem_long.S */
 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
-/* File: arm/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -4452,12 +4008,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 14-17 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long: /* 0xa0 */
-/* File: arm/op_and_long.S */
-/* File: arm/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -4496,12 +4049,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 14-17 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long: /* 0xa1 */
-/* File: arm/op_or_long.S */
-/* File: arm/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -4540,12 +4090,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 14-17 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long: /* 0xa2 */
-/* File: arm/op_xor_long.S */
-/* File: arm/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -4584,11 +4131,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 14-17 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long: /* 0xa3 */
-/* File: arm/op_shl_long.S */
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -4620,7 +4165,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long: /* 0xa4 */
-/* File: arm/op_shr_long.S */
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -4652,7 +4196,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long: /* 0xa5 */
-/* File: arm/op_ushr_long.S */
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -4684,8 +4227,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_add_float: /* 0xa6 */
-/* File: arm/op_add_float.S */
-/* File: arm/fbinop.S */
     /*
      * Generic 32-bit floating-point operation.  Provide an "instr" line that
      * specifies an instruction that performs "s2 = s0 op s1".  Because we
@@ -4710,12 +4251,9 @@ constvalop_long_to_double:
     fsts    s2, [r9]                    @ vAA<- s2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float: /* 0xa7 */
-/* File: arm/op_sub_float.S */
-/* File: arm/fbinop.S */
     /*
      * Generic 32-bit floating-point operation.  Provide an "instr" line that
      * specifies an instruction that performs "s2 = s0 op s1".  Because we
@@ -4740,12 +4278,9 @@ constvalop_long_to_double:
     fsts    s2, [r9]                    @ vAA<- s2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float: /* 0xa8 */
-/* File: arm/op_mul_float.S */
-/* File: arm/fbinop.S */
     /*
      * Generic 32-bit floating-point operation.  Provide an "instr" line that
      * specifies an instruction that performs "s2 = s0 op s1".  Because we
@@ -4770,12 +4305,9 @@ constvalop_long_to_double:
     fsts    s2, [r9]                    @ vAA<- s2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float: /* 0xa9 */
-/* File: arm/op_div_float.S */
-/* File: arm/fbinop.S */
     /*
      * Generic 32-bit floating-point operation.  Provide an "instr" line that
      * specifies an instruction that performs "s2 = s0 op s1".  Because we
@@ -4800,13 +4332,10 @@ constvalop_long_to_double:
     fsts    s2, [r9]                    @ vAA<- s2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float: /* 0xaa */
-/* File: arm/op_rem_float.S */
 /* EABI doesn't define a float remainder function, but libm does */
-/* File: arm/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0 op r1".
@@ -4842,12 +4371,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_double: /* 0xab */
-/* File: arm/op_add_double.S */
-/* File: arm/fbinopWide.S */
     /*
      * Generic 64-bit double-precision floating point binary operation.
      * Provide an "instr" line that specifies an instruction that performs
@@ -4872,12 +4398,9 @@ constvalop_long_to_double:
     fstd    d2, [r9]                    @ vAA<- d2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double: /* 0xac */
-/* File: arm/op_sub_double.S */
-/* File: arm/fbinopWide.S */
     /*
      * Generic 64-bit double-precision floating point binary operation.
      * Provide an "instr" line that specifies an instruction that performs
@@ -4902,12 +4425,9 @@ constvalop_long_to_double:
     fstd    d2, [r9]                    @ vAA<- d2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double: /* 0xad */
-/* File: arm/op_mul_double.S */
-/* File: arm/fbinopWide.S */
     /*
      * Generic 64-bit double-precision floating point binary operation.
      * Provide an "instr" line that specifies an instruction that performs
@@ -4932,12 +4452,9 @@ constvalop_long_to_double:
     fstd    d2, [r9]                    @ vAA<- d2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double: /* 0xae */
-/* File: arm/op_div_double.S */
-/* File: arm/fbinopWide.S */
     /*
      * Generic 64-bit double-precision floating point binary operation.
      * Provide an "instr" line that specifies an instruction that performs
@@ -4962,13 +4479,10 @@ constvalop_long_to_double:
     fstd    d2, [r9]                    @ vAA<- d2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double: /* 0xaf */
-/* File: arm/op_rem_double.S */
 /* EABI doesn't define a double remainder function, but libm does */
-/* File: arm/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -5007,12 +4521,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 14-17 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_2addr: /* 0xb0 */
-/* File: arm/op_add_int_2addr.S */
-/* File: arm/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -5045,12 +4556,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int_2addr: /* 0xb1 */
-/* File: arm/op_sub_int_2addr.S */
-/* File: arm/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -5083,13 +4591,10 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_2addr: /* 0xb2 */
-/* File: arm/op_mul_int_2addr.S */
 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
-/* File: arm/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -5122,11 +4627,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_2addr: /* 0xb3 */
-/* File: arm/op_div_int_2addr.S */
     /*
      * Specialized 32-bit binary operation
      *
@@ -5155,11 +4658,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_2addr: /* 0xb4 */
-/* File: arm/op_rem_int_2addr.S */
     /*
      * Specialized 32-bit binary operation
      *
@@ -5191,12 +4692,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_2addr: /* 0xb5 */
-/* File: arm/op_and_int_2addr.S */
-/* File: arm/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -5229,12 +4727,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_2addr: /* 0xb6 */
-/* File: arm/op_or_int_2addr.S */
-/* File: arm/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -5267,12 +4762,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_2addr: /* 0xb7 */
-/* File: arm/op_xor_int_2addr.S */
-/* File: arm/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -5305,12 +4797,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_2addr: /* 0xb8 */
-/* File: arm/op_shl_int_2addr.S */
-/* File: arm/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -5343,12 +4832,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_2addr: /* 0xb9 */
-/* File: arm/op_shr_int_2addr.S */
-/* File: arm/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -5381,12 +4867,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_2addr: /* 0xba */
-/* File: arm/op_ushr_int_2addr.S */
-/* File: arm/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -5419,12 +4902,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long_2addr: /* 0xbb */
-/* File: arm/op_add_long_2addr.S */
-/* File: arm/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -5459,12 +4939,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 12-15 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long_2addr: /* 0xbc */
-/* File: arm/op_sub_long_2addr.S */
-/* File: arm/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -5499,11 +4976,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 12-15 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long_2addr: /* 0xbd */
-/* File: arm/op_mul_long_2addr.S */
     /*
      * Signed 64-bit integer multiply, "/2addr" version.
      *
@@ -5532,8 +5007,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_div_long_2addr: /* 0xbe */
-/* File: arm/op_div_long_2addr.S */
-/* File: arm/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -5568,13 +5041,10 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 12-15 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long_2addr: /* 0xbf */
-/* File: arm/op_rem_long_2addr.S */
 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
-/* File: arm/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -5609,12 +5079,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 12-15 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long_2addr: /* 0xc0 */
-/* File: arm/op_and_long_2addr.S */
-/* File: arm/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -5649,12 +5116,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 12-15 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long_2addr: /* 0xc1 */
-/* File: arm/op_or_long_2addr.S */
-/* File: arm/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -5689,12 +5153,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 12-15 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long_2addr: /* 0xc2 */
-/* File: arm/op_xor_long_2addr.S */
-/* File: arm/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -5729,11 +5190,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 12-15 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long_2addr: /* 0xc3 */
-/* File: arm/op_shl_long_2addr.S */
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
@@ -5760,7 +5219,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long_2addr: /* 0xc4 */
-/* File: arm/op_shr_long_2addr.S */
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
@@ -5787,7 +5245,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long_2addr: /* 0xc5 */
-/* File: arm/op_ushr_long_2addr.S */
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
@@ -5814,8 +5271,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_add_float_2addr: /* 0xc6 */
-/* File: arm/op_add_float_2addr.S */
-/* File: arm/fbinop2addr.S */
     /*
      * Generic 32-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -5836,12 +5291,9 @@ constvalop_long_to_double:
     fsts    s2, [r9]                    @ vAA<- s2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float_2addr: /* 0xc7 */
-/* File: arm/op_sub_float_2addr.S */
-/* File: arm/fbinop2addr.S */
     /*
      * Generic 32-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -5862,12 +5314,9 @@ constvalop_long_to_double:
     fsts    s2, [r9]                    @ vAA<- s2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float_2addr: /* 0xc8 */
-/* File: arm/op_mul_float_2addr.S */
-/* File: arm/fbinop2addr.S */
     /*
      * Generic 32-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -5888,12 +5337,9 @@ constvalop_long_to_double:
     fsts    s2, [r9]                    @ vAA<- s2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float_2addr: /* 0xc9 */
-/* File: arm/op_div_float_2addr.S */
-/* File: arm/fbinop2addr.S */
     /*
      * Generic 32-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -5914,13 +5360,10 @@ constvalop_long_to_double:
     fsts    s2, [r9]                    @ vAA<- s2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float_2addr: /* 0xca */
-/* File: arm/op_rem_float_2addr.S */
 /* EABI doesn't define a float remainder function, but libm does */
-/* File: arm/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -5953,12 +5396,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_double_2addr: /* 0xcb */
-/* File: arm/op_add_double_2addr.S */
-/* File: arm/fbinopWide2addr.S */
     /*
      * Generic 64-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -5981,12 +5421,9 @@ constvalop_long_to_double:
     fstd    d2, [r9]                    @ vAA<- d2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double_2addr: /* 0xcc */
-/* File: arm/op_sub_double_2addr.S */
-/* File: arm/fbinopWide2addr.S */
     /*
      * Generic 64-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -6009,12 +5446,9 @@ constvalop_long_to_double:
     fstd    d2, [r9]                    @ vAA<- d2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double_2addr: /* 0xcd */
-/* File: arm/op_mul_double_2addr.S */
-/* File: arm/fbinopWide2addr.S */
     /*
      * Generic 64-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -6037,12 +5471,9 @@ constvalop_long_to_double:
     fstd    d2, [r9]                    @ vAA<- d2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double_2addr: /* 0xce */
-/* File: arm/op_div_double_2addr.S */
-/* File: arm/fbinopWide2addr.S */
     /*
      * Generic 64-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -6065,13 +5496,10 @@ constvalop_long_to_double:
     fstd    d2, [r9]                    @ vAA<- d2
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double_2addr: /* 0xcf */
-/* File: arm/op_rem_double_2addr.S */
 /* EABI doesn't define a double remainder function, but libm does */
-/* File: arm/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0-r1 op r2-r3".
@@ -6106,12 +5534,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 12-15 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit16: /* 0xd0 */
-/* File: arm/op_add_int_lit16.S */
-/* File: arm/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6141,13 +5566,10 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int: /* 0xd1 */
-/* File: arm/op_rsub_int.S */
 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
-/* File: arm/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6177,13 +5599,10 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit16: /* 0xd2 */
-/* File: arm/op_mul_int_lit16.S */
 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
-/* File: arm/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6213,11 +5632,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit16: /* 0xd3 */
-/* File: arm/op_div_int_lit16.S */
     /*
      * Specialized 32-bit binary operation
      *
@@ -6249,7 +5666,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit16: /* 0xd4 */
-/* File: arm/op_rem_int_lit16.S */
     /*
      * Specialized 32-bit binary operation
      *
@@ -6284,8 +5700,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit16: /* 0xd5 */
-/* File: arm/op_and_int_lit16.S */
-/* File: arm/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6315,12 +5729,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit16: /* 0xd6 */
-/* File: arm/op_or_int_lit16.S */
-/* File: arm/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6350,12 +5761,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit16: /* 0xd7 */
-/* File: arm/op_xor_int_lit16.S */
-/* File: arm/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6385,12 +5793,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit8: /* 0xd8 */
-/* File: arm/op_add_int_lit8.S */
-/* File: arm/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6426,12 +5831,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int_lit8: /* 0xd9 */
-/* File: arm/op_rsub_int_lit8.S */
-/* File: arm/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6467,13 +5869,10 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit8: /* 0xda */
-/* File: arm/op_mul_int_lit8.S */
 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
-/* File: arm/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6509,11 +5908,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit8: /* 0xdb */
-/* File: arm/op_div_int_lit8.S */
     /*
      * Specialized 32-bit binary operation
      *
@@ -6546,7 +5943,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit8: /* 0xdc */
-/* File: arm/op_rem_int_lit8.S */
     /*
      * Specialized 32-bit binary operation
      *
@@ -6582,8 +5978,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit8: /* 0xdd */
-/* File: arm/op_and_int_lit8.S */
-/* File: arm/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6619,12 +6013,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit8: /* 0xde */
-/* File: arm/op_or_int_lit8.S */
-/* File: arm/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6660,12 +6051,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit8: /* 0xdf */
-/* File: arm/op_xor_int_lit8.S */
-/* File: arm/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6701,12 +6089,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_lit8: /* 0xe0 */
-/* File: arm/op_shl_int_lit8.S */
-/* File: arm/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6742,12 +6127,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_lit8: /* 0xe1 */
-/* File: arm/op_shr_int_lit8.S */
-/* File: arm/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6783,12 +6165,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_lit8: /* 0xe2 */
-/* File: arm/op_ushr_int_lit8.S */
-/* File: arm/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = r0 op r1".
@@ -6824,11 +6203,9 @@ constvalop_long_to_double:
     GOTO_OPCODE ip                      @ jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_quick: /* 0xe3 */
-/* File: arm/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
@@ -6846,7 +6223,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide_quick: /* 0xe4 */
-/* File: arm/op_iget_wide_quick.S */
     /* iget-wide-quick vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
     FETCH ip, 1                         @ ip<- field byte offset
@@ -6865,7 +6241,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object_quick: /* 0xe5 */
-/* File: arm/op_iget_object_quick.S */
     /* For: iget-object-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
@@ -6886,7 +6261,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_iput_quick: /* 0xe6 */
-/* File: arm/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
@@ -6904,7 +6278,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide_quick: /* 0xe7 */
-/* File: arm/op_iput_wide_quick.S */
     /* iput-wide-quick vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
     FETCH r3, 1                         @ r3<- field byte offset
@@ -6922,7 +6295,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object_quick: /* 0xe8 */
-/* File: arm/op_iput_object_quick.S */
     EXPORT_PC
     add     r0, rFP, #OFF_FP_SHADOWFRAME
     mov     r1, rPC
@@ -6937,8 +6309,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_quick: /* 0xe9 */
-/* File: arm/op_invoke_virtual_quick.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -6960,13 +6330,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range_quick: /* 0xea */
-/* File: arm/op_invoke_virtual_range_quick.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -6988,13 +6354,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean_quick: /* 0xeb */
-/* File: arm/op_iput_boolean_quick.S */
-/* File: arm/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
@@ -7009,12 +6371,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte_quick: /* 0xec */
-/* File: arm/op_iput_byte_quick.S */
-/* File: arm/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
@@ -7029,12 +6388,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char_quick: /* 0xed */
-/* File: arm/op_iput_char_quick.S */
-/* File: arm/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
@@ -7049,12 +6405,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short_quick: /* 0xee */
-/* File: arm/op_iput_short_quick.S */
-/* File: arm/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
@@ -7069,12 +6422,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean_quick: /* 0xef */
-/* File: arm/op_iget_boolean_quick.S */
-/* File: arm/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
@@ -7089,12 +6439,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte_quick: /* 0xf0 */
-/* File: arm/op_iget_byte_quick.S */
-/* File: arm/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
@@ -7109,12 +6456,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char_quick: /* 0xf1 */
-/* File: arm/op_iget_char_quick.S */
-/* File: arm/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
@@ -7129,12 +6473,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short_quick: /* 0xf2 */
-/* File: arm/op_iget_short_quick.S */
-/* File: arm/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     mov     r2, rINST, lsr #12          @ r2<- B
@@ -7149,89 +6490,65 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f3: /* 0xf3 */
-/* File: arm/op_unused_f3.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f4: /* 0xf4 */
-/* File: arm/op_unused_f4.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f5: /* 0xf5 */
-/* File: arm/op_unused_f5.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f6: /* 0xf6 */
-/* File: arm/op_unused_f6.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f7: /* 0xf7 */
-/* File: arm/op_unused_f7.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f8: /* 0xf8 */
-/* File: arm/op_unused_f8.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f9: /* 0xf9 */
-/* File: arm/op_unused_f9.S */
-/* File: arm/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic: /* 0xfa */
-/* File: arm/op_invoke_polymorphic.S */
-/* File: arm/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -7253,12 +6570,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic_range: /* 0xfb */
-/* File: arm/op_invoke_polymorphic_range.S */
-/* File: arm/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -7280,12 +6594,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom: /* 0xfc */
-/* File: arm/op_invoke_custom.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -7307,7 +6618,6 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
     /*
      * Handle an invoke-custom invocation.
      *
@@ -7319,8 +6629,6 @@ constvalop_long_to_double:
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom_range: /* 0xfd */
-/* File: arm/op_invoke_custom_range.S */
-/* File: arm/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -7342,13 +6650,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_handle: /* 0xfe */
-/* File: arm/op_const_method_handle.S */
-/* File: arm/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -7367,12 +6671,9 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_type: /* 0xff */
-/* File: arm/op_const_method_type.S */
-/* File: arm/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -7391,32 +6692,19 @@ constvalop_long_to_double:
     GET_INST_OPCODE ip                  @ extract opcode from rINST
     GOTO_OPCODE ip                      @ jump to next instruction
 
-
     .balign 128
-/* File: arm/instruction_end.S */
 
     .type artMterpAsmInstructionEnd, #object
     .hidden artMterpAsmInstructionEnd
     .global artMterpAsmInstructionEnd
 artMterpAsmInstructionEnd:
 
-
-/*
- * ===========================================================================
- *  Sister implementations
- * ===========================================================================
- */
-/* File: arm/instruction_start_sister.S */
-
     .type artMterpAsmSisterStart, #object
     .hidden artMterpAsmSisterStart
     .global artMterpAsmSisterStart
     .text
     .balign 4
 artMterpAsmSisterStart:
-
-
-/* continuation for op_float_to_long */
 /*
  * Convert the float in r0 to a long in r0/r1.
  *
@@ -7445,8 +6733,6 @@ f2l_maybeNaN:
     mov     r0, #0
     mov     r1, #0
     bx      lr                          @ return 0 for NaN
-
-/* continuation for op_double_to_long */
 /*
  * Convert the double in r0/r1 to a long in r0/r1.
  *
@@ -7477,25 +6763,20 @@ d2l_maybeNaN:
     mov     r0, #0
     mov     r1, #0
     bx      lr                          @ return 0 for NaN
-/* File: arm/instruction_end_sister.S */
 
     .type artMterpAsmSisterEnd, #object
     .hidden artMterpAsmSisterEnd
     .global artMterpAsmSisterEnd
 artMterpAsmSisterEnd:
 
-/* File: arm/instruction_start_alt.S */
-
     .type artMterpAsmAltInstructionStart, #object
     .hidden artMterpAsmAltInstructionStart
     .global artMterpAsmAltInstructionStart
 artMterpAsmAltInstructionStart = .L_ALT_op_nop
     .text
-
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_nop: /* 0x00 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7513,7 +6794,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move: /* 0x01 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7531,7 +6811,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_from16: /* 0x02 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7549,7 +6828,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_16: /* 0x03 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7567,7 +6845,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide: /* 0x04 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7585,7 +6862,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_from16: /* 0x05 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7603,7 +6879,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_16: /* 0x06 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7621,7 +6896,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object: /* 0x07 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7639,7 +6913,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_from16: /* 0x08 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7657,7 +6930,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_16: /* 0x09 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7675,7 +6947,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result: /* 0x0a */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7693,7 +6964,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_wide: /* 0x0b */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7711,7 +6981,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_object: /* 0x0c */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7729,7 +6998,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_exception: /* 0x0d */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7747,7 +7015,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void: /* 0x0e */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7765,7 +7032,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return: /* 0x0f */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7783,7 +7049,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_wide: /* 0x10 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7801,7 +7066,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_object: /* 0x11 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7819,7 +7083,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_4: /* 0x12 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7837,7 +7100,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_16: /* 0x13 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7855,7 +7117,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const: /* 0x14 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7873,7 +7134,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_high16: /* 0x15 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7891,7 +7151,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_16: /* 0x16 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7909,7 +7168,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_32: /* 0x17 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7927,7 +7185,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide: /* 0x18 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7945,7 +7202,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_high16: /* 0x19 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7963,7 +7219,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string: /* 0x1a */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7981,7 +7236,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string_jumbo: /* 0x1b */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7999,7 +7253,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_class: /* 0x1c */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8017,7 +7270,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_enter: /* 0x1d */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8035,7 +7287,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_exit: /* 0x1e */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8053,7 +7304,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_check_cast: /* 0x1f */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8071,7 +7321,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_instance_of: /* 0x20 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8089,7 +7338,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_array_length: /* 0x21 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8107,7 +7355,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_instance: /* 0x22 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8125,7 +7372,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_array: /* 0x23 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8143,7 +7389,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array: /* 0x24 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8161,7 +7406,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array_range: /* 0x25 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8179,7 +7423,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_fill_array_data: /* 0x26 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8197,7 +7440,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_throw: /* 0x27 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8215,7 +7457,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto: /* 0x28 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8233,7 +7474,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_16: /* 0x29 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8251,7 +7491,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_32: /* 0x2a */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8269,7 +7508,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_packed_switch: /* 0x2b */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8287,7 +7525,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sparse_switch: /* 0x2c */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8305,7 +7542,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_float: /* 0x2d */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8323,7 +7559,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_float: /* 0x2e */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8341,7 +7576,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_double: /* 0x2f */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8359,7 +7593,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_double: /* 0x30 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8377,7 +7610,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmp_long: /* 0x31 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8395,7 +7627,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eq: /* 0x32 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8413,7 +7644,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ne: /* 0x33 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8431,7 +7661,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lt: /* 0x34 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8449,7 +7678,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ge: /* 0x35 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8467,7 +7695,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gt: /* 0x36 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8485,7 +7712,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_le: /* 0x37 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8503,7 +7729,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eqz: /* 0x38 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8521,7 +7746,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_nez: /* 0x39 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8539,7 +7763,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ltz: /* 0x3a */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8557,7 +7780,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gez: /* 0x3b */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8575,7 +7797,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gtz: /* 0x3c */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8593,7 +7814,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lez: /* 0x3d */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8611,7 +7831,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3e: /* 0x3e */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8629,7 +7848,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3f: /* 0x3f */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8647,7 +7865,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_40: /* 0x40 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8665,7 +7882,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_41: /* 0x41 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8683,7 +7899,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_42: /* 0x42 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8701,7 +7916,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_43: /* 0x43 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8719,7 +7933,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget: /* 0x44 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8737,7 +7950,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_wide: /* 0x45 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8755,7 +7967,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_object: /* 0x46 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8773,7 +7984,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_boolean: /* 0x47 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8791,7 +8001,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_byte: /* 0x48 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8809,7 +8018,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_char: /* 0x49 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8827,7 +8035,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_short: /* 0x4a */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8845,7 +8052,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput: /* 0x4b */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8863,7 +8069,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_wide: /* 0x4c */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8881,7 +8086,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_object: /* 0x4d */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8899,7 +8103,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_boolean: /* 0x4e */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8917,7 +8120,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_byte: /* 0x4f */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8935,7 +8137,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_char: /* 0x50 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8953,7 +8154,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_short: /* 0x51 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8971,7 +8171,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget: /* 0x52 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8989,7 +8188,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide: /* 0x53 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9007,7 +8205,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object: /* 0x54 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9025,7 +8222,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean: /* 0x55 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9043,7 +8239,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte: /* 0x56 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9061,7 +8256,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char: /* 0x57 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9079,7 +8273,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short: /* 0x58 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9097,7 +8290,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput: /* 0x59 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9115,7 +8307,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide: /* 0x5a */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9133,7 +8324,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object: /* 0x5b */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9151,7 +8341,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean: /* 0x5c */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9169,7 +8358,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte: /* 0x5d */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9187,7 +8375,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char: /* 0x5e */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9205,7 +8392,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short: /* 0x5f */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9223,7 +8409,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget: /* 0x60 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9241,7 +8426,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_wide: /* 0x61 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9259,7 +8443,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_object: /* 0x62 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9277,7 +8460,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_boolean: /* 0x63 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9295,7 +8477,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_byte: /* 0x64 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9313,7 +8494,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_char: /* 0x65 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9331,7 +8511,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_short: /* 0x66 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9349,7 +8528,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput: /* 0x67 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9367,7 +8545,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_wide: /* 0x68 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9385,7 +8562,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_object: /* 0x69 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9403,7 +8579,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_boolean: /* 0x6a */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9421,7 +8596,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_byte: /* 0x6b */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9439,7 +8613,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_char: /* 0x6c */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9457,7 +8630,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_short: /* 0x6d */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9475,7 +8647,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual: /* 0x6e */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9493,7 +8664,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super: /* 0x6f */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9511,7 +8681,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct: /* 0x70 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9529,7 +8698,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static: /* 0x71 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9547,7 +8715,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface: /* 0x72 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9565,7 +8732,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void_no_barrier: /* 0x73 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9583,7 +8749,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range: /* 0x74 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9601,7 +8766,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super_range: /* 0x75 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9619,7 +8783,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct_range: /* 0x76 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9637,7 +8800,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static_range: /* 0x77 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9655,7 +8817,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface_range: /* 0x78 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9673,7 +8834,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_79: /* 0x79 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9691,7 +8851,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_7a: /* 0x7a */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9709,7 +8868,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_int: /* 0x7b */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9727,7 +8885,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_int: /* 0x7c */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9745,7 +8902,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_long: /* 0x7d */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9763,7 +8919,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_long: /* 0x7e */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9781,7 +8936,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_float: /* 0x7f */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9799,7 +8953,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_double: /* 0x80 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9817,7 +8970,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_long: /* 0x81 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9835,7 +8987,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_float: /* 0x82 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9853,7 +9004,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_double: /* 0x83 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9871,7 +9021,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_int: /* 0x84 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9889,7 +9038,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_float: /* 0x85 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9907,7 +9055,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_double: /* 0x86 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9925,7 +9072,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_int: /* 0x87 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9943,7 +9089,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_long: /* 0x88 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9961,7 +9106,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_double: /* 0x89 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9979,7 +9123,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_int: /* 0x8a */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9997,7 +9140,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_long: /* 0x8b */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10015,7 +9157,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_float: /* 0x8c */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10033,7 +9174,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_byte: /* 0x8d */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10051,7 +9191,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_char: /* 0x8e */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10069,7 +9208,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_short: /* 0x8f */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10087,7 +9225,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int: /* 0x90 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10105,7 +9242,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int: /* 0x91 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10123,7 +9259,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int: /* 0x92 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10141,7 +9276,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int: /* 0x93 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10159,7 +9293,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int: /* 0x94 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10177,7 +9310,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int: /* 0x95 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10195,7 +9327,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int: /* 0x96 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10213,7 +9344,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int: /* 0x97 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10231,7 +9361,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int: /* 0x98 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10249,7 +9378,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int: /* 0x99 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10267,7 +9395,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int: /* 0x9a */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10285,7 +9412,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long: /* 0x9b */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10303,7 +9429,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long: /* 0x9c */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10321,7 +9446,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long: /* 0x9d */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10339,7 +9463,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long: /* 0x9e */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10357,7 +9480,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long: /* 0x9f */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10375,7 +9497,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long: /* 0xa0 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10393,7 +9514,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long: /* 0xa1 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10411,7 +9531,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long: /* 0xa2 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10429,7 +9548,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long: /* 0xa3 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10447,7 +9565,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long: /* 0xa4 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10465,7 +9582,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long: /* 0xa5 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10483,7 +9599,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float: /* 0xa6 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10501,7 +9616,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float: /* 0xa7 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10519,7 +9633,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float: /* 0xa8 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10537,7 +9650,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float: /* 0xa9 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10555,7 +9667,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float: /* 0xaa */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10573,7 +9684,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double: /* 0xab */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10591,7 +9701,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double: /* 0xac */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10609,7 +9718,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double: /* 0xad */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10627,7 +9735,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double: /* 0xae */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10645,7 +9752,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double: /* 0xaf */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10663,7 +9769,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_2addr: /* 0xb0 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10681,7 +9786,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int_2addr: /* 0xb1 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10699,7 +9803,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_2addr: /* 0xb2 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10717,7 +9820,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_2addr: /* 0xb3 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10735,7 +9837,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_2addr: /* 0xb4 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10753,7 +9854,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_2addr: /* 0xb5 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10771,7 +9871,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_2addr: /* 0xb6 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10789,7 +9888,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_2addr: /* 0xb7 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10807,7 +9905,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_2addr: /* 0xb8 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10825,7 +9922,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_2addr: /* 0xb9 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10843,7 +9939,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_2addr: /* 0xba */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10861,7 +9956,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long_2addr: /* 0xbb */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10879,7 +9973,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long_2addr: /* 0xbc */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10897,7 +9990,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long_2addr: /* 0xbd */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10915,7 +10007,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long_2addr: /* 0xbe */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10933,7 +10024,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long_2addr: /* 0xbf */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10951,7 +10041,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long_2addr: /* 0xc0 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10969,7 +10058,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long_2addr: /* 0xc1 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10987,7 +10075,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long_2addr: /* 0xc2 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11005,7 +10092,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long_2addr: /* 0xc3 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11023,7 +10109,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long_2addr: /* 0xc4 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11041,7 +10126,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long_2addr: /* 0xc5 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11059,7 +10143,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float_2addr: /* 0xc6 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11077,7 +10160,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float_2addr: /* 0xc7 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11095,7 +10177,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float_2addr: /* 0xc8 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11113,7 +10194,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float_2addr: /* 0xc9 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11131,7 +10211,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float_2addr: /* 0xca */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11149,7 +10228,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double_2addr: /* 0xcb */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11167,7 +10245,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double_2addr: /* 0xcc */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11185,7 +10262,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double_2addr: /* 0xcd */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11203,7 +10279,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double_2addr: /* 0xce */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11221,7 +10296,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double_2addr: /* 0xcf */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11239,7 +10313,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit16: /* 0xd0 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11257,7 +10330,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int: /* 0xd1 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11275,7 +10347,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit16: /* 0xd2 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11293,7 +10364,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit16: /* 0xd3 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11311,7 +10381,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit16: /* 0xd4 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11329,7 +10398,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit16: /* 0xd5 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11347,7 +10415,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit16: /* 0xd6 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11365,7 +10432,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit16: /* 0xd7 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11383,7 +10449,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit8: /* 0xd8 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11401,7 +10466,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int_lit8: /* 0xd9 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11419,7 +10483,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit8: /* 0xda */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11437,7 +10500,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit8: /* 0xdb */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11455,7 +10517,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit8: /* 0xdc */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11473,7 +10534,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit8: /* 0xdd */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11491,7 +10551,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit8: /* 0xde */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11509,7 +10568,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit8: /* 0xdf */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11527,7 +10585,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_lit8: /* 0xe0 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11545,7 +10602,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_lit8: /* 0xe1 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11563,7 +10619,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_lit8: /* 0xe2 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11581,7 +10636,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_quick: /* 0xe3 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11599,7 +10653,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide_quick: /* 0xe4 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11617,7 +10670,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object_quick: /* 0xe5 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11635,7 +10687,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_quick: /* 0xe6 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11653,7 +10704,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide_quick: /* 0xe7 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11671,7 +10721,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object_quick: /* 0xe8 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11689,7 +10738,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11707,7 +10755,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11725,7 +10772,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean_quick: /* 0xeb */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11743,7 +10789,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte_quick: /* 0xec */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11761,7 +10806,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char_quick: /* 0xed */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11779,7 +10823,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short_quick: /* 0xee */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11797,7 +10840,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean_quick: /* 0xef */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11815,7 +10857,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte_quick: /* 0xf0 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11833,7 +10874,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char_quick: /* 0xf1 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11851,7 +10891,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short_quick: /* 0xf2 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11869,7 +10908,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f3: /* 0xf3 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11887,7 +10925,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f4: /* 0xf4 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11905,7 +10942,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f5: /* 0xf5 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11923,7 +10959,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f6: /* 0xf6 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11941,7 +10976,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f7: /* 0xf7 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11959,7 +10993,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f8: /* 0xf8 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11977,7 +11010,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f9: /* 0xf9 */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11995,7 +11027,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic: /* 0xfa */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12013,7 +11044,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12031,7 +11061,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom: /* 0xfc */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12049,7 +11078,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom_range: /* 0xfd */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12067,7 +11095,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_handle: /* 0xfe */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12085,7 +11112,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_type: /* 0xff */
-/* File: arm/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12101,14 +11127,11 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
     b      MterpCheckBefore     @ (self, shadow_frame, dex_pc_ptr)  @ Tail call.
 
     .balign 128
-/* File: arm/instruction_end_alt.S */
 
     .type artMterpAsmAltInstructionEnd, #object
     .hidden artMterpAsmAltInstructionEnd
     .global artMterpAsmAltInstructionEnd
 artMterpAsmAltInstructionEnd:
-
-/* File: arm/footer.S */
 /*
  * ===========================================================================
  *  Common subroutines and data
@@ -12406,4 +11429,3 @@ MterpProfileActive:
 
     END ExecuteMterpImpl
 
-
diff --git a/runtime/interpreter/mterp/out/mterp_arm64.S b/runtime/interpreter/mterp/out/mterp_arm64.S
index fd60c95a373cddd6cba58c62df96f24d3423dfb0..c8c9cdb0fe9f2036c5d36fd2e19d6abe78d91cc9 100644
--- a/runtime/interpreter/mterp/out/mterp_arm64.S
+++ b/runtime/interpreter/mterp/out/mterp_arm64.S
@@ -1,10 +1,4 @@
-/*
- * This file was generated automatically by gen-mterp.py for 'arm64'.
- *
- * --> DO NOT EDIT <--
- */
-
-/* File: arm64/header.S */
+/* DO NOT EDIT: This file was generated by gen-mterp.py. */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -358,8 +352,6 @@ codes.
     .cfi_endproc
     .size \name, .-\name
 .endm
-
-/* File: arm64/entry.S */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -427,18 +419,14 @@ ENTRY ExecuteMterpImpl
     GOTO_OPCODE ip                      // jump to next instruction
     /* NOTE: no fallthrough */
 
-/* File: arm64/instruction_start.S */
-
     .type artMterpAsmInstructionStart, #object
     .hidden artMterpAsmInstructionStart
     .global artMterpAsmInstructionStart
 artMterpAsmInstructionStart = .L_op_nop
     .text
-
 /* ------------------------------ */
     .balign 128
 .L_op_nop: /* 0x00 */
-/* File: arm64/op_nop.S */
     FETCH_ADVANCE_INST 1                // advance to next instr, load rINST
     GET_INST_OPCODE ip                  // ip<- opcode from rINST
     GOTO_OPCODE ip                      // execute it
@@ -446,7 +434,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move: /* 0x01 */
-/* File: arm64/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     lsr     w1, wINST, #12              // x1<- B from 15:12
@@ -464,7 +451,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_from16: /* 0x02 */
-/* File: arm64/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     FETCH w1, 1                         // r1<- BBBB
@@ -482,7 +468,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_16: /* 0x03 */
-/* File: arm64/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     FETCH w1, 2                         // w1<- BBBB
@@ -500,7 +485,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide: /* 0x04 */
-/* File: arm64/op_move_wide.S */
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     lsr     w3, wINST, #12              // w3<- B
@@ -514,7 +498,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_from16: /* 0x05 */
-/* File: arm64/op_move_wide_from16.S */
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     FETCH w3, 1                         // w3<- BBBB
@@ -528,7 +511,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_16: /* 0x06 */
-/* File: arm64/op_move_wide_16.S */
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     FETCH w3, 2                         // w3<- BBBB
@@ -542,8 +524,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_object: /* 0x07 */
-/* File: arm64/op_move_object.S */
-/* File: arm64/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     lsr     w1, wINST, #12              // x1<- B from 15:12
@@ -558,12 +538,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE ip                      // execute next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_from16: /* 0x08 */
-/* File: arm64/op_move_object_from16.S */
-/* File: arm64/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     FETCH w1, 1                         // r1<- BBBB
@@ -578,12 +555,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_16: /* 0x09 */
-/* File: arm64/op_move_object_16.S */
-/* File: arm64/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     FETCH w1, 2                         // w1<- BBBB
@@ -598,11 +572,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_result: /* 0x0a */
-/* File: arm64/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     lsr     w2, wINST, #8               // r2<- AA
@@ -620,7 +592,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_wide: /* 0x0b */
-/* File: arm64/op_move_result_wide.S */
     /* for: move-result-wide */
     /* op vAA */
     lsr     w2, wINST, #8               // r2<- AA
@@ -634,8 +605,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_object: /* 0x0c */
-/* File: arm64/op_move_result_object.S */
-/* File: arm64/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     lsr     w2, wINST, #8               // r2<- AA
@@ -650,11 +619,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_exception: /* 0x0d */
-/* File: arm64/op_move_exception.S */
     /* move-exception vAA */
     lsr     w2, wINST, #8               // w2<- AA
     ldr     x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
@@ -668,7 +635,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_void: /* 0x0e */
-/* File: arm64/op_return_void.S */
     .extern MterpThreadFenceForConstructor
     bl      MterpThreadFenceForConstructor
     ldr     w7, [xSELF, #THREAD_FLAGS_OFFSET]
@@ -685,7 +651,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return: /* 0x0f */
-/* File: arm64/op_return.S */
     /*
      * Return a 32-bit value.
      *
@@ -709,7 +674,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_wide: /* 0x10 */
-/* File: arm64/op_return_wide.S */
     /*
      * Return a 64-bit value.
      */
@@ -732,8 +696,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_object: /* 0x11 */
-/* File: arm64/op_return_object.S */
-/* File: arm64/op_return.S */
     /*
      * Return a 32-bit value.
      *
@@ -754,11 +716,9 @@ artMterpAsmInstructionStart = .L_op_nop
     bl      MterpSuspendCheck           // (self)
     b       .Lop_return_object_return
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_4: /* 0x12 */
-/* File: arm64/op_const_4.S */
     /* const/4 vA, #+B */
     sbfx    w1, wINST, #12, #4          // w1<- sssssssB
     ubfx    w0, wINST, #8, #4           // w0<- A
@@ -770,7 +730,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_16: /* 0x13 */
-/* File: arm64/op_const_16.S */
     /* const/16 vAA, #+BBBB */
     FETCH_S w0, 1                       // w0<- ssssBBBB (sign-extended)
     lsr     w3, wINST, #8               // w3<- AA
@@ -782,7 +741,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const: /* 0x14 */
-/* File: arm64/op_const.S */
     /* const vAA, #+BBBBbbbb */
     lsr     w3, wINST, #8               // w3<- AA
     FETCH w0, 1                         // w0<- bbbb (low
@@ -796,7 +754,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_high16: /* 0x15 */
-/* File: arm64/op_const_high16.S */
     /* const/high16 vAA, #+BBBB0000 */
     FETCH   w0, 1                       // r0<- 0000BBBB (zero-extended)
     lsr     w3, wINST, #8               // r3<- AA
@@ -809,7 +766,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_16: /* 0x16 */
-/* File: arm64/op_const_wide_16.S */
     /* const-wide/16 vAA, #+BBBB */
     FETCH_S x0, 1                       // x0<- ssssssssssssBBBB (sign-extended)
     lsr     w3, wINST, #8               // w3<- AA
@@ -821,7 +777,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_32: /* 0x17 */
-/* File: arm64/op_const_wide_32.S */
     /* const-wide/32 vAA, #+BBBBbbbb */
     FETCH   w0, 1                       // x0<- 000000000000bbbb (low)
     lsr     w3, wINST, #8               // w3<- AA
@@ -835,7 +790,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide: /* 0x18 */
-/* File: arm64/op_const_wide.S */
     /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
     FETCH w0, 1                         // w0<- bbbb (low)
     FETCH w1, 2                         // w1<- BBBB (low middle)
@@ -853,7 +807,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_high16: /* 0x19 */
-/* File: arm64/op_const_wide_high16.S */
     /* const-wide/high16 vAA, #+BBBB000000000000 */
     FETCH w0, 1                         // w0<- 0000BBBB (zero-extended)
     lsr     w1, wINST, #8               // w1<- AA
@@ -866,8 +819,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_string: /* 0x1a */
-/* File: arm64/op_const_string.S */
-/* File: arm64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -885,11 +836,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_string_jumbo: /* 0x1b */
-/* File: arm64/op_const_string_jumbo.S */
     /* const/string vAA, String//BBBBBBBB */
     EXPORT_PC
     FETCH w0, 1                         // w0<- bbbb (low
@@ -908,8 +857,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_class: /* 0x1c */
-/* File: arm64/op_const_class.S */
-/* File: arm64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -927,11 +874,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_enter: /* 0x1d */
-/* File: arm64/op_monitor_enter.S */
     /*
      * Synchronize on an object.
      */
@@ -949,7 +894,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_exit: /* 0x1e */
-/* File: arm64/op_monitor_exit.S */
     /*
      * Unlock an object.
      *
@@ -971,7 +915,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_check_cast: /* 0x1f */
-/* File: arm64/op_check_cast.S */
     /*
      * Check to see if a cast from one class to another is allowed.
      */
@@ -992,7 +935,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_instance_of: /* 0x20 */
-/* File: arm64/op_instance_of.S */
     /*
      * Check to see if an object reference is an instance of a class.
      *
@@ -1019,7 +961,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_array_length: /* 0x21 */
-/* File: arm64/op_array_length.S */
     /*
      * Return the length of an array.
      */
@@ -1036,7 +977,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_instance: /* 0x22 */
-/* File: arm64/op_new_instance.S */
     /*
      * Create a new instance of a class.
      */
@@ -1054,7 +994,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_array: /* 0x23 */
-/* File: arm64/op_new_array.S */
     /*
      * Allocate an array of objects, specified with the array class
      * and a count.
@@ -1077,7 +1016,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array: /* 0x24 */
-/* File: arm64/op_filled_new_array.S */
     /*
      * Create a new array with elements filled from registers.
      *
@@ -1099,8 +1037,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array_range: /* 0x25 */
-/* File: arm64/op_filled_new_array_range.S */
-/* File: arm64/op_filled_new_array.S */
     /*
      * Create a new array with elements filled from registers.
      *
@@ -1119,11 +1055,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_fill_array_data: /* 0x26 */
-/* File: arm64/op_fill_array_data.S */
     /* fill-array-data vAA, +BBBBBBBB */
     EXPORT_PC
     FETCH   w0, 1                       // x0<- 000000000000bbbb (lo)
@@ -1141,7 +1075,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_throw: /* 0x27 */
-/* File: arm64/op_throw.S */
     /*
      * Throw an exception object in the current thread.
      */
@@ -1156,7 +1089,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto: /* 0x28 */
-/* File: arm64/op_goto.S */
     /*
      * Unconditional branch, 8-bit offset.
      *
@@ -1170,7 +1102,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_16: /* 0x29 */
-/* File: arm64/op_goto_16.S */
     /*
      * Unconditional branch, 16-bit offset.
      *
@@ -1184,7 +1115,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_32: /* 0x2a */
-/* File: arm64/op_goto_32.S */
     /*
      * Unconditional branch, 32-bit offset.
      *
@@ -1205,7 +1135,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_packed_switch: /* 0x2b */
-/* File: arm64/op_packed_switch.S */
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
@@ -1229,8 +1158,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_sparse_switch: /* 0x2c */
-/* File: arm64/op_sparse_switch.S */
-/* File: arm64/op_packed_switch.S */
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
@@ -1251,12 +1178,9 @@ artMterpAsmInstructionStart = .L_op_nop
     sxtw    xINST, w0
     b       MterpCommonTakenBranchNoFlags
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_float: /* 0x2d */
-/* File: arm64/op_cmpl_float.S */
-/* File: arm64/fcmp.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1276,12 +1200,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG w0, w4                     // vAA<- w0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_float: /* 0x2e */
-/* File: arm64/op_cmpg_float.S */
-/* File: arm64/fcmp.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1301,12 +1222,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG w0, w4                     // vAA<- w0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_double: /* 0x2f */
-/* File: arm64/op_cmpl_double.S */
-/* File: arm64/fcmp.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1326,12 +1244,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG w0, w4                     // vAA<- w0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_double: /* 0x30 */
-/* File: arm64/op_cmpg_double.S */
-/* File: arm64/fcmp.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1351,11 +1266,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG w0, w4                     // vAA<- w0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmp_long: /* 0x31 */
-/* File: arm64/op_cmp_long.S */
     FETCH w0, 1                         // w0<- CCBB
     lsr     w4, wINST, #8               // w4<- AA
     and     w2, w0, #255                // w2<- BB
@@ -1373,8 +1286,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_if_eq: /* 0x32 */
-/* File: arm64/op_if_eq.S */
-/* File: arm64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1395,12 +1306,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ne: /* 0x33 */
-/* File: arm64/op_if_ne.S */
-/* File: arm64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1421,12 +1329,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lt: /* 0x34 */
-/* File: arm64/op_if_lt.S */
-/* File: arm64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1447,12 +1352,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ge: /* 0x35 */
-/* File: arm64/op_if_ge.S */
-/* File: arm64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1473,12 +1375,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gt: /* 0x36 */
-/* File: arm64/op_if_gt.S */
-/* File: arm64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1499,12 +1398,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_le: /* 0x37 */
-/* File: arm64/op_if_le.S */
-/* File: arm64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1525,12 +1421,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_eqz: /* 0x38 */
-/* File: arm64/op_if_eqz.S */
-/* File: arm64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1551,12 +1444,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_nez: /* 0x39 */
-/* File: arm64/op_if_nez.S */
-/* File: arm64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1577,12 +1467,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ltz: /* 0x3a */
-/* File: arm64/op_if_ltz.S */
-/* File: arm64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1603,12 +1490,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gez: /* 0x3b */
-/* File: arm64/op_if_gez.S */
-/* File: arm64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1629,12 +1513,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gtz: /* 0x3c */
-/* File: arm64/op_if_gtz.S */
-/* File: arm64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1655,12 +1536,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lez: /* 0x3d */
-/* File: arm64/op_if_lez.S */
-/* File: arm64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1681,77 +1559,57 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3e: /* 0x3e */
-/* File: arm64/op_unused_3e.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3f: /* 0x3f */
-/* File: arm64/op_unused_3f.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_40: /* 0x40 */
-/* File: arm64/op_unused_40.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_41: /* 0x41 */
-/* File: arm64/op_unused_41.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_42: /* 0x42 */
-/* File: arm64/op_unused_42.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_43: /* 0x43 */
-/* File: arm64/op_unused_43.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget: /* 0x44 */
-/* File: arm64/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1783,7 +1641,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_wide: /* 0x45 */
-/* File: arm64/op_aget_wide.S */
     /*
      * Array get, 64 bits.  vAA <- vBB[vCC].
      *
@@ -1809,7 +1666,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_object: /* 0x46 */
-/* File: arm64/op_aget_object.S */
     /*
      * Array object get.  vAA <- vBB[vCC].
      *
@@ -1834,8 +1690,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_boolean: /* 0x47 */
-/* File: arm64/op_aget_boolean.S */
-/* File: arm64/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1864,12 +1718,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG w2, w9                     // vAA<- w2
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_byte: /* 0x48 */
-/* File: arm64/op_aget_byte.S */
-/* File: arm64/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1898,12 +1749,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG w2, w9                     // vAA<- w2
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_char: /* 0x49 */
-/* File: arm64/op_aget_char.S */
-/* File: arm64/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1932,12 +1780,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG w2, w9                     // vAA<- w2
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_short: /* 0x4a */
-/* File: arm64/op_aget_short.S */
-/* File: arm64/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1966,11 +1811,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG w2, w9                     // vAA<- w2
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput: /* 0x4b */
-/* File: arm64/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2002,7 +1845,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_wide: /* 0x4c */
-/* File: arm64/op_aput_wide.S */
     /*
      * Array put, 64 bits.  vBB[vCC] <- vAA.
      *
@@ -2028,7 +1870,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_object: /* 0x4d */
-/* File: arm64/op_aput_object.S */
     /*
      * Store an object into an array.  vBB[vCC] <- vAA.
      */
@@ -2046,8 +1887,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_boolean: /* 0x4e */
-/* File: arm64/op_aput_boolean.S */
-/* File: arm64/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2076,12 +1915,9 @@ artMterpAsmInstructionStart = .L_op_nop
     strb  w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET]     // vBB[vCC]<- w2
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_byte: /* 0x4f */
-/* File: arm64/op_aput_byte.S */
-/* File: arm64/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2110,12 +1946,9 @@ artMterpAsmInstructionStart = .L_op_nop
     strb  w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET]     // vBB[vCC]<- w2
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_char: /* 0x50 */
-/* File: arm64/op_aput_char.S */
-/* File: arm64/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2144,12 +1977,9 @@ artMterpAsmInstructionStart = .L_op_nop
     strh  w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET]     // vBB[vCC]<- w2
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_short: /* 0x51 */
-/* File: arm64/op_aput_short.S */
-/* File: arm64/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2178,12 +2008,9 @@ artMterpAsmInstructionStart = .L_op_nop
     strh  w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET]     // vBB[vCC]<- w2
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget: /* 0x52 */
-/* File: arm64/op_iget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2199,13 +2026,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide: /* 0x53 */
-/* File: arm64/op_iget_wide.S */
-/* File: arm64/op_iget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2221,14 +2044,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object: /* 0x54 */
-/* File: arm64/op_iget_object.S */
-/* File: arm64/op_iget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2244,14 +2062,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean: /* 0x55 */
-/* File: arm64/op_iget_boolean.S */
-/* File: arm64/op_iget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2267,14 +2080,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte: /* 0x56 */
-/* File: arm64/op_iget_byte.S */
-/* File: arm64/op_iget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2290,14 +2098,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char: /* 0x57 */
-/* File: arm64/op_iget_char.S */
-/* File: arm64/op_iget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2313,14 +2116,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short: /* 0x58 */
-/* File: arm64/op_iget_short.S */
-/* File: arm64/op_iget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2336,13 +2134,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput: /* 0x59 */
-/* File: arm64/op_iput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2358,13 +2152,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide: /* 0x5a */
-/* File: arm64/op_iput_wide.S */
-/* File: arm64/op_iput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2380,14 +2170,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object: /* 0x5b */
-/* File: arm64/op_iput_object.S */
-/* File: arm64/op_iput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2403,14 +2188,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean: /* 0x5c */
-/* File: arm64/op_iput_boolean.S */
-/* File: arm64/op_iput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2426,14 +2206,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte: /* 0x5d */
-/* File: arm64/op_iput_byte.S */
-/* File: arm64/op_iput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2449,14 +2224,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char: /* 0x5e */
-/* File: arm64/op_iput_char.S */
-/* File: arm64/op_iput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2472,14 +2242,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short: /* 0x5f */
-/* File: arm64/op_iput_short.S */
-/* File: arm64/op_iput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2495,13 +2260,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget: /* 0x60 */
-/* File: arm64/op_sget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2517,13 +2278,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_wide: /* 0x61 */
-/* File: arm64/op_sget_wide.S */
-/* File: arm64/op_sget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2539,14 +2296,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_object: /* 0x62 */
-/* File: arm64/op_sget_object.S */
-/* File: arm64/op_sget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2562,14 +2314,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_boolean: /* 0x63 */
-/* File: arm64/op_sget_boolean.S */
-/* File: arm64/op_sget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2585,14 +2332,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_byte: /* 0x64 */
-/* File: arm64/op_sget_byte.S */
-/* File: arm64/op_sget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2608,14 +2350,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_char: /* 0x65 */
-/* File: arm64/op_sget_char.S */
-/* File: arm64/op_sget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2631,14 +2368,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_short: /* 0x66 */
-/* File: arm64/op_sget_short.S */
-/* File: arm64/op_sget.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2654,13 +2386,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput: /* 0x67 */
-/* File: arm64/op_sput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2676,13 +2404,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_wide: /* 0x68 */
-/* File: arm64/op_sput_wide.S */
-/* File: arm64/op_sput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2698,14 +2422,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_object: /* 0x69 */
-/* File: arm64/op_sput_object.S */
-/* File: arm64/op_sput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2721,14 +2440,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_boolean: /* 0x6a */
-/* File: arm64/op_sput_boolean.S */
-/* File: arm64/op_sput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2744,14 +2458,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_byte: /* 0x6b */
-/* File: arm64/op_sput_byte.S */
-/* File: arm64/op_sput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2767,14 +2476,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_char: /* 0x6c */
-/* File: arm64/op_sput_char.S */
-/* File: arm64/op_sput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2790,14 +2494,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_short: /* 0x6d */
-/* File: arm64/op_sput_short.S */
-/* File: arm64/op_sput.S */
-/* File: arm64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2813,13 +2512,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                     // extract opcode from rINST
     GOTO_OPCODE ip                         // jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual: /* 0x6e */
-/* File: arm64/op_invoke_virtual.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2839,7 +2534,6 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
     /*
      * Handle a virtual method call.
      *
@@ -2851,8 +2545,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super: /* 0x6f */
-/* File: arm64/op_invoke_super.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2872,7 +2564,6 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
     /*
      * Handle a "super" method call.
      *
@@ -2884,8 +2575,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct: /* 0x70 */
-/* File: arm64/op_invoke_direct.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2905,13 +2594,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static: /* 0x71 */
-/* File: arm64/op_invoke_static.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2931,14 +2616,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface: /* 0x72 */
-/* File: arm64/op_invoke_interface.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2958,7 +2638,6 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
     /*
      * Handle an interface method call.
      *
@@ -2970,7 +2649,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_void_no_barrier: /* 0x73 */
-/* File: arm64/op_return_void_no_barrier.S */
     ldr     w7, [xSELF, #THREAD_FLAGS_OFFSET]
     mov     x0, xSELF
     ands    w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
@@ -2985,8 +2663,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range: /* 0x74 */
-/* File: arm64/op_invoke_virtual_range.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3006,13 +2682,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super_range: /* 0x75 */
-/* File: arm64/op_invoke_super_range.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3032,13 +2704,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct_range: /* 0x76 */
-/* File: arm64/op_invoke_direct_range.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3058,13 +2726,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static_range: /* 0x77 */
-/* File: arm64/op_invoke_static_range.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3084,13 +2748,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface_range: /* 0x78 */
-/* File: arm64/op_invoke_interface_range.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3110,35 +2770,25 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_79: /* 0x79 */
-/* File: arm64/op_unused_79.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_7a: /* 0x7a */
-/* File: arm64/op_unused_7a.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_int: /* 0x7b */
-/* File: arm64/op_neg_int.S */
-/* File: arm64/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op w0".
@@ -3158,12 +2808,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_int: /* 0x7c */
-/* File: arm64/op_not_int.S */
-/* File: arm64/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op w0".
@@ -3183,12 +2830,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_long: /* 0x7d */
-/* File: arm64/op_neg_long.S */
-/* File: arm64/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op x0".
@@ -3206,12 +2850,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-11 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_long: /* 0x7e */
-/* File: arm64/op_not_long.S */
-/* File: arm64/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op x0".
@@ -3229,12 +2870,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-11 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_float: /* 0x7f */
-/* File: arm64/op_neg_float.S */
-/* File: arm64/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op w0".
@@ -3254,12 +2892,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_double: /* 0x80 */
-/* File: arm64/op_neg_double.S */
-/* File: arm64/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op x0".
@@ -3277,11 +2912,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-11 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_long: /* 0x81 */
-/* File: arm64/op_int_to_long.S */
     /* int-to-long vA, vB */
     lsr     w3, wINST, #12              // w3<- B
     ubfx    w4, wINST, #8, #4           // w4<- A
@@ -3294,8 +2927,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_float: /* 0x82 */
-/* File: arm64/op_int_to_float.S */
-/* File: arm64/funopNarrow.S */
     /*
      * Generic 32bit-to-32bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "s0 = op w0".
@@ -3313,12 +2944,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG s0, w4                // vA<- d0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_double: /* 0x83 */
-/* File: arm64/op_int_to_double.S */
-/* File: arm64/funopWider.S */
     /*
      * Generic 32bit-to-64bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "d0 = op w0".
@@ -3335,13 +2963,10 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG_WIDE d0, w4           // vA<- d0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_int: /* 0x84 */
-/* File: arm64/op_long_to_int.S */
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-/* File: arm64/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     lsr     w1, wINST, #12              // x1<- B from 15:12
@@ -3356,12 +2981,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE ip                      // execute next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_float: /* 0x85 */
-/* File: arm64/op_long_to_float.S */
-/* File: arm64/funopNarrower.S */
     /*
      * Generic 64bit-to-32bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "s0 = op x0".
@@ -3378,12 +3000,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG s0, w4                // vA<- d0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_double: /* 0x86 */
-/* File: arm64/op_long_to_double.S */
-/* File: arm64/funopWide.S */
     /*
      * Generic 64bit-to-64bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "d0 = op x0".
@@ -3400,12 +3019,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG_WIDE d0, w4           // vA<- d0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_int: /* 0x87 */
-/* File: arm64/op_float_to_int.S */
-/* File: arm64/funopNarrow.S */
     /*
      * Generic 32bit-to-32bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "w0 = op s0".
@@ -3423,12 +3039,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG w0, w4                // vA<- d0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_long: /* 0x88 */
-/* File: arm64/op_float_to_long.S */
-/* File: arm64/funopWider.S */
     /*
      * Generic 32bit-to-64bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "x0 = op s0".
@@ -3445,12 +3058,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG_WIDE x0, w4           // vA<- d0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_double: /* 0x89 */
-/* File: arm64/op_float_to_double.S */
-/* File: arm64/funopWider.S */
     /*
      * Generic 32bit-to-64bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "d0 = op s0".
@@ -3467,12 +3077,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG_WIDE d0, w4           // vA<- d0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_int: /* 0x8a */
-/* File: arm64/op_double_to_int.S */
-/* File: arm64/funopNarrower.S */
     /*
      * Generic 64bit-to-32bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "w0 = op d0".
@@ -3489,12 +3096,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG w0, w4                // vA<- d0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_long: /* 0x8b */
-/* File: arm64/op_double_to_long.S */
-/* File: arm64/funopWide.S */
     /*
      * Generic 64bit-to-64bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "x0 = op d0".
@@ -3511,12 +3115,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG_WIDE x0, w4           // vA<- d0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_float: /* 0x8c */
-/* File: arm64/op_double_to_float.S */
-/* File: arm64/funopNarrower.S */
     /*
      * Generic 64bit-to-32bit floating point unary operation.  Provide an
      * "instr" line that specifies an instruction that performs "s0 = op d0".
@@ -3533,12 +3134,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG s0, w4                // vA<- d0
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_byte: /* 0x8d */
-/* File: arm64/op_int_to_byte.S */
-/* File: arm64/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op w0".
@@ -3558,12 +3156,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_char: /* 0x8e */
-/* File: arm64/op_int_to_char.S */
-/* File: arm64/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op w0".
@@ -3583,12 +3178,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_short: /* 0x8f */
-/* File: arm64/op_int_to_short.S */
-/* File: arm64/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = op w0".
@@ -3608,12 +3200,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 8-9 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int: /* 0x90 */
-/* File: arm64/op_add_int.S */
-/* File: arm64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
@@ -3647,12 +3236,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int: /* 0x91 */
-/* File: arm64/op_sub_int.S */
-/* File: arm64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
@@ -3686,13 +3272,10 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int: /* 0x92 */
-/* File: arm64/op_mul_int.S */
 /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */
-/* File: arm64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
@@ -3726,12 +3309,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int: /* 0x93 */
-/* File: arm64/op_div_int.S */
-/* File: arm64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
@@ -3765,12 +3345,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int: /* 0x94 */
-/* File: arm64/op_rem_int.S */
-/* File: arm64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
@@ -3804,12 +3381,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int: /* 0x95 */
-/* File: arm64/op_and_int.S */
-/* File: arm64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
@@ -3843,12 +3417,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int: /* 0x96 */
-/* File: arm64/op_or_int.S */
-/* File: arm64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
@@ -3882,12 +3453,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int: /* 0x97 */
-/* File: arm64/op_xor_int.S */
-/* File: arm64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
@@ -3921,12 +3489,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int: /* 0x98 */
-/* File: arm64/op_shl_int.S */
-/* File: arm64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
@@ -3960,12 +3525,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int: /* 0x99 */
-/* File: arm64/op_shr_int.S */
-/* File: arm64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
@@ -3999,12 +3561,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int: /* 0x9a */
-/* File: arm64/op_ushr_int.S */
-/* File: arm64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = w0 op w1".
@@ -4038,12 +3597,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long: /* 0x9b */
-/* File: arm64/op_add_long.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4074,12 +3630,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long: /* 0x9c */
-/* File: arm64/op_sub_long.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4110,12 +3663,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long: /* 0x9d */
-/* File: arm64/op_mul_long.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4146,12 +3696,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_long: /* 0x9e */
-/* File: arm64/op_div_long.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4182,12 +3729,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long: /* 0x9f */
-/* File: arm64/op_rem_long.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4218,12 +3762,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long: /* 0xa0 */
-/* File: arm64/op_and_long.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4254,12 +3795,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long: /* 0xa1 */
-/* File: arm64/op_or_long.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4290,12 +3828,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long: /* 0xa2 */
-/* File: arm64/op_xor_long.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4326,12 +3861,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long: /* 0xa3 */
-/* File: arm64/op_shl_long.S */
-/* File: arm64/shiftWide.S */
     /*
      * 64-bit shift operation.
      *
@@ -4351,12 +3883,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long: /* 0xa4 */
-/* File: arm64/op_shr_long.S */
-/* File: arm64/shiftWide.S */
     /*
      * 64-bit shift operation.
      *
@@ -4376,12 +3905,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long: /* 0xa5 */
-/* File: arm64/op_ushr_long.S */
-/* File: arm64/shiftWide.S */
     /*
      * 64-bit shift operation.
      *
@@ -4401,12 +3927,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_float: /* 0xa6 */
-/* File: arm64/op_add_float.S */
-/* File: arm64/fbinop.S */
     /*:
      * Generic 32-bit floating-point operation.
      *
@@ -4426,12 +3949,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG  s0, w1
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float: /* 0xa7 */
-/* File: arm64/op_sub_float.S */
-/* File: arm64/fbinop.S */
     /*:
      * Generic 32-bit floating-point operation.
      *
@@ -4451,12 +3971,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG  s0, w1
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float: /* 0xa8 */
-/* File: arm64/op_mul_float.S */
-/* File: arm64/fbinop.S */
     /*:
      * Generic 32-bit floating-point operation.
      *
@@ -4476,12 +3993,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG  s0, w1
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float: /* 0xa9 */
-/* File: arm64/op_div_float.S */
-/* File: arm64/fbinop.S */
     /*:
      * Generic 32-bit floating-point operation.
      *
@@ -4501,13 +4015,10 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG  s0, w1
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float: /* 0xaa */
-/* File: arm64/op_rem_float.S */
 /* EABI doesn't define a float remainder function, but libm does */
-/* File: arm64/fbinop.S */
     /*:
      * Generic 32-bit floating-point operation.
      *
@@ -4527,12 +4038,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG  s0, w1
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_double: /* 0xab */
-/* File: arm64/op_add_double.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4563,12 +4071,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double: /* 0xac */
-/* File: arm64/op_sub_double.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4599,12 +4104,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double: /* 0xad */
-/* File: arm64/op_mul_double.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4635,12 +4137,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double: /* 0xae */
-/* File: arm64/op_div_double.S */
-/* File: arm64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = x1 op x2".
@@ -4671,11 +4170,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 11-14 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double: /* 0xaf */
-/* File: arm64/op_rem_double.S */
     /* rem vAA, vBB, vCC */
     FETCH w0, 1                         // w0<- CCBB
     lsr     w2, w0, #8                  // w2<- CC
@@ -4693,8 +4190,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_2addr: /* 0xb0 */
-/* File: arm64/op_add_int_2addr.S */
-/* File: arm64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -4725,12 +4220,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int_2addr: /* 0xb1 */
-/* File: arm64/op_sub_int_2addr.S */
-/* File: arm64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -4761,13 +4253,10 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_2addr: /* 0xb2 */
-/* File: arm64/op_mul_int_2addr.S */
 /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */
-/* File: arm64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -4798,12 +4287,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_2addr: /* 0xb3 */
-/* File: arm64/op_div_int_2addr.S */
-/* File: arm64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -4834,12 +4320,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_2addr: /* 0xb4 */
-/* File: arm64/op_rem_int_2addr.S */
-/* File: arm64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -4870,12 +4353,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_2addr: /* 0xb5 */
-/* File: arm64/op_and_int_2addr.S */
-/* File: arm64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -4906,12 +4386,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_2addr: /* 0xb6 */
-/* File: arm64/op_or_int_2addr.S */
-/* File: arm64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -4942,12 +4419,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_2addr: /* 0xb7 */
-/* File: arm64/op_xor_int_2addr.S */
-/* File: arm64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -4978,12 +4452,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_2addr: /* 0xb8 */
-/* File: arm64/op_shl_int_2addr.S */
-/* File: arm64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -5014,12 +4485,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_2addr: /* 0xb9 */
-/* File: arm64/op_shr_int_2addr.S */
-/* File: arm64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -5050,12 +4518,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_2addr: /* 0xba */
-/* File: arm64/op_ushr_int_2addr.S */
-/* File: arm64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -5086,12 +4551,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long_2addr: /* 0xbb */
-/* File: arm64/op_add_long_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5121,12 +4583,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long_2addr: /* 0xbc */
-/* File: arm64/op_sub_long_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5156,12 +4615,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long_2addr: /* 0xbd */
-/* File: arm64/op_mul_long_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5191,12 +4647,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_long_2addr: /* 0xbe */
-/* File: arm64/op_div_long_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5226,12 +4679,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long_2addr: /* 0xbf */
-/* File: arm64/op_rem_long_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5261,12 +4711,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long_2addr: /* 0xc0 */
-/* File: arm64/op_and_long_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5296,12 +4743,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long_2addr: /* 0xc1 */
-/* File: arm64/op_or_long_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5331,12 +4775,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long_2addr: /* 0xc2 */
-/* File: arm64/op_xor_long_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5366,12 +4807,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long_2addr: /* 0xc3 */
-/* File: arm64/op_shl_long_2addr.S */
-/* File: arm64/shiftWide2addr.S */
     /*
      * Generic 64-bit shift operation.
      */
@@ -5387,12 +4825,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long_2addr: /* 0xc4 */
-/* File: arm64/op_shr_long_2addr.S */
-/* File: arm64/shiftWide2addr.S */
     /*
      * Generic 64-bit shift operation.
      */
@@ -5408,12 +4843,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long_2addr: /* 0xc5 */
-/* File: arm64/op_ushr_long_2addr.S */
-/* File: arm64/shiftWide2addr.S */
     /*
      * Generic 64-bit shift operation.
      */
@@ -5429,12 +4861,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_float_2addr: /* 0xc6 */
-/* File: arm64/op_add_float_2addr.S */
-/* File: arm64/fbinop2addr.S */
     /*
      * Generic 32-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -5453,12 +4882,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG s2, w9
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float_2addr: /* 0xc7 */
-/* File: arm64/op_sub_float_2addr.S */
-/* File: arm64/fbinop2addr.S */
     /*
      * Generic 32-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -5477,12 +4903,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG s2, w9
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float_2addr: /* 0xc8 */
-/* File: arm64/op_mul_float_2addr.S */
-/* File: arm64/fbinop2addr.S */
     /*
      * Generic 32-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -5501,12 +4924,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG s2, w9
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float_2addr: /* 0xc9 */
-/* File: arm64/op_div_float_2addr.S */
-/* File: arm64/fbinop2addr.S */
     /*
      * Generic 32-bit floating point "/2addr" binary operation.  Provide
      * an "instr" line that specifies an instruction that performs
@@ -5525,11 +4945,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG s2, w9
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float_2addr: /* 0xca */
-/* File: arm64/op_rem_float_2addr.S */
     /* rem vA, vB */
     lsr     w3, wINST, #12              // w3<- B
     ubfx    w9, wINST, #8, #4           // w9<- A
@@ -5545,8 +4963,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_add_double_2addr: /* 0xcb */
-/* File: arm64/op_add_double_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5576,12 +4992,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double_2addr: /* 0xcc */
-/* File: arm64/op_sub_double_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5611,12 +5024,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double_2addr: /* 0xcd */
-/* File: arm64/op_mul_double_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5646,12 +5056,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double_2addr: /* 0xce */
-/* File: arm64/op_div_double_2addr.S */
-/* File: arm64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "x0 = x0 op x1".
@@ -5681,11 +5088,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double_2addr: /* 0xcf */
-/* File: arm64/op_rem_double_2addr.S */
     /* rem vA, vB */
     lsr     w1, wINST, #12              // w1<- B
     ubfx    w2, wINST, #8, #4           // w2<- A
@@ -5702,8 +5107,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit16: /* 0xd0 */
-/* File: arm64/op_add_int_lit16.S */
-/* File: arm64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -5732,13 +5135,10 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int: /* 0xd1 */
-/* File: arm64/op_rsub_int.S */
 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
-/* File: arm64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -5767,13 +5167,10 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit16: /* 0xd2 */
-/* File: arm64/op_mul_int_lit16.S */
 /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */
-/* File: arm64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -5802,12 +5199,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit16: /* 0xd3 */
-/* File: arm64/op_div_int_lit16.S */
-/* File: arm64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -5836,12 +5230,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit16: /* 0xd4 */
-/* File: arm64/op_rem_int_lit16.S */
-/* File: arm64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -5870,12 +5261,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit16: /* 0xd5 */
-/* File: arm64/op_and_int_lit16.S */
-/* File: arm64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -5904,12 +5292,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit16: /* 0xd6 */
-/* File: arm64/op_or_int_lit16.S */
-/* File: arm64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -5938,12 +5323,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit16: /* 0xd7 */
-/* File: arm64/op_xor_int_lit16.S */
-/* File: arm64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -5972,12 +5354,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-13 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit8: /* 0xd8 */
-/* File: arm64/op_add_int_lit8.S */
-/* File: arm64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -6012,12 +5391,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int_lit8: /* 0xd9 */
-/* File: arm64/op_rsub_int_lit8.S */
-/* File: arm64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -6052,13 +5428,10 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit8: /* 0xda */
-/* File: arm64/op_mul_int_lit8.S */
 /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */
-/* File: arm64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -6093,12 +5466,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit8: /* 0xdb */
-/* File: arm64/op_div_int_lit8.S */
-/* File: arm64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -6133,12 +5503,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit8: /* 0xdc */
-/* File: arm64/op_rem_int_lit8.S */
-/* File: arm64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -6173,12 +5540,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit8: /* 0xdd */
-/* File: arm64/op_and_int_lit8.S */
-/* File: arm64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -6213,12 +5577,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit8: /* 0xde */
-/* File: arm64/op_or_int_lit8.S */
-/* File: arm64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -6253,12 +5614,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit8: /* 0xdf */
-/* File: arm64/op_xor_int_lit8.S */
-/* File: arm64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -6293,12 +5651,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_lit8: /* 0xe0 */
-/* File: arm64/op_shl_int_lit8.S */
-/* File: arm64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -6333,12 +5688,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_lit8: /* 0xe1 */
-/* File: arm64/op_shr_int_lit8.S */
-/* File: arm64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -6373,12 +5725,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_lit8: /* 0xe2 */
-/* File: arm64/op_ushr_int_lit8.S */
-/* File: arm64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = w0 op w1".
@@ -6413,11 +5762,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GOTO_OPCODE ip                      // jump to next instruction
     /* 10-12 instructions */
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_quick: /* 0xe3 */
-/* File: arm64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
@@ -6435,7 +5782,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide_quick: /* 0xe4 */
-/* File: arm64/op_iget_wide_quick.S */
     /* iget-wide-quick vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
     FETCH w4, 1                         // w4<- field byte offset
@@ -6451,7 +5797,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object_quick: /* 0xe5 */
-/* File: arm64/op_iget_object_quick.S */
     /* For: iget-object-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
@@ -6471,7 +5816,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_iput_quick: /* 0xe6 */
-/* File: arm64/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
@@ -6488,7 +5832,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide_quick: /* 0xe7 */
-/* File: arm64/op_iput_wide_quick.S */
     /* iput-wide-quick vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
     FETCH w3, 1                         // w3<- field byte offset
@@ -6504,7 +5847,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object_quick: /* 0xe8 */
-/* File: arm64/op_iput_object_quick.S */
     EXPORT_PC
     add     x0, xFP, #OFF_FP_SHADOWFRAME
     mov     x1, xPC
@@ -6518,8 +5860,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_quick: /* 0xe9 */
-/* File: arm64/op_invoke_virtual_quick.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -6539,13 +5879,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range_quick: /* 0xea */
-/* File: arm64/op_invoke_virtual_range_quick.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -6565,13 +5901,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean_quick: /* 0xeb */
-/* File: arm64/op_iput_boolean_quick.S */
-/* File: arm64/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
@@ -6585,12 +5917,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte_quick: /* 0xec */
-/* File: arm64/op_iput_byte_quick.S */
-/* File: arm64/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
@@ -6604,12 +5933,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char_quick: /* 0xed */
-/* File: arm64/op_iput_char_quick.S */
-/* File: arm64/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
@@ -6623,12 +5949,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short_quick: /* 0xee */
-/* File: arm64/op_iput_short_quick.S */
-/* File: arm64/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
@@ -6642,12 +5965,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean_quick: /* 0xef */
-/* File: arm64/op_iget_boolean_quick.S */
-/* File: arm64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
@@ -6662,12 +5982,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte_quick: /* 0xf0 */
-/* File: arm64/op_iget_byte_quick.S */
-/* File: arm64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
@@ -6682,12 +5999,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char_quick: /* 0xf1 */
-/* File: arm64/op_iget_char_quick.S */
-/* File: arm64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
@@ -6702,12 +6016,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short_quick: /* 0xf2 */
-/* File: arm64/op_iget_short_quick.S */
-/* File: arm64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     lsr     w2, wINST, #12              // w2<- B
@@ -6722,89 +6033,65 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f3: /* 0xf3 */
-/* File: arm64/op_unused_f3.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f4: /* 0xf4 */
-/* File: arm64/op_unused_f4.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f5: /* 0xf5 */
-/* File: arm64/op_unused_f5.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f6: /* 0xf6 */
-/* File: arm64/op_unused_f6.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f7: /* 0xf7 */
-/* File: arm64/op_unused_f7.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f8: /* 0xf8 */
-/* File: arm64/op_unused_f8.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f9: /* 0xf9 */
-/* File: arm64/op_unused_f9.S */
-/* File: arm64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic: /* 0xfa */
-/* File: arm64/op_invoke_polymorphic.S */
-/* File: arm64/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -6824,12 +6111,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic_range: /* 0xfb */
-/* File: arm64/op_invoke_polymorphic_range.S */
-/* File: arm64/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -6849,12 +6133,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom: /* 0xfc */
-/* File: arm64/op_invoke_custom.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -6874,13 +6155,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom_range: /* 0xfd */
-/* File: arm64/op_invoke_custom_range.S */
-/* File: arm64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -6900,13 +6177,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip
     GOTO_OPCODE ip
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_handle: /* 0xfe */
-/* File: arm64/op_const_method_handle.S */
-/* File: arm64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -6924,12 +6197,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_type: /* 0xff */
-/* File: arm64/op_const_method_type.S */
-/* File: arm64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -6947,23 +6217,13 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE ip                  // extract opcode from rINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
     .balign 128
-/* File: arm64/instruction_end.S */
 
     .type artMterpAsmInstructionEnd, #object
     .hidden artMterpAsmInstructionEnd
     .global artMterpAsmInstructionEnd
 artMterpAsmInstructionEnd:
 
-
-/*
- * ===========================================================================
- *  Sister implementations
- * ===========================================================================
- */
-/* File: arm64/instruction_start_sister.S */
-
     .type artMterpAsmSisterStart, #object
     .hidden artMterpAsmSisterStart
     .global artMterpAsmSisterStart
@@ -6971,21 +6231,16 @@ artMterpAsmInstructionEnd:
     .balign 4
 artMterpAsmSisterStart:
 
-/* File: arm64/instruction_end_sister.S */
-
     .type artMterpAsmSisterEnd, #object
     .hidden artMterpAsmSisterEnd
     .global artMterpAsmSisterEnd
 artMterpAsmSisterEnd:
-
-/* File: arm64/footer.S */
 /*
  * ===========================================================================
  *  Common subroutines and data
  * ===========================================================================
  */
 
-
 /*
  * We've detected a condition that will result in an exception, but the exception
  * has not yet been thrown.  Just bail out to the reference interpreter to deal with it.
@@ -7188,7 +6443,6 @@ MterpCommonTakenBranchNoFlags:
     GET_INST_OPCODE ip                  // extract opcode from wINST
     GOTO_OPCODE ip                      // jump to next instruction
 
-
 /*
  * Check for suspend check request.  Assumes wINST already loaded, xPC advanced and
  * still needs to get the opcode and branch to it, and flags are in lr.
@@ -7285,19 +6539,14 @@ MterpProfileActive:
     RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80
     ret
 
-
-/* File: arm64/instruction_start_alt.S */
-
     .type artMterpAsmAltInstructionStart, #object
     .hidden artMterpAsmAltInstructionStart
     .global artMterpAsmAltInstructionStart
 artMterpAsmAltInstructionStart = .L_ALT_op_nop
     .text
-
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_nop: /* 0x00 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7314,7 +6563,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move: /* 0x01 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7331,7 +6579,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_from16: /* 0x02 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7348,7 +6595,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_16: /* 0x03 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7365,7 +6611,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide: /* 0x04 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7382,7 +6627,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_from16: /* 0x05 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7399,7 +6643,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_16: /* 0x06 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7416,7 +6659,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object: /* 0x07 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7433,7 +6675,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_from16: /* 0x08 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7450,7 +6691,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_16: /* 0x09 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7467,7 +6707,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result: /* 0x0a */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7484,7 +6723,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_wide: /* 0x0b */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7501,7 +6739,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_object: /* 0x0c */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7518,7 +6755,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_exception: /* 0x0d */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7535,7 +6771,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void: /* 0x0e */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7552,7 +6787,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return: /* 0x0f */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7569,7 +6803,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_wide: /* 0x10 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7586,7 +6819,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_object: /* 0x11 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7603,7 +6835,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_4: /* 0x12 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7620,7 +6851,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_16: /* 0x13 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7637,7 +6867,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const: /* 0x14 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7654,7 +6883,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_high16: /* 0x15 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7671,7 +6899,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_16: /* 0x16 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7688,7 +6915,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_32: /* 0x17 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7705,7 +6931,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide: /* 0x18 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7722,7 +6947,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_high16: /* 0x19 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7739,7 +6963,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string: /* 0x1a */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7756,7 +6979,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string_jumbo: /* 0x1b */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7773,7 +6995,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_class: /* 0x1c */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7790,7 +7011,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_enter: /* 0x1d */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7807,7 +7027,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_exit: /* 0x1e */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7824,7 +7043,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_check_cast: /* 0x1f */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7841,7 +7059,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_instance_of: /* 0x20 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7858,7 +7075,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_array_length: /* 0x21 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7875,7 +7091,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_instance: /* 0x22 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7892,7 +7107,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_array: /* 0x23 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7909,7 +7123,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array: /* 0x24 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7926,7 +7139,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array_range: /* 0x25 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7943,7 +7155,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_fill_array_data: /* 0x26 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7960,7 +7171,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_throw: /* 0x27 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7977,7 +7187,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto: /* 0x28 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7994,7 +7203,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_16: /* 0x29 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8011,7 +7219,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_32: /* 0x2a */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8028,7 +7235,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_packed_switch: /* 0x2b */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8045,7 +7251,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sparse_switch: /* 0x2c */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8062,7 +7267,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_float: /* 0x2d */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8079,7 +7283,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_float: /* 0x2e */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8096,7 +7299,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_double: /* 0x2f */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8113,7 +7315,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_double: /* 0x30 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8130,7 +7331,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmp_long: /* 0x31 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8147,7 +7347,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eq: /* 0x32 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8164,7 +7363,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ne: /* 0x33 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8181,7 +7379,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lt: /* 0x34 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8198,7 +7395,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ge: /* 0x35 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8215,7 +7411,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gt: /* 0x36 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8232,7 +7427,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_le: /* 0x37 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8249,7 +7443,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eqz: /* 0x38 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8266,7 +7459,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_nez: /* 0x39 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8283,7 +7475,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ltz: /* 0x3a */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8300,7 +7491,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gez: /* 0x3b */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8317,7 +7507,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gtz: /* 0x3c */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8334,7 +7523,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lez: /* 0x3d */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8351,7 +7539,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3e: /* 0x3e */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8368,7 +7555,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3f: /* 0x3f */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8385,7 +7571,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_40: /* 0x40 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8402,7 +7587,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_41: /* 0x41 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8419,7 +7603,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_42: /* 0x42 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8436,7 +7619,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_43: /* 0x43 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8453,7 +7635,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget: /* 0x44 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8470,7 +7651,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_wide: /* 0x45 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8487,7 +7667,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_object: /* 0x46 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8504,7 +7683,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_boolean: /* 0x47 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8521,7 +7699,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_byte: /* 0x48 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8538,7 +7715,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_char: /* 0x49 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8555,7 +7731,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_short: /* 0x4a */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8572,7 +7747,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput: /* 0x4b */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8589,7 +7763,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_wide: /* 0x4c */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8606,7 +7779,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_object: /* 0x4d */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8623,7 +7795,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_boolean: /* 0x4e */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8640,7 +7811,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_byte: /* 0x4f */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8657,7 +7827,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_char: /* 0x50 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8674,7 +7843,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_short: /* 0x51 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8691,7 +7859,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget: /* 0x52 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8708,7 +7875,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide: /* 0x53 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8725,7 +7891,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object: /* 0x54 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8742,7 +7907,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean: /* 0x55 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8759,7 +7923,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte: /* 0x56 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8776,7 +7939,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char: /* 0x57 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8793,7 +7955,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short: /* 0x58 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8810,7 +7971,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput: /* 0x59 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8827,7 +7987,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide: /* 0x5a */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8844,7 +8003,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object: /* 0x5b */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8861,7 +8019,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean: /* 0x5c */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8878,7 +8035,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte: /* 0x5d */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8895,7 +8051,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char: /* 0x5e */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8912,7 +8067,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short: /* 0x5f */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8929,7 +8083,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget: /* 0x60 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8946,7 +8099,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_wide: /* 0x61 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8963,7 +8115,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_object: /* 0x62 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8980,7 +8131,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_boolean: /* 0x63 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8997,7 +8147,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_byte: /* 0x64 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9014,7 +8163,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_char: /* 0x65 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9031,7 +8179,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_short: /* 0x66 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9048,7 +8195,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput: /* 0x67 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9065,7 +8211,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_wide: /* 0x68 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9082,7 +8227,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_object: /* 0x69 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9099,7 +8243,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_boolean: /* 0x6a */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9116,7 +8259,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_byte: /* 0x6b */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9133,7 +8275,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_char: /* 0x6c */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9150,7 +8291,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_short: /* 0x6d */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9167,7 +8307,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual: /* 0x6e */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9184,7 +8323,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super: /* 0x6f */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9201,7 +8339,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct: /* 0x70 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9218,7 +8355,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static: /* 0x71 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9235,7 +8371,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface: /* 0x72 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9252,7 +8387,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void_no_barrier: /* 0x73 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9269,7 +8403,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range: /* 0x74 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9286,7 +8419,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super_range: /* 0x75 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9303,7 +8435,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct_range: /* 0x76 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9320,7 +8451,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static_range: /* 0x77 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9337,7 +8467,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface_range: /* 0x78 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9354,7 +8483,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_79: /* 0x79 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9371,7 +8499,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_7a: /* 0x7a */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9388,7 +8515,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_int: /* 0x7b */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9405,7 +8531,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_int: /* 0x7c */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9422,7 +8547,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_long: /* 0x7d */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9439,7 +8563,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_long: /* 0x7e */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9456,7 +8579,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_float: /* 0x7f */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9473,7 +8595,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_double: /* 0x80 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9490,7 +8611,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_long: /* 0x81 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9507,7 +8627,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_float: /* 0x82 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9524,7 +8643,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_double: /* 0x83 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9541,7 +8659,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_int: /* 0x84 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9558,7 +8675,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_float: /* 0x85 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9575,7 +8691,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_double: /* 0x86 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9592,7 +8707,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_int: /* 0x87 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9609,7 +8723,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_long: /* 0x88 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9626,7 +8739,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_double: /* 0x89 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9643,7 +8755,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_int: /* 0x8a */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9660,7 +8771,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_long: /* 0x8b */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9677,7 +8787,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_float: /* 0x8c */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9694,7 +8803,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_byte: /* 0x8d */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9711,7 +8819,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_char: /* 0x8e */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9728,7 +8835,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_short: /* 0x8f */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9745,7 +8851,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int: /* 0x90 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9762,7 +8867,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int: /* 0x91 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9779,7 +8883,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int: /* 0x92 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9796,7 +8899,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int: /* 0x93 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9813,7 +8915,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int: /* 0x94 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9830,7 +8931,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int: /* 0x95 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9847,7 +8947,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int: /* 0x96 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9864,7 +8963,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int: /* 0x97 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9881,7 +8979,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int: /* 0x98 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9898,7 +8995,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int: /* 0x99 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9915,7 +9011,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int: /* 0x9a */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9932,7 +9027,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long: /* 0x9b */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9949,7 +9043,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long: /* 0x9c */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9966,7 +9059,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long: /* 0x9d */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9983,7 +9075,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long: /* 0x9e */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10000,7 +9091,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long: /* 0x9f */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10017,7 +9107,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long: /* 0xa0 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10034,7 +9123,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long: /* 0xa1 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10051,7 +9139,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long: /* 0xa2 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10068,7 +9155,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long: /* 0xa3 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10085,7 +9171,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long: /* 0xa4 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10102,7 +9187,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long: /* 0xa5 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10119,7 +9203,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float: /* 0xa6 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10136,7 +9219,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float: /* 0xa7 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10153,7 +9235,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float: /* 0xa8 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10170,7 +9251,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float: /* 0xa9 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10187,7 +9267,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float: /* 0xaa */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10204,7 +9283,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double: /* 0xab */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10221,7 +9299,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double: /* 0xac */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10238,7 +9315,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double: /* 0xad */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10255,7 +9331,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double: /* 0xae */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10272,7 +9347,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double: /* 0xaf */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10289,7 +9363,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_2addr: /* 0xb0 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10306,7 +9379,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int_2addr: /* 0xb1 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10323,7 +9395,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_2addr: /* 0xb2 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10340,7 +9411,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_2addr: /* 0xb3 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10357,7 +9427,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_2addr: /* 0xb4 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10374,7 +9443,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_2addr: /* 0xb5 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10391,7 +9459,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_2addr: /* 0xb6 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10408,7 +9475,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_2addr: /* 0xb7 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10425,7 +9491,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_2addr: /* 0xb8 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10442,7 +9507,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_2addr: /* 0xb9 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10459,7 +9523,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_2addr: /* 0xba */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10476,7 +9539,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long_2addr: /* 0xbb */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10493,7 +9555,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long_2addr: /* 0xbc */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10510,7 +9571,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long_2addr: /* 0xbd */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10527,7 +9587,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long_2addr: /* 0xbe */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10544,7 +9603,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long_2addr: /* 0xbf */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10561,7 +9619,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long_2addr: /* 0xc0 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10578,7 +9635,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long_2addr: /* 0xc1 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10595,7 +9651,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long_2addr: /* 0xc2 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10612,7 +9667,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long_2addr: /* 0xc3 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10629,7 +9683,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long_2addr: /* 0xc4 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10646,7 +9699,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long_2addr: /* 0xc5 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10663,7 +9715,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float_2addr: /* 0xc6 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10680,7 +9731,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float_2addr: /* 0xc7 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10697,7 +9747,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float_2addr: /* 0xc8 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10714,7 +9763,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float_2addr: /* 0xc9 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10731,7 +9779,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float_2addr: /* 0xca */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10748,7 +9795,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double_2addr: /* 0xcb */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10765,7 +9811,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double_2addr: /* 0xcc */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10782,7 +9827,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double_2addr: /* 0xcd */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10799,7 +9843,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double_2addr: /* 0xce */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10816,7 +9859,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double_2addr: /* 0xcf */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10833,7 +9875,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit16: /* 0xd0 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10850,7 +9891,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int: /* 0xd1 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10867,7 +9907,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit16: /* 0xd2 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10884,7 +9923,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit16: /* 0xd3 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10901,7 +9939,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit16: /* 0xd4 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10918,7 +9955,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit16: /* 0xd5 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10935,7 +9971,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit16: /* 0xd6 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10952,7 +9987,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit16: /* 0xd7 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10969,7 +10003,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit8: /* 0xd8 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10986,7 +10019,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int_lit8: /* 0xd9 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11003,7 +10035,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit8: /* 0xda */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11020,7 +10051,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit8: /* 0xdb */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11037,7 +10067,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit8: /* 0xdc */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11054,7 +10083,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit8: /* 0xdd */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11071,7 +10099,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit8: /* 0xde */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11088,7 +10115,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit8: /* 0xdf */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11105,7 +10131,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_lit8: /* 0xe0 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11122,7 +10147,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_lit8: /* 0xe1 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11139,7 +10163,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_lit8: /* 0xe2 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11156,7 +10179,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_quick: /* 0xe3 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11173,7 +10195,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide_quick: /* 0xe4 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11190,7 +10211,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object_quick: /* 0xe5 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11207,7 +10227,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_quick: /* 0xe6 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11224,7 +10243,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide_quick: /* 0xe7 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11241,7 +10259,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object_quick: /* 0xe8 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11258,7 +10275,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11275,7 +10291,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11292,7 +10307,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean_quick: /* 0xeb */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11309,7 +10323,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte_quick: /* 0xec */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11326,7 +10339,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char_quick: /* 0xed */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11343,7 +10355,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short_quick: /* 0xee */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11360,7 +10371,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean_quick: /* 0xef */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11377,7 +10387,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte_quick: /* 0xf0 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11394,7 +10403,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char_quick: /* 0xf1 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11411,7 +10419,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short_quick: /* 0xf2 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11428,7 +10435,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f3: /* 0xf3 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11445,7 +10451,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f4: /* 0xf4 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11462,7 +10467,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f5: /* 0xf5 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11479,7 +10483,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f6: /* 0xf6 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11496,7 +10499,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f7: /* 0xf7 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11513,7 +10515,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f8: /* 0xf8 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11530,7 +10531,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f9: /* 0xf9 */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11547,7 +10547,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic: /* 0xfa */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11564,7 +10563,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11581,7 +10579,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom: /* 0xfc */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11598,7 +10595,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom_range: /* 0xfd */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11615,7 +10611,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_handle: /* 0xfe */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11632,7 +10627,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_type: /* 0xff */
-/* File: arm64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11647,16 +10641,12 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
     b      MterpCheckBefore     // (self, shadow_frame, dex_pc_ptr) Note: tail call.
 
     .balign 128
-/* File: arm64/instruction_end_alt.S */
 
     .type artMterpAsmAltInstructionEnd, #object
     .hidden artMterpAsmAltInstructionEnd
     .global artMterpAsmAltInstructionEnd
 artMterpAsmAltInstructionEnd:
-
-/* File: arm64/close_cfi.S */
 // Close out the cfi info.  We're treating mterp as a single function.
 
 END ExecuteMterpImpl
 
-
diff --git a/runtime/interpreter/mterp/out/mterp_mips.S b/runtime/interpreter/mterp/out/mterp_mips.S
index 1f5bea0873d62bd8ca262825b82007341c51fee6..f2f3453e0aa70f44a55b9b8432a524ef1268eed1 100644
--- a/runtime/interpreter/mterp/out/mterp_mips.S
+++ b/runtime/interpreter/mterp/out/mterp_mips.S
@@ -1,10 +1,4 @@
-/*
- * This file was generated automatically by gen-mterp.py for 'mips'.
- *
- * --> DO NOT EDIT <--
- */
-
-/* File: mips/header.S */
+/* DO NOT EDIT: This file was generated by gen-mterp.py. */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -670,7 +664,6 @@
 #define STORE64_F(rlo, rhi, rbase) STORE64_off_F(rlo, rhi, rbase, 0)
 #define LOAD64_F(rlo, rhi, rbase) LOAD64_off_F(rlo, rhi, rbase, 0)
 
-
 #define LOAD_base_offMirrorArray_length(rd, rbase) LOAD_RB_OFF(rd, rbase, MIRROR_ARRAY_LENGTH_OFFSET)
 
 #define STACK_STORE(rd, off) sw rd, off(sp)
@@ -732,8 +725,6 @@
 #define LONG_MIN_HIGH           0x80000000
 #define LONG_MIN_AS_FLOAT       0xDF000000
 #define LONG_MIN_AS_DOUBLE_HIGH 0xC3E00000
-
-/* File: mips/entry.S */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -810,16 +801,12 @@ ExecuteMterpImpl:
     GOTO_OPCODE(t0)                        # jump to next instruction
     /* NOTE: no fallthrough */
 
-/* File: mips/instruction_start.S */
-
     .global artMterpAsmInstructionStart
 artMterpAsmInstructionStart = .L_op_nop
     .text
-
 /* ------------------------------ */
     .balign 128
 .L_op_nop: /* 0x00 */
-/* File: mips/op_nop.S */
     FETCH_ADVANCE_INST(1)                  #  advance rPC, load rINST
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
@@ -827,7 +814,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move: /* 0x01 */
-/* File: mips/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     GET_OPB(a1)                            #  a1 <- B from 15:12
@@ -844,7 +830,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_from16: /* 0x02 */
-/* File: mips/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     FETCH(a1, 1)                           #  a1 <- BBBB
@@ -861,7 +846,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_16: /* 0x03 */
-/* File: mips/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     FETCH(a1, 2)                           #  a1 <- BBBB
@@ -878,7 +862,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide: /* 0x04 */
-/* File: mips/op_move_wide.S */
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */
     GET_OPA4(a2)                           #  a2 <- A(+)
@@ -892,7 +875,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_from16: /* 0x05 */
-/* File: mips/op_move_wide_from16.S */
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */
     FETCH(a3, 1)                           #  a3 <- BBBB
@@ -906,7 +888,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_16: /* 0x06 */
-/* File: mips/op_move_wide_16.S */
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */
     FETCH(a3, 2)                           #  a3 <- BBBB
@@ -920,8 +901,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_object: /* 0x07 */
-/* File: mips/op_move_object.S */
-/* File: mips/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     GET_OPB(a1)                            #  a1 <- B from 15:12
@@ -935,12 +914,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG_GOTO(a2, a0, t0)              #  fp[A] <- a2
     .endif
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_from16: /* 0x08 */
-/* File: mips/op_move_object_from16.S */
-/* File: mips/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     FETCH(a1, 1)                           #  a1 <- BBBB
@@ -954,12 +930,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG_GOTO(a2, a0, t0)              #  fp[AA] <- a2
     .endif
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_16: /* 0x09 */
-/* File: mips/op_move_object_16.S */
-/* File: mips/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     FETCH(a1, 2)                           #  a1 <- BBBB
@@ -973,11 +946,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG_GOTO(a2, a0, t0)              #  fp[AAAA] <- a2
     .endif
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_result: /* 0x0a */
-/* File: mips/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     GET_OPA(a2)                            #  a2 <- AA
@@ -994,7 +965,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_wide: /* 0x0b */
-/* File: mips/op_move_result_wide.S */
     /* move-result-wide vAA */
     GET_OPA(a2)                            #  a2 <- AA
     lw    a3, OFF_FP_RESULT_REGISTER(rFP)  #  get pointer to result JType
@@ -1006,8 +976,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_object: /* 0x0c */
-/* File: mips/op_move_result_object.S */
-/* File: mips/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     GET_OPA(a2)                            #  a2 <- AA
@@ -1021,11 +989,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG_GOTO(a0, a2, t0)              #  fp[AA] <- a0
     .endif
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_exception: /* 0x0d */
-/* File: mips/op_move_exception.S */
     /* move-exception vAA */
     GET_OPA(a2)                                 #  a2 <- AA
     lw    a3, THREAD_EXCEPTION_OFFSET(rSELF)    #  get exception obj
@@ -1039,7 +1005,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_void: /* 0x0e */
-/* File: mips/op_return_void.S */
     .extern MterpThreadFenceForConstructor
     JAL(MterpThreadFenceForConstructor)
     lw        ra, THREAD_FLAGS_OFFSET(rSELF)
@@ -1055,7 +1020,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return: /* 0x0f */
-/* File: mips/op_return.S */
     /*
      * Return a 32-bit value.
      *
@@ -1078,7 +1042,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_wide: /* 0x10 */
-/* File: mips/op_return_wide.S */
     /*
      * Return a 64-bit value.
      */
@@ -1099,8 +1062,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_object: /* 0x11 */
-/* File: mips/op_return_object.S */
-/* File: mips/op_return.S */
     /*
      * Return a 32-bit value.
      *
@@ -1120,11 +1081,9 @@ artMterpAsmInstructionStart = .L_op_nop
     move      v1, zero
     b         MterpReturn
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_4: /* 0x12 */
-/* File: mips/op_const_4.S */
     /* const/4 vA, +B */
     sll       a1, rINST, 16                #  a1 <- Bxxx0000
     GET_OPA(a0)                            #  a0 <- A+
@@ -1137,7 +1096,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_16: /* 0x13 */
-/* File: mips/op_const_16.S */
     /* const/16 vAA, +BBBB */
     FETCH_S(a0, 1)                         #  a0 <- ssssBBBB (sign-extended)
     GET_OPA(a3)                            #  a3 <- AA
@@ -1148,7 +1106,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const: /* 0x14 */
-/* File: mips/op_const.S */
     /* const vAA, +BBBBbbbb */
     GET_OPA(a3)                            #  a3 <- AA
     FETCH(a0, 1)                           #  a0 <- bbbb (low)
@@ -1161,7 +1118,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_high16: /* 0x15 */
-/* File: mips/op_const_high16.S */
     /* const/high16 vAA, +BBBB0000 */
     FETCH(a0, 1)                           #  a0 <- 0000BBBB (zero-extended)
     GET_OPA(a3)                            #  a3 <- AA
@@ -1173,7 +1129,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_16: /* 0x16 */
-/* File: mips/op_const_wide_16.S */
     /* const-wide/16 vAA, +BBBB */
     FETCH_S(a0, 1)                         #  a0 <- ssssBBBB (sign-extended)
     GET_OPA(a3)                            #  a3 <- AA
@@ -1185,7 +1140,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_32: /* 0x17 */
-/* File: mips/op_const_wide_32.S */
     /* const-wide/32 vAA, +BBBBbbbb */
     FETCH(a0, 1)                           #  a0 <- 0000bbbb (low)
     GET_OPA(a3)                            #  a3 <- AA
@@ -1199,7 +1153,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide: /* 0x18 */
-/* File: mips/op_const_wide.S */
     /* const-wide vAA, +HHHHhhhhBBBBbbbb */
     FETCH(a0, 1)                           #  a0 <- bbbb (low)
     FETCH(a1, 2)                           #  a1 <- BBBB (low middle)
@@ -1215,7 +1168,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_high16: /* 0x19 */
-/* File: mips/op_const_wide_high16.S */
     /* const-wide/high16 vAA, +BBBB000000000000 */
     FETCH(a1, 1)                           #  a1 <- 0000BBBB (zero-extended)
     GET_OPA(a3)                            #  a3 <- AA
@@ -1228,8 +1180,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_string: /* 0x1a */
-/* File: mips/op_const_string.S */
-/* File: mips/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -1247,11 +1197,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                 # extract opcode from rINST
     GOTO_OPCODE(t0)                     # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_string_jumbo: /* 0x1b */
-/* File: mips/op_const_string_jumbo.S */
     /* const/string vAA, string@BBBBBBBB */
     EXPORT_PC()
     FETCH(a0, 1)                        # a0 <- bbbb (low)
@@ -1270,8 +1218,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_class: /* 0x1c */
-/* File: mips/op_const_class.S */
-/* File: mips/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -1289,11 +1235,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                 # extract opcode from rINST
     GOTO_OPCODE(t0)                     # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_enter: /* 0x1d */
-/* File: mips/op_monitor_enter.S */
     /*
      * Synchronize on an object.
      */
@@ -1311,7 +1255,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_exit: /* 0x1e */
-/* File: mips/op_monitor_exit.S */
     /*
      * Unlock an object.
      *
@@ -1333,7 +1276,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_check_cast: /* 0x1f */
-/* File: mips/op_check_cast.S */
     /*
      * Check to see if a cast from one class to another is allowed.
      */
@@ -1354,7 +1296,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_instance_of: /* 0x20 */
-/* File: mips/op_instance_of.S */
     /*
      * Check to see if an object reference is an instance of a class.
      *
@@ -1380,7 +1321,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_array_length: /* 0x21 */
-/* File: mips/op_array_length.S */
     /*
      * Return the length of an array.
      */
@@ -1398,7 +1338,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_instance: /* 0x22 */
-/* File: mips/op_new_instance.S */
     /*
      * Create a new instance of a class.
      */
@@ -1416,7 +1355,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_array: /* 0x23 */
-/* File: mips/op_new_array.S */
     /*
      * Allocate an array of objects, specified with the array class
      * and a count.
@@ -1439,7 +1377,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array: /* 0x24 */
-/* File: mips/op_filled_new_array.S */
     /*
      * Create a new array with elements filled from registers.
      *
@@ -1461,8 +1398,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array_range: /* 0x25 */
-/* File: mips/op_filled_new_array_range.S */
-/* File: mips/op_filled_new_array.S */
     /*
      * Create a new array with elements filled from registers.
      *
@@ -1481,11 +1416,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_fill_array_data: /* 0x26 */
-/* File: mips/op_fill_array_data.S */
     /* fill-array-data vAA, +BBBBBBBB */
     EXPORT_PC()
     FETCH(a1, 1)                           #  a1 <- bbbb (lo)
@@ -1503,7 +1436,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_throw: /* 0x27 */
-/* File: mips/op_throw.S */
     /*
      * Throw an exception object in the current thread.
      */
@@ -1519,7 +1451,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto: /* 0x28 */
-/* File: mips/op_goto.S */
     /*
      * Unconditional branch, 8-bit offset.
      *
@@ -1534,7 +1465,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_16: /* 0x29 */
-/* File: mips/op_goto_16.S */
     /*
      * Unconditional branch, 16-bit offset.
      *
@@ -1548,7 +1478,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_32: /* 0x2a */
-/* File: mips/op_goto_32.S */
     /*
      * Unconditional branch, 32-bit offset.
      *
@@ -1567,7 +1496,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_packed_switch: /* 0x2b */
-/* File: mips/op_packed_switch.S */
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
@@ -1591,8 +1519,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_sparse_switch: /* 0x2c */
-/* File: mips/op_sparse_switch.S */
-/* File: mips/op_packed_switch.S */
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
@@ -1613,11 +1539,9 @@ artMterpAsmInstructionStart = .L_op_nop
     move      rINST, v0
     b         MterpCommonTakenBranchNoFlags
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_float: /* 0x2d */
-/* File: mips/op_cmpl_float.S */
     /*
      * Compare two floating-point values. Puts 0(==), 1(>), or -1(<)
      * into the destination register based on the comparison results.
@@ -1671,8 +1595,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_float: /* 0x2e */
-/* File: mips/op_cmpg_float.S */
-/* File: mips/op_cmpl_float.S */
     /*
      * Compare two floating-point values. Puts 0(==), 1(>), or -1(<)
      * into the destination register based on the comparison results.
@@ -1723,11 +1645,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(rTEMP, rOBJ, t0)         #  vAA <- rTEMP
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_double: /* 0x2f */
-/* File: mips/op_cmpl_double.S */
     /*
      * Compare two floating-point values. Puts 0(==), 1(>), or -1(<)
      * into the destination register based on the comparison results.
@@ -1783,8 +1703,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_double: /* 0x30 */
-/* File: mips/op_cmpg_double.S */
-/* File: mips/op_cmpl_double.S */
     /*
      * Compare two floating-point values. Puts 0(==), 1(>), or -1(<)
      * into the destination register based on the comparison results.
@@ -1837,11 +1755,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(rTEMP, rOBJ, t0)         #  vAA <- rTEMP
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmp_long: /* 0x31 */
-/* File: mips/op_cmp_long.S */
     /*
      * Compare two 64-bit values
      *    x = y     return  0
@@ -1880,8 +1796,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_if_eq: /* 0x32 */
-/* File: mips/op_if_eq.S */
-/* File: mips/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1901,12 +1815,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ne: /* 0x33 */
-/* File: mips/op_if_ne.S */
-/* File: mips/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1926,12 +1837,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lt: /* 0x34 */
-/* File: mips/op_if_lt.S */
-/* File: mips/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1951,12 +1859,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ge: /* 0x35 */
-/* File: mips/op_if_ge.S */
-/* File: mips/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -1976,12 +1881,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gt: /* 0x36 */
-/* File: mips/op_if_gt.S */
-/* File: mips/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -2001,12 +1903,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_le: /* 0x37 */
-/* File: mips/op_if_le.S */
-/* File: mips/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -2026,12 +1925,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_eqz: /* 0x38 */
-/* File: mips/op_if_eqz.S */
-/* File: mips/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -2049,12 +1945,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_nez: /* 0x39 */
-/* File: mips/op_if_nez.S */
-/* File: mips/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -2072,12 +1965,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ltz: /* 0x3a */
-/* File: mips/op_if_ltz.S */
-/* File: mips/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -2095,12 +1985,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gez: /* 0x3b */
-/* File: mips/op_if_gez.S */
-/* File: mips/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -2118,12 +2005,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gtz: /* 0x3c */
-/* File: mips/op_if_gtz.S */
-/* File: mips/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -2141,12 +2025,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lez: /* 0x3d */
-/* File: mips/op_if_lez.S */
-/* File: mips/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform.
@@ -2164,77 +2045,57 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     GOTO_OPCODE(t0)                        #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3e: /* 0x3e */
-/* File: mips/op_unused_3e.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3f: /* 0x3f */
-/* File: mips/op_unused_3f.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_40: /* 0x40 */
-/* File: mips/op_unused_40.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_41: /* 0x41 */
-/* File: mips/op_unused_41.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_42: /* 0x42 */
-/* File: mips/op_unused_42.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_43: /* 0x43 */
-/* File: mips/op_unused_43.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget: /* 0x44 */
-/* File: mips/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -2266,7 +2127,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_wide: /* 0x45 */
-/* File: mips/op_aget_wide.S */
     /*
      * Array get, 64 bits.  vAA <- vBB[vCC].
      *
@@ -2293,7 +2153,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_object: /* 0x46 */
-/* File: mips/op_aget_object.S */
     /*
      * Array object get.  vAA <- vBB[vCC].
      *
@@ -2317,8 +2176,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_boolean: /* 0x47 */
-/* File: mips/op_aget_boolean.S */
-/* File: mips/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -2347,12 +2204,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a2, rOBJ, t0)            #  vAA <- a2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_byte: /* 0x48 */
-/* File: mips/op_aget_byte.S */
-/* File: mips/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -2381,12 +2235,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a2, rOBJ, t0)            #  vAA <- a2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_char: /* 0x49 */
-/* File: mips/op_aget_char.S */
-/* File: mips/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -2415,12 +2266,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a2, rOBJ, t0)            #  vAA <- a2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_short: /* 0x4a */
-/* File: mips/op_aget_short.S */
-/* File: mips/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -2449,11 +2297,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a2, rOBJ, t0)            #  vAA <- a2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput: /* 0x4b */
-/* File: mips/op_aput.S */
 
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
@@ -2484,7 +2330,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_wide: /* 0x4c */
-/* File: mips/op_aput_wide.S */
     /*
      * Array put, 64 bits.  vBB[vCC] <- vAA.
      */
@@ -2513,7 +2358,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_object: /* 0x4d */
-/* File: mips/op_aput_object.S */
     /*
      * Store an object into an array.  vBB[vCC] <- vAA.
      *
@@ -2532,8 +2376,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_boolean: /* 0x4e */
-/* File: mips/op_aput_boolean.S */
-/* File: mips/op_aput.S */
 
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
@@ -2561,12 +2403,9 @@ artMterpAsmInstructionStart = .L_op_nop
     sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0)            #  vBB[vCC] <- a2
     JR(t0)                                 #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_byte: /* 0x4f */
-/* File: mips/op_aput_byte.S */
-/* File: mips/op_aput.S */
 
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
@@ -2594,12 +2433,9 @@ artMterpAsmInstructionStart = .L_op_nop
     sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0)            #  vBB[vCC] <- a2
     JR(t0)                                 #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_char: /* 0x50 */
-/* File: mips/op_aput_char.S */
-/* File: mips/op_aput.S */
 
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
@@ -2627,12 +2463,9 @@ artMterpAsmInstructionStart = .L_op_nop
     sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0)            #  vBB[vCC] <- a2
     JR(t0)                                 #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_short: /* 0x51 */
-/* File: mips/op_aput_short.S */
-/* File: mips/op_aput.S */
 
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
@@ -2660,284 +2493,149 @@ artMterpAsmInstructionStart = .L_op_nop
     sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0)            #  vBB[vCC] <- a2
     JR(t0)                                 #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget: /* 0x52 */
-/* File: mips/op_iget.S */
-/* File: mips/field.S */
 TODO
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide: /* 0x53 */
-/* File: mips/op_iget_wide.S */
-/* File: mips/op_iget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object: /* 0x54 */
-/* File: mips/op_iget_object.S */
-/* File: mips/op_iget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean: /* 0x55 */
-/* File: mips/op_iget_boolean.S */
-/* File: mips/op_iget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte: /* 0x56 */
-/* File: mips/op_iget_byte.S */
-/* File: mips/op_iget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char: /* 0x57 */
-/* File: mips/op_iget_char.S */
-/* File: mips/op_iget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short: /* 0x58 */
-/* File: mips/op_iget_short.S */
-/* File: mips/op_iget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput: /* 0x59 */
-/* File: mips/op_iput.S */
-/* File: mips/field.S */
 TODO
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide: /* 0x5a */
-/* File: mips/op_iput_wide.S */
-/* File: mips/op_iput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object: /* 0x5b */
-/* File: mips/op_iput_object.S */
-/* File: mips/op_iput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean: /* 0x5c */
-/* File: mips/op_iput_boolean.S */
-/* File: mips/op_iput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte: /* 0x5d */
-/* File: mips/op_iput_byte.S */
-/* File: mips/op_iput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char: /* 0x5e */
-/* File: mips/op_iput_char.S */
-/* File: mips/op_iput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short: /* 0x5f */
-/* File: mips/op_iput_short.S */
-/* File: mips/op_iput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget: /* 0x60 */
-/* File: mips/op_sget.S */
-/* File: mips/field.S */
 TODO
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_wide: /* 0x61 */
-/* File: mips/op_sget_wide.S */
-/* File: mips/op_sget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_object: /* 0x62 */
-/* File: mips/op_sget_object.S */
-/* File: mips/op_sget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_boolean: /* 0x63 */
-/* File: mips/op_sget_boolean.S */
-/* File: mips/op_sget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_byte: /* 0x64 */
-/* File: mips/op_sget_byte.S */
-/* File: mips/op_sget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_char: /* 0x65 */
-/* File: mips/op_sget_char.S */
-/* File: mips/op_sget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_short: /* 0x66 */
-/* File: mips/op_sget_short.S */
-/* File: mips/op_sget.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput: /* 0x67 */
-/* File: mips/op_sput.S */
-/* File: mips/field.S */
 TODO
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_wide: /* 0x68 */
-/* File: mips/op_sput_wide.S */
-/* File: mips/op_sput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_object: /* 0x69 */
-/* File: mips/op_sput_object.S */
-/* File: mips/op_sput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_boolean: /* 0x6a */
-/* File: mips/op_sput_boolean.S */
-/* File: mips/op_sput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_byte: /* 0x6b */
-/* File: mips/op_sput_byte.S */
-/* File: mips/op_sput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_char: /* 0x6c */
-/* File: mips/op_sput_char.S */
-/* File: mips/op_sput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_short: /* 0x6d */
-/* File: mips/op_sput_short.S */
-/* File: mips/op_sput.S */
-/* File: mips/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual: /* 0x6e */
-/* File: mips/op_invoke_virtual.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2957,12 +2655,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super: /* 0x6f */
-/* File: mips/op_invoke_super.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2982,12 +2677,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct: /* 0x70 */
-/* File: mips/op_invoke_direct.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3007,12 +2699,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static: /* 0x71 */
-/* File: mips/op_invoke_static.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3032,12 +2721,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface: /* 0x72 */
-/* File: mips/op_invoke_interface.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3057,11 +2743,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_return_void_no_barrier: /* 0x73 */
-/* File: mips/op_return_void_no_barrier.S */
     lw     ra, THREAD_FLAGS_OFFSET(rSELF)
     move   a0, rSELF
     and    ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
@@ -3075,8 +2759,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range: /* 0x74 */
-/* File: mips/op_invoke_virtual_range.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3096,12 +2778,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super_range: /* 0x75 */
-/* File: mips/op_invoke_super_range.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3121,12 +2800,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct_range: /* 0x76 */
-/* File: mips/op_invoke_direct_range.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3146,12 +2822,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static_range: /* 0x77 */
-/* File: mips/op_invoke_static_range.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3171,12 +2844,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface_range: /* 0x78 */
-/* File: mips/op_invoke_interface_range.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -3196,34 +2866,25 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_79: /* 0x79 */
-/* File: mips/op_unused_79.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_7a: /* 0x7a */
-/* File: mips/op_unused_7a.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_int: /* 0x7b */
-/* File: mips/op_neg_int.S */
-/* File: mips/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result0 = op a0".
@@ -3242,12 +2903,9 @@ TODO
     GET_INST_OPCODE(t1)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, t0, t1)        #  vA <- result0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_int: /* 0x7c */
-/* File: mips/op_not_int.S */
-/* File: mips/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result0 = op a0".
@@ -3266,12 +2924,9 @@ TODO
     GET_INST_OPCODE(t1)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, t0, t1)        #  vA <- result0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_long: /* 0x7d */
-/* File: mips/op_neg_long.S */
-/* File: mips/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result0/result1 = op a0/a1".
@@ -3290,12 +2945,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(v0, v1, rOBJ, t0)   #  vA/vA+1 <- a0/a1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_long: /* 0x7e */
-/* File: mips/op_not_long.S */
-/* File: mips/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result0/result1 = op a0/a1".
@@ -3314,12 +2966,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(a0, a1, rOBJ, t0)   #  vA/vA+1 <- a0/a1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_float: /* 0x7f */
-/* File: mips/op_neg_float.S */
-/* File: mips/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result0 = op a0".
@@ -3338,12 +2987,9 @@ TODO
     GET_INST_OPCODE(t1)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, t0, t1)        #  vA <- result0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_double: /* 0x80 */
-/* File: mips/op_neg_double.S */
-/* File: mips/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result0/result1 = op a0/a1".
@@ -3362,12 +3008,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(a0, a1, rOBJ, t0)   #  vA/vA+1 <- a0/a1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_long: /* 0x81 */
-/* File: mips/op_int_to_long.S */
-/* File: mips/unopWider.S */
     /*
      * Generic 32bit-to-64bit unary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result0/result1 = op a0".
@@ -3384,12 +3027,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(a0, a1, rOBJ, t0)   #  vA/vA+1 <- a0/a1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_float: /* 0x82 */
-/* File: mips/op_int_to_float.S */
-/* File: mips/funop.S */
     /*
      * Generic 32-bit floating-point unary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = op fa0".
@@ -3406,12 +3046,9 @@ TODO
     GET_INST_OPCODE(t1)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t1)         #  vA <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_double: /* 0x83 */
-/* File: mips/op_int_to_double.S */
-/* File: mips/funopWider.S */
     /*
      * Generic 32bit-to-64bit floating-point unary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = op fa0".
@@ -3427,13 +3064,10 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) #  vA/vA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_int: /* 0x84 */
-/* File: mips/op_long_to_int.S */
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-/* File: mips/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     GET_OPB(a1)                            #  a1 <- B from 15:12
@@ -3447,11 +3081,9 @@ TODO
     SET_VREG_GOTO(a2, a0, t0)              #  fp[A] <- a2
     .endif
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_float: /* 0x85 */
-/* File: mips/op_long_to_float.S */
     /*
      * long-to-float
      */
@@ -3476,7 +3108,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_double: /* 0x86 */
-/* File: mips/op_long_to_double.S */
     /*
      * long-to-double
      */
@@ -3501,7 +3132,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_int: /* 0x87 */
-/* File: mips/op_float_to_int.S */
     /*
      * float-to-int
      *
@@ -3535,7 +3165,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_long: /* 0x88 */
-/* File: mips/op_float_to_long.S */
     /*
      * float-to-long
      *
@@ -3580,8 +3209,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_double: /* 0x89 */
-/* File: mips/op_float_to_double.S */
-/* File: mips/funopWider.S */
     /*
      * Generic 32bit-to-64bit floating-point unary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = op fa0".
@@ -3597,11 +3224,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) #  vA/vA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_int: /* 0x8a */
-/* File: mips/op_double_to_int.S */
     /*
      * double-to-int
      *
@@ -3637,7 +3262,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_long: /* 0x8b */
-/* File: mips/op_double_to_long.S */
     /*
      * double-to-long
      *
@@ -3684,8 +3308,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_float: /* 0x8c */
-/* File: mips/op_double_to_float.S */
-/* File: mips/unopNarrower.S */
     /*
      * Generic 64bit-to-32bit floating-point unary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = op fa0".
@@ -3702,12 +3324,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t0)         #  vA <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_byte: /* 0x8d */
-/* File: mips/op_int_to_byte.S */
-/* File: mips/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result0 = op a0".
@@ -3726,12 +3345,9 @@ TODO
     GET_INST_OPCODE(t1)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, t0, t1)        #  vA <- result0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_char: /* 0x8e */
-/* File: mips/op_int_to_char.S */
-/* File: mips/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result0 = op a0".
@@ -3750,12 +3366,9 @@ TODO
     GET_INST_OPCODE(t1)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, t0, t1)        #  vA <- result0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_short: /* 0x8f */
-/* File: mips/op_int_to_short.S */
-/* File: mips/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result0 = op a0".
@@ -3774,12 +3387,9 @@ TODO
     GET_INST_OPCODE(t1)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, t0, t1)        #  vA <- result0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int: /* 0x90 */
-/* File: mips/op_add_int.S */
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3812,12 +3422,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int: /* 0x91 */
-/* File: mips/op_sub_int.S */
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3850,12 +3457,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int: /* 0x92 */
-/* File: mips/op_mul_int.S */
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3888,13 +3492,10 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int: /* 0x93 */
-/* File: mips/op_div_int.S */
 #ifdef MIPS32REVGE6
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3926,9 +3527,7 @@ TODO
     div a0, a0, a1                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
-
 #else
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3960,15 +3559,12 @@ TODO
     mflo a0                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
-
 #endif
 
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int: /* 0x94 */
-/* File: mips/op_rem_int.S */
 #ifdef MIPS32REVGE6
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4000,9 +3596,7 @@ TODO
     mod a0, a0, a1                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
-
 #else
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4034,14 +3628,11 @@ TODO
     mfhi a0                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
-
 #endif
 
 /* ------------------------------ */
     .balign 128
 .L_op_and_int: /* 0x95 */
-/* File: mips/op_and_int.S */
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4074,12 +3665,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int: /* 0x96 */
-/* File: mips/op_or_int.S */
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4112,12 +3700,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int: /* 0x97 */
-/* File: mips/op_xor_int.S */
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4150,12 +3735,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int: /* 0x98 */
-/* File: mips/op_shl_int.S */
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4188,12 +3770,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int: /* 0x99 */
-/* File: mips/op_shr_int.S */
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4226,12 +3805,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int: /* 0x9a */
-/* File: mips/op_ushr_int.S */
-/* File: mips/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4264,11 +3840,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long: /* 0x9b */
-/* File: mips/op_add_long.S */
 /*
  *  The compiler generates the following sequence for
  *  [v1 v0] =  [a1 a0] + [a3 a2];
@@ -4277,7 +3851,6 @@ TODO
  *    sltu v1,v0,a2
  *    addu v1,v1,a1
  */
-/* File: mips/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -4312,11 +3885,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(v0, v1, rOBJ, t0)   #  vAA/vAA+1 <- v0/v1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long: /* 0x9c */
-/* File: mips/op_sub_long.S */
 /*
  * For little endian the code sequence looks as follows:
  *    subu    v0,a0,a2
@@ -4324,7 +3895,6 @@ TODO
  *    sltu    a0,a0,v0
  *    subu    v1,v1,a0
  */
-/* File: mips/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -4359,11 +3929,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(v0, v1, rOBJ, t0)   #  vAA/vAA+1 <- v0/v1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long: /* 0x9d */
-/* File: mips/op_mul_long.S */
     /*
      * Signed 64-bit integer multiply.
      *         a1   a0
@@ -4405,8 +3973,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_div_long: /* 0x9e */
-/* File: mips/op_div_long.S */
-/* File: mips/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -4441,12 +4007,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(v0, v1, rOBJ, t0)   #  vAA/vAA+1 <- v0/v1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long: /* 0x9f */
-/* File: mips/op_rem_long.S */
-/* File: mips/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -4481,12 +4044,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(v0, v1, rOBJ, t0)   #  vAA/vAA+1 <- v0/v1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long: /* 0xa0 */
-/* File: mips/op_and_long.S */
-/* File: mips/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -4521,12 +4081,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(a0, a1, rOBJ, t0)   #  vAA/vAA+1 <- a0/a1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long: /* 0xa1 */
-/* File: mips/op_or_long.S */
-/* File: mips/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -4561,12 +4118,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(a0, a1, rOBJ, t0)   #  vAA/vAA+1 <- a0/a1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long: /* 0xa2 */
-/* File: mips/op_xor_long.S */
-/* File: mips/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -4601,11 +4155,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(a0, a1, rOBJ, t0)   #  vAA/vAA+1 <- a0/a1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long: /* 0xa3 */
-/* File: mips/op_shl_long.S */
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -4637,7 +4189,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long: /* 0xa4 */
-/* File: mips/op_shr_long.S */
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -4668,7 +4219,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long: /* 0xa5 */
-/* File: mips/op_ushr_long.S */
     /*
      * Long integer shift.  This is different from the generic 32/64-bit
      * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -4700,8 +4250,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_add_float: /* 0xa6 */
-/* File: mips/op_add_float.S */
-/* File: mips/fbinop.S */
     /*
      * Generic 32-bit binary float operation.
      *
@@ -4721,12 +4269,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t0)         #  vAA <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float: /* 0xa7 */
-/* File: mips/op_sub_float.S */
-/* File: mips/fbinop.S */
     /*
      * Generic 32-bit binary float operation.
      *
@@ -4746,12 +4291,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t0)         #  vAA <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float: /* 0xa8 */
-/* File: mips/op_mul_float.S */
-/* File: mips/fbinop.S */
     /*
      * Generic 32-bit binary float operation.
      *
@@ -4771,12 +4313,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t0)         #  vAA <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float: /* 0xa9 */
-/* File: mips/op_div_float.S */
-/* File: mips/fbinop.S */
     /*
      * Generic 32-bit binary float operation.
      *
@@ -4796,12 +4335,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t0)         #  vAA <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float: /* 0xaa */
-/* File: mips/op_rem_float.S */
-/* File: mips/fbinop.S */
     /*
      * Generic 32-bit binary float operation.
      *
@@ -4821,12 +4357,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t0)         #  vAA <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_double: /* 0xab */
-/* File: mips/op_add_double.S */
-/* File: mips/fbinopWide.S */
     /*
      * Generic 64-bit floating-point binary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = fa0 op fa1".
@@ -4851,12 +4384,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0)  #  vAA/vAA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double: /* 0xac */
-/* File: mips/op_sub_double.S */
-/* File: mips/fbinopWide.S */
     /*
      * Generic 64-bit floating-point binary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = fa0 op fa1".
@@ -4881,12 +4411,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0)  #  vAA/vAA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double: /* 0xad */
-/* File: mips/op_mul_double.S */
-/* File: mips/fbinopWide.S */
     /*
      * Generic 64-bit floating-point binary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = fa0 op fa1".
@@ -4911,12 +4438,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0)  #  vAA/vAA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double: /* 0xae */
-/* File: mips/op_div_double.S */
-/* File: mips/fbinopWide.S */
     /*
      * Generic 64-bit floating-point binary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = fa0 op fa1".
@@ -4941,12 +4465,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0)  #  vAA/vAA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double: /* 0xaf */
-/* File: mips/op_rem_double.S */
-/* File: mips/fbinopWide.S */
     /*
      * Generic 64-bit floating-point binary operation.  Provide an "instr"
      * line that specifies an instruction that performs "fv0 = fa0 op fa1".
@@ -4971,12 +4492,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0)  #  vAA/vAA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_2addr: /* 0xb0 */
-/* File: mips/op_add_int_2addr.S */
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5005,12 +4523,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int_2addr: /* 0xb1 */
-/* File: mips/op_sub_int_2addr.S */
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5039,12 +4554,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_2addr: /* 0xb2 */
-/* File: mips/op_mul_int_2addr.S */
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5073,13 +4585,10 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_2addr: /* 0xb3 */
-/* File: mips/op_div_int_2addr.S */
 #ifdef MIPS32REVGE6
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5107,9 +4616,7 @@ TODO
     div a0, a0, a1                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
-
 #else
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5137,15 +4644,12 @@ TODO
     mflo a0                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
-
 #endif
 
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_2addr: /* 0xb4 */
-/* File: mips/op_rem_int_2addr.S */
 #ifdef MIPS32REVGE6
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5173,9 +4677,7 @@ TODO
     mod a0, a0, a1                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
-
 #else
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5203,14 +4705,11 @@ TODO
     mfhi a0                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
-
 #endif
 
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_2addr: /* 0xb5 */
-/* File: mips/op_and_int_2addr.S */
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5239,12 +4738,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_2addr: /* 0xb6 */
-/* File: mips/op_or_int_2addr.S */
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5273,12 +4769,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_2addr: /* 0xb7 */
-/* File: mips/op_xor_int_2addr.S */
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5307,12 +4800,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_2addr: /* 0xb8 */
-/* File: mips/op_shl_int_2addr.S */
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5341,12 +4831,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_2addr: /* 0xb9 */
-/* File: mips/op_shr_int_2addr.S */
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5375,12 +4862,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_2addr: /* 0xba */
-/* File: mips/op_ushr_int_2addr.S */
-/* File: mips/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5409,15 +4893,12 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long_2addr: /* 0xbb */
-/* File: mips/op_add_long_2addr.S */
 /*
  * See op_add_long.S for details
  */
-/* File: mips/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -5448,15 +4929,12 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(v0, v1, rOBJ, t0)   #  vA/vA+1 <- v0/v1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long_2addr: /* 0xbc */
-/* File: mips/op_sub_long_2addr.S */
 /*
  * See op_sub_long.S for more details
  */
-/* File: mips/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -5487,11 +4965,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(v0, v1, rOBJ, t0)   #  vA/vA+1 <- v0/v1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long_2addr: /* 0xbd */
-/* File: mips/op_mul_long_2addr.S */
     /*
      * See op_mul_long.S for more details
      */
@@ -5525,8 +5001,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_div_long_2addr: /* 0xbe */
-/* File: mips/op_div_long_2addr.S */
-/* File: mips/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -5557,12 +5031,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(v0, v1, rOBJ, t0)   #  vA/vA+1 <- v0/v1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long_2addr: /* 0xbf */
-/* File: mips/op_rem_long_2addr.S */
-/* File: mips/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -5593,12 +5064,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(v0, v1, rOBJ, t0)   #  vA/vA+1 <- v0/v1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long_2addr: /* 0xc0 */
-/* File: mips/op_and_long_2addr.S */
-/* File: mips/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -5629,12 +5097,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(a0, a1, rOBJ, t0)   #  vA/vA+1 <- a0/a1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long_2addr: /* 0xc1 */
-/* File: mips/op_or_long_2addr.S */
-/* File: mips/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -5665,12 +5130,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(a0, a1, rOBJ, t0)   #  vA/vA+1 <- a0/a1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long_2addr: /* 0xc2 */
-/* File: mips/op_xor_long_2addr.S */
-/* File: mips/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0-a1 op a2-a3".
@@ -5701,11 +5163,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(a0, a1, rOBJ, t0)   #  vA/vA+1 <- a0/a1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long_2addr: /* 0xc3 */
-/* File: mips/op_shl_long_2addr.S */
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
@@ -5733,7 +5193,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long_2addr: /* 0xc4 */
-/* File: mips/op_shr_long_2addr.S */
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
@@ -5760,7 +5219,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long_2addr: /* 0xc5 */
-/* File: mips/op_ushr_long_2addr.S */
     /*
      * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
      * 32-bit shift distance.
@@ -5788,8 +5246,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_add_float_2addr: /* 0xc6 */
-/* File: mips/op_add_float_2addr.S */
-/* File: mips/fbinop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr"
      * that specifies an instruction that performs "fv0 = fa0 op fa1".
@@ -5809,12 +5265,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t0)         #  vA <- result
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float_2addr: /* 0xc7 */
-/* File: mips/op_sub_float_2addr.S */
-/* File: mips/fbinop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr"
      * that specifies an instruction that performs "fv0 = fa0 op fa1".
@@ -5834,12 +5287,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t0)         #  vA <- result
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float_2addr: /* 0xc8 */
-/* File: mips/op_mul_float_2addr.S */
-/* File: mips/fbinop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr"
      * that specifies an instruction that performs "fv0 = fa0 op fa1".
@@ -5859,12 +5309,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t0)         #  vA <- result
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float_2addr: /* 0xc9 */
-/* File: mips/op_div_float_2addr.S */
-/* File: mips/fbinop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr"
      * that specifies an instruction that performs "fv0 = fa0 op fa1".
@@ -5884,12 +5331,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t0)         #  vA <- result
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float_2addr: /* 0xca */
-/* File: mips/op_rem_float_2addr.S */
-/* File: mips/fbinop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr"
      * that specifies an instruction that performs "fv0 = fa0 op fa1".
@@ -5909,12 +5353,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_F_GOTO(fv0, rOBJ, t0)         #  vA <- result
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_double_2addr: /* 0xcb */
-/* File: mips/op_add_double_2addr.S */
-/* File: mips/fbinopWide2addr.S */
     /*
      * Generic 64-bit floating-point "/2addr" binary operation.
      * Provide an "instr" line that specifies an instruction that
@@ -5937,12 +5378,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0)  #  vA/vA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double_2addr: /* 0xcc */
-/* File: mips/op_sub_double_2addr.S */
-/* File: mips/fbinopWide2addr.S */
     /*
      * Generic 64-bit floating-point "/2addr" binary operation.
      * Provide an "instr" line that specifies an instruction that
@@ -5965,12 +5403,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0)  #  vA/vA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double_2addr: /* 0xcd */
-/* File: mips/op_mul_double_2addr.S */
-/* File: mips/fbinopWide2addr.S */
     /*
      * Generic 64-bit floating-point "/2addr" binary operation.
      * Provide an "instr" line that specifies an instruction that
@@ -5993,12 +5428,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0)  #  vA/vA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double_2addr: /* 0xce */
-/* File: mips/op_div_double_2addr.S */
-/* File: mips/fbinopWide2addr.S */
     /*
      * Generic 64-bit floating-point "/2addr" binary operation.
      * Provide an "instr" line that specifies an instruction that
@@ -6021,12 +5453,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0)  #  vA/vA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double_2addr: /* 0xcf */
-/* File: mips/op_rem_double_2addr.S */
-/* File: mips/fbinopWide2addr.S */
     /*
      * Generic 64-bit floating-point "/2addr" binary operation.
      * Provide an "instr" line that specifies an instruction that
@@ -6049,12 +5478,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0)  #  vA/vA+1 <- fv0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit16: /* 0xd0 */
-/* File: mips/op_add_int_lit16.S */
-/* File: mips/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6083,13 +5509,10 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int: /* 0xd1 */
-/* File: mips/op_rsub_int.S */
 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
-/* File: mips/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6118,12 +5541,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit16: /* 0xd2 */
-/* File: mips/op_mul_int_lit16.S */
-/* File: mips/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6152,13 +5572,10 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit16: /* 0xd3 */
-/* File: mips/op_div_int_lit16.S */
 #ifdef MIPS32REVGE6
-/* File: mips/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6186,9 +5603,7 @@ TODO
     div a0, a0, a1                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
-
 #else
-/* File: mips/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6216,15 +5631,12 @@ TODO
     mflo a0                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
-
 #endif
 
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit16: /* 0xd4 */
-/* File: mips/op_rem_int_lit16.S */
 #ifdef MIPS32REVGE6
-/* File: mips/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6252,9 +5664,7 @@ TODO
     mod a0, a0, a1                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
-
 #else
-/* File: mips/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6282,14 +5692,11 @@ TODO
     mfhi a0                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
-
 #endif
 
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit16: /* 0xd5 */
-/* File: mips/op_and_int_lit16.S */
-/* File: mips/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6318,12 +5725,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit16: /* 0xd6 */
-/* File: mips/op_or_int_lit16.S */
-/* File: mips/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6352,12 +5756,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit16: /* 0xd7 */
-/* File: mips/op_xor_int_lit16.S */
-/* File: mips/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6386,12 +5787,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit8: /* 0xd8 */
-/* File: mips/op_add_int_lit8.S */
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6422,12 +5820,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int_lit8: /* 0xd9 */
-/* File: mips/op_rsub_int_lit8.S */
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6458,12 +5853,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit8: /* 0xda */
-/* File: mips/op_mul_int_lit8.S */
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6494,13 +5886,10 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit8: /* 0xdb */
-/* File: mips/op_div_int_lit8.S */
 #ifdef MIPS32REVGE6
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6530,9 +5919,7 @@ TODO
     div a0, a0, a1                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
-
 #else
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6562,15 +5949,12 @@ TODO
     mflo a0                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
-
 #endif
 
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit8: /* 0xdc */
-/* File: mips/op_rem_int_lit8.S */
 #ifdef MIPS32REVGE6
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6600,9 +5984,7 @@ TODO
     mod a0, a0, a1                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
-
 #else
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6632,14 +6014,11 @@ TODO
     mfhi a0                                 #  a0 <- op, a0-a3 changed
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
-
 #endif
 
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit8: /* 0xdd */
-/* File: mips/op_and_int_lit8.S */
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6670,12 +6049,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit8: /* 0xde */
-/* File: mips/op_or_int_lit8.S */
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6706,12 +6082,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit8: /* 0xdf */
-/* File: mips/op_xor_int_lit8.S */
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6742,12 +6115,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_lit8: /* 0xe0 */
-/* File: mips/op_shl_int_lit8.S */
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6778,12 +6148,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_lit8: /* 0xe1 */
-/* File: mips/op_shr_int_lit8.S */
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6814,12 +6181,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_lit8: /* 0xe2 */
-/* File: mips/op_ushr_int_lit8.S */
-/* File: mips/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6850,11 +6214,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, rOBJ, t0)       #  vAA <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_quick: /* 0xe3 */
-/* File: mips/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
@@ -6872,7 +6234,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide_quick: /* 0xe4 */
-/* File: mips/op_iget_wide_quick.S */
     /* iget-wide-quick vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
     GET_VREG(a3, a2)                       #  a3 <- object we're operating on
@@ -6889,7 +6250,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object_quick: /* 0xe5 */
-/* File: mips/op_iget_object_quick.S */
     /* For: iget-object-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
@@ -6908,7 +6268,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_iput_quick: /* 0xe6 */
-/* File: mips/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
@@ -6927,7 +6286,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide_quick: /* 0xe7 */
-/* File: mips/op_iput_wide_quick.S */
     /* iput-wide-quick vA, vB, offset@CCCC */
     GET_OPA4(a0)                           #  a0 <- A(+)
     GET_OPB(a1)                            #  a1 <- B
@@ -6947,7 +6305,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object_quick: /* 0xe8 */
-/* File: mips/op_iput_object_quick.S */
     /* For: iput-object-quick */
     /* op vA, vB, offset@CCCC */
     EXPORT_PC()
@@ -6963,8 +6320,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_quick: /* 0xe9 */
-/* File: mips/op_invoke_virtual_quick.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -6984,12 +6339,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range_quick: /* 0xea */
-/* File: mips/op_invoke_virtual_range_quick.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -7009,12 +6361,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean_quick: /* 0xeb */
-/* File: mips/op_iput_boolean_quick.S */
-/* File: mips/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
@@ -7030,12 +6379,9 @@ TODO
     sb    a0, 0(t0)                    #  obj.field (8/16/32 bits) <- a0
     JR(t1)                                 #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte_quick: /* 0xec */
-/* File: mips/op_iput_byte_quick.S */
-/* File: mips/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
@@ -7051,12 +6397,9 @@ TODO
     sb    a0, 0(t0)                    #  obj.field (8/16/32 bits) <- a0
     JR(t1)                                 #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char_quick: /* 0xed */
-/* File: mips/op_iput_char_quick.S */
-/* File: mips/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
@@ -7072,12 +6415,9 @@ TODO
     sh    a0, 0(t0)                    #  obj.field (8/16/32 bits) <- a0
     JR(t1)                                 #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short_quick: /* 0xee */
-/* File: mips/op_iput_short_quick.S */
-/* File: mips/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
@@ -7093,12 +6433,9 @@ TODO
     sh    a0, 0(t0)                    #  obj.field (8/16/32 bits) <- a0
     JR(t1)                                 #  jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean_quick: /* 0xef */
-/* File: mips/op_iget_boolean_quick.S */
-/* File: mips/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
@@ -7113,12 +6450,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, a2, t0)              #  fp[A] <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte_quick: /* 0xf0 */
-/* File: mips/op_iget_byte_quick.S */
-/* File: mips/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
@@ -7133,12 +6467,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, a2, t0)              #  fp[A] <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char_quick: /* 0xf1 */
-/* File: mips/op_iget_char_quick.S */
-/* File: mips/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
@@ -7153,12 +6484,9 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, a2, t0)              #  fp[A] <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short_quick: /* 0xf2 */
-/* File: mips/op_iget_short_quick.S */
-/* File: mips/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     GET_OPB(a2)                            #  a2 <- B
@@ -7173,89 +6501,65 @@ TODO
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG_GOTO(a0, a2, t0)              #  fp[A] <- a0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f3: /* 0xf3 */
-/* File: mips/op_unused_f3.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f4: /* 0xf4 */
-/* File: mips/op_unused_f4.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f5: /* 0xf5 */
-/* File: mips/op_unused_f5.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f6: /* 0xf6 */
-/* File: mips/op_unused_f6.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f7: /* 0xf7 */
-/* File: mips/op_unused_f7.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f8: /* 0xf8 */
-/* File: mips/op_unused_f8.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f9: /* 0xf9 */
-/* File: mips/op_unused_f9.S */
-/* File: mips/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
   b MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic: /* 0xfa */
-/* File: mips/op_invoke_polymorphic.S */
-/* File: mips/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -7275,12 +6579,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic_range: /* 0xfb */
-/* File: mips/op_invoke_polymorphic_range.S */
-/* File: mips/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -7300,12 +6601,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom: /* 0xfc */
-/* File: mips/op_invoke_custom.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -7325,12 +6623,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom_range: /* 0xfd */
-/* File: mips/op_invoke_custom_range.S */
-/* File: mips/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -7350,12 +6645,9 @@ TODO
     GET_INST_OPCODE(t0)
     GOTO_OPCODE(t0)
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_handle: /* 0xfe */
-/* File: mips/op_const_method_handle.S */
-/* File: mips/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -7373,12 +6665,9 @@ TODO
     GET_INST_OPCODE(t0)                 # extract opcode from rINST
     GOTO_OPCODE(t0)                     # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_type: /* 0xff */
-/* File: mips/op_const_method_type.S */
-/* File: mips/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -7396,29 +6685,16 @@ TODO
     GET_INST_OPCODE(t0)                 # extract opcode from rINST
     GOTO_OPCODE(t0)                     # jump to next instruction
 
-
     .balign 128
-/* File: mips/instruction_end.S */
 
     .global artMterpAsmInstructionEnd
 artMterpAsmInstructionEnd:
 
-
-/*
- * ===========================================================================
- *  Sister implementations
- * ===========================================================================
- */
-/* File: mips/instruction_start_sister.S */
-
     .global artMterpAsmSisterStart
     .text
     .balign 4
 artMterpAsmSisterStart:
 
-
-/* continuation for op_float_to_long */
-
 #ifndef MIPS32REVGE6
 .Lop_float_to_long_get_opcode:
     GET_INST_OPCODE(t1)                    #  extract opcode from rINST
@@ -7426,8 +6702,6 @@ artMterpAsmSisterStart:
     SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1)   #  vA/vA+1 <- v0/v1
 #endif
 
-/* continuation for op_double_to_long */
-
 #ifndef MIPS32REVGE6
 .Lop_double_to_long_get_opcode:
     GET_INST_OPCODE(t1)                    #  extract opcode from rINST
@@ -7435,58 +6709,39 @@ artMterpAsmSisterStart:
     SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1)   #  vA/vA+1 <- v0/v1
 #endif
 
-/* continuation for op_mul_long */
-
 .Lop_mul_long_finish:
     GET_INST_OPCODE(t0)                    #  extract opcode from rINST
     SET_VREG64_GOTO(v0, v1, a0, t0)        #  vAA/vAA+1 <- v0(low)/v1(high)
 
-/* continuation for op_shl_long */
-
 .Lop_shl_long_finish:
     SET_VREG64_GOTO(zero, v0, t2, t0)      #  vAA/vAA+1 <- rlo/rhi
 
-/* continuation for op_shr_long */
-
 .Lop_shr_long_finish:
     sra     a3, a1, 31                     #  a3<- sign(ah)
     SET_VREG64_GOTO(v1, a3, t3, t0)        #  vAA/VAA+1 <- rlo/rhi
 
-/* continuation for op_ushr_long */
-
 .Lop_ushr_long_finish:
     SET_VREG64_GOTO(v1, zero, rOBJ, t0)    #  vAA/vAA+1 <- rlo/rhi
 
-/* continuation for op_shl_long_2addr */
-
 .Lop_shl_long_2addr_finish:
     SET_VREG64_GOTO(zero, v0, rOBJ, t0)    #  vA/vA+1 <- rlo/rhi
 
-/* continuation for op_shr_long_2addr */
-
 .Lop_shr_long_2addr_finish:
     sra     a3, a1, 31                     #  a3<- sign(ah)
     SET_VREG64_GOTO(v1, a3, t2, t0)        #  vA/vA+1 <- rlo/rhi
 
-/* continuation for op_ushr_long_2addr */
-
 .Lop_ushr_long_2addr_finish:
     SET_VREG64_GOTO(v1, zero, t3, t0)      #  vA/vA+1 <- rlo/rhi
-/* File: mips/instruction_end_sister.S */
 
     .global artMterpAsmSisterEnd
 artMterpAsmSisterEnd:
 
-/* File: mips/instruction_start_alt.S */
-
     .global artMterpAsmAltInstructionStart
 artMterpAsmAltInstructionStart = .L_ALT_op_nop
     .text
-
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_nop: /* 0x00 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7504,7 +6759,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move: /* 0x01 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7522,7 +6776,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_from16: /* 0x02 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7540,7 +6793,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_16: /* 0x03 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7558,7 +6810,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide: /* 0x04 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7576,7 +6827,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_from16: /* 0x05 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7594,7 +6844,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_16: /* 0x06 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7612,7 +6861,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object: /* 0x07 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7630,7 +6878,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_from16: /* 0x08 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7648,7 +6895,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_16: /* 0x09 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7666,7 +6912,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result: /* 0x0a */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7684,7 +6929,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_wide: /* 0x0b */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7702,7 +6946,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_object: /* 0x0c */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7720,7 +6963,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_exception: /* 0x0d */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7738,7 +6980,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void: /* 0x0e */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7756,7 +6997,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return: /* 0x0f */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7774,7 +7014,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_wide: /* 0x10 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7792,7 +7031,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_object: /* 0x11 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7810,7 +7048,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_4: /* 0x12 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7828,7 +7065,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_16: /* 0x13 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7846,7 +7082,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const: /* 0x14 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7864,7 +7099,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_high16: /* 0x15 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7882,7 +7116,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_16: /* 0x16 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7900,7 +7133,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_32: /* 0x17 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7918,7 +7150,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide: /* 0x18 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7936,7 +7167,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_high16: /* 0x19 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7954,7 +7184,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string: /* 0x1a */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7972,7 +7201,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string_jumbo: /* 0x1b */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7990,7 +7218,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_class: /* 0x1c */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8008,7 +7235,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_enter: /* 0x1d */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8026,7 +7252,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_exit: /* 0x1e */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8044,7 +7269,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_check_cast: /* 0x1f */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8062,7 +7286,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_instance_of: /* 0x20 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8080,7 +7303,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_array_length: /* 0x21 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8098,7 +7320,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_instance: /* 0x22 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8116,7 +7337,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_array: /* 0x23 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8134,7 +7354,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array: /* 0x24 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8152,7 +7371,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array_range: /* 0x25 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8170,7 +7388,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_fill_array_data: /* 0x26 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8188,7 +7405,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_throw: /* 0x27 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8206,7 +7422,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto: /* 0x28 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8224,7 +7439,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_16: /* 0x29 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8242,7 +7456,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_32: /* 0x2a */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8260,7 +7473,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_packed_switch: /* 0x2b */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8278,7 +7490,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sparse_switch: /* 0x2c */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8296,7 +7507,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_float: /* 0x2d */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8314,7 +7524,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_float: /* 0x2e */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8332,7 +7541,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_double: /* 0x2f */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8350,7 +7558,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_double: /* 0x30 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8368,7 +7575,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmp_long: /* 0x31 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8386,7 +7592,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eq: /* 0x32 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8404,7 +7609,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ne: /* 0x33 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8422,7 +7626,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lt: /* 0x34 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8440,7 +7643,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ge: /* 0x35 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8458,7 +7660,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gt: /* 0x36 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8476,7 +7677,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_le: /* 0x37 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8494,7 +7694,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eqz: /* 0x38 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8512,7 +7711,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_nez: /* 0x39 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8530,7 +7728,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ltz: /* 0x3a */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8548,7 +7745,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gez: /* 0x3b */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8566,7 +7762,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gtz: /* 0x3c */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8584,7 +7779,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lez: /* 0x3d */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8602,7 +7796,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3e: /* 0x3e */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8620,7 +7813,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3f: /* 0x3f */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8638,7 +7830,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_40: /* 0x40 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8656,7 +7847,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_41: /* 0x41 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8674,7 +7864,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_42: /* 0x42 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8692,7 +7881,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_43: /* 0x43 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8710,7 +7898,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget: /* 0x44 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8728,7 +7915,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_wide: /* 0x45 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8746,7 +7932,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_object: /* 0x46 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8764,7 +7949,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_boolean: /* 0x47 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8782,7 +7966,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_byte: /* 0x48 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8800,7 +7983,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_char: /* 0x49 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8818,7 +8000,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_short: /* 0x4a */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8836,7 +8017,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput: /* 0x4b */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8854,7 +8034,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_wide: /* 0x4c */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8872,7 +8051,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_object: /* 0x4d */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8890,7 +8068,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_boolean: /* 0x4e */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8908,7 +8085,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_byte: /* 0x4f */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8926,7 +8102,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_char: /* 0x50 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8944,7 +8119,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_short: /* 0x51 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8962,7 +8136,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget: /* 0x52 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8980,7 +8153,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide: /* 0x53 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8998,7 +8170,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object: /* 0x54 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9016,7 +8187,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean: /* 0x55 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9034,7 +8204,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte: /* 0x56 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9052,7 +8221,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char: /* 0x57 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9070,7 +8238,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short: /* 0x58 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9088,7 +8255,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput: /* 0x59 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9106,7 +8272,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide: /* 0x5a */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9124,7 +8289,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object: /* 0x5b */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9142,7 +8306,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean: /* 0x5c */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9160,7 +8323,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte: /* 0x5d */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9178,7 +8340,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char: /* 0x5e */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9196,7 +8357,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short: /* 0x5f */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9214,7 +8374,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget: /* 0x60 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9232,7 +8391,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_wide: /* 0x61 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9250,7 +8408,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_object: /* 0x62 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9268,7 +8425,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_boolean: /* 0x63 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9286,7 +8442,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_byte: /* 0x64 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9304,7 +8459,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_char: /* 0x65 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9322,7 +8476,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_short: /* 0x66 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9340,7 +8493,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput: /* 0x67 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9358,7 +8510,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_wide: /* 0x68 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9376,7 +8527,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_object: /* 0x69 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9394,7 +8544,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_boolean: /* 0x6a */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9412,7 +8561,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_byte: /* 0x6b */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9430,7 +8578,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_char: /* 0x6c */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9448,7 +8595,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_short: /* 0x6d */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9466,7 +8612,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual: /* 0x6e */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9484,7 +8629,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super: /* 0x6f */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9502,7 +8646,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct: /* 0x70 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9520,7 +8663,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static: /* 0x71 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9538,7 +8680,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface: /* 0x72 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9556,7 +8697,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void_no_barrier: /* 0x73 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9574,7 +8714,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range: /* 0x74 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9592,7 +8731,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super_range: /* 0x75 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9610,7 +8748,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct_range: /* 0x76 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9628,7 +8765,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static_range: /* 0x77 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9646,7 +8782,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface_range: /* 0x78 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9664,7 +8799,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_79: /* 0x79 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9682,7 +8816,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_7a: /* 0x7a */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9700,7 +8833,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_int: /* 0x7b */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9718,7 +8850,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_int: /* 0x7c */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9736,7 +8867,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_long: /* 0x7d */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9754,7 +8884,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_long: /* 0x7e */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9772,7 +8901,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_float: /* 0x7f */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9790,7 +8918,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_double: /* 0x80 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9808,7 +8935,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_long: /* 0x81 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9826,7 +8952,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_float: /* 0x82 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9844,7 +8969,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_double: /* 0x83 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9862,7 +8986,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_int: /* 0x84 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9880,7 +9003,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_float: /* 0x85 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9898,7 +9020,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_double: /* 0x86 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9916,7 +9037,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_int: /* 0x87 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9934,7 +9054,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_long: /* 0x88 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9952,7 +9071,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_double: /* 0x89 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9970,7 +9088,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_int: /* 0x8a */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9988,7 +9105,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_long: /* 0x8b */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10006,7 +9122,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_float: /* 0x8c */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10024,7 +9139,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_byte: /* 0x8d */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10042,7 +9156,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_char: /* 0x8e */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10060,7 +9173,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_short: /* 0x8f */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10078,7 +9190,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int: /* 0x90 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10096,7 +9207,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int: /* 0x91 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10114,7 +9224,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int: /* 0x92 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10132,7 +9241,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int: /* 0x93 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10150,7 +9258,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int: /* 0x94 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10168,7 +9275,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int: /* 0x95 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10186,7 +9292,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int: /* 0x96 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10204,7 +9309,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int: /* 0x97 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10222,7 +9326,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int: /* 0x98 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10240,7 +9343,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int: /* 0x99 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10258,7 +9360,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int: /* 0x9a */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10276,7 +9377,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long: /* 0x9b */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10294,7 +9394,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long: /* 0x9c */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10312,7 +9411,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long: /* 0x9d */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10330,7 +9428,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long: /* 0x9e */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10348,7 +9445,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long: /* 0x9f */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10366,7 +9462,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long: /* 0xa0 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10384,7 +9479,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long: /* 0xa1 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10402,7 +9496,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long: /* 0xa2 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10420,7 +9513,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long: /* 0xa3 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10438,7 +9530,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long: /* 0xa4 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10456,7 +9547,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long: /* 0xa5 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10474,7 +9564,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float: /* 0xa6 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10492,7 +9581,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float: /* 0xa7 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10510,7 +9598,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float: /* 0xa8 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10528,7 +9615,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float: /* 0xa9 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10546,7 +9632,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float: /* 0xaa */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10564,7 +9649,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double: /* 0xab */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10582,7 +9666,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double: /* 0xac */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10600,7 +9683,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double: /* 0xad */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10618,7 +9700,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double: /* 0xae */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10636,7 +9717,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double: /* 0xaf */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10654,7 +9734,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_2addr: /* 0xb0 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10672,7 +9751,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int_2addr: /* 0xb1 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10690,7 +9768,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_2addr: /* 0xb2 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10708,7 +9785,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_2addr: /* 0xb3 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10726,7 +9802,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_2addr: /* 0xb4 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10744,7 +9819,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_2addr: /* 0xb5 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10762,7 +9836,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_2addr: /* 0xb6 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10780,7 +9853,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_2addr: /* 0xb7 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10798,7 +9870,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_2addr: /* 0xb8 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10816,7 +9887,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_2addr: /* 0xb9 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10834,7 +9904,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_2addr: /* 0xba */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10852,7 +9921,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long_2addr: /* 0xbb */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10870,7 +9938,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long_2addr: /* 0xbc */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10888,7 +9955,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long_2addr: /* 0xbd */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10906,7 +9972,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long_2addr: /* 0xbe */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10924,7 +9989,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long_2addr: /* 0xbf */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10942,7 +10006,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long_2addr: /* 0xc0 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10960,7 +10023,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long_2addr: /* 0xc1 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10978,7 +10040,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long_2addr: /* 0xc2 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10996,7 +10057,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long_2addr: /* 0xc3 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11014,7 +10074,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long_2addr: /* 0xc4 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11032,7 +10091,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long_2addr: /* 0xc5 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11050,7 +10108,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float_2addr: /* 0xc6 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11068,7 +10125,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float_2addr: /* 0xc7 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11086,7 +10142,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float_2addr: /* 0xc8 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11104,7 +10159,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float_2addr: /* 0xc9 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11122,7 +10176,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float_2addr: /* 0xca */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11140,7 +10193,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double_2addr: /* 0xcb */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11158,7 +10210,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double_2addr: /* 0xcc */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11176,7 +10227,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double_2addr: /* 0xcd */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11194,7 +10244,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double_2addr: /* 0xce */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11212,7 +10261,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double_2addr: /* 0xcf */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11230,7 +10278,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit16: /* 0xd0 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11248,7 +10295,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int: /* 0xd1 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11266,7 +10312,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit16: /* 0xd2 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11284,7 +10329,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit16: /* 0xd3 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11302,7 +10346,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit16: /* 0xd4 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11320,7 +10363,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit16: /* 0xd5 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11338,7 +10380,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit16: /* 0xd6 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11356,7 +10397,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit16: /* 0xd7 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11374,7 +10414,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit8: /* 0xd8 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11392,7 +10431,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int_lit8: /* 0xd9 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11410,7 +10448,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit8: /* 0xda */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11428,7 +10465,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit8: /* 0xdb */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11446,7 +10482,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit8: /* 0xdc */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11464,7 +10499,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit8: /* 0xdd */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11482,7 +10516,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit8: /* 0xde */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11500,7 +10533,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit8: /* 0xdf */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11518,7 +10550,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_lit8: /* 0xe0 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11536,7 +10567,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_lit8: /* 0xe1 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11554,7 +10584,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_lit8: /* 0xe2 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11572,7 +10601,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_quick: /* 0xe3 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11590,7 +10618,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide_quick: /* 0xe4 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11608,7 +10635,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object_quick: /* 0xe5 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11626,7 +10652,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_quick: /* 0xe6 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11644,7 +10669,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide_quick: /* 0xe7 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11662,7 +10686,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object_quick: /* 0xe8 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11680,7 +10703,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11698,7 +10720,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11716,7 +10737,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean_quick: /* 0xeb */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11734,7 +10754,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte_quick: /* 0xec */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11752,7 +10771,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char_quick: /* 0xed */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11770,7 +10788,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short_quick: /* 0xee */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11788,7 +10805,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean_quick: /* 0xef */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11806,7 +10822,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte_quick: /* 0xf0 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11824,7 +10839,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char_quick: /* 0xf1 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11842,7 +10856,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short_quick: /* 0xf2 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11860,7 +10873,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f3: /* 0xf3 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11878,7 +10890,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f4: /* 0xf4 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11896,7 +10907,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f5: /* 0xf5 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11914,7 +10924,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f6: /* 0xf6 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11932,7 +10941,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f7: /* 0xf7 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11950,7 +10958,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f8: /* 0xf8 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11968,7 +10975,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f9: /* 0xf9 */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11986,7 +10992,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic: /* 0xfa */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12004,7 +11009,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12022,7 +11026,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom: /* 0xfc */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12040,7 +11043,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom_range: /* 0xfd */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12058,7 +11060,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_handle: /* 0xfe */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12076,7 +11077,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_type: /* 0xff */
-/* File: mips/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12092,12 +11092,9 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
     jalr   zero, t9                     # Tail call to Mterp(self, shadow_frame, dex_pc_ptr)
 
     .balign 128
-/* File: mips/instruction_end_alt.S */
 
     .global artMterpAsmAltInstructionEnd
 artMterpAsmAltInstructionEnd:
-
-/* File: mips/footer.S */
 /*
  * ===========================================================================
  *  Common subroutines and data
@@ -12386,4 +11383,3 @@ MterpProfileActive:
 
     .cfi_endproc
     .end ExecuteMterpImpl
-
diff --git a/runtime/interpreter/mterp/out/mterp_mips64.S b/runtime/interpreter/mterp/out/mterp_mips64.S
index 40a8396f776b01e92d3bb3b88790e926c863f9d7..cf95a57a0eed0212936ad4c08300424452c9e998 100644
--- a/runtime/interpreter/mterp/out/mterp_mips64.S
+++ b/runtime/interpreter/mterp/out/mterp_mips64.S
@@ -1,10 +1,4 @@
-/*
- * This file was generated automatically by gen-mterp.py for 'mips64'.
- *
- * --> DO NOT EDIT <--
- */
-
-/* File: mips64/header.S */
+/* DO NOT EDIT: This file was generated by gen-mterp.py. */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -333,8 +327,6 @@ The following registers have fixed assignments:
 #define LONG_MIN            0x8000000000000000
 #define LONG_MIN_AS_FLOAT   0xDF000000
 #define LONG_MIN_AS_DOUBLE  0xC3E0000000000000
-
-/* File: mips64/entry.S */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -430,16 +422,12 @@ ExecuteMterpImpl:
 
     /* NOTE: no fallthrough */
 
-/* File: mips64/instruction_start.S */
-
     .global artMterpAsmInstructionStart
 artMterpAsmInstructionStart = .L_op_nop
     .text
-
 /* ------------------------------ */
     .balign 128
 .L_op_nop: /* 0x00 */
-/* File: mips64/op_nop.S */
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
@@ -447,7 +435,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move: /* 0x01 */
-/* File: mips64/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     ext     a2, rINST, 8, 4             # a2 <- A
@@ -465,7 +452,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_from16: /* 0x02 */
-/* File: mips64/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     lhu     a3, 2(rPC)                  # a3 <- BBBB
@@ -483,7 +469,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_16: /* 0x03 */
-/* File: mips64/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     lhu     a3, 4(rPC)                  # a3 <- BBBB
@@ -501,7 +486,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide: /* 0x04 */
-/* File: mips64/op_move_wide.S */
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     ext     a3, rINST, 12, 4            # a3 <- B
@@ -515,7 +499,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_from16: /* 0x05 */
-/* File: mips64/op_move_wide_from16.S */
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     lhu     a3, 2(rPC)                  # a3 <- BBBB
@@ -529,7 +512,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_16: /* 0x06 */
-/* File: mips64/op_move_wide_16.S */
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     lhu     a3, 4(rPC)                  # a3 <- BBBB
@@ -543,8 +525,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_object: /* 0x07 */
-/* File: mips64/op_move_object.S */
-/* File: mips64/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     ext     a2, rINST, 8, 4             # a2 <- A
@@ -559,12 +539,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_from16: /* 0x08 */
-/* File: mips64/op_move_object_from16.S */
-/* File: mips64/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     lhu     a3, 2(rPC)                  # a3 <- BBBB
@@ -579,12 +556,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_16: /* 0x09 */
-/* File: mips64/op_move_object_16.S */
-/* File: mips64/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     lhu     a3, 4(rPC)                  # a3 <- BBBB
@@ -599,11 +573,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_result: /* 0x0a */
-/* File: mips64/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     srl     a2, rINST, 8                # a2 <- AA
@@ -621,7 +593,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_wide: /* 0x0b */
-/* File: mips64/op_move_result_wide.S */
     /* for: move-result-wide */
     /* op vAA */
     srl     a2, rINST, 8                # a2 <- AA
@@ -635,8 +606,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_object: /* 0x0c */
-/* File: mips64/op_move_result_object.S */
-/* File: mips64/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     srl     a2, rINST, 8                # a2 <- AA
@@ -651,11 +620,9 @@ artMterpAsmInstructionStart = .L_op_nop
     .endif
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_exception: /* 0x0d */
-/* File: mips64/op_move_exception.S */
     /* move-exception vAA */
     srl     a2, rINST, 8                # a2 <- AA
     ld      a0, THREAD_EXCEPTION_OFFSET(rSELF)  # load exception obj
@@ -668,7 +635,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_void: /* 0x0e */
-/* File: mips64/op_return_void.S */
     .extern MterpThreadFenceForConstructor
     .extern MterpSuspendCheck
     jal     MterpThreadFenceForConstructor
@@ -684,7 +650,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return: /* 0x0f */
-/* File: mips64/op_return.S */
     /*
      * Return a 32-bit value.
      *
@@ -707,7 +672,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_wide: /* 0x10 */
-/* File: mips64/op_return_wide.S */
     /*
      * Return a 64-bit value.
      */
@@ -729,8 +693,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_object: /* 0x11 */
-/* File: mips64/op_return_object.S */
-/* File: mips64/op_return.S */
     /*
      * Return a 32-bit value.
      *
@@ -750,11 +712,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_VREG_U  a0, a2                      # a0 <- vAA
     b       MterpReturn
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_4: /* 0x12 */
-/* File: mips64/op_const_4.S */
     /* const/4 vA, #+B */
     ext     a2, rINST, 8, 4             # a2 <- A
     seh     a0, rINST                   # sign extend B in rINST
@@ -767,7 +727,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_16: /* 0x13 */
-/* File: mips64/op_const_16.S */
     /* const/16 vAA, #+BBBB */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- sign-extended BBBB
@@ -779,7 +738,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const: /* 0x14 */
-/* File: mips64/op_const.S */
     /* const vAA, #+BBBBbbbb */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- bbbb (low)
@@ -793,7 +751,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_high16: /* 0x15 */
-/* File: mips64/op_const_high16.S */
     /* const/high16 vAA, #+BBBB0000 */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- BBBB
@@ -806,7 +763,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_16: /* 0x16 */
-/* File: mips64/op_const_wide_16.S */
     /* const-wide/16 vAA, #+BBBB */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- sign-extended BBBB
@@ -818,7 +774,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_32: /* 0x17 */
-/* File: mips64/op_const_wide_32.S */
     /* const-wide/32 vAA, #+BBBBbbbb */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- bbbb (low)
@@ -832,7 +787,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide: /* 0x18 */
-/* File: mips64/op_const_wide.S */
     /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
     srl     a4, rINST, 8                # a4 <- AA
     lh      a0, 2(rPC)                  # a0 <- bbbb (low)
@@ -850,7 +804,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_high16: /* 0x19 */
-/* File: mips64/op_const_wide_high16.S */
     /* const-wide/high16 vAA, #+BBBB000000000000 */
     srl     a2, rINST, 8                # a2 <- AA
     lh      a0, 2(rPC)                  # a0 <- BBBB
@@ -863,8 +816,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_string: /* 0x1a */
-/* File: mips64/op_const_string.S */
-/* File: mips64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -882,11 +833,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_string_jumbo: /* 0x1b */
-/* File: mips64/op_const_string_jumbo.S */
     /* const/string vAA, String//BBBBBBBB */
     .extern MterpConstString
     EXPORT_PC
@@ -906,8 +855,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_class: /* 0x1c */
-/* File: mips64/op_const_class.S */
-/* File: mips64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -925,11 +872,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_enter: /* 0x1d */
-/* File: mips64/op_monitor_enter.S */
     /*
      * Synchronize on an object.
      */
@@ -948,7 +893,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_exit: /* 0x1e */
-/* File: mips64/op_monitor_exit.S */
     /*
      * Unlock an object.
      *
@@ -971,7 +915,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_check_cast: /* 0x1f */
-/* File: mips64/op_check_cast.S */
     /*
      * Check to see if a cast from one class to another is allowed.
      */
@@ -993,7 +936,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_instance_of: /* 0x20 */
-/* File: mips64/op_instance_of.S */
     /*
      * Check to see if an object reference is an instance of a class.
      *
@@ -1021,7 +963,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_array_length: /* 0x21 */
-/* File: mips64/op_array_length.S */
     /*
      * Return the length of an array.
      */
@@ -1038,7 +979,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_instance: /* 0x22 */
-/* File: mips64/op_new_instance.S */
     /*
      * Create a new instance of a class.
      */
@@ -1057,7 +997,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_array: /* 0x23 */
-/* File: mips64/op_new_array.S */
     /*
      * Allocate an array of objects, specified with the array class
      * and a count.
@@ -1081,7 +1020,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array: /* 0x24 */
-/* File: mips64/op_filled_new_array.S */
     /*
      * Create a new array with elements filled from registers.
      *
@@ -1103,8 +1041,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array_range: /* 0x25 */
-/* File: mips64/op_filled_new_array_range.S */
-/* File: mips64/op_filled_new_array.S */
     /*
      * Create a new array with elements filled from registers.
      *
@@ -1123,11 +1059,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_fill_array_data: /* 0x26 */
-/* File: mips64/op_fill_array_data.S */
     /* fill-array-data vAA, +BBBBBBBB */
     .extern MterpFillArrayData
     EXPORT_PC
@@ -1146,7 +1080,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_throw: /* 0x27 */
-/* File: mips64/op_throw.S */
     /*
      * Throw an exception object in the current thread.
      */
@@ -1161,7 +1094,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto: /* 0x28 */
-/* File: mips64/op_goto.S */
     /*
      * Unconditional branch, 8-bit offset.
      *
@@ -1176,7 +1108,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_16: /* 0x29 */
-/* File: mips64/op_goto_16.S */
     /*
      * Unconditional branch, 16-bit offset.
      *
@@ -1190,7 +1121,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_32: /* 0x2a */
-/* File: mips64/op_goto_32.S */
     /*
      * Unconditional branch, 32-bit offset.
      *
@@ -1209,7 +1139,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_packed_switch: /* 0x2b */
-/* File: mips64/op_packed_switch.S */
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
@@ -1234,8 +1163,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_sparse_switch: /* 0x2c */
-/* File: mips64/op_sparse_switch.S */
-/* File: mips64/op_packed_switch.S */
     /*
      * Handle a packed-switch or sparse-switch instruction.  In both cases
      * we decode it and hand it off to a helper function.
@@ -1257,12 +1184,9 @@ artMterpAsmInstructionStart = .L_op_nop
     move    rINST, v0
     b       MterpCommonTakenBranchNoFlags
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_float: /* 0x2d */
-/* File: mips64/op_cmpl_float.S */
-/* File: mips64/fcmp.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1295,12 +1219,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG a0, a4                     # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_float: /* 0x2e */
-/* File: mips64/op_cmpg_float.S */
-/* File: mips64/fcmp.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1333,12 +1254,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG a0, a4                     # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_double: /* 0x2f */
-/* File: mips64/op_cmpl_double.S */
-/* File: mips64/fcmpWide.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1371,12 +1289,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG a0, a4                     # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_double: /* 0x30 */
-/* File: mips64/op_cmpg_double.S */
-/* File: mips64/fcmpWide.S */
     /*
      * Compare two floating-point values.  Puts 0, 1, or -1 into the
      * destination register based on the results of the comparison.
@@ -1409,11 +1324,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG a0, a4                     # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmp_long: /* 0x31 */
-/* File: mips64/op_cmp_long.S */
     /* cmp-long vAA, vBB, vCC */
     lbu     a2, 2(rPC)                  # a2 <- BB
     lbu     a3, 3(rPC)                  # a3 <- CC
@@ -1431,8 +1344,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_if_eq: /* 0x32 */
-/* File: mips64/op_if_eq.S */
-/* File: mips64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1453,12 +1364,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ne: /* 0x33 */
-/* File: mips64/op_if_ne.S */
-/* File: mips64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1479,12 +1387,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lt: /* 0x34 */
-/* File: mips64/op_if_lt.S */
-/* File: mips64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1505,12 +1410,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ge: /* 0x35 */
-/* File: mips64/op_if_ge.S */
-/* File: mips64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1531,12 +1433,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gt: /* 0x36 */
-/* File: mips64/op_if_gt.S */
-/* File: mips64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1557,12 +1456,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_le: /* 0x37 */
-/* File: mips64/op_if_le.S */
-/* File: mips64/bincmp.S */
     /*
      * Generic two-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1583,12 +1479,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_eqz: /* 0x38 */
-/* File: mips64/op_if_eqz.S */
-/* File: mips64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1607,12 +1500,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_nez: /* 0x39 */
-/* File: mips64/op_if_nez.S */
-/* File: mips64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1631,12 +1521,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ltz: /* 0x3a */
-/* File: mips64/op_if_ltz.S */
-/* File: mips64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1655,12 +1542,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gez: /* 0x3b */
-/* File: mips64/op_if_gez.S */
-/* File: mips64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1679,12 +1563,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gtz: /* 0x3c */
-/* File: mips64/op_if_gtz.S */
-/* File: mips64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1703,12 +1584,9 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lez: /* 0x3d */
-/* File: mips64/op_if_lez.S */
-/* File: mips64/zcmp.S */
     /*
      * Generic one-operand compare-and-branch operation.  Provide a "condition"
      * fragment that specifies the comparison to perform, e.g. for
@@ -1727,77 +1605,57 @@ artMterpAsmInstructionStart = .L_op_nop
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3e: /* 0x3e */
-/* File: mips64/op_unused_3e.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3f: /* 0x3f */
-/* File: mips64/op_unused_3f.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_40: /* 0x40 */
-/* File: mips64/op_unused_40.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_41: /* 0x41 */
-/* File: mips64/op_unused_41.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_42: /* 0x42 */
-/* File: mips64/op_unused_42.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_43: /* 0x43 */
-/* File: mips64/op_unused_43.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget: /* 0x44 */
-/* File: mips64/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1830,7 +1688,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_wide: /* 0x45 */
-/* File: mips64/op_aget_wide.S */
     /*
      * Array get, 64 bits.  vAA <- vBB[vCC].
      *
@@ -1856,7 +1713,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_object: /* 0x46 */
-/* File: mips64/op_aget_object.S */
     /*
      * Array object get.  vAA <- vBB[vCC].
      *
@@ -1882,8 +1738,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_boolean: /* 0x47 */
-/* File: mips64/op_aget_boolean.S */
-/* File: mips64/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1913,12 +1767,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG a2, a4                     # vAA <- a2
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_byte: /* 0x48 */
-/* File: mips64/op_aget_byte.S */
-/* File: mips64/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1948,12 +1799,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG a2, a4                     # vAA <- a2
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_char: /* 0x49 */
-/* File: mips64/op_aget_char.S */
-/* File: mips64/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -1983,12 +1831,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG a2, a4                     # vAA <- a2
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_short: /* 0x4a */
-/* File: mips64/op_aget_short.S */
-/* File: mips64/op_aget.S */
     /*
      * Array get, 32 bits or less.  vAA <- vBB[vCC].
      *
@@ -2018,11 +1863,9 @@ artMterpAsmInstructionStart = .L_op_nop
     SET_VREG a2, a4                     # vAA <- a2
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput: /* 0x4b */
-/* File: mips64/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2055,7 +1898,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_wide: /* 0x4c */
-/* File: mips64/op_aput_wide.S */
     /*
      * Array put, 64 bits.  vBB[vCC] <- vAA.
      *
@@ -2081,7 +1923,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_object: /* 0x4d */
-/* File: mips64/op_aput_object.S */
     /*
      * Store an object into an array.  vBB[vCC] <- vAA.
      */
@@ -2100,8 +1941,6 @@ artMterpAsmInstructionStart = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_boolean: /* 0x4e */
-/* File: mips64/op_aput_boolean.S */
-/* File: mips64/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2131,12 +1970,9 @@ artMterpAsmInstructionStart = .L_op_nop
     sb  a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0)        # vBB[vCC] <- a2
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_byte: /* 0x4f */
-/* File: mips64/op_aput_byte.S */
-/* File: mips64/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2166,12 +2002,9 @@ artMterpAsmInstructionStart = .L_op_nop
     sb  a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0)        # vBB[vCC] <- a2
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_char: /* 0x50 */
-/* File: mips64/op_aput_char.S */
-/* File: mips64/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2201,12 +2034,9 @@ artMterpAsmInstructionStart = .L_op_nop
     sh  a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0)        # vBB[vCC] <- a2
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_short: /* 0x51 */
-/* File: mips64/op_aput_short.S */
-/* File: mips64/op_aput.S */
     /*
      * Array put, 32 bits or less.  vBB[vCC] <- vAA.
      *
@@ -2236,284 +2066,149 @@ artMterpAsmInstructionStart = .L_op_nop
     sh  a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0)        # vBB[vCC] <- a2
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget: /* 0x52 */
-/* File: mips64/op_iget.S */
-/* File: mips64/field.S */
 TODO
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide: /* 0x53 */
-/* File: mips64/op_iget_wide.S */
-/* File: mips64/op_iget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object: /* 0x54 */
-/* File: mips64/op_iget_object.S */
-/* File: mips64/op_iget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean: /* 0x55 */
-/* File: mips64/op_iget_boolean.S */
-/* File: mips64/op_iget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte: /* 0x56 */
-/* File: mips64/op_iget_byte.S */
-/* File: mips64/op_iget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char: /* 0x57 */
-/* File: mips64/op_iget_char.S */
-/* File: mips64/op_iget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short: /* 0x58 */
-/* File: mips64/op_iget_short.S */
-/* File: mips64/op_iget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput: /* 0x59 */
-/* File: mips64/op_iput.S */
-/* File: mips64/field.S */
 TODO
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide: /* 0x5a */
-/* File: mips64/op_iput_wide.S */
-/* File: mips64/op_iput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object: /* 0x5b */
-/* File: mips64/op_iput_object.S */
-/* File: mips64/op_iput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean: /* 0x5c */
-/* File: mips64/op_iput_boolean.S */
-/* File: mips64/op_iput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte: /* 0x5d */
-/* File: mips64/op_iput_byte.S */
-/* File: mips64/op_iput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char: /* 0x5e */
-/* File: mips64/op_iput_char.S */
-/* File: mips64/op_iput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short: /* 0x5f */
-/* File: mips64/op_iput_short.S */
-/* File: mips64/op_iput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget: /* 0x60 */
-/* File: mips64/op_sget.S */
-/* File: mips64/field.S */
 TODO
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_wide: /* 0x61 */
-/* File: mips64/op_sget_wide.S */
-/* File: mips64/op_sget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_object: /* 0x62 */
-/* File: mips64/op_sget_object.S */
-/* File: mips64/op_sget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_boolean: /* 0x63 */
-/* File: mips64/op_sget_boolean.S */
-/* File: mips64/op_sget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_byte: /* 0x64 */
-/* File: mips64/op_sget_byte.S */
-/* File: mips64/op_sget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_char: /* 0x65 */
-/* File: mips64/op_sget_char.S */
-/* File: mips64/op_sget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_short: /* 0x66 */
-/* File: mips64/op_sget_short.S */
-/* File: mips64/op_sget.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput: /* 0x67 */
-/* File: mips64/op_sput.S */
-/* File: mips64/field.S */
 TODO
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_wide: /* 0x68 */
-/* File: mips64/op_sput_wide.S */
-/* File: mips64/op_sput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_object: /* 0x69 */
-/* File: mips64/op_sput_object.S */
-/* File: mips64/op_sput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_boolean: /* 0x6a */
-/* File: mips64/op_sput_boolean.S */
-/* File: mips64/op_sput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_byte: /* 0x6b */
-/* File: mips64/op_sput_byte.S */
-/* File: mips64/op_sput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_char: /* 0x6c */
-/* File: mips64/op_sput_char.S */
-/* File: mips64/op_sput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_short: /* 0x6d */
-/* File: mips64/op_sput_short.S */
-/* File: mips64/op_sput.S */
-/* File: mips64/field.S */
 TODO
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual: /* 0x6e */
-/* File: mips64/op_invoke_virtual.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2533,7 +2228,6 @@ TODO
     bnezc   v0, MterpFallback
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
-
     /*
      * Handle a virtual method call.
      *
@@ -2545,8 +2239,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super: /* 0x6f */
-/* File: mips64/op_invoke_super.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2566,7 +2258,6 @@ TODO
     bnezc   v0, MterpFallback
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
-
     /*
      * Handle a "super" method call.
      *
@@ -2578,8 +2269,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct: /* 0x70 */
-/* File: mips64/op_invoke_direct.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2600,12 +2289,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static: /* 0x71 */
-/* File: mips64/op_invoke_static.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2626,12 +2312,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface: /* 0x72 */
-/* File: mips64/op_invoke_interface.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2651,7 +2334,6 @@ TODO
     bnezc   v0, MterpFallback
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
-
     /*
      * Handle an interface method call.
      *
@@ -2663,7 +2345,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_return_void_no_barrier: /* 0x73 */
-/* File: mips64/op_return_void_no_barrier.S */
     .extern MterpSuspendCheck
     lw      ra, THREAD_FLAGS_OFFSET(rSELF)
     move    a0, rSELF
@@ -2677,8 +2358,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range: /* 0x74 */
-/* File: mips64/op_invoke_virtual_range.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2699,12 +2378,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super_range: /* 0x75 */
-/* File: mips64/op_invoke_super_range.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2725,12 +2401,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct_range: /* 0x76 */
-/* File: mips64/op_invoke_direct_range.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2751,12 +2424,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static_range: /* 0x77 */
-/* File: mips64/op_invoke_static_range.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2777,12 +2447,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface_range: /* 0x78 */
-/* File: mips64/op_invoke_interface_range.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -2803,34 +2470,25 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_79: /* 0x79 */
-/* File: mips64/op_unused_79.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_7a: /* 0x7a */
-/* File: mips64/op_unused_7a.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_int: /* 0x7b */
-/* File: mips64/op_neg_int.S */
-/* File: mips64/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "a0 = op a0".
@@ -2849,12 +2507,9 @@ TODO
     SET_VREG a0, a2                     # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_int: /* 0x7c */
-/* File: mips64/op_not_int.S */
-/* File: mips64/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "a0 = op a0".
@@ -2873,12 +2528,9 @@ TODO
     SET_VREG a0, a2                     # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_long: /* 0x7d */
-/* File: mips64/op_neg_long.S */
-/* File: mips64/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "a0 = op a0".
@@ -2896,12 +2548,9 @@ TODO
     SET_VREG_WIDE a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_long: /* 0x7e */
-/* File: mips64/op_not_long.S */
-/* File: mips64/unopWide.S */
     /*
      * Generic 64-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "a0 = op a0".
@@ -2919,12 +2568,9 @@ TODO
     SET_VREG_WIDE a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_float: /* 0x7f */
-/* File: mips64/op_neg_float.S */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -2940,9 +2586,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_FLOAT f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     neg.s   f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -2962,12 +2606,9 @@ TODO
     SET_VREG_FLOAT f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_double: /* 0x80 */
-/* File: mips64/op_neg_double.S */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -2983,9 +2624,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_DOUBLE f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     neg.d   f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -3005,11 +2644,9 @@ TODO
     SET_VREG_DOUBLE f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_long: /* 0x81 */
-/* File: mips64/op_int_to_long.S */
     /* int-to-long vA, vB */
     ext     a3, rINST, 12, 4            # a3 <- B
     GET_VREG a0, a3                     # a0 <- vB (sign-extended to 64 bits)
@@ -3022,13 +2659,11 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_float: /* 0x82 */
-/* File: mips64/op_int_to_float.S */
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -3044,9 +2679,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_FLOAT f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     cvt.s.w f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -3066,17 +2699,14 @@ TODO
     SET_VREG_FLOAT f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_double: /* 0x83 */
-/* File: mips64/op_int_to_double.S */
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -3092,9 +2722,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_FLOAT f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     cvt.d.w f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -3114,13 +2742,10 @@ TODO
     SET_VREG_DOUBLE f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_int: /* 0x84 */
-/* File: mips64/op_long_to_int.S */
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-/* File: mips64/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     ext     a2, rINST, 8, 4             # a2 <- A
@@ -3135,17 +2760,14 @@ TODO
     .endif
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_float: /* 0x85 */
-/* File: mips64/op_long_to_float.S */
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -3161,9 +2783,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_DOUBLE f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     cvt.s.l f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -3183,17 +2803,14 @@ TODO
     SET_VREG_FLOAT f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_double: /* 0x86 */
-/* File: mips64/op_long_to_double.S */
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -3209,9 +2826,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_DOUBLE f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     cvt.d.l f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -3231,12 +2846,9 @@ TODO
     SET_VREG_DOUBLE f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_int: /* 0x87 */
-/* File: mips64/op_float_to_int.S */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -3252,9 +2864,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_FLOAT f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     trunc.w.s f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -3274,12 +2884,9 @@ TODO
     SET_VREG_FLOAT f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_long: /* 0x88 */
-/* File: mips64/op_float_to_long.S */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -3295,9 +2902,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_FLOAT f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     trunc.l.s f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -3317,17 +2922,14 @@ TODO
     SET_VREG_DOUBLE f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_double: /* 0x89 */
-/* File: mips64/op_float_to_double.S */
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -3343,9 +2945,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_FLOAT f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     cvt.d.s f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -3365,12 +2965,9 @@ TODO
     SET_VREG_DOUBLE f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_int: /* 0x8a */
-/* File: mips64/op_double_to_int.S */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -3386,9 +2983,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_DOUBLE f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     trunc.w.d f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -3408,12 +3003,9 @@ TODO
     SET_VREG_FLOAT f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_long: /* 0x8b */
-/* File: mips64/op_double_to_long.S */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -3429,9 +3021,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_DOUBLE f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     trunc.l.d f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -3451,17 +3041,14 @@ TODO
     SET_VREG_DOUBLE f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_float: /* 0x8c */
-/* File: mips64/op_double_to_float.S */
     /*
      * Conversion from or to floating-point happens in a floating-point register.
      * Therefore we load the input and store the output into or from a
      * floating-point register irrespective of the type.
      */
-/* File: mips64/fcvtHeader.S */
     /*
      * Loads a specified register from vB. Used primarily for conversions
      * from or to a floating-point type.
@@ -3477,9 +3064,7 @@ TODO
     srl     a2, rINST, 12               # a2 <- B
     GET_VREG_DOUBLE f0, a2
     FETCH_ADVANCE_INST 1                # advance rPC, load rINST
-
     cvt.s.d f0, f0
-/* File: mips64/fcvtFooter.S */
     /*
      * Stores a specified register containing the result of conversion
      * from or to a floating-point type and jumps to the next instruction.
@@ -3499,12 +3084,9 @@ TODO
     SET_VREG_FLOAT f0, a1
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_byte: /* 0x8d */
-/* File: mips64/op_int_to_byte.S */
-/* File: mips64/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "a0 = op a0".
@@ -3523,12 +3105,9 @@ TODO
     SET_VREG a0, a2                     # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_char: /* 0x8e */
-/* File: mips64/op_int_to_char.S */
-/* File: mips64/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "a0 = op a0".
@@ -3547,12 +3126,9 @@ TODO
     SET_VREG a0, a2                     # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_short: /* 0x8f */
-/* File: mips64/op_int_to_short.S */
-/* File: mips64/unop.S */
     /*
      * Generic 32-bit unary operation.  Provide an "instr" line that
      * specifies an instruction that performs "a0 = op a0".
@@ -3571,12 +3147,9 @@ TODO
     SET_VREG a0, a2                     # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int: /* 0x90 */
-/* File: mips64/op_add_int.S */
-/* File: mips64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3607,12 +3180,9 @@ TODO
     SET_VREG a0, a4                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int: /* 0x91 */
-/* File: mips64/op_sub_int.S */
-/* File: mips64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3643,12 +3213,9 @@ TODO
     SET_VREG a0, a4                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int: /* 0x92 */
-/* File: mips64/op_mul_int.S */
-/* File: mips64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3679,12 +3246,9 @@ TODO
     SET_VREG a0, a4                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int: /* 0x93 */
-/* File: mips64/op_div_int.S */
-/* File: mips64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3715,12 +3279,9 @@ TODO
     SET_VREG a0, a4                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int: /* 0x94 */
-/* File: mips64/op_rem_int.S */
-/* File: mips64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3751,12 +3312,9 @@ TODO
     SET_VREG a0, a4                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int: /* 0x95 */
-/* File: mips64/op_and_int.S */
-/* File: mips64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3787,12 +3345,9 @@ TODO
     SET_VREG a0, a4                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int: /* 0x96 */
-/* File: mips64/op_or_int.S */
-/* File: mips64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3823,12 +3378,9 @@ TODO
     SET_VREG a0, a4                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int: /* 0x97 */
-/* File: mips64/op_xor_int.S */
-/* File: mips64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3859,12 +3411,9 @@ TODO
     SET_VREG a0, a4                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int: /* 0x98 */
-/* File: mips64/op_shl_int.S */
-/* File: mips64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3895,12 +3444,9 @@ TODO
     SET_VREG a0, a4                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int: /* 0x99 */
-/* File: mips64/op_shr_int.S */
-/* File: mips64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3931,12 +3477,9 @@ TODO
     SET_VREG a0, a4                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int: /* 0x9a */
-/* File: mips64/op_ushr_int.S */
-/* File: mips64/binop.S */
     /*
      * Generic 32-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -3967,12 +3510,9 @@ TODO
     SET_VREG a0, a4                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long: /* 0x9b */
-/* File: mips64/op_add_long.S */
-/* File: mips64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4003,12 +3543,9 @@ TODO
     SET_VREG_WIDE a0, a4           # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long: /* 0x9c */
-/* File: mips64/op_sub_long.S */
-/* File: mips64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4039,12 +3576,9 @@ TODO
     SET_VREG_WIDE a0, a4           # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long: /* 0x9d */
-/* File: mips64/op_mul_long.S */
-/* File: mips64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4075,12 +3609,9 @@ TODO
     SET_VREG_WIDE a0, a4           # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_long: /* 0x9e */
-/* File: mips64/op_div_long.S */
-/* File: mips64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4111,12 +3642,9 @@ TODO
     SET_VREG_WIDE a0, a4           # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long: /* 0x9f */
-/* File: mips64/op_rem_long.S */
-/* File: mips64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4147,12 +3675,9 @@ TODO
     SET_VREG_WIDE a0, a4           # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long: /* 0xa0 */
-/* File: mips64/op_and_long.S */
-/* File: mips64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4183,12 +3708,9 @@ TODO
     SET_VREG_WIDE a0, a4           # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long: /* 0xa1 */
-/* File: mips64/op_or_long.S */
-/* File: mips64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4219,12 +3741,9 @@ TODO
     SET_VREG_WIDE a0, a4           # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long: /* 0xa2 */
-/* File: mips64/op_xor_long.S */
-/* File: mips64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4255,12 +3774,9 @@ TODO
     SET_VREG_WIDE a0, a4           # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long: /* 0xa3 */
-/* File: mips64/op_shl_long.S */
-/* File: mips64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4291,12 +3807,9 @@ TODO
     SET_VREG_WIDE a0, a4           # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long: /* 0xa4 */
-/* File: mips64/op_shr_long.S */
-/* File: mips64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4327,12 +3840,9 @@ TODO
     SET_VREG_WIDE a0, a4           # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long: /* 0xa5 */
-/* File: mips64/op_ushr_long.S */
-/* File: mips64/binopWide.S */
     /*
      * Generic 64-bit binary operation.  Provide an "instr" line that
      * specifies an instruction that performs "result = a0 op a1".
@@ -4363,12 +3873,9 @@ TODO
     SET_VREG_WIDE a0, a4           # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_float: /* 0xa6 */
-/* File: mips64/op_add_float.S */
-/* File: mips64/fbinop.S */
     /*:
      * Generic 32-bit floating-point operation.
      *
@@ -4387,12 +3894,9 @@ TODO
     SET_VREG_FLOAT f0, a4               # vAA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float: /* 0xa7 */
-/* File: mips64/op_sub_float.S */
-/* File: mips64/fbinop.S */
     /*:
      * Generic 32-bit floating-point operation.
      *
@@ -4411,12 +3915,9 @@ TODO
     SET_VREG_FLOAT f0, a4               # vAA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float: /* 0xa8 */
-/* File: mips64/op_mul_float.S */
-/* File: mips64/fbinop.S */
     /*:
      * Generic 32-bit floating-point operation.
      *
@@ -4435,12 +3936,9 @@ TODO
     SET_VREG_FLOAT f0, a4               # vAA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float: /* 0xa9 */
-/* File: mips64/op_div_float.S */
-/* File: mips64/fbinop.S */
     /*:
      * Generic 32-bit floating-point operation.
      *
@@ -4459,11 +3957,9 @@ TODO
     SET_VREG_FLOAT f0, a4               # vAA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float: /* 0xaa */
-/* File: mips64/op_rem_float.S */
     /* rem-float vAA, vBB, vCC */
     .extern fmodf
     lbu     a2, 2(rPC)                  # a2 <- BB
@@ -4480,8 +3976,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_add_double: /* 0xab */
-/* File: mips64/op_add_double.S */
-/* File: mips64/fbinopWide.S */
     /*:
      * Generic 64-bit floating-point operation.
      *
@@ -4500,12 +3994,9 @@ TODO
     SET_VREG_DOUBLE f0, a4              # vAA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double: /* 0xac */
-/* File: mips64/op_sub_double.S */
-/* File: mips64/fbinopWide.S */
     /*:
      * Generic 64-bit floating-point operation.
      *
@@ -4524,12 +4015,9 @@ TODO
     SET_VREG_DOUBLE f0, a4              # vAA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double: /* 0xad */
-/* File: mips64/op_mul_double.S */
-/* File: mips64/fbinopWide.S */
     /*:
      * Generic 64-bit floating-point operation.
      *
@@ -4548,12 +4036,9 @@ TODO
     SET_VREG_DOUBLE f0, a4              # vAA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double: /* 0xae */
-/* File: mips64/op_div_double.S */
-/* File: mips64/fbinopWide.S */
     /*:
      * Generic 64-bit floating-point operation.
      *
@@ -4572,11 +4057,9 @@ TODO
     SET_VREG_DOUBLE f0, a4              # vAA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double: /* 0xaf */
-/* File: mips64/op_rem_double.S */
     /* rem-double vAA, vBB, vCC */
     .extern fmod
     lbu     a2, 2(rPC)                  # a2 <- BB
@@ -4593,8 +4076,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_2addr: /* 0xb0 */
-/* File: mips64/op_add_int_2addr.S */
-/* File: mips64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -4625,12 +4106,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int_2addr: /* 0xb1 */
-/* File: mips64/op_sub_int_2addr.S */
-/* File: mips64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -4661,12 +4139,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_2addr: /* 0xb2 */
-/* File: mips64/op_mul_int_2addr.S */
-/* File: mips64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -4697,12 +4172,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_2addr: /* 0xb3 */
-/* File: mips64/op_div_int_2addr.S */
-/* File: mips64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -4733,12 +4205,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_2addr: /* 0xb4 */
-/* File: mips64/op_rem_int_2addr.S */
-/* File: mips64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -4769,12 +4238,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_2addr: /* 0xb5 */
-/* File: mips64/op_and_int_2addr.S */
-/* File: mips64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -4805,12 +4271,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_2addr: /* 0xb6 */
-/* File: mips64/op_or_int_2addr.S */
-/* File: mips64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -4841,12 +4304,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_2addr: /* 0xb7 */
-/* File: mips64/op_xor_int_2addr.S */
-/* File: mips64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -4877,12 +4337,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_2addr: /* 0xb8 */
-/* File: mips64/op_shl_int_2addr.S */
-/* File: mips64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -4913,12 +4370,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_2addr: /* 0xb9 */
-/* File: mips64/op_shr_int_2addr.S */
-/* File: mips64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -4949,12 +4403,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_2addr: /* 0xba */
-/* File: mips64/op_ushr_int_2addr.S */
-/* File: mips64/binop2addr.S */
     /*
      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -4985,12 +4436,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long_2addr: /* 0xbb */
-/* File: mips64/op_add_long_2addr.S */
-/* File: mips64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5021,12 +4469,9 @@ TODO
     SET_VREG_WIDE a0, a2           # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long_2addr: /* 0xbc */
-/* File: mips64/op_sub_long_2addr.S */
-/* File: mips64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5057,12 +4502,9 @@ TODO
     SET_VREG_WIDE a0, a2           # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long_2addr: /* 0xbd */
-/* File: mips64/op_mul_long_2addr.S */
-/* File: mips64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5093,12 +4535,9 @@ TODO
     SET_VREG_WIDE a0, a2           # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_long_2addr: /* 0xbe */
-/* File: mips64/op_div_long_2addr.S */
-/* File: mips64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5129,12 +4568,9 @@ TODO
     SET_VREG_WIDE a0, a2           # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long_2addr: /* 0xbf */
-/* File: mips64/op_rem_long_2addr.S */
-/* File: mips64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5165,12 +4601,9 @@ TODO
     SET_VREG_WIDE a0, a2           # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long_2addr: /* 0xc0 */
-/* File: mips64/op_and_long_2addr.S */
-/* File: mips64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5201,12 +4634,9 @@ TODO
     SET_VREG_WIDE a0, a2           # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long_2addr: /* 0xc1 */
-/* File: mips64/op_or_long_2addr.S */
-/* File: mips64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5237,12 +4667,9 @@ TODO
     SET_VREG_WIDE a0, a2           # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long_2addr: /* 0xc2 */
-/* File: mips64/op_xor_long_2addr.S */
-/* File: mips64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5273,12 +4700,9 @@ TODO
     SET_VREG_WIDE a0, a2           # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long_2addr: /* 0xc3 */
-/* File: mips64/op_shl_long_2addr.S */
-/* File: mips64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5309,12 +4733,9 @@ TODO
     SET_VREG_WIDE a0, a2           # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long_2addr: /* 0xc4 */
-/* File: mips64/op_shr_long_2addr.S */
-/* File: mips64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5345,12 +4766,9 @@ TODO
     SET_VREG_WIDE a0, a2           # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long_2addr: /* 0xc5 */
-/* File: mips64/op_ushr_long_2addr.S */
-/* File: mips64/binopWide2addr.S */
     /*
      * Generic 64-bit "/2addr" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5381,12 +4799,9 @@ TODO
     SET_VREG_WIDE a0, a2           # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_float_2addr: /* 0xc6 */
-/* File: mips64/op_add_float_2addr.S */
-/* File: mips64/fbinop2addr.S */
     /*:
      * Generic 32-bit "/2addr" floating-point operation.
      *
@@ -5404,12 +4819,9 @@ TODO
     SET_VREG_FLOAT f0, a2               # vA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float_2addr: /* 0xc7 */
-/* File: mips64/op_sub_float_2addr.S */
-/* File: mips64/fbinop2addr.S */
     /*:
      * Generic 32-bit "/2addr" floating-point operation.
      *
@@ -5427,12 +4839,9 @@ TODO
     SET_VREG_FLOAT f0, a2               # vA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float_2addr: /* 0xc8 */
-/* File: mips64/op_mul_float_2addr.S */
-/* File: mips64/fbinop2addr.S */
     /*:
      * Generic 32-bit "/2addr" floating-point operation.
      *
@@ -5450,12 +4859,9 @@ TODO
     SET_VREG_FLOAT f0, a2               # vA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float_2addr: /* 0xc9 */
-/* File: mips64/op_div_float_2addr.S */
-/* File: mips64/fbinop2addr.S */
     /*:
      * Generic 32-bit "/2addr" floating-point operation.
      *
@@ -5473,11 +4879,9 @@ TODO
     SET_VREG_FLOAT f0, a2               # vA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float_2addr: /* 0xca */
-/* File: mips64/op_rem_float_2addr.S */
     /* rem-float/2addr vA, vB */
     .extern fmodf
     ext     a2, rINST, 8, 4             # a2 <- A
@@ -5494,8 +4898,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_add_double_2addr: /* 0xcb */
-/* File: mips64/op_add_double_2addr.S */
-/* File: mips64/fbinopWide2addr.S */
     /*:
      * Generic 64-bit "/2addr" floating-point operation.
      *
@@ -5513,12 +4915,9 @@ TODO
     SET_VREG_DOUBLE f0, a2              # vA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double_2addr: /* 0xcc */
-/* File: mips64/op_sub_double_2addr.S */
-/* File: mips64/fbinopWide2addr.S */
     /*:
      * Generic 64-bit "/2addr" floating-point operation.
      *
@@ -5536,12 +4935,9 @@ TODO
     SET_VREG_DOUBLE f0, a2              # vA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double_2addr: /* 0xcd */
-/* File: mips64/op_mul_double_2addr.S */
-/* File: mips64/fbinopWide2addr.S */
     /*:
      * Generic 64-bit "/2addr" floating-point operation.
      *
@@ -5559,12 +4955,9 @@ TODO
     SET_VREG_DOUBLE f0, a2              # vA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double_2addr: /* 0xce */
-/* File: mips64/op_div_double_2addr.S */
-/* File: mips64/fbinopWide2addr.S */
     /*:
      * Generic 64-bit "/2addr" floating-point operation.
      *
@@ -5582,11 +4975,9 @@ TODO
     SET_VREG_DOUBLE f0, a2              # vA <- f0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double_2addr: /* 0xcf */
-/* File: mips64/op_rem_double_2addr.S */
     /* rem-double/2addr vA, vB */
     .extern fmod
     ext     a2, rINST, 8, 4             # a2 <- A
@@ -5603,8 +4994,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit16: /* 0xd0 */
-/* File: mips64/op_add_int_lit16.S */
-/* File: mips64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5632,13 +5021,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int: /* 0xd1 */
-/* File: mips64/op_rsub_int.S */
-/* File: mips64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5666,13 +5051,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit16: /* 0xd2 */
-/* File: mips64/op_mul_int_lit16.S */
-/* File: mips64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5700,13 +5081,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit16: /* 0xd3 */
-/* File: mips64/op_div_int_lit16.S */
-/* File: mips64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5734,13 +5111,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit16: /* 0xd4 */
-/* File: mips64/op_rem_int_lit16.S */
-/* File: mips64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5768,13 +5141,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit16: /* 0xd5 */
-/* File: mips64/op_and_int_lit16.S */
-/* File: mips64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5802,13 +5171,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit16: /* 0xd6 */
-/* File: mips64/op_or_int_lit16.S */
-/* File: mips64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5836,13 +5201,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit16: /* 0xd7 */
-/* File: mips64/op_xor_int_lit16.S */
-/* File: mips64/binopLit16.S */
     /*
      * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5870,13 +5231,9 @@ TODO
     SET_VREG a0, a2                # vA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit8: /* 0xd8 */
-/* File: mips64/op_add_int_lit8.S */
-/* File: mips64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5905,13 +5262,9 @@ TODO
     SET_VREG a0, a2                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int_lit8: /* 0xd9 */
-/* File: mips64/op_rsub_int_lit8.S */
-/* File: mips64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5940,13 +5293,9 @@ TODO
     SET_VREG a0, a2                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit8: /* 0xda */
-/* File: mips64/op_mul_int_lit8.S */
-/* File: mips64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -5975,13 +5324,9 @@ TODO
     SET_VREG a0, a2                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit8: /* 0xdb */
-/* File: mips64/op_div_int_lit8.S */
-/* File: mips64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6010,13 +5355,9 @@ TODO
     SET_VREG a0, a2                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit8: /* 0xdc */
-/* File: mips64/op_rem_int_lit8.S */
-/* File: mips64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6045,13 +5386,9 @@ TODO
     SET_VREG a0, a2                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit8: /* 0xdd */
-/* File: mips64/op_and_int_lit8.S */
-/* File: mips64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6080,13 +5417,9 @@ TODO
     SET_VREG a0, a2                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit8: /* 0xde */
-/* File: mips64/op_or_int_lit8.S */
-/* File: mips64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6115,13 +5448,9 @@ TODO
     SET_VREG a0, a2                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit8: /* 0xdf */
-/* File: mips64/op_xor_int_lit8.S */
-/* File: mips64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6150,13 +5479,9 @@ TODO
     SET_VREG a0, a2                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_lit8: /* 0xe0 */
-/* File: mips64/op_shl_int_lit8.S */
-/* File: mips64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6185,13 +5510,9 @@ TODO
     SET_VREG a0, a2                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_lit8: /* 0xe1 */
-/* File: mips64/op_shr_int_lit8.S */
-/* File: mips64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6220,13 +5541,9 @@ TODO
     SET_VREG a0, a2                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_lit8: /* 0xe2 */
-/* File: mips64/op_ushr_int_lit8.S */
-/* File: mips64/binopLit8.S */
     /*
      * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
      * that specifies an instruction that performs "result = a0 op a1".
@@ -6255,12 +5572,9 @@ TODO
     SET_VREG a0, a2                # vAA <- a0
     GOTO_OPCODE v0                      # jump to next instruction
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_quick: /* 0xe3 */
-/* File: mips64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
@@ -6278,7 +5592,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide_quick: /* 0xe4 */
-/* File: mips64/op_iget_wide_quick.S */
     /* iget-wide-quick vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
     lhu     a4, 2(rPC)                  # a4 <- field byte offset
@@ -6297,7 +5610,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object_quick: /* 0xe5 */
-/* File: mips64/op_iget_object_quick.S */
     /* For: iget-object-quick */
     /* op vA, vB, offset//CCCC */
     .extern artIGetObjectFromMterp
@@ -6318,7 +5630,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_iput_quick: /* 0xe6 */
-/* File: mips64/op_iput_quick.S */
     /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
@@ -6336,7 +5647,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide_quick: /* 0xe7 */
-/* File: mips64/op_iput_wide_quick.S */
     /* iput-wide-quick vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
     lhu     a3, 2(rPC)                  # a3 <- field byte offset
@@ -6355,7 +5665,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object_quick: /* 0xe8 */
-/* File: mips64/op_iput_object_quick.S */
     .extern MterpIputObjectQuick
     EXPORT_PC
     daddu   a0, rFP, OFF_FP_SHADOWFRAME
@@ -6370,8 +5679,6 @@ TODO
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_quick: /* 0xe9 */
-/* File: mips64/op_invoke_virtual_quick.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -6392,12 +5699,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range_quick: /* 0xea */
-/* File: mips64/op_invoke_virtual_range_quick.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -6418,12 +5722,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean_quick: /* 0xeb */
-/* File: mips64/op_iput_boolean_quick.S */
-/* File: mips64/op_iput_quick.S */
     /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
@@ -6438,12 +5739,9 @@ TODO
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte_quick: /* 0xec */
-/* File: mips64/op_iput_byte_quick.S */
-/* File: mips64/op_iput_quick.S */
     /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
@@ -6458,12 +5756,9 @@ TODO
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char_quick: /* 0xed */
-/* File: mips64/op_iput_char_quick.S */
-/* File: mips64/op_iput_quick.S */
     /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
@@ -6478,12 +5773,9 @@ TODO
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short_quick: /* 0xee */
-/* File: mips64/op_iput_short_quick.S */
-/* File: mips64/op_iput_quick.S */
     /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
@@ -6498,12 +5790,9 @@ TODO
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean_quick: /* 0xef */
-/* File: mips64/op_iget_boolean_quick.S */
-/* File: mips64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
@@ -6518,12 +5807,9 @@ TODO
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte_quick: /* 0xf0 */
-/* File: mips64/op_iget_byte_quick.S */
-/* File: mips64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
@@ -6538,12 +5824,9 @@ TODO
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char_quick: /* 0xf1 */
-/* File: mips64/op_iget_char_quick.S */
-/* File: mips64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
@@ -6558,12 +5841,9 @@ TODO
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short_quick: /* 0xf2 */
-/* File: mips64/op_iget_short_quick.S */
-/* File: mips64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset//CCCC */
     srl     a2, rINST, 12               # a2 <- B
@@ -6578,89 +5858,65 @@ TODO
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f3: /* 0xf3 */
-/* File: mips64/op_unused_f3.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f4: /* 0xf4 */
-/* File: mips64/op_unused_f4.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f5: /* 0xf5 */
-/* File: mips64/op_unused_f5.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f6: /* 0xf6 */
-/* File: mips64/op_unused_f6.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f7: /* 0xf7 */
-/* File: mips64/op_unused_f7.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f8: /* 0xf8 */
-/* File: mips64/op_unused_f8.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f9: /* 0xf9 */
-/* File: mips64/op_unused_f9.S */
-/* File: mips64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     b       MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic: /* 0xfa */
-/* File: mips64/op_invoke_polymorphic.S */
-/* File: mips64/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -6681,12 +5937,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic_range: /* 0xfb */
-/* File: mips64/op_invoke_polymorphic_range.S */
-/* File: mips64/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -6707,12 +5960,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom: /* 0xfc */
-/* File: mips64/op_invoke_custom.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -6733,12 +5983,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom_range: /* 0xfd */
-/* File: mips64/op_invoke_custom_range.S */
-/* File: mips64/invoke.S */
     /*
      * Generic invoke handler wrapper.
      */
@@ -6759,12 +6006,9 @@ TODO
     GET_INST_OPCODE v0
     GOTO_OPCODE v0
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_handle: /* 0xfe */
-/* File: mips64/op_const_method_handle.S */
-/* File: mips64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -6782,12 +6026,9 @@ TODO
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_type: /* 0xff */
-/* File: mips64/op_const_method_type.S */
-/* File: mips64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -6805,41 +6046,25 @@ TODO
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
-
     .balign 128
-/* File: mips64/instruction_end.S */
 
     .global artMterpAsmInstructionEnd
 artMterpAsmInstructionEnd:
 
-
-/*
- * ===========================================================================
- *  Sister implementations
- * ===========================================================================
- */
-/* File: mips64/instruction_start_sister.S */
-
     .global artMterpAsmSisterStart
     .text
     .balign 4
 artMterpAsmSisterStart:
 
-/* File: mips64/instruction_end_sister.S */
-
     .global artMterpAsmSisterEnd
 artMterpAsmSisterEnd:
 
-/* File: mips64/instruction_start_alt.S */
-
     .global artMterpAsmAltInstructionStart
 artMterpAsmAltInstructionStart = .L_ALT_op_nop
     .text
-
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_nop: /* 0x00 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6858,7 +6083,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move: /* 0x01 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6877,7 +6101,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_from16: /* 0x02 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6896,7 +6119,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_16: /* 0x03 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6915,7 +6137,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide: /* 0x04 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6934,7 +6155,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_from16: /* 0x05 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6953,7 +6173,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_16: /* 0x06 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6972,7 +6191,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object: /* 0x07 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6991,7 +6209,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_from16: /* 0x08 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7010,7 +6227,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_16: /* 0x09 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7029,7 +6245,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result: /* 0x0a */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7048,7 +6263,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_wide: /* 0x0b */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7067,7 +6281,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_object: /* 0x0c */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7086,7 +6299,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_exception: /* 0x0d */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7105,7 +6317,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void: /* 0x0e */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7124,7 +6335,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return: /* 0x0f */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7143,7 +6353,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_wide: /* 0x10 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7162,7 +6371,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_object: /* 0x11 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7181,7 +6389,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_4: /* 0x12 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7200,7 +6407,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_16: /* 0x13 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7219,7 +6425,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const: /* 0x14 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7238,7 +6443,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_high16: /* 0x15 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7257,7 +6461,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_16: /* 0x16 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7276,7 +6479,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_32: /* 0x17 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7295,7 +6497,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide: /* 0x18 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7314,7 +6515,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_high16: /* 0x19 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7333,7 +6533,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string: /* 0x1a */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7352,7 +6551,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string_jumbo: /* 0x1b */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7371,7 +6569,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_class: /* 0x1c */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7390,7 +6587,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_enter: /* 0x1d */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7409,7 +6605,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_exit: /* 0x1e */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7428,7 +6623,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_check_cast: /* 0x1f */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7447,7 +6641,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_instance_of: /* 0x20 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7466,7 +6659,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_array_length: /* 0x21 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7485,7 +6677,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_instance: /* 0x22 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7504,7 +6695,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_array: /* 0x23 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7523,7 +6713,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array: /* 0x24 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7542,7 +6731,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array_range: /* 0x25 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7561,7 +6749,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_fill_array_data: /* 0x26 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7580,7 +6767,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_throw: /* 0x27 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7599,7 +6785,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto: /* 0x28 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7618,7 +6803,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_16: /* 0x29 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7637,7 +6821,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_32: /* 0x2a */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7656,7 +6839,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_packed_switch: /* 0x2b */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7675,7 +6857,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sparse_switch: /* 0x2c */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7694,7 +6875,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_float: /* 0x2d */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7713,7 +6893,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_float: /* 0x2e */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7732,7 +6911,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_double: /* 0x2f */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7751,7 +6929,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_double: /* 0x30 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7770,7 +6947,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmp_long: /* 0x31 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7789,7 +6965,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eq: /* 0x32 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7808,7 +6983,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ne: /* 0x33 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7827,7 +7001,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lt: /* 0x34 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7846,7 +7019,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ge: /* 0x35 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7865,7 +7037,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gt: /* 0x36 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7884,7 +7055,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_le: /* 0x37 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7903,7 +7073,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eqz: /* 0x38 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7922,7 +7091,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_nez: /* 0x39 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7941,7 +7109,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ltz: /* 0x3a */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7960,7 +7127,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gez: /* 0x3b */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7979,7 +7145,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gtz: /* 0x3c */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7998,7 +7163,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lez: /* 0x3d */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8017,7 +7181,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3e: /* 0x3e */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8036,7 +7199,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3f: /* 0x3f */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8055,7 +7217,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_40: /* 0x40 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8074,7 +7235,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_41: /* 0x41 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8093,7 +7253,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_42: /* 0x42 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8112,7 +7271,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_43: /* 0x43 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8131,7 +7289,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget: /* 0x44 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8150,7 +7307,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_wide: /* 0x45 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8169,7 +7325,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_object: /* 0x46 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8188,7 +7343,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_boolean: /* 0x47 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8207,7 +7361,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_byte: /* 0x48 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8226,7 +7379,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_char: /* 0x49 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8245,7 +7397,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_short: /* 0x4a */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8264,7 +7415,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput: /* 0x4b */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8283,7 +7433,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_wide: /* 0x4c */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8302,7 +7451,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_object: /* 0x4d */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8321,7 +7469,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_boolean: /* 0x4e */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8340,7 +7487,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_byte: /* 0x4f */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8359,7 +7505,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_char: /* 0x50 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8378,7 +7523,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_short: /* 0x51 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8397,7 +7541,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget: /* 0x52 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8416,7 +7559,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide: /* 0x53 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8435,7 +7577,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object: /* 0x54 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8454,7 +7595,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean: /* 0x55 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8473,7 +7613,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte: /* 0x56 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8492,7 +7631,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char: /* 0x57 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8511,7 +7649,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short: /* 0x58 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8530,7 +7667,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput: /* 0x59 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8549,7 +7685,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide: /* 0x5a */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8568,7 +7703,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object: /* 0x5b */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8587,7 +7721,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean: /* 0x5c */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8606,7 +7739,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte: /* 0x5d */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8625,7 +7757,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char: /* 0x5e */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8644,7 +7775,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short: /* 0x5f */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8663,7 +7793,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget: /* 0x60 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8682,7 +7811,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_wide: /* 0x61 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8701,7 +7829,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_object: /* 0x62 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8720,7 +7847,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_boolean: /* 0x63 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8739,7 +7865,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_byte: /* 0x64 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8758,7 +7883,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_char: /* 0x65 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8777,7 +7901,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_short: /* 0x66 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8796,7 +7919,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput: /* 0x67 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8815,7 +7937,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_wide: /* 0x68 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8834,7 +7955,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_object: /* 0x69 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8853,7 +7973,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_boolean: /* 0x6a */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8872,7 +7991,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_byte: /* 0x6b */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8891,7 +8009,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_char: /* 0x6c */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8910,7 +8027,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_short: /* 0x6d */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8929,7 +8045,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual: /* 0x6e */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8948,7 +8063,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super: /* 0x6f */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8967,7 +8081,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct: /* 0x70 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8986,7 +8099,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static: /* 0x71 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9005,7 +8117,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface: /* 0x72 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9024,7 +8135,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void_no_barrier: /* 0x73 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9043,7 +8153,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range: /* 0x74 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9062,7 +8171,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super_range: /* 0x75 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9081,7 +8189,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct_range: /* 0x76 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9100,7 +8207,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static_range: /* 0x77 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9119,7 +8225,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface_range: /* 0x78 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9138,7 +8243,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_79: /* 0x79 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9157,7 +8261,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_7a: /* 0x7a */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9176,7 +8279,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_int: /* 0x7b */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9195,7 +8297,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_int: /* 0x7c */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9214,7 +8315,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_long: /* 0x7d */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9233,7 +8333,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_long: /* 0x7e */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9252,7 +8351,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_float: /* 0x7f */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9271,7 +8369,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_double: /* 0x80 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9290,7 +8387,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_long: /* 0x81 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9309,7 +8405,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_float: /* 0x82 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9328,7 +8423,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_double: /* 0x83 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9347,7 +8441,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_int: /* 0x84 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9366,7 +8459,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_float: /* 0x85 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9385,7 +8477,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_double: /* 0x86 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9404,7 +8495,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_int: /* 0x87 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9423,7 +8513,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_long: /* 0x88 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9442,7 +8531,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_double: /* 0x89 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9461,7 +8549,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_int: /* 0x8a */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9480,7 +8567,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_long: /* 0x8b */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9499,7 +8585,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_float: /* 0x8c */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9518,7 +8603,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_byte: /* 0x8d */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9537,7 +8621,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_char: /* 0x8e */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9556,7 +8639,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_short: /* 0x8f */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9575,7 +8657,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int: /* 0x90 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9594,7 +8675,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int: /* 0x91 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9613,7 +8693,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int: /* 0x92 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9632,7 +8711,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int: /* 0x93 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9651,7 +8729,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int: /* 0x94 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9670,7 +8747,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int: /* 0x95 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9689,7 +8765,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int: /* 0x96 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9708,7 +8783,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int: /* 0x97 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9727,7 +8801,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int: /* 0x98 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9746,7 +8819,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int: /* 0x99 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9765,7 +8837,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int: /* 0x9a */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9784,7 +8855,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long: /* 0x9b */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9803,7 +8873,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long: /* 0x9c */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9822,7 +8891,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long: /* 0x9d */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9841,7 +8909,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long: /* 0x9e */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9860,7 +8927,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long: /* 0x9f */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9879,7 +8945,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long: /* 0xa0 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9898,7 +8963,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long: /* 0xa1 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9917,7 +8981,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long: /* 0xa2 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9936,7 +8999,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long: /* 0xa3 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9955,7 +9017,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long: /* 0xa4 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9974,7 +9035,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long: /* 0xa5 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9993,7 +9053,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float: /* 0xa6 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10012,7 +9071,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float: /* 0xa7 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10031,7 +9089,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float: /* 0xa8 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10050,7 +9107,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float: /* 0xa9 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10069,7 +9125,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float: /* 0xaa */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10088,7 +9143,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double: /* 0xab */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10107,7 +9161,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double: /* 0xac */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10126,7 +9179,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double: /* 0xad */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10145,7 +9197,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double: /* 0xae */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10164,7 +9215,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double: /* 0xaf */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10183,7 +9233,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_2addr: /* 0xb0 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10202,7 +9251,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int_2addr: /* 0xb1 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10221,7 +9269,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_2addr: /* 0xb2 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10240,7 +9287,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_2addr: /* 0xb3 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10259,7 +9305,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_2addr: /* 0xb4 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10278,7 +9323,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_2addr: /* 0xb5 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10297,7 +9341,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_2addr: /* 0xb6 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10316,7 +9359,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_2addr: /* 0xb7 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10335,7 +9377,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_2addr: /* 0xb8 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10354,7 +9395,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_2addr: /* 0xb9 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10373,7 +9413,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_2addr: /* 0xba */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10392,7 +9431,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long_2addr: /* 0xbb */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10411,7 +9449,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long_2addr: /* 0xbc */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10430,7 +9467,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long_2addr: /* 0xbd */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10449,7 +9485,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long_2addr: /* 0xbe */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10468,7 +9503,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long_2addr: /* 0xbf */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10487,7 +9521,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long_2addr: /* 0xc0 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10506,7 +9539,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long_2addr: /* 0xc1 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10525,7 +9557,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long_2addr: /* 0xc2 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10544,7 +9575,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long_2addr: /* 0xc3 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10563,7 +9593,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long_2addr: /* 0xc4 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10582,7 +9611,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long_2addr: /* 0xc5 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10601,7 +9629,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float_2addr: /* 0xc6 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10620,7 +9647,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float_2addr: /* 0xc7 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10639,7 +9665,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float_2addr: /* 0xc8 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10658,7 +9683,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float_2addr: /* 0xc9 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10677,7 +9701,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float_2addr: /* 0xca */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10696,7 +9719,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double_2addr: /* 0xcb */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10715,7 +9737,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double_2addr: /* 0xcc */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10734,7 +9755,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double_2addr: /* 0xcd */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10753,7 +9773,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double_2addr: /* 0xce */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10772,7 +9791,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double_2addr: /* 0xcf */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10791,7 +9809,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit16: /* 0xd0 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10810,7 +9827,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int: /* 0xd1 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10829,7 +9845,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit16: /* 0xd2 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10848,7 +9863,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit16: /* 0xd3 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10867,7 +9881,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit16: /* 0xd4 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10886,7 +9899,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit16: /* 0xd5 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10905,7 +9917,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit16: /* 0xd6 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10924,7 +9935,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit16: /* 0xd7 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10943,7 +9953,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit8: /* 0xd8 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10962,7 +9971,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int_lit8: /* 0xd9 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10981,7 +9989,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit8: /* 0xda */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11000,7 +10007,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit8: /* 0xdb */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11019,7 +10025,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit8: /* 0xdc */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11038,7 +10043,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit8: /* 0xdd */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11057,7 +10061,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit8: /* 0xde */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11076,7 +10079,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit8: /* 0xdf */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11095,7 +10097,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_lit8: /* 0xe0 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11114,7 +10115,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_lit8: /* 0xe1 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11133,7 +10133,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_lit8: /* 0xe2 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11152,7 +10151,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_quick: /* 0xe3 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11171,7 +10169,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide_quick: /* 0xe4 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11190,7 +10187,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object_quick: /* 0xe5 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11209,7 +10205,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_quick: /* 0xe6 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11228,7 +10223,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide_quick: /* 0xe7 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11247,7 +10241,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object_quick: /* 0xe8 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11266,7 +10259,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11285,7 +10277,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11304,7 +10295,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean_quick: /* 0xeb */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11323,7 +10313,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte_quick: /* 0xec */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11342,7 +10331,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char_quick: /* 0xed */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11361,7 +10349,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short_quick: /* 0xee */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11380,7 +10367,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean_quick: /* 0xef */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11399,7 +10385,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte_quick: /* 0xf0 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11418,7 +10403,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char_quick: /* 0xf1 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11437,7 +10421,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short_quick: /* 0xf2 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11456,7 +10439,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f3: /* 0xf3 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11475,7 +10457,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f4: /* 0xf4 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11494,7 +10475,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f5: /* 0xf5 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11513,7 +10493,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f6: /* 0xf6 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11532,7 +10511,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f7: /* 0xf7 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11551,7 +10529,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f8: /* 0xf8 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11570,7 +10547,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f9: /* 0xf9 */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11589,7 +10565,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic: /* 0xfa */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11608,7 +10583,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11627,7 +10601,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom: /* 0xfc */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11646,7 +10619,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom_range: /* 0xfd */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11665,7 +10637,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_handle: /* 0xfe */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11684,7 +10655,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_type: /* 0xff */
-/* File: mips64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11701,12 +10671,9 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop
     jalr    zero, t9                            # (self, shadow_frame, dex_pc_ptr) Note: tail call.
 
     .balign 128
-/* File: mips64/instruction_end_alt.S */
 
     .global artMterpAsmAltInstructionEnd
 artMterpAsmAltInstructionEnd:
-
-/* File: mips64/footer.S */
 /*
  * We've detected a condition that will result in an exception, but the exception
  * has not yet been thrown.  Just bail out to the reference interpreter to deal with it.
@@ -11880,7 +10847,7 @@ MterpCommonTakenBranchNoFlags:
     EXPORT_PC
     jal     MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset)
     bnezc   v0, MterpOnStackReplacement
-    FETCH_ADVANCE_INST 2 
+    FETCH_ADVANCE_INST 2
     GET_INST_OPCODE v0                  # extract opcode from rINST
     GOTO_OPCODE v0                      # jump to next instruction
 
@@ -11983,4 +10950,3 @@ MterpProfileActive:
     .cfi_endproc
     .set    reorder
     .size ExecuteMterpImpl, .-ExecuteMterpImpl
-
diff --git a/runtime/interpreter/mterp/out/mterp_x86.S b/runtime/interpreter/mterp/out/mterp_x86.S
index 32811ff370c6660fe1fda6e92eab5aced9a2d30c..5a1bbf264b149bda34fb3c18b837ca66b228216a 100644
--- a/runtime/interpreter/mterp/out/mterp_x86.S
+++ b/runtime/interpreter/mterp/out/mterp_x86.S
@@ -1,10 +1,4 @@
-/*
- * This file was generated automatically by gen-mterp.py for 'x86'.
- *
- * --> DO NOT EDIT <--
- */
-
-/* File: x86/header.S */
+/* DO NOT EDIT: This file was generated by gen-mterp.py. */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -321,8 +315,6 @@ unspecified registers or condition codes.
     movl    MACRO_LITERAL(0),  (rREFS,\_vreg,4)
     movl    MACRO_LITERAL(0), 4(rREFS,\_vreg,4)
 .endm
-
-/* File: x86/entry.S */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -407,24 +399,19 @@ SYMBOL(ExecuteMterpImpl):
     GOTO_NEXT
     /* NOTE: no fallthrough */
 
-/* File: x86/instruction_start.S */
-
     OBJECT_TYPE(artMterpAsmInstructionStart)
     ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart)
     .global SYMBOL(artMterpAsmInstructionStart)
 SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .text
-
 /* ------------------------------ */
     .balign 128
 .L_op_nop: /* 0x00 */
-/* File: x86/op_nop.S */
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
 /* ------------------------------ */
     .balign 128
 .L_op_move: /* 0x01 */
-/* File: x86/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     movzbl  rINSTbl, %eax                   # eax <- BA
@@ -441,7 +428,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_from16: /* 0x02 */
-/* File: x86/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     movzx   rINSTbl, %eax                   # eax <- AA
@@ -457,7 +443,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_16: /* 0x03 */
-/* File: x86/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     movzwl  4(rPC), %ecx                    # ecx <- BBBB
@@ -473,7 +458,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide: /* 0x04 */
-/* File: x86/op_move_wide.S */
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -486,7 +470,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_from16: /* 0x05 */
-/* File: x86/op_move_wide_from16.S */
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movzwl  2(rPC), %ecx                    # ecx <- BBBB
@@ -498,7 +481,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_16: /* 0x06 */
-/* File: x86/op_move_wide_16.S */
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movzwl  4(rPC), %ecx                    # ecx<- BBBB
@@ -510,8 +492,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_object: /* 0x07 */
-/* File: x86/op_move_object.S */
-/* File: x86/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     movzbl  rINSTbl, %eax                   # eax <- BA
@@ -525,12 +505,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_from16: /* 0x08 */
-/* File: x86/op_move_object_from16.S */
-/* File: x86/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     movzx   rINSTbl, %eax                   # eax <- AA
@@ -543,12 +520,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_16: /* 0x09 */
-/* File: x86/op_move_object_16.S */
-/* File: x86/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     movzwl  4(rPC), %ecx                    # ecx <- BBBB
@@ -561,11 +535,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 3
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_result: /* 0x0a */
-/* File: x86/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     movl    OFF_FP_RESULT_REGISTER(rFP), %eax    # get pointer to result JType.
@@ -580,7 +552,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_wide: /* 0x0b */
-/* File: x86/op_move_result_wide.S */
     /* move-result-wide vAA */
     movl    OFF_FP_RESULT_REGISTER(rFP), %eax    # get pointer to result JType.
     movl    4(%eax), %ecx                   # Get high
@@ -592,8 +563,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_object: /* 0x0c */
-/* File: x86/op_move_result_object.S */
-/* File: x86/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     movl    OFF_FP_RESULT_REGISTER(rFP), %eax    # get pointer to result JType.
@@ -605,11 +574,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_exception: /* 0x0d */
-/* File: x86/op_move_exception.S */
     /* move-exception vAA */
     movl    rSELF, %ecx
     movl    THREAD_EXCEPTION_OFFSET(%ecx), %eax
@@ -620,7 +587,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_void: /* 0x0e */
-/* File: x86/op_return_void.S */
     .extern MterpThreadFenceForConstructor
     call    SYMBOL(MterpThreadFenceForConstructor)
     movl    rSELF, %eax
@@ -636,7 +602,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return: /* 0x0f */
-/* File: x86/op_return.S */
 /*
  * Return a 32-bit value.
  *
@@ -658,7 +623,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_wide: /* 0x10 */
-/* File: x86/op_return_wide.S */
 /*
  * Return a 64-bit value.
  */
@@ -678,8 +642,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_object: /* 0x11 */
-/* File: x86/op_return_object.S */
-/* File: x86/op_return.S */
 /*
  * Return a 32-bit value.
  *
@@ -698,11 +660,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     xorl    %ecx, %ecx
     jmp     MterpReturn
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_4: /* 0x12 */
-/* File: x86/op_const_4.S */
     /* const/4 vA, #+B */
     movsx   rINSTbl, %eax                   # eax <-ssssssBx
     movl    $0xf, rINST
@@ -714,7 +674,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_16: /* 0x13 */
-/* File: x86/op_const_16.S */
     /* const/16 vAA, #+BBBB */
     movswl  2(rPC), %ecx                    # ecx <- ssssBBBB
     SET_VREG %ecx, rINST                    # vAA <- ssssBBBB
@@ -723,7 +682,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const: /* 0x14 */
-/* File: x86/op_const.S */
     /* const vAA, #+BBBBbbbb */
     movl    2(rPC), %eax                    # grab all 32 bits at once
     SET_VREG %eax, rINST                    # vAA<- eax
@@ -732,7 +690,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_high16: /* 0x15 */
-/* File: x86/op_const_high16.S */
     /* const/high16 vAA, #+BBBB0000 */
     movzwl  2(rPC), %eax                    # eax <- 0000BBBB
     sall    $16, %eax                      # eax <- BBBB0000
@@ -742,7 +699,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_16: /* 0x16 */
-/* File: x86/op_const_wide_16.S */
     /* const-wide/16 vAA, #+BBBB */
     movswl  2(rPC), %eax                    # eax <- ssssBBBB
     movl    rIBASE, %ecx                    # preserve rIBASE (cltd trashes it)
@@ -755,7 +711,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_32: /* 0x17 */
-/* File: x86/op_const_wide_32.S */
     /* const-wide/32 vAA, #+BBBBbbbb */
     movl    2(rPC), %eax                    # eax <- BBBBbbbb
     movl    rIBASE, %ecx                    # preserve rIBASE (cltd trashes it)
@@ -768,7 +723,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide: /* 0x18 */
-/* File: x86/op_const_wide.S */
     /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
     movl    2(rPC), %eax                    # eax <- lsw
     movzbl  rINSTbl, %ecx                   # ecx <- AA
@@ -780,7 +734,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_high16: /* 0x19 */
-/* File: x86/op_const_wide_high16.S */
     /* const-wide/high16 vAA, #+BBBB000000000000 */
     movzwl  2(rPC), %eax                    # eax <- 0000BBBB
     sall    $16, %eax                      # eax <- BBBB0000
@@ -792,8 +745,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_string: /* 0x1a */
-/* File: x86/op_const_string.S */
-/* File: x86/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -813,11 +764,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jnz     MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_string_jumbo: /* 0x1b */
-/* File: x86/op_const_string_jumbo.S */
     /* const/string vAA, String@BBBBBBBB */
     EXPORT_PC
     movl    2(rPC), %eax                    # eax <- BBBB
@@ -836,8 +785,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_class: /* 0x1c */
-/* File: x86/op_const_class.S */
-/* File: x86/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -857,11 +804,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jnz     MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_enter: /* 0x1d */
-/* File: x86/op_monitor_enter.S */
 /*
  * Synchronize on an object.
  */
@@ -880,7 +825,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_exit: /* 0x1e */
-/* File: x86/op_monitor_exit.S */
 /*
  * Unlock an object.
  *
@@ -903,7 +847,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_check_cast: /* 0x1f */
-/* File: x86/op_check_cast.S */
 /*
  * Check to see if a cast from one class to another is allowed.
  */
@@ -926,7 +869,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_instance_of: /* 0x20 */
-/* File: x86/op_instance_of.S */
 /*
  * Check to see if an object reference is an instance of a class.
  *
@@ -957,7 +899,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_array_length: /* 0x21 */
-/* File: x86/op_array_length.S */
 /*
  * Return the length of an array.
  */
@@ -974,7 +915,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_instance: /* 0x22 */
-/* File: x86/op_new_instance.S */
 /*
  * Create a new instance of a class.
  */
@@ -995,7 +935,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_array: /* 0x23 */
-/* File: x86/op_new_array.S */
 /*
  * Allocate an array of objects, specified with the array class
  * and a count.
@@ -1021,7 +960,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array: /* 0x24 */
-/* File: x86/op_filled_new_array.S */
 /*
  * Create a new array with elements filled from registers.
  *
@@ -1045,8 +983,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array_range: /* 0x25 */
-/* File: x86/op_filled_new_array_range.S */
-/* File: x86/op_filled_new_array.S */
 /*
  * Create a new array with elements filled from registers.
  *
@@ -1067,11 +1003,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 3
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_fill_array_data: /* 0x26 */
-/* File: x86/op_fill_array_data.S */
     /* fill-array-data vAA, +BBBBBBBB */
     EXPORT_PC
     movl    2(rPC), %ecx                    # ecx <- BBBBbbbb
@@ -1088,7 +1022,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_throw: /* 0x27 */
-/* File: x86/op_throw.S */
 /*
  * Throw an exception object in the current thread.
  */
@@ -1104,7 +1037,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto: /* 0x28 */
-/* File: x86/op_goto.S */
 /*
  * Unconditional branch, 8-bit offset.
  *
@@ -1119,7 +1051,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_16: /* 0x29 */
-/* File: x86/op_goto_16.S */
 /*
  * Unconditional branch, 16-bit offset.
  *
@@ -1134,7 +1065,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_32: /* 0x2a */
-/* File: x86/op_goto_32.S */
 /*
  * Unconditional branch, 32-bit offset.
  *
@@ -1154,7 +1084,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_packed_switch: /* 0x2b */
-/* File: x86/op_packed_switch.S */
 /*
  * Handle a packed-switch or sparse-switch instruction.  In both cases
  * we decode it and hand it off to a helper function.
@@ -1179,8 +1108,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_sparse_switch: /* 0x2c */
-/* File: x86/op_sparse_switch.S */
-/* File: x86/op_packed_switch.S */
 /*
  * Handle a packed-switch or sparse-switch instruction.  In both cases
  * we decode it and hand it off to a helper function.
@@ -1202,12 +1129,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movl    %eax, rINST
     jmp     MterpCommonTakenBranch
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_float: /* 0x2d */
-/* File: x86/op_cmpl_float.S */
-/* File: x86/fpcmp.S */
 /*
  * Compare two floating-point values.  Puts 0, 1, or -1 into the
  * destination register based on the results of the comparison.
@@ -1243,12 +1167,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_float: /* 0x2e */
-/* File: x86/op_cmpg_float.S */
-/* File: x86/fpcmp.S */
 /*
  * Compare two floating-point values.  Puts 0, 1, or -1 into the
  * destination register based on the results of the comparison.
@@ -1284,12 +1205,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_double: /* 0x2f */
-/* File: x86/op_cmpl_double.S */
-/* File: x86/fpcmp.S */
 /*
  * Compare two floating-point values.  Puts 0, 1, or -1 into the
  * destination register based on the results of the comparison.
@@ -1325,12 +1243,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_double: /* 0x30 */
-/* File: x86/op_cmpg_double.S */
-/* File: x86/fpcmp.S */
 /*
  * Compare two floating-point values.  Puts 0, 1, or -1 into the
  * destination register based on the results of the comparison.
@@ -1366,11 +1281,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmp_long: /* 0x31 */
-/* File: x86/op_cmp_long.S */
 /*
  * Compare two 64-bit values.  Puts 0, 1, or -1 into the destination
  * register based on the results of the comparison.
@@ -1402,8 +1315,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_if_eq: /* 0x32 */
-/* File: x86/op_if_eq.S */
-/* File: x86/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1426,12 +1337,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ne: /* 0x33 */
-/* File: x86/op_if_ne.S */
-/* File: x86/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1454,12 +1362,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lt: /* 0x34 */
-/* File: x86/op_if_lt.S */
-/* File: x86/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1482,12 +1387,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ge: /* 0x35 */
-/* File: x86/op_if_ge.S */
-/* File: x86/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1510,12 +1412,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gt: /* 0x36 */
-/* File: x86/op_if_gt.S */
-/* File: x86/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1538,12 +1437,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_le: /* 0x37 */
-/* File: x86/op_if_le.S */
-/* File: x86/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1566,12 +1462,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_eqz: /* 0x38 */
-/* File: x86/op_if_eqz.S */
-/* File: x86/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1590,12 +1483,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_nez: /* 0x39 */
-/* File: x86/op_if_nez.S */
-/* File: x86/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1614,12 +1504,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ltz: /* 0x3a */
-/* File: x86/op_if_ltz.S */
-/* File: x86/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1638,12 +1525,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gez: /* 0x3b */
-/* File: x86/op_if_gez.S */
-/* File: x86/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1662,12 +1546,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gtz: /* 0x3c */
-/* File: x86/op_if_gtz.S */
-/* File: x86/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1686,12 +1567,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lez: /* 0x3d */
-/* File: x86/op_if_lez.S */
-/* File: x86/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1710,77 +1588,57 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3e: /* 0x3e */
-/* File: x86/op_unused_3e.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3f: /* 0x3f */
-/* File: x86/op_unused_3f.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_40: /* 0x40 */
-/* File: x86/op_unused_40.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_41: /* 0x41 */
-/* File: x86/op_unused_41.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_42: /* 0x42 */
-/* File: x86/op_unused_42.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_43: /* 0x43 */
-/* File: x86/op_unused_43.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget: /* 0x44 */
-/* File: x86/op_aget.S */
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
@@ -1803,7 +1661,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_wide: /* 0x45 */
-/* File: x86/op_aget_wide.S */
 /*
  * Array get, 64 bits.  vAA <- vBB[vCC].
  */
@@ -1824,7 +1681,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_object: /* 0x46 */
-/* File: x86/op_aget_object.S */
 /*
  * Array object get.  vAA <- vBB[vCC].
  *
@@ -1849,8 +1705,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_boolean: /* 0x47 */
-/* File: x86/op_aget_boolean.S */
-/* File: x86/op_aget.S */
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
@@ -1870,12 +1724,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_byte: /* 0x48 */
-/* File: x86/op_aget_byte.S */
-/* File: x86/op_aget.S */
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
@@ -1895,12 +1746,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_char: /* 0x49 */
-/* File: x86/op_aget_char.S */
-/* File: x86/op_aget.S */
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
@@ -1920,12 +1768,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_short: /* 0x4a */
-/* File: x86/op_aget_short.S */
-/* File: x86/op_aget.S */
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
@@ -1945,11 +1790,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput: /* 0x4b */
-/* File: x86/op_aput.S */
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
@@ -1973,7 +1816,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_wide: /* 0x4c */
-/* File: x86/op_aput_wide.S */
 /*
  * Array put, 64 bits.  vBB[vCC] <- vAA.
  *
@@ -1995,7 +1837,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_object: /* 0x4d */
-/* File: x86/op_aput_object.S */
 /*
  * Store an object into an array.  vBB[vCC] <- vAA.
  */
@@ -2015,8 +1856,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_boolean: /* 0x4e */
-/* File: x86/op_aput_boolean.S */
-/* File: x86/op_aput.S */
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
@@ -2037,12 +1876,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movb  rINSTbl, (%eax)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_byte: /* 0x4f */
-/* File: x86/op_aput_byte.S */
-/* File: x86/op_aput.S */
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
@@ -2063,12 +1899,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movb  rINSTbl, (%eax)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_char: /* 0x50 */
-/* File: x86/op_aput_char.S */
-/* File: x86/op_aput.S */
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
@@ -2089,12 +1922,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movw  rINSTw, (%eax)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_short: /* 0x51 */
-/* File: x86/op_aput_short.S */
-/* File: x86/op_aput.S */
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
@@ -2115,12 +1945,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movw  rINSTw, (%eax)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget: /* 0x52 */
-/* File: x86/op_iget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2138,13 +1965,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide: /* 0x53 */
-/* File: x86/op_iget_wide.S */
-/* File: x86/op_iget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2162,14 +1985,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object: /* 0x54 */
-/* File: x86/op_iget_object.S */
-/* File: x86/op_iget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2187,14 +2005,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean: /* 0x55 */
-/* File: x86/op_iget_boolean.S */
-/* File: x86/op_iget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2212,14 +2025,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte: /* 0x56 */
-/* File: x86/op_iget_byte.S */
-/* File: x86/op_iget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2237,14 +2045,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char: /* 0x57 */
-/* File: x86/op_iget_char.S */
-/* File: x86/op_iget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2262,14 +2065,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short: /* 0x58 */
-/* File: x86/op_iget_short.S */
-/* File: x86/op_iget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2287,13 +2085,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput: /* 0x59 */
-/* File: x86/op_iput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2311,13 +2105,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide: /* 0x5a */
-/* File: x86/op_iput_wide.S */
-/* File: x86/op_iput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2335,14 +2125,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object: /* 0x5b */
-/* File: x86/op_iput_object.S */
-/* File: x86/op_iput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2360,14 +2145,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean: /* 0x5c */
-/* File: x86/op_iput_boolean.S */
-/* File: x86/op_iput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2385,14 +2165,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte: /* 0x5d */
-/* File: x86/op_iput_byte.S */
-/* File: x86/op_iput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2410,14 +2185,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char: /* 0x5e */
-/* File: x86/op_iput_char.S */
-/* File: x86/op_iput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2435,14 +2205,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short: /* 0x5f */
-/* File: x86/op_iput_short.S */
-/* File: x86/op_iput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2460,13 +2225,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget: /* 0x60 */
-/* File: x86/op_sget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2484,13 +2245,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_wide: /* 0x61 */
-/* File: x86/op_sget_wide.S */
-/* File: x86/op_sget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2508,14 +2265,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_object: /* 0x62 */
-/* File: x86/op_sget_object.S */
-/* File: x86/op_sget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2533,14 +2285,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_boolean: /* 0x63 */
-/* File: x86/op_sget_boolean.S */
-/* File: x86/op_sget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2558,14 +2305,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_byte: /* 0x64 */
-/* File: x86/op_sget_byte.S */
-/* File: x86/op_sget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2583,14 +2325,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_char: /* 0x65 */
-/* File: x86/op_sget_char.S */
-/* File: x86/op_sget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2608,14 +2345,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_short: /* 0x66 */
-/* File: x86/op_sget_short.S */
-/* File: x86/op_sget.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2633,13 +2365,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput: /* 0x67 */
-/* File: x86/op_sput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2657,13 +2385,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_wide: /* 0x68 */
-/* File: x86/op_sput_wide.S */
-/* File: x86/op_sput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2681,14 +2405,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_object: /* 0x69 */
-/* File: x86/op_sput_object.S */
-/* File: x86/op_sput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2706,14 +2425,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_boolean: /* 0x6a */
-/* File: x86/op_sput_boolean.S */
-/* File: x86/op_sput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2731,14 +2445,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_byte: /* 0x6b */
-/* File: x86/op_sput_byte.S */
-/* File: x86/op_sput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2756,14 +2465,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_char: /* 0x6c */
-/* File: x86/op_sput_char.S */
-/* File: x86/op_sput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2781,14 +2485,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_short: /* 0x6d */
-/* File: x86/op_sput_short.S */
-/* File: x86/op_sput.S */
-/* File: x86/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2806,13 +2505,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual: /* 0x6e */
-/* File: x86/op_invoke_virtual.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2837,7 +2532,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     FETCH_INST
     GOTO_NEXT
-
 /*
  * Handle a virtual method call.
  *
@@ -2849,8 +2543,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super: /* 0x6f */
-/* File: x86/op_invoke_super.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2875,7 +2567,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     FETCH_INST
     GOTO_NEXT
-
 /*
  * Handle a "super" method call.
  *
@@ -2887,8 +2578,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct: /* 0x70 */
-/* File: x86/op_invoke_direct.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2914,12 +2603,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static: /* 0x71 */
-/* File: x86/op_invoke_static.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2945,13 +2631,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface: /* 0x72 */
-/* File: x86/op_invoke_interface.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2976,7 +2658,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     RESTORE_IBASE
     FETCH_INST
     GOTO_NEXT
-
 /*
  * Handle an interface method call.
  *
@@ -2988,7 +2669,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_void_no_barrier: /* 0x73 */
-/* File: x86/op_return_void_no_barrier.S */
     movl    rSELF, %eax
     testl   $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax)
     jz      1f
@@ -3002,8 +2682,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range: /* 0x74 */
-/* File: x86/op_invoke_virtual_range.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -3029,12 +2707,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super_range: /* 0x75 */
-/* File: x86/op_invoke_super_range.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -3060,12 +2735,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct_range: /* 0x76 */
-/* File: x86/op_invoke_direct_range.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -3091,12 +2763,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static_range: /* 0x77 */
-/* File: x86/op_invoke_static_range.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -3122,12 +2791,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface_range: /* 0x78 */
-/* File: x86/op_invoke_interface_range.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -3153,34 +2819,25 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_79: /* 0x79 */
-/* File: x86/op_unused_79.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_7a: /* 0x7a */
-/* File: x86/op_unused_7a.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_int: /* 0x7b */
-/* File: x86/op_neg_int.S */
-/* File: x86/unop.S */
 /*
  * Generic 32-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3194,12 +2851,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, %ecx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_int: /* 0x7c */
-/* File: x86/op_not_int.S */
-/* File: x86/unop.S */
 /*
  * Generic 32-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3213,11 +2867,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, %ecx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_long: /* 0x7d */
-/* File: x86/op_neg_long.S */
     /* unop vA, vB */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
     sarl    $4, %ecx                       # ecx <- B
@@ -3231,11 +2883,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG_HIGH %ecx, rINST               # v[A+1] <- ecx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_long: /* 0x7e */
-/* File: x86/op_not_long.S */
     /* unop vA, vB */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
     sarl    $4, %ecx                       # ecx <- B
@@ -3251,8 +2901,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_neg_float: /* 0x7f */
-/* File: x86/op_neg_float.S */
-/* File: x86/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3270,12 +2918,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_double: /* 0x80 */
-/* File: x86/op_neg_double.S */
-/* File: x86/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3293,11 +2938,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_long: /* 0x81 */
-/* File: x86/op_int_to_long.S */
     /* int to long vA, vB */
     movzbl  rINSTbl, %eax                   # eax <- +A
     sarl    $4, %eax                       # eax <- B
@@ -3310,12 +2953,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movl    %ecx, rIBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_float: /* 0x82 */
-/* File: x86/op_int_to_float.S */
-/* File: x86/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3333,12 +2973,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_double: /* 0x83 */
-/* File: x86/op_int_to_double.S */
-/* File: x86/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3356,13 +2993,10 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_int: /* 0x84 */
-/* File: x86/op_long_to_int.S */
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-/* File: x86/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     movzbl  rINSTbl, %eax                   # eax <- BA
@@ -3376,12 +3010,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_float: /* 0x85 */
-/* File: x86/op_long_to_float.S */
-/* File: x86/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3399,12 +3030,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_double: /* 0x86 */
-/* File: x86/op_long_to_double.S */
-/* File: x86/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3422,12 +3050,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_int: /* 0x87 */
-/* File: x86/op_float_to_int.S */
-/* File: x86/cvtfp_int.S */
 /* On fp to int conversions, Java requires that
  * if the result > maxint, it should be clamped to maxint.  If it is less
  * than minint, it should be clamped to minint.  If it is a nan, the result
@@ -3489,12 +3114,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     jmp     .Lop_float_to_int_finish
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_long: /* 0x88 */
-/* File: x86/op_float_to_long.S */
-/* File: x86/cvtfp_int.S */
 /* On fp to int conversions, Java requires that
  * if the result > maxint, it should be clamped to maxint.  If it is less
  * than minint, it should be clamped to minint.  If it is a nan, the result
@@ -3556,12 +3178,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     jmp     .Lop_float_to_long_finish
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_double: /* 0x89 */
-/* File: x86/op_float_to_double.S */
-/* File: x86/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3579,12 +3198,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_int: /* 0x8a */
-/* File: x86/op_double_to_int.S */
-/* File: x86/cvtfp_int.S */
 /* On fp to int conversions, Java requires that
  * if the result > maxint, it should be clamped to maxint.  If it is less
  * than minint, it should be clamped to minint.  If it is a nan, the result
@@ -3646,12 +3262,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     jmp     .Lop_double_to_int_finish
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_long: /* 0x8b */
-/* File: x86/op_double_to_long.S */
-/* File: x86/cvtfp_int.S */
 /* On fp to int conversions, Java requires that
  * if the result > maxint, it should be clamped to maxint.  If it is less
  * than minint, it should be clamped to minint.  If it is a nan, the result
@@ -3713,12 +3326,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     jmp     .Lop_double_to_long_finish
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_float: /* 0x8c */
-/* File: x86/op_double_to_float.S */
-/* File: x86/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3736,12 +3346,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_byte: /* 0x8d */
-/* File: x86/op_int_to_byte.S */
-/* File: x86/unop.S */
 /*
  * Generic 32-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3755,12 +3362,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, %ecx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_char: /* 0x8e */
-/* File: x86/op_int_to_char.S */
-/* File: x86/unop.S */
 /*
  * Generic 32-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3774,12 +3378,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, %ecx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_short: /* 0x8f */
-/* File: x86/op_int_to_short.S */
-/* File: x86/unop.S */
 /*
  * Generic 32-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3793,12 +3394,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, %ecx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int: /* 0x90 */
-/* File: x86/op_add_int.S */
-/* File: x86/binop.S */
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
@@ -3816,12 +3414,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int: /* 0x91 */
-/* File: x86/op_sub_int.S */
-/* File: x86/binop.S */
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
@@ -3839,11 +3434,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int: /* 0x92 */
-/* File: x86/op_mul_int.S */
     /*
      * 32-bit binary multiplication.
      */
@@ -3860,8 +3453,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_div_int: /* 0x93 */
-/* File: x86/op_div_int.S */
-/* File: x86/bindiv.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op0=minint and
  * op1=-1.
@@ -3910,12 +3501,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     mov     LOCAL0(%esp), rIBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int: /* 0x94 */
-/* File: x86/op_rem_int.S */
-/* File: x86/bindiv.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op0=minint and
  * op1=-1.
@@ -3964,12 +3552,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     mov     LOCAL0(%esp), rIBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int: /* 0x95 */
-/* File: x86/op_and_int.S */
-/* File: x86/binop.S */
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
@@ -3987,12 +3572,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int: /* 0x96 */
-/* File: x86/op_or_int.S */
-/* File: x86/binop.S */
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
@@ -4010,12 +3592,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int: /* 0x97 */
-/* File: x86/op_xor_int.S */
-/* File: x86/binop.S */
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
@@ -4033,12 +3612,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int: /* 0x98 */
-/* File: x86/op_shl_int.S */
-/* File: x86/binop1.S */
 /*
  * Generic 32-bit binary operation in which both operands loaded to
  * registers (op0 in eax, op1 in ecx).
@@ -4052,12 +3628,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int: /* 0x99 */
-/* File: x86/op_shr_int.S */
-/* File: x86/binop1.S */
 /*
  * Generic 32-bit binary operation in which both operands loaded to
  * registers (op0 in eax, op1 in ecx).
@@ -4071,12 +3644,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int: /* 0x9a */
-/* File: x86/op_ushr_int.S */
-/* File: x86/binop1.S */
 /*
  * Generic 32-bit binary operation in which both operands loaded to
  * registers (op0 in eax, op1 in ecx).
@@ -4090,12 +3660,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long: /* 0x9b */
-/* File: x86/op_add_long.S */
-/* File: x86/binopWide.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4112,12 +3679,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG_HIGH %eax, rINST               # v[AA+1] <- eax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long: /* 0x9c */
-/* File: x86/op_sub_long.S */
-/* File: x86/binopWide.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4134,11 +3698,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG_HIGH %eax, rINST               # v[AA+1] <- eax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long: /* 0x9d */
-/* File: x86/op_mul_long.S */
 /*
  * Signed 64-bit integer multiply.
  *
@@ -4176,7 +3738,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_div_long: /* 0x9e */
-/* File: x86/op_div_long.S */
 /* art_quick_* methods has quick abi,
  *   so use eax, ecx, edx, ebx for args
  */
@@ -4203,8 +3764,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long: /* 0x9f */
-/* File: x86/op_rem_long.S */
-/* File: x86/op_div_long.S */
 /* art_quick_* methods has quick abi,
  *   so use eax, ecx, edx, ebx for args
  */
@@ -4228,12 +3787,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     mov     LOCAL0(%esp), rIBASE            # restore rIBASE/%edx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long: /* 0xa0 */
-/* File: x86/op_and_long.S */
-/* File: x86/binopWide.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4250,12 +3806,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG_HIGH %eax, rINST               # v[AA+1] <- eax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long: /* 0xa1 */
-/* File: x86/op_or_long.S */
-/* File: x86/binopWide.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4272,12 +3825,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG_HIGH %eax, rINST               # v[AA+1] <- eax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long: /* 0xa2 */
-/* File: x86/op_xor_long.S */
-/* File: x86/binopWide.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4294,11 +3844,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG_HIGH %eax, rINST               # v[AA+1] <- eax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long: /* 0xa3 */
-/* File: x86/op_shl_long.S */
 /*
  * Long integer shift.  This is different from the generic 32/64-bit
  * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -4332,7 +3880,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long: /* 0xa4 */
-/* File: x86/op_shr_long.S */
 /*
  * Long integer shift.  This is different from the generic 32/64-bit
  * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -4366,7 +3913,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long: /* 0xa5 */
-/* File: x86/op_ushr_long.S */
 /*
  * Long integer shift.  This is different from the generic 32/64-bit
  * binary operations because vAA/vBB are 64-bit but vCC (the shift
@@ -4400,8 +3946,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_add_float: /* 0xa6 */
-/* File: x86/op_add_float.S */
-/* File: x86/sseBinop.S */
     movzbl  2(rPC), %ecx                    # ecx <- BB
     movzbl  3(rPC), %eax                    # eax <- CC
     movss   VREG_ADDRESS(%ecx), %xmm0  # %xmm0 <- 1st src
@@ -4411,12 +3955,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movss   %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float: /* 0xa7 */
-/* File: x86/op_sub_float.S */
-/* File: x86/sseBinop.S */
     movzbl  2(rPC), %ecx                    # ecx <- BB
     movzbl  3(rPC), %eax                    # eax <- CC
     movss   VREG_ADDRESS(%ecx), %xmm0  # %xmm0 <- 1st src
@@ -4426,12 +3967,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movss   %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float: /* 0xa8 */
-/* File: x86/op_mul_float.S */
-/* File: x86/sseBinop.S */
     movzbl  2(rPC), %ecx                    # ecx <- BB
     movzbl  3(rPC), %eax                    # eax <- CC
     movss   VREG_ADDRESS(%ecx), %xmm0  # %xmm0 <- 1st src
@@ -4441,12 +3979,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movss   %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float: /* 0xa9 */
-/* File: x86/op_div_float.S */
-/* File: x86/sseBinop.S */
     movzbl  2(rPC), %ecx                    # ecx <- BB
     movzbl  3(rPC), %eax                    # eax <- CC
     movss   VREG_ADDRESS(%ecx), %xmm0  # %xmm0 <- 1st src
@@ -4456,11 +3991,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movss   %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float: /* 0xaa */
-/* File: x86/op_rem_float.S */
     /* rem_float vAA, vBB, vCC */
     movzbl  3(rPC), %ecx                    # ecx <- BB
     movzbl  2(rPC), %eax                    # eax <- CC
@@ -4479,8 +4012,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_add_double: /* 0xab */
-/* File: x86/op_add_double.S */
-/* File: x86/sseBinop.S */
     movzbl  2(rPC), %ecx                    # ecx <- BB
     movzbl  3(rPC), %eax                    # eax <- CC
     movsd   VREG_ADDRESS(%ecx), %xmm0  # %xmm0 <- 1st src
@@ -4490,12 +4021,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movsd   %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double: /* 0xac */
-/* File: x86/op_sub_double.S */
-/* File: x86/sseBinop.S */
     movzbl  2(rPC), %ecx                    # ecx <- BB
     movzbl  3(rPC), %eax                    # eax <- CC
     movsd   VREG_ADDRESS(%ecx), %xmm0  # %xmm0 <- 1st src
@@ -4505,12 +4033,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movsd   %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double: /* 0xad */
-/* File: x86/op_mul_double.S */
-/* File: x86/sseBinop.S */
     movzbl  2(rPC), %ecx                    # ecx <- BB
     movzbl  3(rPC), %eax                    # eax <- CC
     movsd   VREG_ADDRESS(%ecx), %xmm0  # %xmm0 <- 1st src
@@ -4520,12 +4045,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movsd   %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double: /* 0xae */
-/* File: x86/op_div_double.S */
-/* File: x86/sseBinop.S */
     movzbl  2(rPC), %ecx                    # ecx <- BB
     movzbl  3(rPC), %eax                    # eax <- CC
     movsd   VREG_ADDRESS(%ecx), %xmm0  # %xmm0 <- 1st src
@@ -4535,11 +4057,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movsd   %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double: /* 0xaf */
-/* File: x86/op_rem_double.S */
     /* rem_double vAA, vBB, vCC */
     movzbl  3(rPC), %ecx                    # ecx <- BB
     movzbl  2(rPC), %eax                    # eax <- CC
@@ -4558,8 +4078,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_2addr: /* 0xb0 */
-/* File: x86/op_add_int_2addr.S */
-/* File: x86/binop2addr.S */
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
@@ -4579,12 +4097,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     CLEAR_REF %ecx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int_2addr: /* 0xb1 */
-/* File: x86/op_sub_int_2addr.S */
-/* File: x86/binop2addr.S */
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
@@ -4604,11 +4119,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     CLEAR_REF %ecx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_2addr: /* 0xb2 */
-/* File: x86/op_mul_int_2addr.S */
     /* mul vA, vB */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     sarl    $4, rINST                      # rINST <- B
@@ -4623,8 +4136,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_2addr: /* 0xb3 */
-/* File: x86/op_div_int_2addr.S */
-/* File: x86/bindiv2addr.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op0=minint and
  * op1=-1.
@@ -4654,12 +4165,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     mov     LOCAL0(%esp), rIBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_2addr: /* 0xb4 */
-/* File: x86/op_rem_int_2addr.S */
-/* File: x86/bindiv2addr.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op0=minint and
  * op1=-1.
@@ -4689,12 +4197,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     mov     LOCAL0(%esp), rIBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_2addr: /* 0xb5 */
-/* File: x86/op_and_int_2addr.S */
-/* File: x86/binop2addr.S */
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
@@ -4714,12 +4219,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     CLEAR_REF %ecx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_2addr: /* 0xb6 */
-/* File: x86/op_or_int_2addr.S */
-/* File: x86/binop2addr.S */
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
@@ -4739,12 +4241,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     CLEAR_REF %ecx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_2addr: /* 0xb7 */
-/* File: x86/op_xor_int_2addr.S */
-/* File: x86/binop2addr.S */
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
@@ -4764,12 +4263,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     CLEAR_REF %ecx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_2addr: /* 0xb8 */
-/* File: x86/op_shl_int_2addr.S */
-/* File: x86/shop2addr.S */
 /*
  * Generic 32-bit "shift/2addr" operation.
  */
@@ -4783,12 +4279,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_2addr: /* 0xb9 */
-/* File: x86/op_shr_int_2addr.S */
-/* File: x86/shop2addr.S */
 /*
  * Generic 32-bit "shift/2addr" operation.
  */
@@ -4802,12 +4295,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_2addr: /* 0xba */
-/* File: x86/op_ushr_int_2addr.S */
-/* File: x86/shop2addr.S */
 /*
  * Generic 32-bit "shift/2addr" operation.
  */
@@ -4821,12 +4311,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long_2addr: /* 0xbb */
-/* File: x86/op_add_long_2addr.S */
-/* File: x86/binopWide2addr.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4841,12 +4328,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     CLEAR_WIDE_REF rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long_2addr: /* 0xbc */
-/* File: x86/op_sub_long_2addr.S */
-/* File: x86/binopWide2addr.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4861,11 +4345,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     CLEAR_WIDE_REF rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long_2addr: /* 0xbd */
-/* File: x86/op_mul_long_2addr.S */
 /*
  * Signed 64-bit integer multiply, 2-addr version
  *
@@ -4905,7 +4387,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_div_long_2addr: /* 0xbe */
-/* File: x86/op_div_long_2addr.S */
 /* art_quick_* methods has quick abi,
  *   so use eax, ecx, edx, ebx for args
  */
@@ -4934,8 +4415,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long_2addr: /* 0xbf */
-/* File: x86/op_rem_long_2addr.S */
-/* File: x86/op_div_long_2addr.S */
 /* art_quick_* methods has quick abi,
  *   so use eax, ecx, edx, ebx for args
  */
@@ -4961,12 +4440,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     mov     LOCAL0(%esp), rIBASE            # restore rIBASE/%edx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long_2addr: /* 0xc0 */
-/* File: x86/op_and_long_2addr.S */
-/* File: x86/binopWide2addr.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4981,12 +4457,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     CLEAR_WIDE_REF rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long_2addr: /* 0xc1 */
-/* File: x86/op_or_long_2addr.S */
-/* File: x86/binopWide2addr.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -5001,12 +4474,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     CLEAR_WIDE_REF rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long_2addr: /* 0xc2 */
-/* File: x86/op_xor_long_2addr.S */
-/* File: x86/binopWide2addr.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -5021,11 +4491,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     CLEAR_WIDE_REF rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long_2addr: /* 0xc3 */
-/* File: x86/op_shl_long_2addr.S */
 /*
  * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
  * 32-bit shift distance.
@@ -5056,7 +4524,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long_2addr: /* 0xc4 */
-/* File: x86/op_shr_long_2addr.S */
 /*
  * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
  * 32-bit shift distance.
@@ -5087,7 +4554,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long_2addr: /* 0xc5 */
-/* File: x86/op_ushr_long_2addr.S */
 /*
  * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
  * 32-bit shift distance.
@@ -5118,8 +4584,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_add_float_2addr: /* 0xc6 */
-/* File: x86/op_add_float_2addr.S */
-/* File: x86/sseBinop2Addr.S */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movss VREG_ADDRESS(%ecx), %xmm0      # %xmm0 <- 1st src
@@ -5130,12 +4594,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movss %xmm0, VREG_REF_ADDRESS(rINST)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float_2addr: /* 0xc7 */
-/* File: x86/op_sub_float_2addr.S */
-/* File: x86/sseBinop2Addr.S */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movss VREG_ADDRESS(%ecx), %xmm0      # %xmm0 <- 1st src
@@ -5146,12 +4607,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movss %xmm0, VREG_REF_ADDRESS(rINST)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float_2addr: /* 0xc8 */
-/* File: x86/op_mul_float_2addr.S */
-/* File: x86/sseBinop2Addr.S */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movss VREG_ADDRESS(%ecx), %xmm0      # %xmm0 <- 1st src
@@ -5162,12 +4620,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movss %xmm0, VREG_REF_ADDRESS(rINST)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float_2addr: /* 0xc9 */
-/* File: x86/op_div_float_2addr.S */
-/* File: x86/sseBinop2Addr.S */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movss VREG_ADDRESS(%ecx), %xmm0      # %xmm0 <- 1st src
@@ -5178,11 +4633,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movss %xmm0, VREG_REF_ADDRESS(rINST)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float_2addr: /* 0xca */
-/* File: x86/op_rem_float_2addr.S */
     /* rem_float/2addr vA, vB */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     sarl    $4, rINST                      # rINST <- B
@@ -5202,8 +4655,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_add_double_2addr: /* 0xcb */
-/* File: x86/op_add_double_2addr.S */
-/* File: x86/sseBinop2Addr.S */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movsd VREG_ADDRESS(%ecx), %xmm0      # %xmm0 <- 1st src
@@ -5214,12 +4665,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movsd %xmm0, VREG_REF_ADDRESS(rINST)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double_2addr: /* 0xcc */
-/* File: x86/op_sub_double_2addr.S */
-/* File: x86/sseBinop2Addr.S */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movsd VREG_ADDRESS(%ecx), %xmm0      # %xmm0 <- 1st src
@@ -5230,12 +4678,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movsd %xmm0, VREG_REF_ADDRESS(rINST)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double_2addr: /* 0xcd */
-/* File: x86/op_mul_double_2addr.S */
-/* File: x86/sseBinop2Addr.S */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movsd VREG_ADDRESS(%ecx), %xmm0      # %xmm0 <- 1st src
@@ -5246,12 +4691,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movsd %xmm0, VREG_REF_ADDRESS(rINST)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double_2addr: /* 0xce */
-/* File: x86/op_div_double_2addr.S */
-/* File: x86/sseBinop2Addr.S */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movsd VREG_ADDRESS(%ecx), %xmm0      # %xmm0 <- 1st src
@@ -5262,11 +4704,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movsd %xmm0, VREG_REF_ADDRESS(rINST)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double_2addr: /* 0xcf */
-/* File: x86/op_rem_double_2addr.S */
     /* rem_double/2addr vA, vB */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     sarl    $4, rINST                      # rINST <- B
@@ -5286,8 +4726,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit16: /* 0xd0 */
-/* File: x86/op_add_int_lit16.S */
-/* File: x86/binopLit16.S */
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5307,13 +4745,10 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int: /* 0xd1 */
-/* File: x86/op_rsub_int.S */
 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
-/* File: x86/binopLit16.S */
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5333,11 +4768,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %ecx, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit16: /* 0xd2 */
-/* File: x86/op_mul_int_lit16.S */
     /* mul/lit16 vA, vB, #+CCCC */
     /* Need A in rINST, ssssCCCC in ecx, vB in eax */
     movzbl  rINSTbl, %eax                   # eax <- 000000BA
@@ -5354,8 +4787,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit16: /* 0xd3 */
-/* File: x86/op_div_int_lit16.S */
-/* File: x86/bindivLit16.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op0=minint and
  * op1=-1.
@@ -5385,12 +4816,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     mov     LOCAL0(%esp), rIBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit16: /* 0xd4 */
-/* File: x86/op_rem_int_lit16.S */
-/* File: x86/bindivLit16.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op0=minint and
  * op1=-1.
@@ -5420,12 +4848,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     mov     LOCAL0(%esp), rIBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit16: /* 0xd5 */
-/* File: x86/op_and_int_lit16.S */
-/* File: x86/binopLit16.S */
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5445,12 +4870,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit16: /* 0xd6 */
-/* File: x86/op_or_int_lit16.S */
-/* File: x86/binopLit16.S */
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5470,12 +4892,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit16: /* 0xd7 */
-/* File: x86/op_xor_int_lit16.S */
-/* File: x86/binopLit16.S */
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5495,12 +4914,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit8: /* 0xd8 */
-/* File: x86/op_add_int_lit8.S */
-/* File: x86/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5519,12 +4935,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int_lit8: /* 0xd9 */
-/* File: x86/op_rsub_int_lit8.S */
-/* File: x86/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5543,11 +4956,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %ecx, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit8: /* 0xda */
-/* File: x86/op_mul_int_lit8.S */
     /* mul/lit8 vAA, vBB, #+CC */
     movzbl  2(rPC), %eax                    # eax <- BB
     movl    rIBASE, %ecx
@@ -5561,8 +4972,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit8: /* 0xdb */
-/* File: x86/op_div_int_lit8.S */
-/* File: x86/bindivLit8.S */
 /*
  * 32-bit div/rem "lit8" binary operation.  Handles special case of
  * op0=minint & op1=-1
@@ -5589,12 +4998,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     mov     LOCAL0(%esp), rIBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit8: /* 0xdc */
-/* File: x86/op_rem_int_lit8.S */
-/* File: x86/bindivLit8.S */
 /*
  * 32-bit div/rem "lit8" binary operation.  Handles special case of
  * op0=minint & op1=-1
@@ -5621,12 +5027,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     mov     LOCAL0(%esp), rIBASE
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit8: /* 0xdd */
-/* File: x86/op_and_int_lit8.S */
-/* File: x86/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5645,12 +5048,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit8: /* 0xde */
-/* File: x86/op_or_int_lit8.S */
-/* File: x86/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5669,12 +5069,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit8: /* 0xdf */
-/* File: x86/op_xor_int_lit8.S */
-/* File: x86/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5693,12 +5090,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_lit8: /* 0xe0 */
-/* File: x86/op_shl_int_lit8.S */
-/* File: x86/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5717,12 +5111,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_lit8: /* 0xe1 */
-/* File: x86/op_shr_int_lit8.S */
-/* File: x86/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5741,12 +5132,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_lit8: /* 0xe2 */
-/* File: x86/op_ushr_int_lit8.S */
-/* File: x86/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5765,11 +5153,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_quick: /* 0xe3 */
-/* File: x86/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -5786,7 +5172,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide_quick: /* 0xe4 */
-/* File: x86/op_iget_wide_quick.S */
     /* iget-wide-quick vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
     sarl    $4, %ecx                       # ecx <- B
@@ -5802,7 +5187,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object_quick: /* 0xe5 */
-/* File: x86/op_iget_object_quick.S */
     /* For: iget-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -5824,7 +5208,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_iput_quick: /* 0xe6 */
-/* File: x86/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -5841,7 +5224,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide_quick: /* 0xe7 */
-/* File: x86/op_iput_wide_quick.S */
     /* iput-wide-quick vA, vB, offset@CCCC */
     movzbl    rINSTbl, %ecx                 # ecx<- BA
     sarl      $4, %ecx                     # ecx<- B
@@ -5858,7 +5240,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object_quick: /* 0xe8 */
-/* File: x86/op_iput_object_quick.S */
     EXPORT_PC
     leal    OFF_FP_SHADOWFRAME(rFP), %eax
     movl    %eax, OUT_ARG0(%esp)
@@ -5874,8 +5255,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_quick: /* 0xe9 */
-/* File: x86/op_invoke_virtual_quick.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -5901,12 +5280,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range_quick: /* 0xea */
-/* File: x86/op_invoke_virtual_range_quick.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -5932,12 +5308,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean_quick: /* 0xeb */
-/* File: x86/op_iput_boolean_quick.S */
-/* File: x86/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -5951,12 +5324,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movb    rINSTbl, (%ecx,%eax,1)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte_quick: /* 0xec */
-/* File: x86/op_iput_byte_quick.S */
-/* File: x86/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -5970,12 +5340,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movb    rINSTbl, (%ecx,%eax,1)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char_quick: /* 0xed */
-/* File: x86/op_iput_char_quick.S */
-/* File: x86/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -5989,12 +5356,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movw    rINSTw, (%ecx,%eax,1)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short_quick: /* 0xee */
-/* File: x86/op_iput_short_quick.S */
-/* File: x86/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -6008,12 +5372,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movw    rINSTw, (%ecx,%eax,1)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean_quick: /* 0xef */
-/* File: x86/op_iget_boolean_quick.S */
-/* File: x86/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -6027,12 +5388,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST                    # fp[A] <- value
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte_quick: /* 0xf0 */
-/* File: x86/op_iget_byte_quick.S */
-/* File: x86/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -6046,12 +5404,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST                    # fp[A] <- value
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char_quick: /* 0xf1 */
-/* File: x86/op_iget_char_quick.S */
-/* File: x86/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -6065,12 +5420,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST                    # fp[A] <- value
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short_quick: /* 0xf2 */
-/* File: x86/op_iget_short_quick.S */
-/* File: x86/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
@@ -6084,89 +5436,65 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINST                    # fp[A] <- value
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f3: /* 0xf3 */
-/* File: x86/op_unused_f3.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f4: /* 0xf4 */
-/* File: x86/op_unused_f4.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f5: /* 0xf5 */
-/* File: x86/op_unused_f5.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f6: /* 0xf6 */
-/* File: x86/op_unused_f6.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f7: /* 0xf7 */
-/* File: x86/op_unused_f7.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f8: /* 0xf8 */
-/* File: x86/op_unused_f8.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f9: /* 0xf9 */
-/* File: x86/op_unused_f9.S */
-/* File: x86/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic: /* 0xfa */
-/* File: x86/op_invoke_polymorphic.S */
-/* File: x86/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -6192,12 +5520,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic_range: /* 0xfb */
-/* File: x86/op_invoke_polymorphic_range.S */
-/* File: x86/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -6223,12 +5548,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom: /* 0xfc */
-/* File: x86/op_invoke_custom.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -6254,12 +5576,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom_range: /* 0xfd */
-/* File: x86/op_invoke_custom_range.S */
-/* File: x86/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -6285,12 +5604,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_handle: /* 0xfe */
-/* File: x86/op_const_method_handle.S */
-/* File: x86/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -6310,12 +5626,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jnz     MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_type: /* 0xff */
-/* File: x86/op_const_method_type.S */
-/* File: x86/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -6335,23 +5648,13 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jnz     MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
     .balign 128
-/* File: x86/instruction_end.S */
 
     OBJECT_TYPE(artMterpAsmInstructionEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd)
     .global SYMBOL(artMterpAsmInstructionEnd)
 SYMBOL(artMterpAsmInstructionEnd):
 
-
-/*
- * ===========================================================================
- *  Sister implementations
- * ===========================================================================
- */
-/* File: x86/instruction_start_sister.S */
-
     OBJECT_TYPE(artMterpAsmSisterStart)
     ASM_HIDDEN SYMBOL(artMterpAsmSisterStart)
     .global SYMBOL(artMterpAsmSisterStart)
@@ -6359,25 +5662,19 @@ SYMBOL(artMterpAsmInstructionEnd):
     .balign 4
 SYMBOL(artMterpAsmSisterStart):
 
-/* File: x86/instruction_end_sister.S */
-
     OBJECT_TYPE(artMterpAsmSisterEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd)
     .global SYMBOL(artMterpAsmSisterEnd)
 SYMBOL(artMterpAsmSisterEnd):
 
-/* File: x86/instruction_start_alt.S */
-
     OBJECT_TYPE(artMterpAsmAltInstructionStart)
     ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart)
     .global SYMBOL(artMterpAsmAltInstructionStart)
     .text
 SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
-
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_nop: /* 0x00 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6401,7 +5698,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move: /* 0x01 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6425,7 +5721,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_from16: /* 0x02 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6449,7 +5744,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_16: /* 0x03 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6473,7 +5767,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide: /* 0x04 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6497,7 +5790,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_from16: /* 0x05 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6521,7 +5813,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_16: /* 0x06 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6545,7 +5836,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object: /* 0x07 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6569,7 +5859,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_from16: /* 0x08 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6593,7 +5882,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_16: /* 0x09 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6617,7 +5905,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result: /* 0x0a */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6641,7 +5928,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_wide: /* 0x0b */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6665,7 +5951,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_object: /* 0x0c */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6689,7 +5974,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_exception: /* 0x0d */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6713,7 +5997,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void: /* 0x0e */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6737,7 +6020,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return: /* 0x0f */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6761,7 +6043,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_wide: /* 0x10 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6785,7 +6066,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_object: /* 0x11 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6809,7 +6089,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_4: /* 0x12 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6833,7 +6112,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_16: /* 0x13 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6857,7 +6135,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const: /* 0x14 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6881,7 +6158,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_high16: /* 0x15 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6905,7 +6181,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_16: /* 0x16 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6929,7 +6204,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_32: /* 0x17 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6953,7 +6227,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide: /* 0x18 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6977,7 +6250,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_high16: /* 0x19 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7001,7 +6273,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string: /* 0x1a */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7025,7 +6296,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string_jumbo: /* 0x1b */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7049,7 +6319,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_class: /* 0x1c */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7073,7 +6342,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_enter: /* 0x1d */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7097,7 +6365,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_exit: /* 0x1e */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7121,7 +6388,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_check_cast: /* 0x1f */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7145,7 +6411,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_instance_of: /* 0x20 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7169,7 +6434,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_array_length: /* 0x21 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7193,7 +6457,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_instance: /* 0x22 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7217,7 +6480,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_array: /* 0x23 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7241,7 +6503,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array: /* 0x24 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7265,7 +6526,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array_range: /* 0x25 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7289,7 +6549,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_fill_array_data: /* 0x26 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7313,7 +6572,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_throw: /* 0x27 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7337,7 +6595,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto: /* 0x28 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7361,7 +6618,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_16: /* 0x29 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7385,7 +6641,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_32: /* 0x2a */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7409,7 +6664,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_packed_switch: /* 0x2b */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7433,7 +6687,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sparse_switch: /* 0x2c */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7457,7 +6710,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_float: /* 0x2d */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7481,7 +6733,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_float: /* 0x2e */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7505,7 +6756,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_double: /* 0x2f */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7529,7 +6779,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_double: /* 0x30 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7553,7 +6802,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmp_long: /* 0x31 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7577,7 +6825,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eq: /* 0x32 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7601,7 +6848,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ne: /* 0x33 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7625,7 +6871,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lt: /* 0x34 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7649,7 +6894,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ge: /* 0x35 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7673,7 +6917,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gt: /* 0x36 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7697,7 +6940,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_le: /* 0x37 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7721,7 +6963,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eqz: /* 0x38 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7745,7 +6986,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_nez: /* 0x39 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7769,7 +7009,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ltz: /* 0x3a */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7793,7 +7032,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gez: /* 0x3b */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7817,7 +7055,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gtz: /* 0x3c */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7841,7 +7078,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lez: /* 0x3d */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7865,7 +7101,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3e: /* 0x3e */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7889,7 +7124,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3f: /* 0x3f */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7913,7 +7147,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_40: /* 0x40 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7937,7 +7170,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_41: /* 0x41 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7961,7 +7193,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_42: /* 0x42 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7985,7 +7216,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_43: /* 0x43 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8009,7 +7239,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget: /* 0x44 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8033,7 +7262,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_wide: /* 0x45 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8057,7 +7285,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_object: /* 0x46 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8081,7 +7308,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_boolean: /* 0x47 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8105,7 +7331,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_byte: /* 0x48 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8129,7 +7354,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_char: /* 0x49 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8153,7 +7377,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_short: /* 0x4a */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8177,7 +7400,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput: /* 0x4b */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8201,7 +7423,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_wide: /* 0x4c */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8225,7 +7446,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_object: /* 0x4d */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8249,7 +7469,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_boolean: /* 0x4e */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8273,7 +7492,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_byte: /* 0x4f */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8297,7 +7515,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_char: /* 0x50 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8321,7 +7538,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_short: /* 0x51 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8345,7 +7561,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget: /* 0x52 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8369,7 +7584,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide: /* 0x53 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8393,7 +7607,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object: /* 0x54 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8417,7 +7630,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean: /* 0x55 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8441,7 +7653,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte: /* 0x56 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8465,7 +7676,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char: /* 0x57 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8489,7 +7699,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short: /* 0x58 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8513,7 +7722,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput: /* 0x59 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8537,7 +7745,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide: /* 0x5a */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8561,7 +7768,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object: /* 0x5b */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8585,7 +7791,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean: /* 0x5c */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8609,7 +7814,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte: /* 0x5d */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8633,7 +7837,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char: /* 0x5e */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8657,7 +7860,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short: /* 0x5f */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8681,7 +7883,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget: /* 0x60 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8705,7 +7906,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_wide: /* 0x61 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8729,7 +7929,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_object: /* 0x62 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8753,7 +7952,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_boolean: /* 0x63 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8777,7 +7975,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_byte: /* 0x64 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8801,7 +7998,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_char: /* 0x65 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8825,7 +8021,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_short: /* 0x66 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8849,7 +8044,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput: /* 0x67 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8873,7 +8067,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_wide: /* 0x68 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8897,7 +8090,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_object: /* 0x69 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8921,7 +8113,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_boolean: /* 0x6a */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8945,7 +8136,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_byte: /* 0x6b */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8969,7 +8159,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_char: /* 0x6c */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8993,7 +8182,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_short: /* 0x6d */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9017,7 +8205,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual: /* 0x6e */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9041,7 +8228,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super: /* 0x6f */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9065,7 +8251,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct: /* 0x70 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9089,7 +8274,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static: /* 0x71 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9113,7 +8297,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface: /* 0x72 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9137,7 +8320,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void_no_barrier: /* 0x73 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9161,7 +8343,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range: /* 0x74 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9185,7 +8366,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super_range: /* 0x75 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9209,7 +8389,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct_range: /* 0x76 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9233,7 +8412,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static_range: /* 0x77 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9257,7 +8435,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface_range: /* 0x78 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9281,7 +8458,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_79: /* 0x79 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9305,7 +8481,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_7a: /* 0x7a */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9329,7 +8504,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_int: /* 0x7b */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9353,7 +8527,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_int: /* 0x7c */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9377,7 +8550,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_long: /* 0x7d */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9401,7 +8573,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_long: /* 0x7e */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9425,7 +8596,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_float: /* 0x7f */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9449,7 +8619,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_double: /* 0x80 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9473,7 +8642,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_long: /* 0x81 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9497,7 +8665,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_float: /* 0x82 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9521,7 +8688,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_double: /* 0x83 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9545,7 +8711,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_int: /* 0x84 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9569,7 +8734,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_float: /* 0x85 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9593,7 +8757,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_double: /* 0x86 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9617,7 +8780,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_int: /* 0x87 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9641,7 +8803,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_long: /* 0x88 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9665,7 +8826,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_double: /* 0x89 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9689,7 +8849,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_int: /* 0x8a */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9713,7 +8872,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_long: /* 0x8b */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9737,7 +8895,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_float: /* 0x8c */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9761,7 +8918,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_byte: /* 0x8d */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9785,7 +8941,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_char: /* 0x8e */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9809,7 +8964,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_short: /* 0x8f */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9833,7 +8987,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int: /* 0x90 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9857,7 +9010,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int: /* 0x91 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9881,7 +9033,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int: /* 0x92 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9905,7 +9056,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int: /* 0x93 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9929,7 +9079,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int: /* 0x94 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9953,7 +9102,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int: /* 0x95 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9977,7 +9125,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int: /* 0x96 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10001,7 +9148,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int: /* 0x97 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10025,7 +9171,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int: /* 0x98 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10049,7 +9194,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int: /* 0x99 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10073,7 +9217,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int: /* 0x9a */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10097,7 +9240,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long: /* 0x9b */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10121,7 +9263,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long: /* 0x9c */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10145,7 +9286,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long: /* 0x9d */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10169,7 +9309,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long: /* 0x9e */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10193,7 +9332,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long: /* 0x9f */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10217,7 +9355,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long: /* 0xa0 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10241,7 +9378,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long: /* 0xa1 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10265,7 +9401,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long: /* 0xa2 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10289,7 +9424,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long: /* 0xa3 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10313,7 +9447,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long: /* 0xa4 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10337,7 +9470,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long: /* 0xa5 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10361,7 +9493,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float: /* 0xa6 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10385,7 +9516,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float: /* 0xa7 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10409,7 +9539,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float: /* 0xa8 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10433,7 +9562,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float: /* 0xa9 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10457,7 +9585,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float: /* 0xaa */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10481,7 +9608,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double: /* 0xab */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10505,7 +9631,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double: /* 0xac */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10529,7 +9654,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double: /* 0xad */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10553,7 +9677,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double: /* 0xae */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10577,7 +9700,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double: /* 0xaf */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10601,7 +9723,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_2addr: /* 0xb0 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10625,7 +9746,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int_2addr: /* 0xb1 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10649,7 +9769,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_2addr: /* 0xb2 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10673,7 +9792,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_2addr: /* 0xb3 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10697,7 +9815,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_2addr: /* 0xb4 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10721,7 +9838,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_2addr: /* 0xb5 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10745,7 +9861,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_2addr: /* 0xb6 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10769,7 +9884,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_2addr: /* 0xb7 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10793,7 +9907,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_2addr: /* 0xb8 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10817,7 +9930,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_2addr: /* 0xb9 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10841,7 +9953,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_2addr: /* 0xba */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10865,7 +9976,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long_2addr: /* 0xbb */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10889,7 +9999,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long_2addr: /* 0xbc */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10913,7 +10022,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long_2addr: /* 0xbd */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10937,7 +10045,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long_2addr: /* 0xbe */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10961,7 +10068,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long_2addr: /* 0xbf */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10985,7 +10091,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long_2addr: /* 0xc0 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11009,7 +10114,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long_2addr: /* 0xc1 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11033,7 +10137,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long_2addr: /* 0xc2 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11057,7 +10160,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long_2addr: /* 0xc3 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11081,7 +10183,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long_2addr: /* 0xc4 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11105,7 +10206,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long_2addr: /* 0xc5 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11129,7 +10229,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float_2addr: /* 0xc6 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11153,7 +10252,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float_2addr: /* 0xc7 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11177,7 +10275,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float_2addr: /* 0xc8 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11201,7 +10298,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float_2addr: /* 0xc9 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11225,7 +10321,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float_2addr: /* 0xca */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11249,7 +10344,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double_2addr: /* 0xcb */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11273,7 +10367,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double_2addr: /* 0xcc */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11297,7 +10390,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double_2addr: /* 0xcd */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11321,7 +10413,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double_2addr: /* 0xce */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11345,7 +10436,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double_2addr: /* 0xcf */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11369,7 +10459,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit16: /* 0xd0 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11393,7 +10482,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int: /* 0xd1 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11417,7 +10505,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit16: /* 0xd2 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11441,7 +10528,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit16: /* 0xd3 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11465,7 +10551,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit16: /* 0xd4 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11489,7 +10574,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit16: /* 0xd5 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11513,7 +10597,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit16: /* 0xd6 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11537,7 +10620,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit16: /* 0xd7 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11561,7 +10643,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit8: /* 0xd8 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11585,7 +10666,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int_lit8: /* 0xd9 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11609,7 +10689,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit8: /* 0xda */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11633,7 +10712,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit8: /* 0xdb */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11657,7 +10735,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit8: /* 0xdc */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11681,7 +10758,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit8: /* 0xdd */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11705,7 +10781,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit8: /* 0xde */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11729,7 +10804,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit8: /* 0xdf */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11753,7 +10827,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_lit8: /* 0xe0 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11777,7 +10850,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_lit8: /* 0xe1 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11801,7 +10873,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_lit8: /* 0xe2 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11825,7 +10896,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_quick: /* 0xe3 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11849,7 +10919,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide_quick: /* 0xe4 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11873,7 +10942,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object_quick: /* 0xe5 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11897,7 +10965,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_quick: /* 0xe6 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11921,7 +10988,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide_quick: /* 0xe7 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11945,7 +11011,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object_quick: /* 0xe8 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11969,7 +11034,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11993,7 +11057,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12017,7 +11080,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean_quick: /* 0xeb */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12041,7 +11103,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte_quick: /* 0xec */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12065,7 +11126,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char_quick: /* 0xed */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12089,7 +11149,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short_quick: /* 0xee */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12113,7 +11172,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean_quick: /* 0xef */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12137,7 +11195,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte_quick: /* 0xf0 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12161,7 +11218,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char_quick: /* 0xf1 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12185,7 +11241,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short_quick: /* 0xf2 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12209,7 +11264,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f3: /* 0xf3 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12233,7 +11287,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f4: /* 0xf4 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12257,7 +11310,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f5: /* 0xf5 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12281,7 +11333,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f6: /* 0xf6 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12305,7 +11356,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f7: /* 0xf7 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12329,7 +11379,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f8: /* 0xf8 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12353,7 +11402,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f9: /* 0xf9 */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12377,7 +11425,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic: /* 0xfa */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12401,7 +11448,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12425,7 +11471,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom: /* 0xfc */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12449,7 +11494,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom_range: /* 0xfd */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12473,7 +11517,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_handle: /* 0xfe */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12497,7 +11540,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_type: /* 0xff */
-/* File: x86/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -12519,14 +11561,11 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
     jmp     .L_op_nop+(255*128)
 
     .balign 128
-/* File: x86/instruction_end_alt.S */
 
     OBJECT_TYPE(artMterpAsmAltInstructionEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd)
     .global SYMBOL(artMterpAsmAltInstructionEnd)
 SYMBOL(artMterpAsmAltInstructionEnd):
-
-/* File: x86/footer.S */
 /*
  * ===========================================================================
  *  Common subroutines and data
@@ -12852,4 +11891,3 @@ MRestoreFrame:
     ret
     .cfi_endproc
     SIZE(ExecuteMterpImpl,ExecuteMterpImpl)
-
diff --git a/runtime/interpreter/mterp/out/mterp_x86_64.S b/runtime/interpreter/mterp/out/mterp_x86_64.S
index 6d8bb4c7c45e39b713ffadb5cb4c42f8c67bddb0..1c45059e078dbc8e3a4108b7f4adba52d03a383c 100644
--- a/runtime/interpreter/mterp/out/mterp_x86_64.S
+++ b/runtime/interpreter/mterp/out/mterp_x86_64.S
@@ -1,10 +1,4 @@
-/*
- * This file was generated automatically by gen-mterp.py for 'x86_64'.
- *
- * --> DO NOT EDIT <--
- */
-
-/* File: x86_64/header.S */
+/* DO NOT EDIT: This file was generated by gen-mterp.py. */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -307,8 +301,6 @@ unspecified registers or condition codes.
     movl    MACRO_LITERAL(0),  (rREFS,\_vreg,4)
     movl    MACRO_LITERAL(0), 4(rREFS,\_vreg,4)
 .endm
-
-/* File: x86_64/entry.S */
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
@@ -389,24 +381,19 @@ SYMBOL(ExecuteMterpImpl):
     GOTO_NEXT
     /* NOTE: no fallthrough */
 
-/* File: x86_64/instruction_start.S */
-
     OBJECT_TYPE(artMterpAsmInstructionStart)
     ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart)
     .global SYMBOL(artMterpAsmInstructionStart)
 SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .text
-
 /* ------------------------------ */
     .balign 128
 .L_op_nop: /* 0x00 */
-/* File: x86_64/op_nop.S */
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
 /* ------------------------------ */
     .balign 128
 .L_op_move: /* 0x01 */
-/* File: x86_64/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     movl    rINST, %eax                     # eax <- BA
@@ -423,7 +410,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_from16: /* 0x02 */
-/* File: x86_64/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     movzwq  2(rPC), %rax                    # eax <- BBBB
@@ -438,7 +424,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_16: /* 0x03 */
-/* File: x86_64/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     movzwq  4(rPC), %rcx                    # ecx <- BBBB
@@ -454,7 +439,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide: /* 0x04 */
-/* File: x86_64/op_move_wide.S */
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movl    rINST, %ecx                     # ecx <- BA
@@ -467,7 +451,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_from16: /* 0x05 */
-/* File: x86_64/op_move_wide_from16.S */
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movzwl  2(rPC), %ecx                    # ecx <- BBBB
@@ -478,7 +461,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_wide_16: /* 0x06 */
-/* File: x86_64/op_move_wide_16.S */
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movzwq  4(rPC), %rcx                    # ecx<- BBBB
@@ -490,8 +472,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_object: /* 0x07 */
-/* File: x86_64/op_move_object.S */
-/* File: x86_64/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     movl    rINST, %eax                     # eax <- BA
@@ -505,12 +485,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_from16: /* 0x08 */
-/* File: x86_64/op_move_object_from16.S */
-/* File: x86_64/op_move_from16.S */
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     movzwq  2(rPC), %rax                    # eax <- BBBB
@@ -522,12 +499,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_object_16: /* 0x09 */
-/* File: x86_64/op_move_object_16.S */
-/* File: x86_64/op_move_16.S */
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     movzwq  4(rPC), %rcx                    # ecx <- BBBB
@@ -540,11 +514,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 3
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_result: /* 0x0a */
-/* File: x86_64/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     movq    OFF_FP_RESULT_REGISTER(rFP), %rax    # get pointer to result JType.
@@ -559,7 +531,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_wide: /* 0x0b */
-/* File: x86_64/op_move_result_wide.S */
     /* move-result-wide vAA */
     movq    OFF_FP_RESULT_REGISTER(rFP), %rax    # get pointer to result JType.
     movq    (%rax), %rdx                         # Get wide
@@ -569,8 +540,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_move_result_object: /* 0x0c */
-/* File: x86_64/op_move_result_object.S */
-/* File: x86_64/op_move_result.S */
     /* for: move-result, move-result-object */
     /* op vAA */
     movq    OFF_FP_RESULT_REGISTER(rFP), %rax    # get pointer to result JType.
@@ -582,11 +551,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_move_exception: /* 0x0d */
-/* File: x86_64/op_move_exception.S */
     /* move-exception vAA */
     movq    rSELF, %rcx
     movl    THREAD_EXCEPTION_OFFSET(%rcx), %eax
@@ -597,7 +564,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_void: /* 0x0e */
-/* File: x86_64/op_return_void.S */
     .extern MterpThreadFenceForConstructor
     call    SYMBOL(MterpThreadFenceForConstructor)
     movq    rSELF, OUT_ARG0
@@ -611,7 +577,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return: /* 0x0f */
-/* File: x86_64/op_return.S */
 /*
  * Return a 32-bit value.
  *
@@ -631,7 +596,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_wide: /* 0x10 */
-/* File: x86_64/op_return_wide.S */
 /*
  * Return a 64-bit value.
  */
@@ -649,8 +613,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_object: /* 0x11 */
-/* File: x86_64/op_return_object.S */
-/* File: x86_64/op_return.S */
 /*
  * Return a 32-bit value.
  *
@@ -667,11 +629,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     GET_VREG %eax, rINSTq                   # eax <- vAA
     jmp     MterpReturn
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_4: /* 0x12 */
-/* File: x86_64/op_const_4.S */
     /* const/4 vA, #+B */
     movsbl  rINSTbl, %eax                   # eax <-ssssssBx
     movl    $0xf, rINST
@@ -683,7 +643,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_16: /* 0x13 */
-/* File: x86_64/op_const_16.S */
     /* const/16 vAA, #+BBBB */
     movswl  2(rPC), %ecx                    # ecx <- ssssBBBB
     SET_VREG %ecx, rINSTq                   # vAA <- ssssBBBB
@@ -692,7 +651,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const: /* 0x14 */
-/* File: x86_64/op_const.S */
     /* const vAA, #+BBBBbbbb */
     movl    2(rPC), %eax                    # grab all 32 bits at once
     SET_VREG %eax, rINSTq                   # vAA<- eax
@@ -701,7 +659,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_high16: /* 0x15 */
-/* File: x86_64/op_const_high16.S */
     /* const/high16 vAA, #+BBBB0000 */
     movzwl  2(rPC), %eax                    # eax <- 0000BBBB
     sall    $16, %eax                      # eax <- BBBB0000
@@ -711,7 +668,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_16: /* 0x16 */
-/* File: x86_64/op_const_wide_16.S */
     /* const-wide/16 vAA, #+BBBB */
     movswq  2(rPC), %rax                    # rax <- ssssBBBB
     SET_WIDE_VREG %rax, rINSTq              # store
@@ -720,7 +676,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_32: /* 0x17 */
-/* File: x86_64/op_const_wide_32.S */
     /* const-wide/32 vAA, #+BBBBbbbb */
     movslq   2(rPC), %rax                   # eax <- ssssssssBBBBbbbb
     SET_WIDE_VREG %rax, rINSTq              # store
@@ -729,7 +684,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide: /* 0x18 */
-/* File: x86_64/op_const_wide.S */
     /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
     movq    2(rPC), %rax                    # rax <- HHHHhhhhBBBBbbbb
     SET_WIDE_VREG %rax, rINSTq
@@ -738,7 +692,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_wide_high16: /* 0x19 */
-/* File: x86_64/op_const_wide_high16.S */
     /* const-wide/high16 vAA, #+BBBB000000000000 */
     movzwq  2(rPC), %rax                    # eax <- 0000BBBB
     salq    $48, %rax                      # eax <- BBBB0000
@@ -748,8 +701,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_string: /* 0x1a */
-/* File: x86_64/op_const_string.S */
-/* File: x86_64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -765,11 +716,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jnz     MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_string_jumbo: /* 0x1b */
-/* File: x86_64/op_const_string_jumbo.S */
     /* const/string vAA, String@BBBBBBBB */
     EXPORT_PC
     movl    2(rPC), OUT_32_ARG0             # OUT_32_ARG0 <- BBBB
@@ -784,8 +733,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_const_class: /* 0x1c */
-/* File: x86_64/op_const_class.S */
-/* File: x86_64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -801,11 +748,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jnz     MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_enter: /* 0x1d */
-/* File: x86_64/op_monitor_enter.S */
 /*
  * Synchronize on an object.
  */
@@ -821,7 +766,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_monitor_exit: /* 0x1e */
-/* File: x86_64/op_monitor_exit.S */
 /*
  * Unlock an object.
  *
@@ -841,7 +785,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_check_cast: /* 0x1f */
-/* File: x86_64/op_check_cast.S */
 /*
  * Check to see if a cast from one class to another is allowed.
  */
@@ -859,7 +802,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_instance_of: /* 0x20 */
-/* File: x86_64/op_instance_of.S */
 /*
  * Check to see if an object reference is an instance of a class.
  *
@@ -886,7 +828,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_array_length: /* 0x21 */
-/* File: x86_64/op_array_length.S */
 /*
  * Return the length of an array.
  */
@@ -903,7 +844,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_instance: /* 0x22 */
-/* File: x86_64/op_new_instance.S */
 /*
  * Create a new instance of a class.
  */
@@ -921,7 +861,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_new_array: /* 0x23 */
-/* File: x86_64/op_new_array.S */
 /*
  * Allocate an array of objects, specified with the array class
  * and a count.
@@ -944,7 +883,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array: /* 0x24 */
-/* File: x86_64/op_filled_new_array.S */
 /*
  * Create a new array with elements filled from registers.
  *
@@ -965,8 +903,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_filled_new_array_range: /* 0x25 */
-/* File: x86_64/op_filled_new_array_range.S */
-/* File: x86_64/op_filled_new_array.S */
 /*
  * Create a new array with elements filled from registers.
  *
@@ -984,11 +920,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 3
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_fill_array_data: /* 0x26 */
-/* File: x86_64/op_fill_array_data.S */
     /* fill-array-data vAA, +BBBBBBBB */
     EXPORT_PC
     movslq  2(rPC), %rcx                    # rcx <- ssssssssBBBBbbbb
@@ -1002,7 +936,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_throw: /* 0x27 */
-/* File: x86_64/op_throw.S */
 /*
  * Throw an exception object in the current thread.
  */
@@ -1018,7 +951,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto: /* 0x28 */
-/* File: x86_64/op_goto.S */
 /*
  * Unconditional branch, 8-bit offset.
  *
@@ -1033,7 +965,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_16: /* 0x29 */
-/* File: x86_64/op_goto_16.S */
 /*
  * Unconditional branch, 16-bit offset.
  *
@@ -1048,7 +979,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_goto_32: /* 0x2a */
-/* File: x86_64/op_goto_32.S */
 /*
  * Unconditional branch, 32-bit offset.
  *
@@ -1066,7 +996,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_packed_switch: /* 0x2b */
-/* File: x86_64/op_packed_switch.S */
 /*
  * Handle a packed-switch or sparse-switch instruction.  In both cases
  * we decode it and hand it off to a helper function.
@@ -1088,8 +1017,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_sparse_switch: /* 0x2c */
-/* File: x86_64/op_sparse_switch.S */
-/* File: x86_64/op_packed_switch.S */
 /*
  * Handle a packed-switch or sparse-switch instruction.  In both cases
  * we decode it and hand it off to a helper function.
@@ -1108,12 +1035,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movslq  %eax, rINSTq
     jmp     MterpCommonTakenBranch
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_float: /* 0x2d */
-/* File: x86_64/op_cmpl_float.S */
-/* File: x86_64/fpcmp.S */
 /*
  * Compare two floating-point values.  Puts 0, 1, or -1 into the
  * destination register based on the results of the comparison.
@@ -1149,12 +1073,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_float: /* 0x2e */
-/* File: x86_64/op_cmpg_float.S */
-/* File: x86_64/fpcmp.S */
 /*
  * Compare two floating-point values.  Puts 0, 1, or -1 into the
  * destination register based on the results of the comparison.
@@ -1190,12 +1111,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpl_double: /* 0x2f */
-/* File: x86_64/op_cmpl_double.S */
-/* File: x86_64/fpcmp.S */
 /*
  * Compare two floating-point values.  Puts 0, 1, or -1 into the
  * destination register based on the results of the comparison.
@@ -1231,12 +1149,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmpg_double: /* 0x30 */
-/* File: x86_64/op_cmpg_double.S */
-/* File: x86_64/fpcmp.S */
 /*
  * Compare two floating-point values.  Puts 0, 1, or -1 into the
  * destination register based on the results of the comparison.
@@ -1272,11 +1187,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_cmp_long: /* 0x31 */
-/* File: x86_64/op_cmp_long.S */
 /*
  * Compare two 64-bit values.  Puts 0, 1, or -1 into the destination
  * register based on the results of the comparison.
@@ -1298,8 +1211,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_if_eq: /* 0x32 */
-/* File: x86_64/op_if_eq.S */
-/* File: x86_64/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1322,12 +1233,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ne: /* 0x33 */
-/* File: x86_64/op_if_ne.S */
-/* File: x86_64/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1350,12 +1258,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lt: /* 0x34 */
-/* File: x86_64/op_if_lt.S */
-/* File: x86_64/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1378,12 +1283,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ge: /* 0x35 */
-/* File: x86_64/op_if_ge.S */
-/* File: x86_64/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1406,12 +1308,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gt: /* 0x36 */
-/* File: x86_64/op_if_gt.S */
-/* File: x86_64/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1434,12 +1333,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_le: /* 0x37 */
-/* File: x86_64/op_if_le.S */
-/* File: x86_64/bincmp.S */
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1462,12 +1358,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_eqz: /* 0x38 */
-/* File: x86_64/op_if_eqz.S */
-/* File: x86_64/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1486,12 +1379,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_nez: /* 0x39 */
-/* File: x86_64/op_if_nez.S */
-/* File: x86_64/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1510,12 +1400,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_ltz: /* 0x3a */
-/* File: x86_64/op_if_ltz.S */
-/* File: x86_64/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1534,12 +1421,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gez: /* 0x3b */
-/* File: x86_64/op_if_gez.S */
-/* File: x86_64/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1558,12 +1442,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_gtz: /* 0x3c */
-/* File: x86_64/op_if_gtz.S */
-/* File: x86_64/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1582,12 +1463,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_if_lez: /* 0x3d */
-/* File: x86_64/op_if_lez.S */
-/* File: x86_64/zcmp.S */
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
@@ -1606,77 +1484,57 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     je      .L_check_not_taken_osr
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3e: /* 0x3e */
-/* File: x86_64/op_unused_3e.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_3f: /* 0x3f */
-/* File: x86_64/op_unused_3f.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_40: /* 0x40 */
-/* File: x86_64/op_unused_40.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_41: /* 0x41 */
-/* File: x86_64/op_unused_41.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_42: /* 0x42 */
-/* File: x86_64/op_unused_42.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_43: /* 0x43 */
-/* File: x86_64/op_unused_43.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget: /* 0x44 */
-/* File: x86_64/op_aget.S */
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
@@ -1704,8 +1562,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_wide: /* 0x45 */
-/* File: x86_64/op_aget_wide.S */
-/* File: x86_64/op_aget.S */
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
@@ -1730,11 +1586,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_object: /* 0x46 */
-/* File: x86_64/op_aget_object.S */
 /*
  * Array object get.  vAA <- vBB[vCC].
  *
@@ -1756,8 +1610,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aget_boolean: /* 0x47 */
-/* File: x86_64/op_aget_boolean.S */
-/* File: x86_64/op_aget.S */
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
@@ -1782,12 +1634,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_byte: /* 0x48 */
-/* File: x86_64/op_aget_byte.S */
-/* File: x86_64/op_aget.S */
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
@@ -1812,12 +1661,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_char: /* 0x49 */
-/* File: x86_64/op_aget_char.S */
-/* File: x86_64/op_aget.S */
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
@@ -1842,12 +1688,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aget_short: /* 0x4a */
-/* File: x86_64/op_aget_short.S */
-/* File: x86_64/op_aget.S */
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
@@ -1872,11 +1715,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput: /* 0x4b */
-/* File: x86_64/op_aput.S */
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
@@ -1903,8 +1744,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_wide: /* 0x4c */
-/* File: x86_64/op_aput_wide.S */
-/* File: x86_64/op_aput.S */
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
@@ -1928,11 +1767,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movq    rINSTq, MIRROR_WIDE_ARRAY_DATA_OFFSET(%rax,%rcx,8)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_object: /* 0x4d */
-/* File: x86_64/op_aput_object.S */
 /*
  * Store an object into an array.  vBB[vCC] <- vAA.
  */
@@ -1950,8 +1787,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_aput_boolean: /* 0x4e */
-/* File: x86_64/op_aput_boolean.S */
-/* File: x86_64/op_aput.S */
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
@@ -1975,12 +1810,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movb    rINSTbl, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%rax,%rcx,1)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_byte: /* 0x4f */
-/* File: x86_64/op_aput_byte.S */
-/* File: x86_64/op_aput.S */
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
@@ -2004,12 +1836,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movb    rINSTbl, MIRROR_BYTE_ARRAY_DATA_OFFSET(%rax,%rcx,1)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_char: /* 0x50 */
-/* File: x86_64/op_aput_char.S */
-/* File: x86_64/op_aput.S */
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
@@ -2033,12 +1862,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movw    rINSTw, MIRROR_CHAR_ARRAY_DATA_OFFSET(%rax,%rcx,2)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_aput_short: /* 0x51 */
-/* File: x86_64/op_aput_short.S */
-/* File: x86_64/op_aput.S */
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
@@ -2062,12 +1888,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     movw    rINSTw, MIRROR_SHORT_ARRAY_DATA_OFFSET(%rax,%rcx,2)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget: /* 0x52 */
-/* File: x86_64/op_iget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2082,13 +1905,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide: /* 0x53 */
-/* File: x86_64/op_iget_wide.S */
-/* File: x86_64/op_iget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2103,14 +1922,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object: /* 0x54 */
-/* File: x86_64/op_iget_object.S */
-/* File: x86_64/op_iget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2125,14 +1939,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean: /* 0x55 */
-/* File: x86_64/op_iget_boolean.S */
-/* File: x86_64/op_iget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2147,14 +1956,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte: /* 0x56 */
-/* File: x86_64/op_iget_byte.S */
-/* File: x86_64/op_iget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2169,14 +1973,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char: /* 0x57 */
-/* File: x86_64/op_iget_char.S */
-/* File: x86_64/op_iget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2191,14 +1990,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short: /* 0x58 */
-/* File: x86_64/op_iget_short.S */
-/* File: x86_64/op_iget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2213,13 +2007,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput: /* 0x59 */
-/* File: x86_64/op_iput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2234,13 +2024,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide: /* 0x5a */
-/* File: x86_64/op_iput_wide.S */
-/* File: x86_64/op_iput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2255,14 +2041,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object: /* 0x5b */
-/* File: x86_64/op_iput_object.S */
-/* File: x86_64/op_iput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2277,14 +2058,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean: /* 0x5c */
-/* File: x86_64/op_iput_boolean.S */
-/* File: x86_64/op_iput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2299,14 +2075,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte: /* 0x5d */
-/* File: x86_64/op_iput_byte.S */
-/* File: x86_64/op_iput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2321,14 +2092,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char: /* 0x5e */
-/* File: x86_64/op_iput_char.S */
-/* File: x86_64/op_iput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2343,14 +2109,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short: /* 0x5f */
-/* File: x86_64/op_iput_short.S */
-/* File: x86_64/op_iput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2365,13 +2126,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget: /* 0x60 */
-/* File: x86_64/op_sget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2386,13 +2143,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_wide: /* 0x61 */
-/* File: x86_64/op_sget_wide.S */
-/* File: x86_64/op_sget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2407,14 +2160,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_object: /* 0x62 */
-/* File: x86_64/op_sget_object.S */
-/* File: x86_64/op_sget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2429,14 +2177,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_boolean: /* 0x63 */
-/* File: x86_64/op_sget_boolean.S */
-/* File: x86_64/op_sget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2451,14 +2194,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_byte: /* 0x64 */
-/* File: x86_64/op_sget_byte.S */
-/* File: x86_64/op_sget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2473,14 +2211,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_char: /* 0x65 */
-/* File: x86_64/op_sget_char.S */
-/* File: x86_64/op_sget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2495,14 +2228,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sget_short: /* 0x66 */
-/* File: x86_64/op_sget_short.S */
-/* File: x86_64/op_sget.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2517,13 +2245,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput: /* 0x67 */
-/* File: x86_64/op_sput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2538,13 +2262,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_wide: /* 0x68 */
-/* File: x86_64/op_sput_wide.S */
-/* File: x86_64/op_sput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2559,14 +2279,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_object: /* 0x69 */
-/* File: x86_64/op_sput_object.S */
-/* File: x86_64/op_sput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2581,14 +2296,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_boolean: /* 0x6a */
-/* File: x86_64/op_sput_boolean.S */
-/* File: x86_64/op_sput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2603,14 +2313,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_byte: /* 0x6b */
-/* File: x86_64/op_sput_byte.S */
-/* File: x86_64/op_sput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2625,14 +2330,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_char: /* 0x6c */
-/* File: x86_64/op_sput_char.S */
-/* File: x86_64/op_sput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2647,14 +2347,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_sput_short: /* 0x6d */
-/* File: x86_64/op_sput_short.S */
-/* File: x86_64/op_sput.S */
-/* File: x86_64/field.S */
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
@@ -2669,13 +2364,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jz      MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual: /* 0x6e */
-/* File: x86_64/op_invoke_virtual.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2697,7 +2388,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jnz     MterpFallback
     FETCH_INST
     GOTO_NEXT
-
 /*
  * Handle a virtual method call.
  *
@@ -2709,8 +2399,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super: /* 0x6f */
-/* File: x86_64/op_invoke_super.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2732,7 +2420,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jnz     MterpFallback
     FETCH_INST
     GOTO_NEXT
-
 /*
  * Handle a "super" method call.
  *
@@ -2744,8 +2431,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct: /* 0x70 */
-/* File: x86_64/op_invoke_direct.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2768,12 +2453,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static: /* 0x71 */
-/* File: x86_64/op_invoke_static.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2796,13 +2478,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface: /* 0x72 */
-/* File: x86_64/op_invoke_interface.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2824,7 +2502,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     jnz     MterpFallback
     FETCH_INST
     GOTO_NEXT
-
 /*
  * Handle an interface method call.
  *
@@ -2836,7 +2513,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_return_void_no_barrier: /* 0x73 */
-/* File: x86_64/op_return_void_no_barrier.S */
     movq    rSELF, OUT_ARG0
     testl   $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0)
     jz      1f
@@ -2848,8 +2524,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range: /* 0x74 */
-/* File: x86_64/op_invoke_virtual_range.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2872,12 +2546,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_super_range: /* 0x75 */
-/* File: x86_64/op_invoke_super_range.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2900,12 +2571,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_direct_range: /* 0x76 */
-/* File: x86_64/op_invoke_direct_range.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2928,12 +2596,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_static_range: /* 0x77 */
-/* File: x86_64/op_invoke_static_range.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2956,12 +2621,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_interface_range: /* 0x78 */
-/* File: x86_64/op_invoke_interface_range.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -2984,34 +2646,25 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_79: /* 0x79 */
-/* File: x86_64/op_unused_79.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_7a: /* 0x7a */
-/* File: x86_64/op_unused_7a.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_int: /* 0x7b */
-/* File: x86_64/op_neg_int.S */
-/* File: x86_64/unop.S */
 /*
  * Generic 32/64-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3034,12 +2687,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_int: /* 0x7c */
-/* File: x86_64/op_not_int.S */
-/* File: x86_64/unop.S */
 /*
  * Generic 32/64-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3062,12 +2712,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_long: /* 0x7d */
-/* File: x86_64/op_neg_long.S */
-/* File: x86_64/unop.S */
 /*
  * Generic 32/64-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3090,12 +2737,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_not_long: /* 0x7e */
-/* File: x86_64/op_not_long.S */
-/* File: x86_64/unop.S */
 /*
  * Generic 32/64-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3118,12 +2762,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_float: /* 0x7f */
-/* File: x86_64/op_neg_float.S */
-/* File: x86_64/unop.S */
 /*
  * Generic 32/64-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3146,12 +2787,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_neg_double: /* 0x80 */
-/* File: x86_64/op_neg_double.S */
-/* File: x86_64/unop.S */
 /*
  * Generic 32/64-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3174,11 +2812,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_long: /* 0x81 */
-/* File: x86_64/op_int_to_long.S */
     /* int to long vA, vB */
     movzbq  rINSTbl, %rax                   # rax <- +A
     sarl    $4, %eax                       # eax <- B
@@ -3187,12 +2823,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     SET_WIDE_VREG %rax, rINSTq              # v[A] <- %rax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_float: /* 0x82 */
-/* File: x86_64/op_int_to_float.S */
-/* File: x86_64/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3210,12 +2843,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_double: /* 0x83 */
-/* File: x86_64/op_int_to_double.S */
-/* File: x86_64/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3233,13 +2863,10 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_int: /* 0x84 */
-/* File: x86_64/op_long_to_int.S */
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-/* File: x86_64/op_move.S */
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     movl    rINST, %eax                     # eax <- BA
@@ -3253,12 +2880,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_float: /* 0x85 */
-/* File: x86_64/op_long_to_float.S */
-/* File: x86_64/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3276,12 +2900,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_long_to_double: /* 0x86 */
-/* File: x86_64/op_long_to_double.S */
-/* File: x86_64/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3299,12 +2920,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_int: /* 0x87 */
-/* File: x86_64/op_float_to_int.S */
-/* File: x86_64/cvtfp_int.S */
 /* On fp to int conversions, Java requires that
  * if the result > maxint, it should be clamped to maxint.  If it is less
  * than minint, it should be clamped to minint.  If it is a nan, the result
@@ -3332,12 +2950,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_long: /* 0x88 */
-/* File: x86_64/op_float_to_long.S */
-/* File: x86_64/cvtfp_int.S */
 /* On fp to int conversions, Java requires that
  * if the result > maxint, it should be clamped to maxint.  If it is less
  * than minint, it should be clamped to minint.  If it is a nan, the result
@@ -3365,12 +2980,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_float_to_double: /* 0x89 */
-/* File: x86_64/op_float_to_double.S */
-/* File: x86_64/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3388,12 +3000,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_int: /* 0x8a */
-/* File: x86_64/op_double_to_int.S */
-/* File: x86_64/cvtfp_int.S */
 /* On fp to int conversions, Java requires that
  * if the result > maxint, it should be clamped to maxint.  If it is less
  * than minint, it should be clamped to minint.  If it is a nan, the result
@@ -3421,12 +3030,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_long: /* 0x8b */
-/* File: x86_64/op_double_to_long.S */
-/* File: x86_64/cvtfp_int.S */
 /* On fp to int conversions, Java requires that
  * if the result > maxint, it should be clamped to maxint.  If it is less
  * than minint, it should be clamped to minint.  If it is a nan, the result
@@ -3454,12 +3060,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_double_to_float: /* 0x8c */
-/* File: x86_64/op_double_to_float.S */
-/* File: x86_64/fpcvt.S */
 /*
  * Generic 32-bit FP conversion operation.
  */
@@ -3477,12 +3080,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_byte: /* 0x8d */
-/* File: x86_64/op_int_to_byte.S */
-/* File: x86_64/unop.S */
 /*
  * Generic 32/64-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3505,12 +3105,9 @@ movsbl  %al, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_char: /* 0x8e */
-/* File: x86_64/op_int_to_char.S */
-/* File: x86_64/unop.S */
 /*
  * Generic 32/64-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3533,12 +3130,9 @@ movzwl  %ax,%eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_int_to_short: /* 0x8f */
-/* File: x86_64/op_int_to_short.S */
-/* File: x86_64/unop.S */
 /*
  * Generic 32/64-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
@@ -3561,12 +3155,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int: /* 0x90 */
-/* File: x86_64/op_add_int.S */
-/* File: x86_64/binop.S */
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
@@ -3584,12 +3175,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int: /* 0x91 */
-/* File: x86_64/op_sub_int.S */
-/* File: x86_64/binop.S */
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
@@ -3607,12 +3195,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int: /* 0x92 */
-/* File: x86_64/op_mul_int.S */
-/* File: x86_64/binop.S */
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
@@ -3630,12 +3215,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int: /* 0x93 */
-/* File: x86_64/op_div_int.S */
-/* File: x86_64/bindiv.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
@@ -3670,12 +3252,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int: /* 0x94 */
-/* File: x86_64/op_rem_int.S */
-/* File: x86_64/bindiv.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
@@ -3710,12 +3289,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int: /* 0x95 */
-/* File: x86_64/op_and_int.S */
-/* File: x86_64/binop.S */
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
@@ -3733,12 +3309,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int: /* 0x96 */
-/* File: x86_64/op_or_int.S */
-/* File: x86_64/binop.S */
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
@@ -3756,12 +3329,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int: /* 0x97 */
-/* File: x86_64/op_xor_int.S */
-/* File: x86_64/binop.S */
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
@@ -3779,12 +3349,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int: /* 0x98 */
-/* File: x86_64/op_shl_int.S */
-/* File: x86_64/binop1.S */
 /*
  * Generic 32-bit binary operation in which both operands loaded to
  * registers (op0 in eax, op1 in ecx).
@@ -3804,12 +3371,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int: /* 0x99 */
-/* File: x86_64/op_shr_int.S */
-/* File: x86_64/binop1.S */
 /*
  * Generic 32-bit binary operation in which both operands loaded to
  * registers (op0 in eax, op1 in ecx).
@@ -3829,12 +3393,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int: /* 0x9a */
-/* File: x86_64/op_ushr_int.S */
-/* File: x86_64/binop1.S */
 /*
  * Generic 32-bit binary operation in which both operands loaded to
  * registers (op0 in eax, op1 in ecx).
@@ -3854,12 +3415,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long: /* 0x9b */
-/* File: x86_64/op_add_long.S */
-/* File: x86_64/binopWide.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -3871,12 +3429,9 @@ movswl %ax, %eax
     SET_WIDE_VREG %rax, rINSTq              # v[AA] <- rax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long: /* 0x9c */
-/* File: x86_64/op_sub_long.S */
-/* File: x86_64/binopWide.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -3888,12 +3443,9 @@ movswl %ax, %eax
     SET_WIDE_VREG %rax, rINSTq              # v[AA] <- rax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long: /* 0x9d */
-/* File: x86_64/op_mul_long.S */
-/* File: x86_64/binopWide.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -3905,12 +3457,9 @@ movswl %ax, %eax
     SET_WIDE_VREG %rax, rINSTq              # v[AA] <- rax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_long: /* 0x9e */
-/* File: x86_64/op_div_long.S */
-/* File: x86_64/bindiv.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
@@ -3945,12 +3494,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long: /* 0x9f */
-/* File: x86_64/op_rem_long.S */
-/* File: x86_64/bindiv.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
@@ -3985,12 +3531,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long: /* 0xa0 */
-/* File: x86_64/op_and_long.S */
-/* File: x86_64/binopWide.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4002,12 +3545,9 @@ movswl %ax, %eax
     SET_WIDE_VREG %rax, rINSTq              # v[AA] <- rax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long: /* 0xa1 */
-/* File: x86_64/op_or_long.S */
-/* File: x86_64/binopWide.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4019,12 +3559,9 @@ movswl %ax, %eax
     SET_WIDE_VREG %rax, rINSTq              # v[AA] <- rax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long: /* 0xa2 */
-/* File: x86_64/op_xor_long.S */
-/* File: x86_64/binopWide.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4036,12 +3573,9 @@ movswl %ax, %eax
     SET_WIDE_VREG %rax, rINSTq              # v[AA] <- rax
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long: /* 0xa3 */
-/* File: x86_64/op_shl_long.S */
-/* File: x86_64/binop1.S */
 /*
  * Generic 32-bit binary operation in which both operands loaded to
  * registers (op0 in eax, op1 in ecx).
@@ -4061,12 +3595,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long: /* 0xa4 */
-/* File: x86_64/op_shr_long.S */
-/* File: x86_64/binop1.S */
 /*
  * Generic 32-bit binary operation in which both operands loaded to
  * registers (op0 in eax, op1 in ecx).
@@ -4086,12 +3617,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long: /* 0xa5 */
-/* File: x86_64/op_ushr_long.S */
-/* File: x86_64/binop1.S */
 /*
  * Generic 32-bit binary operation in which both operands loaded to
  * registers (op0 in eax, op1 in ecx).
@@ -4111,12 +3639,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_float: /* 0xa6 */
-/* File: x86_64/op_add_float.S */
-/* File: x86_64/sseBinop.S */
     movzbq  2(rPC), %rcx                    # ecx <- BB
     movzbq  3(rPC), %rax                    # eax <- CC
     movss   VREG_ADDRESS(%rcx), %xmm0       # %xmm0 <- 1st src
@@ -4126,12 +3651,9 @@ movswl %ax, %eax
     movss   %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float: /* 0xa7 */
-/* File: x86_64/op_sub_float.S */
-/* File: x86_64/sseBinop.S */
     movzbq  2(rPC), %rcx                    # ecx <- BB
     movzbq  3(rPC), %rax                    # eax <- CC
     movss   VREG_ADDRESS(%rcx), %xmm0       # %xmm0 <- 1st src
@@ -4141,12 +3663,9 @@ movswl %ax, %eax
     movss   %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float: /* 0xa8 */
-/* File: x86_64/op_mul_float.S */
-/* File: x86_64/sseBinop.S */
     movzbq  2(rPC), %rcx                    # ecx <- BB
     movzbq  3(rPC), %rax                    # eax <- CC
     movss   VREG_ADDRESS(%rcx), %xmm0       # %xmm0 <- 1st src
@@ -4156,12 +3675,9 @@ movswl %ax, %eax
     movss   %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float: /* 0xa9 */
-/* File: x86_64/op_div_float.S */
-/* File: x86_64/sseBinop.S */
     movzbq  2(rPC), %rcx                    # ecx <- BB
     movzbq  3(rPC), %rax                    # eax <- CC
     movss   VREG_ADDRESS(%rcx), %xmm0       # %xmm0 <- 1st src
@@ -4171,11 +3687,9 @@ movswl %ax, %eax
     movss   %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float: /* 0xaa */
-/* File: x86_64/op_rem_float.S */
     /* rem_float vAA, vBB, vCC */
     movzbq  3(rPC), %rcx                    # ecx <- BB
     movzbq  2(rPC), %rax                    # eax <- CC
@@ -4194,8 +3708,6 @@ movswl %ax, %eax
 /* ------------------------------ */
     .balign 128
 .L_op_add_double: /* 0xab */
-/* File: x86_64/op_add_double.S */
-/* File: x86_64/sseBinop.S */
     movzbq  2(rPC), %rcx                    # ecx <- BB
     movzbq  3(rPC), %rax                    # eax <- CC
     movsd   VREG_ADDRESS(%rcx), %xmm0       # %xmm0 <- 1st src
@@ -4205,12 +3717,9 @@ movswl %ax, %eax
     movsd   %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double: /* 0xac */
-/* File: x86_64/op_sub_double.S */
-/* File: x86_64/sseBinop.S */
     movzbq  2(rPC), %rcx                    # ecx <- BB
     movzbq  3(rPC), %rax                    # eax <- CC
     movsd   VREG_ADDRESS(%rcx), %xmm0       # %xmm0 <- 1st src
@@ -4220,12 +3729,9 @@ movswl %ax, %eax
     movsd   %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double: /* 0xad */
-/* File: x86_64/op_mul_double.S */
-/* File: x86_64/sseBinop.S */
     movzbq  2(rPC), %rcx                    # ecx <- BB
     movzbq  3(rPC), %rax                    # eax <- CC
     movsd   VREG_ADDRESS(%rcx), %xmm0       # %xmm0 <- 1st src
@@ -4235,12 +3741,9 @@ movswl %ax, %eax
     movsd   %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double: /* 0xae */
-/* File: x86_64/op_div_double.S */
-/* File: x86_64/sseBinop.S */
     movzbq  2(rPC), %rcx                    # ecx <- BB
     movzbq  3(rPC), %rax                    # eax <- CC
     movsd   VREG_ADDRESS(%rcx), %xmm0       # %xmm0 <- 1st src
@@ -4250,11 +3753,9 @@ movswl %ax, %eax
     movsd   %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double: /* 0xaf */
-/* File: x86_64/op_rem_double.S */
     /* rem_double vAA, vBB, vCC */
     movzbq  3(rPC), %rcx                    # ecx <- BB
     movzbq  2(rPC), %rax                    # eax <- CC
@@ -4273,8 +3774,6 @@ movswl %ax, %eax
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_2addr: /* 0xb0 */
-/* File: x86_64/op_add_int_2addr.S */
-/* File: x86_64/binop2addr.S */
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
@@ -4294,12 +3793,9 @@ movswl %ax, %eax
     CLEAR_REF %rcx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_int_2addr: /* 0xb1 */
-/* File: x86_64/op_sub_int_2addr.S */
-/* File: x86_64/binop2addr.S */
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
@@ -4319,11 +3815,9 @@ movswl %ax, %eax
     CLEAR_REF %rcx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_2addr: /* 0xb2 */
-/* File: x86_64/op_mul_int_2addr.S */
     /* mul vA, vB */
     movl    rINST, %ecx                     # rcx <- A+
     sarl    $4, rINST                      # rINST <- B
@@ -4336,8 +3830,6 @@ movswl %ax, %eax
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_2addr: /* 0xb3 */
-/* File: x86_64/op_div_int_2addr.S */
-/* File: x86_64/bindiv2addr.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
@@ -4373,12 +3865,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_2addr: /* 0xb4 */
-/* File: x86_64/op_rem_int_2addr.S */
-/* File: x86_64/bindiv2addr.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
@@ -4414,12 +3903,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_2addr: /* 0xb5 */
-/* File: x86_64/op_and_int_2addr.S */
-/* File: x86_64/binop2addr.S */
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
@@ -4439,12 +3925,9 @@ movswl %ax, %eax
     CLEAR_REF %rcx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_2addr: /* 0xb6 */
-/* File: x86_64/op_or_int_2addr.S */
-/* File: x86_64/binop2addr.S */
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
@@ -4464,12 +3947,9 @@ movswl %ax, %eax
     CLEAR_REF %rcx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_2addr: /* 0xb7 */
-/* File: x86_64/op_xor_int_2addr.S */
-/* File: x86_64/binop2addr.S */
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
@@ -4489,12 +3969,9 @@ movswl %ax, %eax
     CLEAR_REF %rcx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_2addr: /* 0xb8 */
-/* File: x86_64/op_shl_int_2addr.S */
-/* File: x86_64/shop2addr.S */
 /*
  * Generic 32-bit "shift/2addr" operation.
  */
@@ -4514,12 +3991,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_2addr: /* 0xb9 */
-/* File: x86_64/op_shr_int_2addr.S */
-/* File: x86_64/shop2addr.S */
 /*
  * Generic 32-bit "shift/2addr" operation.
  */
@@ -4539,12 +4013,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_2addr: /* 0xba */
-/* File: x86_64/op_ushr_int_2addr.S */
-/* File: x86_64/shop2addr.S */
 /*
  * Generic 32-bit "shift/2addr" operation.
  */
@@ -4564,12 +4035,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_long_2addr: /* 0xbb */
-/* File: x86_64/op_add_long_2addr.S */
-/* File: x86_64/binopWide2addr.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4582,12 +4050,9 @@ movswl %ax, %eax
     CLEAR_WIDE_REF %rcx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_long_2addr: /* 0xbc */
-/* File: x86_64/op_sub_long_2addr.S */
-/* File: x86_64/binopWide2addr.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4600,11 +4065,9 @@ movswl %ax, %eax
     CLEAR_WIDE_REF %rcx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_long_2addr: /* 0xbd */
-/* File: x86_64/op_mul_long_2addr.S */
     /* mul vA, vB */
     movl    rINST, %ecx                     # rcx <- A+
     sarl    $4, rINST                      # rINST <- B
@@ -4617,8 +4080,6 @@ movswl %ax, %eax
 /* ------------------------------ */
     .balign 128
 .L_op_div_long_2addr: /* 0xbe */
-/* File: x86_64/op_div_long_2addr.S */
-/* File: x86_64/bindiv2addr.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
@@ -4654,12 +4115,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_long_2addr: /* 0xbf */
-/* File: x86_64/op_rem_long_2addr.S */
-/* File: x86_64/bindiv2addr.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
@@ -4695,12 +4153,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_long_2addr: /* 0xc0 */
-/* File: x86_64/op_and_long_2addr.S */
-/* File: x86_64/binopWide2addr.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4713,12 +4168,9 @@ movswl %ax, %eax
     CLEAR_WIDE_REF %rcx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_long_2addr: /* 0xc1 */
-/* File: x86_64/op_or_long_2addr.S */
-/* File: x86_64/binopWide2addr.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4731,12 +4183,9 @@ movswl %ax, %eax
     CLEAR_WIDE_REF %rcx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_long_2addr: /* 0xc2 */
-/* File: x86_64/op_xor_long_2addr.S */
-/* File: x86_64/binopWide2addr.S */
 /*
  * Generic 64-bit binary operation.
  */
@@ -4749,12 +4198,9 @@ movswl %ax, %eax
     CLEAR_WIDE_REF %rcx
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_long_2addr: /* 0xc3 */
-/* File: x86_64/op_shl_long_2addr.S */
-/* File: x86_64/shop2addr.S */
 /*
  * Generic 32-bit "shift/2addr" operation.
  */
@@ -4774,12 +4220,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_long_2addr: /* 0xc4 */
-/* File: x86_64/op_shr_long_2addr.S */
-/* File: x86_64/shop2addr.S */
 /*
  * Generic 32-bit "shift/2addr" operation.
  */
@@ -4799,12 +4242,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_long_2addr: /* 0xc5 */
-/* File: x86_64/op_ushr_long_2addr.S */
-/* File: x86_64/shop2addr.S */
 /*
  * Generic 32-bit "shift/2addr" operation.
  */
@@ -4824,12 +4264,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_float_2addr: /* 0xc6 */
-/* File: x86_64/op_add_float_2addr.S */
-/* File: x86_64/sseBinop2Addr.S */
     movl    rINST, %ecx                     # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movss VREG_ADDRESS(%rcx), %xmm0        # %xmm0 <- 1st src
@@ -4840,12 +4277,9 @@ movswl %ax, %eax
     movss %xmm0, VREG_REF_ADDRESS(rINSTq)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_float_2addr: /* 0xc7 */
-/* File: x86_64/op_sub_float_2addr.S */
-/* File: x86_64/sseBinop2Addr.S */
     movl    rINST, %ecx                     # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movss VREG_ADDRESS(%rcx), %xmm0        # %xmm0 <- 1st src
@@ -4856,12 +4290,9 @@ movswl %ax, %eax
     movss %xmm0, VREG_REF_ADDRESS(rINSTq)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_float_2addr: /* 0xc8 */
-/* File: x86_64/op_mul_float_2addr.S */
-/* File: x86_64/sseBinop2Addr.S */
     movl    rINST, %ecx                     # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movss VREG_ADDRESS(%rcx), %xmm0        # %xmm0 <- 1st src
@@ -4872,12 +4303,9 @@ movswl %ax, %eax
     movss %xmm0, VREG_REF_ADDRESS(rINSTq)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_float_2addr: /* 0xc9 */
-/* File: x86_64/op_div_float_2addr.S */
-/* File: x86_64/sseBinop2Addr.S */
     movl    rINST, %ecx                     # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movss VREG_ADDRESS(%rcx), %xmm0        # %xmm0 <- 1st src
@@ -4888,11 +4316,9 @@ movswl %ax, %eax
     movss %xmm0, VREG_REF_ADDRESS(rINSTq)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_float_2addr: /* 0xca */
-/* File: x86_64/op_rem_float_2addr.S */
     /* rem_float/2addr vA, vB */
     movzbq  rINSTbl, %rcx                   # ecx <- A+
     sarl    $4, rINST                      # rINST <- B
@@ -4912,8 +4338,6 @@ movswl %ax, %eax
 /* ------------------------------ */
     .balign 128
 .L_op_add_double_2addr: /* 0xcb */
-/* File: x86_64/op_add_double_2addr.S */
-/* File: x86_64/sseBinop2Addr.S */
     movl    rINST, %ecx                     # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movsd VREG_ADDRESS(%rcx), %xmm0        # %xmm0 <- 1st src
@@ -4924,12 +4348,9 @@ movswl %ax, %eax
     movsd %xmm0, VREG_REF_ADDRESS(rINSTq)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_sub_double_2addr: /* 0xcc */
-/* File: x86_64/op_sub_double_2addr.S */
-/* File: x86_64/sseBinop2Addr.S */
     movl    rINST, %ecx                     # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movsd VREG_ADDRESS(%rcx), %xmm0        # %xmm0 <- 1st src
@@ -4940,12 +4361,9 @@ movswl %ax, %eax
     movsd %xmm0, VREG_REF_ADDRESS(rINSTq)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_double_2addr: /* 0xcd */
-/* File: x86_64/op_mul_double_2addr.S */
-/* File: x86_64/sseBinop2Addr.S */
     movl    rINST, %ecx                     # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movsd VREG_ADDRESS(%rcx), %xmm0        # %xmm0 <- 1st src
@@ -4956,12 +4374,9 @@ movswl %ax, %eax
     movsd %xmm0, VREG_REF_ADDRESS(rINSTq)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_double_2addr: /* 0xce */
-/* File: x86_64/op_div_double_2addr.S */
-/* File: x86_64/sseBinop2Addr.S */
     movl    rINST, %ecx                     # ecx <- A+
     andl    $0xf, %ecx                     # ecx <- A
     movsd VREG_ADDRESS(%rcx), %xmm0        # %xmm0 <- 1st src
@@ -4972,11 +4387,9 @@ movswl %ax, %eax
     movsd %xmm0, VREG_REF_ADDRESS(rINSTq)  # clear ref
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_double_2addr: /* 0xcf */
-/* File: x86_64/op_rem_double_2addr.S */
     /* rem_double/2addr vA, vB */
     movzbq  rINSTbl, %rcx                   # ecx <- A+
     sarl    $4, rINST                      # rINST <- B
@@ -4996,8 +4409,6 @@ movswl %ax, %eax
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit16: /* 0xd0 */
-/* File: x86_64/op_add_int_lit16.S */
-/* File: x86_64/binopLit16.S */
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5017,13 +4428,10 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int: /* 0xd1 */
-/* File: x86_64/op_rsub_int.S */
 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
-/* File: x86_64/binopLit16.S */
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5043,12 +4451,9 @@ movswl %ax, %eax
     SET_VREG %ecx, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit16: /* 0xd2 */
-/* File: x86_64/op_mul_int_lit16.S */
-/* File: x86_64/binopLit16.S */
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5068,12 +4473,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit16: /* 0xd3 */
-/* File: x86_64/op_div_int_lit16.S */
-/* File: x86_64/bindivLit16.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
@@ -5101,12 +4503,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit16: /* 0xd4 */
-/* File: x86_64/op_rem_int_lit16.S */
-/* File: x86_64/bindivLit16.S */
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
@@ -5134,12 +4533,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit16: /* 0xd5 */
-/* File: x86_64/op_and_int_lit16.S */
-/* File: x86_64/binopLit16.S */
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5159,12 +4555,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit16: /* 0xd6 */
-/* File: x86_64/op_or_int_lit16.S */
-/* File: x86_64/binopLit16.S */
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5184,12 +4577,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit16: /* 0xd7 */
-/* File: x86_64/op_xor_int_lit16.S */
-/* File: x86_64/binopLit16.S */
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5209,12 +4599,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_add_int_lit8: /* 0xd8 */
-/* File: x86_64/op_add_int_lit8.S */
-/* File: x86_64/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5233,12 +4620,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rsub_int_lit8: /* 0xd9 */
-/* File: x86_64/op_rsub_int_lit8.S */
-/* File: x86_64/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5257,12 +4641,9 @@ movswl %ax, %eax
     SET_VREG %ecx, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_mul_int_lit8: /* 0xda */
-/* File: x86_64/op_mul_int_lit8.S */
-/* File: x86_64/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5281,12 +4662,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_div_int_lit8: /* 0xdb */
-/* File: x86_64/op_div_int_lit8.S */
-/* File: x86_64/bindivLit8.S */
 /*
  * 32-bit div/rem "lit8" binary operation.  Handles special case of
  * op0=minint & op1=-1
@@ -5312,12 +4690,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_rem_int_lit8: /* 0xdc */
-/* File: x86_64/op_rem_int_lit8.S */
-/* File: x86_64/bindivLit8.S */
 /*
  * 32-bit div/rem "lit8" binary operation.  Handles special case of
  * op0=minint & op1=-1
@@ -5343,12 +4718,9 @@ movswl %ax, %eax
     .endif
     jmp     1b
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_and_int_lit8: /* 0xdd */
-/* File: x86_64/op_and_int_lit8.S */
-/* File: x86_64/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5367,12 +4739,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_or_int_lit8: /* 0xde */
-/* File: x86_64/op_or_int_lit8.S */
-/* File: x86_64/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5391,12 +4760,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_xor_int_lit8: /* 0xdf */
-/* File: x86_64/op_xor_int_lit8.S */
-/* File: x86_64/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5415,12 +4781,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shl_int_lit8: /* 0xe0 */
-/* File: x86_64/op_shl_int_lit8.S */
-/* File: x86_64/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5439,12 +4802,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_shr_int_lit8: /* 0xe1 */
-/* File: x86_64/op_shr_int_lit8.S */
-/* File: x86_64/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5463,12 +4823,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_ushr_int_lit8: /* 0xe2 */
-/* File: x86_64/op_ushr_int_lit8.S */
-/* File: x86_64/binopLit8.S */
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
@@ -5487,11 +4844,9 @@ movswl %ax, %eax
     SET_VREG %eax, rINSTq
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_quick: /* 0xe3 */
-/* File: x86_64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */
     /* op vA, vB, offset@CCCC */
     movl    rINST, %ecx                     # rcx <- BA
@@ -5513,8 +4868,6 @@ movswl %ax, %eax
 /* ------------------------------ */
     .balign 128
 .L_op_iget_wide_quick: /* 0xe4 */
-/* File: x86_64/op_iget_wide_quick.S */
-/* File: x86_64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */
     /* op vA, vB, offset@CCCC */
     movl    rINST, %ecx                     # rcx <- BA
@@ -5533,11 +4886,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_object_quick: /* 0xe5 */
-/* File: x86_64/op_iget_object_quick.S */
     /* For: iget-object-quick */
     /* op vA, vB, offset@CCCC */
     .extern artIGetObjectFromMterp
@@ -5557,7 +4908,6 @@ movswl %ax, %eax
 /* ------------------------------ */
     .balign 128
 .L_op_iput_quick: /* 0xe6 */
-/* File: x86_64/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbq  rINSTbl, %rcx                   # rcx <- BA
@@ -5574,7 +4924,6 @@ movswl %ax, %eax
 /* ------------------------------ */
     .balign 128
 .L_op_iput_wide_quick: /* 0xe7 */
-/* File: x86_64/op_iput_wide_quick.S */
     /* iput-wide-quick vA, vB, offset@CCCC */
     movzbq    rINSTbl, %rcx                 # rcx<- BA
     sarl      $4, %ecx                     # ecx<- B
@@ -5591,7 +4940,6 @@ movswl %ax, %eax
 /* ------------------------------ */
     .balign 128
 .L_op_iput_object_quick: /* 0xe8 */
-/* File: x86_64/op_iput_object_quick.S */
     EXPORT_PC
     leaq    OFF_FP_SHADOWFRAME(rFP), OUT_ARG0
     movq    rPC, OUT_ARG1
@@ -5605,8 +4953,6 @@ movswl %ax, %eax
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_quick: /* 0xe9 */
-/* File: x86_64/op_invoke_virtual_quick.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -5629,12 +4975,9 @@ movswl %ax, %eax
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_virtual_range_quick: /* 0xea */
-/* File: x86_64/op_invoke_virtual_range_quick.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -5657,12 +5000,9 @@ movswl %ax, %eax
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_boolean_quick: /* 0xeb */
-/* File: x86_64/op_iput_boolean_quick.S */
-/* File: x86_64/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbq  rINSTbl, %rcx                   # rcx <- BA
@@ -5676,12 +5016,9 @@ movswl %ax, %eax
     movb    rINSTbl, (%rcx,%rax,1)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_byte_quick: /* 0xec */
-/* File: x86_64/op_iput_byte_quick.S */
-/* File: x86_64/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbq  rINSTbl, %rcx                   # rcx <- BA
@@ -5695,12 +5032,9 @@ movswl %ax, %eax
     movb    rINSTbl, (%rcx,%rax,1)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_char_quick: /* 0xed */
-/* File: x86_64/op_iput_char_quick.S */
-/* File: x86_64/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbq  rINSTbl, %rcx                   # rcx <- BA
@@ -5714,12 +5048,9 @@ movswl %ax, %eax
     movw    rINSTw, (%rcx,%rax,1)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iput_short_quick: /* 0xee */
-/* File: x86_64/op_iput_short_quick.S */
-/* File: x86_64/op_iput_quick.S */
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbq  rINSTbl, %rcx                   # rcx <- BA
@@ -5733,12 +5064,9 @@ movswl %ax, %eax
     movw    rINSTw, (%rcx,%rax,1)
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_boolean_quick: /* 0xef */
-/* File: x86_64/op_iget_boolean_quick.S */
-/* File: x86_64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */
     /* op vA, vB, offset@CCCC */
     movl    rINST, %ecx                     # rcx <- BA
@@ -5757,12 +5085,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_byte_quick: /* 0xf0 */
-/* File: x86_64/op_iget_byte_quick.S */
-/* File: x86_64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */
     /* op vA, vB, offset@CCCC */
     movl    rINST, %ecx                     # rcx <- BA
@@ -5781,12 +5106,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_char_quick: /* 0xf1 */
-/* File: x86_64/op_iget_char_quick.S */
-/* File: x86_64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */
     /* op vA, vB, offset@CCCC */
     movl    rINST, %ecx                     # rcx <- BA
@@ -5805,12 +5127,9 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_iget_short_quick: /* 0xf2 */
-/* File: x86_64/op_iget_short_quick.S */
-/* File: x86_64/op_iget_quick.S */
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */
     /* op vA, vB, offset@CCCC */
     movl    rINST, %ecx                     # rcx <- BA
@@ -5829,89 +5148,65 @@ movswl %ax, %eax
     .endif
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f3: /* 0xf3 */
-/* File: x86_64/op_unused_f3.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f4: /* 0xf4 */
-/* File: x86_64/op_unused_f4.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f5: /* 0xf5 */
-/* File: x86_64/op_unused_f5.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f6: /* 0xf6 */
-/* File: x86_64/op_unused_f6.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f7: /* 0xf7 */
-/* File: x86_64/op_unused_f7.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f8: /* 0xf8 */
-/* File: x86_64/op_unused_f8.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_unused_f9: /* 0xf9 */
-/* File: x86_64/op_unused_f9.S */
-/* File: x86_64/unused.S */
 /*
  * Bail to reference interpreter to throw.
  */
     jmp     MterpFallback
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic: /* 0xfa */
-/* File: x86_64/op_invoke_polymorphic.S */
-/* File: x86_64/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -5934,12 +5229,9 @@ movswl %ax, %eax
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_polymorphic_range: /* 0xfb */
-/* File: x86_64/op_invoke_polymorphic_range.S */
-/* File: x86_64/invoke_polymorphic.S */
     /*
      * invoke-polymorphic handler wrapper.
      */
@@ -5962,12 +5254,9 @@ movswl %ax, %eax
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom: /* 0xfc */
-/* File: x86_64/op_invoke_custom.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -5990,12 +5279,9 @@ movswl %ax, %eax
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_invoke_custom_range: /* 0xfd */
-/* File: x86_64/op_invoke_custom_range.S */
-/* File: x86_64/invoke.S */
 /*
  * Generic invoke handler wrapper.
  */
@@ -6018,12 +5304,9 @@ movswl %ax, %eax
     FETCH_INST
     GOTO_NEXT
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_handle: /* 0xfe */
-/* File: x86_64/op_const_method_handle.S */
-/* File: x86_64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -6039,12 +5322,9 @@ movswl %ax, %eax
     jnz     MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
 /* ------------------------------ */
     .balign 128
 .L_op_const_method_type: /* 0xff */
-/* File: x86_64/op_const_method_type.S */
-/* File: x86_64/const.S */
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
@@ -6060,23 +5340,13 @@ movswl %ax, %eax
     jnz     MterpPossibleException
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
 
-
     .balign 128
-/* File: x86_64/instruction_end.S */
 
     OBJECT_TYPE(artMterpAsmInstructionEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd)
     .global SYMBOL(artMterpAsmInstructionEnd)
 SYMBOL(artMterpAsmInstructionEnd):
 
-
-/*
- * ===========================================================================
- *  Sister implementations
- * ===========================================================================
- */
-/* File: x86_64/instruction_start_sister.S */
-
     OBJECT_TYPE(artMterpAsmSisterStart)
     ASM_HIDDEN SYMBOL(artMterpAsmSisterStart)
     .global SYMBOL(artMterpAsmSisterStart)
@@ -6084,25 +5354,19 @@ SYMBOL(artMterpAsmInstructionEnd):
     .balign 4
 SYMBOL(artMterpAsmSisterStart):
 
-/* File: x86_64/instruction_end_sister.S */
-
     OBJECT_TYPE(artMterpAsmSisterEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd)
     .global SYMBOL(artMterpAsmSisterEnd)
 SYMBOL(artMterpAsmSisterEnd):
 
-/* File: x86_64/instruction_start_alt.S */
-
     OBJECT_TYPE(artMterpAsmAltInstructionStart)
     ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart)
     .global SYMBOL(artMterpAsmAltInstructionStart)
     .text
 SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
-
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_nop: /* 0x00 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6124,7 +5388,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move: /* 0x01 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6146,7 +5409,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_from16: /* 0x02 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6168,7 +5430,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_16: /* 0x03 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6190,7 +5451,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide: /* 0x04 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6212,7 +5472,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_from16: /* 0x05 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6234,7 +5493,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_wide_16: /* 0x06 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6256,7 +5514,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object: /* 0x07 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6278,7 +5535,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_from16: /* 0x08 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6300,7 +5556,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_object_16: /* 0x09 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6322,7 +5577,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result: /* 0x0a */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6344,7 +5598,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_wide: /* 0x0b */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6366,7 +5619,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_result_object: /* 0x0c */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6388,7 +5640,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_move_exception: /* 0x0d */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6410,7 +5661,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void: /* 0x0e */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6432,7 +5682,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return: /* 0x0f */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6454,7 +5703,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_wide: /* 0x10 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6476,7 +5724,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_object: /* 0x11 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6498,7 +5745,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_4: /* 0x12 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6520,7 +5766,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_16: /* 0x13 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6542,7 +5787,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const: /* 0x14 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6564,7 +5808,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_high16: /* 0x15 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6586,7 +5829,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_16: /* 0x16 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6608,7 +5850,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_32: /* 0x17 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6630,7 +5871,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide: /* 0x18 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6652,7 +5892,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_wide_high16: /* 0x19 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6674,7 +5913,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string: /* 0x1a */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6696,7 +5934,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_string_jumbo: /* 0x1b */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6718,7 +5955,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_class: /* 0x1c */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6740,7 +5976,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_enter: /* 0x1d */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6762,7 +5997,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_monitor_exit: /* 0x1e */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6784,7 +6018,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_check_cast: /* 0x1f */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6806,7 +6039,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_instance_of: /* 0x20 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6828,7 +6060,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_array_length: /* 0x21 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6850,7 +6081,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_instance: /* 0x22 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6872,7 +6102,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_new_array: /* 0x23 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6894,7 +6123,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array: /* 0x24 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6916,7 +6144,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_filled_new_array_range: /* 0x25 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6938,7 +6165,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_fill_array_data: /* 0x26 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6960,7 +6186,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_throw: /* 0x27 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -6982,7 +6207,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto: /* 0x28 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7004,7 +6228,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_16: /* 0x29 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7026,7 +6249,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_goto_32: /* 0x2a */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7048,7 +6270,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_packed_switch: /* 0x2b */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7070,7 +6291,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sparse_switch: /* 0x2c */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7092,7 +6312,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_float: /* 0x2d */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7114,7 +6333,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_float: /* 0x2e */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7136,7 +6354,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpl_double: /* 0x2f */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7158,7 +6375,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmpg_double: /* 0x30 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7180,7 +6396,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_cmp_long: /* 0x31 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7202,7 +6417,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eq: /* 0x32 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7224,7 +6438,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ne: /* 0x33 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7246,7 +6459,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lt: /* 0x34 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7268,7 +6480,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ge: /* 0x35 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7290,7 +6501,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gt: /* 0x36 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7312,7 +6522,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_le: /* 0x37 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7334,7 +6543,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_eqz: /* 0x38 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7356,7 +6564,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_nez: /* 0x39 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7378,7 +6585,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_ltz: /* 0x3a */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7400,7 +6606,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gez: /* 0x3b */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7422,7 +6627,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_gtz: /* 0x3c */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7444,7 +6648,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_if_lez: /* 0x3d */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7466,7 +6669,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3e: /* 0x3e */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7488,7 +6690,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_3f: /* 0x3f */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7510,7 +6711,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_40: /* 0x40 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7532,7 +6732,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_41: /* 0x41 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7554,7 +6753,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_42: /* 0x42 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7576,7 +6774,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_43: /* 0x43 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7598,7 +6795,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget: /* 0x44 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7620,7 +6816,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_wide: /* 0x45 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7642,7 +6837,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_object: /* 0x46 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7664,7 +6858,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_boolean: /* 0x47 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7686,7 +6879,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_byte: /* 0x48 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7708,7 +6900,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_char: /* 0x49 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7730,7 +6921,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aget_short: /* 0x4a */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7752,7 +6942,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput: /* 0x4b */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7774,7 +6963,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_wide: /* 0x4c */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7796,7 +6984,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_object: /* 0x4d */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7818,7 +7005,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_boolean: /* 0x4e */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7840,7 +7026,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_byte: /* 0x4f */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7862,7 +7047,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_char: /* 0x50 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7884,7 +7068,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_aput_short: /* 0x51 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7906,7 +7089,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget: /* 0x52 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7928,7 +7110,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide: /* 0x53 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7950,7 +7131,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object: /* 0x54 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7972,7 +7152,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean: /* 0x55 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -7994,7 +7173,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte: /* 0x56 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8016,7 +7194,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char: /* 0x57 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8038,7 +7215,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short: /* 0x58 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8060,7 +7236,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput: /* 0x59 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8082,7 +7257,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide: /* 0x5a */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8104,7 +7278,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object: /* 0x5b */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8126,7 +7299,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean: /* 0x5c */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8148,7 +7320,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte: /* 0x5d */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8170,7 +7341,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char: /* 0x5e */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8192,7 +7362,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short: /* 0x5f */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8214,7 +7383,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget: /* 0x60 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8236,7 +7404,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_wide: /* 0x61 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8258,7 +7425,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_object: /* 0x62 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8280,7 +7446,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_boolean: /* 0x63 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8302,7 +7467,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_byte: /* 0x64 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8324,7 +7488,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_char: /* 0x65 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8346,7 +7509,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sget_short: /* 0x66 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8368,7 +7530,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput: /* 0x67 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8390,7 +7551,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_wide: /* 0x68 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8412,7 +7572,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_object: /* 0x69 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8434,7 +7593,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_boolean: /* 0x6a */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8456,7 +7614,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_byte: /* 0x6b */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8478,7 +7635,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_char: /* 0x6c */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8500,7 +7656,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sput_short: /* 0x6d */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8522,7 +7677,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual: /* 0x6e */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8544,7 +7698,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super: /* 0x6f */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8566,7 +7719,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct: /* 0x70 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8588,7 +7740,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static: /* 0x71 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8610,7 +7761,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface: /* 0x72 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8632,7 +7782,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_return_void_no_barrier: /* 0x73 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8654,7 +7803,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range: /* 0x74 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8676,7 +7824,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_super_range: /* 0x75 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8698,7 +7845,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_direct_range: /* 0x76 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8720,7 +7866,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_static_range: /* 0x77 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8742,7 +7887,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_interface_range: /* 0x78 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8764,7 +7908,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_79: /* 0x79 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8786,7 +7929,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_7a: /* 0x7a */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8808,7 +7950,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_int: /* 0x7b */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8830,7 +7971,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_int: /* 0x7c */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8852,7 +7992,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_long: /* 0x7d */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8874,7 +8013,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_not_long: /* 0x7e */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8896,7 +8034,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_float: /* 0x7f */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8918,7 +8055,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_neg_double: /* 0x80 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8940,7 +8076,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_long: /* 0x81 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8962,7 +8097,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_float: /* 0x82 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -8984,7 +8118,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_double: /* 0x83 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9006,7 +8139,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_int: /* 0x84 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9028,7 +8160,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_float: /* 0x85 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9050,7 +8181,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_long_to_double: /* 0x86 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9072,7 +8202,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_int: /* 0x87 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9094,7 +8223,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_long: /* 0x88 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9116,7 +8244,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_float_to_double: /* 0x89 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9138,7 +8265,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_int: /* 0x8a */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9160,7 +8286,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_long: /* 0x8b */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9182,7 +8307,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_double_to_float: /* 0x8c */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9204,7 +8328,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_byte: /* 0x8d */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9226,7 +8349,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_char: /* 0x8e */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9248,7 +8370,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_int_to_short: /* 0x8f */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9270,7 +8391,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int: /* 0x90 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9292,7 +8412,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int: /* 0x91 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9314,7 +8433,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int: /* 0x92 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9336,7 +8454,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int: /* 0x93 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9358,7 +8475,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int: /* 0x94 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9380,7 +8496,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int: /* 0x95 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9402,7 +8517,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int: /* 0x96 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9424,7 +8538,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int: /* 0x97 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9446,7 +8559,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int: /* 0x98 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9468,7 +8580,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int: /* 0x99 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9490,7 +8601,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int: /* 0x9a */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9512,7 +8622,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long: /* 0x9b */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9534,7 +8643,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long: /* 0x9c */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9556,7 +8664,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long: /* 0x9d */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9578,7 +8685,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long: /* 0x9e */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9600,7 +8706,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long: /* 0x9f */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9622,7 +8727,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long: /* 0xa0 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9644,7 +8748,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long: /* 0xa1 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9666,7 +8769,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long: /* 0xa2 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9688,7 +8790,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long: /* 0xa3 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9710,7 +8811,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long: /* 0xa4 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9732,7 +8832,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long: /* 0xa5 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9754,7 +8853,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float: /* 0xa6 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9776,7 +8874,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float: /* 0xa7 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9798,7 +8895,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float: /* 0xa8 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9820,7 +8916,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float: /* 0xa9 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9842,7 +8937,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float: /* 0xaa */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9864,7 +8958,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double: /* 0xab */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9886,7 +8979,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double: /* 0xac */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9908,7 +9000,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double: /* 0xad */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9930,7 +9021,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double: /* 0xae */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9952,7 +9042,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double: /* 0xaf */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9974,7 +9063,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_2addr: /* 0xb0 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -9996,7 +9084,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_int_2addr: /* 0xb1 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10018,7 +9105,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_2addr: /* 0xb2 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10040,7 +9126,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_2addr: /* 0xb3 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10062,7 +9147,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_2addr: /* 0xb4 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10084,7 +9168,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_2addr: /* 0xb5 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10106,7 +9189,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_2addr: /* 0xb6 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10128,7 +9210,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_2addr: /* 0xb7 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10150,7 +9231,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_2addr: /* 0xb8 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10172,7 +9252,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_2addr: /* 0xb9 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10194,7 +9273,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_2addr: /* 0xba */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10216,7 +9294,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_long_2addr: /* 0xbb */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10238,7 +9315,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_long_2addr: /* 0xbc */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10260,7 +9336,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_long_2addr: /* 0xbd */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10282,7 +9357,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_long_2addr: /* 0xbe */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10304,7 +9378,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_long_2addr: /* 0xbf */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10326,7 +9399,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_long_2addr: /* 0xc0 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10348,7 +9420,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_long_2addr: /* 0xc1 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10370,7 +9441,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_long_2addr: /* 0xc2 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10392,7 +9462,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_long_2addr: /* 0xc3 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10414,7 +9483,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_long_2addr: /* 0xc4 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10436,7 +9504,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_long_2addr: /* 0xc5 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10458,7 +9525,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_float_2addr: /* 0xc6 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10480,7 +9546,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_float_2addr: /* 0xc7 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10502,7 +9567,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_float_2addr: /* 0xc8 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10524,7 +9588,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_float_2addr: /* 0xc9 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10546,7 +9609,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_float_2addr: /* 0xca */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10568,7 +9630,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_double_2addr: /* 0xcb */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10590,7 +9651,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_sub_double_2addr: /* 0xcc */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10612,7 +9672,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_double_2addr: /* 0xcd */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10634,7 +9693,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_double_2addr: /* 0xce */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10656,7 +9714,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_double_2addr: /* 0xcf */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10678,7 +9735,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit16: /* 0xd0 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10700,7 +9756,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int: /* 0xd1 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10722,7 +9777,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit16: /* 0xd2 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10744,7 +9798,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit16: /* 0xd3 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10766,7 +9819,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit16: /* 0xd4 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10788,7 +9840,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit16: /* 0xd5 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10810,7 +9861,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit16: /* 0xd6 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10832,7 +9882,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit16: /* 0xd7 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10854,7 +9903,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_add_int_lit8: /* 0xd8 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10876,7 +9924,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rsub_int_lit8: /* 0xd9 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10898,7 +9945,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_mul_int_lit8: /* 0xda */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10920,7 +9966,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_div_int_lit8: /* 0xdb */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10942,7 +9987,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_rem_int_lit8: /* 0xdc */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10964,7 +10008,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_and_int_lit8: /* 0xdd */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -10986,7 +10029,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_or_int_lit8: /* 0xde */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11008,7 +10050,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_xor_int_lit8: /* 0xdf */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11030,7 +10071,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shl_int_lit8: /* 0xe0 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11052,7 +10092,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_shr_int_lit8: /* 0xe1 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11074,7 +10113,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_ushr_int_lit8: /* 0xe2 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11096,7 +10134,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_quick: /* 0xe3 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11118,7 +10155,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_wide_quick: /* 0xe4 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11140,7 +10176,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_object_quick: /* 0xe5 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11162,7 +10197,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_quick: /* 0xe6 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11184,7 +10218,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_wide_quick: /* 0xe7 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11206,7 +10239,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_object_quick: /* 0xe8 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11228,7 +10260,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11250,7 +10281,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11272,7 +10302,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_boolean_quick: /* 0xeb */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11294,7 +10323,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_byte_quick: /* 0xec */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11316,7 +10344,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_char_quick: /* 0xed */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11338,7 +10365,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iput_short_quick: /* 0xee */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11360,7 +10386,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_boolean_quick: /* 0xef */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11382,7 +10407,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_byte_quick: /* 0xf0 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11404,7 +10428,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_char_quick: /* 0xf1 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11426,7 +10449,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_iget_short_quick: /* 0xf2 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11448,7 +10470,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f3: /* 0xf3 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11470,7 +10491,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f4: /* 0xf4 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11492,7 +10512,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f5: /* 0xf5 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11514,7 +10533,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f6: /* 0xf6 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11536,7 +10554,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f7: /* 0xf7 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11558,7 +10575,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f8: /* 0xf8 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11580,7 +10596,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_unused_f9: /* 0xf9 */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11602,7 +10617,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic: /* 0xfa */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11624,7 +10638,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11646,7 +10659,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom: /* 0xfc */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11668,7 +10680,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_invoke_custom_range: /* 0xfd */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11690,7 +10701,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_handle: /* 0xfe */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11712,7 +10722,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
 /* ------------------------------ */
     .balign 128
 .L_ALT_op_const_method_type: /* 0xff */
-/* File: x86_64/alt_stub.S */
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
@@ -11732,14 +10741,11 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop
     jmp     .L_op_nop+(255*128)
 
     .balign 128
-/* File: x86_64/instruction_end_alt.S */
 
     OBJECT_TYPE(artMterpAsmAltInstructionEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd)
     .global SYMBOL(artMterpAsmAltInstructionEnd)
 SYMBOL(artMterpAsmAltInstructionEnd):
-
-/* File: x86_64/footer.S */
 /*
  * ===========================================================================
  *  Common subroutines and data
@@ -12037,4 +11043,3 @@ MRestoreFrame:
     ret
     .cfi_endproc
     SIZE(ExecuteMterpImpl,ExecuteMterpImpl)
-
diff --git a/runtime/interpreter/mterp/rebuild.sh b/runtime/interpreter/mterp/rebuild.sh
deleted file mode 100755
index ca3dcd9a136a27844fcba607cc3f27c11b1e08c3..0000000000000000000000000000000000000000
--- a/runtime/interpreter/mterp/rebuild.sh
+++ /dev/null
@@ -1,23 +0,0 @@
-#!/bin/sh
-#
-# Copyright (C) 2016 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-#
-# Rebuild for all known targets.  Necessary until the stuff in "out" gets
-# generated as part of the build.
-#
-set -e
-
-for arch in arm x86 mips arm64 x86_64 mips64; do TARGET_ARCH_EXT=$arch make -f Makefile_mterp; done
diff --git a/runtime/interpreter/mterp/x86/alt_stub.S b/runtime/interpreter/mterp/x86/alt_stub.S
index a5b39b80e9f44e56a5fe69904f1593d28f385d56..79e3f74d1a560feaf2219ef368e16a68a802acfe 100644
--- a/runtime/interpreter/mterp/x86/alt_stub.S
+++ b/runtime/interpreter/mterp/x86/alt_stub.S
@@ -1,3 +1,4 @@
+%def alt_stub():
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
diff --git a/runtime/interpreter/mterp/x86/bincmp.S b/runtime/interpreter/mterp/x86/bincmp.S
index ee32278d5b2001e5a43d90f9bc1526cdeef420f3..28ea08e341fef5fcdec526d35aa37ed5725f7909 100644
--- a/runtime/interpreter/mterp/x86/bincmp.S
+++ b/runtime/interpreter/mterp/x86/bincmp.S
@@ -1,3 +1,4 @@
+%def bincmp(revcmp=""):
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
diff --git a/runtime/interpreter/mterp/x86/bindiv.S b/runtime/interpreter/mterp/x86/bindiv.S
index e87ba45546b811a1da21fbeb3276e97a9c01e365..e59e6ad6806ce23d7302cbc00d917300a2633c2e 100644
--- a/runtime/interpreter/mterp/x86/bindiv.S
+++ b/runtime/interpreter/mterp/x86/bindiv.S
@@ -1,4 +1,4 @@
-%default {"result":"","special":"","rem":""}
+%def bindiv(result="", special="", rem=""):
 /*
  * 32-bit binary div/rem operation.  Handles special case of op0=minint and
  * op1=-1.
diff --git a/runtime/interpreter/mterp/x86/bindiv2addr.S b/runtime/interpreter/mterp/x86/bindiv2addr.S
index e620996c9fba732ca10bea62e37ccc8cfab86b1d..40c22bb271450267e3d7c26205fa7d8ae1532f50 100644
--- a/runtime/interpreter/mterp/x86/bindiv2addr.S
+++ b/runtime/interpreter/mterp/x86/bindiv2addr.S
@@ -1,4 +1,4 @@
-%default {"result":"","special":""}
+%def bindiv2addr(result="", special=""):
 /*
  * 32-bit binary div/rem operation.  Handles special case of op0=minint and
  * op1=-1.
diff --git a/runtime/interpreter/mterp/x86/bindivLit16.S b/runtime/interpreter/mterp/x86/bindivLit16.S
index be094aee496e172908f4c3f0387722d01766eb50..a89f45203123b7ce90957d11491381d75ee9f684 100644
--- a/runtime/interpreter/mterp/x86/bindivLit16.S
+++ b/runtime/interpreter/mterp/x86/bindivLit16.S
@@ -1,4 +1,4 @@
-%default {"result":"","special":""}
+%def bindivLit16(result="", special=""):
 /*
  * 32-bit binary div/rem operation.  Handles special case of op0=minint and
  * op1=-1.
diff --git a/runtime/interpreter/mterp/x86/bindivLit8.S b/runtime/interpreter/mterp/x86/bindivLit8.S
index fddb54574d91afa8b86c27c9f357d01656cd90a6..ce130194b0d615b180c347bc1acfc220832b3f23 100644
--- a/runtime/interpreter/mterp/x86/bindivLit8.S
+++ b/runtime/interpreter/mterp/x86/bindivLit8.S
@@ -1,4 +1,4 @@
-%default {"result":"","special":""}
+%def bindivLit8(result="", special=""):
 /*
  * 32-bit div/rem "lit8" binary operation.  Handles special case of
  * op0=minint & op1=-1
diff --git a/runtime/interpreter/mterp/x86/binop.S b/runtime/interpreter/mterp/x86/binop.S
index d8952352129bf5f59d5b7a3e0fe1b23c94f599cb..c82737209d62eadb9ff129b6d7c19fbdbc3b20df 100644
--- a/runtime/interpreter/mterp/x86/binop.S
+++ b/runtime/interpreter/mterp/x86/binop.S
@@ -1,4 +1,4 @@
-%default {"result":"%eax"}
+%def binop(result="%eax", instr=""):
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
diff --git a/runtime/interpreter/mterp/x86/binop1.S b/runtime/interpreter/mterp/x86/binop1.S
index 5049bb325e009605cbb12a0e1bd7cc45ad377c5f..e6ae857eed54100098e19a5df3e9b41171926fb8 100644
--- a/runtime/interpreter/mterp/x86/binop1.S
+++ b/runtime/interpreter/mterp/x86/binop1.S
@@ -1,4 +1,4 @@
-%default {"result":"%eax","tmp":"%ecx"}
+%def binop1(result="%eax", tmp="%ecx", instr=""):
 /*
  * Generic 32-bit binary operation in which both operands loaded to
  * registers (op0 in eax, op1 in ecx).
diff --git a/runtime/interpreter/mterp/x86/binop2addr.S b/runtime/interpreter/mterp/x86/binop2addr.S
index f126234a40ceefd115a6ec2e11d7f6fe5cd04fad..0b74364897d18a0037cbcd2ad8dd684e0eaa70e1 100644
--- a/runtime/interpreter/mterp/x86/binop2addr.S
+++ b/runtime/interpreter/mterp/x86/binop2addr.S
@@ -1,4 +1,4 @@
-%default {"result":"%eax"}
+%def binop2addr(result="%eax", instr=""):
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
diff --git a/runtime/interpreter/mterp/x86/binopLit16.S b/runtime/interpreter/mterp/x86/binopLit16.S
index 2fd59de9361cf90f4f409b84ab52404611744dbd..5b162f16ca668af7980594d1a5e7549d90c9e304 100644
--- a/runtime/interpreter/mterp/x86/binopLit16.S
+++ b/runtime/interpreter/mterp/x86/binopLit16.S
@@ -1,4 +1,4 @@
-%default {"result":"%eax"}
+%def binopLit16(result="%eax", instr=""):
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
diff --git a/runtime/interpreter/mterp/x86/binopLit8.S b/runtime/interpreter/mterp/x86/binopLit8.S
index 67cead27d5bcbcbfcff2cc4b9f8d1dcbb884e324..c2ebc1800c9dbcd4d1e19d329b79b5b79832961b 100644
--- a/runtime/interpreter/mterp/x86/binopLit8.S
+++ b/runtime/interpreter/mterp/x86/binopLit8.S
@@ -1,4 +1,4 @@
-%default {"result":"%eax"}
+%def binopLit8(result="%eax", instr=""):
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
diff --git a/runtime/interpreter/mterp/x86/binopWide.S b/runtime/interpreter/mterp/x86/binopWide.S
index da1293d5b94be087f370f61277d5a4a4af9d7ce7..1e878c8991327a4d0631059c9ed301df50a6f8f1 100644
--- a/runtime/interpreter/mterp/x86/binopWide.S
+++ b/runtime/interpreter/mterp/x86/binopWide.S
@@ -1,3 +1,4 @@
+%def binopWide(instr1="", instr2=""):
 /*
  * Generic 64-bit binary operation.
  */
diff --git a/runtime/interpreter/mterp/x86/binopWide2addr.S b/runtime/interpreter/mterp/x86/binopWide2addr.S
index da816f468bd0761dd77096b2ed417c8602dac0db..65da1df36cd0dc980ee409f7befd49a1912396fc 100644
--- a/runtime/interpreter/mterp/x86/binopWide2addr.S
+++ b/runtime/interpreter/mterp/x86/binopWide2addr.S
@@ -1,3 +1,4 @@
+%def binopWide2addr(instr1="", instr2=""):
 /*
  * Generic 64-bit binary operation.
  */
diff --git a/runtime/interpreter/mterp/x86/const.S b/runtime/interpreter/mterp/x86/const.S
index f0cac1a19b3f3625ebdecf696244dbe75ba6a873..aad76bb4eed951a9e2b0a2e7958f9d284b37cda8 100644
--- a/runtime/interpreter/mterp/x86/const.S
+++ b/runtime/interpreter/mterp/x86/const.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedConstHandler" }
+%def const(helper="UndefinedConstHandler"):
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
diff --git a/runtime/interpreter/mterp/x86/cvtfp_int.S b/runtime/interpreter/mterp/x86/cvtfp_int.S
index a8bad639d60491df4a8c4390dc63156802d22bc4..0bc9908e94f135ee1be523a350e35192f1c0c468 100644
--- a/runtime/interpreter/mterp/x86/cvtfp_int.S
+++ b/runtime/interpreter/mterp/x86/cvtfp_int.S
@@ -1,4 +1,4 @@
-%default {"srcdouble":"1","tgtlong":"1"}
+%def cvtfp_int(srcdouble="1", tgtlong="1"):
 /* On fp to int conversions, Java requires that
  * if the result > maxint, it should be clamped to maxint.  If it is less
  * than minint, it should be clamped to minint.  If it is a nan, the result
diff --git a/runtime/interpreter/mterp/x86/entry.S b/runtime/interpreter/mterp/x86/entry.S
index 939dc61d952c0efb0d6627071e1b87cb9bcb3000..b6291c139310e3b65acbe51a26c8a25bf229793c 100644
--- a/runtime/interpreter/mterp/x86/entry.S
+++ b/runtime/interpreter/mterp/x86/entry.S
@@ -1,3 +1,4 @@
+%def entry():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
diff --git a/runtime/interpreter/mterp/x86/fallback.S b/runtime/interpreter/mterp/x86/fallback.S
index 8d61166f63d57a950db9bb1e3bceef3edb6a8374..e3c2e2bd40c3cc11f26d20119106d2b881821094 100644
--- a/runtime/interpreter/mterp/x86/fallback.S
+++ b/runtime/interpreter/mterp/x86/fallback.S
@@ -1,3 +1,4 @@
+%def fallback():
 /* Transfer stub to alternate interpreter */
     jmp     MterpFallback
 
diff --git a/runtime/interpreter/mterp/x86/field.S b/runtime/interpreter/mterp/x86/field.S
index 8432c744ea6944b388b3935757c876b864a0178c..06362d866b49637f8de2e0b1466a73fcb7c87e1b 100644
--- a/runtime/interpreter/mterp/x86/field.S
+++ b/runtime/interpreter/mterp/x86/field.S
@@ -1,4 +1,4 @@
-%default { }
+%def field(helper=""):
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
diff --git a/runtime/interpreter/mterp/x86/footer.S b/runtime/interpreter/mterp/x86/footer.S
index 0b08cf98a379972929ebceb6225ccf123a1bcc55..31cc067d5a4098359fb6748f8f116222dd8b4409 100644
--- a/runtime/interpreter/mterp/x86/footer.S
+++ b/runtime/interpreter/mterp/x86/footer.S
@@ -1,3 +1,4 @@
+%def footer():
 /*
  * ===========================================================================
  *  Common subroutines and data
diff --git a/runtime/interpreter/mterp/x86/fpcmp.S b/runtime/interpreter/mterp/x86/fpcmp.S
index 5f9eef9d097c641cbcb6dc33344f712e2bc05bf1..7cd18f6227bd1880e6d2cdb4adbd81bb35297354 100644
--- a/runtime/interpreter/mterp/x86/fpcmp.S
+++ b/runtime/interpreter/mterp/x86/fpcmp.S
@@ -1,4 +1,4 @@
-%default {"suff":"d","nanval":"pos"}
+%def fpcmp(suff="d", nanval="pos"):
 /*
  * Compare two floating-point values.  Puts 0, 1, or -1 into the
  * destination register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/x86/fpcvt.S b/runtime/interpreter/mterp/x86/fpcvt.S
index 780828518fbc0660d025542febdff7834bee5445..4280f1580eb6e6f406e754dce9fb143cb7981e43 100644
--- a/runtime/interpreter/mterp/x86/fpcvt.S
+++ b/runtime/interpreter/mterp/x86/fpcvt.S
@@ -1,4 +1,4 @@
-%default {"instr":"","load":"","store":"","wide":"0"}
+%def fpcvt(instr="", load="", store="", wide="0"):
 /*
  * Generic 32-bit FP conversion operation.
  */
diff --git a/runtime/interpreter/mterp/x86/header.S b/runtime/interpreter/mterp/x86/header.S
index a79db27abf1b0d21efeb8fc7eb3768c093413873..f0d14fea1904401a0630b93a250a21c2f3860c5e 100644
--- a/runtime/interpreter/mterp/x86/header.S
+++ b/runtime/interpreter/mterp/x86/header.S
@@ -1,3 +1,4 @@
+%def header():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
diff --git a/runtime/interpreter/mterp/x86/instruction_end.S b/runtime/interpreter/mterp/x86/instruction_end.S
index 94587f83b7ece94acc81c162b24242ca73dbf6a8..5a24b66decca371073500034a552ba621bd6137a 100644
--- a/runtime/interpreter/mterp/x86/instruction_end.S
+++ b/runtime/interpreter/mterp/x86/instruction_end.S
@@ -1,3 +1,4 @@
+%def instruction_end():
 
     OBJECT_TYPE(artMterpAsmInstructionEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd)
diff --git a/runtime/interpreter/mterp/x86/instruction_end_alt.S b/runtime/interpreter/mterp/x86/instruction_end_alt.S
index 7757bce9a7eba09c81d13bb34be3356a1c0813d8..d037db988c668c05844c8eb65ce1920647270f21 100644
--- a/runtime/interpreter/mterp/x86/instruction_end_alt.S
+++ b/runtime/interpreter/mterp/x86/instruction_end_alt.S
@@ -1,3 +1,4 @@
+%def instruction_end_alt():
 
     OBJECT_TYPE(artMterpAsmAltInstructionEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd)
diff --git a/runtime/interpreter/mterp/x86/instruction_end_sister.S b/runtime/interpreter/mterp/x86/instruction_end_sister.S
index 8eb79accdf82bd257721ba37a04ed9319d23c36b..7b1ec89d60e578f4412a00178d0b519bb30de1e5 100644
--- a/runtime/interpreter/mterp/x86/instruction_end_sister.S
+++ b/runtime/interpreter/mterp/x86/instruction_end_sister.S
@@ -1,3 +1,4 @@
+%def instruction_end_sister():
 
     OBJECT_TYPE(artMterpAsmSisterEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd)
diff --git a/runtime/interpreter/mterp/x86/instruction_start.S b/runtime/interpreter/mterp/x86/instruction_start.S
index 5d29a8199373e2abfc49b32baf183107a96b3c1d..dee581b60f05ee71d567a2acaa17f7f72163e1d0 100644
--- a/runtime/interpreter/mterp/x86/instruction_start.S
+++ b/runtime/interpreter/mterp/x86/instruction_start.S
@@ -1,3 +1,4 @@
+%def instruction_start():
 
     OBJECT_TYPE(artMterpAsmInstructionStart)
     ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart)
diff --git a/runtime/interpreter/mterp/x86/instruction_start_alt.S b/runtime/interpreter/mterp/x86/instruction_start_alt.S
index 8dcf5bfaf95be22f84f4e8670a19a56d7b9a2d46..66650e7a6e69cbce9a8499c347dee7dc04d857b5 100644
--- a/runtime/interpreter/mterp/x86/instruction_start_alt.S
+++ b/runtime/interpreter/mterp/x86/instruction_start_alt.S
@@ -1,3 +1,4 @@
+%def instruction_start_alt():
 
     OBJECT_TYPE(artMterpAsmAltInstructionStart)
     ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart)
diff --git a/runtime/interpreter/mterp/x86/instruction_start_sister.S b/runtime/interpreter/mterp/x86/instruction_start_sister.S
index 796e98b09a4ca70adac9aa64992c0928fce7229e..8c156adf7e188b93cd598d64ab349621e8877c83 100644
--- a/runtime/interpreter/mterp/x86/instruction_start_sister.S
+++ b/runtime/interpreter/mterp/x86/instruction_start_sister.S
@@ -1,3 +1,4 @@
+%def instruction_start_sister():
 
     OBJECT_TYPE(artMterpAsmSisterStart)
     ASM_HIDDEN SYMBOL(artMterpAsmSisterStart)
diff --git a/runtime/interpreter/mterp/x86/invoke.S b/runtime/interpreter/mterp/x86/invoke.S
index c23053becb94cbb05aaf4b303481664afb50e2ee..eb5cdbc786b919b0e594e9402047d7db0879c4c7 100644
--- a/runtime/interpreter/mterp/x86/invoke.S
+++ b/runtime/interpreter/mterp/x86/invoke.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke(helper="UndefinedInvokeHandler"):
 /*
  * Generic invoke handler wrapper.
  */
diff --git a/runtime/interpreter/mterp/x86/invoke_polymorphic.S b/runtime/interpreter/mterp/x86/invoke_polymorphic.S
index 5690b22028e61a03a366e4693e6222153a5183b3..63196ec360e07038b8fa337452ed06e0da0034ef 100644
--- a/runtime/interpreter/mterp/x86/invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/x86/invoke_polymorphic.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke_polymorphic(helper="UndefinedInvokeHandler"):
     /*
      * invoke-polymorphic handler wrapper.
      */
diff --git a/runtime/interpreter/mterp/x86/op_add_double.S b/runtime/interpreter/mterp/x86/op_add_double.S
index de2708f442ee79c6b88719fd2b617e9513d910bc..a00923928b59cc7aef30983b49743a3a7506646e 100644
--- a/runtime/interpreter/mterp/x86/op_add_double.S
+++ b/runtime/interpreter/mterp/x86/op_add_double.S
@@ -1 +1,2 @@
-%include "x86/sseBinop.S" {"instr":"adds","suff":"d"}
+%def op_add_double():
+%  sseBinop(instr="adds", suff="d")
diff --git a/runtime/interpreter/mterp/x86/op_add_double_2addr.S b/runtime/interpreter/mterp/x86/op_add_double_2addr.S
index 538c9ab76ef90c977d7ef4e3efd1c3e80b7f0c65..8cb45a9a202a163d2b563fa3bb37af08d420503f 100644
--- a/runtime/interpreter/mterp/x86/op_add_double_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_add_double_2addr.S
@@ -1 +1,2 @@
-%include "x86/sseBinop2Addr.S" {"instr":"adds","suff":"d"}
+%def op_add_double_2addr():
+%  sseBinop2Addr(instr="adds", suff="d")
diff --git a/runtime/interpreter/mterp/x86/op_add_float.S b/runtime/interpreter/mterp/x86/op_add_float.S
index 80b173658b695f27e05d6d37370b4aed20d0b500..dee28c7b8bce8901043dde115e81a94d4b69a695 100644
--- a/runtime/interpreter/mterp/x86/op_add_float.S
+++ b/runtime/interpreter/mterp/x86/op_add_float.S
@@ -1 +1,2 @@
-%include "x86/sseBinop.S" {"instr":"adds","suff":"s"}
+%def op_add_float():
+%  sseBinop(instr="adds", suff="s")
diff --git a/runtime/interpreter/mterp/x86/op_add_float_2addr.S b/runtime/interpreter/mterp/x86/op_add_float_2addr.S
index 66492539762423ca945461b0698fc5f975d39ee3..4deb4451ce3d3db4cf944be31161e1070c8b2fc5 100644
--- a/runtime/interpreter/mterp/x86/op_add_float_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_add_float_2addr.S
@@ -1 +1,2 @@
-%include "x86/sseBinop2Addr.S" {"instr":"adds","suff":"s"}
+%def op_add_float_2addr():
+%  sseBinop2Addr(instr="adds", suff="s")
diff --git a/runtime/interpreter/mterp/x86/op_add_int.S b/runtime/interpreter/mterp/x86/op_add_int.S
index f71a56b65eca404a392b8c7baa4b66ccad893726..9c4455ab64a15112b0535cfff695b7c1029f22d9 100644
--- a/runtime/interpreter/mterp/x86/op_add_int.S
+++ b/runtime/interpreter/mterp/x86/op_add_int.S
@@ -1 +1,2 @@
-%include "x86/binop.S" {"instr":"addl    (rFP,%ecx,4), %eax"}
+%def op_add_int():
+%  binop(instr="addl    (rFP,%ecx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86/op_add_int_2addr.S b/runtime/interpreter/mterp/x86/op_add_int_2addr.S
index 5d43b6517d639d644afc6e2c56acd9db1cb74058..b04ae4c57f27ab04653703e1ef2b4dd1dd935f1e 100644
--- a/runtime/interpreter/mterp/x86/op_add_int_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_add_int_2addr.S
@@ -1 +1,2 @@
-%include "x86/binop2addr.S" {"instr":"addl    %eax, (rFP,%ecx,4)"}
+%def op_add_int_2addr():
+%  binop2addr(instr="addl    %eax, (rFP,%ecx,4)")
diff --git a/runtime/interpreter/mterp/x86/op_add_int_lit16.S b/runtime/interpreter/mterp/x86/op_add_int_lit16.S
index 4f34d173f260a8d52c638dc547518bc8deea4be2..a43103019e65b948d4b81072164ada0f15982e0b 100644
--- a/runtime/interpreter/mterp/x86/op_add_int_lit16.S
+++ b/runtime/interpreter/mterp/x86/op_add_int_lit16.S
@@ -1 +1,2 @@
-%include "x86/binopLit16.S" {"instr":"addl    %ecx, %eax"}
+%def op_add_int_lit16():
+%  binopLit16(instr="addl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_add_int_lit8.S b/runtime/interpreter/mterp/x86/op_add_int_lit8.S
index 3f14744dcd6998f95c86d20221b0739889745c66..3205aee0cb35ef38c13eb4604053ae202072f85f 100644
--- a/runtime/interpreter/mterp/x86/op_add_int_lit8.S
+++ b/runtime/interpreter/mterp/x86/op_add_int_lit8.S
@@ -1 +1,2 @@
-%include "x86/binopLit8.S" {"instr":"addl    %ecx, %eax"}
+%def op_add_int_lit8():
+%  binopLit8(instr="addl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_add_long.S b/runtime/interpreter/mterp/x86/op_add_long.S
index dce0c265276ef4c307d873f445a8a2752053bc5b..24a922601fafe14d3a06effa0a26c05f88dbb095 100644
--- a/runtime/interpreter/mterp/x86/op_add_long.S
+++ b/runtime/interpreter/mterp/x86/op_add_long.S
@@ -1 +1,2 @@
-%include "x86/binopWide.S" {"instr1":"addl    (rFP,%ecx,4), rIBASE", "instr2":"adcl    4(rFP,%ecx,4), %eax"}
+%def op_add_long():
+%  binopWide(instr1="addl    (rFP,%ecx,4), rIBASE", instr2="adcl    4(rFP,%ecx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86/op_add_long_2addr.S b/runtime/interpreter/mterp/x86/op_add_long_2addr.S
index 7847640e38c1e207fcccf8e5f3d8e91aa9b52807..e020714a7476715075a83fbf8da15a28db75c08c 100644
--- a/runtime/interpreter/mterp/x86/op_add_long_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_add_long_2addr.S
@@ -1 +1,2 @@
-%include "x86/binopWide2addr.S" {"instr1":"addl    %eax, (rFP,rINST,4)","instr2":"adcl    %ecx, 4(rFP,rINST,4)"}
+%def op_add_long_2addr():
+%  binopWide2addr(instr1="addl    %eax, (rFP,rINST,4)", instr2="adcl    %ecx, 4(rFP,rINST,4)")
diff --git a/runtime/interpreter/mterp/x86/op_aget.S b/runtime/interpreter/mterp/x86/op_aget.S
index 338386ff409ea32a9fb5e6b4783bfc140396e828..fc57a911465d57ef4808500f026273ef4ec87bc8 100644
--- a/runtime/interpreter/mterp/x86/op_aget.S
+++ b/runtime/interpreter/mterp/x86/op_aget.S
@@ -1,4 +1,4 @@
-%default { "load":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
+%def op_aget(load="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"):
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
diff --git a/runtime/interpreter/mterp/x86/op_aget_boolean.S b/runtime/interpreter/mterp/x86/op_aget_boolean.S
index d910c94e458a5b73a4856513ce18918ff07ce2df..279e6fc73958331e2d3831cd5e50ddac32a81aaf 100644
--- a/runtime/interpreter/mterp/x86/op_aget_boolean.S
+++ b/runtime/interpreter/mterp/x86/op_aget_boolean.S
@@ -1 +1,2 @@
-%include "x86/op_aget.S" { "load":"movzbl", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aget_boolean():
+%  op_aget(load="movzbl", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86/op_aget_byte.S b/runtime/interpreter/mterp/x86/op_aget_byte.S
index aba9ffc25a699e7f7aa31f06c2920b6464a9d1e6..19894507437487dadd2d64f15234a815fc2ff5f8 100644
--- a/runtime/interpreter/mterp/x86/op_aget_byte.S
+++ b/runtime/interpreter/mterp/x86/op_aget_byte.S
@@ -1 +1,2 @@
-%include "x86/op_aget.S" { "load":"movsbl", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aget_byte():
+%  op_aget(load="movsbl", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86/op_aget_char.S b/runtime/interpreter/mterp/x86/op_aget_char.S
index 748e4108b33633eed27e56b68714b023f2f6375c..a35269bd6522bddc452d6e8d26d09f8196941bb4 100644
--- a/runtime/interpreter/mterp/x86/op_aget_char.S
+++ b/runtime/interpreter/mterp/x86/op_aget_char.S
@@ -1 +1,2 @@
-%include "x86/op_aget.S" { "load":"movzwl", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aget_char():
+%  op_aget(load="movzwl", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86/op_aget_object.S b/runtime/interpreter/mterp/x86/op_aget_object.S
index 35ec053854a8c8b049c93b3691f63418e19a232a..4cf90e94a4db41ba16f9721b83b5230d020c942e 100644
--- a/runtime/interpreter/mterp/x86/op_aget_object.S
+++ b/runtime/interpreter/mterp/x86/op_aget_object.S
@@ -1,3 +1,4 @@
+%def op_aget_object():
 /*
  * Array object get.  vAA <- vBB[vCC].
  *
diff --git a/runtime/interpreter/mterp/x86/op_aget_short.S b/runtime/interpreter/mterp/x86/op_aget_short.S
index 6eaf5d922d93dfb64ffa555abcef0136aaddbdbd..ca51ec80522c9196f466605a913b6a7335605025 100644
--- a/runtime/interpreter/mterp/x86/op_aget_short.S
+++ b/runtime/interpreter/mterp/x86/op_aget_short.S
@@ -1 +1,2 @@
-%include "x86/op_aget.S" { "load":"movswl", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aget_short():
+%  op_aget(load="movswl", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86/op_aget_wide.S b/runtime/interpreter/mterp/x86/op_aget_wide.S
index 92c612a25ca4c2c8f52d18456f7f6dba0e2151c3..03cf50a5b8e5cfae187e3971ade92e2663188d18 100644
--- a/runtime/interpreter/mterp/x86/op_aget_wide.S
+++ b/runtime/interpreter/mterp/x86/op_aget_wide.S
@@ -1,3 +1,4 @@
+%def op_aget_wide():
 /*
  * Array get, 64 bits.  vAA <- vBB[vCC].
  */
diff --git a/runtime/interpreter/mterp/x86/op_and_int.S b/runtime/interpreter/mterp/x86/op_and_int.S
index 6272c4e30d032d4f1db75c36fccc14d38822a37b..ffa28d70fa7622a56bde566e978d917c3e71123e 100644
--- a/runtime/interpreter/mterp/x86/op_and_int.S
+++ b/runtime/interpreter/mterp/x86/op_and_int.S
@@ -1 +1,2 @@
-%include "x86/binop.S" {"instr":"andl    (rFP,%ecx,4), %eax"}
+%def op_and_int():
+%  binop(instr="andl    (rFP,%ecx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86/op_and_int_2addr.S b/runtime/interpreter/mterp/x86/op_and_int_2addr.S
index 95df8731719e65583719e43ac0bf0efaef1f6047..8648980c19f6cfcc7cb95b0b4776a8673489c57b 100644
--- a/runtime/interpreter/mterp/x86/op_and_int_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_and_int_2addr.S
@@ -1 +1,2 @@
-%include "x86/binop2addr.S" {"instr":"andl    %eax, (rFP,%ecx,4)"}
+%def op_and_int_2addr():
+%  binop2addr(instr="andl    %eax, (rFP,%ecx,4)")
diff --git a/runtime/interpreter/mterp/x86/op_and_int_lit16.S b/runtime/interpreter/mterp/x86/op_and_int_lit16.S
index b06206410660b8c569d871e652eb5b2c6ebbccbe..d7752b1230b67994aacc6527ca72ea06d06928c9 100644
--- a/runtime/interpreter/mterp/x86/op_and_int_lit16.S
+++ b/runtime/interpreter/mterp/x86/op_and_int_lit16.S
@@ -1 +1,2 @@
-%include "x86/binopLit16.S" {"instr":"andl    %ecx, %eax"}
+%def op_and_int_lit16():
+%  binopLit16(instr="andl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_and_int_lit8.S b/runtime/interpreter/mterp/x86/op_and_int_lit8.S
index 99915dfa304eb9f08a590daefe2a88e075920e5e..a353178a884adce00f5d8dc4703657b83fc60ed2 100644
--- a/runtime/interpreter/mterp/x86/op_and_int_lit8.S
+++ b/runtime/interpreter/mterp/x86/op_and_int_lit8.S
@@ -1 +1,2 @@
-%include "x86/binopLit8.S" {"instr":"andl    %ecx, %eax"}
+%def op_and_int_lit8():
+%  binopLit8(instr="andl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_and_long.S b/runtime/interpreter/mterp/x86/op_and_long.S
index f8514ea802f4fdd25b9ba0e401bde9f333b04ff4..15164aee796e920e5b7a8cbfa7eecf6107023b3f 100644
--- a/runtime/interpreter/mterp/x86/op_and_long.S
+++ b/runtime/interpreter/mterp/x86/op_and_long.S
@@ -1 +1,2 @@
-%include "x86/binopWide.S" {"instr1":"andl    (rFP,%ecx,4), rIBASE", "instr2":"andl    4(rFP,%ecx,4), %eax"}
+%def op_and_long():
+%  binopWide(instr1="andl    (rFP,%ecx,4), rIBASE", instr2="andl    4(rFP,%ecx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86/op_and_long_2addr.S b/runtime/interpreter/mterp/x86/op_and_long_2addr.S
index 37249b8153f2dbf8729b7482d700610535851888..173c159f9867208acdb1c18981e77089a5d67618 100644
--- a/runtime/interpreter/mterp/x86/op_and_long_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_and_long_2addr.S
@@ -1 +1,2 @@
-%include "x86/binopWide2addr.S" {"instr1":"andl    %eax, (rFP,rINST,4)","instr2":"andl    %ecx, 4(rFP,rINST,4)"}
+%def op_and_long_2addr():
+%  binopWide2addr(instr1="andl    %eax, (rFP,rINST,4)", instr2="andl    %ecx, 4(rFP,rINST,4)")
diff --git a/runtime/interpreter/mterp/x86/op_aput.S b/runtime/interpreter/mterp/x86/op_aput.S
index 9d8c52d1273907b24eff570cf614b2337799951f..60bcc5027d086c50d1408a7ad1693b46295e87ec 100644
--- a/runtime/interpreter/mterp/x86/op_aput.S
+++ b/runtime/interpreter/mterp/x86/op_aput.S
@@ -1,4 +1,4 @@
-%default { "reg":"rINST", "store":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
+%def op_aput(reg="rINST", store="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"):
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
diff --git a/runtime/interpreter/mterp/x86/op_aput_boolean.S b/runtime/interpreter/mterp/x86/op_aput_boolean.S
index e7fdd53924d2a637ec7f2493ec745c2a64ccae10..8420b5af8ff4d6d2ec53888b22e6f2859a5b1004 100644
--- a/runtime/interpreter/mterp/x86/op_aput_boolean.S
+++ b/runtime/interpreter/mterp/x86/op_aput_boolean.S
@@ -1 +1,2 @@
-%include "x86/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aput_boolean():
+%  op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86/op_aput_byte.S b/runtime/interpreter/mterp/x86/op_aput_byte.S
index 491d03cd72ca0f6f42ce1f03b30d461dd5f03153..6c181a48d9086e90dba63a4a1cb75f144f00c80d 100644
--- a/runtime/interpreter/mterp/x86/op_aput_byte.S
+++ b/runtime/interpreter/mterp/x86/op_aput_byte.S
@@ -1 +1,2 @@
-%include "x86/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aput_byte():
+%  op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86/op_aput_char.S b/runtime/interpreter/mterp/x86/op_aput_char.S
index ca42cf0c74cca1cb3065f6386141391b6dbfef75..3f4602a7f47d175a054b925515458ef9fa8890f7 100644
--- a/runtime/interpreter/mterp/x86/op_aput_char.S
+++ b/runtime/interpreter/mterp/x86/op_aput_char.S
@@ -1 +1,2 @@
-%include "x86/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aput_char():
+%  op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86/op_aput_object.S b/runtime/interpreter/mterp/x86/op_aput_object.S
index 980b26a40144906627472e1e6995c0773f528096..5d0bb0b894d6624d195e7d6bcc38815d90ff70da 100644
--- a/runtime/interpreter/mterp/x86/op_aput_object.S
+++ b/runtime/interpreter/mterp/x86/op_aput_object.S
@@ -1,3 +1,4 @@
+%def op_aput_object():
 /*
  * Store an object into an array.  vBB[vCC] <- vAA.
  */
diff --git a/runtime/interpreter/mterp/x86/op_aput_short.S b/runtime/interpreter/mterp/x86/op_aput_short.S
index 5e634821cc512ead0c3c649d5586a5578ef3fa8f..e76d83368bf4bd66332e2cdf9eba80d9970814db 100644
--- a/runtime/interpreter/mterp/x86/op_aput_short.S
+++ b/runtime/interpreter/mterp/x86/op_aput_short.S
@@ -1 +1,2 @@
-%include "x86/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aput_short():
+%  op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86/op_aput_wide.S b/runtime/interpreter/mterp/x86/op_aput_wide.S
index 43ef64a54aac03f08b1d987ca1d951beef10e860..c59f7b37aea1c05fbb114a6cb1e2052a050ec927 100644
--- a/runtime/interpreter/mterp/x86/op_aput_wide.S
+++ b/runtime/interpreter/mterp/x86/op_aput_wide.S
@@ -1,3 +1,4 @@
+%def op_aput_wide():
 /*
  * Array put, 64 bits.  vBB[vCC] <- vAA.
  *
diff --git a/runtime/interpreter/mterp/x86/op_array_length.S b/runtime/interpreter/mterp/x86/op_array_length.S
index 60ed80b5413c39ef9a71923277a93b0ba620e955..c9d8930643b0f9b985a355cbd20f199917ac3214 100644
--- a/runtime/interpreter/mterp/x86/op_array_length.S
+++ b/runtime/interpreter/mterp/x86/op_array_length.S
@@ -1,3 +1,4 @@
+%def op_array_length():
 /*
  * Return the length of an array.
  */
diff --git a/runtime/interpreter/mterp/x86/op_check_cast.S b/runtime/interpreter/mterp/x86/op_check_cast.S
index d090aa3785135d1630139d27da9962842ad3ed67..12f854377794bcfa10de3b0f595d1fdc936a180c 100644
--- a/runtime/interpreter/mterp/x86/op_check_cast.S
+++ b/runtime/interpreter/mterp/x86/op_check_cast.S
@@ -1,3 +1,4 @@
+%def op_check_cast():
 /*
  * Check to see if a cast from one class to another is allowed.
  */
diff --git a/runtime/interpreter/mterp/x86/op_cmp_long.S b/runtime/interpreter/mterp/x86/op_cmp_long.S
index 1f729b078e33625f625d39dfef8039aa7b6a58eb..0e33874a33638c3cfd4717a2b495e180f6131202 100644
--- a/runtime/interpreter/mterp/x86/op_cmp_long.S
+++ b/runtime/interpreter/mterp/x86/op_cmp_long.S
@@ -1,3 +1,4 @@
+%def op_cmp_long():
 /*
  * Compare two 64-bit values.  Puts 0, 1, or -1 into the destination
  * register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/x86/op_cmpg_double.S b/runtime/interpreter/mterp/x86/op_cmpg_double.S
index a73ba550d23a5e1a721264068bff5cebb6f840ee..1c04e997f103eb2956adc16d1f21009ea1136b04 100644
--- a/runtime/interpreter/mterp/x86/op_cmpg_double.S
+++ b/runtime/interpreter/mterp/x86/op_cmpg_double.S
@@ -1 +1,2 @@
-%include "x86/fpcmp.S" {"suff":"d","nanval":"pos"}
+%def op_cmpg_double():
+%  fpcmp(suff="d", nanval="pos")
diff --git a/runtime/interpreter/mterp/x86/op_cmpg_float.S b/runtime/interpreter/mterp/x86/op_cmpg_float.S
index 648051b583a7d756f5abc120a1bea6c6ef964d09..797c3d52d74bfc8b7e448ede512e336dc62286ee 100644
--- a/runtime/interpreter/mterp/x86/op_cmpg_float.S
+++ b/runtime/interpreter/mterp/x86/op_cmpg_float.S
@@ -1 +1,2 @@
-%include "x86/fpcmp.S" {"suff":"s","nanval":"pos"}
+%def op_cmpg_float():
+%  fpcmp(suff="s", nanval="pos")
diff --git a/runtime/interpreter/mterp/x86/op_cmpl_double.S b/runtime/interpreter/mterp/x86/op_cmpl_double.S
index 058163e8990d2bea41e0d8b97acdbb6af0da2d5f..cbe8db713ba806f329b6bd891d5bce475337d110 100644
--- a/runtime/interpreter/mterp/x86/op_cmpl_double.S
+++ b/runtime/interpreter/mterp/x86/op_cmpl_double.S
@@ -1 +1,2 @@
-%include "x86/fpcmp.S" {"suff":"d","nanval":"neg"}
+%def op_cmpl_double():
+%  fpcmp(suff="d", nanval="neg")
diff --git a/runtime/interpreter/mterp/x86/op_cmpl_float.S b/runtime/interpreter/mterp/x86/op_cmpl_float.S
index 302f0784755ac155500b4cb707e1b64801034acf..068f4cb5c1f837a1e0edb0aff71bd414b9aa31e5 100644
--- a/runtime/interpreter/mterp/x86/op_cmpl_float.S
+++ b/runtime/interpreter/mterp/x86/op_cmpl_float.S
@@ -1 +1,2 @@
-%include "x86/fpcmp.S" {"suff":"s","nanval":"neg"}
+%def op_cmpl_float():
+%  fpcmp(suff="s", nanval="neg")
diff --git a/runtime/interpreter/mterp/x86/op_const.S b/runtime/interpreter/mterp/x86/op_const.S
index 544d63b22acc540e69f49add0e8984959125124c..dc4342f571e037ff334c04ef820c20b3f2d52c24 100644
--- a/runtime/interpreter/mterp/x86/op_const.S
+++ b/runtime/interpreter/mterp/x86/op_const.S
@@ -1,3 +1,4 @@
+%def op_const():
     /* const vAA, #+BBBBbbbb */
     movl    2(rPC), %eax                    # grab all 32 bits at once
     SET_VREG %eax, rINST                    # vAA<- eax
diff --git a/runtime/interpreter/mterp/x86/op_const_16.S b/runtime/interpreter/mterp/x86/op_const_16.S
index 97cd5faf2fb263cdd61485d21389f82d6a5f8f74..84678ae2a98914354de6cfdbcb0fae0bd03e0d1c 100644
--- a/runtime/interpreter/mterp/x86/op_const_16.S
+++ b/runtime/interpreter/mterp/x86/op_const_16.S
@@ -1,3 +1,4 @@
+%def op_const_16():
     /* const/16 vAA, #+BBBB */
     movswl  2(rPC), %ecx                    # ecx <- ssssBBBB
     SET_VREG %ecx, rINST                    # vAA <- ssssBBBB
diff --git a/runtime/interpreter/mterp/x86/op_const_4.S b/runtime/interpreter/mterp/x86/op_const_4.S
index a60ba96c5a55d0e923186c36befec618afa350c8..8cfd9c096d2c77ed090c7c9d15c32f903d237b9f 100644
--- a/runtime/interpreter/mterp/x86/op_const_4.S
+++ b/runtime/interpreter/mterp/x86/op_const_4.S
@@ -1,3 +1,4 @@
+%def op_const_4():
     /* const/4 vA, #+B */
     movsx   rINSTbl, %eax                   # eax <-ssssssBx
     movl    $$0xf, rINST
diff --git a/runtime/interpreter/mterp/x86/op_const_class.S b/runtime/interpreter/mterp/x86/op_const_class.S
index 71648b5df7014919551922d4a3fc6de7f99a59a2..db12ec31414690de6acb180ce962f6676f3ab2f5 100644
--- a/runtime/interpreter/mterp/x86/op_const_class.S
+++ b/runtime/interpreter/mterp/x86/op_const_class.S
@@ -1 +1,2 @@
-%include "x86/const.S" { "helper":"MterpConstClass" }
+%def op_const_class():
+%  const(helper="MterpConstClass")
diff --git a/runtime/interpreter/mterp/x86/op_const_high16.S b/runtime/interpreter/mterp/x86/op_const_high16.S
index 576967af99f54bd9579fca91c6cf33800eb6367d..5252ba21ba7228ff32c320838e8ed5133400821b 100644
--- a/runtime/interpreter/mterp/x86/op_const_high16.S
+++ b/runtime/interpreter/mterp/x86/op_const_high16.S
@@ -1,3 +1,4 @@
+%def op_const_high16():
     /* const/high16 vAA, #+BBBB0000 */
     movzwl  2(rPC), %eax                    # eax <- 0000BBBB
     sall    $$16, %eax                      # eax <- BBBB0000
diff --git a/runtime/interpreter/mterp/x86/op_const_method_handle.S b/runtime/interpreter/mterp/x86/op_const_method_handle.S
index 77948fd8f9f72bbc6ba7602b0553f9e4bb42451e..2680c17aad5d6f537298bc455177da35df137274 100644
--- a/runtime/interpreter/mterp/x86/op_const_method_handle.S
+++ b/runtime/interpreter/mterp/x86/op_const_method_handle.S
@@ -1 +1,2 @@
-%include "x86/const.S" { "helper":"MterpConstMethodHandle" }
+%def op_const_method_handle():
+%  const(helper="MterpConstMethodHandle")
diff --git a/runtime/interpreter/mterp/x86/op_const_method_type.S b/runtime/interpreter/mterp/x86/op_const_method_type.S
index 03c6ce535063fd7841be9ca582dafa1dd5be6bda..ea814bf64826079ab9f55e43e47f42180c3ad420 100644
--- a/runtime/interpreter/mterp/x86/op_const_method_type.S
+++ b/runtime/interpreter/mterp/x86/op_const_method_type.S
@@ -1 +1,2 @@
-%include "x86/const.S" { "helper":"MterpConstMethodType" }
+%def op_const_method_type():
+%  const(helper="MterpConstMethodType")
diff --git a/runtime/interpreter/mterp/x86/op_const_string.S b/runtime/interpreter/mterp/x86/op_const_string.S
index 5553aab55700c42aec96610903a62b7cb39b0f5f..41376f870340354594a5a218b1d2379e08042008 100644
--- a/runtime/interpreter/mterp/x86/op_const_string.S
+++ b/runtime/interpreter/mterp/x86/op_const_string.S
@@ -1 +1,2 @@
-%include "x86/const.S" { "helper":"MterpConstString" }
+%def op_const_string():
+%  const(helper="MterpConstString")
diff --git a/runtime/interpreter/mterp/x86/op_const_string_jumbo.S b/runtime/interpreter/mterp/x86/op_const_string_jumbo.S
index e7f952a3060e3dca3295e5128a777dca62c62515..dc70c255ce8cf21bcb19faf469bf843b1d399110 100644
--- a/runtime/interpreter/mterp/x86/op_const_string_jumbo.S
+++ b/runtime/interpreter/mterp/x86/op_const_string_jumbo.S
@@ -1,3 +1,4 @@
+%def op_const_string_jumbo():
     /* const/string vAA, String@BBBBBBBB */
     EXPORT_PC
     movl    2(rPC), %eax                    # eax <- BBBB
diff --git a/runtime/interpreter/mterp/x86/op_const_wide.S b/runtime/interpreter/mterp/x86/op_const_wide.S
index 375072812810b193d3e56dcd7d80f0ae2b9973b2..d076e837aa22fb963be343f3b8d83363079e51b4 100644
--- a/runtime/interpreter/mterp/x86/op_const_wide.S
+++ b/runtime/interpreter/mterp/x86/op_const_wide.S
@@ -1,3 +1,4 @@
+%def op_const_wide():
     /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
     movl    2(rPC), %eax                    # eax <- lsw
     movzbl  rINSTbl, %ecx                   # ecx <- AA
diff --git a/runtime/interpreter/mterp/x86/op_const_wide_16.S b/runtime/interpreter/mterp/x86/op_const_wide_16.S
index 1331c329dc929584d7d44fa009f2494eab283a70..328cdeedcedef5456cb263e257d8e4a2e86fe53d 100644
--- a/runtime/interpreter/mterp/x86/op_const_wide_16.S
+++ b/runtime/interpreter/mterp/x86/op_const_wide_16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_16():
     /* const-wide/16 vAA, #+BBBB */
     movswl  2(rPC), %eax                    # eax <- ssssBBBB
     movl    rIBASE, %ecx                    # preserve rIBASE (cltd trashes it)
diff --git a/runtime/interpreter/mterp/x86/op_const_wide_32.S b/runtime/interpreter/mterp/x86/op_const_wide_32.S
index ed7d62b39677142de524dfd7320aaef393d28fd6..c4b5b6714d3e16f0b1adcc8c01ea429f2d9f8ebc 100644
--- a/runtime/interpreter/mterp/x86/op_const_wide_32.S
+++ b/runtime/interpreter/mterp/x86/op_const_wide_32.S
@@ -1,3 +1,4 @@
+%def op_const_wide_32():
     /* const-wide/32 vAA, #+BBBBbbbb */
     movl    2(rPC), %eax                    # eax <- BBBBbbbb
     movl    rIBASE, %ecx                    # preserve rIBASE (cltd trashes it)
diff --git a/runtime/interpreter/mterp/x86/op_const_wide_high16.S b/runtime/interpreter/mterp/x86/op_const_wide_high16.S
index 11b9310be54224c4392ce2550d3732925cd8d307..f99e674ce1b2b7b133c5fe83547af493e4754347 100644
--- a/runtime/interpreter/mterp/x86/op_const_wide_high16.S
+++ b/runtime/interpreter/mterp/x86/op_const_wide_high16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_high16():
     /* const-wide/high16 vAA, #+BBBB000000000000 */
     movzwl  2(rPC), %eax                    # eax <- 0000BBBB
     sall    $$16, %eax                      # eax <- BBBB0000
diff --git a/runtime/interpreter/mterp/x86/op_div_double.S b/runtime/interpreter/mterp/x86/op_div_double.S
index 575716dc9d7ace76ed1ae6b500579e417ab68796..6b342f89bf2e3cf6d25b21509a6785241aba15d3 100644
--- a/runtime/interpreter/mterp/x86/op_div_double.S
+++ b/runtime/interpreter/mterp/x86/op_div_double.S
@@ -1 +1,2 @@
-%include "x86/sseBinop.S" {"instr":"divs","suff":"d"}
+%def op_div_double():
+%  sseBinop(instr="divs", suff="d")
diff --git a/runtime/interpreter/mterp/x86/op_div_double_2addr.S b/runtime/interpreter/mterp/x86/op_div_double_2addr.S
index 8229a31d6740793473ceeff0a36633fdb2c97310..212c82547efa9b8a7eff14bcc6395951827e2748 100644
--- a/runtime/interpreter/mterp/x86/op_div_double_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_div_double_2addr.S
@@ -1 +1,2 @@
-%include "x86/sseBinop2Addr.S" {"instr":"divs","suff":"d"}
+%def op_div_double_2addr():
+%  sseBinop2Addr(instr="divs", suff="d")
diff --git a/runtime/interpreter/mterp/x86/op_div_float.S b/runtime/interpreter/mterp/x86/op_div_float.S
index 250f1dccc6ac7329b8ca3c796af17db5d1c019df..b6537d9d8911c972bd8ec5366495fc85b7f3675e 100644
--- a/runtime/interpreter/mterp/x86/op_div_float.S
+++ b/runtime/interpreter/mterp/x86/op_div_float.S
@@ -1 +1,2 @@
-%include "x86/sseBinop.S" {"instr":"divs","suff":"s"}
+%def op_div_float():
+%  sseBinop(instr="divs", suff="s")
diff --git a/runtime/interpreter/mterp/x86/op_div_float_2addr.S b/runtime/interpreter/mterp/x86/op_div_float_2addr.S
index c30d148356e21e9ddc0bfc812dcbbc71c339c983..19ae27d61aa37ac69120d46f1136ae0d56517776 100644
--- a/runtime/interpreter/mterp/x86/op_div_float_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_div_float_2addr.S
@@ -1 +1,2 @@
-%include "x86/sseBinop2Addr.S" {"instr":"divs","suff":"s"}
+%def op_div_float_2addr():
+%  sseBinop2Addr(instr="divs", suff="s")
diff --git a/runtime/interpreter/mterp/x86/op_div_int.S b/runtime/interpreter/mterp/x86/op_div_int.S
index 5fc8fa519e5b020982a757833bcbbbb92e28ddc6..4df3b927b482fd6503cab31ee5743cda5c0c5144 100644
--- a/runtime/interpreter/mterp/x86/op_div_int.S
+++ b/runtime/interpreter/mterp/x86/op_div_int.S
@@ -1 +1,2 @@
-%include "x86/bindiv.S" {"result":"%eax","special":"$0x80000000","rem":"0"}
+%def op_div_int():
+%  bindiv(result="%eax", special="$0x80000000", rem="0")
diff --git a/runtime/interpreter/mterp/x86/op_div_int_2addr.S b/runtime/interpreter/mterp/x86/op_div_int_2addr.S
index 04cf1bae6a4c12d44c6ee05130429192e4de52f4..d43135f0dd9194c2ce10885ac9ec32f8fa7514a9 100644
--- a/runtime/interpreter/mterp/x86/op_div_int_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_div_int_2addr.S
@@ -1 +1,2 @@
-%include "x86/bindiv2addr.S" {"result":"%eax","special":"$0x80000000"}
+%def op_div_int_2addr():
+%  bindiv2addr(result="%eax", special="$0x80000000")
diff --git a/runtime/interpreter/mterp/x86/op_div_int_lit16.S b/runtime/interpreter/mterp/x86/op_div_int_lit16.S
index dd396bb68a7b74548cc78f22f8f282d02a0da2aa..e561eae38e32c6e8c5c39e66ce9e9999f601011a 100644
--- a/runtime/interpreter/mterp/x86/op_div_int_lit16.S
+++ b/runtime/interpreter/mterp/x86/op_div_int_lit16.S
@@ -1 +1,2 @@
-%include "x86/bindivLit16.S" {"result":"%eax","special":"$0x80000000"}
+%def op_div_int_lit16():
+%  bindivLit16(result="%eax", special="$0x80000000")
diff --git a/runtime/interpreter/mterp/x86/op_div_int_lit8.S b/runtime/interpreter/mterp/x86/op_div_int_lit8.S
index 3cbd9d0cf517f0f595363d1b05959e453153bd43..5facee247e8d6153aca16d8d61a81d381a9f7d0b 100644
--- a/runtime/interpreter/mterp/x86/op_div_int_lit8.S
+++ b/runtime/interpreter/mterp/x86/op_div_int_lit8.S
@@ -1 +1,2 @@
-%include "x86/bindivLit8.S" {"result":"%eax","special":"$0x80000000"}
+%def op_div_int_lit8():
+%  bindivLit8(result="%eax", special="$0x80000000")
diff --git a/runtime/interpreter/mterp/x86/op_div_long.S b/runtime/interpreter/mterp/x86/op_div_long.S
index e56a035f1dc15803244da0b04917e3d015c9dfd0..2fdf6ad1bfe83fb0b9b29b7fc028b1562f0cf055 100644
--- a/runtime/interpreter/mterp/x86/op_div_long.S
+++ b/runtime/interpreter/mterp/x86/op_div_long.S
@@ -1,4 +1,4 @@
-%default {"routine":"art_quick_ldiv"}
+%def op_div_long(routine="art_quick_ldiv"):
 /* art_quick_* methods has quick abi,
  *   so use eax, ecx, edx, ebx for args
  */
diff --git a/runtime/interpreter/mterp/x86/op_div_long_2addr.S b/runtime/interpreter/mterp/x86/op_div_long_2addr.S
index 159cc44444b910c72d85ff52c0e2c02e88b6ac69..b3d81a45801419b718c33501537982d7c4f6dfae 100644
--- a/runtime/interpreter/mterp/x86/op_div_long_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_div_long_2addr.S
@@ -1,4 +1,4 @@
-%default {"routine":"art_quick_ldiv"}
+%def op_div_long_2addr(routine="art_quick_ldiv"):
 /* art_quick_* methods has quick abi,
  *   so use eax, ecx, edx, ebx for args
  */
diff --git a/runtime/interpreter/mterp/x86/op_double_to_float.S b/runtime/interpreter/mterp/x86/op_double_to_float.S
index 5135d60ed7244d4a99b7abd5e0c59e1deb9caeab..a52b505368bc7b22c080eb4af34e2402b7b233f6 100644
--- a/runtime/interpreter/mterp/x86/op_double_to_float.S
+++ b/runtime/interpreter/mterp/x86/op_double_to_float.S
@@ -1 +1,2 @@
-%include "x86/fpcvt.S" {"load":"fldl","store":"fstps"}
+%def op_double_to_float():
+%  fpcvt(load="fldl", store="fstps")
diff --git a/runtime/interpreter/mterp/x86/op_double_to_int.S b/runtime/interpreter/mterp/x86/op_double_to_int.S
index 9c4e11cf9e122a559212f101b67d3a8fef161ef6..65c31fbf5e1564afb88dc24c845d0619ba629b95 100644
--- a/runtime/interpreter/mterp/x86/op_double_to_int.S
+++ b/runtime/interpreter/mterp/x86/op_double_to_int.S
@@ -1 +1,2 @@
-%include "x86/cvtfp_int.S" {"srcdouble":"1","tgtlong":"0"}
+%def op_double_to_int():
+%  cvtfp_int(srcdouble="1", tgtlong="0")
diff --git a/runtime/interpreter/mterp/x86/op_double_to_long.S b/runtime/interpreter/mterp/x86/op_double_to_long.S
index fe0eee24d0a294a65abfa9cb4986befcc80cba31..1eb74bf5394415e221b44ef4919eaab57ca213dd 100644
--- a/runtime/interpreter/mterp/x86/op_double_to_long.S
+++ b/runtime/interpreter/mterp/x86/op_double_to_long.S
@@ -1 +1,2 @@
-%include "x86/cvtfp_int.S" {"srcdouble":"1","tgtlong":"1"}
+%def op_double_to_long():
+%  cvtfp_int(srcdouble="1", tgtlong="1")
diff --git a/runtime/interpreter/mterp/x86/op_fill_array_data.S b/runtime/interpreter/mterp/x86/op_fill_array_data.S
index 585528490122d6a71fb74f02ac4fb10c4840c07d..f121787f62faf4a4b9d57711b0edfa269c259488 100644
--- a/runtime/interpreter/mterp/x86/op_fill_array_data.S
+++ b/runtime/interpreter/mterp/x86/op_fill_array_data.S
@@ -1,3 +1,4 @@
+%def op_fill_array_data():
     /* fill-array-data vAA, +BBBBBBBB */
     EXPORT_PC
     movl    2(rPC), %ecx                    # ecx <- BBBBbbbb
diff --git a/runtime/interpreter/mterp/x86/op_filled_new_array.S b/runtime/interpreter/mterp/x86/op_filled_new_array.S
index 35b2fe8dfc9f765bb4cf9bfa39ed77b427ca829e..8e5bd03978b8a27ca07e016578f5e871a2bc3843 100644
--- a/runtime/interpreter/mterp/x86/op_filled_new_array.S
+++ b/runtime/interpreter/mterp/x86/op_filled_new_array.S
@@ -1,4 +1,4 @@
-%default { "helper":"MterpFilledNewArray" }
+%def op_filled_new_array(helper="MterpFilledNewArray"):
 /*
  * Create a new array with elements filled from registers.
  *
diff --git a/runtime/interpreter/mterp/x86/op_filled_new_array_range.S b/runtime/interpreter/mterp/x86/op_filled_new_array_range.S
index 841059e4e210314320cf62f6b7acce60f3de9059..1667de149ace0bdaaafcd36c43724422682df424 100644
--- a/runtime/interpreter/mterp/x86/op_filled_new_array_range.S
+++ b/runtime/interpreter/mterp/x86/op_filled_new_array_range.S
@@ -1 +1,2 @@
-%include "x86/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" }
+%def op_filled_new_array_range():
+%  op_filled_new_array(helper="MterpFilledNewArrayRange")
diff --git a/runtime/interpreter/mterp/x86/op_float_to_double.S b/runtime/interpreter/mterp/x86/op_float_to_double.S
index 12a3e14caa86f68da9516a09ba12a3d64790a61e..152bb0085976ea6f5a6dbf180f23f7d38225183a 100644
--- a/runtime/interpreter/mterp/x86/op_float_to_double.S
+++ b/runtime/interpreter/mterp/x86/op_float_to_double.S
@@ -1 +1,2 @@
-%include "x86/fpcvt.S" {"load":"flds","store":"fstpl","wide":"1"}
+%def op_float_to_double():
+%  fpcvt(load="flds", store="fstpl", wide="1")
diff --git a/runtime/interpreter/mterp/x86/op_float_to_int.S b/runtime/interpreter/mterp/x86/op_float_to_int.S
index ac57388744ccdaca71a344d8fa67736f34a500c9..1f8e5cc1e582f525424494ee30ae4dbf7a5e712e 100644
--- a/runtime/interpreter/mterp/x86/op_float_to_int.S
+++ b/runtime/interpreter/mterp/x86/op_float_to_int.S
@@ -1 +1,2 @@
-%include "x86/cvtfp_int.S" {"srcdouble":"0","tgtlong":"0"}
+%def op_float_to_int():
+%  cvtfp_int(srcdouble="0", tgtlong="0")
diff --git a/runtime/interpreter/mterp/x86/op_float_to_long.S b/runtime/interpreter/mterp/x86/op_float_to_long.S
index be1d9821b3271f07ce28df266271ccca0a543a2a..a0567691c2c7dd96745c4b9fcb8eb79234b65d67 100644
--- a/runtime/interpreter/mterp/x86/op_float_to_long.S
+++ b/runtime/interpreter/mterp/x86/op_float_to_long.S
@@ -1 +1,2 @@
-%include "x86/cvtfp_int.S" {"srcdouble":"0","tgtlong":"1"}
+%def op_float_to_long():
+%  cvtfp_int(srcdouble="0", tgtlong="1")
diff --git a/runtime/interpreter/mterp/x86/op_goto.S b/runtime/interpreter/mterp/x86/op_goto.S
index 1827d68eed11f5a0436955a7d021460446bf2efb..b6236fe9a8ff9ad347e7602557d31d85b1420c03 100644
--- a/runtime/interpreter/mterp/x86/op_goto.S
+++ b/runtime/interpreter/mterp/x86/op_goto.S
@@ -1,3 +1,4 @@
+%def op_goto():
 /*
  * Unconditional branch, 8-bit offset.
  *
diff --git a/runtime/interpreter/mterp/x86/op_goto_16.S b/runtime/interpreter/mterp/x86/op_goto_16.S
index ea5ea9001fc848e89cf3d538e2aa316d9b9d4f51..a8c2bf590d61839735f4259f982c17e66537f3ce 100644
--- a/runtime/interpreter/mterp/x86/op_goto_16.S
+++ b/runtime/interpreter/mterp/x86/op_goto_16.S
@@ -1,3 +1,4 @@
+%def op_goto_16():
 /*
  * Unconditional branch, 16-bit offset.
  *
diff --git a/runtime/interpreter/mterp/x86/op_goto_32.S b/runtime/interpreter/mterp/x86/op_goto_32.S
index 4becaf34b1d64b6ba2d66b15e0ed54c14e663138..87d0e338e06400d957ea448357990ea875de6126 100644
--- a/runtime/interpreter/mterp/x86/op_goto_32.S
+++ b/runtime/interpreter/mterp/x86/op_goto_32.S
@@ -1,3 +1,4 @@
+%def op_goto_32():
 /*
  * Unconditional branch, 32-bit offset.
  *
diff --git a/runtime/interpreter/mterp/x86/op_if_eq.S b/runtime/interpreter/mterp/x86/op_if_eq.S
index 5413d98580820739ae23c4f9cf1690ed8391f53d..4d1f6a54d2f6f2701623f8f79e910da73b8c4bcd 100644
--- a/runtime/interpreter/mterp/x86/op_if_eq.S
+++ b/runtime/interpreter/mterp/x86/op_if_eq.S
@@ -1 +1,2 @@
-%include "x86/bincmp.S" { "revcmp":"ne" }
+%def op_if_eq():
+%  bincmp(revcmp="ne")
diff --git a/runtime/interpreter/mterp/x86/op_if_eqz.S b/runtime/interpreter/mterp/x86/op_if_eqz.S
index 53dc99ef9051351cd1a0e6b2b08f020181f4a695..12de5585506ffd994b0e3bcf0eeaf3f49e88c000 100644
--- a/runtime/interpreter/mterp/x86/op_if_eqz.S
+++ b/runtime/interpreter/mterp/x86/op_if_eqz.S
@@ -1 +1,2 @@
-%include "x86/zcmp.S" { "revcmp":"ne" }
+%def op_if_eqz():
+%  zcmp(revcmp="ne")
diff --git a/runtime/interpreter/mterp/x86/op_if_ge.S b/runtime/interpreter/mterp/x86/op_if_ge.S
index c2ba3c6d5187b4c07156c713e8bf52f9bce29f09..684902776f0c93ab9990f02a7fb3515228a968d3 100644
--- a/runtime/interpreter/mterp/x86/op_if_ge.S
+++ b/runtime/interpreter/mterp/x86/op_if_ge.S
@@ -1 +1,2 @@
-%include "x86/bincmp.S" { "revcmp":"l" }
+%def op_if_ge():
+%  bincmp(revcmp="l")
diff --git a/runtime/interpreter/mterp/x86/op_if_gez.S b/runtime/interpreter/mterp/x86/op_if_gez.S
index cd2c77237d8fb0689ddcfb269c4b3e89c0334fe1..87bdcbfa326470703ea928ff91bc6ac6b9d0e876 100644
--- a/runtime/interpreter/mterp/x86/op_if_gez.S
+++ b/runtime/interpreter/mterp/x86/op_if_gez.S
@@ -1 +1,2 @@
-%include "x86/zcmp.S" { "revcmp":"l" }
+%def op_if_gez():
+%  zcmp(revcmp="l")
diff --git a/runtime/interpreter/mterp/x86/op_if_gt.S b/runtime/interpreter/mterp/x86/op_if_gt.S
index 9fe84bb786ecc6f7eca50498954e8911ed563816..4a521006b3a8028a624a2f7cf633da031cb313da 100644
--- a/runtime/interpreter/mterp/x86/op_if_gt.S
+++ b/runtime/interpreter/mterp/x86/op_if_gt.S
@@ -1 +1,2 @@
-%include "x86/bincmp.S" { "revcmp":"le" }
+%def op_if_gt():
+%  bincmp(revcmp="le")
diff --git a/runtime/interpreter/mterp/x86/op_if_gtz.S b/runtime/interpreter/mterp/x86/op_if_gtz.S
index b454ffdb34b1c7317b2438f03e4c89fd96a0db0a..a0b2e3a35bf284dc0218e692b1669b14318c7c3a 100644
--- a/runtime/interpreter/mterp/x86/op_if_gtz.S
+++ b/runtime/interpreter/mterp/x86/op_if_gtz.S
@@ -1 +1,2 @@
-%include "x86/zcmp.S" { "revcmp":"le" }
+%def op_if_gtz():
+%  zcmp(revcmp="le")
diff --git a/runtime/interpreter/mterp/x86/op_if_le.S b/runtime/interpreter/mterp/x86/op_if_le.S
index 93571a7083a71578b04e971d65277140246ae658..69e94db79faa4ae1b4c62b9332fb7d20378e40d4 100644
--- a/runtime/interpreter/mterp/x86/op_if_le.S
+++ b/runtime/interpreter/mterp/x86/op_if_le.S
@@ -1 +1,2 @@
-%include "x86/bincmp.S" { "revcmp":"g" }
+%def op_if_le():
+%  bincmp(revcmp="g")
diff --git a/runtime/interpreter/mterp/x86/op_if_lez.S b/runtime/interpreter/mterp/x86/op_if_lez.S
index 779c77f2be792a5340d70b30b89049008a58394a..42e69d969ad81e1804ad2cb72bc16ef0e3b77542 100644
--- a/runtime/interpreter/mterp/x86/op_if_lez.S
+++ b/runtime/interpreter/mterp/x86/op_if_lez.S
@@ -1 +1,2 @@
-%include "x86/zcmp.S" { "revcmp":"g" }
+%def op_if_lez():
+%  zcmp(revcmp="g")
diff --git a/runtime/interpreter/mterp/x86/op_if_lt.S b/runtime/interpreter/mterp/x86/op_if_lt.S
index 1fb15210548490780072f1a27b4bc1c0f6497800..052aabe1e74070c2eb42cdfe48c166fe27fde50d 100644
--- a/runtime/interpreter/mterp/x86/op_if_lt.S
+++ b/runtime/interpreter/mterp/x86/op_if_lt.S
@@ -1 +1,2 @@
-%include "x86/bincmp.S" { "revcmp":"ge" }
+%def op_if_lt():
+%  bincmp(revcmp="ge")
diff --git a/runtime/interpreter/mterp/x86/op_if_ltz.S b/runtime/interpreter/mterp/x86/op_if_ltz.S
index 155c356e4c98f72ac4daa7f74c0957becba45736..8e13e48c2a476d6bfa6f40821545bafc7cb95baf 100644
--- a/runtime/interpreter/mterp/x86/op_if_ltz.S
+++ b/runtime/interpreter/mterp/x86/op_if_ltz.S
@@ -1 +1,2 @@
-%include "x86/zcmp.S" { "revcmp":"ge" }
+%def op_if_ltz():
+%  zcmp(revcmp="ge")
diff --git a/runtime/interpreter/mterp/x86/op_if_ne.S b/runtime/interpreter/mterp/x86/op_if_ne.S
index 7e1b065fc09ae9face8b01be86e1c1c03c2dfe65..2cfd8a9a1e8e49ae10af479a9f54d77eb07626fe 100644
--- a/runtime/interpreter/mterp/x86/op_if_ne.S
+++ b/runtime/interpreter/mterp/x86/op_if_ne.S
@@ -1 +1,2 @@
-%include "x86/bincmp.S" { "revcmp":"e" }
+%def op_if_ne():
+%  bincmp(revcmp="e")
diff --git a/runtime/interpreter/mterp/x86/op_if_nez.S b/runtime/interpreter/mterp/x86/op_if_nez.S
index 8951f5b19fe444c9710c1488c9c5595746800a4d..261a173a38b3816ab812c55e14fd02b0961e345f 100644
--- a/runtime/interpreter/mterp/x86/op_if_nez.S
+++ b/runtime/interpreter/mterp/x86/op_if_nez.S
@@ -1 +1,2 @@
-%include "x86/zcmp.S" { "revcmp":"e" }
+%def op_if_nez():
+%  zcmp(revcmp="e")
diff --git a/runtime/interpreter/mterp/x86/op_iget.S b/runtime/interpreter/mterp/x86/op_iget.S
index d85d54c51522b1ecd9a1c2bb66e741f9b0d2cb43..d09edc0a17c38245736a29f1cf55eb6f5272b87d 100644
--- a/runtime/interpreter/mterp/x86/op_iget.S
+++ b/runtime/interpreter/mterp/x86/op_iget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIGetU32"}
-%include "x86/field.S" { }
+%def op_iget(is_object="0", helper="MterpIGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/x86/op_iget_boolean.S b/runtime/interpreter/mterp/x86/op_iget_boolean.S
index ddccc41cda9ff92bc2e98153ad8037adb8bcd4b1..cb8edeec773fb6468b5c331b435e409da634f505 100644
--- a/runtime/interpreter/mterp/x86/op_iget_boolean.S
+++ b/runtime/interpreter/mterp/x86/op_iget_boolean.S
@@ -1 +1,2 @@
-%include "x86/op_iget.S" { "helper":"MterpIGetU8" }
+%def op_iget_boolean():
+%  op_iget(helper="MterpIGetU8")
diff --git a/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S b/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S
index 02b0c16cf2c2d727c2e469c17c1ceb6cc9f8299c..4e1676844b0d67ac7212c0d5a14591549bc92535 100644
--- a/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S
@@ -1 +1,2 @@
-%include "x86/op_iget_quick.S" { "load":"movsbl" }
+%def op_iget_boolean_quick():
+%  op_iget_quick(load="movsbl")
diff --git a/runtime/interpreter/mterp/x86/op_iget_byte.S b/runtime/interpreter/mterp/x86/op_iget_byte.S
index cd46d3de082877f28ff5f1dda6b430f8bea68274..2b87fb16b560430baefa05d3f6e20195cb963d23 100644
--- a/runtime/interpreter/mterp/x86/op_iget_byte.S
+++ b/runtime/interpreter/mterp/x86/op_iget_byte.S
@@ -1 +1,2 @@
-%include "x86/op_iget.S" { "helper":"MterpIGetI8" }
+%def op_iget_byte():
+%  op_iget(helper="MterpIGetI8")
diff --git a/runtime/interpreter/mterp/x86/op_iget_byte_quick.S b/runtime/interpreter/mterp/x86/op_iget_byte_quick.S
index 02b0c16cf2c2d727c2e469c17c1ceb6cc9f8299c..b92936c28dcff04ec8c75086cf3c2bdadffbba1c 100644
--- a/runtime/interpreter/mterp/x86/op_iget_byte_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iget_byte_quick.S
@@ -1 +1,2 @@
-%include "x86/op_iget_quick.S" { "load":"movsbl" }
+%def op_iget_byte_quick():
+%  op_iget_quick(load="movsbl")
diff --git a/runtime/interpreter/mterp/x86/op_iget_char.S b/runtime/interpreter/mterp/x86/op_iget_char.S
index 99697349aebad51fa0df6ac17a43107a292956be..001bd03e2b85edc215b29789ba4fc55044b4a230 100644
--- a/runtime/interpreter/mterp/x86/op_iget_char.S
+++ b/runtime/interpreter/mterp/x86/op_iget_char.S
@@ -1 +1,2 @@
-%include "x86/op_iget.S" { "helper":"MterpIGetU16" }
+%def op_iget_char():
+%  op_iget(helper="MterpIGetU16")
diff --git a/runtime/interpreter/mterp/x86/op_iget_char_quick.S b/runtime/interpreter/mterp/x86/op_iget_char_quick.S
index a5d971278d6a4d4c7b66d341fd7f7927c3ce9bae..d6f836b28e7c02f8a8265cc92e4c5205389b46ba 100644
--- a/runtime/interpreter/mterp/x86/op_iget_char_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iget_char_quick.S
@@ -1 +1,2 @@
-%include "x86/op_iget_quick.S" { "load":"movzwl" }
+%def op_iget_char_quick():
+%  op_iget_quick(load="movzwl")
diff --git a/runtime/interpreter/mterp/x86/op_iget_object.S b/runtime/interpreter/mterp/x86/op_iget_object.S
index 3d421fcf7fb2919d55074f325593bededa67db0b..4e5f769547b494ed962728edba2d102a106b332a 100644
--- a/runtime/interpreter/mterp/x86/op_iget_object.S
+++ b/runtime/interpreter/mterp/x86/op_iget_object.S
@@ -1 +1,2 @@
-%include "x86/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" }
+%def op_iget_object():
+%  op_iget(is_object="1", helper="MterpIGetObj")
diff --git a/runtime/interpreter/mterp/x86/op_iget_object_quick.S b/runtime/interpreter/mterp/x86/op_iget_object_quick.S
index b1551a01795021de057e28000cb8e8079e1761f5..66340e91d26fe5ee2083ea100dffb1046ae8b09a 100644
--- a/runtime/interpreter/mterp/x86/op_iget_object_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iget_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iget_object_quick():
     /* For: iget-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
diff --git a/runtime/interpreter/mterp/x86/op_iget_quick.S b/runtime/interpreter/mterp/x86/op_iget_quick.S
index 1b7440fc9ad6a585224df206e50b0d6a9ed39bc2..8ca2c86f3f272447c778a0d4d00518d51e65aaf8 100644
--- a/runtime/interpreter/mterp/x86/op_iget_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iget_quick.S
@@ -1,4 +1,4 @@
-%default { "load":"movl"}
+%def op_iget_quick(load="movl"):
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
diff --git a/runtime/interpreter/mterp/x86/op_iget_short.S b/runtime/interpreter/mterp/x86/op_iget_short.S
index c7477f5db34f894ac6ad0f888217a2d8a023d561..a62c4d998f1d05ed2a3bb1c2f2bf2cca501dfdb8 100644
--- a/runtime/interpreter/mterp/x86/op_iget_short.S
+++ b/runtime/interpreter/mterp/x86/op_iget_short.S
@@ -1 +1,2 @@
-%include "x86/op_iget.S" { "helper":"MterpIGetI16" }
+%def op_iget_short():
+%  op_iget(helper="MterpIGetI16")
diff --git a/runtime/interpreter/mterp/x86/op_iget_short_quick.S b/runtime/interpreter/mterp/x86/op_iget_short_quick.S
index 2c3aeb67eb45e79a438edcb9bc93ae9aedaebb8e..f5e48d621a36ad2d2ac8f6e9bde807755dd7a955 100644
--- a/runtime/interpreter/mterp/x86/op_iget_short_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iget_short_quick.S
@@ -1 +1,2 @@
-%include "x86/op_iget_quick.S" { "load":"movswl" }
+%def op_iget_short_quick():
+%  op_iget_quick(load="movswl")
diff --git a/runtime/interpreter/mterp/x86/op_iget_wide.S b/runtime/interpreter/mterp/x86/op_iget_wide.S
index 741a64e4cb7e3ac897919b16b2f142e0ec97c163..9643cc340313b657f2485df521ed0ee0cba25f7b 100644
--- a/runtime/interpreter/mterp/x86/op_iget_wide.S
+++ b/runtime/interpreter/mterp/x86/op_iget_wide.S
@@ -1 +1,2 @@
-%include "x86/op_iget.S" { "helper":"MterpIGetU64" }
+%def op_iget_wide():
+%  op_iget(helper="MterpIGetU64")
diff --git a/runtime/interpreter/mterp/x86/op_iget_wide_quick.S b/runtime/interpreter/mterp/x86/op_iget_wide_quick.S
index 7ce74cc71bf332b1d89cbde41d3e816290a325a8..c1a13269f328c865ff76fe086ec48f51ae6c7432 100644
--- a/runtime/interpreter/mterp/x86/op_iget_wide_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iget_wide_quick.S
@@ -1,3 +1,4 @@
+%def op_iget_wide_quick():
     /* iget-wide-quick vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
     sarl    $$4, %ecx                       # ecx <- B
diff --git a/runtime/interpreter/mterp/x86/op_instance_of.S b/runtime/interpreter/mterp/x86/op_instance_of.S
index e6fe5b2cecf694d90e73b7500ff1da65126df94f..ae1afae855aab7f294e88170028cda9cc7c4e120 100644
--- a/runtime/interpreter/mterp/x86/op_instance_of.S
+++ b/runtime/interpreter/mterp/x86/op_instance_of.S
@@ -1,3 +1,4 @@
+%def op_instance_of():
 /*
  * Check to see if an object reference is an instance of a class.
  *
diff --git a/runtime/interpreter/mterp/x86/op_int_to_byte.S b/runtime/interpreter/mterp/x86/op_int_to_byte.S
index b4e8d22c98d1289e8ff93e2011c6abefa2b6814b..80e4d5c3105a170b703ea8761b2873d81f03e5fd 100644
--- a/runtime/interpreter/mterp/x86/op_int_to_byte.S
+++ b/runtime/interpreter/mterp/x86/op_int_to_byte.S
@@ -1 +1,2 @@
-%include "x86/unop.S" {"instr":"movsbl  %al, %eax"}
+%def op_int_to_byte():
+%  unop(instr="movsbl  %al, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_int_to_char.S b/runtime/interpreter/mterp/x86/op_int_to_char.S
index 4608971469f9c8e17edb03ad8ec9bde89312269a..83e9868ef31ad71e61832596a8f98d7eb53fd375 100644
--- a/runtime/interpreter/mterp/x86/op_int_to_char.S
+++ b/runtime/interpreter/mterp/x86/op_int_to_char.S
@@ -1 +1,2 @@
-%include "x86/unop.S" {"instr":"movzwl  %ax,%eax"}
+%def op_int_to_char():
+%  unop(instr="movzwl  %ax,%eax")
diff --git a/runtime/interpreter/mterp/x86/op_int_to_double.S b/runtime/interpreter/mterp/x86/op_int_to_double.S
index 3e9921eb8f83d4f05e3e6111ddb6bdcabdca9856..e304d8eaf59533ef39fb496279cf9d95fc0bf3dd 100644
--- a/runtime/interpreter/mterp/x86/op_int_to_double.S
+++ b/runtime/interpreter/mterp/x86/op_int_to_double.S
@@ -1 +1,2 @@
-%include "x86/fpcvt.S" {"load":"fildl","store":"fstpl","wide":"1"}
+%def op_int_to_double():
+%  fpcvt(load="fildl", store="fstpl", wide="1")
diff --git a/runtime/interpreter/mterp/x86/op_int_to_float.S b/runtime/interpreter/mterp/x86/op_int_to_float.S
index 849540da09cbcaabbe8960c07726c3c5d0a2883a..fe00097c697ed6f693393a2e211ff78b17338c45 100644
--- a/runtime/interpreter/mterp/x86/op_int_to_float.S
+++ b/runtime/interpreter/mterp/x86/op_int_to_float.S
@@ -1 +1,2 @@
-%include "x86/fpcvt.S" {"load":"fildl","store":"fstps"}
+%def op_int_to_float():
+%  fpcvt(load="fildl", store="fstps")
diff --git a/runtime/interpreter/mterp/x86/op_int_to_long.S b/runtime/interpreter/mterp/x86/op_int_to_long.S
index 6f9ea269f4ddccbe30b0b942b957f730fe0e970a..849197382f0361d7888196161063b71eb1106a5f 100644
--- a/runtime/interpreter/mterp/x86/op_int_to_long.S
+++ b/runtime/interpreter/mterp/x86/op_int_to_long.S
@@ -1,3 +1,4 @@
+%def op_int_to_long():
     /* int to long vA, vB */
     movzbl  rINSTbl, %eax                   # eax <- +A
     sarl    $$4, %eax                       # eax <- B
diff --git a/runtime/interpreter/mterp/x86/op_int_to_short.S b/runtime/interpreter/mterp/x86/op_int_to_short.S
index 90d0ae65b1da895dcc36e56fcdb2649038427776..e4db90b8013cec280138cab7c055b4d2b80110f1 100644
--- a/runtime/interpreter/mterp/x86/op_int_to_short.S
+++ b/runtime/interpreter/mterp/x86/op_int_to_short.S
@@ -1 +1,2 @@
-%include "x86/unop.S" {"instr":"movswl %ax, %eax"}
+%def op_int_to_short():
+%  unop(instr="movswl %ax, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_custom.S b/runtime/interpreter/mterp/x86/op_invoke_custom.S
index eddd5b33a329cb5b095b4eb0e232a03000f23686..4bba9ee5241061aa29e63ea32bb9d575e34286ea 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_custom.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_custom.S
@@ -1 +1,2 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeCustom" }
+%def op_invoke_custom():
+%  invoke(helper="MterpInvokeCustom")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_custom_range.S b/runtime/interpreter/mterp/x86/op_invoke_custom_range.S
index 1a4e884166b9eaa8e2404d3ae0cd52ca8fac1e12..57e61af1fa860d814a9da1eaab56b25f199771aa 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_custom_range.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_custom_range.S
@@ -1 +1,2 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeCustomRange" }
+%def op_invoke_custom_range():
+%  invoke(helper="MterpInvokeCustomRange")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_direct.S b/runtime/interpreter/mterp/x86/op_invoke_direct.S
index 76fb9a6786db01ef130616773ae418e28f242f75..d3139cf39b42aca474e7d18dcf526e32e80ced85 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_direct.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_direct.S
@@ -1 +1,2 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeDirect" }
+%def op_invoke_direct():
+%  invoke(helper="MterpInvokeDirect")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_direct_range.S b/runtime/interpreter/mterp/x86/op_invoke_direct_range.S
index a6ab6049f537d65db8d9d141fe3f2a7ee72f5357..b4a161f48bf8b90b0561e577cdf35f27feb71f23 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_direct_range.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_direct_range.S
@@ -1 +1,2 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeDirectRange" }
+%def op_invoke_direct_range():
+%  invoke(helper="MterpInvokeDirectRange")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_interface.S b/runtime/interpreter/mterp/x86/op_invoke_interface.S
index 91c24f5db63887039333ee3ce4ca82d95a6bfdc8..559b9768d9c0c7c8d93c348115c83d1821e35ded 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_interface.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_interface.S
@@ -1,4 +1,5 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeInterface" }
+%def op_invoke_interface():
+%  invoke(helper="MterpInvokeInterface")
 /*
  * Handle an interface method call.
  *
diff --git a/runtime/interpreter/mterp/x86/op_invoke_interface_range.S b/runtime/interpreter/mterp/x86/op_invoke_interface_range.S
index e478beb596dedcacb85458e3b8f36efd76f5118f..298911537760c27944307413bb6bbc1a686768a5 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_interface_range.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_interface_range.S
@@ -1 +1,2 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeInterfaceRange" }
+%def op_invoke_interface_range():
+%  invoke(helper="MterpInvokeInterfaceRange")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S b/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S
index 3907689476c28a01166a0d90ddd00c197c19cffa..ce61f5aa0e6039481359af9e0d7de053a159fc79 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S
@@ -1 +1,2 @@
-%include "x86/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" }
+%def op_invoke_polymorphic():
+%  invoke_polymorphic(helper="MterpInvokePolymorphic")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S
index 59a823076dec67ef102f056568bec30fb83f14ff..16731bdb4040829bf0020b8524b4f70866b1f1e8 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S
@@ -1 +1,2 @@
-%include "x86/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" }
+%def op_invoke_polymorphic_range():
+%  invoke_polymorphic(helper="MterpInvokePolymorphicRange")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_static.S b/runtime/interpreter/mterp/x86/op_invoke_static.S
index b4c1236f7a3b77a1b6c512c0759aa19a3aa752a3..3e38d36a27a20c1d0f1481b80d6585a43343b6cb 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_static.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_static.S
@@ -1,2 +1,3 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeStatic" }
+%def op_invoke_static():
+%  invoke(helper="MterpInvokeStatic")
 
diff --git a/runtime/interpreter/mterp/x86/op_invoke_static_range.S b/runtime/interpreter/mterp/x86/op_invoke_static_range.S
index 3dc8a26856b794d15898932108cb67d51d4e4647..e0a546c92b4be72a4a5040d03e0018b1b248f536 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_static_range.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_static_range.S
@@ -1 +1,2 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeStaticRange" }
+%def op_invoke_static_range():
+%  invoke(helper="MterpInvokeStaticRange")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_super.S b/runtime/interpreter/mterp/x86/op_invoke_super.S
index be20edd07c0c468c2b252cfce86622770db4f76e..5b2055010efc04b9c5a25b98bfbbded2238ff615 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_super.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_super.S
@@ -1,4 +1,5 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeSuper" }
+%def op_invoke_super():
+%  invoke(helper="MterpInvokeSuper")
 /*
  * Handle a "super" method call.
  *
diff --git a/runtime/interpreter/mterp/x86/op_invoke_super_range.S b/runtime/interpreter/mterp/x86/op_invoke_super_range.S
index f36bf72bcfa8af7538f1a0d91d31491a1608ecf0..caeafaa13c91fddf7dd3751252e4daf3045dcd2e 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_super_range.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_super_range.S
@@ -1 +1,2 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeSuperRange" }
+%def op_invoke_super_range():
+%  invoke(helper="MterpInvokeSuperRange")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual.S b/runtime/interpreter/mterp/x86/op_invoke_virtual.S
index 7e9c456a95f83bd840ef4c8b5dfa2e8997666604..e27eeedacc335c0a428ee0155fbafe1e8fce37da 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_virtual.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_virtual.S
@@ -1,4 +1,5 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeVirtual" }
+%def op_invoke_virtual():
+%  invoke(helper="MterpInvokeVirtual")
 /*
  * Handle a virtual method call.
  *
diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S
index 2dc9ab6298df635ebb95ef816a53bebf8b644437..ea72c171ecfedd9ddb94bc2e2202e2c56ab11e53 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S
@@ -1 +1,2 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeVirtualQuick" }
+%def op_invoke_virtual_quick():
+%  invoke(helper="MterpInvokeVirtualQuick")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S
index d1d20d29ac7f9bb745c7b78b0bf51125f768fdc5..baa077959359e0dcfbfd3b3cd9814c31b3f6d727 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S
@@ -1 +1,2 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeVirtualRange" }
+%def op_invoke_virtual_range():
+%  invoke(helper="MterpInvokeVirtualRange")
diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S
index 21bfc55b731e57f17fb9e38f2bd1fac5cb5bee11..1d961a0781a94d0087847bce02fcae1f37a75f29 100644
--- a/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S
+++ b/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S
@@ -1 +1,2 @@
-%include "x86/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" }
+%def op_invoke_virtual_range_quick():
+%  invoke(helper="MterpInvokeVirtualQuickRange")
diff --git a/runtime/interpreter/mterp/x86/op_iput.S b/runtime/interpreter/mterp/x86/op_iput.S
index 3628ffdb56ef0bbdc184e8cce24fc26aae0ed1df..e5351baf557fe295afb718387a6de58585ba5184 100644
--- a/runtime/interpreter/mterp/x86/op_iput.S
+++ b/runtime/interpreter/mterp/x86/op_iput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIPutU32" }
-%include "x86/field.S" { }
+%def op_iput(is_object="0", helper="MterpIPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/x86/op_iput_boolean.S b/runtime/interpreter/mterp/x86/op_iput_boolean.S
index fdd530374e2053255eda4fa724fb0042d2d3ad79..9eb849877b6207d46a36c083b47c83ebbd7e5d00 100644
--- a/runtime/interpreter/mterp/x86/op_iput_boolean.S
+++ b/runtime/interpreter/mterp/x86/op_iput_boolean.S
@@ -1 +1,2 @@
-%include "x86/op_iput.S" { "helper":"MterpIPutU8" }
+%def op_iput_boolean():
+%  op_iput(helper="MterpIPutU8")
diff --git a/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S b/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S
index 93865de169c965d8104563a215267ca2f8b6ae05..c304c76b519bf83014b21fb9219fbe07b7b81105 100644
--- a/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S
@@ -1 +1,2 @@
-%include "x86/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" }
+%def op_iput_boolean_quick():
+%  op_iput_quick(reg="rINSTbl", store="movb")
diff --git a/runtime/interpreter/mterp/x86/op_iput_byte.S b/runtime/interpreter/mterp/x86/op_iput_byte.S
index b81850c5384ce798f0b1a7af4cea5dc8a86a0366..4b74f9fb0e3c8bfe5566574fae72b21f71cd2067 100644
--- a/runtime/interpreter/mterp/x86/op_iput_byte.S
+++ b/runtime/interpreter/mterp/x86/op_iput_byte.S
@@ -1 +1,2 @@
-%include "x86/op_iput.S" { "helper":"MterpIPutI8" }
+%def op_iput_byte():
+%  op_iput(helper="MterpIPutI8")
diff --git a/runtime/interpreter/mterp/x86/op_iput_byte_quick.S b/runtime/interpreter/mterp/x86/op_iput_byte_quick.S
index 93865de169c965d8104563a215267ca2f8b6ae05..dac18e63ccd618dbc1c7adb955e1371bf33295c1 100644
--- a/runtime/interpreter/mterp/x86/op_iput_byte_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iput_byte_quick.S
@@ -1 +1,2 @@
-%include "x86/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" }
+%def op_iput_byte_quick():
+%  op_iput_quick(reg="rINSTbl", store="movb")
diff --git a/runtime/interpreter/mterp/x86/op_iput_char.S b/runtime/interpreter/mterp/x86/op_iput_char.S
index dde385371e59aae452ec69d15970d555c1225f60..64a249fc122e7eb749561fbc7ef7b3cc1be67382 100644
--- a/runtime/interpreter/mterp/x86/op_iput_char.S
+++ b/runtime/interpreter/mterp/x86/op_iput_char.S
@@ -1 +1,2 @@
-%include "x86/op_iput.S" { "helper":"MterpIPutU16" }
+%def op_iput_char():
+%  op_iput(helper="MterpIPutU16")
diff --git a/runtime/interpreter/mterp/x86/op_iput_char_quick.S b/runtime/interpreter/mterp/x86/op_iput_char_quick.S
index 4ec80290c6a3b492857aba7ab87d85a60db5ad1f..21a25812b15f735dac19e8cc35b6f04f2799e504 100644
--- a/runtime/interpreter/mterp/x86/op_iput_char_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iput_char_quick.S
@@ -1 +1,2 @@
-%include "x86/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" }
+%def op_iput_char_quick():
+%  op_iput_quick(reg="rINSTw", store="movw")
diff --git a/runtime/interpreter/mterp/x86/op_iput_object.S b/runtime/interpreter/mterp/x86/op_iput_object.S
index a124b7ed410db421c846f19e7d6fe06e558f0664..131edd5dbdae914ae95c3220d01788eba1a7ffb2 100644
--- a/runtime/interpreter/mterp/x86/op_iput_object.S
+++ b/runtime/interpreter/mterp/x86/op_iput_object.S
@@ -1 +1,2 @@
-%include "x86/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" }
+%def op_iput_object():
+%  op_iput(is_object="1", helper="MterpIPutObj")
diff --git a/runtime/interpreter/mterp/x86/op_iput_object_quick.S b/runtime/interpreter/mterp/x86/op_iput_object_quick.S
index cb779295b7beb2dc7e6d732dda7c831efc139f77..6b6fb2d553ba21b06c3dbc8f68daabf7a321079b 100644
--- a/runtime/interpreter/mterp/x86/op_iput_object_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iput_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_object_quick():
     EXPORT_PC
     leal    OFF_FP_SHADOWFRAME(rFP), %eax
     movl    %eax, OUT_ARG0(%esp)
diff --git a/runtime/interpreter/mterp/x86/op_iput_quick.S b/runtime/interpreter/mterp/x86/op_iput_quick.S
index b67cee08594b47ff07f750b5cdd3dbe9264efae8..5198cfe5dcae7136bde74c5a6e49e0c669b572cf 100644
--- a/runtime/interpreter/mterp/x86/op_iput_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iput_quick.S
@@ -1,4 +1,4 @@
-%default { "reg":"rINST", "store":"movl" }
+%def op_iput_quick(reg="rINST", store="movl"):
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
diff --git a/runtime/interpreter/mterp/x86/op_iput_short.S b/runtime/interpreter/mterp/x86/op_iput_short.S
index 130e875bb22d7e9fb50285f68353bb462218f17c..e631a3b259e969ae8ae1222244d299fd0e4da3d7 100644
--- a/runtime/interpreter/mterp/x86/op_iput_short.S
+++ b/runtime/interpreter/mterp/x86/op_iput_short.S
@@ -1 +1,2 @@
-%include "x86/op_iput.S" { "helper":"MterpIPutI16" }
+%def op_iput_short():
+%  op_iput(helper="MterpIPutI16")
diff --git a/runtime/interpreter/mterp/x86/op_iput_short_quick.S b/runtime/interpreter/mterp/x86/op_iput_short_quick.S
index 4ec80290c6a3b492857aba7ab87d85a60db5ad1f..5eb28d6922d19c63770208f6e61321153fea6a08 100644
--- a/runtime/interpreter/mterp/x86/op_iput_short_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iput_short_quick.S
@@ -1 +1,2 @@
-%include "x86/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" }
+%def op_iput_short_quick():
+%  op_iput_quick(reg="rINSTw", store="movw")
diff --git a/runtime/interpreter/mterp/x86/op_iput_wide.S b/runtime/interpreter/mterp/x86/op_iput_wide.S
index 2820ede182975e5d1c5ec9659cba34fea633ac09..2f34fd39f9ed2ca1104582178602a4dac83ee761 100644
--- a/runtime/interpreter/mterp/x86/op_iput_wide.S
+++ b/runtime/interpreter/mterp/x86/op_iput_wide.S
@@ -1 +1,2 @@
-%include "x86/op_iput.S" { "helper":"MterpIPutU64" }
+%def op_iput_wide():
+%  op_iput(helper="MterpIPutU64")
diff --git a/runtime/interpreter/mterp/x86/op_iput_wide_quick.S b/runtime/interpreter/mterp/x86/op_iput_wide_quick.S
index 17de6f8502111712bedc4da2234da80d308ffad6..6e1feefffc5eb789ac6715d33efe12f4e906f266 100644
--- a/runtime/interpreter/mterp/x86/op_iput_wide_quick.S
+++ b/runtime/interpreter/mterp/x86/op_iput_wide_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_wide_quick():
     /* iput-wide-quick vA, vB, offset@CCCC */
     movzbl    rINSTbl, %ecx                 # ecx<- BA
     sarl      $$4, %ecx                     # ecx<- B
diff --git a/runtime/interpreter/mterp/x86/op_long_to_double.S b/runtime/interpreter/mterp/x86/op_long_to_double.S
index 2c7f90525974226632c4f9caf8c3711bdb439db5..858cb2e6b596505b9cc0a3a8bbc1a93400306bda 100644
--- a/runtime/interpreter/mterp/x86/op_long_to_double.S
+++ b/runtime/interpreter/mterp/x86/op_long_to_double.S
@@ -1 +1,2 @@
-%include "x86/fpcvt.S" {"load":"fildll","store":"fstpl","wide":"1"}
+%def op_long_to_double():
+%  fpcvt(load="fildll", store="fstpl", wide="1")
diff --git a/runtime/interpreter/mterp/x86/op_long_to_float.S b/runtime/interpreter/mterp/x86/op_long_to_float.S
index e500e39d46b12682b8ad302a3127cfb18e87493e..b26085af311a737ebf108a9b12af98e959c5bc93 100644
--- a/runtime/interpreter/mterp/x86/op_long_to_float.S
+++ b/runtime/interpreter/mterp/x86/op_long_to_float.S
@@ -1 +1,2 @@
-%include "x86/fpcvt.S" {"load":"fildll","store":"fstps"}
+%def op_long_to_float():
+%  fpcvt(load="fildll", store="fstps")
diff --git a/runtime/interpreter/mterp/x86/op_long_to_int.S b/runtime/interpreter/mterp/x86/op_long_to_int.S
index 1c39b96d5c9a8c76eb910aa38ccdda42455d4de8..eacb8f59ec402cbb87d740022854981c341e9a09 100644
--- a/runtime/interpreter/mterp/x86/op_long_to_int.S
+++ b/runtime/interpreter/mterp/x86/op_long_to_int.S
@@ -1,2 +1,3 @@
+%def op_long_to_int():
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-%include "x86/op_move.S"
+%  op_move()
diff --git a/runtime/interpreter/mterp/x86/op_monitor_enter.S b/runtime/interpreter/mterp/x86/op_monitor_enter.S
index b35c68488aecc46d750216972f29713ba16aea1a..d28ab4c307932adfbb1e5c48b44d7769a3683c57 100644
--- a/runtime/interpreter/mterp/x86/op_monitor_enter.S
+++ b/runtime/interpreter/mterp/x86/op_monitor_enter.S
@@ -1,3 +1,4 @@
+%def op_monitor_enter():
 /*
  * Synchronize on an object.
  */
diff --git a/runtime/interpreter/mterp/x86/op_monitor_exit.S b/runtime/interpreter/mterp/x86/op_monitor_exit.S
index 2d17d5e7c55e386579f236839e10c1aac91754fa..63a8287519d88cb64caa5b5ae5d12198636fb043 100644
--- a/runtime/interpreter/mterp/x86/op_monitor_exit.S
+++ b/runtime/interpreter/mterp/x86/op_monitor_exit.S
@@ -1,3 +1,4 @@
+%def op_monitor_exit():
 /*
  * Unlock an object.
  *
diff --git a/runtime/interpreter/mterp/x86/op_move.S b/runtime/interpreter/mterp/x86/op_move.S
index ea173b97d6e809ae5ce44b20e3b6ad9e3ffb8023..e02375596a70f0bcba5187dc8a3a9e7325b5dce1 100644
--- a/runtime/interpreter/mterp/x86/op_move.S
+++ b/runtime/interpreter/mterp/x86/op_move.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move(is_object="0"):
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     movzbl  rINSTbl, %eax                   # eax <- BA
diff --git a/runtime/interpreter/mterp/x86/op_move_16.S b/runtime/interpreter/mterp/x86/op_move_16.S
index 454deb5d08971399f3a45d2b19442ed2b9d1c82c..0b4f8396f46e31fa8aeba392d3795bceef2b110d 100644
--- a/runtime/interpreter/mterp/x86/op_move_16.S
+++ b/runtime/interpreter/mterp/x86/op_move_16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_16(is_object="0"):
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     movzwl  4(rPC), %ecx                    # ecx <- BBBB
diff --git a/runtime/interpreter/mterp/x86/op_move_exception.S b/runtime/interpreter/mterp/x86/op_move_exception.S
index d8dc74fdac6c9cda666c35946491716891811ca7..cadce403504f4c482c89611688d52e7dcb16f6c2 100644
--- a/runtime/interpreter/mterp/x86/op_move_exception.S
+++ b/runtime/interpreter/mterp/x86/op_move_exception.S
@@ -1,3 +1,4 @@
+%def op_move_exception():
     /* move-exception vAA */
     movl    rSELF, %ecx
     movl    THREAD_EXCEPTION_OFFSET(%ecx), %eax
diff --git a/runtime/interpreter/mterp/x86/op_move_from16.S b/runtime/interpreter/mterp/x86/op_move_from16.S
index e86985536e331647a1a8cfae59da719205e3f5ed..b8a9c8bceb286949c4b52dbc72497539741ee85b 100644
--- a/runtime/interpreter/mterp/x86/op_move_from16.S
+++ b/runtime/interpreter/mterp/x86/op_move_from16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_from16(is_object="0"):
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     movzx   rINSTbl, %eax                   # eax <- AA
diff --git a/runtime/interpreter/mterp/x86/op_move_object.S b/runtime/interpreter/mterp/x86/op_move_object.S
index a6a7c90195e09e03847a0337a85e4e773a46dc68..dbb4d5971027d54f58728020aadfa71973fb509a 100644
--- a/runtime/interpreter/mterp/x86/op_move_object.S
+++ b/runtime/interpreter/mterp/x86/op_move_object.S
@@ -1 +1,2 @@
-%include "x86/op_move.S" {"is_object":"1"}
+%def op_move_object():
+%  op_move(is_object="1")
diff --git a/runtime/interpreter/mterp/x86/op_move_object_16.S b/runtime/interpreter/mterp/x86/op_move_object_16.S
index e0c8527a29180f1b20cdc76bf231191610c3b2b8..40120379d51d6027f960ef7742f12d8d16773855 100644
--- a/runtime/interpreter/mterp/x86/op_move_object_16.S
+++ b/runtime/interpreter/mterp/x86/op_move_object_16.S
@@ -1 +1,2 @@
-%include "x86/op_move_16.S" {"is_object":"1"}
+%def op_move_object_16():
+%  op_move_16(is_object="1")
diff --git a/runtime/interpreter/mterp/x86/op_move_object_from16.S b/runtime/interpreter/mterp/x86/op_move_object_from16.S
index e623820470028fbe4c84bfc577dbdfb20e187c0b..c82698e81e6805ad74ebe1f6c8c36e3ff3a1bd4b 100644
--- a/runtime/interpreter/mterp/x86/op_move_object_from16.S
+++ b/runtime/interpreter/mterp/x86/op_move_object_from16.S
@@ -1 +1,2 @@
-%include "x86/op_move_from16.S" {"is_object":"1"}
+%def op_move_object_from16():
+%  op_move_from16(is_object="1")
diff --git a/runtime/interpreter/mterp/x86/op_move_result.S b/runtime/interpreter/mterp/x86/op_move_result.S
index f6f2129f66960abafaa5e43de580c4f467e350ae..c287faadf51417550c725e572abe43f0e81d42c8 100644
--- a/runtime/interpreter/mterp/x86/op_move_result.S
+++ b/runtime/interpreter/mterp/x86/op_move_result.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_result(is_object="0"):
     /* for: move-result, move-result-object */
     /* op vAA */
     movl    OFF_FP_RESULT_REGISTER(rFP), %eax    # get pointer to result JType.
diff --git a/runtime/interpreter/mterp/x86/op_move_result_object.S b/runtime/interpreter/mterp/x86/op_move_result_object.S
index cbf5e1db60a4b9ec869d687d69e0cc78df31eca4..87aea2646a6b25bae7ee8970a973915a76557939 100644
--- a/runtime/interpreter/mterp/x86/op_move_result_object.S
+++ b/runtime/interpreter/mterp/x86/op_move_result_object.S
@@ -1 +1,2 @@
-%include "x86/op_move_result.S" {"is_object":"1"}
+%def op_move_result_object():
+%  op_move_result(is_object="1")
diff --git a/runtime/interpreter/mterp/x86/op_move_result_wide.S b/runtime/interpreter/mterp/x86/op_move_result_wide.S
index 7818cceaf99583fa7fef6438c7e2f45e20cb2ecc..68b1d803b0d00fc10e67b5ef9a727db6f18b15bf 100644
--- a/runtime/interpreter/mterp/x86/op_move_result_wide.S
+++ b/runtime/interpreter/mterp/x86/op_move_result_wide.S
@@ -1,3 +1,4 @@
+%def op_move_result_wide():
     /* move-result-wide vAA */
     movl    OFF_FP_RESULT_REGISTER(rFP), %eax    # get pointer to result JType.
     movl    4(%eax), %ecx                   # Get high
diff --git a/runtime/interpreter/mterp/x86/op_move_wide.S b/runtime/interpreter/mterp/x86/op_move_wide.S
index 79ce7b77bcd16f8d89ce49c6cafebb2d690f0829..0559d01f87710839549d0037b42fef6158eca7fa 100644
--- a/runtime/interpreter/mterp/x86/op_move_wide.S
+++ b/runtime/interpreter/mterp/x86/op_move_wide.S
@@ -1,3 +1,4 @@
+%def op_move_wide():
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
diff --git a/runtime/interpreter/mterp/x86/op_move_wide_16.S b/runtime/interpreter/mterp/x86/op_move_wide_16.S
index a6b8596b98abf686697d84cc78939e0c159f611f..13a5e0d83a64a901cb726b5494bd610bfb215ec6 100644
--- a/runtime/interpreter/mterp/x86/op_move_wide_16.S
+++ b/runtime/interpreter/mterp/x86/op_move_wide_16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_16():
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movzwl  4(rPC), %ecx                    # ecx<- BBBB
diff --git a/runtime/interpreter/mterp/x86/op_move_wide_from16.S b/runtime/interpreter/mterp/x86/op_move_wide_from16.S
index ec344de95fe58a48f628cf459cc372dc919fcdfc..5380a8fa8a799cd473088d44aa1c56356c3080b3 100644
--- a/runtime/interpreter/mterp/x86/op_move_wide_from16.S
+++ b/runtime/interpreter/mterp/x86/op_move_wide_from16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_from16():
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movzwl  2(rPC), %ecx                    # ecx <- BBBB
diff --git a/runtime/interpreter/mterp/x86/op_mul_double.S b/runtime/interpreter/mterp/x86/op_mul_double.S
index 7cef4c08702410f90fd2ed1d731c3c00b543112c..53530287982830edc82175937b29fdbf60992c82 100644
--- a/runtime/interpreter/mterp/x86/op_mul_double.S
+++ b/runtime/interpreter/mterp/x86/op_mul_double.S
@@ -1 +1,2 @@
-%include "x86/sseBinop.S" {"instr":"muls","suff":"d"}
+%def op_mul_double():
+%  sseBinop(instr="muls", suff="d")
diff --git a/runtime/interpreter/mterp/x86/op_mul_double_2addr.S b/runtime/interpreter/mterp/x86/op_mul_double_2addr.S
index bb722b6901657335e2cd3a6face18872c8ad7856..7a6dcd0cb85e6309f990772de0532483cf5f2565 100644
--- a/runtime/interpreter/mterp/x86/op_mul_double_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_mul_double_2addr.S
@@ -1 +1,2 @@
-%include "x86/sseBinop2Addr.S" {"instr":"muls","suff":"d"}
+%def op_mul_double_2addr():
+%  sseBinop2Addr(instr="muls", suff="d")
diff --git a/runtime/interpreter/mterp/x86/op_mul_float.S b/runtime/interpreter/mterp/x86/op_mul_float.S
index 115623047aa5de0af1d1d75ea308b2cc4771d195..b9eeeeeb69c7dfc401e59b28b0550e379e521648 100644
--- a/runtime/interpreter/mterp/x86/op_mul_float.S
+++ b/runtime/interpreter/mterp/x86/op_mul_float.S
@@ -1 +1,2 @@
-%include "x86/sseBinop.S" {"instr":"muls","suff":"s"}
+%def op_mul_float():
+%  sseBinop(instr="muls", suff="s")
diff --git a/runtime/interpreter/mterp/x86/op_mul_float_2addr.S b/runtime/interpreter/mterp/x86/op_mul_float_2addr.S
index e9316dff69109915553bfd27f9cd73f379d53797..949af7b25409313b3f4eb36547b6c27a212a1056 100644
--- a/runtime/interpreter/mterp/x86/op_mul_float_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_mul_float_2addr.S
@@ -1 +1,2 @@
-%include "x86/sseBinop2Addr.S" {"instr":"muls","suff":"s"}
+%def op_mul_float_2addr():
+%  sseBinop2Addr(instr="muls", suff="s")
diff --git a/runtime/interpreter/mterp/x86/op_mul_int.S b/runtime/interpreter/mterp/x86/op_mul_int.S
index 77f4659d6a4e953dd8219759ff54a38e663a1497..93884860d68011134916122602052719bf48dd3f 100644
--- a/runtime/interpreter/mterp/x86/op_mul_int.S
+++ b/runtime/interpreter/mterp/x86/op_mul_int.S
@@ -1,3 +1,4 @@
+%def op_mul_int():
     /*
      * 32-bit binary multiplication.
      */
diff --git a/runtime/interpreter/mterp/x86/op_mul_int_2addr.S b/runtime/interpreter/mterp/x86/op_mul_int_2addr.S
index da699ae19bf88a74c46fc69dec1eb4a81be00b92..34e9b31bc665379b2571aaeeee04c5e633f8f147 100644
--- a/runtime/interpreter/mterp/x86/op_mul_int_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_mul_int_2addr.S
@@ -1,3 +1,4 @@
+%def op_mul_int_2addr():
     /* mul vA, vB */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     sarl    $$4, rINST                      # rINST <- B
diff --git a/runtime/interpreter/mterp/x86/op_mul_int_lit16.S b/runtime/interpreter/mterp/x86/op_mul_int_lit16.S
index 056f491befb1d56f25d499e098c7e37b0e35903e..491fde41b084f0ba32156ee0859203e9a22876eb 100644
--- a/runtime/interpreter/mterp/x86/op_mul_int_lit16.S
+++ b/runtime/interpreter/mterp/x86/op_mul_int_lit16.S
@@ -1,3 +1,4 @@
+%def op_mul_int_lit16():
     /* mul/lit16 vA, vB, #+CCCC */
     /* Need A in rINST, ssssCCCC in ecx, vB in eax */
     movzbl  rINSTbl, %eax                   # eax <- 000000BA
diff --git a/runtime/interpreter/mterp/x86/op_mul_int_lit8.S b/runtime/interpreter/mterp/x86/op_mul_int_lit8.S
index 59b384426c4ebfd57d8c15582b04a23355750581..d76973c776bbbd4e9cc6280e23ee74409696cf88 100644
--- a/runtime/interpreter/mterp/x86/op_mul_int_lit8.S
+++ b/runtime/interpreter/mterp/x86/op_mul_int_lit8.S
@@ -1,3 +1,4 @@
+%def op_mul_int_lit8():
     /* mul/lit8 vAA, vBB, #+CC */
     movzbl  2(rPC), %eax                    # eax <- BB
     movl    rIBASE, %ecx
diff --git a/runtime/interpreter/mterp/x86/op_mul_long.S b/runtime/interpreter/mterp/x86/op_mul_long.S
index f35ca1372b078fd0edf897ad3578dac46da886de..03592725212d1a11a0196138c1c1d24bae73a68d 100644
--- a/runtime/interpreter/mterp/x86/op_mul_long.S
+++ b/runtime/interpreter/mterp/x86/op_mul_long.S
@@ -1,3 +1,4 @@
+%def op_mul_long():
 /*
  * Signed 64-bit integer multiply.
  *
diff --git a/runtime/interpreter/mterp/x86/op_mul_long_2addr.S b/runtime/interpreter/mterp/x86/op_mul_long_2addr.S
index 565a57cd399a65f14eae088a5a4a67477f2f43c3..b48f58d2980481847f641a5f677413eae9d4c745 100644
--- a/runtime/interpreter/mterp/x86/op_mul_long_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_mul_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_mul_long_2addr():
 /*
  * Signed 64-bit integer multiply, 2-addr version
  *
diff --git a/runtime/interpreter/mterp/x86/op_neg_double.S b/runtime/interpreter/mterp/x86/op_neg_double.S
index fac4322f8e0c41ad5e300a87f4560d5bfc47bf33..df290535e2020dafd5943bfe9ae83e91a1da0647 100644
--- a/runtime/interpreter/mterp/x86/op_neg_double.S
+++ b/runtime/interpreter/mterp/x86/op_neg_double.S
@@ -1 +1,2 @@
-%include "x86/fpcvt.S" {"instr":"fchs","load":"fldl","store":"fstpl","wide":"1"}
+%def op_neg_double():
+%  fpcvt(instr="fchs", load="fldl", store="fstpl", wide="1")
diff --git a/runtime/interpreter/mterp/x86/op_neg_float.S b/runtime/interpreter/mterp/x86/op_neg_float.S
index 30f071b991002c5e16c3eb0e48f86c891c8146ee..0abe45c7cc4a7b1186d923cb0a975dcc30be9951 100644
--- a/runtime/interpreter/mterp/x86/op_neg_float.S
+++ b/runtime/interpreter/mterp/x86/op_neg_float.S
@@ -1 +1,2 @@
-%include "x86/fpcvt.S" {"instr":"fchs","load":"flds","store":"fstps"}
+%def op_neg_float():
+%  fpcvt(instr="fchs", load="flds", store="fstps")
diff --git a/runtime/interpreter/mterp/x86/op_neg_int.S b/runtime/interpreter/mterp/x86/op_neg_int.S
index 67d4d182aafe82149a241b314dcaadf9935b90c6..24604a9b0cbc4734b0df9fdcaedad657312f8197 100644
--- a/runtime/interpreter/mterp/x86/op_neg_int.S
+++ b/runtime/interpreter/mterp/x86/op_neg_int.S
@@ -1 +1,2 @@
-%include "x86/unop.S" {"instr":"negl    %eax"}
+%def op_neg_int():
+%  unop(instr="negl    %eax")
diff --git a/runtime/interpreter/mterp/x86/op_neg_long.S b/runtime/interpreter/mterp/x86/op_neg_long.S
index 30da247208066d5ecf227efc32b460068aadb6a2..75f32798f4ba57c2372c74db354a17b195e7480a 100644
--- a/runtime/interpreter/mterp/x86/op_neg_long.S
+++ b/runtime/interpreter/mterp/x86/op_neg_long.S
@@ -1,3 +1,4 @@
+%def op_neg_long():
     /* unop vA, vB */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
     sarl    $$4, %ecx                       # ecx <- B
diff --git a/runtime/interpreter/mterp/x86/op_new_array.S b/runtime/interpreter/mterp/x86/op_new_array.S
index 16226e989c65ac92f48b9c8e748531b74be520f8..e59e10610331a52301de631b8045965ef67e70c7 100644
--- a/runtime/interpreter/mterp/x86/op_new_array.S
+++ b/runtime/interpreter/mterp/x86/op_new_array.S
@@ -1,3 +1,4 @@
+%def op_new_array():
 /*
  * Allocate an array of objects, specified with the array class
  * and a count.
diff --git a/runtime/interpreter/mterp/x86/op_new_instance.S b/runtime/interpreter/mterp/x86/op_new_instance.S
index f976accb1e3ea75f380cb87f1068006de14999f2..81631c6ae797a6945ad864cb8d6e76d5af0803c8 100644
--- a/runtime/interpreter/mterp/x86/op_new_instance.S
+++ b/runtime/interpreter/mterp/x86/op_new_instance.S
@@ -1,3 +1,4 @@
+%def op_new_instance():
 /*
  * Create a new instance of a class.
  */
diff --git a/runtime/interpreter/mterp/x86/op_nop.S b/runtime/interpreter/mterp/x86/op_nop.S
index 4cb68e392e719513e5e85a72fa4aeb942105536b..aa4a843ab509709b7c4b9a9ec2b852829d9b1bdd 100644
--- a/runtime/interpreter/mterp/x86/op_nop.S
+++ b/runtime/interpreter/mterp/x86/op_nop.S
@@ -1 +1,2 @@
+%def op_nop():
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
diff --git a/runtime/interpreter/mterp/x86/op_not_int.S b/runtime/interpreter/mterp/x86/op_not_int.S
index 335ab09a5a02885c29c40a8937d2882f0743375b..c95ac08d185371bf3619f09332df8109dbd27a65 100644
--- a/runtime/interpreter/mterp/x86/op_not_int.S
+++ b/runtime/interpreter/mterp/x86/op_not_int.S
@@ -1 +1,2 @@
-%include "x86/unop.S" {"instr":"notl %eax"}
+%def op_not_int():
+%  unop(instr="notl %eax")
diff --git a/runtime/interpreter/mterp/x86/op_not_long.S b/runtime/interpreter/mterp/x86/op_not_long.S
index 8f706e13bed3414a23aa81069ed476d259cd8dad..c79f9d02f942cad108bd0915a295e877b91dc147 100644
--- a/runtime/interpreter/mterp/x86/op_not_long.S
+++ b/runtime/interpreter/mterp/x86/op_not_long.S
@@ -1,3 +1,4 @@
+%def op_not_long():
     /* unop vA, vB */
     movzbl  rINSTbl, %ecx                   # ecx <- BA
     sarl    $$4, %ecx                       # ecx <- B
diff --git a/runtime/interpreter/mterp/x86/op_or_int.S b/runtime/interpreter/mterp/x86/op_or_int.S
index ebe2ec2cd6d448dff6c61eaf5960d8999d5915c8..f44ac0d6049a2da5dc8c1d0dc650cd7e79d891d4 100644
--- a/runtime/interpreter/mterp/x86/op_or_int.S
+++ b/runtime/interpreter/mterp/x86/op_or_int.S
@@ -1 +1,2 @@
-%include "x86/binop.S" {"instr":"orl     (rFP,%ecx,4), %eax"}
+%def op_or_int():
+%  binop(instr="orl     (rFP,%ecx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86/op_or_int_2addr.S b/runtime/interpreter/mterp/x86/op_or_int_2addr.S
index 36c17db5a78cbf0e61825cfb609a76cf5c7421ec..f0f278c3ce31bd65e821787de8b5645d2c4980fe 100644
--- a/runtime/interpreter/mterp/x86/op_or_int_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_or_int_2addr.S
@@ -1 +1,2 @@
-%include "x86/binop2addr.S" {"instr":"orl     %eax, (rFP,%ecx,4)"}
+%def op_or_int_2addr():
+%  binop2addr(instr="orl     %eax, (rFP,%ecx,4)")
diff --git a/runtime/interpreter/mterp/x86/op_or_int_lit16.S b/runtime/interpreter/mterp/x86/op_or_int_lit16.S
index 0a88ff590205eb12c8f3e12a9e1acf933ba9fddd..ba9b6bff185786a11678ff7eeb4ece59b2bb728c 100644
--- a/runtime/interpreter/mterp/x86/op_or_int_lit16.S
+++ b/runtime/interpreter/mterp/x86/op_or_int_lit16.S
@@ -1 +1,2 @@
-%include "x86/binopLit16.S" {"instr":"orl     %ecx, %eax"}
+%def op_or_int_lit16():
+%  binopLit16(instr="orl     %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_or_int_lit8.S b/runtime/interpreter/mterp/x86/op_or_int_lit8.S
index 0670b6785e0b2af661c76f6913463f9f8d103d97..758109bc0531e079ab152f0eb0f5a774dc7590aa 100644
--- a/runtime/interpreter/mterp/x86/op_or_int_lit8.S
+++ b/runtime/interpreter/mterp/x86/op_or_int_lit8.S
@@ -1 +1,2 @@
-%include "x86/binopLit8.S" {"instr":"orl     %ecx, %eax"}
+%def op_or_int_lit8():
+%  binopLit8(instr="orl     %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_or_long.S b/runtime/interpreter/mterp/x86/op_or_long.S
index 09ca539f2ae57e8e6ac5ec7af0b264daa1ce6557..389081d6fbffebad8d3c37a4bddabd5f1a242351 100644
--- a/runtime/interpreter/mterp/x86/op_or_long.S
+++ b/runtime/interpreter/mterp/x86/op_or_long.S
@@ -1 +1,2 @@
-%include "x86/binopWide.S" {"instr1":"orl     (rFP,%ecx,4), rIBASE", "instr2":"orl     4(rFP,%ecx,4), %eax"}
+%def op_or_long():
+%  binopWide(instr1="orl     (rFP,%ecx,4), rIBASE", instr2="orl     4(rFP,%ecx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86/op_or_long_2addr.S b/runtime/interpreter/mterp/x86/op_or_long_2addr.S
index 2062e81e35dc3f0d0a4f7c532c34318e5d604355..5beb9a2e01ffa97c4245525a28671a5bf11ee650 100644
--- a/runtime/interpreter/mterp/x86/op_or_long_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_or_long_2addr.S
@@ -1 +1,2 @@
-%include "x86/binopWide2addr.S" {"instr1":"orl     %eax, (rFP,rINST,4)","instr2":"orl     %ecx, 4(rFP,rINST,4)"}
+%def op_or_long_2addr():
+%  binopWide2addr(instr1="orl     %eax, (rFP,rINST,4)", instr2="orl     %ecx, 4(rFP,rINST,4)")
diff --git a/runtime/interpreter/mterp/x86/op_packed_switch.S b/runtime/interpreter/mterp/x86/op_packed_switch.S
index fcb7509ebf9166002008fa591969e54363481380..b4c393fb84ae01c01a745dd0e362fcaf2c3d156b 100644
--- a/runtime/interpreter/mterp/x86/op_packed_switch.S
+++ b/runtime/interpreter/mterp/x86/op_packed_switch.S
@@ -1,4 +1,4 @@
-%default { "func":"MterpDoPackedSwitch" }
+%def op_packed_switch(func="MterpDoPackedSwitch"):
 /*
  * Handle a packed-switch or sparse-switch instruction.  In both cases
  * we decode it and hand it off to a helper function.
diff --git a/runtime/interpreter/mterp/x86/op_rem_double.S b/runtime/interpreter/mterp/x86/op_rem_double.S
index 4b52a06042f7a799250ea5fe2395f16ab56dd551..df7b74057612497d0e78142df0131b8aaba8a400 100644
--- a/runtime/interpreter/mterp/x86/op_rem_double.S
+++ b/runtime/interpreter/mterp/x86/op_rem_double.S
@@ -1,3 +1,4 @@
+%def op_rem_double():
     /* rem_double vAA, vBB, vCC */
     movzbl  3(rPC), %ecx                    # ecx <- BB
     movzbl  2(rPC), %eax                    # eax <- CC
diff --git a/runtime/interpreter/mterp/x86/op_rem_double_2addr.S b/runtime/interpreter/mterp/x86/op_rem_double_2addr.S
index 5a0e669787bdb02b60dd4951c0a4a0c6fad81a60..fb4e3937002fe9fd8b79c50fb0071247b30279ac 100644
--- a/runtime/interpreter/mterp/x86/op_rem_double_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_rem_double_2addr.S
@@ -1,3 +1,4 @@
+%def op_rem_double_2addr():
     /* rem_double/2addr vA, vB */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     sarl    $$4, rINST                      # rINST <- B
diff --git a/runtime/interpreter/mterp/x86/op_rem_float.S b/runtime/interpreter/mterp/x86/op_rem_float.S
index 05e0bf1132ac2a51cd53327cf1570256c23d62b5..9b436f2759953306b2987e38c8200afc0b9b7b4a 100644
--- a/runtime/interpreter/mterp/x86/op_rem_float.S
+++ b/runtime/interpreter/mterp/x86/op_rem_float.S
@@ -1,3 +1,4 @@
+%def op_rem_float():
     /* rem_float vAA, vBB, vCC */
     movzbl  3(rPC), %ecx                    # ecx <- BB
     movzbl  2(rPC), %eax                    # eax <- CC
diff --git a/runtime/interpreter/mterp/x86/op_rem_float_2addr.S b/runtime/interpreter/mterp/x86/op_rem_float_2addr.S
index 29f84e635ab43a3c04c25e7db05037cdc39d35e1..81d44c8b14a95c7024139df7f35c082380fa69d5 100644
--- a/runtime/interpreter/mterp/x86/op_rem_float_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_rem_float_2addr.S
@@ -1,3 +1,4 @@
+%def op_rem_float_2addr():
     /* rem_float/2addr vA, vB */
     movzx   rINSTbl, %ecx                   # ecx <- A+
     sarl    $$4, rINST                      # rINST <- B
diff --git a/runtime/interpreter/mterp/x86/op_rem_int.S b/runtime/interpreter/mterp/x86/op_rem_int.S
index d25b93ce3fbd2c542bce0bea89ce3bc3361afa0d..71da7b81dbf0342674f5f094161714e631b2c149 100644
--- a/runtime/interpreter/mterp/x86/op_rem_int.S
+++ b/runtime/interpreter/mterp/x86/op_rem_int.S
@@ -1 +1,2 @@
-%include "x86/bindiv.S" {"result":"rIBASE","special":"$0","rem":"1"}
+%def op_rem_int():
+%  bindiv(result="rIBASE", special="$0", rem="1")
diff --git a/runtime/interpreter/mterp/x86/op_rem_int_2addr.S b/runtime/interpreter/mterp/x86/op_rem_int_2addr.S
index c788e0eed06dcc3da1b80c3c2ffde4a7e3943639..f58f4ac73fa171dfad178857a4204ec6789d0a58 100644
--- a/runtime/interpreter/mterp/x86/op_rem_int_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_rem_int_2addr.S
@@ -1 +1,2 @@
-%include "x86/bindiv2addr.S" {"result":"rIBASE","special":"$0"}
+%def op_rem_int_2addr():
+%  bindiv2addr(result="rIBASE", special="$0")
diff --git a/runtime/interpreter/mterp/x86/op_rem_int_lit16.S b/runtime/interpreter/mterp/x86/op_rem_int_lit16.S
index 3df9d3911ddb0f1b021a07b95aac0812d1da6edd..8915740c04cafa6ad73e9237eb1d6f654853ccf7 100644
--- a/runtime/interpreter/mterp/x86/op_rem_int_lit16.S
+++ b/runtime/interpreter/mterp/x86/op_rem_int_lit16.S
@@ -1 +1,2 @@
-%include "x86/bindivLit16.S" {"result":"rIBASE","special":"$0"}
+%def op_rem_int_lit16():
+%  bindivLit16(result="rIBASE", special="$0")
diff --git a/runtime/interpreter/mterp/x86/op_rem_int_lit8.S b/runtime/interpreter/mterp/x86/op_rem_int_lit8.S
index 56e19c6b17afb73c341468851ec8a96a3b2c3f84..88369def7fb50d4ac0297c12536790ffae06d3db 100644
--- a/runtime/interpreter/mterp/x86/op_rem_int_lit8.S
+++ b/runtime/interpreter/mterp/x86/op_rem_int_lit8.S
@@ -1 +1,2 @@
-%include "x86/bindivLit8.S" {"result":"rIBASE","special":"$0"}
+%def op_rem_int_lit8():
+%  bindivLit8(result="rIBASE", special="$0")
diff --git a/runtime/interpreter/mterp/x86/op_rem_long.S b/runtime/interpreter/mterp/x86/op_rem_long.S
index 0ffe1f668cca24f02c45bd277f812e38122a87ff..ef23c05ed81823ce354664738a993506101c0e59 100644
--- a/runtime/interpreter/mterp/x86/op_rem_long.S
+++ b/runtime/interpreter/mterp/x86/op_rem_long.S
@@ -1 +1,2 @@
-%include "x86/op_div_long.S" {"routine":"art_quick_lmod"}
+%def op_rem_long():
+%  op_div_long(routine="art_quick_lmod")
diff --git a/runtime/interpreter/mterp/x86/op_rem_long_2addr.S b/runtime/interpreter/mterp/x86/op_rem_long_2addr.S
index 4b977352a111c9ee55db38c5c5ebb0151a4f5df7..f6a8ec36a276bfb0ac8864d376edf552bbbb91dd 100644
--- a/runtime/interpreter/mterp/x86/op_rem_long_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_rem_long_2addr.S
@@ -1 +1,2 @@
-%include "x86/op_div_long_2addr.S" {"routine":"art_quick_lmod"}
+%def op_rem_long_2addr():
+%  op_div_long_2addr(routine="art_quick_lmod")
diff --git a/runtime/interpreter/mterp/x86/op_return.S b/runtime/interpreter/mterp/x86/op_return.S
index a8ebbed64e2a764e12ddfcc39ad90868a5c27a07..0fdd6f51c8421b1ebdf7ed3d62a286efa3fa2163 100644
--- a/runtime/interpreter/mterp/x86/op_return.S
+++ b/runtime/interpreter/mterp/x86/op_return.S
@@ -1,3 +1,4 @@
+%def op_return():
 /*
  * Return a 32-bit value.
  *
diff --git a/runtime/interpreter/mterp/x86/op_return_object.S b/runtime/interpreter/mterp/x86/op_return_object.S
index 12c84b32a2d94ddc9ec11dfbf894edc1e491a129..2eeec0b94824884ff1b3c0aeccbfa0948268f9ab 100644
--- a/runtime/interpreter/mterp/x86/op_return_object.S
+++ b/runtime/interpreter/mterp/x86/op_return_object.S
@@ -1 +1,2 @@
-%include "x86/op_return.S"
+%def op_return_object():
+%  op_return()
diff --git a/runtime/interpreter/mterp/x86/op_return_void.S b/runtime/interpreter/mterp/x86/op_return_void.S
index d9eddf39f2524a305a4e7afdd9a9c00977234e11..3eb5b6602e11587c1f4b5815ba96b50983e7efb9 100644
--- a/runtime/interpreter/mterp/x86/op_return_void.S
+++ b/runtime/interpreter/mterp/x86/op_return_void.S
@@ -1,3 +1,4 @@
+%def op_return_void():
     .extern MterpThreadFenceForConstructor
     call    SYMBOL(MterpThreadFenceForConstructor)
     movl    rSELF, %eax
diff --git a/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S b/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S
index 2fbda6bfe995dcc8fd16fa460684c22b01703316..eadd522299a9ad415bcaec3958aec9f069968066 100644
--- a/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S
+++ b/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S
@@ -1,3 +1,4 @@
+%def op_return_void_no_barrier():
     movl    rSELF, %eax
     testl   $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax)
     jz      1f
diff --git a/runtime/interpreter/mterp/x86/op_return_wide.S b/runtime/interpreter/mterp/x86/op_return_wide.S
index 5fff62620065e1995121eb359fb331be370d3393..67a103dac6964b68141f43c1c7708f31b522cf95 100644
--- a/runtime/interpreter/mterp/x86/op_return_wide.S
+++ b/runtime/interpreter/mterp/x86/op_return_wide.S
@@ -1,3 +1,4 @@
+%def op_return_wide():
 /*
  * Return a 64-bit value.
  */
diff --git a/runtime/interpreter/mterp/x86/op_rsub_int.S b/runtime/interpreter/mterp/x86/op_rsub_int.S
index d6449c6c47665afe6d34ecff132703472dbc1d65..05ba130f2f80670a6830956b50d72a6ea68cda16 100644
--- a/runtime/interpreter/mterp/x86/op_rsub_int.S
+++ b/runtime/interpreter/mterp/x86/op_rsub_int.S
@@ -1,2 +1,3 @@
+%def op_rsub_int():
 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
-%include "x86/binopLit16.S" {"instr":"subl    %eax, %ecx","result":"%ecx"}
+%  binopLit16(instr="subl    %eax, %ecx", result="%ecx")
diff --git a/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S b/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S
index 15d0e359bff791fa70e32fa24abd8bb395f81960..d0230476d700ef0b90027789faecff8e508711f5 100644
--- a/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S
+++ b/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S
@@ -1 +1,2 @@
-%include "x86/binopLit8.S" {"instr":"subl    %eax, %ecx" , "result":"%ecx"}
+%def op_rsub_int_lit8():
+%  binopLit8(instr="subl    %eax, %ecx", result="%ecx")
diff --git a/runtime/interpreter/mterp/x86/op_sget.S b/runtime/interpreter/mterp/x86/op_sget.S
index ada4e0e26a116a282bc9ac2af6ddfe7009d97367..8a6a66ab6032f5a140fcaa4cb0f85af9cb84bd7a 100644
--- a/runtime/interpreter/mterp/x86/op_sget.S
+++ b/runtime/interpreter/mterp/x86/op_sget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSGetU32" }
-%include "x86/field.S" { }
+%def op_sget(is_object="0", helper="MterpSGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/x86/op_sget_boolean.S b/runtime/interpreter/mterp/x86/op_sget_boolean.S
index 3936eeae4548865fc8cca3e59a7dee53ab967ce3..d9c12c9b280100ec8c517e2c264d9c99022bb429 100644
--- a/runtime/interpreter/mterp/x86/op_sget_boolean.S
+++ b/runtime/interpreter/mterp/x86/op_sget_boolean.S
@@ -1 +1,2 @@
-%include "x86/op_sget.S" {"helper":"MterpSGetU8"}
+%def op_sget_boolean():
+%  op_sget(helper="MterpSGetU8")
diff --git a/runtime/interpreter/mterp/x86/op_sget_byte.S b/runtime/interpreter/mterp/x86/op_sget_byte.S
index 967586d9440bd83674797b7b5fc42c0933f6406f..37c6879cd4b02e1fe323434a8f0e490352d4d391 100644
--- a/runtime/interpreter/mterp/x86/op_sget_byte.S
+++ b/runtime/interpreter/mterp/x86/op_sget_byte.S
@@ -1 +1,2 @@
-%include "x86/op_sget.S" {"helper":"MterpSGetI8"}
+%def op_sget_byte():
+%  op_sget(helper="MterpSGetI8")
diff --git a/runtime/interpreter/mterp/x86/op_sget_char.S b/runtime/interpreter/mterp/x86/op_sget_char.S
index b706f18638f4fae7539348b1a5898123e625987a..003bcd16833da0b4c77b8ef60e71ee9bbb01e8da 100644
--- a/runtime/interpreter/mterp/x86/op_sget_char.S
+++ b/runtime/interpreter/mterp/x86/op_sget_char.S
@@ -1 +1,2 @@
-%include "x86/op_sget.S" {"helper":"MterpSGetU16"}
+%def op_sget_char():
+%  op_sget(helper="MterpSGetU16")
diff --git a/runtime/interpreter/mterp/x86/op_sget_object.S b/runtime/interpreter/mterp/x86/op_sget_object.S
index eac88365347156292ca909478b21a0c98cc04101..7cf3597f44f59b999d828d0749f53401e98cfee6 100644
--- a/runtime/interpreter/mterp/x86/op_sget_object.S
+++ b/runtime/interpreter/mterp/x86/op_sget_object.S
@@ -1 +1,2 @@
-%include "x86/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"}
+%def op_sget_object():
+%  op_sget(is_object="1", helper="MterpSGetObj")
diff --git a/runtime/interpreter/mterp/x86/op_sget_short.S b/runtime/interpreter/mterp/x86/op_sget_short.S
index ee058a60167a1c3ca6d865d3940366840be63f29..afacb578d90caf9455c969edfe13663d0927cb03 100644
--- a/runtime/interpreter/mterp/x86/op_sget_short.S
+++ b/runtime/interpreter/mterp/x86/op_sget_short.S
@@ -1 +1,2 @@
-%include "x86/op_sget.S" {"helper":"MterpSGetI16"}
+%def op_sget_short():
+%  op_sget(helper="MterpSGetI16")
diff --git a/runtime/interpreter/mterp/x86/op_sget_wide.S b/runtime/interpreter/mterp/x86/op_sget_wide.S
index 59232749a2633527302289d909ed1cae2f932c42..fff2be6945510278d990141764285ab694e302ed 100644
--- a/runtime/interpreter/mterp/x86/op_sget_wide.S
+++ b/runtime/interpreter/mterp/x86/op_sget_wide.S
@@ -1 +1,2 @@
-%include "x86/op_sget.S" {"helper":"MterpSGetU64"}
+%def op_sget_wide():
+%  op_sget(helper="MterpSGetU64")
diff --git a/runtime/interpreter/mterp/x86/op_shl_int.S b/runtime/interpreter/mterp/x86/op_shl_int.S
index 6a41d1c70bff084242133fa163532eff3b671fad..a98b25612097d5113d7a62462811cd3d50bc85a7 100644
--- a/runtime/interpreter/mterp/x86/op_shl_int.S
+++ b/runtime/interpreter/mterp/x86/op_shl_int.S
@@ -1 +1,2 @@
-%include "x86/binop1.S" {"instr":"sall    %cl, %eax"}
+%def op_shl_int():
+%  binop1(instr="sall    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_shl_int_2addr.S b/runtime/interpreter/mterp/x86/op_shl_int_2addr.S
index 72abb8ebe0abab53042ba2968ed29e4d270eccab..987c7d1e2875cb7e52d3ed50f32b36bea4dcf584 100644
--- a/runtime/interpreter/mterp/x86/op_shl_int_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_shl_int_2addr.S
@@ -1 +1,2 @@
-%include "x86/shop2addr.S" {"instr":"sall    %cl, %eax"}
+%def op_shl_int_2addr():
+%  shop2addr(instr="sall    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_shl_int_lit8.S b/runtime/interpreter/mterp/x86/op_shl_int_lit8.S
index b8d60691779692b183fa5c2c1bc1170217105307..ee1a15e69698074fa6977398655337909b229060 100644
--- a/runtime/interpreter/mterp/x86/op_shl_int_lit8.S
+++ b/runtime/interpreter/mterp/x86/op_shl_int_lit8.S
@@ -1 +1,2 @@
-%include "x86/binopLit8.S" {"instr":"sall    %cl, %eax"}
+%def op_shl_int_lit8():
+%  binopLit8(instr="sall    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_shl_long.S b/runtime/interpreter/mterp/x86/op_shl_long.S
index aa58a93f9c88383af827db5018e655feb89ab765..d45705a6ad60955148709e6d5772751e8b34082f 100644
--- a/runtime/interpreter/mterp/x86/op_shl_long.S
+++ b/runtime/interpreter/mterp/x86/op_shl_long.S
@@ -1,3 +1,4 @@
+%def op_shl_long():
 /*
  * Long integer shift.  This is different from the generic 32/64-bit
  * binary operations because vAA/vBB are 64-bit but vCC (the shift
diff --git a/runtime/interpreter/mterp/x86/op_shl_long_2addr.S b/runtime/interpreter/mterp/x86/op_shl_long_2addr.S
index 6bbf49ca69a467f1b4c2d81045c0d95591da145b..7d40f56cc026cdced5288863bdea8287fd2da032 100644
--- a/runtime/interpreter/mterp/x86/op_shl_long_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_shl_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_shl_long_2addr():
 /*
  * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
  * 32-bit shift distance.
diff --git a/runtime/interpreter/mterp/x86/op_shr_int.S b/runtime/interpreter/mterp/x86/op_shr_int.S
index 687b2c3b7b6546ea3df53eabd89cac4c0c0b37d0..4d4d79cc09a580384be816e42014f7dcd65f086d 100644
--- a/runtime/interpreter/mterp/x86/op_shr_int.S
+++ b/runtime/interpreter/mterp/x86/op_shr_int.S
@@ -1 +1,2 @@
-%include "x86/binop1.S" {"instr":"sarl    %cl, %eax"}
+%def op_shr_int():
+%  binop1(instr="sarl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_shr_int_2addr.S b/runtime/interpreter/mterp/x86/op_shr_int_2addr.S
index 533b0e95b9f1e11be525560af719d8c15ced1f36..8e4b055e157771df5bb4591534c54001c486fb32 100644
--- a/runtime/interpreter/mterp/x86/op_shr_int_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_shr_int_2addr.S
@@ -1 +1,2 @@
-%include "x86/shop2addr.S" {"instr":"sarl    %cl, %eax"}
+%def op_shr_int_2addr():
+%  shop2addr(instr="sarl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_shr_int_lit8.S b/runtime/interpreter/mterp/x86/op_shr_int_lit8.S
index ebd1beafaceed5164f238d146fdc2d8bcfc32673..a7acf5f384edb60ed25e989c11c993a43703b806 100644
--- a/runtime/interpreter/mterp/x86/op_shr_int_lit8.S
+++ b/runtime/interpreter/mterp/x86/op_shr_int_lit8.S
@@ -1 +1,2 @@
-%include "x86/binopLit8.S" {"instr":"sarl    %cl, %eax"}
+%def op_shr_int_lit8():
+%  binopLit8(instr="sarl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_shr_long.S b/runtime/interpreter/mterp/x86/op_shr_long.S
index 68aa0ee83712371f39c8c1fe302f85b23b71ab38..3b859411ae0e2422c55683e64b32fc7209620651 100644
--- a/runtime/interpreter/mterp/x86/op_shr_long.S
+++ b/runtime/interpreter/mterp/x86/op_shr_long.S
@@ -1,3 +1,4 @@
+%def op_shr_long():
 /*
  * Long integer shift.  This is different from the generic 32/64-bit
  * binary operations because vAA/vBB are 64-bit but vCC (the shift
diff --git a/runtime/interpreter/mterp/x86/op_shr_long_2addr.S b/runtime/interpreter/mterp/x86/op_shr_long_2addr.S
index 148bd1b9ebf6ab570aa62b021de14b3d400886af..6427dedbf474a2d02a5060bfe753e5a709d65541 100644
--- a/runtime/interpreter/mterp/x86/op_shr_long_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_shr_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_shr_long_2addr():
 /*
  * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
  * 32-bit shift distance.
diff --git a/runtime/interpreter/mterp/x86/op_sparse_switch.S b/runtime/interpreter/mterp/x86/op_sparse_switch.S
index fdaec4762ad76f9945b6dc031e54dc09444668c7..b74d7da81633f307dbf7c07ffaada2d14f131ec3 100644
--- a/runtime/interpreter/mterp/x86/op_sparse_switch.S
+++ b/runtime/interpreter/mterp/x86/op_sparse_switch.S
@@ -1 +1,2 @@
-%include "x86/op_packed_switch.S" { "func":"MterpDoSparseSwitch" }
+%def op_sparse_switch():
+%  op_packed_switch(func="MterpDoSparseSwitch")
diff --git a/runtime/interpreter/mterp/x86/op_sput.S b/runtime/interpreter/mterp/x86/op_sput.S
index 2ad68e7683895533b7dc10769881e85e9c39c4af..cbd6ee96d345758221edb4c7f71dd2dda57ac8f0 100644
--- a/runtime/interpreter/mterp/x86/op_sput.S
+++ b/runtime/interpreter/mterp/x86/op_sput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSPutU32"}
-%include "x86/field.S" { }
+%def op_sput(is_object="0", helper="MterpSPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/x86/op_sput_boolean.S b/runtime/interpreter/mterp/x86/op_sput_boolean.S
index c6aa7c4cd128aabd7d88111ef73f36c8a5013359..36fba8448b478323ce47a26f2a4d79accbf9964d 100644
--- a/runtime/interpreter/mterp/x86/op_sput_boolean.S
+++ b/runtime/interpreter/mterp/x86/op_sput_boolean.S
@@ -1 +1,2 @@
-%include "x86/op_sput.S" {"helper":"MterpSPutU8"}
+%def op_sput_boolean():
+%  op_sput(helper="MterpSPutU8")
diff --git a/runtime/interpreter/mterp/x86/op_sput_byte.S b/runtime/interpreter/mterp/x86/op_sput_byte.S
index fd504a8023d204942ddb0ded13d89590564b08a9..84ad4a0ff86ccfcd1159672dac902ee99cfc37d9 100644
--- a/runtime/interpreter/mterp/x86/op_sput_byte.S
+++ b/runtime/interpreter/mterp/x86/op_sput_byte.S
@@ -1 +1,2 @@
-%include "x86/op_sput.S" {"helper":"MterpSPutI8"}
+%def op_sput_byte():
+%  op_sput(helper="MterpSPutI8")
diff --git a/runtime/interpreter/mterp/x86/op_sput_char.S b/runtime/interpreter/mterp/x86/op_sput_char.S
index b4d0997737673ac9d9896ab0c28bca0091b2bafe..9b8eeba578f555750ab9497c8fc21ce4a52e8b89 100644
--- a/runtime/interpreter/mterp/x86/op_sput_char.S
+++ b/runtime/interpreter/mterp/x86/op_sput_char.S
@@ -1 +1,2 @@
-%include "x86/op_sput.S" {"helper":"MterpSPutU16"}
+%def op_sput_char():
+%  op_sput(helper="MterpSPutU16")
diff --git a/runtime/interpreter/mterp/x86/op_sput_object.S b/runtime/interpreter/mterp/x86/op_sput_object.S
index 4452dba2723820a26214259b6c875e024bee1ff7..081360c40fb12c03e3a48c24a3677ee55a609758 100644
--- a/runtime/interpreter/mterp/x86/op_sput_object.S
+++ b/runtime/interpreter/mterp/x86/op_sput_object.S
@@ -1 +1,2 @@
-%include "x86/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"}
+%def op_sput_object():
+%  op_sput(is_object="1", helper="MterpSPutObj")
diff --git a/runtime/interpreter/mterp/x86/op_sput_short.S b/runtime/interpreter/mterp/x86/op_sput_short.S
index eba01bdfd0b93bc08415e1d4ad06bd0f58a24d92..ee16513486189f1a65fe9922285fe9ae08606b97 100644
--- a/runtime/interpreter/mterp/x86/op_sput_short.S
+++ b/runtime/interpreter/mterp/x86/op_sput_short.S
@@ -1 +1,2 @@
-%include "x86/op_sput.S" {"helper":"MterpSPutI16"}
+%def op_sput_short():
+%  op_sput(helper="MterpSPutI16")
diff --git a/runtime/interpreter/mterp/x86/op_sput_wide.S b/runtime/interpreter/mterp/x86/op_sput_wide.S
index d79b068f33d9017d142650563822b6155a6d137d..44c1a188edf6bb3cf29011f1b361701ae71aaf9c 100644
--- a/runtime/interpreter/mterp/x86/op_sput_wide.S
+++ b/runtime/interpreter/mterp/x86/op_sput_wide.S
@@ -1 +1,2 @@
-%include "x86/op_sput.S" {"helper":"MterpSPutU64"}
+%def op_sput_wide():
+%  op_sput(helper="MterpSPutU64")
diff --git a/runtime/interpreter/mterp/x86/op_sub_double.S b/runtime/interpreter/mterp/x86/op_sub_double.S
index e83afeb215f5496a8651e7e112d67bc5941a3a9e..64a28c376be4998a49728c396ed4b6357c1427ca 100644
--- a/runtime/interpreter/mterp/x86/op_sub_double.S
+++ b/runtime/interpreter/mterp/x86/op_sub_double.S
@@ -1 +1,2 @@
-%include "x86/sseBinop.S" {"instr":"subs","suff":"d"}
+%def op_sub_double():
+%  sseBinop(instr="subs", suff="d")
diff --git a/runtime/interpreter/mterp/x86/op_sub_double_2addr.S b/runtime/interpreter/mterp/x86/op_sub_double_2addr.S
index af9a2ab3f84a60c204c6d1df7550016da2f52a85..753074bd375cb81e3866d4d7d729c156462a6bce 100644
--- a/runtime/interpreter/mterp/x86/op_sub_double_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_sub_double_2addr.S
@@ -1 +1,2 @@
-%include "x86/sseBinop2Addr.S" {"instr":"subs","suff":"d"}
+%def op_sub_double_2addr():
+%  sseBinop2Addr(instr="subs", suff="d")
diff --git a/runtime/interpreter/mterp/x86/op_sub_float.S b/runtime/interpreter/mterp/x86/op_sub_float.S
index 423d8340690e9e87e5cddc258ef903537ca3f1d6..1a1966dba26a69764d9e05d71e911b58706fcb63 100644
--- a/runtime/interpreter/mterp/x86/op_sub_float.S
+++ b/runtime/interpreter/mterp/x86/op_sub_float.S
@@ -1 +1,2 @@
-%include "x86/sseBinop.S" {"instr":"subs","suff":"s"}
+%def op_sub_float():
+%  sseBinop(instr="subs", suff="s")
diff --git a/runtime/interpreter/mterp/x86/op_sub_float_2addr.S b/runtime/interpreter/mterp/x86/op_sub_float_2addr.S
index 18de000b492ef5fbabfba33e465017c9c28d43f3..9557907bd260028f75695c381eca036287c2c187 100644
--- a/runtime/interpreter/mterp/x86/op_sub_float_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_sub_float_2addr.S
@@ -1 +1,2 @@
-%include "x86/sseBinop2Addr.S" {"instr":"subs","suff":"s"}
+%def op_sub_float_2addr():
+%  sseBinop2Addr(instr="subs", suff="s")
diff --git a/runtime/interpreter/mterp/x86/op_sub_int.S b/runtime/interpreter/mterp/x86/op_sub_int.S
index 7fe03fb1693e2abc74af26301e6351269f0ec149..289d241accd3de709eaa7302237a1cac3faa0169 100644
--- a/runtime/interpreter/mterp/x86/op_sub_int.S
+++ b/runtime/interpreter/mterp/x86/op_sub_int.S
@@ -1 +1,2 @@
-%include "x86/binop.S" {"instr":"subl    (rFP,%ecx,4), %eax"}
+%def op_sub_int():
+%  binop(instr="subl    (rFP,%ecx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86/op_sub_int_2addr.S b/runtime/interpreter/mterp/x86/op_sub_int_2addr.S
index cc9bf60f2e2623fd0e6af9488fbd5573776302a9..b55f8874d98e005a0e04f0c85d3847b5f7f1eccc 100644
--- a/runtime/interpreter/mterp/x86/op_sub_int_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_sub_int_2addr.S
@@ -1 +1,2 @@
-%include "x86/binop2addr.S" {"instr":"subl    %eax, (rFP,%ecx,4)"}
+%def op_sub_int_2addr():
+%  binop2addr(instr="subl    %eax, (rFP,%ecx,4)")
diff --git a/runtime/interpreter/mterp/x86/op_sub_long.S b/runtime/interpreter/mterp/x86/op_sub_long.S
index 014591e41e9bc46a8f7d4e0b845a01308ff26b8e..d45c9a78465aa845a1da62d5344a41be2cae961e 100644
--- a/runtime/interpreter/mterp/x86/op_sub_long.S
+++ b/runtime/interpreter/mterp/x86/op_sub_long.S
@@ -1 +1,2 @@
-%include "x86/binopWide.S" {"instr1":"subl    (rFP,%ecx,4), rIBASE", "instr2":"sbbl    4(rFP,%ecx,4), %eax"}
+%def op_sub_long():
+%  binopWide(instr1="subl    (rFP,%ecx,4), rIBASE", instr2="sbbl    4(rFP,%ecx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86/op_sub_long_2addr.S b/runtime/interpreter/mterp/x86/op_sub_long_2addr.S
index 7498029ebf7b7cb394b1bc448fac75bd580398e7..615b535ef44d143f5dfa9518293c968363293805 100644
--- a/runtime/interpreter/mterp/x86/op_sub_long_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_sub_long_2addr.S
@@ -1 +1,2 @@
-%include "x86/binopWide2addr.S" {"instr1":"subl    %eax, (rFP,rINST,4)","instr2":"sbbl    %ecx, 4(rFP,rINST,4)"}
+%def op_sub_long_2addr():
+%  binopWide2addr(instr1="subl    %eax, (rFP,rINST,4)", instr2="sbbl    %ecx, 4(rFP,rINST,4)")
diff --git a/runtime/interpreter/mterp/x86/op_throw.S b/runtime/interpreter/mterp/x86/op_throw.S
index a6e6b1ed5626efdd976d718a90e21721ca0d1142..fa4a9d02a75aa81bf7c4770cdcf9ae017abf0231 100644
--- a/runtime/interpreter/mterp/x86/op_throw.S
+++ b/runtime/interpreter/mterp/x86/op_throw.S
@@ -1,3 +1,4 @@
+%def op_throw():
 /*
  * Throw an exception object in the current thread.
  */
diff --git a/runtime/interpreter/mterp/x86/op_unused_3e.S b/runtime/interpreter/mterp/x86/op_unused_3e.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..d889f1a5fb4be366ce5101882ae40577a9b0b90b 100644
--- a/runtime/interpreter/mterp/x86/op_unused_3e.S
+++ b/runtime/interpreter/mterp/x86/op_unused_3e.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_3e():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_3f.S b/runtime/interpreter/mterp/x86/op_unused_3f.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..b3ebcfaeaa402ba263610b3f305daf92cc23bebb 100644
--- a/runtime/interpreter/mterp/x86/op_unused_3f.S
+++ b/runtime/interpreter/mterp/x86/op_unused_3f.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_3f():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_40.S b/runtime/interpreter/mterp/x86/op_unused_40.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..7920fb350f2f93b310d33ec19166b6b8445bb0eb 100644
--- a/runtime/interpreter/mterp/x86/op_unused_40.S
+++ b/runtime/interpreter/mterp/x86/op_unused_40.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_40():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_41.S b/runtime/interpreter/mterp/x86/op_unused_41.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..5ed03b85065e78c670f3d26c62b6c56f58338d44 100644
--- a/runtime/interpreter/mterp/x86/op_unused_41.S
+++ b/runtime/interpreter/mterp/x86/op_unused_41.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_41():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_42.S b/runtime/interpreter/mterp/x86/op_unused_42.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..ac32521add543fb2f858aa858af6c3d5594f187e 100644
--- a/runtime/interpreter/mterp/x86/op_unused_42.S
+++ b/runtime/interpreter/mterp/x86/op_unused_42.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_42():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_43.S b/runtime/interpreter/mterp/x86/op_unused_43.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..33e2aa10f8bec8407ff8090cfd81dda49b2a19b8 100644
--- a/runtime/interpreter/mterp/x86/op_unused_43.S
+++ b/runtime/interpreter/mterp/x86/op_unused_43.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_43():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_79.S b/runtime/interpreter/mterp/x86/op_unused_79.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..3c6dafc7898855a1034ff93b17bed71a07df1e51 100644
--- a/runtime/interpreter/mterp/x86/op_unused_79.S
+++ b/runtime/interpreter/mterp/x86/op_unused_79.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_79():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_7a.S b/runtime/interpreter/mterp/x86/op_unused_7a.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..9c03cd55355a41369dc85dbea7e07e7bd8e96383 100644
--- a/runtime/interpreter/mterp/x86/op_unused_7a.S
+++ b/runtime/interpreter/mterp/x86/op_unused_7a.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_7a():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_f3.S b/runtime/interpreter/mterp/x86/op_unused_f3.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..ab10b78be2a0b681652d52185cf7c39d3403a41e 100644
--- a/runtime/interpreter/mterp/x86/op_unused_f3.S
+++ b/runtime/interpreter/mterp/x86/op_unused_f3.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_f3():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_f4.S b/runtime/interpreter/mterp/x86/op_unused_f4.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..09229d6d99f58a24b923c56b2937662a10e16de6 100644
--- a/runtime/interpreter/mterp/x86/op_unused_f4.S
+++ b/runtime/interpreter/mterp/x86/op_unused_f4.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_f4():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_f5.S b/runtime/interpreter/mterp/x86/op_unused_f5.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..0d6149b5fd6eeb0221067adb660d453080ba1fd2 100644
--- a/runtime/interpreter/mterp/x86/op_unused_f5.S
+++ b/runtime/interpreter/mterp/x86/op_unused_f5.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_f5():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_f6.S b/runtime/interpreter/mterp/x86/op_unused_f6.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..117b03de6d321ace7f917fe69b79b9f182081e11 100644
--- a/runtime/interpreter/mterp/x86/op_unused_f6.S
+++ b/runtime/interpreter/mterp/x86/op_unused_f6.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_f6():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_f7.S b/runtime/interpreter/mterp/x86/op_unused_f7.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..4e3a0f3c9a6eef078506555805a72056272abfc1 100644
--- a/runtime/interpreter/mterp/x86/op_unused_f7.S
+++ b/runtime/interpreter/mterp/x86/op_unused_f7.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_f7():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_f8.S b/runtime/interpreter/mterp/x86/op_unused_f8.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..d1220752d7b5b191c0712bf975e90ac7777e4303 100644
--- a/runtime/interpreter/mterp/x86/op_unused_f8.S
+++ b/runtime/interpreter/mterp/x86/op_unused_f8.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_f8():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_f9.S b/runtime/interpreter/mterp/x86/op_unused_f9.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..7d09a0ebcfce77f4a1bd8b19865ac5d782e382dd 100644
--- a/runtime/interpreter/mterp/x86/op_unused_f9.S
+++ b/runtime/interpreter/mterp/x86/op_unused_f9.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_f9():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_fc.S b/runtime/interpreter/mterp/x86/op_unused_fc.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..06978191ebbcceb51b9820b3e650a0baf767a507 100644
--- a/runtime/interpreter/mterp/x86/op_unused_fc.S
+++ b/runtime/interpreter/mterp/x86/op_unused_fc.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_fc():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_unused_fd.S b/runtime/interpreter/mterp/x86/op_unused_fd.S
index 31d98c1f3976aba75092829d6a05e76dd485d56b..4bc2b4bdb6516467406cb88476e1d993a3f0c749 100644
--- a/runtime/interpreter/mterp/x86/op_unused_fd.S
+++ b/runtime/interpreter/mterp/x86/op_unused_fd.S
@@ -1 +1,2 @@
-%include "x86/unused.S"
+%def op_unused_fd():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86/op_ushr_int.S b/runtime/interpreter/mterp/x86/op_ushr_int.S
index dfe25ff05df2b02874dc0a89885d29c439f4afc0..38c8782ca9b132a3ae910d37db37ad2565a4d170 100644
--- a/runtime/interpreter/mterp/x86/op_ushr_int.S
+++ b/runtime/interpreter/mterp/x86/op_ushr_int.S
@@ -1 +1,2 @@
-%include "x86/binop1.S" {"instr":"shrl    %cl, %eax"}
+%def op_ushr_int():
+%  binop1(instr="shrl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S b/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S
index c14bc980ba142cb95fe4a843b08d39180b39cfdf..f1da71a47af2dd3d132afc76f399a6ab14542ad8 100644
--- a/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S
@@ -1 +1,2 @@
-%include "x86/shop2addr.S" {"instr":"shrl    %cl, %eax"}
+%def op_ushr_int_2addr():
+%  shop2addr(instr="shrl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S b/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S
index e129f6bbe6574cd446966a1a9c46fea5dd642a20..4298d36c3d223dc938e55d5899e91d49064a553a 100644
--- a/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S
+++ b/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S
@@ -1 +1,2 @@
-%include "x86/binopLit8.S" {"instr":"shrl    %cl, %eax"}
+%def op_ushr_int_lit8():
+%  binopLit8(instr="shrl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_ushr_long.S b/runtime/interpreter/mterp/x86/op_ushr_long.S
index 9527c9c2e465d93badec3b6a4bdc3188b0fcb07c..5837a9a79293f511da29c2fbebf9cb7259eae016 100644
--- a/runtime/interpreter/mterp/x86/op_ushr_long.S
+++ b/runtime/interpreter/mterp/x86/op_ushr_long.S
@@ -1,3 +1,4 @@
+%def op_ushr_long():
 /*
  * Long integer shift.  This is different from the generic 32/64-bit
  * binary operations because vAA/vBB are 64-bit but vCC (the shift
diff --git a/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S b/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S
index 72fcc36fffeefc40fbd4467edd7f44993c03b67f..f07318aeb9827dac30effeea72773d710724e5e0 100644
--- a/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_ushr_long_2addr():
 /*
  * Long integer shift, 2addr version.  vA is 64-bit value/result, vB is
  * 32-bit shift distance.
diff --git a/runtime/interpreter/mterp/x86/op_xor_int.S b/runtime/interpreter/mterp/x86/op_xor_int.S
index 35aca6a821ae907cfc1973a3cb0d7be68844f6c2..351d73ae9d362c7b3a364048f009aea7dcea15ab 100644
--- a/runtime/interpreter/mterp/x86/op_xor_int.S
+++ b/runtime/interpreter/mterp/x86/op_xor_int.S
@@ -1 +1,2 @@
-%include "x86/binop.S" {"instr":"xorl    (rFP,%ecx,4), %eax"}
+%def op_xor_int():
+%  binop(instr="xorl    (rFP,%ecx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86/op_xor_int_2addr.S b/runtime/interpreter/mterp/x86/op_xor_int_2addr.S
index d7b70e2ea1cb23ba95143fb7e0a3f3ea03ce674d..daeebed8665499b73c5e0fee12ff1c0e5a7c1338 100644
--- a/runtime/interpreter/mterp/x86/op_xor_int_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_xor_int_2addr.S
@@ -1 +1,2 @@
-%include "x86/binop2addr.S" {"instr":"xorl    %eax, (rFP,%ecx,4)"}
+%def op_xor_int_2addr():
+%  binop2addr(instr="xorl    %eax, (rFP,%ecx,4)")
diff --git a/runtime/interpreter/mterp/x86/op_xor_int_lit16.S b/runtime/interpreter/mterp/x86/op_xor_int_lit16.S
index 115f0a0410a9367dccb16d37e265eaddeff10d8c..f5dc00e074397b774b0fe2b03ac7795873f15bd1 100644
--- a/runtime/interpreter/mterp/x86/op_xor_int_lit16.S
+++ b/runtime/interpreter/mterp/x86/op_xor_int_lit16.S
@@ -1 +1,2 @@
-%include "x86/binopLit16.S" {"instr":"xorl    %ecx, %eax"}
+%def op_xor_int_lit16():
+%  binopLit16(instr="xorl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_xor_int_lit8.S b/runtime/interpreter/mterp/x86/op_xor_int_lit8.S
index 243971c5494b1cdfecdd6089967608a89748e0f8..98a1a432dd16b3e07fc2dc844659d80892a646e3 100644
--- a/runtime/interpreter/mterp/x86/op_xor_int_lit8.S
+++ b/runtime/interpreter/mterp/x86/op_xor_int_lit8.S
@@ -1 +1,2 @@
-%include "x86/binopLit8.S" {"instr":"xorl    %ecx, %eax"}
+%def op_xor_int_lit8():
+%  binopLit8(instr="xorl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86/op_xor_long.S b/runtime/interpreter/mterp/x86/op_xor_long.S
index 0d3c0f5cac50190406e8e1de47f152c7d438ce8a..cc749e66c79bf1c8b02a54063f486f87f37857a1 100644
--- a/runtime/interpreter/mterp/x86/op_xor_long.S
+++ b/runtime/interpreter/mterp/x86/op_xor_long.S
@@ -1 +1,2 @@
-%include "x86/binopWide.S" {"instr1":"xorl    (rFP,%ecx,4), rIBASE", "instr2":"xorl    4(rFP,%ecx,4), %eax"}
+%def op_xor_long():
+%  binopWide(instr1="xorl    (rFP,%ecx,4), rIBASE", instr2="xorl    4(rFP,%ecx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86/op_xor_long_2addr.S b/runtime/interpreter/mterp/x86/op_xor_long_2addr.S
index b5000e44268b03e90b9f387f5ed45b7c822d16df..3aa92357a9d6c2ccba026ce6eb2b74d619214313 100644
--- a/runtime/interpreter/mterp/x86/op_xor_long_2addr.S
+++ b/runtime/interpreter/mterp/x86/op_xor_long_2addr.S
@@ -1 +1,2 @@
-%include "x86/binopWide2addr.S" {"instr1":"xorl    %eax, (rFP,rINST,4)","instr2":"xorl    %ecx, 4(rFP,rINST,4)"}
+%def op_xor_long_2addr():
+%  binopWide2addr(instr1="xorl    %eax, (rFP,rINST,4)", instr2="xorl    %ecx, 4(rFP,rINST,4)")
diff --git a/runtime/interpreter/mterp/x86/shop2addr.S b/runtime/interpreter/mterp/x86/shop2addr.S
index 96c9954d2162b62b29401036c6eaf1680cdc7550..9a57677832e776f4bc072bde954aed8ebe941e9e 100644
--- a/runtime/interpreter/mterp/x86/shop2addr.S
+++ b/runtime/interpreter/mterp/x86/shop2addr.S
@@ -1,4 +1,4 @@
-%default {"result":"%eax"}
+%def shop2addr(result="%eax", instr=""):
 /*
  * Generic 32-bit "shift/2addr" operation.
  */
diff --git a/runtime/interpreter/mterp/x86/sseBinop.S b/runtime/interpreter/mterp/x86/sseBinop.S
index 63a1e21a8f745582486223733472ab0f20270150..a20db7cc2b2f131c1a8d6a97da89b57f2330e1d2 100644
--- a/runtime/interpreter/mterp/x86/sseBinop.S
+++ b/runtime/interpreter/mterp/x86/sseBinop.S
@@ -1,4 +1,4 @@
-%default {"instr":"","suff":""}
+%def sseBinop(instr="", suff=""):
     movzbl  2(rPC), %ecx                    # ecx <- BB
     movzbl  3(rPC), %eax                    # eax <- CC
     movs${suff}   VREG_ADDRESS(%ecx), %xmm0  # %xmm0 <- 1st src
diff --git a/runtime/interpreter/mterp/x86/sseBinop2Addr.S b/runtime/interpreter/mterp/x86/sseBinop2Addr.S
index d157e67b91924699f40248f7b1dbc0ca3c082aef..1186fb7c2ced2616b4f15eec294581c2db2a982e 100644
--- a/runtime/interpreter/mterp/x86/sseBinop2Addr.S
+++ b/runtime/interpreter/mterp/x86/sseBinop2Addr.S
@@ -1,4 +1,4 @@
-%default {"instr":"","suff":""}
+%def sseBinop2Addr(instr="", suff=""):
     movzx   rINSTbl, %ecx                   # ecx <- A+
     andl    $$0xf, %ecx                     # ecx <- A
     movs${suff} VREG_ADDRESS(%ecx), %xmm0      # %xmm0 <- 1st src
diff --git a/runtime/interpreter/mterp/x86/unop.S b/runtime/interpreter/mterp/x86/unop.S
index db09fc04879ff7b670a943f1c2c004d28a728107..5594cb9e1bfccef2124f2dea7f0ed6dab9db704c 100644
--- a/runtime/interpreter/mterp/x86/unop.S
+++ b/runtime/interpreter/mterp/x86/unop.S
@@ -1,4 +1,4 @@
-%default {"instr":""}
+%def unop(instr=""):
 /*
  * Generic 32-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
diff --git a/runtime/interpreter/mterp/x86/unused.S b/runtime/interpreter/mterp/x86/unused.S
index c95ef947d3c4187addee86d70f601836922c05c4..ef35b6e73f3cadbecbcec84a9dba917e80f4adc8 100644
--- a/runtime/interpreter/mterp/x86/unused.S
+++ b/runtime/interpreter/mterp/x86/unused.S
@@ -1,3 +1,4 @@
+%def unused():
 /*
  * Bail to reference interpreter to throw.
  */
diff --git a/runtime/interpreter/mterp/x86/zcmp.S b/runtime/interpreter/mterp/x86/zcmp.S
index c1161591c6262d3e718e493784e4228b78a710b2..120f1ed94984bf66aa5d9b3c8cb8e0404b68bfaf 100644
--- a/runtime/interpreter/mterp/x86/zcmp.S
+++ b/runtime/interpreter/mterp/x86/zcmp.S
@@ -1,3 +1,4 @@
+%def zcmp(revcmp=""):
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
diff --git a/runtime/interpreter/mterp/x86_64/alt_stub.S b/runtime/interpreter/mterp/x86_64/alt_stub.S
index 24cd1a821d465bb0870c78907b2b8db94ad02b76..0c71716e22b76767c2b28a465e899e2712512169 100644
--- a/runtime/interpreter/mterp/x86_64/alt_stub.S
+++ b/runtime/interpreter/mterp/x86_64/alt_stub.S
@@ -1,3 +1,4 @@
+%def alt_stub():
 /*
  * Inter-instruction transfer stub.  Call out to MterpCheckBefore to handle
  * any interesting requests and then jump to the real instruction
diff --git a/runtime/interpreter/mterp/x86_64/bincmp.S b/runtime/interpreter/mterp/x86_64/bincmp.S
index 6601483ebe177cd54800cc340edf45dc6cce0cb2..64a118c10378902fb0d9620613c08f9a9048e7ac 100644
--- a/runtime/interpreter/mterp/x86_64/bincmp.S
+++ b/runtime/interpreter/mterp/x86_64/bincmp.S
@@ -1,3 +1,4 @@
+%def bincmp(revcmp=""):
 /*
  * Generic two-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.
diff --git a/runtime/interpreter/mterp/x86_64/bindiv.S b/runtime/interpreter/mterp/x86_64/bindiv.S
index e10d1dc4b10094c4a99b6a31df435fc1091e6362..d7e5333af6f457a71fe9e9b5f99a2dcd6079c1e1 100644
--- a/runtime/interpreter/mterp/x86_64/bindiv.S
+++ b/runtime/interpreter/mterp/x86_64/bindiv.S
@@ -1,4 +1,4 @@
-%default {"result":"","second":"","wide":"","suffix":"","rem":"0","ext":"cdq"}
+%def bindiv(result="", second="", wide="", suffix="", rem="0", ext="cdq"):
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
diff --git a/runtime/interpreter/mterp/x86_64/bindiv2addr.S b/runtime/interpreter/mterp/x86_64/bindiv2addr.S
index 8b9bc953d2e6591f1551b6a159b9bde61c2f4429..c55351ecb0074732e41fec6bbb158e50b0f5ec92 100644
--- a/runtime/interpreter/mterp/x86_64/bindiv2addr.S
+++ b/runtime/interpreter/mterp/x86_64/bindiv2addr.S
@@ -1,4 +1,4 @@
-%default {"result":"","second":"","wide":"","suffix":"","rem":"0","ext":"cdq"}
+%def bindiv2addr(result="", second="", wide="", suffix="", rem="0", ext="cdq"):
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
diff --git a/runtime/interpreter/mterp/x86_64/bindivLit16.S b/runtime/interpreter/mterp/x86_64/bindivLit16.S
index 80dbce297549f5b192b03beffeae28237347e011..dbda8343317c3ac45cfaa361a6246ee0396178d9 100644
--- a/runtime/interpreter/mterp/x86_64/bindivLit16.S
+++ b/runtime/interpreter/mterp/x86_64/bindivLit16.S
@@ -1,4 +1,4 @@
-%default {"result":"","rem":"0"}
+%def bindivLit16(result="", rem="0"):
 /*
  * 32-bit binary div/rem operation.  Handles special case of op1=-1.
  */
diff --git a/runtime/interpreter/mterp/x86_64/bindivLit8.S b/runtime/interpreter/mterp/x86_64/bindivLit8.S
index ab535f3fb0a564e1f06e21ada90f7b87d5597971..a5164b5021934165aa837322a6d22af34e1e83cb 100644
--- a/runtime/interpreter/mterp/x86_64/bindivLit8.S
+++ b/runtime/interpreter/mterp/x86_64/bindivLit8.S
@@ -1,4 +1,4 @@
-%default {"result":"","rem":"0"}
+%def bindivLit8(result="", rem="0"):
 /*
  * 32-bit div/rem "lit8" binary operation.  Handles special case of
  * op0=minint & op1=-1
diff --git a/runtime/interpreter/mterp/x86_64/binop.S b/runtime/interpreter/mterp/x86_64/binop.S
index 962dd61eea875919314693b1121ab165b7705813..fddeaa182659b078508dd9e585403ff64e1f325b 100644
--- a/runtime/interpreter/mterp/x86_64/binop.S
+++ b/runtime/interpreter/mterp/x86_64/binop.S
@@ -1,4 +1,4 @@
-%default {"result":"%eax"}
+%def binop(result="%eax", instr=""):
 /*
  * Generic 32-bit binary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
diff --git a/runtime/interpreter/mterp/x86_64/binop1.S b/runtime/interpreter/mterp/x86_64/binop1.S
index bdd57325aadaf04611b72eb1dfa41dd224ad36d0..9915c32fbf06a3ca2bea29b4727411e983661ed3 100644
--- a/runtime/interpreter/mterp/x86_64/binop1.S
+++ b/runtime/interpreter/mterp/x86_64/binop1.S
@@ -1,4 +1,4 @@
-%default {"wide":"0"}
+%def binop1(wide="0", instr=""):
 /*
  * Generic 32-bit binary operation in which both operands loaded to
  * registers (op0 in eax, op1 in ecx).
diff --git a/runtime/interpreter/mterp/x86_64/binop2addr.S b/runtime/interpreter/mterp/x86_64/binop2addr.S
index 4448a815e99cee6ae86bbd36cafe350c973aa996..1cdf7fd401f8c4ebd5d6141d8f64ee9956653327 100644
--- a/runtime/interpreter/mterp/x86_64/binop2addr.S
+++ b/runtime/interpreter/mterp/x86_64/binop2addr.S
@@ -1,4 +1,4 @@
-%default {"result":"%eax"}
+%def binop2addr(result="%eax", instr=""):
 /*
  * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = r0 op r1".
diff --git a/runtime/interpreter/mterp/x86_64/binopLit16.S b/runtime/interpreter/mterp/x86_64/binopLit16.S
index de43b53d5cb3615f6a29895dafec80d11e80e656..bb882cba7573f230fdffec715135a5aa6b327f4d 100644
--- a/runtime/interpreter/mterp/x86_64/binopLit16.S
+++ b/runtime/interpreter/mterp/x86_64/binopLit16.S
@@ -1,4 +1,4 @@
-%default {"result":"%eax"}
+%def binopLit16(result="%eax", instr=""):
 /*
  * Generic 32-bit "lit16" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
diff --git a/runtime/interpreter/mterp/x86_64/binopLit8.S b/runtime/interpreter/mterp/x86_64/binopLit8.S
index 995002b7e45caa3161910f8c8d4bd590a91d618b..a30d2e8ed28e42bd769fdb7c9b45d0f99e41277e 100644
--- a/runtime/interpreter/mterp/x86_64/binopLit8.S
+++ b/runtime/interpreter/mterp/x86_64/binopLit8.S
@@ -1,4 +1,4 @@
-%default {"result":"%eax"}
+%def binopLit8(result="%eax", instr=""):
 /*
  * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
  * that specifies an instruction that performs "result = eax op ecx".
diff --git a/runtime/interpreter/mterp/x86_64/binopWide.S b/runtime/interpreter/mterp/x86_64/binopWide.S
index f92f18e013a6b46c99c8319a3f991538fd78e65e..015d9eef419eddc671efd4894a667082f80541b1 100644
--- a/runtime/interpreter/mterp/x86_64/binopWide.S
+++ b/runtime/interpreter/mterp/x86_64/binopWide.S
@@ -1,3 +1,4 @@
+%def binopWide(instr=""):
 /*
  * Generic 64-bit binary operation.
  */
diff --git a/runtime/interpreter/mterp/x86_64/binopWide2addr.S b/runtime/interpreter/mterp/x86_64/binopWide2addr.S
index d9e6cfbc9dc05700f635886bf6dda83dd3ec50a2..e4c1e4da73ec52c5056b5267c2b85beed2417d55 100644
--- a/runtime/interpreter/mterp/x86_64/binopWide2addr.S
+++ b/runtime/interpreter/mterp/x86_64/binopWide2addr.S
@@ -1,3 +1,4 @@
+%def binopWide2addr(instr=""):
 /*
  * Generic 64-bit binary operation.
  */
diff --git a/runtime/interpreter/mterp/x86_64/const.S b/runtime/interpreter/mterp/x86_64/const.S
index 1ddf20fdca66ab4bdd02920b6d77adcacf01442a..fa98637a29ec4e70df7fafcbdf05b4a2ff8ec992 100644
--- a/runtime/interpreter/mterp/x86_64/const.S
+++ b/runtime/interpreter/mterp/x86_64/const.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedConstHandler" }
+%def const(helper="UndefinedConstHandler"):
     /* const/class vAA, type@BBBB */
     /* const/method-handle vAA, method_handle@BBBB */
     /* const/method-type vAA, proto@BBBB */
diff --git a/runtime/interpreter/mterp/x86_64/cvtfp_int.S b/runtime/interpreter/mterp/x86_64/cvtfp_int.S
index 1472bd26bd5f13ee9cab83fd374aaa87be6edf36..e18986f0dbd4775765e5edc98d5005c39daf8f7f 100644
--- a/runtime/interpreter/mterp/x86_64/cvtfp_int.S
+++ b/runtime/interpreter/mterp/x86_64/cvtfp_int.S
@@ -1,4 +1,4 @@
-%default {"fp_suffix":"","i_suffix":"","max_const":"","result_reg":"","wide":""}
+%def cvtfp_int(fp_suffix="", i_suffix="", max_const="", result_reg="", wide=""):
 /* On fp to int conversions, Java requires that
  * if the result > maxint, it should be clamped to maxint.  If it is less
  * than minint, it should be clamped to minint.  If it is a nan, the result
diff --git a/runtime/interpreter/mterp/x86_64/entry.S b/runtime/interpreter/mterp/x86_64/entry.S
index b08419b2199c410a24af64ea5ba2c63c3ba69bdb..515ffbc3ea707fdff044db19edf59137e324d869 100644
--- a/runtime/interpreter/mterp/x86_64/entry.S
+++ b/runtime/interpreter/mterp/x86_64/entry.S
@@ -1,3 +1,4 @@
+%def entry():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
diff --git a/runtime/interpreter/mterp/x86_64/fallback.S b/runtime/interpreter/mterp/x86_64/fallback.S
index 8d61166f63d57a950db9bb1e3bceef3edb6a8374..e3c2e2bd40c3cc11f26d20119106d2b881821094 100644
--- a/runtime/interpreter/mterp/x86_64/fallback.S
+++ b/runtime/interpreter/mterp/x86_64/fallback.S
@@ -1,3 +1,4 @@
+%def fallback():
 /* Transfer stub to alternate interpreter */
     jmp     MterpFallback
 
diff --git a/runtime/interpreter/mterp/x86_64/field.S b/runtime/interpreter/mterp/x86_64/field.S
index f8b0588e1be4ace13dfa41b43e8e29449cc175fc..f6c40eb22444d04e45aa1c1a8c8728695c4316a8 100644
--- a/runtime/interpreter/mterp/x86_64/field.S
+++ b/runtime/interpreter/mterp/x86_64/field.S
@@ -1,4 +1,4 @@
-%default { }
+%def field(helper=""):
     /*
      * General field read / write (iget-* iput-* sget-* sput-*).
      */
diff --git a/runtime/interpreter/mterp/x86_64/footer.S b/runtime/interpreter/mterp/x86_64/footer.S
index 3cc75321cf4ff1d6f47d588085d6ee4f30c728b7..140fbaed497d0c01c92efefff4d5d93c8e830e71 100644
--- a/runtime/interpreter/mterp/x86_64/footer.S
+++ b/runtime/interpreter/mterp/x86_64/footer.S
@@ -1,3 +1,4 @@
+%def footer():
 /*
  * ===========================================================================
  *  Common subroutines and data
diff --git a/runtime/interpreter/mterp/x86_64/fpcmp.S b/runtime/interpreter/mterp/x86_64/fpcmp.S
index 806bc2b1ef392193748e8caf680b227f45f1dba9..15161c8bf1a13288307c5005fb4f043252e8b385 100644
--- a/runtime/interpreter/mterp/x86_64/fpcmp.S
+++ b/runtime/interpreter/mterp/x86_64/fpcmp.S
@@ -1,4 +1,4 @@
-%default {"suff":"d","nanval":"pos"}
+%def fpcmp(suff="d", nanval="pos"):
 /*
  * Compare two floating-point values.  Puts 0, 1, or -1 into the
  * destination register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/x86_64/fpcvt.S b/runtime/interpreter/mterp/x86_64/fpcvt.S
index 657869e0bdd60e5df4ce942f57df29d03f26d308..6647ff369cc0d925c0b813549726f78dc73e46c1 100644
--- a/runtime/interpreter/mterp/x86_64/fpcvt.S
+++ b/runtime/interpreter/mterp/x86_64/fpcvt.S
@@ -1,4 +1,4 @@
-%default {"source_suffix":"","dest_suffix":"","wide":""}
+%def fpcvt(source_suffix="", dest_suffix="", wide=""):
 /*
  * Generic 32-bit FP conversion operation.
  */
diff --git a/runtime/interpreter/mterp/x86_64/header.S b/runtime/interpreter/mterp/x86_64/header.S
index 0332ce272c8fa6ed2803163fc673b37a776ca7ba..44ece2e42c46e6d326520da670e3e19057d9c997 100644
--- a/runtime/interpreter/mterp/x86_64/header.S
+++ b/runtime/interpreter/mterp/x86_64/header.S
@@ -1,3 +1,4 @@
+%def header():
 /*
  * Copyright (C) 2016 The Android Open Source Project
  *
diff --git a/runtime/interpreter/mterp/x86_64/instruction_end.S b/runtime/interpreter/mterp/x86_64/instruction_end.S
index 94587f83b7ece94acc81c162b24242ca73dbf6a8..5a24b66decca371073500034a552ba621bd6137a 100644
--- a/runtime/interpreter/mterp/x86_64/instruction_end.S
+++ b/runtime/interpreter/mterp/x86_64/instruction_end.S
@@ -1,3 +1,4 @@
+%def instruction_end():
 
     OBJECT_TYPE(artMterpAsmInstructionEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd)
diff --git a/runtime/interpreter/mterp/x86_64/instruction_end_alt.S b/runtime/interpreter/mterp/x86_64/instruction_end_alt.S
index 7757bce9a7eba09c81d13bb34be3356a1c0813d8..d037db988c668c05844c8eb65ce1920647270f21 100644
--- a/runtime/interpreter/mterp/x86_64/instruction_end_alt.S
+++ b/runtime/interpreter/mterp/x86_64/instruction_end_alt.S
@@ -1,3 +1,4 @@
+%def instruction_end_alt():
 
     OBJECT_TYPE(artMterpAsmAltInstructionEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd)
diff --git a/runtime/interpreter/mterp/x86_64/instruction_end_sister.S b/runtime/interpreter/mterp/x86_64/instruction_end_sister.S
index 8eb79accdf82bd257721ba37a04ed9319d23c36b..7b1ec89d60e578f4412a00178d0b519bb30de1e5 100644
--- a/runtime/interpreter/mterp/x86_64/instruction_end_sister.S
+++ b/runtime/interpreter/mterp/x86_64/instruction_end_sister.S
@@ -1,3 +1,4 @@
+%def instruction_end_sister():
 
     OBJECT_TYPE(artMterpAsmSisterEnd)
     ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd)
diff --git a/runtime/interpreter/mterp/x86_64/instruction_start.S b/runtime/interpreter/mterp/x86_64/instruction_start.S
index 5d29a8199373e2abfc49b32baf183107a96b3c1d..dee581b60f05ee71d567a2acaa17f7f72163e1d0 100644
--- a/runtime/interpreter/mterp/x86_64/instruction_start.S
+++ b/runtime/interpreter/mterp/x86_64/instruction_start.S
@@ -1,3 +1,4 @@
+%def instruction_start():
 
     OBJECT_TYPE(artMterpAsmInstructionStart)
     ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart)
diff --git a/runtime/interpreter/mterp/x86_64/instruction_start_alt.S b/runtime/interpreter/mterp/x86_64/instruction_start_alt.S
index 8dcf5bfaf95be22f84f4e8670a19a56d7b9a2d46..66650e7a6e69cbce9a8499c347dee7dc04d857b5 100644
--- a/runtime/interpreter/mterp/x86_64/instruction_start_alt.S
+++ b/runtime/interpreter/mterp/x86_64/instruction_start_alt.S
@@ -1,3 +1,4 @@
+%def instruction_start_alt():
 
     OBJECT_TYPE(artMterpAsmAltInstructionStart)
     ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart)
diff --git a/runtime/interpreter/mterp/x86_64/instruction_start_sister.S b/runtime/interpreter/mterp/x86_64/instruction_start_sister.S
index 796e98b09a4ca70adac9aa64992c0928fce7229e..8c156adf7e188b93cd598d64ab349621e8877c83 100644
--- a/runtime/interpreter/mterp/x86_64/instruction_start_sister.S
+++ b/runtime/interpreter/mterp/x86_64/instruction_start_sister.S
@@ -1,3 +1,4 @@
+%def instruction_start_sister():
 
     OBJECT_TYPE(artMterpAsmSisterStart)
     ASM_HIDDEN SYMBOL(artMterpAsmSisterStart)
diff --git a/runtime/interpreter/mterp/x86_64/invoke.S b/runtime/interpreter/mterp/x86_64/invoke.S
index f7e6155c161db943fe415f12ab937aa05a88a7ac..42b50f269ecc59fb7388f8b6200f350f97c5d278 100644
--- a/runtime/interpreter/mterp/x86_64/invoke.S
+++ b/runtime/interpreter/mterp/x86_64/invoke.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke(helper="UndefinedInvokeHandler"):
 /*
  * Generic invoke handler wrapper.
  */
diff --git a/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S b/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S
index 5157860b376b8890f314f336341c157efcb69bad..18fd5e61250b713696340e928ecb4387961aea01 100644
--- a/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S
@@ -1,4 +1,4 @@
-%default { "helper":"UndefinedInvokeHandler" }
+%def invoke_polymorphic(helper="UndefinedInvokeHandler"):
     /*
      * invoke-polymorphic handler wrapper.
      */
diff --git a/runtime/interpreter/mterp/x86_64/op_add_double.S b/runtime/interpreter/mterp/x86_64/op_add_double.S
index cb462cb816224e5f19a6471fd222ab7a866f690e..a00923928b59cc7aef30983b49743a3a7506646e 100644
--- a/runtime/interpreter/mterp/x86_64/op_add_double.S
+++ b/runtime/interpreter/mterp/x86_64/op_add_double.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop.S" {"instr":"adds","suff":"d"}
+%def op_add_double():
+%  sseBinop(instr="adds", suff="d")
diff --git a/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S
index 063bde3fb3b5f88f06e35e36745e6046e7cbdb15..8cb45a9a202a163d2b563fa3bb37af08d420503f 100644
--- a/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop2Addr.S" {"instr":"adds","suff":"d"}
+%def op_add_double_2addr():
+%  sseBinop2Addr(instr="adds", suff="d")
diff --git a/runtime/interpreter/mterp/x86_64/op_add_float.S b/runtime/interpreter/mterp/x86_64/op_add_float.S
index 7753bf88702c879997680f3be5f3abc60929ca06..dee28c7b8bce8901043dde115e81a94d4b69a695 100644
--- a/runtime/interpreter/mterp/x86_64/op_add_float.S
+++ b/runtime/interpreter/mterp/x86_64/op_add_float.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop.S" {"instr":"adds","suff":"s"}
+%def op_add_float():
+%  sseBinop(instr="adds", suff="s")
diff --git a/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S
index 6c8005b1822c8b406efc37202c38397d412ceae2..4deb4451ce3d3db4cf944be31161e1070c8b2fc5 100644
--- a/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop2Addr.S" {"instr":"adds","suff":"s"}
+%def op_add_float_2addr():
+%  sseBinop2Addr(instr="adds", suff="s")
diff --git a/runtime/interpreter/mterp/x86_64/op_add_int.S b/runtime/interpreter/mterp/x86_64/op_add_int.S
index e316be7b9dcb32f7d7a26cfdeaad3b13fa5c8515..aaf0b35b57934c2c62bab77c852c8fdc2ef58c69 100644
--- a/runtime/interpreter/mterp/x86_64/op_add_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_add_int.S
@@ -1 +1,2 @@
-%include "x86_64/binop.S" {"instr":"addl    (rFP,%rcx,4), %eax"}
+%def op_add_int():
+%  binop(instr="addl    (rFP,%rcx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S
index 2ff82935ae87efc82f476bbbd167f740ec6850fd..8ce26f6e7165cba4d4a42ba3bfba6847bf40db6c 100644
--- a/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/binop2addr.S" {"instr":"addl    %eax, (rFP,%rcx,4)"}
+%def op_add_int_2addr():
+%  binop2addr(instr="addl    %eax, (rFP,%rcx,4)")
diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S
index bfeb7caabcb03a0f6387f93985f8512448046a6e..a43103019e65b948d4b81072164ada0f15982e0b 100644
--- a/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S
+++ b/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit16.S" {"instr":"addl    %ecx, %eax"}
+%def op_add_int_lit16():
+%  binopLit16(instr="addl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S
index 8954844eae0f0f2e449f07de13184447f59b0968..3205aee0cb35ef38c13eb4604053ae202072f85f 100644
--- a/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S
+++ b/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit8.S" {"instr":"addl    %ecx, %eax"}
+%def op_add_int_lit8():
+%  binopLit8(instr="addl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_add_long.S b/runtime/interpreter/mterp/x86_64/op_add_long.S
index 89131ffe0e8e3f73a9314d6ea9b3988515e7d49e..fac8163f4b6ee3d5032e9615ebd65792763cc2ac 100644
--- a/runtime/interpreter/mterp/x86_64/op_add_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_add_long.S
@@ -1 +1,2 @@
-%include "x86_64/binopWide.S" {"instr":"addq    (rFP,%rcx,4), %rax"}
+%def op_add_long():
+%  binopWide(instr="addq    (rFP,%rcx,4), %rax")
diff --git a/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S
index fed98bc3e688f5bcc7048adf63a61e83b7b20fe3..17684e6b2b43a530485932719778723be37f79f0 100644
--- a/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/binopWide2addr.S" {"instr":"addq    %rax, (rFP,%rcx,4)"}
+%def op_add_long_2addr():
+%  binopWide2addr(instr="addq    %rax, (rFP,%rcx,4)")
diff --git a/runtime/interpreter/mterp/x86_64/op_aget.S b/runtime/interpreter/mterp/x86_64/op_aget.S
index 58d49481cfdeaa164d5dbd19268a7a66926f78f5..b45f43a9abd1e0f04729c378bfd3e6be8bd16f24 100644
--- a/runtime/interpreter/mterp/x86_64/op_aget.S
+++ b/runtime/interpreter/mterp/x86_64/op_aget.S
@@ -1,4 +1,4 @@
-%default { "load":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET", "wide":"0" }
+%def op_aget(load="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET", wide="0"):
 /*
  * Array get, 32 bits or less.  vAA <- vBB[vCC].
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_aget_boolean.S b/runtime/interpreter/mterp/x86_64/op_aget_boolean.S
index cf7bdb582b21c73612d343cbd06d6d3853904278..279e6fc73958331e2d3831cd5e50ddac32a81aaf 100644
--- a/runtime/interpreter/mterp/x86_64/op_aget_boolean.S
+++ b/runtime/interpreter/mterp/x86_64/op_aget_boolean.S
@@ -1 +1,2 @@
-%include "x86_64/op_aget.S" { "load":"movzbl", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aget_boolean():
+%  op_aget(load="movzbl", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86_64/op_aget_byte.S b/runtime/interpreter/mterp/x86_64/op_aget_byte.S
index 1cbb56902498628c451de56f4312c593f37c34f4..19894507437487dadd2d64f15234a815fc2ff5f8 100644
--- a/runtime/interpreter/mterp/x86_64/op_aget_byte.S
+++ b/runtime/interpreter/mterp/x86_64/op_aget_byte.S
@@ -1 +1,2 @@
-%include "x86_64/op_aget.S" { "load":"movsbl", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aget_byte():
+%  op_aget(load="movsbl", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86_64/op_aget_char.S b/runtime/interpreter/mterp/x86_64/op_aget_char.S
index 45c90851fd3308adcfe7a4cf6f48374df60ac31a..a35269bd6522bddc452d6e8d26d09f8196941bb4 100644
--- a/runtime/interpreter/mterp/x86_64/op_aget_char.S
+++ b/runtime/interpreter/mterp/x86_64/op_aget_char.S
@@ -1 +1,2 @@
-%include "x86_64/op_aget.S" { "load":"movzwl", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aget_char():
+%  op_aget(load="movzwl", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86_64/op_aget_object.S b/runtime/interpreter/mterp/x86_64/op_aget_object.S
index 5f77a9774835c4e0155f3f448f0811ca4f9704fc..fc099dc3a273e8ed42b734ce9522a16aed31686a 100644
--- a/runtime/interpreter/mterp/x86_64/op_aget_object.S
+++ b/runtime/interpreter/mterp/x86_64/op_aget_object.S
@@ -1,3 +1,4 @@
+%def op_aget_object():
 /*
  * Array object get.  vAA <- vBB[vCC].
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_aget_short.S b/runtime/interpreter/mterp/x86_64/op_aget_short.S
index 82c4a1ddf34498fbb9b748831a2a7ad80e7483e0..ca51ec80522c9196f466605a913b6a7335605025 100644
--- a/runtime/interpreter/mterp/x86_64/op_aget_short.S
+++ b/runtime/interpreter/mterp/x86_64/op_aget_short.S
@@ -1 +1,2 @@
-%include "x86_64/op_aget.S" { "load":"movswl", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aget_short():
+%  op_aget(load="movswl", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86_64/op_aget_wide.S b/runtime/interpreter/mterp/x86_64/op_aget_wide.S
index 4f2771b9c403c24d158712f6e8de4b640694c670..42513fc19ad338fa1f95ffe3d75c79ee2b235bec 100644
--- a/runtime/interpreter/mterp/x86_64/op_aget_wide.S
+++ b/runtime/interpreter/mterp/x86_64/op_aget_wide.S
@@ -1 +1,2 @@
-%include "x86_64/op_aget.S" { "load":"movq", "shift":"8", "data_offset":"MIRROR_WIDE_ARRAY_DATA_OFFSET", "wide":"1" }
+%def op_aget_wide():
+%  op_aget(load="movq", shift="8", data_offset="MIRROR_WIDE_ARRAY_DATA_OFFSET", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_and_int.S b/runtime/interpreter/mterp/x86_64/op_and_int.S
index 446988993df6db0f10eb63a130ebb08767e7d497..afe2d67047b34ca7d2ed72c40bb3a7fa17b6c80e 100644
--- a/runtime/interpreter/mterp/x86_64/op_and_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_and_int.S
@@ -1 +1,2 @@
-%include "x86_64/binop.S" {"instr":"andl    (rFP,%rcx,4), %eax"}
+%def op_and_int():
+%  binop(instr="andl    (rFP,%rcx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S
index 16315bba0353820ae51fcd87e75303ddcd18e36a..ed9fc654b347af5e0dfb567322a8d8d45d365c11 100644
--- a/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/binop2addr.S" {"instr":"andl    %eax, (rFP,%rcx,4)"}
+%def op_and_int_2addr():
+%  binop2addr(instr="andl    %eax, (rFP,%rcx,4)")
diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S
index 63e851b4497da49bad125313747773e4b52027fa..d7752b1230b67994aacc6527ca72ea06d06928c9 100644
--- a/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S
+++ b/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit16.S" {"instr":"andl    %ecx, %eax"}
+%def op_and_int_lit16():
+%  binopLit16(instr="andl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S
index da7a20fdff904fb3f472455b660dbb324c6d63ba..a353178a884adce00f5d8dc4703657b83fc60ed2 100644
--- a/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S
+++ b/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit8.S" {"instr":"andl    %ecx, %eax"}
+%def op_and_int_lit8():
+%  binopLit8(instr="andl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_and_long.S b/runtime/interpreter/mterp/x86_64/op_and_long.S
index ce1dd264dd55d151b709a6132ac04590a10595c7..7375154bdccca4dd86e58a421720919bd25dbdee 100644
--- a/runtime/interpreter/mterp/x86_64/op_and_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_and_long.S
@@ -1 +1,2 @@
-%include "x86_64/binopWide.S" {"instr":"andq    (rFP,%rcx,4), %rax"}
+%def op_and_long():
+%  binopWide(instr="andq    (rFP,%rcx,4), %rax")
diff --git a/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S
index d17ab8d58bd19921acb98ac127cbd570abcb5bad..41938ac4dcb5761bd0c91fda5d29d138d946ef0f 100644
--- a/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/binopWide2addr.S" {"instr":"andq    %rax, (rFP,%rcx,4)"}
+%def op_and_long_2addr():
+%  binopWide2addr(instr="andq    %rax, (rFP,%rcx,4)")
diff --git a/runtime/interpreter/mterp/x86_64/op_aput.S b/runtime/interpreter/mterp/x86_64/op_aput.S
index 11500ad201dd5166046bd7165174901b73d66085..bef2e2abe75bb52d06599617aaa81b190ec81cef 100644
--- a/runtime/interpreter/mterp/x86_64/op_aput.S
+++ b/runtime/interpreter/mterp/x86_64/op_aput.S
@@ -1,4 +1,4 @@
-%default { "reg":"rINST", "store":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET", "wide":"0" }
+%def op_aput(reg="rINST", store="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET", wide="0"):
 /*
  * Array put, 32 bits or less.  vBB[vCC] <- vAA.
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_aput_boolean.S b/runtime/interpreter/mterp/x86_64/op_aput_boolean.S
index 7d77a865288fe99f9788fb83d45f147a4ba81896..8420b5af8ff4d6d2ec53888b22e6f2859a5b1004 100644
--- a/runtime/interpreter/mterp/x86_64/op_aput_boolean.S
+++ b/runtime/interpreter/mterp/x86_64/op_aput_boolean.S
@@ -1 +1,2 @@
-%include "x86_64/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
+%def op_aput_boolean():
+%  op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86_64/op_aput_byte.S b/runtime/interpreter/mterp/x86_64/op_aput_byte.S
index 7a1723e0fe24a6879ea6a71690eaef0c9ac0d91f..6c181a48d9086e90dba63a4a1cb75f144f00c80d 100644
--- a/runtime/interpreter/mterp/x86_64/op_aput_byte.S
+++ b/runtime/interpreter/mterp/x86_64/op_aput_byte.S
@@ -1 +1,2 @@
-%include "x86_64/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
+%def op_aput_byte():
+%  op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86_64/op_aput_char.S b/runtime/interpreter/mterp/x86_64/op_aput_char.S
index f8f50a3b2e61837196298c2496d3d0305d1335f1..3f4602a7f47d175a054b925515458ef9fa8890f7 100644
--- a/runtime/interpreter/mterp/x86_64/op_aput_char.S
+++ b/runtime/interpreter/mterp/x86_64/op_aput_char.S
@@ -1 +1,2 @@
-%include "x86_64/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
+%def op_aput_char():
+%  op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86_64/op_aput_object.S b/runtime/interpreter/mterp/x86_64/op_aput_object.S
index b1bae0f45758b5740a12035fe6b260707b73a478..cf4bdf1a09d39c4c2654c1e381e9e86622319d7d 100644
--- a/runtime/interpreter/mterp/x86_64/op_aput_object.S
+++ b/runtime/interpreter/mterp/x86_64/op_aput_object.S
@@ -1,3 +1,4 @@
+%def op_aput_object():
 /*
  * Store an object into an array.  vBB[vCC] <- vAA.
  */
diff --git a/runtime/interpreter/mterp/x86_64/op_aput_short.S b/runtime/interpreter/mterp/x86_64/op_aput_short.S
index 481fd6847b7dfe0027f075eb81d2bbb49a6fcc28..e76d83368bf4bd66332e2cdf9eba80d9970814db 100644
--- a/runtime/interpreter/mterp/x86_64/op_aput_short.S
+++ b/runtime/interpreter/mterp/x86_64/op_aput_short.S
@@ -1 +1,2 @@
-%include "x86_64/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
+%def op_aput_short():
+%  op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
diff --git a/runtime/interpreter/mterp/x86_64/op_aput_wide.S b/runtime/interpreter/mterp/x86_64/op_aput_wide.S
index 5bbd39b0b6426c15466d1c18f40cd7baf85d9078..c1ca1ef81c39e8653bf30486f5f4bdf820c2ee8b 100644
--- a/runtime/interpreter/mterp/x86_64/op_aput_wide.S
+++ b/runtime/interpreter/mterp/x86_64/op_aput_wide.S
@@ -1 +1,2 @@
-%include "x86_64/op_aput.S" { "reg":"rINSTq", "store":"movq", "shift":"8", "data_offset":"MIRROR_WIDE_ARRAY_DATA_OFFSET", "wide":"1" }
+%def op_aput_wide():
+%  op_aput(reg="rINSTq", store="movq", shift="8", data_offset="MIRROR_WIDE_ARRAY_DATA_OFFSET", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_array_length.S b/runtime/interpreter/mterp/x86_64/op_array_length.S
index e80d665160ec20cc0b5c88da3f97eb308ecbb1d9..7e6c5c0b5257b2a9ab1424c2f1ac5408e5a8c67c 100644
--- a/runtime/interpreter/mterp/x86_64/op_array_length.S
+++ b/runtime/interpreter/mterp/x86_64/op_array_length.S
@@ -1,3 +1,4 @@
+%def op_array_length():
 /*
  * Return the length of an array.
  */
diff --git a/runtime/interpreter/mterp/x86_64/op_check_cast.S b/runtime/interpreter/mterp/x86_64/op_check_cast.S
index f8fa7b2036e3527b410ef2792b79d7834d4a9041..ac7051b19b82000e46c2d07feedb9672153c3bb5 100644
--- a/runtime/interpreter/mterp/x86_64/op_check_cast.S
+++ b/runtime/interpreter/mterp/x86_64/op_check_cast.S
@@ -1,3 +1,4 @@
+%def op_check_cast():
 /*
  * Check to see if a cast from one class to another is allowed.
  */
diff --git a/runtime/interpreter/mterp/x86_64/op_cmp_long.S b/runtime/interpreter/mterp/x86_64/op_cmp_long.S
index 23ca3e5e6d5f09d30ac6c635fc91b021fee10f00..f222813a02778c474e1472af36f70fa293345663 100644
--- a/runtime/interpreter/mterp/x86_64/op_cmp_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_cmp_long.S
@@ -1,3 +1,4 @@
+%def op_cmp_long():
 /*
  * Compare two 64-bit values.  Puts 0, 1, or -1 into the destination
  * register based on the results of the comparison.
diff --git a/runtime/interpreter/mterp/x86_64/op_cmpg_double.S b/runtime/interpreter/mterp/x86_64/op_cmpg_double.S
index 7c0aa1bdbab7f247e4cdce74788677d924514801..1c04e997f103eb2956adc16d1f21009ea1136b04 100644
--- a/runtime/interpreter/mterp/x86_64/op_cmpg_double.S
+++ b/runtime/interpreter/mterp/x86_64/op_cmpg_double.S
@@ -1 +1,2 @@
-%include "x86_64/fpcmp.S" {"suff":"d","nanval":"pos"}
+%def op_cmpg_double():
+%  fpcmp(suff="d", nanval="pos")
diff --git a/runtime/interpreter/mterp/x86_64/op_cmpg_float.S b/runtime/interpreter/mterp/x86_64/op_cmpg_float.S
index 14e8472672a8f8f5f61ce70347b47f0d2642b6c6..797c3d52d74bfc8b7e448ede512e336dc62286ee 100644
--- a/runtime/interpreter/mterp/x86_64/op_cmpg_float.S
+++ b/runtime/interpreter/mterp/x86_64/op_cmpg_float.S
@@ -1 +1,2 @@
-%include "x86_64/fpcmp.S" {"suff":"s","nanval":"pos"}
+%def op_cmpg_float():
+%  fpcmp(suff="s", nanval="pos")
diff --git a/runtime/interpreter/mterp/x86_64/op_cmpl_double.S b/runtime/interpreter/mterp/x86_64/op_cmpl_double.S
index 1d4c4243ae16cc9489152a487f7b5349ba2a735c..cbe8db713ba806f329b6bd891d5bce475337d110 100644
--- a/runtime/interpreter/mterp/x86_64/op_cmpl_double.S
+++ b/runtime/interpreter/mterp/x86_64/op_cmpl_double.S
@@ -1 +1,2 @@
-%include "x86_64/fpcmp.S" {"suff":"d","nanval":"neg"}
+%def op_cmpl_double():
+%  fpcmp(suff="d", nanval="neg")
diff --git a/runtime/interpreter/mterp/x86_64/op_cmpl_float.S b/runtime/interpreter/mterp/x86_64/op_cmpl_float.S
index 97a12a6a7dd5cc80772f5487c0f4e35ee3711a93..068f4cb5c1f837a1e0edb0aff71bd414b9aa31e5 100644
--- a/runtime/interpreter/mterp/x86_64/op_cmpl_float.S
+++ b/runtime/interpreter/mterp/x86_64/op_cmpl_float.S
@@ -1 +1,2 @@
-%include "x86_64/fpcmp.S" {"suff":"s","nanval":"neg"}
+%def op_cmpl_float():
+%  fpcmp(suff="s", nanval="neg")
diff --git a/runtime/interpreter/mterp/x86_64/op_const.S b/runtime/interpreter/mterp/x86_64/op_const.S
index 3cfafdb13bbd44445ffde9e31038aa99db292c47..36220952bcab9e1dc73b64eca8fb3c6c519195bc 100644
--- a/runtime/interpreter/mterp/x86_64/op_const.S
+++ b/runtime/interpreter/mterp/x86_64/op_const.S
@@ -1,3 +1,4 @@
+%def op_const():
     /* const vAA, #+BBBBbbbb */
     movl    2(rPC), %eax                    # grab all 32 bits at once
     SET_VREG %eax, rINSTq                   # vAA<- eax
diff --git a/runtime/interpreter/mterp/x86_64/op_const_16.S b/runtime/interpreter/mterp/x86_64/op_const_16.S
index 1a139c683e2ff2d03bb90dde630797e608fb31ed..fa86060906ea87b0cf4f607aa7ed0ec7ad66087e 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_16.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_16.S
@@ -1,3 +1,4 @@
+%def op_const_16():
     /* const/16 vAA, #+BBBB */
     movswl  2(rPC), %ecx                    # ecx <- ssssBBBB
     SET_VREG %ecx, rINSTq                   # vAA <- ssssBBBB
diff --git a/runtime/interpreter/mterp/x86_64/op_const_4.S b/runtime/interpreter/mterp/x86_64/op_const_4.S
index 23c4816f8288071cbec7f3f55e60664d015a28c0..9f39ceec49cde46d8ffbbd749187a7860e0d6ff1 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_4.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_4.S
@@ -1,3 +1,4 @@
+%def op_const_4():
     /* const/4 vA, #+B */
     movsbl  rINSTbl, %eax                   # eax <-ssssssBx
     movl    $$0xf, rINST
diff --git a/runtime/interpreter/mterp/x86_64/op_const_class.S b/runtime/interpreter/mterp/x86_64/op_const_class.S
index 0c402e1489e9e1eb985add188985c9350991bbdd..db12ec31414690de6acb180ce962f6676f3ab2f5 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_class.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_class.S
@@ -1 +1,2 @@
-%include "x86_64/const.S" { "helper":"MterpConstClass" }
+%def op_const_class():
+%  const(helper="MterpConstClass")
diff --git a/runtime/interpreter/mterp/x86_64/op_const_high16.S b/runtime/interpreter/mterp/x86_64/op_const_high16.S
index 64e633c7a0d3799206aaca32868f3038c9c8296c..e1e61e387a9ed278ab6584a95127c8abada7b9c2 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_high16.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_high16.S
@@ -1,3 +1,4 @@
+%def op_const_high16():
     /* const/high16 vAA, #+BBBB0000 */
     movzwl  2(rPC), %eax                    # eax <- 0000BBBB
     sall    $$16, %eax                      # eax <- BBBB0000
diff --git a/runtime/interpreter/mterp/x86_64/op_const_method_handle.S b/runtime/interpreter/mterp/x86_64/op_const_method_handle.S
index 2b8b0a258a1440d8613ba119a74c91b76bae0fe8..2680c17aad5d6f537298bc455177da35df137274 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_method_handle.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_method_handle.S
@@ -1 +1,2 @@
-%include "x86_64/const.S" { "helper":"MterpConstMethodHandle" }
+%def op_const_method_handle():
+%  const(helper="MterpConstMethodHandle")
diff --git a/runtime/interpreter/mterp/x86_64/op_const_method_type.S b/runtime/interpreter/mterp/x86_64/op_const_method_type.S
index 33ce952031eb96e7dea978a21923e7cd353319e7..ea814bf64826079ab9f55e43e47f42180c3ad420 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_method_type.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_method_type.S
@@ -1 +1,2 @@
-%include "x86_64/const.S" { "helper":"MterpConstMethodType" }
+%def op_const_method_type():
+%  const(helper="MterpConstMethodType")
diff --git a/runtime/interpreter/mterp/x86_64/op_const_string.S b/runtime/interpreter/mterp/x86_64/op_const_string.S
index 5a29bd3dde28e5ec45de65c45425be5eec092b4c..41376f870340354594a5a218b1d2379e08042008 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_string.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_string.S
@@ -1 +1,2 @@
-%include "x86_64/const.S" { "helper":"MterpConstString" }
+%def op_const_string():
+%  const(helper="MterpConstString")
diff --git a/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S b/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S
index ae03d20f4f17cba3de06bfeda0cee2f8935975de..c12abb114f68eed7506d91d542eac47fd202ca8e 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S
@@ -1,3 +1,4 @@
+%def op_const_string_jumbo():
     /* const/string vAA, String@BBBBBBBB */
     EXPORT_PC
     movl    2(rPC), OUT_32_ARG0             # OUT_32_ARG0 <- BBBB
diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide.S b/runtime/interpreter/mterp/x86_64/op_const_wide.S
index 56151771752cd13efdef2090825c3d6e8c9e7308..f7a74c218a4a09fc9a5ddaff9ff9e1e59203d8d8 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_wide.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_wide.S
@@ -1,3 +1,4 @@
+%def op_const_wide():
     /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
     movq    2(rPC), %rax                    # rax <- HHHHhhhhBBBBbbbb
     SET_WIDE_VREG %rax, rINSTq
diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_16.S b/runtime/interpreter/mterp/x86_64/op_const_wide_16.S
index 593b62466f677a55f65a62138a103deb1019db6d..8d1e17c906dca3c7c178da5e1c1e950dc405967b 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_wide_16.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_wide_16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_16():
     /* const-wide/16 vAA, #+BBBB */
     movswq  2(rPC), %rax                    # rax <- ssssBBBB
     SET_WIDE_VREG %rax, rINSTq              # store
diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_32.S b/runtime/interpreter/mterp/x86_64/op_const_wide_32.S
index 5ef363612973230c8d5477968a2e643002bc1a77..22b807477c7daaf4133f85a47b8649aa7020b72f 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_wide_32.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_wide_32.S
@@ -1,3 +1,4 @@
+%def op_const_wide_32():
     /* const-wide/32 vAA, #+BBBBbbbb */
     movslq   2(rPC), %rax                   # eax <- ssssssssBBBBbbbb
     SET_WIDE_VREG %rax, rINSTq              # store
diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S b/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S
index b86b4e582bb7733c659fd98368fdf946970adabd..d41b02a6b433e8b4e69e79684bc3bcd3f8d71f89 100644
--- a/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S
+++ b/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S
@@ -1,3 +1,4 @@
+%def op_const_wide_high16():
     /* const-wide/high16 vAA, #+BBBB000000000000 */
     movzwq  2(rPC), %rax                    # eax <- 0000BBBB
     salq    $$48, %rax                      # eax <- BBBB0000
diff --git a/runtime/interpreter/mterp/x86_64/op_div_double.S b/runtime/interpreter/mterp/x86_64/op_div_double.S
index 45c700c0667791a5736cec47546439b9d8a9ce6c..6b342f89bf2e3cf6d25b21509a6785241aba15d3 100644
--- a/runtime/interpreter/mterp/x86_64/op_div_double.S
+++ b/runtime/interpreter/mterp/x86_64/op_div_double.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop.S" {"instr":"divs","suff":"d"}
+%def op_div_double():
+%  sseBinop(instr="divs", suff="d")
diff --git a/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S
index 83f270e245b2ddc3317db25d2247cdac080ed456..212c82547efa9b8a7eff14bcc6395951827e2748 100644
--- a/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop2Addr.S" {"instr":"divs","suff":"d"}
+%def op_div_double_2addr():
+%  sseBinop2Addr(instr="divs", suff="d")
diff --git a/runtime/interpreter/mterp/x86_64/op_div_float.S b/runtime/interpreter/mterp/x86_64/op_div_float.S
index aa90b24698859e915198657a39f506481a2d8e49..b6537d9d8911c972bd8ec5366495fc85b7f3675e 100644
--- a/runtime/interpreter/mterp/x86_64/op_div_float.S
+++ b/runtime/interpreter/mterp/x86_64/op_div_float.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop.S" {"instr":"divs","suff":"s"}
+%def op_div_float():
+%  sseBinop(instr="divs", suff="s")
diff --git a/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S
index f0f8f1a6c8636de59341f5293c2d1ba5bf279c88..19ae27d61aa37ac69120d46f1136ae0d56517776 100644
--- a/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop2Addr.S" {"instr":"divs","suff":"s"}
+%def op_div_float_2addr():
+%  sseBinop2Addr(instr="divs", suff="s")
diff --git a/runtime/interpreter/mterp/x86_64/op_div_int.S b/runtime/interpreter/mterp/x86_64/op_div_int.S
index bba5a176a0f9cb039904ad5313747f38854f00eb..cd7f3db9141d37f8972023553fc3ba9a200ba9aa 100644
--- a/runtime/interpreter/mterp/x86_64/op_div_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_div_int.S
@@ -1 +1,2 @@
-%include "x86_64/bindiv.S" {"result":"%eax","second":"%ecx","wide":"0","suffix":"l"}
+%def op_div_int():
+%  bindiv(result="%eax", second="%ecx", wide="0", suffix="l")
diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S
index fa4255ddfa8c13a39bb81b95006ea431db20490b..3a734dbf882ce9064624df3ecd17d0a598836bea 100644
--- a/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/bindiv2addr.S" {"result":"%eax","second":"%ecx","wide":"0","suffix":"l"}
+%def op_div_int_2addr():
+%  bindiv2addr(result="%eax", second="%ecx", wide="0", suffix="l")
diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S
index 3fa1e09fd696ee2bb7214edb012b1bc4534aca68..cdcee2d774eff94c8a8cabbd28a6172d77902b0a 100644
--- a/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S
+++ b/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S
@@ -1 +1,2 @@
-%include "x86_64/bindivLit16.S" {"result":"%eax"}
+%def op_div_int_lit16():
+%  bindivLit16(result="%eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S
index 859883e5c74e7133cf58e68a87f73a6b0d09b4ae..7d258c80db10bb328db4000b155494c9080d3fd3 100644
--- a/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S
+++ b/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S
@@ -1 +1,2 @@
-%include "x86_64/bindivLit8.S" {"result":"%eax"}
+%def op_div_int_lit8():
+%  bindivLit8(result="%eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_div_long.S b/runtime/interpreter/mterp/x86_64/op_div_long.S
index a061a88b135a0b06654041eb64ea18d86c451f71..59f9073087d0fab4fe93290d0b8333185d984648 100644
--- a/runtime/interpreter/mterp/x86_64/op_div_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_div_long.S
@@ -1 +1,2 @@
-%include "x86_64/bindiv.S" {"result":"%rax","second":"%rcx","wide":"1","suffix":"q","ext":"cqo"}
+%def op_div_long():
+%  bindiv(result="%rax", second="%rcx", wide="1", suffix="q", ext="cqo")
diff --git a/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S
index 8886e6824878f445251a054a72ac6735f8a96d5b..d7a46f540cd563ba9d3b046b70c39adea832086a 100644
--- a/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/bindiv2addr.S" {"result":"%rax","second":"%rcx","wide":"1","suffix":"q","ext":"cqo"}
+%def op_div_long_2addr():
+%  bindiv2addr(result="%rax", second="%rcx", wide="1", suffix="q", ext="cqo")
diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_float.S b/runtime/interpreter/mterp/x86_64/op_double_to_float.S
index cea1482038a021322d3b74ff281049b46aaab5b8..e62aa4d2a6ba66edda4075e30aa39ae2629c58cd 100644
--- a/runtime/interpreter/mterp/x86_64/op_double_to_float.S
+++ b/runtime/interpreter/mterp/x86_64/op_double_to_float.S
@@ -1 +1,2 @@
-%include "x86_64/fpcvt.S" {"source_suffix":"d","dest_suffix":"s","wide":"0"}
+%def op_double_to_float():
+%  fpcvt(source_suffix="d", dest_suffix="s", wide="0")
diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_int.S b/runtime/interpreter/mterp/x86_64/op_double_to_int.S
index a9965edcc3fe49784f26675fdba6a3fa7676a005..24fca631b7a5bfca26c592c64b0a5c22bdca60a2 100644
--- a/runtime/interpreter/mterp/x86_64/op_double_to_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_double_to_int.S
@@ -1 +1,2 @@
-%include "x86_64/cvtfp_int.S" {"fp_suffix":"d","i_suffix":"l","max_const":"$0x7fffffff","result_reg":"%eax","wide":"0"}
+%def op_double_to_int():
+%  cvtfp_int(fp_suffix="d", i_suffix="l", max_const="$0x7fffffff", result_reg="%eax", wide="0")
diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_long.S b/runtime/interpreter/mterp/x86_64/op_double_to_long.S
index 179e6a16053779fcbaf69a7e93b53d5b3ed62a10..8f042c0ca10df264f1ff2c475350c3eca491c45f 100644
--- a/runtime/interpreter/mterp/x86_64/op_double_to_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_double_to_long.S
@@ -1 +1,2 @@
-%include "x86_64/cvtfp_int.S" {"fp_suffix":"d","i_suffix":"q","max_const":"$0x7fffffffffffffff","result_reg":"%rax","wide":"1"}
+%def op_double_to_long():
+%  cvtfp_int(fp_suffix="d", i_suffix="q", max_const="$0x7fffffffffffffff", result_reg="%rax", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_fill_array_data.S b/runtime/interpreter/mterp/x86_64/op_fill_array_data.S
index 7ea36a6136df96bc260ab7c27c1ce5cc5870a93e..694ee79bf891bced78521b3bb5421834810a9558 100644
--- a/runtime/interpreter/mterp/x86_64/op_fill_array_data.S
+++ b/runtime/interpreter/mterp/x86_64/op_fill_array_data.S
@@ -1,3 +1,4 @@
+%def op_fill_array_data():
     /* fill-array-data vAA, +BBBBBBBB */
     EXPORT_PC
     movslq  2(rPC), %rcx                    # rcx <- ssssssssBBBBbbbb
diff --git a/runtime/interpreter/mterp/x86_64/op_filled_new_array.S b/runtime/interpreter/mterp/x86_64/op_filled_new_array.S
index a7f7ddc2a0da16d320acf1fd95d2d7626442fe63..0f8b20e6aaf7374fde23cabb65e509082e9057bb 100644
--- a/runtime/interpreter/mterp/x86_64/op_filled_new_array.S
+++ b/runtime/interpreter/mterp/x86_64/op_filled_new_array.S
@@ -1,4 +1,4 @@
-%default { "helper":"MterpFilledNewArray" }
+%def op_filled_new_array(helper="MterpFilledNewArray"):
 /*
  * Create a new array with elements filled from registers.
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S b/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S
index 4ca79a3fe16c4b370f66553422f0665d30630def..1667de149ace0bdaaafcd36c43724422682df424 100644
--- a/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S
+++ b/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S
@@ -1 +1,2 @@
-%include "x86_64/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" }
+%def op_filled_new_array_range():
+%  op_filled_new_array(helper="MterpFilledNewArrayRange")
diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_double.S b/runtime/interpreter/mterp/x86_64/op_float_to_double.S
index 785520557503fdd89b7bdfc32cd776f00dbbafa1..a7cf8d3345e3a003abba3b7aefda664e67a37fdf 100644
--- a/runtime/interpreter/mterp/x86_64/op_float_to_double.S
+++ b/runtime/interpreter/mterp/x86_64/op_float_to_double.S
@@ -1 +1,2 @@
-%include "x86_64/fpcvt.S" {"source_suffix":"s","dest_suffix":"d","wide":"1"}
+%def op_float_to_double():
+%  fpcvt(source_suffix="s", dest_suffix="d", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_int.S b/runtime/interpreter/mterp/x86_64/op_float_to_int.S
index cb90555405c59354555deee41996573bbf738fa2..11955868a81fe82693e5add0394cdee18af9e59a 100644
--- a/runtime/interpreter/mterp/x86_64/op_float_to_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_float_to_int.S
@@ -1 +1,2 @@
-%include "x86_64/cvtfp_int.S" {"fp_suffix":"s","i_suffix":"l","max_const":"$0x7fffffff","result_reg":"%eax","wide":"0"}
+%def op_float_to_int():
+%  cvtfp_int(fp_suffix="s", i_suffix="l", max_const="$0x7fffffff", result_reg="%eax", wide="0")
diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_long.S b/runtime/interpreter/mterp/x86_64/op_float_to_long.S
index 96bb4eee6f55c257c707b39f75f165d11bb9c861..4548d6a47f26ffd93b5a907c29ea503a0aa938bf 100644
--- a/runtime/interpreter/mterp/x86_64/op_float_to_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_float_to_long.S
@@ -1 +1,2 @@
-%include "x86_64/cvtfp_int.S" {"fp_suffix":"s","i_suffix":"q","max_const":"$0x7fffffffffffffff","result_reg":"%rax","wide":"1"}
+%def op_float_to_long():
+%  cvtfp_int(fp_suffix="s", i_suffix="q", max_const="$0x7fffffffffffffff", result_reg="%rax", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_goto.S b/runtime/interpreter/mterp/x86_64/op_goto.S
index 9749901f5a7a46d889de27ec1d43c29b151d1378..0659bbc0e66d6d154389ef47574fe1b4f195fc28 100644
--- a/runtime/interpreter/mterp/x86_64/op_goto.S
+++ b/runtime/interpreter/mterp/x86_64/op_goto.S
@@ -1,3 +1,4 @@
+%def op_goto():
 /*
  * Unconditional branch, 8-bit offset.
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_goto_16.S b/runtime/interpreter/mterp/x86_64/op_goto_16.S
index 77688e05e4f66b76154400e870baed07e2d1ebd2..1193f70aecfbd079e34e1ad9824c33c3a10f5cfb 100644
--- a/runtime/interpreter/mterp/x86_64/op_goto_16.S
+++ b/runtime/interpreter/mterp/x86_64/op_goto_16.S
@@ -1,3 +1,4 @@
+%def op_goto_16():
 /*
  * Unconditional branch, 16-bit offset.
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_goto_32.S b/runtime/interpreter/mterp/x86_64/op_goto_32.S
index 29d777b5a61e46d6b771d3c0fd4d45f1647d02f9..cd0b5222746ffd77c0cc72b607c1a29406378c1e 100644
--- a/runtime/interpreter/mterp/x86_64/op_goto_32.S
+++ b/runtime/interpreter/mterp/x86_64/op_goto_32.S
@@ -1,3 +1,4 @@
+%def op_goto_32():
 /*
  * Unconditional branch, 32-bit offset.
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_if_eq.S b/runtime/interpreter/mterp/x86_64/op_if_eq.S
index d56ce72461c76894a9d8e9eba5f8c4f3015ae569..4d1f6a54d2f6f2701623f8f79e910da73b8c4bcd 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_eq.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_eq.S
@@ -1 +1,2 @@
-%include "x86_64/bincmp.S" { "revcmp":"ne" }
+%def op_if_eq():
+%  bincmp(revcmp="ne")
diff --git a/runtime/interpreter/mterp/x86_64/op_if_eqz.S b/runtime/interpreter/mterp/x86_64/op_if_eqz.S
index a0fc4448a3980ebf8497955ed9e7981f123ddebe..12de5585506ffd994b0e3bcf0eeaf3f49e88c000 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_eqz.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_eqz.S
@@ -1 +1,2 @@
-%include "x86_64/zcmp.S" { "revcmp":"ne" }
+%def op_if_eqz():
+%  zcmp(revcmp="ne")
diff --git a/runtime/interpreter/mterp/x86_64/op_if_ge.S b/runtime/interpreter/mterp/x86_64/op_if_ge.S
index a7832efb68368126366149d82f27fc769158bbf3..684902776f0c93ab9990f02a7fb3515228a968d3 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_ge.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_ge.S
@@ -1 +1,2 @@
-%include "x86_64/bincmp.S" { "revcmp":"l" }
+%def op_if_ge():
+%  bincmp(revcmp="l")
diff --git a/runtime/interpreter/mterp/x86_64/op_if_gez.S b/runtime/interpreter/mterp/x86_64/op_if_gez.S
index f9af5db933dbf65b4f6fc14971e09d080c6fcc19..87bdcbfa326470703ea928ff91bc6ac6b9d0e876 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_gez.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_gez.S
@@ -1 +1,2 @@
-%include "x86_64/zcmp.S" { "revcmp":"l" }
+%def op_if_gez():
+%  zcmp(revcmp="l")
diff --git a/runtime/interpreter/mterp/x86_64/op_if_gt.S b/runtime/interpreter/mterp/x86_64/op_if_gt.S
index 70f2b9e12f29ec8c64302ba5318da02333c66a90..4a521006b3a8028a624a2f7cf633da031cb313da 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_gt.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_gt.S
@@ -1 +1,2 @@
-%include "x86_64/bincmp.S" { "revcmp":"le" }
+%def op_if_gt():
+%  bincmp(revcmp="le")
diff --git a/runtime/interpreter/mterp/x86_64/op_if_gtz.S b/runtime/interpreter/mterp/x86_64/op_if_gtz.S
index 2fb0d509377a06d45d5b8a3522e98e073938de17..a0b2e3a35bf284dc0218e692b1669b14318c7c3a 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_gtz.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_gtz.S
@@ -1 +1,2 @@
-%include "x86_64/zcmp.S" { "revcmp":"le" }
+%def op_if_gtz():
+%  zcmp(revcmp="le")
diff --git a/runtime/interpreter/mterp/x86_64/op_if_le.S b/runtime/interpreter/mterp/x86_64/op_if_le.S
index 321962a040367738c278b2fbd6f0929b4feeaa67..69e94db79faa4ae1b4c62b9332fb7d20378e40d4 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_le.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_le.S
@@ -1 +1,2 @@
-%include "x86_64/bincmp.S" { "revcmp":"g" }
+%def op_if_le():
+%  bincmp(revcmp="g")
diff --git a/runtime/interpreter/mterp/x86_64/op_if_lez.S b/runtime/interpreter/mterp/x86_64/op_if_lez.S
index d3dc334f7bcad1be0a42b630f904dd0bed16b987..42e69d969ad81e1804ad2cb72bc16ef0e3b77542 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_lez.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_lez.S
@@ -1 +1,2 @@
-%include "x86_64/zcmp.S" { "revcmp":"g" }
+%def op_if_lez():
+%  zcmp(revcmp="g")
diff --git a/runtime/interpreter/mterp/x86_64/op_if_lt.S b/runtime/interpreter/mterp/x86_64/op_if_lt.S
index f028005844911e31c39d413a33736f17953f4895..052aabe1e74070c2eb42cdfe48c166fe27fde50d 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_lt.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_lt.S
@@ -1 +1,2 @@
-%include "x86_64/bincmp.S" { "revcmp":"ge" }
+%def op_if_lt():
+%  bincmp(revcmp="ge")
diff --git a/runtime/interpreter/mterp/x86_64/op_if_ltz.S b/runtime/interpreter/mterp/x86_64/op_if_ltz.S
index 383d73aa7a70ba35c9dac15644724fc3b92541a6..8e13e48c2a476d6bfa6f40821545bafc7cb95baf 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_ltz.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_ltz.S
@@ -1 +1,2 @@
-%include "x86_64/zcmp.S" { "revcmp":"ge" }
+%def op_if_ltz():
+%  zcmp(revcmp="ge")
diff --git a/runtime/interpreter/mterp/x86_64/op_if_ne.S b/runtime/interpreter/mterp/x86_64/op_if_ne.S
index ac6e063cd100a41f5cb834f1ecb98fa97cabe5c7..2cfd8a9a1e8e49ae10af479a9f54d77eb07626fe 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_ne.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_ne.S
@@ -1 +1,2 @@
-%include "x86_64/bincmp.S" { "revcmp":"e" }
+%def op_if_ne():
+%  bincmp(revcmp="e")
diff --git a/runtime/interpreter/mterp/x86_64/op_if_nez.S b/runtime/interpreter/mterp/x86_64/op_if_nez.S
index c96e4f3d16b878ffb472b750fc8a2032a31dae78..261a173a38b3816ab812c55e14fd02b0961e345f 100644
--- a/runtime/interpreter/mterp/x86_64/op_if_nez.S
+++ b/runtime/interpreter/mterp/x86_64/op_if_nez.S
@@ -1 +1,2 @@
-%include "x86_64/zcmp.S" { "revcmp":"e" }
+%def op_if_nez():
+%  zcmp(revcmp="e")
diff --git a/runtime/interpreter/mterp/x86_64/op_iget.S b/runtime/interpreter/mterp/x86_64/op_iget.S
index 4ab7c27c5116ad58e1408ed7c69a7e43b626a8cd..d09edc0a17c38245736a29f1cf55eb6f5272b87d 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIGetU32"}
-%include "x86_64/field.S" { }
+%def op_iget(is_object="0", helper="MterpIGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_boolean.S b/runtime/interpreter/mterp/x86_64/op_iget_boolean.S
index 18e926492623b596dedf9f6f388b2155001d5466..cb8edeec773fb6468b5c331b435e409da634f505 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_boolean.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_boolean.S
@@ -1 +1,2 @@
-%include "x86_64/op_iget.S" { "helper":"MterpIGetU8" }
+%def op_iget_boolean():
+%  op_iget(helper="MterpIGetU8")
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S
index 07139c75ee394338f4680c97860af46cb24af45c..4e1676844b0d67ac7212c0d5a14591549bc92535 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S
@@ -1 +1,2 @@
-%include "x86_64/op_iget_quick.S" { "load":"movsbl" }
+%def op_iget_boolean_quick():
+%  op_iget_quick(load="movsbl")
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_byte.S b/runtime/interpreter/mterp/x86_64/op_iget_byte.S
index bec0ad526c262d2984294ba15733599749e5623a..2b87fb16b560430baefa05d3f6e20195cb963d23 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_byte.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_byte.S
@@ -1 +1,2 @@
-%include "x86_64/op_iget.S" { "helper":"MterpIGetI8" }
+%def op_iget_byte():
+%  op_iget(helper="MterpIGetI8")
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S
index 07139c75ee394338f4680c97860af46cb24af45c..b92936c28dcff04ec8c75086cf3c2bdadffbba1c 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S
@@ -1 +1,2 @@
-%include "x86_64/op_iget_quick.S" { "load":"movsbl" }
+%def op_iget_byte_quick():
+%  op_iget_quick(load="movsbl")
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_char.S b/runtime/interpreter/mterp/x86_64/op_iget_char.S
index 5e22b88129b312c6d0b03a6640ba322a85533c51..001bd03e2b85edc215b29789ba4fc55044b4a230 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_char.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_char.S
@@ -1 +1,2 @@
-%include "x86_64/op_iget.S" { "helper":"MterpIGetU16" }
+%def op_iget_char():
+%  op_iget(helper="MterpIGetU16")
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S
index 8cb3be3b65288583d6b506c6a91c68bc94c4cbc7..d6f836b28e7c02f8a8265cc92e4c5205389b46ba 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S
@@ -1 +1,2 @@
-%include "x86_64/op_iget_quick.S" { "load":"movzwl" }
+%def op_iget_char_quick():
+%  op_iget_quick(load="movzwl")
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_object.S b/runtime/interpreter/mterp/x86_64/op_iget_object.S
index bcef1d2c25e94c259fb454cb736c86384425d808..4e5f769547b494ed962728edba2d102a106b332a 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_object.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_object.S
@@ -1 +1,2 @@
-%include "x86_64/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" }
+%def op_iget_object():
+%  op_iget(is_object="1", helper="MterpIGetObj")
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S
index 176c9544ef7a01f86e5657a69a0f13513125e3c6..1969a25a0ddb9aac096b7cbb2739417eab427b4f 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iget_object_quick():
     /* For: iget-object-quick */
     /* op vA, vB, offset@CCCC */
     .extern artIGetObjectFromMterp
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_quick.S
index bfb7530167678594cb2defbe551aa2d5cbf8a0d2..ba9e8e40e7fbf48ddf14aef1d1ad470fb87bc5ac 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_quick.S
@@ -1,4 +1,4 @@
-%default { "load":"movl", "wide":"0"}
+%def op_iget_quick(load="movl", wide="0"):
     /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */
     /* op vA, vB, offset@CCCC */
     movl    rINST, %ecx                     # rcx <- BA
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_short.S b/runtime/interpreter/mterp/x86_64/op_iget_short.S
index 14c49f77114c31664b1384b14675c6060f49bb04..a62c4d998f1d05ed2a3bb1c2f2bf2cca501dfdb8 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_short.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_short.S
@@ -1 +1,2 @@
-%include "x86_64/op_iget.S" { "helper":"MterpIGetI16" }
+%def op_iget_short():
+%  op_iget(helper="MterpIGetI16")
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S
index 56ca858e74db9c028e724047f83db8469dba57a9..f5e48d621a36ad2d2ac8f6e9bde807755dd7a955 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S
@@ -1 +1,2 @@
-%include "x86_64/op_iget_quick.S" { "load":"movswl" }
+%def op_iget_short_quick():
+%  op_iget_quick(load="movswl")
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_wide.S b/runtime/interpreter/mterp/x86_64/op_iget_wide.S
index a85a4748453d60faaa6860f02bf221f338fe3ab8..9643cc340313b657f2485df521ed0ee0cba25f7b 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_wide.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_wide.S
@@ -1 +1,2 @@
-%include "x86_64/op_iget.S" { "helper":"MterpIGetU64" }
+%def op_iget_wide():
+%  op_iget(helper="MterpIGetU64")
diff --git a/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S
index 169d625529c7437ea65ac3b927ce81b6c82949d5..263ea8cff86fa5c71bc0e446ce0be9e72a7385b0 100644
--- a/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S
@@ -1 +1,2 @@
-%include "x86_64/op_iget_quick.S" { "load":"movswl", "wide":"1" }
+%def op_iget_wide_quick():
+%  op_iget_quick(load="movswl", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_instance_of.S b/runtime/interpreter/mterp/x86_64/op_instance_of.S
index 4819833658906b8f06e4c9e71c78cf85633a40cd..237dd39868ad3fb258f10859ce3c622041760ca0 100644
--- a/runtime/interpreter/mterp/x86_64/op_instance_of.S
+++ b/runtime/interpreter/mterp/x86_64/op_instance_of.S
@@ -1,3 +1,4 @@
+%def op_instance_of():
 /*
  * Check to see if an object reference is an instance of a class.
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_byte.S b/runtime/interpreter/mterp/x86_64/op_int_to_byte.S
index f4e578f868e1046ce40121d461206958e849b3cf..80e4d5c3105a170b703ea8761b2873d81f03e5fd 100644
--- a/runtime/interpreter/mterp/x86_64/op_int_to_byte.S
+++ b/runtime/interpreter/mterp/x86_64/op_int_to_byte.S
@@ -1 +1,2 @@
-%include "x86_64/unop.S" {"instr":"movsbl  %al, %eax"}
+%def op_int_to_byte():
+%  unop(instr="movsbl  %al, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_char.S b/runtime/interpreter/mterp/x86_64/op_int_to_char.S
index c1bf17f271e4685b8075dbea04acc39fdba66770..83e9868ef31ad71e61832596a8f98d7eb53fd375 100644
--- a/runtime/interpreter/mterp/x86_64/op_int_to_char.S
+++ b/runtime/interpreter/mterp/x86_64/op_int_to_char.S
@@ -1 +1,2 @@
-%include "x86_64/unop.S" {"instr":"movzwl  %ax,%eax"}
+%def op_int_to_char():
+%  unop(instr="movzwl  %ax,%eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_double.S b/runtime/interpreter/mterp/x86_64/op_int_to_double.S
index 27ebf42dbb5920ae7f444f830967342aa546a495..74e91ecebfd1cccddb69cc1be3ac5ec9820b8997 100644
--- a/runtime/interpreter/mterp/x86_64/op_int_to_double.S
+++ b/runtime/interpreter/mterp/x86_64/op_int_to_double.S
@@ -1 +1,2 @@
-%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"dl","wide":"1"}
+%def op_int_to_double():
+%  fpcvt(source_suffix="i", dest_suffix="dl", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_float.S b/runtime/interpreter/mterp/x86_64/op_int_to_float.S
index 5a98d44337e9498e31b25f67b09ff1669b2b1c80..b57fc84d0d0f30e43386351a53cdc39f62332dc6 100644
--- a/runtime/interpreter/mterp/x86_64/op_int_to_float.S
+++ b/runtime/interpreter/mterp/x86_64/op_int_to_float.S
@@ -1 +1,2 @@
-%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"sl","wide":"0"}
+%def op_int_to_float():
+%  fpcvt(source_suffix="i", dest_suffix="sl", wide="0")
diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_long.S b/runtime/interpreter/mterp/x86_64/op_int_to_long.S
index 9281137a546acac0e62f57b0027b26e55c0d6ed7..473d6a2ab7ca16c91af4d5770ea51f7abc1c84cc 100644
--- a/runtime/interpreter/mterp/x86_64/op_int_to_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_int_to_long.S
@@ -1,3 +1,4 @@
+%def op_int_to_long():
     /* int to long vA, vB */
     movzbq  rINSTbl, %rax                   # rax <- +A
     sarl    $$4, %eax                       # eax <- B
diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_short.S b/runtime/interpreter/mterp/x86_64/op_int_to_short.S
index 6ae6b50f3460dbd7fc1f08d2325c1074686d4fd2..e4db90b8013cec280138cab7c055b4d2b80110f1 100644
--- a/runtime/interpreter/mterp/x86_64/op_int_to_short.S
+++ b/runtime/interpreter/mterp/x86_64/op_int_to_short.S
@@ -1 +1,2 @@
-%include "x86_64/unop.S" {"instr":"movswl %ax, %eax"}
+%def op_int_to_short():
+%  unop(instr="movswl %ax, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_custom.S b/runtime/interpreter/mterp/x86_64/op_invoke_custom.S
index f4011f6d86cdd78e2be64b0346da854da3b96bc2..4bba9ee5241061aa29e63ea32bb9d575e34286ea 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_custom.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_custom.S
@@ -1 +1,2 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeCustom" }
+%def op_invoke_custom():
+%  invoke(helper="MterpInvokeCustom")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S
index 94612c47d58d51773a154cb17db0a8de2b7b40b1..57e61af1fa860d814a9da1eaab56b25f199771aa 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S
@@ -1 +1,2 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeCustomRange" }
+%def op_invoke_custom_range():
+%  invoke(helper="MterpInvokeCustomRange")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_direct.S b/runtime/interpreter/mterp/x86_64/op_invoke_direct.S
index 9628589b03b777fb321be09e41ac22480ae88522..d3139cf39b42aca474e7d18dcf526e32e80ced85 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_direct.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_direct.S
@@ -1 +1,2 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeDirect" }
+%def op_invoke_direct():
+%  invoke(helper="MterpInvokeDirect")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S
index 09ac8812fcda8f13f3ea20c9e285f54760911418..b4a161f48bf8b90b0561e577cdf35f27feb71f23 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S
@@ -1 +1,2 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeDirectRange" }
+%def op_invoke_direct_range():
+%  invoke(helper="MterpInvokeDirectRange")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_interface.S b/runtime/interpreter/mterp/x86_64/op_invoke_interface.S
index 76d9cd426f617b84fd3262ea7bad5c5bf35e061b..559b9768d9c0c7c8d93c348115c83d1821e35ded 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_interface.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_interface.S
@@ -1,4 +1,5 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeInterface" }
+%def op_invoke_interface():
+%  invoke(helper="MterpInvokeInterface")
 /*
  * Handle an interface method call.
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S
index 785b43c1a881c21eb7af1b9b8e550339f0de5c77..298911537760c27944307413bb6bbc1a686768a5 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S
@@ -1 +1,2 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeInterfaceRange" }
+%def op_invoke_interface_range():
+%  invoke(helper="MterpInvokeInterfaceRange")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S
index 452944536d93fbca29b04de3ad0e674a7a733805..ce61f5aa0e6039481359af9e0d7de053a159fc79 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S
@@ -1 +1,2 @@
-%include "x86_64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" }
+%def op_invoke_polymorphic():
+%  invoke_polymorphic(helper="MterpInvokePolymorphic")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S
index 01981c1b49f84c88df4f8ea9955894ff45cfb835..16731bdb4040829bf0020b8524b4f70866b1f1e8 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S
@@ -1 +1,2 @@
-%include "x86_64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" }
+%def op_invoke_polymorphic_range():
+%  invoke_polymorphic(helper="MterpInvokePolymorphicRange")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_static.S b/runtime/interpreter/mterp/x86_64/op_invoke_static.S
index dd8027d58c5501a594a0c6f429660e0661717585..3e38d36a27a20c1d0f1481b80d6585a43343b6cb 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_static.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_static.S
@@ -1,2 +1,3 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeStatic" }
+%def op_invoke_static():
+%  invoke(helper="MterpInvokeStatic")
 
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S
index ee26074f921801d705d60b59c3519f5f7bb6e1cd..e0a546c92b4be72a4a5040d03e0018b1b248f536 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S
@@ -1 +1,2 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeStaticRange" }
+%def op_invoke_static_range():
+%  invoke(helper="MterpInvokeStaticRange")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_super.S b/runtime/interpreter/mterp/x86_64/op_invoke_super.S
index d07f8d555b0fbd34445a219036b60c573e473300..5b2055010efc04b9c5a25b98bfbbded2238ff615 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_super.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_super.S
@@ -1,4 +1,5 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeSuper" }
+%def op_invoke_super():
+%  invoke(helper="MterpInvokeSuper")
 /*
  * Handle a "super" method call.
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S
index 7245cfd405c833d74dfe71a3e4c4ac7fdbbcc861..caeafaa13c91fddf7dd3751252e4daf3045dcd2e 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S
@@ -1 +1,2 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeSuperRange" }
+%def op_invoke_super_range():
+%  invoke(helper="MterpInvokeSuperRange")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S
index 19c708bd2aa7f460c4f0ec9cafeff8f019bee36e..e27eeedacc335c0a428ee0155fbafe1e8fce37da 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S
@@ -1,4 +1,5 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtual" }
+%def op_invoke_virtual():
+%  invoke(helper="MterpInvokeVirtual")
 /*
  * Handle a virtual method call.
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S
index 313bd058b1ec69f8dfe818df786e83b105ad8e94..ea72c171ecfedd9ddb94bc2e2202e2c56ab11e53 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S
@@ -1 +1,2 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtualQuick" }
+%def op_invoke_virtual_quick():
+%  invoke(helper="MterpInvokeVirtualQuick")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S
index 424ad321a3524aaaf1259e6dddcad8f9600df8ce..baa077959359e0dcfbfd3b3cd9814c31b3f6d727 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S
@@ -1 +1,2 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtualRange" }
+%def op_invoke_virtual_range():
+%  invoke(helper="MterpInvokeVirtualRange")
diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S
index 556f718ffbf682b84aa379fb0fe5103268ef84d1..1d961a0781a94d0087847bce02fcae1f37a75f29 100644
--- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S
@@ -1 +1,2 @@
-%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" }
+%def op_invoke_virtual_range_quick():
+%  invoke(helper="MterpInvokeVirtualQuickRange")
diff --git a/runtime/interpreter/mterp/x86_64/op_iput.S b/runtime/interpreter/mterp/x86_64/op_iput.S
index dad5af664b371984b3793ed3712fb2e20e477e4c..e5351baf557fe295afb718387a6de58585ba5184 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpIPutU32" }
-%include "x86_64/field.S" { }
+%def op_iput(is_object="0", helper="MterpIPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_boolean.S b/runtime/interpreter/mterp/x86_64/op_iput_boolean.S
index 06bbd704d7725ce9b99136ae84036230454570a7..9eb849877b6207d46a36c083b47c83ebbd7e5d00 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_boolean.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_boolean.S
@@ -1 +1,2 @@
-%include "x86_64/op_iput.S" { "helper":"MterpIPutU8" }
+%def op_iput_boolean():
+%  op_iput(helper="MterpIPutU8")
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S
index 6bd060e4f3808dd94515fdf114a66dbfdf6f15ed..c304c76b519bf83014b21fb9219fbe07b7b81105 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S
@@ -1 +1,2 @@
-%include "x86_64/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" }
+%def op_iput_boolean_quick():
+%  op_iput_quick(reg="rINSTbl", store="movb")
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_byte.S b/runtime/interpreter/mterp/x86_64/op_iput_byte.S
index 53f9008eb55e62811bba0226f42d2ef491681988..4b74f9fb0e3c8bfe5566574fae72b21f71cd2067 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_byte.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_byte.S
@@ -1 +1,2 @@
-%include "x86_64/op_iput.S" { "helper":"MterpIPutI8" }
+%def op_iput_byte():
+%  op_iput(helper="MterpIPutI8")
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S
index 6bd060e4f3808dd94515fdf114a66dbfdf6f15ed..dac18e63ccd618dbc1c7adb955e1371bf33295c1 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S
@@ -1 +1,2 @@
-%include "x86_64/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" }
+%def op_iput_byte_quick():
+%  op_iput_quick(reg="rINSTbl", store="movb")
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_char.S b/runtime/interpreter/mterp/x86_64/op_iput_char.S
index 4736f5e9d44726921bffd488c227591063fb391f..64a249fc122e7eb749561fbc7ef7b3cc1be67382 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_char.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_char.S
@@ -1 +1,2 @@
-%include "x86_64/op_iput.S" { "helper":"MterpIPutU16" }
+%def op_iput_char():
+%  op_iput(helper="MterpIPutU16")
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S
index 3da96d53afcec7a3948365c9b016ee491912cff2..21a25812b15f735dac19e8cc35b6f04f2799e504 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S
@@ -1 +1,2 @@
-%include "x86_64/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" }
+%def op_iput_char_quick():
+%  op_iput_quick(reg="rINSTw", store="movw")
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_object.S b/runtime/interpreter/mterp/x86_64/op_iput_object.S
index 202e33fa7606ef2689ac55c50297dbfe6185c340..131edd5dbdae914ae95c3220d01788eba1a7ffb2 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_object.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_object.S
@@ -1 +1,2 @@
-%include "x86_64/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" }
+%def op_iput_object():
+%  op_iput(is_object="1", helper="MterpIPutObj")
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S
index b5b128ab7fdc83fee0df8ad34805dfeeee0ec1a1..e41540d5b78517f85a44215fc71c99617a79aa06 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_object_quick():
     EXPORT_PC
     leaq    OFF_FP_SHADOWFRAME(rFP), OUT_ARG0
     movq    rPC, OUT_ARG1
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_quick.S
index ecaf98e415c69d572b9275cea41a3583186b789f..3cbb7e99c33bc831c08ac84090b7579c84ff5c16 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_quick.S
@@ -1,4 +1,4 @@
-%default { "reg":"rINST", "store":"movl" }
+%def op_iput_quick(reg="rINST", store="movl"):
     /* For: iput-quick, iput-object-quick */
     /* op vA, vB, offset@CCCC */
     movzbq  rINSTbl, %rcx                   # rcx <- BA
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_short.S b/runtime/interpreter/mterp/x86_64/op_iput_short.S
index dca5735963694550f7f33b788c112457b0b87656..e631a3b259e969ae8ae1222244d299fd0e4da3d7 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_short.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_short.S
@@ -1 +1,2 @@
-%include "x86_64/op_iput.S" { "helper":"MterpIPutI16" }
+%def op_iput_short():
+%  op_iput(helper="MterpIPutI16")
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S
index 3da96d53afcec7a3948365c9b016ee491912cff2..5eb28d6922d19c63770208f6e61321153fea6a08 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S
@@ -1 +1,2 @@
-%include "x86_64/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" }
+%def op_iput_short_quick():
+%  op_iput_quick(reg="rINSTw", store="movw")
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_wide.S b/runtime/interpreter/mterp/x86_64/op_iput_wide.S
index db520167d2844e48c4a56569ceda8d9d7c207fcc..2f34fd39f9ed2ca1104582178602a4dac83ee761 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_wide.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_wide.S
@@ -1 +1,2 @@
-%include "x86_64/op_iput.S" { "helper":"MterpIPutU64" }
+%def op_iput_wide():
+%  op_iput(helper="MterpIPutU64")
diff --git a/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S
index 473189d007122db21736588cc45c1f0d16e05ac1..a13a6340efcffa0be5575932aabe918a1205265c 100644
--- a/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S
+++ b/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S
@@ -1,3 +1,4 @@
+%def op_iput_wide_quick():
     /* iput-wide-quick vA, vB, offset@CCCC */
     movzbq    rINSTbl, %rcx                 # rcx<- BA
     sarl      $$4, %ecx                     # ecx<- B
diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_double.S b/runtime/interpreter/mterp/x86_64/op_long_to_double.S
index 7cdae32373109d76c50933ecfdbe44c3f215cfb6..6b2d7bf5746effb702c15015ee24eb356ee3a152 100644
--- a/runtime/interpreter/mterp/x86_64/op_long_to_double.S
+++ b/runtime/interpreter/mterp/x86_64/op_long_to_double.S
@@ -1 +1,2 @@
-%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"dq","wide":"1"}
+%def op_long_to_double():
+%  fpcvt(source_suffix="i", dest_suffix="dq", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_float.S b/runtime/interpreter/mterp/x86_64/op_long_to_float.S
index 7553348633db34683e0d4d418155d69c44cd98e4..7c2edfd613e261ce4c26a45df1ee4960a97c5250 100644
--- a/runtime/interpreter/mterp/x86_64/op_long_to_float.S
+++ b/runtime/interpreter/mterp/x86_64/op_long_to_float.S
@@ -1 +1,2 @@
-%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"sq","wide":"0"}
+%def op_long_to_float():
+%  fpcvt(source_suffix="i", dest_suffix="sq", wide="0")
diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_int.S b/runtime/interpreter/mterp/x86_64/op_long_to_int.S
index 7b50c8e0b357dafee5aab52f1c13a1c8255fb7e9..eacb8f59ec402cbb87d740022854981c341e9a09 100644
--- a/runtime/interpreter/mterp/x86_64/op_long_to_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_long_to_int.S
@@ -1,2 +1,3 @@
+%def op_long_to_int():
 /* we ignore the high word, making this equivalent to a 32-bit reg move */
-%include "x86_64/op_move.S"
+%  op_move()
diff --git a/runtime/interpreter/mterp/x86_64/op_monitor_enter.S b/runtime/interpreter/mterp/x86_64/op_monitor_enter.S
index 411091f23e044e12c98bd4ed01a312abed95f40e..7865156c25740c1e74086a85f2c6f708f53f1c0a 100644
--- a/runtime/interpreter/mterp/x86_64/op_monitor_enter.S
+++ b/runtime/interpreter/mterp/x86_64/op_monitor_enter.S
@@ -1,3 +1,4 @@
+%def op_monitor_enter():
 /*
  * Synchronize on an object.
  */
diff --git a/runtime/interpreter/mterp/x86_64/op_monitor_exit.S b/runtime/interpreter/mterp/x86_64/op_monitor_exit.S
index 72d9a23a87978fd18153f6420718cdf7a591c4a5..6422bc8759d2d28538e06a646341e87e03722a84 100644
--- a/runtime/interpreter/mterp/x86_64/op_monitor_exit.S
+++ b/runtime/interpreter/mterp/x86_64/op_monitor_exit.S
@@ -1,3 +1,4 @@
+%def op_monitor_exit():
 /*
  * Unlock an object.
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_move.S b/runtime/interpreter/mterp/x86_64/op_move.S
index ccaac2caa89db061daf6a30272c393745e0da058..0ccf228ee8583fc45b8a6f07c59ac21eed4b26f9 100644
--- a/runtime/interpreter/mterp/x86_64/op_move.S
+++ b/runtime/interpreter/mterp/x86_64/op_move.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move(is_object="0"):
     /* for move, move-object, long-to-int */
     /* op vA, vB */
     movl    rINST, %eax                     # eax <- BA
diff --git a/runtime/interpreter/mterp/x86_64/op_move_16.S b/runtime/interpreter/mterp/x86_64/op_move_16.S
index 6a813eb5ce2d8592b7283785537aaa5d365adbfb..238f089beffd84ede8a8f9edf8f019cfb04fd3b7 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_16.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_16(is_object="0"):
     /* for: move/16, move-object/16 */
     /* op vAAAA, vBBBB */
     movzwq  4(rPC), %rcx                    # ecx <- BBBB
diff --git a/runtime/interpreter/mterp/x86_64/op_move_exception.S b/runtime/interpreter/mterp/x86_64/op_move_exception.S
index 33db8782362717e9543c66c1b161f2705aba3db2..9d87f7c8f7eb350e3591d9d13bbaae9d532edea0 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_exception.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_exception.S
@@ -1,3 +1,4 @@
+%def op_move_exception():
     /* move-exception vAA */
     movq    rSELF, %rcx
     movl    THREAD_EXCEPTION_OFFSET(%rcx), %eax
diff --git a/runtime/interpreter/mterp/x86_64/op_move_from16.S b/runtime/interpreter/mterp/x86_64/op_move_from16.S
index 150e9c2f2c8ef0218f2aaab67ce2249eac9bc9a8..6163e6d37dd6da51e61a62f2bcdc1002ec052bef 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_from16.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_from16.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_from16(is_object="0"):
     /* for: move/from16, move-object/from16 */
     /* op vAA, vBBBB */
     movzwq  2(rPC), %rax                    # eax <- BBBB
diff --git a/runtime/interpreter/mterp/x86_64/op_move_object.S b/runtime/interpreter/mterp/x86_64/op_move_object.S
index 0d866496e8a17f20927019de15a9c2340368ecf8..dbb4d5971027d54f58728020aadfa71973fb509a 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_object.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_object.S
@@ -1 +1,2 @@
-%include "x86_64/op_move.S" {"is_object":"1"}
+%def op_move_object():
+%  op_move(is_object="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_move_object_16.S b/runtime/interpreter/mterp/x86_64/op_move_object_16.S
index 32541ff2bfdfee06ddee388d13bdea5f5a86bbcb..40120379d51d6027f960ef7742f12d8d16773855 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_object_16.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_object_16.S
@@ -1 +1,2 @@
-%include "x86_64/op_move_16.S" {"is_object":"1"}
+%def op_move_object_16():
+%  op_move_16(is_object="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_move_object_from16.S b/runtime/interpreter/mterp/x86_64/op_move_object_from16.S
index 983e4abae5174c2794e494360a983ed27547f928..c82698e81e6805ad74ebe1f6c8c36e3ff3a1bd4b 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_object_from16.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_object_from16.S
@@ -1 +1,2 @@
-%include "x86_64/op_move_from16.S" {"is_object":"1"}
+%def op_move_object_from16():
+%  op_move_from16(is_object="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_move_result.S b/runtime/interpreter/mterp/x86_64/op_move_result.S
index 8268344bcedc0ae4996282c86eabc9550f9e6434..a089623bca4d9b25e4e038ed7da045a50de61ca4 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_result.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_result.S
@@ -1,4 +1,4 @@
-%default { "is_object":"0" }
+%def op_move_result(is_object="0"):
     /* for: move-result, move-result-object */
     /* op vAA */
     movq    OFF_FP_RESULT_REGISTER(rFP), %rax    # get pointer to result JType.
diff --git a/runtime/interpreter/mterp/x86_64/op_move_result_object.S b/runtime/interpreter/mterp/x86_64/op_move_result_object.S
index c5aac17f41594016ab9651d035f1527752319770..87aea2646a6b25bae7ee8970a973915a76557939 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_result_object.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_result_object.S
@@ -1 +1,2 @@
-%include "x86_64/op_move_result.S" {"is_object":"1"}
+%def op_move_result_object():
+%  op_move_result(is_object="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_move_result_wide.S b/runtime/interpreter/mterp/x86_64/op_move_result_wide.S
index 03de7836273ef9726837e198647a68300cd19ab8..80f49aaa159448d0d2a9b2a4f172211398dfe5d8 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_result_wide.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_result_wide.S
@@ -1,3 +1,4 @@
+%def op_move_result_wide():
     /* move-result-wide vAA */
     movq    OFF_FP_RESULT_REGISTER(rFP), %rax    # get pointer to result JType.
     movq    (%rax), %rdx                         # Get wide
diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide.S b/runtime/interpreter/mterp/x86_64/op_move_wide.S
index 508f8cc1521fcbf2cbd741d3251fa19630f84b86..afb67efd1078b2b55cc4c94c11f726530ce3d587 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_wide.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_wide.S
@@ -1,3 +1,4 @@
+%def op_move_wide():
     /* move-wide vA, vB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movl    rINST, %ecx                     # ecx <- BA
diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide_16.S b/runtime/interpreter/mterp/x86_64/op_move_wide_16.S
index ce371a920eccb60fc402492389628f04292f4007..b4de5206fdc141fac34c8a986704da944b0eb8a7 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_wide_16.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_wide_16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_16():
     /* move-wide/16 vAAAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movzwq  4(rPC), %rcx                    # ecx<- BBBB
diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S b/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S
index 0d6971a674da52e598ec1d507c5cb2b16777fa6c..c4389a4873af7225bd51fbcb8b9c63eb82f00141 100644
--- a/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S
+++ b/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S
@@ -1,3 +1,4 @@
+%def op_move_wide_from16():
     /* move-wide/from16 vAA, vBBBB */
     /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
     movzwl  2(rPC), %ecx                    # ecx <- BBBB
diff --git a/runtime/interpreter/mterp/x86_64/op_mul_double.S b/runtime/interpreter/mterp/x86_64/op_mul_double.S
index 1f4bcb3d00b49c217baff3bc1cf099676a930f19..53530287982830edc82175937b29fdbf60992c82 100644
--- a/runtime/interpreter/mterp/x86_64/op_mul_double.S
+++ b/runtime/interpreter/mterp/x86_64/op_mul_double.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop.S" {"instr":"muls","suff":"d"}
+%def op_mul_double():
+%  sseBinop(instr="muls", suff="d")
diff --git a/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S
index 9850a28995cdbc543e0adac9e418ac61f0be150d..7a6dcd0cb85e6309f990772de0532483cf5f2565 100644
--- a/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop2Addr.S" {"instr":"muls","suff":"d"}
+%def op_mul_double_2addr():
+%  sseBinop2Addr(instr="muls", suff="d")
diff --git a/runtime/interpreter/mterp/x86_64/op_mul_float.S b/runtime/interpreter/mterp/x86_64/op_mul_float.S
index 85960e9decbf6a35aeaf0e701447912bc071d455..b9eeeeeb69c7dfc401e59b28b0550e379e521648 100644
--- a/runtime/interpreter/mterp/x86_64/op_mul_float.S
+++ b/runtime/interpreter/mterp/x86_64/op_mul_float.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop.S" {"instr":"muls","suff":"s"}
+%def op_mul_float():
+%  sseBinop(instr="muls", suff="s")
diff --git a/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S
index 6d36b6a178554028806dec63876541e5b57dd655..949af7b25409313b3f4eb36547b6c27a212a1056 100644
--- a/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop2Addr.S" {"instr":"muls","suff":"s"}
+%def op_mul_float_2addr():
+%  sseBinop2Addr(instr="muls", suff="s")
diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int.S b/runtime/interpreter/mterp/x86_64/op_mul_int.S
index 5f3923a20e7d446322f814a82bfe815823e1fc2f..51abae6294e5b0f9672afc8187e69b3e4120c55a 100644
--- a/runtime/interpreter/mterp/x86_64/op_mul_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_mul_int.S
@@ -1 +1,2 @@
-%include "x86_64/binop.S" {"instr":"imull   (rFP,%rcx,4), %eax"}
+%def op_mul_int():
+%  binop(instr="imull   (rFP,%rcx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S
index 0b5af8a927fd83417ea0e43ae8db6bde28edf80d..fb2ec8924551bafb689b301d3162fbb9ad097f9f 100644
--- a/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S
@@ -1,3 +1,4 @@
+%def op_mul_int_2addr():
     /* mul vA, vB */
     movl    rINST, %ecx                     # rcx <- A+
     sarl    $$4, rINST                      # rINST <- B
diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S
index a4cfdbce3eac0bd6f07f5b12c0893b883cc27f1e..a0b1e714c685cec86f85465df07b38118c4b9eab 100644
--- a/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S
+++ b/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit16.S" {"instr":"imull   %ecx, %eax"}
+%def op_mul_int_lit16():
+%  binopLit16(instr="imull   %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S
index 89e9acb77df807c8f15443d61f1fac4cf34f27ab..e68e7f7e2ff7c1554a8cfc79c215bf8cc91b2d09 100644
--- a/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S
+++ b/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit8.S" {"instr":"imull   %ecx, %eax"}
+%def op_mul_int_lit8():
+%  binopLit8(instr="imull   %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_mul_long.S b/runtime/interpreter/mterp/x86_64/op_mul_long.S
index 2b853705cf42bab73a42c6f4731f9084e399a891..e5bffa4035b266773a0e3f4dc2c3afbd8afa0634 100644
--- a/runtime/interpreter/mterp/x86_64/op_mul_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_mul_long.S
@@ -1 +1,2 @@
-%include "x86_64/binopWide.S" {"instr":"imulq   (rFP,%rcx,4), %rax"}
+%def op_mul_long():
+%  binopWide(instr="imulq   (rFP,%rcx,4), %rax")
diff --git a/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S
index 167128b4d180887d6ca457c3063d8ecf592ae5ce..25ffc148a53e4b8d5f7fdca76cf0727fa785fca9 100644
--- a/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S
@@ -1,3 +1,4 @@
+%def op_mul_long_2addr():
     /* mul vA, vB */
     movl    rINST, %ecx                     # rcx <- A+
     sarl    $$4, rINST                      # rINST <- B
diff --git a/runtime/interpreter/mterp/x86_64/op_neg_double.S b/runtime/interpreter/mterp/x86_64/op_neg_double.S
index 2c14b091cb38e148fac4431638fc4ea6a6af2627..56e38041b163bd758dcb64b9afb8f9f486d12314 100644
--- a/runtime/interpreter/mterp/x86_64/op_neg_double.S
+++ b/runtime/interpreter/mterp/x86_64/op_neg_double.S
@@ -1 +1,2 @@
-%include "x86_64/unop.S" {"preinstr":"    movq    $0x8000000000000000, %rsi", "instr":"    xorq    %rsi, %rax", "wide":"1"}
+%def op_neg_double():
+%  unop(preinstr="    movq    $0x8000000000000000, %rsi", instr="    xorq    %rsi, %rax", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_neg_float.S b/runtime/interpreter/mterp/x86_64/op_neg_float.S
index 148b21ec9a325a63bf79f8be590ac58fd5c2f9cf..6a394449633c4b9125904a1a019b0b1c4f316e3f 100644
--- a/runtime/interpreter/mterp/x86_64/op_neg_float.S
+++ b/runtime/interpreter/mterp/x86_64/op_neg_float.S
@@ -1 +1,2 @@
-%include "x86_64/unop.S" {"instr":"    xorl    $0x80000000, %eax"}
+%def op_neg_float():
+%  unop(instr="    xorl    $0x80000000, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_neg_int.S b/runtime/interpreter/mterp/x86_64/op_neg_int.S
index f90a937a8b7d784777fcbd859fca4a6514288739..44790edd510982b8afb43004ea60ae3bb142f027 100644
--- a/runtime/interpreter/mterp/x86_64/op_neg_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_neg_int.S
@@ -1 +1,2 @@
-%include "x86_64/unop.S" {"instr":"    negl    %eax"}
+%def op_neg_int():
+%  unop(instr="    negl    %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_neg_long.S b/runtime/interpreter/mterp/x86_64/op_neg_long.S
index 18fc3ccecef02c6895ddfd81467818dd997f81b2..2d296ee19d91ea77a3f8d2941dc9af8369ed6691 100644
--- a/runtime/interpreter/mterp/x86_64/op_neg_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_neg_long.S
@@ -1 +1,2 @@
-%include "x86_64/unop.S" {"instr":"    negq    %rax", "wide":"1"}
+%def op_neg_long():
+%  unop(instr="    negq    %rax", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_new_array.S b/runtime/interpreter/mterp/x86_64/op_new_array.S
index 9831a0b8884c87205f2aa341e70b1bb6b5197eae..de1b0016d2061157082cd0d40e3ebbe1541a7656 100644
--- a/runtime/interpreter/mterp/x86_64/op_new_array.S
+++ b/runtime/interpreter/mterp/x86_64/op_new_array.S
@@ -1,3 +1,4 @@
+%def op_new_array():
 /*
  * Allocate an array of objects, specified with the array class
  * and a count.
diff --git a/runtime/interpreter/mterp/x86_64/op_new_instance.S b/runtime/interpreter/mterp/x86_64/op_new_instance.S
index fc8c8cd98c4cd5c17731f333f00ff1fe71ccb225..cc3f31cb5ee6baadeb0f691c4f9f50de3489d580 100644
--- a/runtime/interpreter/mterp/x86_64/op_new_instance.S
+++ b/runtime/interpreter/mterp/x86_64/op_new_instance.S
@@ -1,3 +1,4 @@
+%def op_new_instance():
 /*
  * Create a new instance of a class.
  */
diff --git a/runtime/interpreter/mterp/x86_64/op_nop.S b/runtime/interpreter/mterp/x86_64/op_nop.S
index 4cb68e392e719513e5e85a72fa4aeb942105536b..aa4a843ab509709b7c4b9a9ec2b852829d9b1bdd 100644
--- a/runtime/interpreter/mterp/x86_64/op_nop.S
+++ b/runtime/interpreter/mterp/x86_64/op_nop.S
@@ -1 +1,2 @@
+%def op_nop():
     ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
diff --git a/runtime/interpreter/mterp/x86_64/op_not_int.S b/runtime/interpreter/mterp/x86_64/op_not_int.S
index 463d080de96da8e08188110e5b1e1fac4fa3a453..55ac8a7ff3d542f1d39bfc3e8052563db909eced 100644
--- a/runtime/interpreter/mterp/x86_64/op_not_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_not_int.S
@@ -1 +1,2 @@
-%include "x86_64/unop.S" {"instr":"    notl    %eax"}
+%def op_not_int():
+%  unop(instr="    notl    %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_not_long.S b/runtime/interpreter/mterp/x86_64/op_not_long.S
index c97bb9ea1aebab74f3c33ef176818919b77f5c04..c6c0f859c3fcc9cede081b642d19111a22c13eb7 100644
--- a/runtime/interpreter/mterp/x86_64/op_not_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_not_long.S
@@ -1 +1,2 @@
-%include "x86_64/unop.S" {"instr":"    notq    %rax", "wide":"1"}
+%def op_not_long():
+%  unop(instr="    notq    %rax", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_or_int.S b/runtime/interpreter/mterp/x86_64/op_or_int.S
index 730310f6afa7e0f6074db8648170aafd09b628f6..0e6dd67c2733fa441b23df4f809b708c44d7047d 100644
--- a/runtime/interpreter/mterp/x86_64/op_or_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_or_int.S
@@ -1 +1,2 @@
-%include "x86_64/binop.S" {"instr":"orl     (rFP,%rcx,4), %eax"}
+%def op_or_int():
+%  binop(instr="orl     (rFP,%rcx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S
index f722e4dd9c6b095ba2e3d422404e67d25c904df0..c722938c820dcedfe51411862447f93f972c2e59 100644
--- a/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/binop2addr.S" {"instr":"orl     %eax, (rFP,%rcx,4)"}
+%def op_or_int_2addr():
+%  binop2addr(instr="orl     %eax, (rFP,%rcx,4)")
diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S
index fee86c7c62d5810c22a60545765e9603c7188c98..ba9b6bff185786a11678ff7eeb4ece59b2bb728c 100644
--- a/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S
+++ b/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit16.S" {"instr":"orl     %ecx, %eax"}
+%def op_or_int_lit16():
+%  binopLit16(instr="orl     %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S
index 81104c7e56a65eedc8668c38c9682b0c575fc3bf..758109bc0531e079ab152f0eb0f5a774dc7590aa 100644
--- a/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S
+++ b/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit8.S" {"instr":"orl     %ecx, %eax"}
+%def op_or_int_lit8():
+%  binopLit8(instr="orl     %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_or_long.S b/runtime/interpreter/mterp/x86_64/op_or_long.S
index 6c70a2001ee10dd6f2e4ac4fa57f30a9fed0e3b2..b9c9321b2e6a140df9e2093f4ef82107b3f79d55 100644
--- a/runtime/interpreter/mterp/x86_64/op_or_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_or_long.S
@@ -1 +1,2 @@
-%include "x86_64/binopWide.S" {"instr":"orq     (rFP,%rcx,4), %rax"}
+%def op_or_long():
+%  binopWide(instr="orq     (rFP,%rcx,4), %rax")
diff --git a/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S
index 546da1de2d02b5b8a99f3059e6323bc029df52f0..616288e315aa559a01d582bbb4de842a43dd6d9f 100644
--- a/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/binopWide2addr.S" {"instr":"orq     %rax, (rFP,%rcx,4)"}
+%def op_or_long_2addr():
+%  binopWide2addr(instr="orq     %rax, (rFP,%rcx,4)")
diff --git a/runtime/interpreter/mterp/x86_64/op_packed_switch.S b/runtime/interpreter/mterp/x86_64/op_packed_switch.S
index 148552f77eb661da25e977a55e88522d25176635..8b2b18b8cd50c40c34ef291683e5e03dc81ab454 100644
--- a/runtime/interpreter/mterp/x86_64/op_packed_switch.S
+++ b/runtime/interpreter/mterp/x86_64/op_packed_switch.S
@@ -1,4 +1,4 @@
-%default { "func":"MterpDoPackedSwitch" }
+%def op_packed_switch(func="MterpDoPackedSwitch"):
 /*
  * Handle a packed-switch or sparse-switch instruction.  In both cases
  * we decode it and hand it off to a helper function.
diff --git a/runtime/interpreter/mterp/x86_64/op_rem_double.S b/runtime/interpreter/mterp/x86_64/op_rem_double.S
index 00aed787cb33d9ea21e9c5536a9860b4ec9a547c..9b1c0b4bdc4dc9cdccaca04bf69d701c08cb3d98 100644
--- a/runtime/interpreter/mterp/x86_64/op_rem_double.S
+++ b/runtime/interpreter/mterp/x86_64/op_rem_double.S
@@ -1,3 +1,4 @@
+%def op_rem_double():
     /* rem_double vAA, vBB, vCC */
     movzbq  3(rPC), %rcx                    # ecx <- BB
     movzbq  2(rPC), %rax                    # eax <- CC
diff --git a/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S
index 9768266e211c6b6546dcb0f633c2dd7fe4b134e0..0600e90dfb95a7e317616d342406b25ddea93892 100644
--- a/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S
@@ -1,3 +1,4 @@
+%def op_rem_double_2addr():
     /* rem_double/2addr vA, vB */
     movzbq  rINSTbl, %rcx                   # ecx <- A+
     sarl    $$4, rINST                      # rINST <- B
diff --git a/runtime/interpreter/mterp/x86_64/op_rem_float.S b/runtime/interpreter/mterp/x86_64/op_rem_float.S
index 5af28accec3261409af74d1affe2fc398953a7c1..28c1328e7c5f08b88032dcd4e80d3dbcaffe3148 100644
--- a/runtime/interpreter/mterp/x86_64/op_rem_float.S
+++ b/runtime/interpreter/mterp/x86_64/op_rem_float.S
@@ -1,3 +1,4 @@
+%def op_rem_float():
     /* rem_float vAA, vBB, vCC */
     movzbq  3(rPC), %rcx                    # ecx <- BB
     movzbq  2(rPC), %rax                    # eax <- CC
diff --git a/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S
index e9282a8de95d9d587fa2777dbaae1460a23630d4..8cfdca080a3e981ee85876c6a0f73f97b33d9b76 100644
--- a/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S
@@ -1,3 +1,4 @@
+%def op_rem_float_2addr():
     /* rem_float/2addr vA, vB */
     movzbq  rINSTbl, %rcx                   # ecx <- A+
     sarl    $$4, rINST                      # rINST <- B
diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int.S b/runtime/interpreter/mterp/x86_64/op_rem_int.S
index fd77d7cdfe229554c1ea9b10758363ca27283b78..1530f5f94468d285eb36663efe5e76ed8cdf93cc 100644
--- a/runtime/interpreter/mterp/x86_64/op_rem_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_rem_int.S
@@ -1 +1,2 @@
-%include "x86_64/bindiv.S" {"result":"%edx","second":"%ecx","wide":"0","suffix":"l","rem":"1"}
+%def op_rem_int():
+%  bindiv(result="%edx", second="%ecx", wide="0", suffix="l", rem="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S
index 25ffbf713bdd750367a95832d5a145f004c66d05..742213a468efb7cbd48bb11773a3c7289f3a1183 100644
--- a/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/bindiv2addr.S" {"result":"%edx","second":"%ecx","wide":"0","suffix":"l","rem":"1"}
+%def op_rem_int_2addr():
+%  bindiv2addr(result="%edx", second="%ecx", wide="0", suffix="l", rem="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S
index 21cc37087d64e7cb91b3213351edf36d80719f12..eaa44a4608eeca66a7ab48f899de163e99a6e5d7 100644
--- a/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S
+++ b/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S
@@ -1 +1,2 @@
-%include "x86_64/bindivLit16.S" {"result":"%edx","rem":"1"}
+%def op_rem_int_lit16():
+%  bindivLit16(result="%edx", rem="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S
index 2eb0150f63091614c9b386bea2bd241026bfb13b..3fef144d1f315ab7d9b6420a3eba055e39eaf199 100644
--- a/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S
+++ b/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S
@@ -1 +1,2 @@
-%include "x86_64/bindivLit8.S" {"result":"%edx","rem":"1"}
+%def op_rem_int_lit8():
+%  bindivLit8(result="%edx", rem="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_rem_long.S b/runtime/interpreter/mterp/x86_64/op_rem_long.S
index efa721520dd415a14cc89f0ddc867db18aae4716..60bfd3d9df8fa61d476bceba60a5999cbf7cb6c1 100644
--- a/runtime/interpreter/mterp/x86_64/op_rem_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_rem_long.S
@@ -1 +1,2 @@
-%include "x86_64/bindiv.S" {"result":"%rdx","second":"%rcx","wide":"1","suffix":"q","ext":"cqo","rem":"1"}
+%def op_rem_long():
+%  bindiv(result="%rdx", second="%rcx", wide="1", suffix="q", ext="cqo", rem="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S
index ce0dd86539c98efdf07c06d569172c59371833a6..fc5a2d0cb90c5cf30c1d094449813d13833ca231 100644
--- a/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/bindiv2addr.S" {"result":"%rdx","second":"%rcx","wide":"1","suffix":"q","rem":"1","ext":"cqo"}
+%def op_rem_long_2addr():
+%  bindiv2addr(result="%rdx", second="%rcx", wide="1", suffix="q", rem="1", ext="cqo")
diff --git a/runtime/interpreter/mterp/x86_64/op_return.S b/runtime/interpreter/mterp/x86_64/op_return.S
index 8cb6cbaee1e6aea53f04335f99c9510372431818..b838f18b7c452243265567688c0e73ec0ee736a7 100644
--- a/runtime/interpreter/mterp/x86_64/op_return.S
+++ b/runtime/interpreter/mterp/x86_64/op_return.S
@@ -1,3 +1,4 @@
+%def op_return():
 /*
  * Return a 32-bit value.
  *
diff --git a/runtime/interpreter/mterp/x86_64/op_return_object.S b/runtime/interpreter/mterp/x86_64/op_return_object.S
index 1ae69a501c4e6db5621262f68d690bba0379882b..2eeec0b94824884ff1b3c0aeccbfa0948268f9ab 100644
--- a/runtime/interpreter/mterp/x86_64/op_return_object.S
+++ b/runtime/interpreter/mterp/x86_64/op_return_object.S
@@ -1 +1,2 @@
-%include "x86_64/op_return.S"
+%def op_return_object():
+%  op_return()
diff --git a/runtime/interpreter/mterp/x86_64/op_return_void.S b/runtime/interpreter/mterp/x86_64/op_return_void.S
index ba68e7e444a7dacde768db846b21c6f3fc3ae834..301dc9282245ee1259b29e3212e7a20498dc5b82 100644
--- a/runtime/interpreter/mterp/x86_64/op_return_void.S
+++ b/runtime/interpreter/mterp/x86_64/op_return_void.S
@@ -1,3 +1,4 @@
+%def op_return_void():
     .extern MterpThreadFenceForConstructor
     call    SYMBOL(MterpThreadFenceForConstructor)
     movq    rSELF, OUT_ARG0
diff --git a/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S
index 6799da1dbd3701c6ca4fc740332ea8fc253fa693..cec739c38181168d325a02d9b3cb867e328af5e6 100644
--- a/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S
+++ b/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S
@@ -1,3 +1,4 @@
+%def op_return_void_no_barrier():
     movq    rSELF, OUT_ARG0
     testl   $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0)
     jz      1f
diff --git a/runtime/interpreter/mterp/x86_64/op_return_wide.S b/runtime/interpreter/mterp/x86_64/op_return_wide.S
index d6d6d1bf5e835e5496cc863f206b5af3c2785e90..90e0a42d62d5c609ec2cc2d4191f3ea2bb627b8f 100644
--- a/runtime/interpreter/mterp/x86_64/op_return_wide.S
+++ b/runtime/interpreter/mterp/x86_64/op_return_wide.S
@@ -1,3 +1,4 @@
+%def op_return_wide():
 /*
  * Return a 64-bit value.
  */
diff --git a/runtime/interpreter/mterp/x86_64/op_rsub_int.S b/runtime/interpreter/mterp/x86_64/op_rsub_int.S
index 2dd20026df95c6c4486b610495fea0f146365625..05ba130f2f80670a6830956b50d72a6ea68cda16 100644
--- a/runtime/interpreter/mterp/x86_64/op_rsub_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_rsub_int.S
@@ -1,2 +1,3 @@
+%def op_rsub_int():
 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
-%include "x86_64/binopLit16.S" {"instr":"subl    %eax, %ecx","result":"%ecx"}
+%  binopLit16(instr="subl    %eax, %ecx", result="%ecx")
diff --git a/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S
index 64d0d8a704fedd32bd4ce99bb9c2589d01fed04d..d0230476d700ef0b90027789faecff8e508711f5 100644
--- a/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S
+++ b/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit8.S" {"instr":"subl    %eax, %ecx" , "result":"%ecx"}
+%def op_rsub_int_lit8():
+%  binopLit8(instr="subl    %eax, %ecx", result="%ecx")
diff --git a/runtime/interpreter/mterp/x86_64/op_sget.S b/runtime/interpreter/mterp/x86_64/op_sget.S
index 21e8e64b8bfa514aef7cb19bcfbc24504b64296b..8a6a66ab6032f5a140fcaa4cb0f85af9cb84bd7a 100644
--- a/runtime/interpreter/mterp/x86_64/op_sget.S
+++ b/runtime/interpreter/mterp/x86_64/op_sget.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSGetU32" }
-%include "x86_64/field.S" { }
+%def op_sget(is_object="0", helper="MterpSGetU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/x86_64/op_sget_boolean.S b/runtime/interpreter/mterp/x86_64/op_sget_boolean.S
index e5a4e41995cab58bfcd2c154f3c37160cebda6ea..d9c12c9b280100ec8c517e2c264d9c99022bb429 100644
--- a/runtime/interpreter/mterp/x86_64/op_sget_boolean.S
+++ b/runtime/interpreter/mterp/x86_64/op_sget_boolean.S
@@ -1 +1,2 @@
-%include "x86_64/op_sget.S" {"helper":"MterpSGetU8"}
+%def op_sget_boolean():
+%  op_sget(helper="MterpSGetU8")
diff --git a/runtime/interpreter/mterp/x86_64/op_sget_byte.S b/runtime/interpreter/mterp/x86_64/op_sget_byte.S
index 4602f7da5357415660d35b3cd2009d844dba160c..37c6879cd4b02e1fe323434a8f0e490352d4d391 100644
--- a/runtime/interpreter/mterp/x86_64/op_sget_byte.S
+++ b/runtime/interpreter/mterp/x86_64/op_sget_byte.S
@@ -1 +1,2 @@
-%include "x86_64/op_sget.S" {"helper":"MterpSGetI8"}
+%def op_sget_byte():
+%  op_sget(helper="MterpSGetI8")
diff --git a/runtime/interpreter/mterp/x86_64/op_sget_char.S b/runtime/interpreter/mterp/x86_64/op_sget_char.S
index a094a542de6beb354f6c20833fae6632541049b9..003bcd16833da0b4c77b8ef60e71ee9bbb01e8da 100644
--- a/runtime/interpreter/mterp/x86_64/op_sget_char.S
+++ b/runtime/interpreter/mterp/x86_64/op_sget_char.S
@@ -1 +1,2 @@
-%include "x86_64/op_sget.S" {"helper":"MterpSGetU16"}
+%def op_sget_char():
+%  op_sget(helper="MterpSGetU16")
diff --git a/runtime/interpreter/mterp/x86_64/op_sget_object.S b/runtime/interpreter/mterp/x86_64/op_sget_object.S
index 94597b187cc8c70138d764e4c4218cbcb0786e47..7cf3597f44f59b999d828d0749f53401e98cfee6 100644
--- a/runtime/interpreter/mterp/x86_64/op_sget_object.S
+++ b/runtime/interpreter/mterp/x86_64/op_sget_object.S
@@ -1 +1,2 @@
-%include "x86_64/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"}
+%def op_sget_object():
+%  op_sget(is_object="1", helper="MterpSGetObj")
diff --git a/runtime/interpreter/mterp/x86_64/op_sget_short.S b/runtime/interpreter/mterp/x86_64/op_sget_short.S
index dee5c247b9818a78c2cff82584c07023b841badc..afacb578d90caf9455c969edfe13663d0927cb03 100644
--- a/runtime/interpreter/mterp/x86_64/op_sget_short.S
+++ b/runtime/interpreter/mterp/x86_64/op_sget_short.S
@@ -1 +1,2 @@
-%include "x86_64/op_sget.S" {"helper":"MterpSGetI16"}
+%def op_sget_short():
+%  op_sget(helper="MterpSGetI16")
diff --git a/runtime/interpreter/mterp/x86_64/op_sget_wide.S b/runtime/interpreter/mterp/x86_64/op_sget_wide.S
index c53c0773a5f718580c9cf6e4059d503e02ee85df..fff2be6945510278d990141764285ab694e302ed 100644
--- a/runtime/interpreter/mterp/x86_64/op_sget_wide.S
+++ b/runtime/interpreter/mterp/x86_64/op_sget_wide.S
@@ -1 +1,2 @@
-%include "x86_64/op_sget.S" {"helper":"MterpSGetU64"}
+%def op_sget_wide():
+%  op_sget(helper="MterpSGetU64")
diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int.S b/runtime/interpreter/mterp/x86_64/op_shl_int.S
index fa1edb7555f01219fbb8b1523f2b7ebe1d261f68..a98b25612097d5113d7a62462811cd3d50bc85a7 100644
--- a/runtime/interpreter/mterp/x86_64/op_shl_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_shl_int.S
@@ -1 +1,2 @@
-%include "x86_64/binop1.S" {"instr":"sall    %cl, %eax"}
+%def op_shl_int():
+%  binop1(instr="sall    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S
index dd962792c9f0b71c785905bbd1ece29a054a09c8..987c7d1e2875cb7e52d3ed50f32b36bea4dcf584 100644
--- a/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/shop2addr.S" {"instr":"sall    %cl, %eax"}
+%def op_shl_int_2addr():
+%  shop2addr(instr="sall    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S
index 39b23ae1fb4e531c7cd377e973271831e962aa4b..ee1a15e69698074fa6977398655337909b229060 100644
--- a/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S
+++ b/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit8.S" {"instr":"sall    %cl, %eax"}
+%def op_shl_int_lit8():
+%  binopLit8(instr="sall    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_shl_long.S b/runtime/interpreter/mterp/x86_64/op_shl_long.S
index fdc7cb64de5c6a5d16176ac2d261ffef2c5ec1cc..c288b3635276a2aa982d28ce4dfd969d3518e0bb 100644
--- a/runtime/interpreter/mterp/x86_64/op_shl_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_shl_long.S
@@ -1 +1,2 @@
-%include "x86_64/binop1.S" {"instr":"salq    %cl, %rax","wide":"1"}
+%def op_shl_long():
+%  binop1(instr="salq    %cl, %rax", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S
index 546633f7d591219d9c3b63e22ff6811b8e45f121..820e703975e4922a13b89e7cf2aa76f77d44a9c2 100644
--- a/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/shop2addr.S" {"instr":"salq    %cl, %rax","wide":"1"}
+%def op_shl_long_2addr():
+%  shop2addr(instr="salq    %cl, %rax", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int.S b/runtime/interpreter/mterp/x86_64/op_shr_int.S
index fc289f4638c9c352eed0180ed4d7386ad0b6726e..4d4d79cc09a580384be816e42014f7dcd65f086d 100644
--- a/runtime/interpreter/mterp/x86_64/op_shr_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_shr_int.S
@@ -1 +1,2 @@
-%include "x86_64/binop1.S" {"instr":"sarl    %cl, %eax"}
+%def op_shr_int():
+%  binop1(instr="sarl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S
index 0e5bca7057e800f24a6c55c02d35dd41a3234623..8e4b055e157771df5bb4591534c54001c486fb32 100644
--- a/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/shop2addr.S" {"instr":"sarl    %cl, %eax"}
+%def op_shr_int_2addr():
+%  shop2addr(instr="sarl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S
index 3cc930756979cb562683e0c10a14374ad3151b79..a7acf5f384edb60ed25e989c11c993a43703b806 100644
--- a/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S
+++ b/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit8.S" {"instr":"sarl    %cl, %eax"}
+%def op_shr_int_lit8():
+%  binopLit8(instr="sarl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_shr_long.S b/runtime/interpreter/mterp/x86_64/op_shr_long.S
index 25028d3560f4c617eb047a138b12e9a3959a7e39..ed3e504a5538405f4ad71e192f3d88f2cd49cee7 100644
--- a/runtime/interpreter/mterp/x86_64/op_shr_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_shr_long.S
@@ -1 +1,2 @@
-%include "x86_64/binop1.S" {"instr":"sarq    %cl, %rax","wide":"1"}
+%def op_shr_long():
+%  binop1(instr="sarq    %cl, %rax", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S
index 373841322dfdeca26abb79ef81bd667e8ea30653..be6898d5a67f6b8579a7d22789ad32fd61e7b2a2 100644
--- a/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/shop2addr.S" {"instr":"sarq    %cl, %rax","wide":"1"}
+%def op_shr_long_2addr():
+%  shop2addr(instr="sarq    %cl, %rax", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_sparse_switch.S b/runtime/interpreter/mterp/x86_64/op_sparse_switch.S
index 0eaa5148135db6d92cddda70bf7c87380795c262..b74d7da81633f307dbf7c07ffaada2d14f131ec3 100644
--- a/runtime/interpreter/mterp/x86_64/op_sparse_switch.S
+++ b/runtime/interpreter/mterp/x86_64/op_sparse_switch.S
@@ -1 +1,2 @@
-%include "x86_64/op_packed_switch.S" { "func":"MterpDoSparseSwitch" }
+%def op_sparse_switch():
+%  op_packed_switch(func="MterpDoSparseSwitch")
diff --git a/runtime/interpreter/mterp/x86_64/op_sput.S b/runtime/interpreter/mterp/x86_64/op_sput.S
index 7dd24985ffd529e425991ea4caf095fcedbec280..cbd6ee96d345758221edb4c7f71dd2dda57ac8f0 100644
--- a/runtime/interpreter/mterp/x86_64/op_sput.S
+++ b/runtime/interpreter/mterp/x86_64/op_sput.S
@@ -1,2 +1,2 @@
-%default { "is_object":"0", "helper":"MterpSPutU32"}
-%include "x86_64/field.S" { }
+%def op_sput(is_object="0", helper="MterpSPutU32"):
+%  field(helper=helper)
diff --git a/runtime/interpreter/mterp/x86_64/op_sput_boolean.S b/runtime/interpreter/mterp/x86_64/op_sput_boolean.S
index ea9acbfdc72fce142960cad7cce1b4c596465a55..36fba8448b478323ce47a26f2a4d79accbf9964d 100644
--- a/runtime/interpreter/mterp/x86_64/op_sput_boolean.S
+++ b/runtime/interpreter/mterp/x86_64/op_sput_boolean.S
@@ -1 +1,2 @@
-%include "x86_64/op_sput.S" {"helper":"MterpSPutU8"}
+%def op_sput_boolean():
+%  op_sput(helper="MterpSPutU8")
diff --git a/runtime/interpreter/mterp/x86_64/op_sput_byte.S b/runtime/interpreter/mterp/x86_64/op_sput_byte.S
index 62c9e205a1437a7fd4928bd5eb1b9e49e047b7d8..84ad4a0ff86ccfcd1159672dac902ee99cfc37d9 100644
--- a/runtime/interpreter/mterp/x86_64/op_sput_byte.S
+++ b/runtime/interpreter/mterp/x86_64/op_sput_byte.S
@@ -1 +1,2 @@
-%include "x86_64/op_sput.S" {"helper":"MterpSPutI8"}
+%def op_sput_byte():
+%  op_sput(helper="MterpSPutI8")
diff --git a/runtime/interpreter/mterp/x86_64/op_sput_char.S b/runtime/interpreter/mterp/x86_64/op_sput_char.S
index ab0196e027169a5a4bb347843557e002ca614b33..9b8eeba578f555750ab9497c8fc21ce4a52e8b89 100644
--- a/runtime/interpreter/mterp/x86_64/op_sput_char.S
+++ b/runtime/interpreter/mterp/x86_64/op_sput_char.S
@@ -1 +1,2 @@
-%include "x86_64/op_sput.S" {"helper":"MterpSPutU16"}
+%def op_sput_char():
+%  op_sput(helper="MterpSPutU16")
diff --git a/runtime/interpreter/mterp/x86_64/op_sput_object.S b/runtime/interpreter/mterp/x86_64/op_sput_object.S
index c2bd07bcc89c2ba012e693e6ea366757f45699da..081360c40fb12c03e3a48c24a3677ee55a609758 100644
--- a/runtime/interpreter/mterp/x86_64/op_sput_object.S
+++ b/runtime/interpreter/mterp/x86_64/op_sput_object.S
@@ -1 +1,2 @@
-%include "x86_64/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"}
+%def op_sput_object():
+%  op_sput(is_object="1", helper="MterpSPutObj")
diff --git a/runtime/interpreter/mterp/x86_64/op_sput_short.S b/runtime/interpreter/mterp/x86_64/op_sput_short.S
index f73a3fc69ee39d50091171921b7dee579990c6c4..ee16513486189f1a65fe9922285fe9ae08606b97 100644
--- a/runtime/interpreter/mterp/x86_64/op_sput_short.S
+++ b/runtime/interpreter/mterp/x86_64/op_sput_short.S
@@ -1 +1,2 @@
-%include "x86_64/op_sput.S" {"helper":"MterpSPutI16"}
+%def op_sput_short():
+%  op_sput(helper="MterpSPutI16")
diff --git a/runtime/interpreter/mterp/x86_64/op_sput_wide.S b/runtime/interpreter/mterp/x86_64/op_sput_wide.S
index 7e77072dce8362ef207e89a3d0ac808c170c0f35..44c1a188edf6bb3cf29011f1b361701ae71aaf9c 100644
--- a/runtime/interpreter/mterp/x86_64/op_sput_wide.S
+++ b/runtime/interpreter/mterp/x86_64/op_sput_wide.S
@@ -1 +1,2 @@
-%include "x86_64/op_sput.S" {"helper":"MterpSPutU64"}
+%def op_sput_wide():
+%  op_sput(helper="MterpSPutU64")
diff --git a/runtime/interpreter/mterp/x86_64/op_sub_double.S b/runtime/interpreter/mterp/x86_64/op_sub_double.S
index 952667e831e0235f73ef71afcb943be3546d8276..64a28c376be4998a49728c396ed4b6357c1427ca 100644
--- a/runtime/interpreter/mterp/x86_64/op_sub_double.S
+++ b/runtime/interpreter/mterp/x86_64/op_sub_double.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop.S" {"instr":"subs","suff":"d"}
+%def op_sub_double():
+%  sseBinop(instr="subs", suff="d")
diff --git a/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S
index 0bd5dbb8ff0543d2ad8b469ca70bcfa561afea45..753074bd375cb81e3866d4d7d729c156462a6bce 100644
--- a/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop2Addr.S" {"instr":"subs","suff":"d"}
+%def op_sub_double_2addr():
+%  sseBinop2Addr(instr="subs", suff="d")
diff --git a/runtime/interpreter/mterp/x86_64/op_sub_float.S b/runtime/interpreter/mterp/x86_64/op_sub_float.S
index ea0ae14f5b1fb3b2b44d76351d12f9f424717980..1a1966dba26a69764d9e05d71e911b58706fcb63 100644
--- a/runtime/interpreter/mterp/x86_64/op_sub_float.S
+++ b/runtime/interpreter/mterp/x86_64/op_sub_float.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop.S" {"instr":"subs","suff":"s"}
+%def op_sub_float():
+%  sseBinop(instr="subs", suff="s")
diff --git a/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S
index 9dd17805c809b11f33f555534191939e3a3413c3..9557907bd260028f75695c381eca036287c2c187 100644
--- a/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/sseBinop2Addr.S" {"instr":"subs","suff":"s"}
+%def op_sub_float_2addr():
+%  sseBinop2Addr(instr="subs", suff="s")
diff --git a/runtime/interpreter/mterp/x86_64/op_sub_int.S b/runtime/interpreter/mterp/x86_64/op_sub_int.S
index 560394f43f0d9b020c5238510db4e74d87e67cf6..ecab19d72b48a32e69c58bd96169353e63c19bfa 100644
--- a/runtime/interpreter/mterp/x86_64/op_sub_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_sub_int.S
@@ -1 +1,2 @@
-%include "x86_64/binop.S" {"instr":"subl    (rFP,%rcx,4), %eax"}
+%def op_sub_int():
+%  binop(instr="subl    (rFP,%rcx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S
index 6f50f78f41465da7a0ff4da814db8c1f6bf6c198..61fc7a7b150cd001f49af84f1f87c5a3c77bfabc 100644
--- a/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/binop2addr.S" {"instr":"subl    %eax, (rFP,%rcx,4)"}
+%def op_sub_int_2addr():
+%  binop2addr(instr="subl    %eax, (rFP,%rcx,4)")
diff --git a/runtime/interpreter/mterp/x86_64/op_sub_long.S b/runtime/interpreter/mterp/x86_64/op_sub_long.S
index 7fa54e7a11662b549eff85839385e2e3f7e88ef9..9c38f889518d5b440afa8570a6edbcaf6fdcc2cd 100644
--- a/runtime/interpreter/mterp/x86_64/op_sub_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_sub_long.S
@@ -1 +1,2 @@
-%include "x86_64/binopWide.S" {"instr":"subq    (rFP,%rcx,4), %rax"}
+%def op_sub_long():
+%  binopWide(instr="subq    (rFP,%rcx,4), %rax")
diff --git a/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S
index c18be10919af0f7349a5251b609ed329aeefdb0d..ab31aaff8fefb4616089535859aa77ab2cecae28 100644
--- a/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/binopWide2addr.S" {"instr":"subq    %rax, (rFP,%rcx,4)"}
+%def op_sub_long_2addr():
+%  binopWide2addr(instr="subq    %rax, (rFP,%rcx,4)")
diff --git a/runtime/interpreter/mterp/x86_64/op_throw.S b/runtime/interpreter/mterp/x86_64/op_throw.S
index 8095c25b0825b7140005d81d97a0510a7fabb42c..09fc1ec6b87cf1c5c396782cb13b25a32d747c2c 100644
--- a/runtime/interpreter/mterp/x86_64/op_throw.S
+++ b/runtime/interpreter/mterp/x86_64/op_throw.S
@@ -1,3 +1,4 @@
+%def op_throw():
 /*
  * Throw an exception object in the current thread.
  */
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_3e.S b/runtime/interpreter/mterp/x86_64/op_unused_3e.S
index 280615f08b124bd9c513704501c49895504edcd0..d889f1a5fb4be366ce5101882ae40577a9b0b90b 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_3e.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_3e.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_3e():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_3f.S b/runtime/interpreter/mterp/x86_64/op_unused_3f.S
index 280615f08b124bd9c513704501c49895504edcd0..b3ebcfaeaa402ba263610b3f305daf92cc23bebb 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_3f.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_3f.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_3f():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_40.S b/runtime/interpreter/mterp/x86_64/op_unused_40.S
index 280615f08b124bd9c513704501c49895504edcd0..7920fb350f2f93b310d33ec19166b6b8445bb0eb 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_40.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_40.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_40():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_41.S b/runtime/interpreter/mterp/x86_64/op_unused_41.S
index 280615f08b124bd9c513704501c49895504edcd0..5ed03b85065e78c670f3d26c62b6c56f58338d44 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_41.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_41.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_41():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_42.S b/runtime/interpreter/mterp/x86_64/op_unused_42.S
index 280615f08b124bd9c513704501c49895504edcd0..ac32521add543fb2f858aa858af6c3d5594f187e 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_42.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_42.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_42():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_43.S b/runtime/interpreter/mterp/x86_64/op_unused_43.S
index 280615f08b124bd9c513704501c49895504edcd0..33e2aa10f8bec8407ff8090cfd81dda49b2a19b8 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_43.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_43.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_43():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_79.S b/runtime/interpreter/mterp/x86_64/op_unused_79.S
index 280615f08b124bd9c513704501c49895504edcd0..3c6dafc7898855a1034ff93b17bed71a07df1e51 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_79.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_79.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_79():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_7a.S b/runtime/interpreter/mterp/x86_64/op_unused_7a.S
index 280615f08b124bd9c513704501c49895504edcd0..9c03cd55355a41369dc85dbea7e07e7bd8e96383 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_7a.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_7a.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_7a():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f3.S b/runtime/interpreter/mterp/x86_64/op_unused_f3.S
index 280615f08b124bd9c513704501c49895504edcd0..ab10b78be2a0b681652d52185cf7c39d3403a41e 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_f3.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_f3.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_f3():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f4.S b/runtime/interpreter/mterp/x86_64/op_unused_f4.S
index 280615f08b124bd9c513704501c49895504edcd0..09229d6d99f58a24b923c56b2937662a10e16de6 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_f4.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_f4.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_f4():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f5.S b/runtime/interpreter/mterp/x86_64/op_unused_f5.S
index 280615f08b124bd9c513704501c49895504edcd0..0d6149b5fd6eeb0221067adb660d453080ba1fd2 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_f5.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_f5.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_f5():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f6.S b/runtime/interpreter/mterp/x86_64/op_unused_f6.S
index 280615f08b124bd9c513704501c49895504edcd0..117b03de6d321ace7f917fe69b79b9f182081e11 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_f6.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_f6.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_f6():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f7.S b/runtime/interpreter/mterp/x86_64/op_unused_f7.S
index 280615f08b124bd9c513704501c49895504edcd0..4e3a0f3c9a6eef078506555805a72056272abfc1 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_f7.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_f7.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_f7():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f8.S b/runtime/interpreter/mterp/x86_64/op_unused_f8.S
index 280615f08b124bd9c513704501c49895504edcd0..d1220752d7b5b191c0712bf975e90ac7777e4303 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_f8.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_f8.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_f8():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f9.S b/runtime/interpreter/mterp/x86_64/op_unused_f9.S
index 280615f08b124bd9c513704501c49895504edcd0..7d09a0ebcfce77f4a1bd8b19865ac5d782e382dd 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_f9.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_f9.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_f9():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_fc.S b/runtime/interpreter/mterp/x86_64/op_unused_fc.S
index 280615f08b124bd9c513704501c49895504edcd0..06978191ebbcceb51b9820b3e650a0baf767a507 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_fc.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_fc.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_fc():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_unused_fd.S b/runtime/interpreter/mterp/x86_64/op_unused_fd.S
index 280615f08b124bd9c513704501c49895504edcd0..4bc2b4bdb6516467406cb88476e1d993a3f0c749 100644
--- a/runtime/interpreter/mterp/x86_64/op_unused_fd.S
+++ b/runtime/interpreter/mterp/x86_64/op_unused_fd.S
@@ -1 +1,2 @@
-%include "x86_64/unused.S"
+%def op_unused_fd():
+%  unused()
diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int.S b/runtime/interpreter/mterp/x86_64/op_ushr_int.S
index dd91086371e241d76d6a7957af630ee348211b84..38c8782ca9b132a3ae910d37db37ad2565a4d170 100644
--- a/runtime/interpreter/mterp/x86_64/op_ushr_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_ushr_int.S
@@ -1 +1,2 @@
-%include "x86_64/binop1.S" {"instr":"shrl    %cl, %eax"}
+%def op_ushr_int():
+%  binop1(instr="shrl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S
index d38aedd234bb0da0300b60c4f183fc39cb373bad..f1da71a47af2dd3d132afc76f399a6ab14542ad8 100644
--- a/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/shop2addr.S" {"instr":"shrl    %cl, %eax"}
+%def op_ushr_int_2addr():
+%  shop2addr(instr="shrl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S
index f7ff8abc869bc0a6721da5ef0e87b15ca92c582c..4298d36c3d223dc938e55d5899e91d49064a553a 100644
--- a/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S
+++ b/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit8.S" {"instr":"shrl    %cl, %eax"}
+%def op_ushr_int_lit8():
+%  binopLit8(instr="shrl    %cl, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_long.S b/runtime/interpreter/mterp/x86_64/op_ushr_long.S
index 7c6daca05d4f92a2b1a49b6b31b1b002f6ff65e2..a0b4daf14da3e4a048f02432703b18266c5b5b77 100644
--- a/runtime/interpreter/mterp/x86_64/op_ushr_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_ushr_long.S
@@ -1 +1,2 @@
-%include "x86_64/binop1.S" {"instr":"shrq    %cl, %rax","wide":"1"}
+%def op_ushr_long():
+%  binop1(instr="shrq    %cl, %rax", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S
index cd6a22c6fa398d2f8f7e11a8a0509e73dd2df111..2213cf386576bb95e989945dfd8803f082ba2052 100644
--- a/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/shop2addr.S" {"instr":"shrq    %cl, %rax","wide":"1"}
+%def op_ushr_long_2addr():
+%  shop2addr(instr="shrq    %cl, %rax", wide="1")
diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int.S b/runtime/interpreter/mterp/x86_64/op_xor_int.S
index b295d74de0cc53821f02f187f3c9b832b6b20d63..5dc26037350416f4e1d68b501ff17d988ecaab0b 100644
--- a/runtime/interpreter/mterp/x86_64/op_xor_int.S
+++ b/runtime/interpreter/mterp/x86_64/op_xor_int.S
@@ -1 +1,2 @@
-%include "x86_64/binop.S" {"instr":"xorl    (rFP,%rcx,4), %eax"}
+%def op_xor_int():
+%  binop(instr="xorl    (rFP,%rcx,4), %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S
index 879bfc05dc87b24ee77d81865c867ec3272a45ad..2c847028c514ebd79ab3e051f0647ff66d48de42 100644
--- a/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/binop2addr.S" {"instr":"xorl    %eax, (rFP,%rcx,4)"}
+%def op_xor_int_2addr():
+%  binop2addr(instr="xorl    %eax, (rFP,%rcx,4)")
diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S
index 5d375a1cf69ce01aed1f823e27bd37d0a3b75b04..f5dc00e074397b774b0fe2b03ac7795873f15bd1 100644
--- a/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S
+++ b/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit16.S" {"instr":"xorl    %ecx, %eax"}
+%def op_xor_int_lit16():
+%  binopLit16(instr="xorl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S
index 54cce9c18e36677f1dadd87d6538269c775274c8..98a1a432dd16b3e07fc2dc844659d80892a646e3 100644
--- a/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S
+++ b/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S
@@ -1 +1,2 @@
-%include "x86_64/binopLit8.S" {"instr":"xorl    %ecx, %eax"}
+%def op_xor_int_lit8():
+%  binopLit8(instr="xorl    %ecx, %eax")
diff --git a/runtime/interpreter/mterp/x86_64/op_xor_long.S b/runtime/interpreter/mterp/x86_64/op_xor_long.S
index 52b44e29c113337b0522f92f536ce5d35c7ce5d4..1c267930d495708a3b30fc81b1f20ba075d92b97 100644
--- a/runtime/interpreter/mterp/x86_64/op_xor_long.S
+++ b/runtime/interpreter/mterp/x86_64/op_xor_long.S
@@ -1 +1,2 @@
-%include "x86_64/binopWide.S" {"instr":"xorq    (rFP,%rcx,4), %rax"}
+%def op_xor_long():
+%  binopWide(instr="xorq    (rFP,%rcx,4), %rax")
diff --git a/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S
index d75c4ba6ce95e9024edfcbe8e82f8acc9719131f..c6496517f773753ff1d2a530ca67de3cbe00b76f 100644
--- a/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S
+++ b/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S
@@ -1 +1,2 @@
-%include "x86_64/binopWide2addr.S" {"instr":"xorq    %rax, (rFP,%rcx,4)"}
+%def op_xor_long_2addr():
+%  binopWide2addr(instr="xorq    %rax, (rFP,%rcx,4)")
diff --git a/runtime/interpreter/mterp/x86_64/shop2addr.S b/runtime/interpreter/mterp/x86_64/shop2addr.S
index 6b06d002fc99c3e1cc441507185ad5934b0f9aaa..d0d838b8809f5ef0b399fa7fb1e4321920be07b0 100644
--- a/runtime/interpreter/mterp/x86_64/shop2addr.S
+++ b/runtime/interpreter/mterp/x86_64/shop2addr.S
@@ -1,4 +1,4 @@
-%default {"wide":"0"}
+%def shop2addr(wide="0", instr=""):
 /*
  * Generic 32-bit "shift/2addr" operation.
  */
diff --git a/runtime/interpreter/mterp/x86_64/sseBinop.S b/runtime/interpreter/mterp/x86_64/sseBinop.S
index 09d3364de76631a7c8920436e4a1c69580cc794a..638ea8ef56c2fee615eab8da7ec60887f8f1dec3 100644
--- a/runtime/interpreter/mterp/x86_64/sseBinop.S
+++ b/runtime/interpreter/mterp/x86_64/sseBinop.S
@@ -1,4 +1,4 @@
-%default {"instr":"","suff":""}
+%def sseBinop(instr="", suff=""):
     movzbq  2(rPC), %rcx                    # ecx <- BB
     movzbq  3(rPC), %rax                    # eax <- CC
     movs${suff}   VREG_ADDRESS(%rcx), %xmm0       # %xmm0 <- 1st src
diff --git a/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S b/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S
index 084166b95d1dde1ed4e31eb0005bda49aa6b465d..1292a36de315f886d962f082b1565fe6396988bb 100644
--- a/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S
+++ b/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S
@@ -1,4 +1,4 @@
-%default {"instr":"","suff":""}
+%def sseBinop2Addr(instr="", suff=""):
     movl    rINST, %ecx                     # ecx <- A+
     andl    $$0xf, %ecx                     # ecx <- A
     movs${suff} VREG_ADDRESS(%rcx), %xmm0        # %xmm0 <- 1st src
diff --git a/runtime/interpreter/mterp/x86_64/unop.S b/runtime/interpreter/mterp/x86_64/unop.S
index 1777123f3603a51dea8635c43b3e435618ae4672..1dd12a31a176b6fd67a93a99eceddc2576c79f08 100644
--- a/runtime/interpreter/mterp/x86_64/unop.S
+++ b/runtime/interpreter/mterp/x86_64/unop.S
@@ -1,4 +1,4 @@
-%default {"preinstr":"", "instr":"", "wide":"0"}
+%def unop(preinstr="", instr="", wide="0"):
 /*
  * Generic 32/64-bit unary operation.  Provide an "instr" line that
  * specifies an instruction that performs "result = op eax".
diff --git a/runtime/interpreter/mterp/x86_64/unused.S b/runtime/interpreter/mterp/x86_64/unused.S
index c95ef947d3c4187addee86d70f601836922c05c4..ef35b6e73f3cadbecbcec84a9dba917e80f4adc8 100644
--- a/runtime/interpreter/mterp/x86_64/unused.S
+++ b/runtime/interpreter/mterp/x86_64/unused.S
@@ -1,3 +1,4 @@
+%def unused():
 /*
  * Bail to reference interpreter to throw.
  */
diff --git a/runtime/interpreter/mterp/x86_64/zcmp.S b/runtime/interpreter/mterp/x86_64/zcmp.S
index fb8ae6af6ef554835f09aa3a29398490a320c2d9..e794fb0e5b13e0caa25c97b7576a3d19009c6ca5 100644
--- a/runtime/interpreter/mterp/x86_64/zcmp.S
+++ b/runtime/interpreter/mterp/x86_64/zcmp.S
@@ -1,3 +1,4 @@
+%def zcmp(revcmp=""):
 /*
  * Generic one-operand compare-and-branch operation.  Provide a "revcmp"
  * fragment that specifies the *reverse* comparison to perform, e.g.